diff options
Diffstat (limited to 'drivers/video/samsung_duallcd/dsim2')
6 files changed, 2475 insertions, 0 deletions
diff --git a/drivers/video/samsung_duallcd/dsim2/Makefile b/drivers/video/samsung_duallcd/dsim2/Makefile new file mode 100644 index 0000000..984452d --- /dev/null +++ b/drivers/video/samsung_duallcd/dsim2/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for MIPI-DSI driver. +# +obj-$(CONFIG_S5P_MIPI_DSI2) += s5p_mipi_dsi.o s5p_mipi_dsi_common.o\ + s5p_mipi_dsi_lowlevel.o diff --git a/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi.c b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi.c new file mode 100644 index 0000000..29faa03 --- /dev/null +++ b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi.c @@ -0,0 +1,803 @@ +/* linux/drivers/video/s5p_mipi_dsi.c + * + * Samsung SoC MIPI-DSIM driver. + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd + * + * InKi Dae, <inki.dae@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/mutex.h> +#include <linux/wait.h> +#include <linux/fs.h> +#include <linux/mm.h> +#include <linux/fb.h> +#include <linux/ctype.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/memory.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kthread.h> +#include <linux/notifier.h> +#include <linux/regulator/consumer.h> +#include <linux/pm_runtime.h> + +#include <plat/fb.h> +#include <plat/mipi_dsim2.h> + +#include "s5p_mipi_dsi_common.h" +#include "s5p_mipi_dsi_lowlevel.h" + +#define master_to_driver(a) (a->dsim_lcd_drv) +#define master_to_device(a) (a->dsim_lcd_dev) +#define dev_to_dsim(a) platform_get_drvdata(to_platform_device(a)) + +struct mipi_dsim_ddi { + int bus_id; + struct list_head list; + struct mipi_dsim_lcd_device *dsim_lcd_dev; + struct mipi_dsim_lcd_driver *dsim_lcd_drv; +}; + +static LIST_HEAD(dsim_ddi_list); + +static DEFINE_MUTEX(mipi_dsim_lock); + +static struct s5p_platform_mipi_dsim *to_dsim_plat(struct platform_device *pdev) +{ + return (struct s5p_platform_mipi_dsim *)pdev->dev.platform_data; +} + +static int s5p_mipi_regulator_enable(struct mipi_dsim_device *dsim) +{ + int ret = 0; + + mutex_lock(&dsim->lock); + if (dsim->reg_vdd10) { + ret = regulator_enable(dsim->reg_vdd10); + if (ret < 0) { + dev_err(dsim->dev, "failed to enable regulator.\n"); + goto err_vdd10; + } + } + if (dsim->reg_vdd18) { + ret = regulator_enable(dsim->reg_vdd18); + if (ret < 0) { + dev_err(dsim->dev, "failed to enable regulator.\n"); + goto err_vdd18; + } + } + + mutex_unlock(&dsim->lock); + return ret; + +err_vdd18: + ret = regulator_disable(dsim->reg_vdd10); + if (ret < 0) + dev_err(dsim->dev, "failed to disable regulator.\n"); +err_vdd10: + mutex_unlock(&dsim->lock); + return ret; +} + +static int s5p_mipi_regulator_disable(struct mipi_dsim_device *dsim) +{ + int ret = 0; + + mutex_lock(&dsim->lock); + if (dsim->reg_vdd18) { + ret = regulator_disable(dsim->reg_vdd18); + if (ret < 0) { + dev_err(dsim->dev, "failed to disable regulator.\n"); + goto err_vdd18; + } + } + + if (dsim->reg_vdd10) { + ret = regulator_disable(dsim->reg_vdd10); + if (ret < 0) { + dev_err(dsim->dev, "failed to disable regulator.\n"); + goto err_vdd10; + } + } + + mutex_unlock(&dsim->lock); + return ret; + +err_vdd10: + ret = regulator_enable(dsim->reg_vdd18); + if (ret < 0) + dev_err(dsim->dev, "failed to enable regulator.\n"); +err_vdd18: + mutex_unlock(&dsim->lock); + return ret; +} + +/* update all register settings to MIPI DSI controller. */ +static void s5p_mipi_update_cfg(struct mipi_dsim_device *dsim) +{ + /* + * data from Display controller(FIMD) is not transferred in video mode + * but in case of command mode, all settings is not updated to + * registers. + */ + s5p_mipi_dsi_stand_by(dsim, 0); + + s5p_mipi_dsi_init_dsim(dsim); + s5p_mipi_dsi_init_link(dsim); + + s5p_mipi_dsi_set_hs_enable(dsim); + + /* set display timing. */ + s5p_mipi_dsi_set_display_mode(dsim, dsim->dsim_config); + + s5p_mipi_dsi_init_interrupt(dsim); + + /* + * data from Display controller(FIMD) is transferred in video mode + * but in case of command mode, all settigs is updated to registers. + */ + s5p_mipi_dsi_stand_by(dsim, 1); +} + +static int s5p_mipi_dsi_early_blank_mode(struct mipi_dsim_device *dsim, + int power) +{ + switch (power) { + case FB_BLANK_POWERDOWN: + if (!dsim->suspended) + pm_runtime_put_sync(dsim->dev); + + atomic_set(&dsim->early_blank_used_t, 1); + break; + default: + break; + } + + return 0; +} + +static int s5p_mipi_dsi_blank_mode(struct mipi_dsim_device *dsim, int power) +{ + switch (power) { + case FB_BLANK_UNBLANK: + if (dsim->suspended) + pm_runtime_get_sync(dsim->dev); + + atomic_set(&dsim->early_blank_used_t, 0); + break; + case FB_BLANK_NORMAL: + /* TODO. */ + break; + case FB_BLANK_POWERDOWN: + /* + * if this function is called after early fb blank event, + * ignor it. + */ + if (atomic_read(&dsim->early_blank_used_t)) { + atomic_set(&dsim->early_blank_used_t, 0); + break; + } + + if (!dsim->suspended) + pm_runtime_put_sync(dsim->dev); + default: + break; + } + + return 0; +} + +int s5p_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev) +{ + struct mipi_dsim_ddi *dsim_ddi; + + if (!lcd_dev) { + printk(KERN_ERR "mipi_dsim_lcd_device is NULL.\n"); + return -EFAULT; + } + + if (!lcd_dev->name) { + printk(KERN_ERR "dsim_lcd_device name is NULL.\n"); + return -EFAULT; + } + + dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL); + if (!dsim_ddi) { + printk(KERN_ERR "failed to allocate dsim_ddi object.\n"); + return -EFAULT; + } + + dsim_ddi->dsim_lcd_dev = lcd_dev; + + mutex_lock(&mipi_dsim_lock); + list_add_tail(&dsim_ddi->list, &dsim_ddi_list); + mutex_unlock(&mipi_dsim_lock); + + return 0; +} + +struct mipi_dsim_ddi + *s5p_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv) +{ + struct mipi_dsim_ddi *dsim_ddi; + struct mipi_dsim_lcd_device *lcd_dev; + + mutex_lock(&mipi_dsim_lock); + + list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) { + if (!dsim_ddi) + goto out; + + lcd_dev = dsim_ddi->dsim_lcd_dev; + if (!lcd_dev) + continue; + + if (lcd_drv->id >= 0) { + if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0 && + lcd_drv->id == lcd_dev->id) { + /** + * bus_id would be used to identify + * connected bus. + */ + dsim_ddi->bus_id = lcd_dev->bus_id; + mutex_unlock(&mipi_dsim_lock); + + return dsim_ddi; + } + } else { + if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0) { + /** + * bus_id would be used to identify + * connected bus. + */ + dsim_ddi->bus_id = lcd_dev->bus_id; + mutex_unlock(&mipi_dsim_lock); + + return dsim_ddi; + } + } + } + +out: + mutex_unlock(&mipi_dsim_lock); + + return NULL; +} + +int s5p_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv) +{ + struct mipi_dsim_ddi *dsim_ddi; + + if (!lcd_drv) { + printk(KERN_ERR "mipi_dsim_lcd_driver is NULL.\n"); + return -EFAULT; + } + + if (!lcd_drv->name) { + printk(KERN_ERR "dsim_lcd_driver name is NULL.\n"); + return -EFAULT; + } + + dsim_ddi = s5p_mipi_dsi_find_lcd_device(lcd_drv); + if (!dsim_ddi) { + printk(KERN_ERR "mipi_dsim_ddi object not found.\n"); + return -EFAULT; + } + + dsim_ddi->dsim_lcd_drv = lcd_drv; + + printk(KERN_INFO "registered panel driver(%s) to mipi-dsi driver.\n", + lcd_drv->name); + + return 0; + +} + +struct mipi_dsim_ddi + *s5p_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim, + const char *name) +{ + struct mipi_dsim_ddi *dsim_ddi; + struct mipi_dsim_lcd_driver *lcd_drv; + struct mipi_dsim_lcd_device *lcd_dev; + int ret; + + mutex_lock(&dsim->lock); + + list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) { + lcd_drv = dsim_ddi->dsim_lcd_drv; + lcd_dev = dsim_ddi->dsim_lcd_dev; + if (!lcd_drv || !lcd_dev || + (dsim->id != dsim_ddi->bus_id)) + continue; + + dev_dbg(dsim->dev, "lcd_drv->id = %d, lcd_dev->id = %d\n", + lcd_drv->id, lcd_dev->id); + dev_dbg(dsim->dev, "lcd_dev->bus_id = %d, dsim->id = %d\n", + lcd_dev->bus_id, dsim->id); + + if ((strcmp(lcd_drv->name, name) == 0)) { + lcd_dev->master = dsim; + + lcd_dev->dev.parent = dsim->dev; + dev_set_name(&lcd_dev->dev, "%s", lcd_drv->name); + + ret = device_register(&lcd_dev->dev); + if (ret < 0) { + dev_err(dsim->dev, + "can't register %s, status %d\n", + dev_name(&lcd_dev->dev), ret); + mutex_unlock(&dsim->lock); + + return NULL; + } + + dsim->dsim_lcd_dev = lcd_dev; + dsim->dsim_lcd_drv = lcd_drv; + + mutex_unlock(&dsim->lock); + + return dsim_ddi; + } + } + + mutex_unlock(&dsim->lock); + + return NULL; +} + +static void s5p_mipi_dsi_set_pms(struct mipi_dsim_device *dsim, unsigned int p, + unsigned int m, unsigned int s, unsigned int freq_band) +{ + s5p_mipi_dsi_set_pll_pms(dsim, p, m, s); + s5p_mipi_dsi_pll_freq_band(dsim, freq_band); + s5p_mipi_dsi_pll_stable_time(dsim, + dsim->dsim_config->pll_stable_time); + dsim->dsim_config->p = p; + dsim->dsim_config->m = m; + dsim->dsim_config->s = s; +} + +/* define MIPI-DSI Master operations. */ +static struct mipi_dsim_master_ops master_ops = { + .cmd_read = s5p_mipi_dsi_rd_data, + .cmd_write = s5p_mipi_dsi_wr_data, + .get_dsim_frame_done = s5p_mipi_dsi_get_frame_done_status, + .clear_dsim_frame_done = s5p_mipi_dsi_clear_frame_done, + .set_early_blank_mode = s5p_mipi_dsi_early_blank_mode, + .set_blank_mode = s5p_mipi_dsi_blank_mode, + .set_pms = s5p_mipi_dsi_set_pms, +}; + +static int s5p_mipi_dsi_notifier(unsigned int val, void *data) +{ + struct mipi_dsim_device *dsim = (struct mipi_dsim_device *)data; + int ret; + + ret = s5p_mipi_regulator_enable(dsim); + if (ret < 0) + return ret; + + ret = clk_enable(dsim->clock); + if (ret < 0) { + dev_err(dsim->dev, "failed to enable clock.\n"); + /* it doesn't need error check. */ + s5p_mipi_regulator_disable(dsim); + return ret; + } + + /* it doesn't need error check. */ + s5p_mipi_dsi_fifo_clear(dsim, val); + + clk_disable(dsim->clock); + return s5p_mipi_regulator_disable(dsim); +} + +static int register_notif_to_fimd(struct mipi_dsim_device *dsim) +{ + return fimd_register_client(s5p_mipi_dsi_notifier, + (void *)dsim); +} + +static int s5p_mipi_dsi_power_on(struct mipi_dsim_device *dsim, bool enable) +{ + struct mipi_dsim_lcd_driver *client_drv = master_to_driver(dsim); + struct mipi_dsim_lcd_device *client_dev = master_to_device(dsim); + struct platform_device *pdev = to_platform_device(dsim->dev); + + if (enable != false && enable != true) + return -EINVAL; + + if (enable) { + int ret; + + if (!dsim->suspended) + return 0; + + /* lcd panel power on. */ + if (client_drv && client_drv->power_on) + client_drv->power_on(client_dev, 1); + + ret = s5p_mipi_regulator_enable(dsim); + if (ret < 0) { + client_drv->power_on(client_dev, 0); + return ret; + } + + ret = clk_enable(dsim->clock); + if (ret < 0) { + dev_err(dsim->dev, "failed to enable clock.\n"); + /* it doesn't need error check. */ + s5p_mipi_regulator_disable(dsim); + client_drv->power_on(client_dev, 0); + return ret; + } + + /* enable MIPI-DSI PHY. */ + if (dsim->pd->phy_enable) + dsim->pd->phy_enable(pdev, true); + + s5p_mipi_update_cfg(dsim); + + /* set lcd panel sequence commands. */ + if (client_drv && client_drv->set_sequence) + client_drv->set_sequence(client_dev); + + dsim->suspended = false; + } else { + if (dsim->suspended) + return 0; + + if (client_drv && client_drv->suspend) + client_drv->suspend(client_dev); + + if (client_drv && client_drv->power_on) + client_drv->power_on(client_dev, 0); + + clk_disable(dsim->clock); + + dsim->suspended = true; + + return s5p_mipi_regulator_disable(dsim); + } + + return 0; +} + +static int s5p_mipi_dsi_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mipi_dsim_device *dsim; + struct mipi_dsim_config *dsim_config; + struct s5p_platform_mipi_dsim *dsim_pd; + struct mipi_dsim_lcd_driver *client_drv; + struct mipi_dsim_ddi *dsim_ddi; + int ret = -EINVAL; + + dsim = kzalloc(sizeof(struct mipi_dsim_device), GFP_KERNEL); + if (!dsim) { + dev_err(&pdev->dev, "failed to allocate dsim object.\n"); + return -EFAULT; + } + + dsim->pd = to_dsim_plat(pdev); + dsim->dev = &pdev->dev; + dsim->id = pdev->id; + + /* get s5p_platform_mipi_dsim. */ + dsim_pd = (struct s5p_platform_mipi_dsim *)dsim->pd; + if (dsim_pd == NULL) { + dev_err(&pdev->dev, "failed to get platform data for dsim.\n"); + ret = -EFAULT; + goto err_free; + } + /* get mipi_dsim_config. */ + dsim_config = dsim_pd->dsim_config; + if (dsim_config == NULL) { + dev_err(&pdev->dev, "failed to get dsim config data.\n"); + ret = -EFAULT; + goto err_free; + } + + dsim->dsim_config = dsim_config; + dsim->master_ops = &master_ops; + + mutex_init(&dsim->lock); + + dsim->reg_vdd10 = regulator_get(&pdev->dev, "VDD10"); + if (IS_ERR(dsim->reg_vdd10)) { + ret = PTR_ERR(dsim->reg_vdd10); + dev_err(&pdev->dev, "failed to get %s regulator (%d)\n", + "VDD10", ret); + dsim->reg_vdd10 = NULL; + } + + dsim->reg_vdd18 = regulator_get(&pdev->dev, "VDD18"); + if (IS_ERR(dsim->reg_vdd18)) { + ret = PTR_ERR(dsim->reg_vdd18); + dev_err(&pdev->dev, "failed to get %s regulator (%d)\n", + "VDD18", ret); + dsim->reg_vdd18 = NULL; + } + dsim->clock = clk_get(&pdev->dev, "dsim0"); + if (IS_ERR(dsim->clock)) { + dev_err(&pdev->dev, "failed to get dsim clock source\n"); + goto err_regulator; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get io memory region\n"); + goto err_put_clk; + } + + dsim->res = request_mem_region(res->start, resource_size(res), + dev_name(&pdev->dev)); + if (!dsim->res) { + dev_err(&pdev->dev, "failed to request io memory region\n"); + ret = -ENOMEM; + goto err_release_res; + } + + dsim->reg_base = ioremap(res->start, resource_size(res)); + if (!dsim->reg_base) { + dev_err(&pdev->dev, "failed to remap io region\n"); + ret = -EFAULT; + goto err_release_mem; + } + + dsim->irq = platform_get_irq(pdev, 0); + if (dsim->irq < 0) { + dev_err(&pdev->dev, "failed to request dsim irq resource\n"); + ret = -EINVAL; + goto err_unmap; + } + + ret = request_irq(dsim->irq, s5p_mipi_dsi_interrupt_handler, + IRQF_SHARED, pdev->name, dsim); + if (ret != 0) { + dev_err(&pdev->dev, "failed to request dsim irq\n"); + ret = -EINVAL; + goto err_unmap; + } + + /* bind lcd ddi matched with panel name. */ + dsim_ddi = s5p_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name); + if (!dsim_ddi) { + dev_err(&pdev->dev, "mipi_dsim_ddi object not found.\n"); + goto err_free_irq; + } + + /* register a callback called by fimd. */ + ret = register_notif_to_fimd(dsim); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register fimd notifier.\n"); + fimd_unregister_client(s5p_mipi_dsi_notifier); + + goto err_free_irq; + } + + init_completion(&dsim_wr_comp); + init_completion(&dsim_rd_comp); + mutex_init(&dsim->lock); + + client_drv = dsim_ddi->dsim_lcd_drv; + + /* initialize mipi-dsi client(lcd panel). */ + if (client_drv && client_drv->probe) + client_drv->probe(dsim_ddi->dsim_lcd_dev); + + platform_set_drvdata(pdev, dsim); + + /* in case that mipi got enabled at bootloader. */ + if (dsim_pd->enabled) { + ret = s5p_mipi_regulator_enable(dsim); + if (ret < 0) + goto err_regulator_enable; + + ret = pm_runtime_set_active(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to active pm runtime.\n"); + goto err_pm_runtime_active; + } + + s5p_mipi_dsi_init_interrupt(dsim); + + if (client_drv && client_drv->check_mtp) + client_drv->check_mtp(dsim_ddi->dsim_lcd_dev); + + /* set lcd panel sequence commands. */ + if (client_drv && client_drv->set_sequence) + client_drv->set_sequence(dsim_ddi->dsim_lcd_dev); + } else { + /* TODO: + * add check_mtp callback function + * if mipi dsim is off on bootloader, it causes kernel panic */ + pm_runtime_set_suspended(&pdev->dev); + dsim->suspended = true; + } + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get pm runtime.\n"); + pm_runtime_disable(&pdev->dev); + goto err_regulator_enable; + } + + dev_info(&pdev->dev, "mipi-dsi driver(%s mode) has been probed.\n", + (dsim_config->e_interface == DSIM_COMMAND) ? + "CPU" : "RGB"); + + return 0; + +err_pm_runtime_active: + /* it doesn't need error check. */ + s5p_mipi_regulator_disable(dsim); + +err_regulator_enable: + if (client_drv && client_drv->remove) + client_drv->remove(dsim_ddi->dsim_lcd_dev); + +err_free_irq: + free_irq(dsim->irq, dsim); + +err_unmap: + iounmap((void __iomem *) dsim->reg_base); + +err_release_mem: + release_mem_region(dsim->res->start, resource_size(dsim->res)); + +err_release_res: + release_resource(dsim->res); + +err_put_clk: + clk_disable(dsim->clock); + clk_put(dsim->clock); + +err_regulator: + regulator_put(dsim->reg_vdd18); + regulator_put(dsim->reg_vdd10); + +err_free: + kfree(dsim); + return ret; +} + +static int __devexit s5p_mipi_dsi_remove(struct platform_device *pdev) +{ + struct mipi_dsim_device *dsim = platform_get_drvdata(pdev); + struct mipi_dsim_ddi *dsim_ddi; + struct mipi_dsim_lcd_driver *dsim_lcd_drv; + + iounmap(dsim->reg_base); + + s5p_mipi_regulator_disable(dsim); + regulator_put(dsim->reg_vdd18); + regulator_put(dsim->reg_vdd10); + + clk_disable(dsim->clock); + clk_put(dsim->clock); + + release_resource(dsim->res); + release_mem_region(dsim->res->start, resource_size(dsim->res)); + + list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) { + if (dsim_ddi) { + if (dsim->id != dsim_ddi->bus_id) + continue; + + dsim_lcd_drv = dsim_ddi->dsim_lcd_drv; + + if (dsim_lcd_drv->remove) + dsim_lcd_drv->remove(dsim_ddi->dsim_lcd_dev); + + list_del(&dsim_ddi->list); + kfree(dsim_ddi); + } + } + + kfree(dsim); + + return 0; +} + +#ifdef CONFIG_PM +static int s5p_mipi_dsi_suspend(struct device *dev) +{ + struct mipi_dsim_device *dsim = dev_to_dsim(dev); + + if (pm_runtime_suspended(dev)) + return 0; + + /* + * do not use pm_runtime_suspend(). if pm_runtime_suspend() is + * called here, an error would be returned by that interface + * because the usage_count of pm runtime is more than 1. + */ + return s5p_mipi_dsi_power_on(dsim, false); +} + +static int s5p_mipi_dsi_resume(struct device *dev) +{ + struct mipi_dsim_device *dsim = dev_to_dsim(dev); + + /* + * if entering to sleep when lcd panel is on, the usage_count + * of pm runtime would still be 1 so in this case, mipi dsi driver + * should be on directly not drawing on pm runtime interface. + */ + if (!pm_runtime_suspended(dev)) + return s5p_mipi_dsi_power_on(dsim, true); + + return 0; +} + +static int s5p_mipi_dsi_runtime_suspend(struct device *dev) +{ + struct mipi_dsim_device *dsim = dev_to_dsim(dev); + + return s5p_mipi_dsi_power_on(dsim, false); +} + +static int s5p_mipi_dsi_runtime_resume(struct device *dev) +{ + struct mipi_dsim_device *dsim = dev_to_dsim(dev); + + return s5p_mipi_dsi_power_on(dsim, true); +} + +static const struct dev_pm_ops s5p_mipi_dsi_pm_ops = { + .suspend = s5p_mipi_dsi_suspend, + .resume = s5p_mipi_dsi_resume, +#ifdef CONFIG_HIBERNATION + .freeze = s5p_mipi_dsi_suspend, + .thaw = s5p_mipi_dsi_resume, + .restore = s5p_mipi_dsi_resume, +#endif + .runtime_suspend = s5p_mipi_dsi_runtime_suspend, + .runtime_resume = s5p_mipi_dsi_runtime_resume, +}; +#endif + +static struct platform_driver s5p_mipi_dsi_driver = { + .probe = s5p_mipi_dsi_probe, + .remove = __devexit_p(s5p_mipi_dsi_remove), + .driver = { + .name = "s5p-mipi-dsim", + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &s5p_mipi_dsi_pm_ops, +#endif + }, +}; + +static int s5p_mipi_dsi_register(void) +{ + platform_driver_register(&s5p_mipi_dsi_driver); + + return 0; +} + +static void s5p_mipi_dsi_unregister(void) +{ + platform_driver_unregister(&s5p_mipi_dsi_driver); +} + +late_initcall(s5p_mipi_dsi_register); +module_exit(s5p_mipi_dsi_unregister); + +MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>"); +MODULE_DESCRIPTION("Samusung SoC MIPI-DSI driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_common.c b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_common.c new file mode 100644 index 0000000..9b4714c --- /dev/null +++ b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_common.c @@ -0,0 +1,884 @@ +/* linux/drivers/video/s5p_mipi_dsi_common.c + * + * Samsung SoC MIPI-DSI common driver. + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd + * + * InKi Dae, <inki.dae@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/mutex.h> +#include <linux/wait.h> +#include <linux/fs.h> +#include <linux/mm.h> +#include <linux/fb.h> +#include <linux/ctype.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/memory.h> +#include <linux/delay.h> +#include <linux/kthread.h> + +#include <video/mipi_display.h> + +#include <plat/regs-dsim2.h> + +#include <mach/map.h> +#include <plat/mipi_dsim2.h> +#include <plat/regs-dsim2.h> + +#include "s5p_mipi_dsi_lowlevel.h" +#include "s5p_mipi_dsi_common.h" + +#define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250) +#define MIPI_RX_FIFO_READ_DONE 0x30800002 +#define MIPI_MAX_RX_FIFO 20 +#define MHZ (1000 * 1000) +#define FIN_HZ (24 * MHZ) + +#define DFIN_PLL_MIN_HZ (6 * MHZ) +#define DFIN_PLL_MAX_HZ (12 * MHZ) + +#define DFVCO_MIN_HZ (500 * MHZ) +#define DFVCO_MAX_HZ (1000 * MHZ) + +#define TRY_GET_FIFO_TIMEOUT (5000 * 2) +#define TRY_FIFO_CLEAR (10) + +/* MIPI-DSIM status types. */ +enum { + DSIM_STATE_INIT, /* should be initialized. */ + DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */ + DSIM_STATE_HSCLKEN, /* HS clock was enabled. */ + DSIM_STATE_ULPS +}; + +/* define DSI lane types. */ +enum { + DSIM_LANE_CLOCK = (1 << 0), + DSIM_LANE_DATA0 = (1 << 1), + DSIM_LANE_DATA1 = (1 << 2), + DSIM_LANE_DATA2 = (1 << 3), + DSIM_LANE_DATA3 = (1 << 4) +}; + +static unsigned int dpll_table[15] = { + 100, 120, 170, 220, 270, + 320, 390, 450, 510, 560, + 640, 690, 770, 870, 950, +}; + +irqreturn_t s5p_mipi_dsi_interrupt_handler(int irq, void *dev_id) +{ + unsigned int intsrc = 0; + unsigned int intmsk = 0; + struct mipi_dsim_device *dsim = NULL; + + dsim = (struct mipi_dsim_device *)dev_id; + if (!dsim) { + dev_dbg(dsim->dev, KERN_ERR "%s:error: wrong parameter\n", + __func__); + return IRQ_HANDLED; + } + + intsrc = s5p_mipi_dsi_read_interrupt(dsim); + intmsk = s5p_mipi_dsi_read_interrupt_mask(dsim); + + intmsk = ~(intmsk) & intsrc; + + switch (intmsk) { + case INTMSK_RX_DONE: + complete(&dsim_rd_comp); + dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n"); + break; + case INTMSK_FIFO_EMPTY: + complete(&dsim_wr_comp); + dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n"); + break; + default: + break; + } + + s5p_mipi_dsi_clear_interrupt(dsim, intmsk); + + return IRQ_HANDLED; +} + +static void s5p_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, + unsigned int data0, unsigned int data1) +{ + unsigned int data_cnt = 0, payload = 0; + + /* in case that data count is more then 4 */ + for (data_cnt = 0; data_cnt < data1; data_cnt += 4) { + /* + * after sending 4bytes per one time, + * send remainder data less then 4. + */ + if ((data1 - data_cnt) < 4) { + if ((data1 - data_cnt) == 3) { + payload = *(u8 *)(data0 + data_cnt) | + (*(u8 *)(data0 + (data_cnt + 1))) << 8 | + (*(u8 *)(data0 + (data_cnt + 2))) << 16; + dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n", + payload, *(u8 *)(data0 + data_cnt), + *(u8 *)(data0 + (data_cnt + 1)), + *(u8 *)(data0 + (data_cnt + 2))); + } else if ((data1 - data_cnt) == 2) { + payload = *(u8 *)(data0 + data_cnt) | + (*(u8 *)(data0 + (data_cnt + 1))) << 8; + dev_dbg(dsim->dev, + "count = 2 payload = %x, %x %x\n", payload, + *(u8 *)(data0 + data_cnt), + *(u8 *)(data0 + (data_cnt + 1))); + } else if ((data1 - data_cnt) == 1) { + payload = *(u8 *)(data0 + data_cnt); + } + + s5p_mipi_dsi_wr_tx_data(dsim, payload); + /* send 4bytes per one time. */ + } else { + payload = *(u8 *)(data0 + data_cnt) | + (*(u8 *)(data0 + (data_cnt + 1))) << 8 | + (*(u8 *)(data0 + (data_cnt + 2))) << 16 | + (*(u8 *)(data0 + (data_cnt + 3))) << 24; + + dev_dbg(dsim->dev, + "count = 4 payload = %x, %x %x %x %x\n", + payload, *(u8 *)(data0 + data_cnt), + *(u8 *)(data0 + (data_cnt + 1)), + *(u8 *)(data0 + (data_cnt + 2)), + *(u8 *)(data0 + (data_cnt + 3))); + + s5p_mipi_dsi_wr_tx_data(dsim, payload); + } + } +} + +int s5p_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int data1) +{ + if (dsim->state == DSIM_STATE_ULPS) { + dev_err(dsim->dev, "state is ULPS.\n"); + + return -EINVAL; + } + + /* FIXME!!! why does it need this delay? */ + msleep(20); + + mutex_lock(&dsim->lock); + + switch (data_id) { + /* short packet types of packet types for command. */ + case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: + case MIPI_DSI_DCS_SHORT_WRITE: + case MIPI_DSI_DCS_SHORT_WRITE_PARAM: + case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: + s5p_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + break; + + /* general command */ + case MIPI_DSI_COLOR_MODE_OFF: + case MIPI_DSI_COLOR_MODE_ON: + case MIPI_DSI_SHUTDOWN_PERIPHERAL: + case MIPI_DSI_TURN_ON_PERIPHERAL: + s5p_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1); + break; + + /* packet types for video data */ + case MIPI_DSI_V_SYNC_START: + case MIPI_DSI_V_SYNC_END: + case MIPI_DSI_H_SYNC_START: + case MIPI_DSI_H_SYNC_END: + case MIPI_DSI_END_OF_TRANSMISSION: + mutex_unlock(&dsim->lock); + return 0; + + /* long packet type and null packet */ + case MIPI_DSI_NULL_PACKET: + case MIPI_DSI_BLANKING_PACKET: + mutex_unlock(&dsim->lock); + return 0; + case MIPI_DSI_GENERIC_LONG_WRITE: + case MIPI_DSI_DCS_LONG_WRITE: + { + unsigned int size, data_cnt = 0, payload = 0; + INIT_COMPLETION(dsim_wr_comp); + + size = data1 * 4; + + /* if data count is less then 4, then send 3bytes data. */ + if (data1 < 4) { + payload = *(u8 *)(data0) | + *(u8 *)(data0 + 1) << 8 | + *(u8 *)(data0 + 2) << 16; + + s5p_mipi_dsi_wr_tx_data(dsim, payload); + + dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n", + data1, payload, + *(u8 *)(data0 + data_cnt), + *(u8 *)(data0 + (data_cnt + 1)), + *(u8 *)(data0 + (data_cnt + 2))); + /* in case that data count is more then 4 */ + } else + s5p_mipi_dsi_long_data_wr(dsim, data0, data1); + + /* put data into header fifo */ + s5p_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff, + (data1 & 0xff00) >> 8); + + if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp, + MIPI_FIFO_TIMEOUT)) { + dev_warn(dsim->dev, "command write timeout.\n"); + mutex_unlock(&dsim->lock); + return -EAGAIN; + } + } + break; + + /* packet typo for video data */ + case MIPI_DSI_PACKED_PIXEL_STREAM_16: + case MIPI_DSI_PACKED_PIXEL_STREAM_18: + case MIPI_DSI_PIXEL_STREAM_3BYTE_18: + case MIPI_DSI_PACKED_PIXEL_STREAM_24: + break; + + default: + dev_warn(dsim->dev, + "data id %x is not supported current DSI spec.\n", + data_id); + + mutex_unlock(&dsim->lock); + return -EINVAL; + } + + /* ToDo : process response func should be implemented. */ + mutex_unlock(&dsim->lock); + return 0; +} + +static unsigned int s5p_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim, + unsigned int req_size, unsigned int rx_data, u8 *rx_buf) +{ + unsigned int rcv_pkt, i, j; + u16 rxsize; + + /* for long packet */ + rxsize = (u16)((rx_data & 0x00ffff00) >> 8); + dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize); + if (rxsize != req_size) { + dev_dbg(dsim->dev, + KERN_ERR"received data size mismatch \ + received: %d, requested: %d\n", rxsize, req_size); + goto err; + } + + for (i = 0; i < (rxsize >> 2); i++) { + rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim); + dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt); + for(j = 0; j < 4; j++) { + rx_buf[(i * 4) + j] = + (u8)(rcv_pkt >> (j * 8)) & 0xff; + dev_dbg(dsim->dev, "received value : %02x\n", + (rcv_pkt >> (j * 8)) & 0xff); + } + } + if (rxsize % 4) { + rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim); + dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt); + for(j = 0; j < (rxsize % 4); j++) { + rx_buf[(i * 4) + j] = + (u8)(rcv_pkt >> (j * 8)) & 0xff; + dev_dbg(dsim->dev, "received value : %02x\n", + (rcv_pkt >> (j * 8)) & 0xff); + } + } + + return rxsize; + +err: + return -EINVAL; +} + +static unsigned int s5p_mipi_dsi_respense_size(unsigned int req_size) +{ + u8 response; + switch (req_size) { + case 1: + response = MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE; + break; + case 2: + response = MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE; + break; + default: + response = MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE; + break; + } + + return response; +} + +int s5p_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int req_size, u8 *rx_buf) +{ + unsigned int rx_data, rcv_pkt, i; + u8 response = 0; + u16 rxsize; + + if (dsim->state == DSIM_STATE_ULPS) { + dev_err(dsim->dev, "state is ULPS.\n"); + + return -EINVAL; + } + + /* FIXME!!! */ + msleep(20); + + mutex_lock(&dsim->lock); + INIT_COMPLETION(dsim_rd_comp); + s5p_mipi_dsi_rd_tx_header(dsim, + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size); + + response = s5p_mipi_dsi_respense_size(req_size); + + switch (data_id) { + case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: + case MIPI_DSI_DCS_READ: + s5p_mipi_dsi_rd_tx_header(dsim, + data_id, data0); + /* process response func should be implemented. */ + break; + default: + dev_warn(dsim->dev, + "data id %x is not supported current DSI spec.\n", + data_id); + + return -EINVAL; + } + + if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp, + MIPI_FIFO_TIMEOUT)) { + printk(KERN_ERR "RX done interrupt timeout\n"); + mutex_unlock(&dsim->lock); + return 0; + } + + msleep(20); + + rx_data = s5p_mipi_dsi_rd_rx_fifo(dsim); + + if ((u8)(rx_data & 0xff) != response) { + printk(KERN_ERR + "mipi dsi wrong response rx_data : %x, response:%x\n", + rx_data, response); + goto clear_rx_fifo; + } + + if (req_size <= 2) { + /* for short packet */ + for (i = 0; i < req_size; i++) + rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff; + rxsize = req_size; + } else { + /* for long packet */ + rxsize = s5p_mipi_dsi_long_data_rd(dsim, req_size, rx_data, rx_buf); + if (rxsize != req_size) + goto clear_rx_fifo; + } + + rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim); + + msleep(20); + + if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) { + dev_info(dsim->dev, + "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt); + goto clear_rx_fifo; + } + + mutex_unlock(&dsim->lock); + + return rxsize; + +clear_rx_fifo: + i = 0; + while (1) { + rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim); + if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE) + || (i > MIPI_MAX_RX_FIFO)) + break; + dev_dbg(dsim->dev, + "mipi dsi clear rx fifo : %08x\n", rcv_pkt); + i++; + } + dev_info(dsim->dev, + "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt); + + mutex_unlock(&dsim->lock); + + return 0; +} + +static int s5p_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + int sw_timeout; + + if (enable) { + sw_timeout = 1000; + + s5p_mipi_dsi_enable_pll(dsim, 1); + while (1) { + sw_timeout--; + if (s5p_mipi_dsi_is_pll_stable(dsim)) + return 0; + if (sw_timeout == 0) + return -EINVAL; + } + } else + s5p_mipi_dsi_enable_pll(dsim, 0); + + return 0; +} + +static unsigned long s5p_mipi_dsi_change_pll(struct mipi_dsim_device *dsim, + unsigned int pre_divider, unsigned int main_divider, + unsigned int scaler) +{ + unsigned long dfin_pll, dfvco, dpll_out; + unsigned int i, freq_band = 0xf; + + dfin_pll = (FIN_HZ / pre_divider); + + /****************************************************** + * Serial Clock(=ByteClk X 8) FreqBand[3:0] * + ****************************************************** + * ~ 99.99 MHz 0000 + * 100 ~ 119.99 MHz 0001 + * 120 ~ 159.99 MHz 0010 + * 160 ~ 199.99 MHz 0011 + * 200 ~ 239.99 MHz 0100 + * 140 ~ 319.99 MHz 0101 + * 320 ~ 389.99 MHz 0110 + * 390 ~ 449.99 MHz 0111 + * 450 ~ 509.99 MHz 1000 + * 510 ~ 559.99 MHz 1001 + * 560 ~ 639.99 MHz 1010 + * 640 ~ 689.99 MHz 1011 + * 690 ~ 769.99 MHz 1100 + * 770 ~ 869.99 MHz 1101 + * 870 ~ 949.99 MHz 1110 + * 950 ~ 1000 MHz 1111 + ******************************************************/ + if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) { + dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n"); + s5p_mipi_dsi_enable_afc(dsim, 0, 0); + } else { + if (dfin_pll < 7 * MHZ) + s5p_mipi_dsi_enable_afc(dsim, 1, 0x1); + else if (dfin_pll < 8 * MHZ) + s5p_mipi_dsi_enable_afc(dsim, 1, 0x0); + else if (dfin_pll < 9 * MHZ) + s5p_mipi_dsi_enable_afc(dsim, 1, 0x3); + else if (dfin_pll < 10 * MHZ) + s5p_mipi_dsi_enable_afc(dsim, 1, 0x2); + else if (dfin_pll < 11 * MHZ) + s5p_mipi_dsi_enable_afc(dsim, 1, 0x5); + else + s5p_mipi_dsi_enable_afc(dsim, 1, 0x4); + } + + dfvco = dfin_pll * main_divider; + dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n", + dfvco, dfin_pll, main_divider); + if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ) + dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n"); + + dpll_out = dfvco / (1 << scaler); + dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n", + dpll_out, dfvco, scaler); + + for (i = 0; i < ARRAY_SIZE(dpll_table); i++) { + if (dpll_out < dpll_table[i] * MHZ) { + freq_band = i; + break; + } + } + + dev_dbg(dsim->dev, "freq_band = %d\n", freq_band); + + s5p_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler); + + s5p_mipi_dsi_hs_zero_ctrl(dsim, 0); + s5p_mipi_dsi_prep_ctrl(dsim, 0); + + /* Freq Band */ + s5p_mipi_dsi_pll_freq_band(dsim, freq_band); + + /* Stable time */ + s5p_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time); + + /* Enable PLL */ + dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n", + (dpll_out / MHZ)); + + return dpll_out; +} + +static int s5p_mipi_dsi_set_clock(struct mipi_dsim_device *dsim, + unsigned int byte_clk_sel, unsigned int enable) +{ + unsigned int esc_div; + unsigned long esc_clk_error_rate; + unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0; + + if (enable) { + dsim->e_clk_src = byte_clk_sel; + + /* Escape mode clock and byte clock source */ + s5p_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel); + + /* DPHY, DSIM Link : D-PHY clock out */ + if (byte_clk_sel == DSIM_PLL_OUT_DIV8) { + hs_clk = s5p_mipi_dsi_change_pll(dsim, + dsim->dsim_config->p, dsim->dsim_config->m, + dsim->dsim_config->s); + if (hs_clk == 0) { + dev_err(dsim->dev, + "failed to get hs clock.\n"); + return -EINVAL; + } + + byte_clk = hs_clk / 8; + s5p_mipi_dsi_enable_pll_bypass(dsim, 0); + s5p_mipi_dsi_pll_on(dsim, 1); + /* DPHY : D-PHY clock out, DSIM link : external clock out */ + } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) { + dev_warn(dsim->dev, "this project is not support\n"); + dev_warn(dsim->dev, + "external clock source for MIPI DSIM.\n"); + } else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) { + dev_warn(dsim->dev, "this project is not support\n"); + dev_warn(dsim->dev, + "external clock source for MIPI DSIM\n"); + } + + /* escape clock divider */ + esc_div = byte_clk / (dsim->dsim_config->esc_clk); + dev_dbg(dsim->dev, + "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n", + esc_div, byte_clk, dsim->dsim_config->esc_clk); + if ((byte_clk / esc_div) >= (20 * MHZ) || + (byte_clk / esc_div) > + dsim->dsim_config->esc_clk) + esc_div += 1; + + escape_clk = byte_clk / esc_div; + dev_dbg(dsim->dev, + "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n", + escape_clk, byte_clk, esc_div); + + /* enable escape clock. */ + s5p_mipi_dsi_enable_byte_clock(dsim, 1); + + /* enable byte clk and escape clock */ + s5p_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div); + /* escape clock on lane */ + s5p_mipi_dsi_enable_esc_clk_on_lane(dsim, + (DSIM_LANE_CLOCK | dsim->data_lane), 1); + + dev_dbg(dsim->dev, "byte clock is %luMHz\n", + (byte_clk / MHZ)); + dev_dbg(dsim->dev, "escape clock that user's need is %lu\n", + (dsim->dsim_config->esc_clk / MHZ)); + dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div); + dev_dbg(dsim->dev, "escape clock is %luMHz\n", + ((byte_clk / esc_div) / MHZ)); + + if ((byte_clk / esc_div) > escape_clk) { + esc_clk_error_rate = escape_clk / + (byte_clk / esc_div); + dev_warn(dsim->dev, "error rate is %lu over.\n", + (esc_clk_error_rate / 100)); + } else if ((byte_clk / esc_div) < (escape_clk)) { + esc_clk_error_rate = (byte_clk / esc_div) / + escape_clk; + dev_warn(dsim->dev, "error rate is %lu under.\n", + (esc_clk_error_rate / 100)); + } + } else { + s5p_mipi_dsi_enable_esc_clk_on_lane(dsim, + (DSIM_LANE_CLOCK | dsim->data_lane), 0); + s5p_mipi_dsi_set_esc_clk_prs(dsim, 0, 0); + + /* disable escape clock. */ + s5p_mipi_dsi_enable_byte_clock(dsim, 0); + + if (byte_clk_sel == DSIM_PLL_OUT_DIV8) + s5p_mipi_dsi_pll_on(dsim, 0); + } + + return 0; +} + +int s5p_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim) +{ + dsim->state = DSIM_STATE_INIT; + + switch (dsim->dsim_config->e_no_data_lane) { + case DSIM_DATA_LANE_1: + dsim->data_lane = DSIM_LANE_DATA0; + break; + case DSIM_DATA_LANE_2: + dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1; + break; + case DSIM_DATA_LANE_3: + dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | + DSIM_LANE_DATA2; + break; + case DSIM_DATA_LANE_4: + dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | + DSIM_LANE_DATA2 | DSIM_LANE_DATA3; + break; + default: + dev_info(dsim->dev, "data lane is invalid.\n"); + return -EINVAL; + }; + + s5p_mipi_dsi_sw_reset(dsim); + s5p_mipi_dsi_func_reset(dsim); + + s5p_mipi_dsi_dp_dn_swap(dsim, 0); + + return 0; +} + +void s5p_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim) +{ + unsigned int src = 0; + + src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE); + s5p_mipi_dsi_set_interrupt(dsim, src, 1); + + src = 0; + src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY); + s5p_mipi_dsi_set_interrupt_mask(dsim, src, 1); +} + +int s5p_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + /* enable only frame done interrupt */ + s5p_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable); + + return 0; +} + +#if 0 +/* this function can be used to convert legacy timing to generic one. */ +void convert_to_fb_videomode(struct fb_videomode *mode1, + struct s3cfb_lcd *mode2) +{ + mode1->xres = mode2->width; + mode1->yres = mode2->height; + mode1->upper_margin = mode2->timing.v_fp; + mode1->lower_margin = mode2->timing.v_bp; + mode1->left_margin = mode2->timing.h_fp; + mode1->right_margin = mode2->timing.h_bp; + mode1->vsync_len = mode2->timing.v_sw; + mode1->hsync_len = mode2->timing.h_sw; +} +#endif + +void s5p_mipi_dsi_stand_by(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + + /* consider Main display and Sub display. */ + + s5p_mipi_dsi_set_main_stand_by(dsim, enable); +} + +int s5p_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_config) +{ + struct s5p_platform_mipi_dsim *dsim_pd; + struct fb_videomode *timing; + + dsim_pd = (struct s5p_platform_mipi_dsim *)dsim->pd; + timing = (struct fb_videomode *)dsim_pd->lcd_panel_info; + + /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */ + if (dsim_config->e_interface == (u32) DSIM_VIDEO) { + if (dsim_config->auto_vertical_cnt == 0) { + s5p_mipi_dsi_set_main_disp_vporch(dsim, + dsim_config->cmd_allow, + timing->lower_margin, + timing->upper_margin); + s5p_mipi_dsi_set_main_disp_hporch(dsim, + timing->right_margin, + timing->left_margin); + s5p_mipi_dsi_set_main_disp_sync_area(dsim, + timing->vsync_len, + timing->hsync_len); + } + } + + s5p_mipi_dsi_set_main_disp_resol(dsim, timing->xres, + timing->yres); + + s5p_mipi_dsi_display_config(dsim, dsim_config); + + dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n", + timing->xres, timing->yres); + + return 0; +} + +int s5p_mipi_dsi_init_link(struct mipi_dsim_device *dsim) +{ + unsigned int time_out = 100; + + switch (dsim->state) { + case DSIM_STATE_INIT: + s5p_mipi_dsi_init_fifo_pointer(dsim, 0x1f); + + /* dsi configuration */ + s5p_mipi_dsi_init_config(dsim); + s5p_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1); + s5p_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1); + + /* set clock configuration */ + s5p_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1); + + /* check clock and data lane state are stop state */ + while (!(s5p_mipi_dsi_is_lane_state(dsim))) { + time_out--; + if (time_out == 0) { + dev_err(dsim->dev, + "DSI Master is not stop state.\n"); + dev_err(dsim->dev, + "Check initialization process\n"); + + return -EINVAL; + } + } + if (time_out != 0) { + dev_info(dsim->dev, + "DSI Master driver has been completed.\n"); + dev_info(dsim->dev, "DSI Master state is stop state\n"); + } + + dsim->state = DSIM_STATE_STOP; + + /* BTA sequence counters */ + s5p_mipi_dsi_set_stop_state_counter(dsim, + dsim->dsim_config->stop_holding_cnt); + s5p_mipi_dsi_set_bta_timeout(dsim, + dsim->dsim_config->bta_timeout); + s5p_mipi_dsi_set_lpdr_timeout(dsim, + dsim->dsim_config->rx_timeout); + + return 0; + default: + dev_info(dsim->dev, "DSI Master is already init.\n"); + return 0; + } + + return 0; +} + +int s5p_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim) +{ + if (dsim->state == DSIM_STATE_STOP) { + if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) { + dsim->state = DSIM_STATE_HSCLKEN; + + /* set LCDC and CPU transfer mode to HS. */ + s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); + s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0); + + s5p_mipi_dsi_enable_hs_clock(dsim, 1); + + return 0; + } else + dev_warn(dsim->dev, + "clock source is external bypass.\n"); + } else + dev_warn(dsim->dev, "DSIM is not stop state.\n"); + + return 0; +} + +int s5p_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int mode) +{ + if (mode) { + if (dsim->state != DSIM_STATE_HSCLKEN) { + dev_err(dsim->dev, "HS Clock lane is not enabled.\n"); + return -EINVAL; + } + + s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); + } else { + if (dsim->state == DSIM_STATE_INIT || dsim->state == + DSIM_STATE_ULPS) { + dev_err(dsim->dev, + "DSI Master is not STOP or HSDT state.\n"); + return -EINVAL; + } + + s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0); + } + + return 0; +} + +int s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim) +{ + return _s5p_mipi_dsi_get_frame_done_status(dsim); +} + +int s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) +{ + _s5p_mipi_dsi_clear_frame_done(dsim); + + return 0; +} + +int s5p_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim, + unsigned int val) +{ + int try = TRY_FIFO_CLEAR; + + s5p_mipi_dsi_sw_reset_release(dsim); + s5p_mipi_dsi_func_reset(dsim); + + do { + if (s5p_mipi_dsi_get_sw_reset_release(dsim)) { + s5p_mipi_dsi_init_interrupt(dsim); + dev_dbg(dsim->dev, "reset release done.\n"); + return 0; + } + } while (--try); + + dev_err(dsim->dev, "failed to clear dsim fifo.\n"); + return -EAGAIN; +} + +MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>"); +MODULE_DESCRIPTION("Samusung MIPI-DSIM common driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_common.h b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_common.h new file mode 100644 index 0000000..4e4883e --- /dev/null +++ b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_common.h @@ -0,0 +1,45 @@ +/* linux/drivers/video/s5p_mipi_dsi_common.h + * + * Header file for Samsung SoC MIPI-DSI common driver. + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd + * + * InKi Dae <inki.dae@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _S5P_MIPI_DSI_COMMON_H +#define _S5P_MIPI_DSI_COMMON_H + +static DECLARE_COMPLETION(dsim_rd_comp); +static DECLARE_COMPLETION(dsim_wr_comp); + +int s5p_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int data1); +int s5p_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id, + unsigned int data0, unsigned int req_size, u8 *rx_buf); +irqreturn_t s5p_mipi_dsi_interrupt_handler(int irq, void *dev_id); +void s5p_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim); +int s5p_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_stand_by(struct mipi_dsim_device *dsim, + unsigned int enable); +int s5p_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_info); +int s5p_mipi_dsi_init_link(struct mipi_dsim_device *dsim); +int s5p_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim); +int s5p_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int mode); +int s5p_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim, + unsigned int enable); +int s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim); +int s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim); + +extern struct fb_info *registered_fb[FB_MAX] __read_mostly; + +int s5p_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim, + unsigned int val); + +#endif /* _S5P_MIPI_DSI_COMMON_H */ diff --git a/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_lowlevel.c b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_lowlevel.c new file mode 100644 index 0000000..48b8967 --- /dev/null +++ b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_lowlevel.c @@ -0,0 +1,627 @@ +/* linux/drivers/video/s5p_mipi_dsi_lowlevel.c + * + * Samsung SoC MIPI-DSI lowlevel driver. + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd + * + * InKi Dae, <inki.dae@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/mutex.h> +#include <linux/wait.h> +#include <linux/delay.h> +#include <linux/fs.h> +#include <linux/mm.h> +#include <linux/ctype.h> +#include <linux/io.h> + +#include <mach/map.h> + +#include <plat/mipi_dsim2.h> +#include <plat/regs-dsim2.h> + +void s5p_mipi_dsi_func_reset(struct mipi_dsim_device *dsim) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_SWRST); + + reg |= DSIM_FUNCRST; + + writel(reg, dsim->reg_base + S5P_DSIM_SWRST); +} + +void s5p_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_SWRST); + + reg |= DSIM_SWRST; + + writel(reg, dsim->reg_base + S5P_DSIM_SWRST); +} + +void s5p_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_INTSRC); + + reg |= INTSRC_SW_RST_RELEASE; + + writel(reg, dsim->reg_base + S5P_DSIM_INTSRC); +} + +int s5p_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim) +{ + return (readl(dsim->reg_base + S5P_DSIM_INTSRC)) & + INTSRC_SW_RST_RELEASE; +} + +unsigned int s5p_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_INTMSK); + + return reg; +} + +void s5p_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, + unsigned int mode, unsigned int mask) +{ + unsigned int reg = 0; + + if (mask) + reg |= mode; + else + reg &= ~mode; + + writel(reg, dsim->reg_base + S5P_DSIM_INTMSK); +} + +void s5p_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, + unsigned int cfg) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_FIFOCTRL); + + writel(reg & ~(cfg), dsim->reg_base + S5P_DSIM_FIFOCTRL); + mdelay(10); + reg |= cfg; + + writel(reg, dsim->reg_base + S5P_DSIM_FIFOCTRL); +} + +/* + * this function set PLL P, M and S value in D-PHY + */ +void s5p_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, + unsigned int value) +{ + writel(DSIM_AFC_CTL(value), dsim->reg_base + S5P_DSIM_PHYACCHR); +} + +void s5p_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_MDRESOL); + + reg &= ~DSIM_MAIN_STAND_BY; + + if (enable) + reg |= DSIM_MAIN_STAND_BY; + + writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL); +} + +void s5p_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, + unsigned int width_resol, unsigned int height_resol) +{ + unsigned int reg; + + /* standby should be set after configuration so set to not ready*/ + reg = (readl(dsim->reg_base + S5P_DSIM_MDRESOL)) & + ~(DSIM_MAIN_STAND_BY); + writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL); + + reg &= ~((0x7ff << 16) | (0x7ff << 0)); + reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol); + + reg |= DSIM_MAIN_STAND_BY; + writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL); +} + +void s5p_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, + unsigned int cmd_allow, unsigned int vfront, unsigned int vback) +{ + unsigned int reg; + + reg = (readl(dsim->reg_base + S5P_DSIM_MVPORCH)) & + ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) | + (DSIM_MAIN_VBP_MASK)); + + reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) | + ((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) | + ((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_MVPORCH); +} + +void s5p_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, + unsigned int front, unsigned int back) +{ + unsigned int reg; + + reg = (readl(dsim->reg_base + S5P_DSIM_MHPORCH)) & + ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK)); + + reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_MHPORCH); +} + +void s5p_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori) +{ + unsigned int reg; + + reg = (readl(dsim->reg_base + S5P_DSIM_MSYNC)) & + ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK)); + + reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) | + (hori << DSIM_MAIN_HSA_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_MSYNC); +} + +void s5p_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori) +{ + unsigned int reg; + + reg = (readl(dsim->reg_base + S5P_DSIM_SDRESOL)) & + ~(DSIM_SUB_STANDY_MASK); + + writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL); + + reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); + reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) | + ((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT); + writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL); + + reg |= (1 << DSIM_SUB_STANDY_SHIFT); + writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL); +} + +void s5p_mipi_dsi_init_config(struct mipi_dsim_device *dsim) +{ + struct mipi_dsim_config *dsim_config = dsim->dsim_config; + + unsigned int cfg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) & + ~((1 << 28) | (0x1f << 20) | (0x3 << 5)); + + cfg = (dsim_config->auto_flush << 29) | + (dsim_config->eot_disable << 28) | + (dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) | + (dsim_config->hse << DSIM_HSE_MODE_SHIFT) | + (dsim_config->hfp << DSIM_HFP_MODE_SHIFT) | + (dsim_config->hbp << DSIM_HBP_MODE_SHIFT) | + (dsim_config->hsa << DSIM_HSA_MODE_SHIFT) | + (dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT); + + writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG); +} + +void s5p_mipi_dsi_display_config(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_config) +{ + u32 reg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) & + ~((0x3 << 26) | (1 << 25) | (0x3 << 18) | (0x7 << 12) | + (0x3 << 16) | (0x7 << 8)); + + if (dsim_config->e_interface == DSIM_VIDEO) + reg |= (1 << 25); + else if (dsim_config->e_interface == DSIM_COMMAND) + reg &= ~(1 << 25); + else { + dev_err(dsim->dev, "unknown lcd type.\n"); + return; + } + + /* main lcd */ + reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 | + ((u8) (dsim_config->e_virtual_ch) & 0x3) << 18 | + ((u8) (dsim_config->e_pixel_format) & 0x7) << 12; + + writel(reg, dsim->reg_base + S5P_DSIM_CONFIG); +} + +void s5p_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, + unsigned int enable) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_CONFIG); + + if (enable) + reg |= DSIM_LANE_ENx(lane); + else + reg &= ~DSIM_LANE_ENx(lane); + + writel(reg, dsim->reg_base + S5P_DSIM_CONFIG); +} + + +void s5p_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, + unsigned int count) +{ + unsigned int cfg; + + /* get the data lane number. */ + cfg = DSIM_NUM_OF_DATA_LANE(count); + + writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG); +} + +void s5p_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable, + unsigned int afc_code) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR); + + if (enable) { + reg |= (1 << 14); + reg &= ~(0x7 << 5); + reg |= (afc_code & 0x7) << 5; + } else + reg &= ~(1 << 14); + + writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR); +} + +void s5p_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & + ~(DSIM_PLL_BYPASS_EXTERNAL); + + reg |= enable << DSIM_PLL_BYPASS_SHIFT; + + writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); +} + +void s5p_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p, + unsigned int m, unsigned int s) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & + ~(0x7ffff << 1); + + reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1); + + writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); +} + +void s5p_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, + unsigned int freq_band) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & + ~(0x1f << DSIM_FREQ_BAND_SHIFT); + + reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); +} + +void s5p_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, + unsigned int pre_divider, unsigned int main_divider, + unsigned int scaler) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & + ~(0x7ffff << 1); + + reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 | + (scaler & 0x7) << 1; + + writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); +} + +void s5p_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, + unsigned int lock_time) +{ + writel(lock_time, dsim->reg_base + S5P_DSIM_PLLTMR); +} + +void s5p_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & + ~(0x1 << DSIM_PLL_EN_SHIFT); + + reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); +} + +void s5p_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, + unsigned int src) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & + ~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT); + + reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT; + + writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); +} + +void s5p_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & + ~(1 << DSIM_BYTE_CLKEN_SHIFT); + + reg |= enable << DSIM_BYTE_CLKEN_SHIFT; + + writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); +} + +void s5p_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, + unsigned int enable, unsigned int prs_val) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & + ~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff)); + + reg |= enable << DSIM_ESC_CLKEN_SHIFT; + if (enable) + reg |= prs_val; + + writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); +} + +void s5p_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, + unsigned int lane_sel, unsigned int enable) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_CLKCTRL); + + if (enable) + reg |= DSIM_LANE_ESC_CLKEN(lane_sel); + else + + reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel); + + writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); +} + +void s5p_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) & + ~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT); + + reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE); +} + +unsigned int s5p_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_STATUS); + + /** + * check clock and data lane states. + * if MIPI-DSI controller was enabled at bootloader then + * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK. + * so it should be checked for two case. + */ + if ((reg & DSIM_STOP_STATE_DAT(0xf)) && + ((reg & DSIM_STOP_STATE_CLK) || + (reg & DSIM_TX_READY_HS_CLK))) + return 1; + else + return 0; + + return 0; +} + +void s5p_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, + unsigned int cnt_val) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) & + ~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT); + + reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE); +} + +void s5p_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) & + ~(0xff << DSIM_BTA_TOUT_SHIFT); + + reg |= (timeout << DSIM_BTA_TOUT_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT); +} + +void s5p_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) & + ~(0xffff << DSIM_LPDR_TOUT_SHIFT); + + reg |= (timeout << DSIM_LPDR_TOUT_SHIFT); + + writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT); +} + +void s5p_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE); + + reg &= ~DSIM_CMD_LPDT_LP; + + if (lp) + reg |= DSIM_CMD_LPDT_LP; + + writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE); +} + +void s5p_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE); + + reg &= ~DSIM_TX_LPDT_LP; + + if (lp) + reg |= DSIM_TX_LPDT_LP; + + writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE); +} + +void s5p_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) & + ~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT); + + reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT; + + writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL); +} + +void s5p_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, + unsigned int swap_en) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR1); + + reg &= ~(0x3 << 0); + reg |= (swap_en & 0x3) << 0; + + writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR1); +} + +void s5p_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, + unsigned int hs_zero) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & + ~(0xf << 28); + + reg |= ((hs_zero & 0xf) << 28); + + writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); +} + +void s5p_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep) +{ + unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) & + ~(0x7 << 20); + + reg |= ((prep & 0x7) << 20); + + writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL); +} + +unsigned int s5p_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim) +{ + return readl(dsim->reg_base + S5P_DSIM_INTSRC); +} + +void s5p_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim, + unsigned int src) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC); + + reg |= src; + + writel(reg, dsim->reg_base + S5P_DSIM_INTSRC); +} + +void s5p_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim, + unsigned int src, unsigned int enable) +{ + unsigned int reg = 0; + + if (enable) + reg |= src; + else + reg &= ~src; + + writel(reg, dsim->reg_base + S5P_DSIM_INTSRC); +} + +unsigned int s5p_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim) +{ + unsigned int reg; + + reg = readl(dsim->reg_base + S5P_DSIM_STATUS); + + return reg & (1 << 31) ? 1 : 0; +} + +unsigned int s5p_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) +{ + unsigned int ret; + + ret = readl(dsim->reg_base + S5P_DSIM_FIFOCTRL) & ~(0x1f); + + return ret; +} + +void s5p_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, + unsigned int di, unsigned int data0, unsigned int data1) +{ + unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0); + + writel(reg, dsim->reg_base + S5P_DSIM_PKTHDR); +} + +void s5p_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim, + unsigned int di, unsigned int data0) +{ + unsigned int reg = (data0 << 8) | (di << 0); + + writel(reg, dsim->reg_base + S5P_DSIM_PKTHDR); +} + +unsigned int s5p_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim) +{ + unsigned int reg = 0; + + reg = readl(dsim->reg_base + S5P_DSIM_RXFIFO); + + return reg; +} + +unsigned int _s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC); + + return (reg & INTSRC_FRAME_DONE) ? 1 : 0; +} + +void _s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) +{ + unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC); + + writel(reg | INTSRC_FRAME_DONE, dsim->reg_base + + S5P_DSIM_INTSRC); +} + +void s5p_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, + unsigned int tx_data) +{ + writel(tx_data, dsim->reg_base + S5P_DSIM_PAYLOAD); +} diff --git a/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_lowlevel.h b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_lowlevel.h new file mode 100644 index 0000000..828e6cd --- /dev/null +++ b/drivers/video/samsung_duallcd/dsim2/s5p_mipi_dsi_lowlevel.h @@ -0,0 +1,111 @@ +/* linux/drivers/video/s5p_mipi_dsi_lowlevel.h + * + * Header file for Samsung SoC MIPI-DSI lowlevel driver. + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd + * + * InKi Dae <inki.dae@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _S5P_MIPI_DSI_LOWLEVEL_H +#define _S5P_MIPI_DSI_LOWLEVEL_H + +void s5p_mipi_dsi_func_reset(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim); +int s5p_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, + unsigned int mode, unsigned int mask); +void s5p_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, + unsigned int count); +void s5p_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, + unsigned int cfg); +void s5p_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, + unsigned int value); +void s5p_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, + unsigned int value); +void s5p_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim, + unsigned int enable); +void s5p_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, + unsigned int width_resol, unsigned int height_resol); +void s5p_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, + unsigned int cmd_allow, unsigned int vfront, unsigned int vback); +void s5p_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, + unsigned int front, unsigned int back); +void s5p_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori); +void s5p_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori); +void s5p_mipi_dsi_init_config(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_display_config(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_config); +void s5p_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, + unsigned int count); +void s5p_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, + unsigned int enable); +void s5p_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable, + unsigned int afc_code); +void s5p_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, + unsigned int enable); +void s5p_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p, + unsigned int m, unsigned int s); +void s5p_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, + unsigned int freq_band); +void s5p_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, + unsigned int pre_divider, unsigned int main_divider, + unsigned int scaler); +void s5p_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, + unsigned int lock_time); +void s5p_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, + unsigned int enable); +void s5p_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, + unsigned int src); +void s5p_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, + unsigned int enable); +void s5p_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, + unsigned int enable, unsigned int prs_val); +void s5p_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, + unsigned int lane_sel, unsigned int enable); +void s5p_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, + unsigned int enable); +unsigned int s5p_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, + unsigned int cnt_val); +void s5p_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout); +void s5p_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout); +void s5p_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp); +void s5p_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp); +void s5p_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, + unsigned int enable); +void s5p_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, + unsigned int swap_en); +void s5p_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, + unsigned int hs_zero); +void s5p_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep); +unsigned int s5p_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim); +unsigned int s5p_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim, + unsigned int src); +void s5p_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim, + unsigned int src, unsigned int enable); +unsigned int s5p_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim); +unsigned int s5p_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim); +unsigned int _s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim); +void _s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim); +void s5p_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, unsigned int di, + unsigned int data0, unsigned int data1); +void s5p_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, + unsigned int tx_data); +void s5p_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim, + unsigned int data0, unsigned int data1); +unsigned int s5p_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim); + +#endif /* _S5P_MIPI_DSI_LOWLEVEL_H */ |