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* OMAP4: clock data: Change DSS clock aliasesTomi Valkeinen2011-04-201-7/+2
| | | | | | | | | | | | | | | | | | | | | | DSS driver has used fck and ick clocks on OMAP2/3 to get DSS HW up and running, and also to get the pixel clock's source clock rate from the fck. On OMAP4 the clock data is set up in a different way, as there's no ick, dss_fck points to a fake clock which just affects DSS's MODULEMODE, and dss_dss_clk if the DSS_FCK. >From DSS driver's point of view the dss_fck sounds like an ick, and dss_dss_clk is the fck. While this is not entirely correct from HW point of view, especially for the ick, configuring the clock aliases that way makes DSS "just work" with OMAP4's clock setup. In the (hopefully near) future DSS driver will be reworked to use pm_runtime support which should clean up the clock code. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'for-paul' of git://gitorious.org/linux-omap-dss2/linuxPaul Mundt2011-03-221-5/+10
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/board-overo.c Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * OMAP4: DSS2: clocks: Add ick as dummy clockSumit Semwal2011-03-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | DSS code uses ick as one of the clocks in clk_get/clk_put. OMAP4 clock database doesn't have ick for DSS, so adding ick as dummy clock. This is needed for backward compatibility with OMAP2/3. Once pm_runtime* APIs get introduced in DSS, this will be revisited. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * OMAP2PLUS: clocks: Align DSS clock names and rolesSumit Semwal2011-03-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, clock database has <dev, clock-name> tuples for DSS2. Because of this, the clock names are different across different OMAP platforms. This patch aligns the DSS2 clock names and roles across OMAP 2420, 2430, 3xxx, 44xx platforms in the clock databases, hwmod databases for opt-clocks, and DSS clock handling. This ensures that clk_get/put/enable/disable APIs in DSS can use uniform role names. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* | Merge branch 'omap-for-linus' of ↵Linus Torvalds2011-03-171-33/+44
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (258 commits) omap: zoom: host should not pull up wl1271's irq line arm: plat-omap: iommu: fix request_mem_region() error path OMAP2+: Common CPU DIE ID reading code reads wrong registers for OMAP4430 omap4: mux: Remove duplicate mux modes omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag omap: iovmm: disallow mapping NULL address when IOVMF_DA_ANON is set omap2+: mux: Fix compile when CONFIG_OMAP_MUX is not selected omap4: board-omap4panda: Initialise the serial pads omap3: board-3430sdp: Initialise the serial pads omap4: board-4430sdp: Initialise the serial pads omap2+: mux: Add macro for configuring static with omap_hwmod_mux_init omap2+: mux: Remove the use of IDLE flag omap2+: Add separate list for dynamic pads to mux perf: add OMAP support for the new power events OMAP4: Add IVA OPP enteries. OMAP4: Update Voltage Rail Values for MPU, IVA and CORE OMAP4: Enable 800 MHz and 1 GHz MPU-OPP OMAP3+: OPP: Replace voltage values with Macros OMAP3: wdtimer: Fix CORE idle transition Watchdog: omap_wdt: add fine grain runtime-pm ... Fix up various conflicts in - arch/arm/mach-omap2/board-omap3evm.c - arch/arm/mach-omap2/clock3xxx_data.c - arch/arm/mach-omap2/usb-musb.c - arch/arm/plat-omap/include/plat/usb.h - drivers/usb/musb/musb_core.h
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| *-. \ Merge remote branches 'remotes/origin/pwrdm_clkdm_b_2.6.39', ↵Paul Walmsley2011-03-101-33/+44
| |\ \ \ | | | |/ | | | | | | | | 'remotes/origin/pwrdm_add_can_lose_context_fns_2.6.39', 'remotes/origin/omap_device_a_2.6.39', 'remotes/origin/mmc_a_2.6.39', 'remotes/origin/hwmod_b_2.6.39', 'remotes/origin/dmtimer_a_2.6.39', 'remotes/origin/pwrdm_clkdm_a_2.6.39', 'remotes/origin/clkdm_statdep_omap4_2.6.39', 'remotes/origin/clk_a_2.6.39', 'remotes/origin/clk_autoidle_a_2.6.39', 'remotes/origin/clk_autoidle_b_2.6.39', 'remotes/origin/clk_b_2.6.39', 'remotes/origin/clk_clkdm_a_2.6.39', 'remotes/origin/misc_a_2.6.39', 'remotes/origin/for_2.6.39/omap3_hwmod_data' and 'remotes/origin/wdtimer_a_2.6.39' into tmp-integration-2.6.39-20110310-024
| | | * OMAP: hsmmc: Rename the device and driverKishore Kadiyala2011-03-011-10/+10
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Modifying the device & driver name from "mmci-omap-hs" to "omap_hsmmc". Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Acked-by: Benoit Cousson<b-cousson@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * OMAP2+: clock: disable autoidle on all clocks during clock initPaul Walmsley2011-02-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable autoidle on all clocks during clock framework initialization. (If CONFIG_PM is set, autoidle is re-enabled for all clocks later in the boot process.) The principle behind this patch, and some similar patches, is that the kernel should start with all power management features disabled. Later in the boot process, the PM code, if compiled in with CONFIG_PM, enables or re-enables power management features. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
| | * omap4: dpll: Enable auto gate control for all MX postdividersRajendra Nayak2011-02-251-22/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hardware gate control for all dpll MX and X2 postdividers. This requires the allow_idle/deny_idle functions to be populated for all clock nodes (mx/x2 post dividers) in clkops. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * OMAP3/4: DPLL: Add allow_idle/deny_idle support for all DPLL'sRajendra Nayak2011-02-251-1/+1
| |/ | | | | | | | | | | | | | | | | All OMAP3/4 dpll's support hardware level autogating. Populate allow_idle/deny_idle function pointers for all DPLL's in clkops. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | arm: omap: usb: clock entries for omap3 and omap4Keshava Munegowda2011-03-011-5/+5
|/ | | | | | | | | | | The devices of clocks are set to usbhs, so that only usbhs common driver can invoke these clocks. The dummy per port clocks are added to omap3 clock data base. This helps to invoke common clock get APIs for omap3 and omap4. Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* OMAP: PRCM: remove duplicated headersFelipe Balbi2011-01-181-1/+0
| | | | | | | | | | | | | | | | | | | | | A few headers are included twice, remove them. Found the following errors using make includecheck: arch/arm/mach-omap2/clock44xx_data.c: prm44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm1_44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm2_44xx.h is included more than once. arch/arm/mach-omap2/powerdomain2xxx_3xxx.c: prm-regbits-34xx.h is included more than once. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Felipe Balbi <balbi@ti.com> [paul@pwsan.com: dropped lists from patch cc:s; tweaked subject line] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'usb-next' of ↵Linus Torvalds2011-01-071-1/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6 * 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (144 commits) USB: add support for Dream Cheeky DL100B Webmail Notifier (1d34:0004) USB: serial: ftdi_sio: add support for TIOCSERGETLSR USB: ehci-mxc: Setup portsc register prior to accessing OTG viewport USB: atmel_usba_udc: fix freeing irq in usba_udc_remove() usb: ehci-omap: fix tll channel enable mask usb: ohci-omap3: fix trivial typo USB: gadget: ci13xxx: don't assume that PAGE_SIZE is 4096 USB: gadget: ci13xxx: fix complete() callback for no_interrupt rq's USB: gadget: update ci13xxx to work with g_ether USB: gadgets: ci13xxx: fix probing of compiled-in gadget drivers Revert "USB: musb: pm: don't rely fully on clock support" Revert "USB: musb: blackfin: pm: make it work" USB: uas: Use GFP_NOIO instead of GFP_KERNEL in I/O submission path USB: uas: Ensure we only bind to a UAS interface USB: uas: Rename sense pipe and sense urb to status pipe and status urb USB: uas: Use kzalloc instead of kmalloc USB: uas: Fix up the Sense IU usb: musb: core: kill unneeded #include's DA8xx: assign name to MUSB IRQ resource usb: gadget: g_ncm added ... Manually fix up trivial conflicts in USB Kconfig changes in: arch/arm/mach-omap2/Kconfig arch/sh/Kconfig drivers/usb/Kconfig drivers/usb/host/ehci-hcd.c and annoying chip clock data conflicts in: arch/arm/mach-omap2/clock3xxx_data.c arch/arm/mach-omap2/clock44xx_data.c
| * usb: musb: move clock handling to glue layerFelipe Balbi2010-12-101-1/+1
| | | | | | | | | | | | | | | | | | musb core doesn't need to know about platform specific details. So start moving clock handling to platform glue layer and make musb core agnostic about that. Signed-off-by: Felipe Balbi <balbi@ti.com>
| * usb: musb: trivial search and replace patchFelipe Balbi2010-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | change all ocurrences of musb_hdrc to musb-hdrc. We will call glue layer drivers musb-<glue layer>, so in order to keep things somewhat standard, let's change the underscore into a dash. Signed-off-by: Felipe Balbi <balbi@ti.com>
| * omap: clock: add clkdev aliases for EHCI clocksAnand Gadiyar2010-12-011-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add clkdev aliases for the USBHOST and USBTLL clocks on OMAP3 and OMAP4, so that the driver can refer to the clocks using a common alias. This will disappear when the driver is converted to use the hwmod database, but until then this patch is needed. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Tony Lindgren <tony@atomide.com>
* | OMAP4: clock data: Add missing fixed divisorsJon Hunter2010-12-221-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following OMAP4 clocks have the following fixed divisors that determine the frequency at which these clocks operate. These dividers are defined by the PRCM specification and without these dividers the rates of the below clocks are calculated incorrectly. This may cause internal peripherals using these clocks to operate at the wrong frequency. - abe_24m_fclk (freq = divided-by-8) - ddrphy_ck (freq = parent divided-by-2) - dll_clk_div_ck (freq = parent divided-by-2) - per_hs_clk_div_ck (freq = parent divided-by-2) - usb_hs_clk_div_ck (freq = parent divided-by-3) - func_12m_fclk (freq = parent divided-by-16) - func_24m_clk (freq = parent divided-by-4) - func_24mc_fclk (freq = parent divided-by-8) - func_48mc_fclk (freq = divided-by-4) - lp_clk_div_ck (freq = divided-by-16) - per_abe_24m_fclk (freq = divided-by-4) Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Keep L3INSTR clock domain modulemode under HW controlSantosh Shilimkar2010-12-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L3INSTR clock domain is read only register and its reset value is HW_AUTO. The modules withing this clock domain needs to be kept under hardware control. MODULEMODE: - 0x0: Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup). - 0x1: Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state. This patch keeps CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL and CM_L3INSTR_INTRCONN_WP1_CLKCTRL module mode under hardware control by using ENABLE_ON_INIT flag. Without this the OMAP4 device OFF mode SAR restore phase aborts during interconnect register restore phase. This can be also handled by doing explicit a clock enable and disable in the low power code since there is no direct module associated with it. But that seems not necessary since the clock domain is under HW control. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clocks: add dummy clock for mailboxHari Kanigeri2010-12-211-0/+1
| | | | | | | | | | | | | | | | | | | | In omap4, there is no explicit configuration register to enable mailbox clocks. Defining dummy clock for mailbox clock module to keep the mailbox driver backward compatible with previous omaps. Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Acked-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP: clock: fix configuration of J-Type DPLLs to work for OMAP3 and OMAP4Jon Hunter2010-12-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | J-Type DPLLs have additional configuration parameters that need to be programmed when setting the multipler and divider for the DPLL. These parameters being the sigma delta divider (SD_DIV) for the DPLL and the digital controlled oscillator (DCO) to be used by the DPLL. The current code is implemented specifically to configure the OMAP3630 PER J-Type DPLL. The OMAP4430 USB DPLL is also a J-Type DPLL and so this code needs to be updated to work for both OMAP3 and OMAP4 devices and any other future devices that have J-TYPE DPLLs. For the OMAP3630 PER DPLL both the SD_DIV and DCO paramenters are used but for the OMAP4430 USB DPLL only the SD_DIV field is used. The current implementation will only program the SD_DIV and DCO fields if the DPLL has both and hence this does not work for OMAP4430. In order to make the code more generic add two new fields to the dpll_data structure for the SD_DIV field and DCO field bit-masks and only program these fields if the masks are defined for a specific DPLL. This simplifies the code and allows us to remove the flag DPLL_NO_DCO_SEL. Tested on OMAP36xx Zoom3 and OMAP4 Blaze. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: removed explicit inlining and added '_' prefix on lookup_*() functions; added testing info to commit message; added 35xx comments back in] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: hwmod & clock data: Fix GPIO opt_clks and ocp_if iclkBenoit Cousson2010-12-211-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix opt clocks name in clock framework and hwmod. Add the missing iclk in the ocp_if structure. Add the HWMOD_CONTROL_OPT_CLKS_IN_RESET flag to ensure the the GPIO optional clock is enable during reset. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Tested-by: Charulatha V <charu@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocksRajendra Nayak2010-12-211-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CORE and PER M3 post dividers are different from the rest of the DPLL post dividers as in they go to SCRM, and are used there to export clocks for instance used by external sensor. There is no automatic HW dependency in PRCM to manage them. Hence these two clocks (dpll post dividers) should be managed by SW and explicitly enabled/disabled. Add control in clock framework to handle that. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Add SCRM auxiliary clock nodesRajendra Nayak2010-12-211-0/+175
| | | | | | | | | | | | | | | | Add support for auxiliary clocks nodes which are part of SCRM. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ckJonathan Bergsagel2010-12-211-1/+5
| | | | | | | | | | | | | | | | | | | | Add register address, mask and link to the clksel structure that were missing in the IVA DPLL mux clock node. Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Add missing DPLL x2 clock nodesThara Gopinath2010-12-211-175/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the OMAP4 clock data to include various x2 clock nodes between DPLL and HS dividers as the clock framework skips a x2 while calculating the dpll locked frequency. The clock database extensions are autogenerated using the scripts maintained by Benoit Cousson. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Thara Gopinath <thara@ti.com> [paul@pwsan.com: fixed merge conflicts against v2.6.37-rc5; dropped dpll_mpu_x2_ck on advice from Benoît] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Add control for pad_clks_ck and slimbus_clkBenoit Cousson2010-12-211-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gating of pad_clks and slimbus_ck is controlled by the PRCM, but since the clock source is external, this is the SW responsability to gate / un-gate it when the mcpdm or slimbus module need to be used. There is no autogating possible with such external clock. Add SW control to enable / disable this SW gating in the pad_clks_ck and slimbus_clk clock node. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP2/3: PRCM: split OMAP2/3-specific PRCM code into OMAP2/3-specific filesPaul Walmsley2010-12-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding OMAP4-specific PRCM accessor/mutator functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific files. Most of what was in mach-omap2/{cm,prm}.{c,h} has now been moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was OMAP2xxx/3xxx-specific. This process also requires the #includes in each of these files to be changed to reference the new file name. As part of doing so, add some comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use "sideways includes", to indicate that these users of the PRM/CM includes should not be doing so. Thanks to Felipe Contreras <felipe.contreras@gmail.com> for comments on this patch. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Jarkko Nikula <jhnikula@gmail.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Felipe Contreras <felipe.contreras@gmail.com> Acked-by: Felipe Contreras <felipe.contreras@gmail.com> Cc: Greg Kroah-Hartman <greg@kroah.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | OMAP4: PRCM: reorganize existing OMAP4 PRCM header filesPaul Walmsley2010-12-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the existing cm44xx.h file into cm1_44xx.h and cm2_44xx.h files so they match their underlying OMAP hardware modules. Add clockdomain offset information. Add header files for the MPU local PRCM, prcm_mpu44xx.h, and for the SCRM, scrm44xx.h. SCRM register offsets still need to be added; TI should do this. Move the "_MOD" macros out of the prcm-common.h header file, into the header file of the hardware module that they belong to. For example, OMAP4430_PRM_*_MOD macros have been moved into the prm44xx.h header. Adjust #includes of all files that used the old PRCM header file names to point to the new filenames. The autogeneration scripts have been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | I2C: i2c-omap: Change device name: i2c_omap -> omap_i2cBenoit Cousson2010-12-201-8/+8
|/ | | | | | | | | | | | | | | | | The convention for omap device naming is omap_XXX. Rename the device and driver name in order to stick to this naming convention. Change device name in clock nodes as well. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ben Dooks <ben-i2c@fluff.org> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP: control: move plat-omap/control.h to mach-omap2/control.hPaul Walmsley2010-10-081-1/+1
| | | | | | | | | | | | | | | | | Only OMAP2+ platforms have the System Control Module (SCM) IP block. In the past, we've kept the SCM header file in plat-omap. This has led to abuse - device drivers including it; includes being added that create implicit dependencies on OMAP2+ builds; etc. In response, move the SCM headers into mach-omap2/. As part of this, remove the direct SCM access from the OMAP UDC driver. It was clearly broken. The UDC code needs an indepth review for use on OMAP2+ chips. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Kyungmin Park <kyungmin.park@samsung.com>
* OMAP4: clocks: Fix ES2 clock issuesBenoit Cousson2010-09-271-33/+55
| | | | | | | | | | | | | | | | | | Fix a few OMAP4430 clock tree problems after the recent manual merge of the various ES2 clock patches: - usim optional clock and its parent had the same name, rename the parent usim_fclk -> usim_ck - OPTFCLKEN_CLK32K is not handled anymore by the USBPHYOCP2SCP module in ES2 Create a new clock that belongs to CM_ALWON_USBPHY_CLKCTRL register This patch depends on some of the PRCM macro updates from Rajendra. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: tweaked patch description] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP4: clock: Add optional clock nodesBenoit Cousson2010-09-271-60/+417
| | | | | | | | | | | | | | | | | OMAP4 IP optional clocks require explicit enable in module CTRLCLK register. In order to allow that we have to create artificial clock nodes that represent this clock inputs in the IP. Notes: - Temporary use OMAP3 names for GPIO optional clocks until the GPIO hwmod convertion is done. It will enforce the usage of OMAP4 names as the reference. - Temporary use OMAP3 names for TIMER main clock (gptX_fck) until TIMER hwmod convertion is done. During that convertion, the new name will have to be used. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP4: clock: Fix clock names and align with hwmod namesBenoit Cousson2010-09-271-355/+310
| | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP4 hwmod data introduced the new naming convention for TI IPs (See patch OMAP4: hwmod: Add partial hwmod support for OMAP4430 ES1.0) The leaf clock names are using the same IP name and thus must be modified to match the clock populated in the hwmod data. - Fix some leaf clocks nodes that were using a _iclk instead of the _fclk prefix. - Fix some wrong interface clock name for master IPs connected to interconnect. Please not that due to the fact that nodes are sorted by name, the name change will introduce a quite ugly diff a little bit hard to follow. Timers clock con_id is still using the old gptX_fck name until the gptimer driver is updated to omap_device framework. Timers entries in hwmods DB are still disabled until the migration if timer to platform_driver + omap_hwmod. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: manually resolved conflicts with Rajendra's clock patch] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP4: clocks: Update clock tree for ES2Rajendra Nayak2010-09-271-98/+74
| | | | | | | | | | | | | | | | | | | | This patch updates the clock tree with all the changes in OMAP4430 ES2. clock nodes added -1- tie_low_clock_ck -2- abe_dpll_bypass_clk_mux_ck clock nodes deleted -1- dpll_sys_ref_clk -2- per_sgx_fclk -3- usbphyocp2scp_ick Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> [paul@pwsan.com: added comment re ES1 clocks to top of file] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
* OMAP4: clock: Fix multi-omap boot with reset un-used clocksSantosh Shilimkar2010-06-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | This patch uses "ENABLE_ON_INIT" flag on the emif clock nodes to avoid the emif clk getting cut as part of reset un-used clock routine which prevents boot. Since "omap4xxx_clk_init()" calls "clk_enable_init_clocks()" which increases the usecount on all ENABLE_ON_INIT clocks, it prevents "omap2_clk_disable_unused()" from disabling the clock. The real fix is to have driver for EMIF and do clock get/enable as part of it. The EMIF driver is planned to be done HWMOD way so till that available to keep omap3_defconfig booting on OMAP4430, this patch is necessary. (Will updated the auto-gen script for 44xx accordingly) The fix was suggested by Paul Walmsley Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* omap4: Adds Dummy Interface clock's for MMC controllerskishore kadiyala2010-05-201-0/+5
| | | | | | | | This patch adds dummy Interface clocks for MMC controllers Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP4: Clocks: Change SPI Instance NamesAbraham Arce2010-04-231-4/+4
| | | | | | | | | | | | | Change the name for the spi instances on omap44xx_clks to match the names omap2 spi driver gives: omap-mcspi.1 -> omap2_mcspi.1 omap-mcspi.2 -> omap2_mcspi.2 omap-mcspi.3 -> omap2_mcspi.3 omap-mcspi.4 -> omap2_mcspi.4 Signed-off-by: Abraham Arce <x0066660@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP4: clock: Add dummy clock nodes for interface clocksSantosh Shilimkar2010-02-241-0/+35
| | | | | | | | | | | | | | | | On OMAP4 platform the iclk control is completly under hardware control and no software control is available. This difference w.r.t previous OMAP's needs all the common driver accross OMAP's , cpu_is_xxxx() checks. To avoid poulluting the drivers dummy clock nodes are created (The autogeneration script has been updated accordingly). Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: made OMAP1 dummy_ck common and edited patch to reuse that] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: clock: Rename leaf clock nodes to end with a _ick or _fckRajendra Nayak2010-02-241-264/+297
| | | | | | | | | | All leaf clock nodes are renamed for OMAP4 to have a clk name which end with a _ick or a _fck. This is done so that the naming convention is same as that followed on older OMAPs. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4 clock: drop the ALWAYS_ENABLED clock flagPaul Walmsley2010-02-241-11/+0
| | | | | | | | | Get rid of the ALWAYS_ENABLED clock flag - it doesn't actually do anything. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoît Cousson <b-cousson@ti.com>
* OMAP3/4 clock: split into per-chip family filesPaul Walmsley2010-02-241-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
* OMAP4 clock: drop the CLOCK_IN_OMAP4430 clock flagPaul Walmsley2010-02-241-113/+11
| | | | | | | | | | | The CLOCK_IN_OMAP4430 clock flag is not currently needed in the OMAP4 ES1 clock tree, and platform discrimination via clock flags is deprecated in favor of the clkdev mechanism, so, drop it. (The OMAP4 clock tree autogeneration script has been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, ↵Paul Walmsley2010-02-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | includes, documentation The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are one increment higher than they should be. See for example the OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into the DPLL's M register bitfield is valid for OMAP2/3 and indicates that the DPLL should enter MN-bypass mode. Also, increase the minimum multiplier (M) value for the DPLL rate rounding code from 1 to 2, to ensure that it does not inadvertently put the DPLL into bypass. Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs does not make clear that the actual DPLL divider value (the "N") is the content of the appropriate register bitfield for the N value, _plus one_. (In other words, an N register bitfield of 0 indicates a DPLL divider value of 1.) This is only clearly documented in the OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167 "CM_CLKSEL_DPLL_USB". While here, update copyrights, add kerneldoc for struct dpll_data, drop the unused struct dpll_data.max_tolerance field, remove some unnecessary #includes in DPLL-related code, and replace the #include of <linux/module.h> with <linux/list.h>, which is what was really needed. The OMAP4 clock autogenerator script has been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP3 clock: introduce DPLL4 JtypeRichard Woodruff2010-02-241-0/+1
| | | | | | | | | | | | | | | | DPLL4 for 3630 introduces a changed block called j type dpll, requiring special divisor bits and additional reg fields. To allow for silicons to use this, this is introduced as a flag and is enabled for 3630 silicon. OMAP4 also has j type dpll for usb. Tested with 3630 ZOOM3 and OMAP3430 ZOOM2 Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: added some comments; updated copyrights and credits; fixed some style issues] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* omap3/4: Fix compile for multi-omap for clkops_noncore_dpll_opsTony Lindgren2010-02-151-6/+6
| | | | | | | | Rename clkops_noncore_dpll_ops for omap3 and omap4. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP2/3/4 clock: rename and clean the omap2_clk_init() functionsPaul Walmsley2010-01-291-3/+1
| | | | | | | | | | | | | | | Rename the omap2_clk_init() in the OMAP2, 3, and 4 clock code to be omap2xxx_clk_init(), omap3xxx_clk_init(), etc. Remove all traces of the (commented) old virt_prcm_set code from omap3xxx_clk_init() and omap4xxx_clk_init(), since this will be handled with the OPP code that is cooking in the PM branch. After this patch, there should be very little else in the clock code that blocks a multi-OMAP 2+3 kernel. (OMAP2420+OMAP2430 still has some outstanding issues that need to be resolved; this is pending on some additions to the hwmod data.) Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4 clock framework: Remove the checks preventing OMAP4 clockdomain ↵Abhijit Pagare2010-01-261-2/+0
| | | | | | | | | | | validation The clockdomain related code being in place, it is not necessary to have some part of the clock code commented out. This would help the validation of the clockdomain functions using the clock level interfaces. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: clocks: Fix the clksel_rate struct DPLL divsRajendra Nayak2010-01-201-31/+31
| | | | | | | | | | For all DPLL's the valid dividers are same as the values to be programmed in the register. 0 is an invalid value. The changes are generated by updating the script which autogenerates the file modifed in the patch. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4: PM: Add init api for DPLL nodesRajendra Nayak2009-12-111-0/+7
| | | | | | | | | | | | An api at init for all dpll nodes seem to be needed to reparent the dpll clk node to its bypass clk in case the dpll is in bypass. If not done this causes sequencing issues at init during propogate_rate. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
* ARM: OMAP4: PM: OMAP4 clock tree and clkdev registrationRajendra Nayak2009-12-111-0/+2759
This patch defines all the clock nodes in OMAP4430 platform. All the clock node structs and the clkdev table is autogenerated using a python script (gen_clock_tree.py) developed by Paul Walmsley, Benoit Cousson and Rajendra Nayak. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
generated by cgit v1.1 at 2024-05-19 14:54:11 +0000