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* Merge linux-3.0.31 from korg into jellybeancodeworkx2012-09-181-1/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mm/proc-v7.S drivers/base/core.c drivers/gpu/drm/i915/i915_gem_execbuffer.c drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i915/intel_lvds.c drivers/gpu/drm/radeon/evergreen.c drivers/gpu/drm/radeon/r100.c drivers/gpu/drm/radeon/radeon_connectors.c drivers/gpu/drm/radeon/rs600.c drivers/usb/core/hub.c drivers/usb/host/xhci-pci.c drivers/usb/host/xhci.c drivers/usb/serial/qcserial.c fs/proc/base.c Change-Id: Ia98b35db3f8c0bfd95817867d3acb85be8e5e772
| * drm/i915: quirk away broken OpRegion VBTDaniel Vetter2012-04-131-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 25e341cfc33d94435472983825163e97fe370a6c upstream. Somehow the BIOS manages to screw things up when copying the VBT around, because the one we scrap from the VBIOS rom actually works. Tested-by: Markus Heinz <markus.heinz@uni-dortmund.de> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28812 Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | samsung update 1codeworkx2012-06-021-70/+99
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* drm: Verify debug message argumentsJoe Perches2011-04-281-3/+3
| | | | | | | | Add __attribute__((format (printf, 4, 5))) to drm_ut_debug_printk and fix fallout. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Revert "drm/i915: Disable SSC for outputs other than LVDS or DP"Chris Wilson2011-02-221-1/+0
| | | | | | | | | | | | This reverts commit 633f2ea26665d37bb3c8ae30799aa14988622653 and the attempted fix dcbe6f2b3d136995915e2f9ecc7d4f3b28f47b6c. There is a single clock source used for both SSC (some LVDS and DP) and non-SSC (VGA, DVI) outputs. So we need to be careful to only enable SSC as necessary. However, fiddling with DREFCLK was causing DP links to be dropped and we do not have a fix ready, so revert. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Override SDVO panel type in VBTChris Wilson2011-02-011-8/+14
| | | | | | | | | | | | | Judging by comments in the BIOS, if the SDVO LVDS option h40 is enabled, then we are supposed to query the real panel type via Int15. We don't do this and so for the Sony Vaio VGC-JS210J which has otherwise default values, we choose the wrong mode. This patch adds a driver option, i915.vbt_sdvo_panel_type, which can be used to override the value in the VBT. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33691 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Disable SSC for outputs other than LVDS or DPChris Wilson2011-01-191-0/+1
| | | | | | | | | | | | For CRT and SDVO/HDMI, we need to use a normal, non-SSC, clock and so we must clear any enabling bits left-over from earlier outputs. And also seems to correct the LVDS panel on the Lenovo U160. However, at one point, it did cause an "ERROR failed to disable trancoder". So prolonged testing on top of Jesse's refactored and error-checking CRTC logic is desired. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/bios: Change default clock source on PineView to use SSCBryan Freed2011-01-191-8/+23
| | | | | | | | | | | | | The i915 driver normally assumes the video bios has configured several of the LVDS panel registers, and it just inherits the values. If the vbios has not run, several of these will need to be setup. If these are not correct then although the panel looks ok, output from an HDMI encoder (eg, Chrontel CH7036) will be incorrect. Signed-off-by: Mark Hayter <mdhayter@chromium.org> [ickle: minor adjustments] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Add a module option to override the use of SSCChris Wilson2011-01-131-11/+6
| | | | | | | | | | | In order to workaround the issue with LVDS not working on the Lenovo U160 apparently due to using the wrong SSC frequency, add an option to disable SSC. Suggested-by: Lukács, Árpád <lukacs.arpad@gmail.com> Bugzillla: https://bugs.freedesktop.org/show_bug.cgi?id=32748 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
* Revert "drm/i915/bios: Reverse order of 100/120 Mhz SSC clocks"Chris Wilson2010-12-301-1/+1
| | | | | | | | | | | As I feared, whilst this fixed the clocks for the Lenovo U160, it broke many other machines. So lets reverts commit 448f53a1ede54eb854d036abf and search for the real bug. Reported-and-tested-by: Travis Hume <travis@computoring.org> [et al] Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=25842 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32698 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/bios: Reverse order of 100/120 Mhz SSC clocksChris Wilson2010-12-141-1/+1
| | | | | | | | | Fixes the lack of output on the LVDS panel of the Lenovo U160. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31596 Reported-and-tested-by: Dirk Gouders <gouders@et.bocholt.fh-gelsenkirchen.de> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson2010-10-211-2/+2
| | | | | | | So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Initialize panel timing registers if VBIOS did notBryan Freed2010-10-191-2/+19
| | | | | | | | | | | | | The time between start of the pixel clock and backlight enable is a basic panel timing constraint. If the Panel Power On/Off registers are found to be 0, assume we are booting without VBIOS initialization and set these registers to something reasonable. Change-Id: Ibed6cc10d46bf52fd92e0beb25ae3525b5eef99d Signed-off-by: Bryan Freed <bfreed@chromium.org> [ickle: rearranged into a separate function to distinguish its role from simply parsing the VBIOS tables.] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: fetch eDP configuration data from the VBTJesse Barnes2010-10-081-11/+49
| | | | | | | | We need to use some of these values in eDP configurations, so be sure to fetch them and store them in the i915 private structure. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* i915: Added function to initialize VBT settingsSimon Que2010-09-301-13/+23
| | | | | | | | | | | | | | | | | | Added a function that sets the LVDS values to default settings. This will be called by intel_init_bios before checking for the VBT (video BIOS table). The default values are thus loaded regardless of whether a VBT is found. The default settings in each parse function have been moved to the new function. This consolidates all the default settings into one place. The default dither bit value has been changed from 0 to 1. We can assume that display devices will want dithering enabled. Signed-off-by: Simon Que <sque@chromium.org> Acked-by: Olof Johansson <olof@lixom.net> [ickle: fixup for -next] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/sdvo: Fix GMBUSificationChris Wilson2010-09-281-0/+9
| | | | | | | | Besides a couple of bugs when writing more than a single byte along the GMBUS, SDVO was completely failing whilst trying to use GMBUS, so use bit banging instead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Parse the eDP link configuration from the vBIOSChris Wilson2010-09-241-14/+27
| | | | | | | First step, lets have a look at the values for troublesome panels and see if they may be used to improve our link training. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Don't offset the pin used for crt_ddcChris Wilson2010-09-221-1/+1
| | | | | | | | | | Previously when converting the GMBUS pin to the GPIO reg, we would offset the pin by one and then use the look-up table. Now that we first try to use the GMBUS pin, we no longer need the offset and can use the value from the VBIOS directly. Reported-by: Carlos R. Mafra <crmafra2@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: use GMBUS to manage i2c linksChris Wilson2010-09-181-12/+4
| | | | | | | | | | | | | | Use the GMBUS interface rather than direct bit banging to grab the EDID over DDC (and for other forms of auxiliary communication with external display controllers). The hope is that this method will be much faster and more reliable than bit banging for fetching EDIDs from buggy monitors or through switches, though we still preserve the bit banging as a fallback in case GMBUS fails. Based on an original patch by Jesse Barnes. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915/bios: Prevent NULL dereference after allocation failureChris Wilson2010-09-121-0/+2
| | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* drm/i915: Use the VBT from OpRegion when available (v3)Chris Wilson2010-09-081-31/+42
| | | | | | | | | | | | | | | | It is recommended that we use the Video BIOS tables that were copied into the OpRegion during POST when initialising the driver. This saves us from having to furtle around inside the ROM ourselves and possibly allows the vBIOS to adjust the tables prior to initialisation. On some systems, such as the Samsung N210, there is no accessible VBIOS and the only means of finding the VBT is through the OpRegion. v2: Rearrange the code so that ASLE is enabled along with ACPI v3: Enable OpRegion parsing even without ACPI Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Garrett <mjg@redhat.com>
* drm/i915: Honor sync polarity from VBT panel timing descriptorsAdam Jackson2010-06-011-0/+10
| | | | | | | I'm actually kind of shocked that it works at all otherwise. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix DDC bus selection for multifunction SDVOAdam Jackson2010-05-101-0/+1
| | | | | | | | | | | | | | | | | | Multifunction SDVO cards stopped working after 14571b4, and would report something that looked remarkably like an ADD2 SPD ROM instead of EDID. This appears to be because DDC bus selection was utterly horked by that commit; controlled_output was no longer always a single bit, so intel_sdvo_select_ddc_bus would pick bus 0, which is (unsurprisingly) the SPD ROM bus, not a DDC bus. So, instead of that, let's just use the DDC bus the child device table tells us to use. I'm guessing at the bitmask and shifting from VBIOS dumps, but it can't possibly be worse. cf. https://bugzilla.redhat.com/584229 Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drivers/gpu/drm/i915/intel_bios.c: fix continuation line formatsJoe Perches2010-03-171-2/+3
| | | | | | | | | | | | | String constants that are continued on subsequent lines with \ will cause spurious whitespace in the resulting output. Signed-off-by: Joe Perches <joe@perches.com> Cc: Dave Airlie <airlied@linux.ie> Cc: Eric Anholt <eric@anholt.net> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> [anholt: whacked it to wrap to 80 columns instead] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.Eric Anholt2010-02-261-1/+2
| | | | Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: parse eDP panel color depth from VBT blockZhenyu Wang2010-01-151-0/+32
| | | | | Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: disable LVDS downclock by defaultJesse Barnes2010-01-151-1/+2
| | | | | | | | | | | | | | | Many platform support this feature, and it can provide significant power savings when the reduced refresh rate is low. However, on some platforms a secondary (reduced) timing is provided but not actually supported by the hardware. This results in undesirable flicker at runtime. So disable the feature by default, but allow users to opt-in to the reduced clock behavior with a new module parameter, lvds_downclock, that can be set to 1 to enable the feature. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix product names and #definesAdam Jackson2009-12-071-1/+1
| | | | | | | | | IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: parse child device from VBTZhao Yakui2009-11-301-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | On some laptops there is no HDMI/DP. But the xrandr still reports several disconnected HDMI/display ports. In such case the user will be confused. >DVI1 disconnected (normal left inverted right x axis y axis) >DP1 disconnected (normal left inverted right x axis y axis) >DVI2 disconnected (normal left inverted right x axis y axis) >DP2 disconnected (normal left inverted right x axis y axis) >DP3 disconnected (normal left inverted right x axis y axis) This patch set is to use the child device parsed in VBT to decide whether the HDMI/DP/LVDS/TV should be initialized. Parse the child device from VBT. The device class type is also added for LFP, TV, HDMI, DP output. https://bugs.freedesktop.org/show_bug.cgi?id=22785 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix gpio register detection logic for BIOS without VBTShaohua Li2009-11-301-4/+0
| | | | | | | | | | | if no VBT is present, crt_ddc_bus will be left at 0, and cause us to use that for the GPIO register offset. That's never a valid register offset, so let the "undefined" value be 0 instead of -1. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net> [anholt: clarified the commit message a bit]
* drm/i915: Check whether the LVDS downclock is found in VBTZhao Yakui2009-11-251-0/+42
| | | | | | | | | | Enumerate the LVDS panel timing info entry list in VBT to check whether the LVDS downclock is found. If found, the downclock is also used to switch dynamically between low and high frequency for LVDS. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMSZhao Yakui2009-11-051-12/+12
| | | | | | | Replace the DRM_DEBUG with DRM_DEBUG_KMS in output device code. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix render reclock availability detection.Andy Lutomirski2009-10-131-8/+6
| | | | | | | | | If the device didn't support EDP, we would bail out too soon. Signed-off-by: Andy Lutomirski <luto@mit.edu> [anholt: Pulled this patch out of the patch for adding quirks to enable reclocking.] Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix SSC frequence for IGDNGZhenyu Wang2009-09-171-0/+3
| | | | | | | | | IGDNG LVDS SSC uses 120Mhz freq. This fixes one 1600x900 LVDS panel black issue on IGDNG with SSC enabled. Cc: Stable Team <stable@kernel.org> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* drm/i915: add dynamic clock frequency controlJesse Barnes2009-09-041-1/+7
| | | | | | | | | | | | | | | | | There are several sources of unnecessary power consumption on Intel graphics systems. The first is the LVDS clock. TFTs don't suffer from persistence issues like CRTs, and so we can reduce the LVDS refresh rate when the screen is idle. It will be automatically upclocked when userspace triggers graphical activity. Beyond that, we can enable memory self refresh. This allows the memory to go into a lower power state when the graphics are idle. Finally, we can drop some clocks on the gpu itself. All of these things can be reenabled between frames when GPU activity is triggered, and so there should be no user visible graphical changes. Signed-off-by: Jesse Barnes <jesse.barnes@intel.com> Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Improve CRTDDC mapping by using VBT infoDavid Müller (ELSOFT AG)2009-08-291-3/+48
| | | | | | | | | | Use VBT information to determine which DDC bus to use for CRTDCC. Fall back to GPIOA if VBT info is not available. Signed-off-by: David Müller <d.mueller@elsoft.ch> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Tested on: 855 (David), and 945GM, 965GM, GM45, and G45 (anholt)
* drm/i915: Add eDP support on IGDNG mobile chipZhenyu Wang2009-07-291-0/+21
| | | | | | | | | | | | | This adds embedded DisplayPort support on next mobile chip which aims to replace origin LVDS port. VBT's driver feature block has been used to determine the type of current internal panel for eDP or LVDS. Currently no panel fitting support for eDP and backlight control would be added in future. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/I915: Fix offset to DVO timings in LVDS dataZhao Yakui2009-07-291-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the DVO timing in LVDS data entry is obtained by using the following step: a. get the entry size for every LVDS panel data b. Get the LVDS fp entry for the preferred panel type c. get the DVO timing by using entry->dvo_timing In our driver the entry->dvo_timing is related with the size of lvds_fp_timing. For example: the size is 46. But it seems that the size of lvds_fp_timing varies on the differnt platform. In such case we will get the incorrect DVO timing entry because of the incorrect DVO offset in LVDS panel data entry. This also removes a hack on new IGDNG to get proper DVO timing. Calculate the DVO timing offset in LVDS data entry to get the DVO timing a. get the DVO timing offset in the LVDS fp data entry by using the pointer definition in LVDS data ptr b. get the LVDS data entry c. get the DVO timing by adding the DVO timing offset to data entry https://bugs.freedesktop.org/show_bug.cgi?id=22787 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Tested-by: Zhenyu Wang <zhenyuw@linux.intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fix for LVDS VBT change on IGDNGZhenyu Wang2009-07-101-1/+9
| | | | | | | | | IGDNG mobile chip's LVDS data block removes panel fitting register definition. So this fixes offset for LVDS timing block parsing. Thanks for Michael Fu to catch this. Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Set SSC frequency for 8xx chips correctlyling.ma@intel.com2009-07-011-4/+6
| | | | | | | | All 8xx class chips have the 66/48 split, not just 855. Signed-off-by: Ma Ling <ling.ma@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: fix LFP data fetchJesse Barnes2009-06-221-1/+11
| | | | | | | | | | | | Apparently the proper way to do this is to use the LFP data pointer block to figure out the LFP data block entry size, then use that plus the panel index to calculate an offset into the LFP data block array. Similar fix has already been pushed to the 2D driver to fix fdo bug applied to the VBIOS reader, and things look sane). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm: Remove memory debugging infrastructure.Eric Anholt2009-06-181-4/+2
| | | | | | | | It hasn't been used in ages, and having the user tell your how much memory is being freed at free time is a recipe for disaster even if it was ever used. Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: parse VBT general definition block to get the SDVO device infoyakui_zhao2009-06-051-1/+85
| | | | | | | | | | | | | | | The general definition block contains the child device tables, which include the SDVO device info. For example: device slave address, device dvo port, device type. We will get the info of SDVO device by parsing the general definition blocks. Only when a valid slave address is found, it is regarded as the SDVO device. And the info of DVO port and slave address is recorded. http://bugs.freedesktop.org/show_bug.cgi?id=20429 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: Fetch SDVO LVDS mode lines from VBT, then reserve themMa Ling2009-05-221-30/+72
| | | | | Signed-off-by: Ma Ling <ling.ma@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
* drm/i915: handle bogus VBT panel timingJesse Barnes2009-02-251-0/+6
| | | | | | | | | We've seen cases in the wild where the VBT sync data is wrong, so add some code to fix it up in that case, taking care to make sure that the total is greater than the sync end. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@linux.ie>
* drm: Use spread spectrum when the bios tells us it's ok.Kristian Høgsberg2009-02-201-0/+8
| | | | | | | | Lifted from the DDX modesetting. Signed-off-by: Kristian Høgsberg <krh@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* DRM: i915: add mode setting supportJesse Barnes2008-12-291-0/+193
This commit adds i915 driver support for the DRM mode setting APIs. Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are supported. HDMI, DisplayPort and additional SDVO output support will follow. Support for the mode setting code is controlled by the new 'modeset' module option. A new config option, CONFIG_DRM_I915_KMS controls the default behavior, and whether a PCI ID list is built into the module for use by user level module utilities. Note that if mode setting is enabled, user level drivers that access display registers directly or that don't use the kernel graphics memory manager will likely corrupt kernel graphics memory, disrupt output configuration (possibly leading to hangs and/or blank displays), and prevent panic/oops messages from appearing. So use caution when enabling this code; be sure your user level code supports the new interfaces. A new SysRq key, 'g', provides emergency support for switching back to the kernel's framebuffer console; which is useful for testing. Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
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