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path: root/drivers/pci/dmar.c
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* intel-iommu: Clean up handling of "caching mode" vs. context flushing.David Woodhouse2009-05-101-10/+3
* Intel IOMMU Pass Through SupportFenghua Yu2009-04-291-1/+10
* intel-iommu: Avoid panic() for DRHD at address zero.David Woodhouse2009-04-101-1/+10
* intel-iommu: Handle PCI domains appropriately.David Woodhouse2009-04-041-0/+1
* Intel IOMMU Suspend/Resume Support - Queued InvalidationFenghua Yu2009-04-031-15/+55
* x86, dmar: use atomic allocations for QI and Intr-remapping initSuresh Siddha2009-03-171-3/+3
* x86, dmar: start with sane state while enabling dma and interrupt-remappingSuresh Siddha2009-03-171-4/+1
* x86, dmar: routines for disabling queued invalidation and intr remappingSuresh Siddha2009-03-171-0/+36
* x86, x2apic: enable fault handling for intr-remappingSuresh Siddha2009-03-171-18/+84
* x86, dmar: move page fault handling code to dmar.cSuresh Siddha2009-03-171-0/+191
* Merge branch 'x86/urgent' into x86/patIngo Molnar2009-03-011-17/+56
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| * intel-iommu: fix endless "Unknown DMAR structure type" loopTony Battersby2009-02-141-0/+8
| * VT-d: handle Invalidation Queue Error to avoid system hangYu Zhao2009-02-091-16/+45
| * intel-iommu: fix build error with INTR_REMAP=y and DMAR=nJoerg Roedel2009-02-091-1/+3
* | pci, x86, acpi: fix early_ioremap() leakYinghai Lu2009-02-111-2/+5
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* calculate agaw for each iommuWeidong Han2009-01-031-0/+10
* VT-d: fix segment number being ignored when searching DRHDYu Zhao2009-01-031-18/+18
* Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds...David Woodhouse2008-10-211-26/+31
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| * Merge branch 'genirq-v28-for-linus' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2008-10-201-27/+34
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| | * dmar: fix dmar_parse_dev() devices_cnt error condition checkSuresh Siddha2008-10-161-1/+1
| | * dmar: use list_for_each_entry_safe() in dmar_dev_scope_init()Suresh Siddha2008-10-161-4/+4
| | * dmar: initialize the return value in dmar_parse_dev()Yinghai Lu2008-10-161-1/+1
| | * dmar: fix using early fixmap mapping for DMAR table parsingYinghai Lu2008-10-161-21/+28
* | | dmar: fix uninitialised 'ret' variable in dmar_parse_dev()David Woodhouse2008-10-181-3/+2
* | | intel-iommu: IA64 supportFenghua Yu2008-10-181-8/+11
* | | dmar: remove the quirk which disables dma-remapping when intr-remapping enabledYouquan Song2008-10-171-15/+5
* | | dmar: context cache and IOTLB invalidation using queued invalidationYouquan Song2008-10-171-0/+56
* | | dmar: use spin_lock_irqsave() in qi_submit_sync()Suresh Siddha2008-10-171-6/+13
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* | VT-d: Changes to support KVMKay, Allen M2008-10-151-2/+2
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* x64, x2apic/intr-remap: disable DMA-remapping if Interrupt-remapping is detec...Suresh Siddha2008-07-121-0/+25
* x64, x2apic/intr-remap: Interrupt remapping infrastructureSuresh Siddha2008-07-121-0/+16
* x64, x2apic/intr-remap: Queued invalidation infrastructure (part of VT-d)Suresh Siddha2008-07-121-0/+150
* x64, x2apic/intr-remap: parse ioapic scope under vt-d structuresSuresh Siddha2008-07-121-0/+3
* x64, x2apic/intr-remap: Fix the need for RMRR in the DMA-remapping detectionSuresh Siddha2008-07-121-3/+1
* x64, x2apic/intr-remap: use CONFIG_DMAR for DMA-remapping specific codeSuresh Siddha2008-07-121-11/+24
* x64, x2apic/intr-remap: code re-structuring, to be used by both DMA and Inter...Suresh Siddha2008-07-121-16/+73
* x64, x2apic/intr-remap: fix the need for sequential array allocation of iommusSuresh Siddha2008-07-121-2/+9
* x64, x2apic/intr-remap: Intel vt-d, IOMMU code reorganizationSuresh Siddha2008-07-121-1/+89
* copyright owner and author clean up for intel iommu and related filesmark gross2008-02-231-4/+5
* Genericizing iova.[ch]David Miller2008-02-061-0/+1
* PCI: More Sanity checks for DMARFenghua Yu2008-02-011-3/+17
* Intel IOMMU: DMAR detection and parsing logicKeshavamurthy, Anil S2007-10-221-0/+329
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