1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
|
/*
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
*
* A copy of the licence is included with the program, and can also be obtained from Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
/**
* @file mali_utgard.h
* Defines types and interface exposed by the Mali Utgard device driver
*/
#ifndef __MALI_UTGARD_H__
#define __MALI_UTGARD_H__
#define MALI_GPU_NAME_UTGARD "mali-utgard"
/* Mali-200 */
#define MALI_GPU_RESOURCES_MALI200(base_addr, gp_irq, pp_irq, mmu_irq) \
MALI_GPU_RESOURCE_PP(base_addr + 0x0000, pp_irq) \
MALI_GPU_RESOURCE_GP(base_addr + 0x2000, gp_irq) \
MALI_GPU_RESOURCE_MMU(base_addr + 0x3000, mmu_irq)
/* Mali-300 */
#define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
#define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
/* Mali-400 */
#define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq)
#define MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
#define MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq)
#define MALI_GPU_RESOURCES_MALI400_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
#define MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0xC000, pp2_irq, base_addr + 0x6000, pp2_mmu_irq)
#define MALI_GPU_RESOURCES_MALI400_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
#define MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0xC000, pp2_irq, base_addr + 0x6000, pp2_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0xE000, pp3_irq, base_addr + 0x7000, pp3_mmu_irq)
#define MALI_GPU_RESOURCES_MALI400_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
/* Mali-450 */
#define MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
#define MALI_GPU_RESOURCES_MALI450_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
#define MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
#define MALI_GPU_RESOURCES_MALI450_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
#define MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x0E000, pp3_irq, base_addr + 0x07000, pp3_mmu_irq) \
MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
#define MALI_GPU_RESOURCES_MALI450_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
#define MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x11000) \
MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x28000, pp3_irq, base_addr + 0x1C000, pp3_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + 0x2A000, pp4_irq, base_addr + 0x1D000, pp4_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + 0x2C000, pp5_irq, base_addr + 0x1E000, pp5_mmu_irq) \
MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
#define MALI_GPU_RESOURCES_MALI450_MP6_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
#define MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x0E000, pp3_irq, base_addr + 0x07000, pp3_mmu_irq) \
MALI_GPU_RESOURCE_L2(base_addr + 0x11000) \
MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + 0x28000, pp4_irq, base_addr + 0x1C000, pp4_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + 0x2A000, pp5_irq, base_addr + 0x1D000, pp5_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(6, base_addr + 0x2C000, pp6_irq, base_addr + 0x1E000, pp6_mmu_irq) \
MALI_GPU_RESOURCE_PP_WITH_MMU(7, base_addr + 0x2E000, pp7_irq, base_addr + 0x1F000, pp7_mmu_irq) \
MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
#define MALI_GPU_RESOURCES_MALI450_MP8_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
#define MALI_GPU_RESOURCE_L2(addr) \
{ \
.name = "Mali_L2", \
.flags = IORESOURCE_MEM, \
.start = addr, \
.end = addr + 0x200, \
},
#define MALI_GPU_RESOURCE_GP(gp_addr, gp_irq) \
{ \
.name = "Mali_GP", \
.flags = IORESOURCE_MEM, \
.start = gp_addr, \
.end = gp_addr + 0x100, \
}, \
{ \
.name = "Mali_GP_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = gp_irq, \
.end = gp_irq, \
}, \
#define MALI_GPU_RESOURCE_GP_WITH_MMU(gp_addr, gp_irq, gp_mmu_addr, gp_mmu_irq) \
{ \
.name = "Mali_GP", \
.flags = IORESOURCE_MEM, \
.start = gp_addr, \
.end = gp_addr + 0x100, \
}, \
{ \
.name = "Mali_GP_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = gp_irq, \
.end = gp_irq, \
}, \
{ \
.name = "Mali_GP_MMU", \
.flags = IORESOURCE_MEM, \
.start = gp_mmu_addr, \
.end = gp_mmu_addr + 0x100, \
}, \
{ \
.name = "Mali_GP_MMU_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = gp_mmu_irq, \
.end = gp_mmu_irq, \
},
#define MALI_GPU_RESOURCE_PP(pp_addr, pp_irq) \
{ \
.name = "Mali_PP", \
.flags = IORESOURCE_MEM, \
.start = pp_addr, \
.end = pp_addr + 0x1100, \
}, \
{ \
.name = "Mali_PP_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = pp_irq, \
.end = pp_irq, \
}, \
#define MALI_GPU_RESOURCE_PP_WITH_MMU(id, pp_addr, pp_irq, pp_mmu_addr, pp_mmu_irq) \
{ \
.name = "Mali_PP" #id, \
.flags = IORESOURCE_MEM, \
.start = pp_addr, \
.end = pp_addr + 0x1100, \
}, \
{ \
.name = "Mali_PP" #id "_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = pp_irq, \
.end = pp_irq, \
}, \
{ \
.name = "Mali_PP" #id "_MMU", \
.flags = IORESOURCE_MEM, \
.start = pp_mmu_addr, \
.end = pp_mmu_addr + 0x100, \
}, \
{ \
.name = "Mali_PP" #id "_MMU_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = pp_mmu_irq, \
.end = pp_mmu_irq, \
},
#define MALI_GPU_RESOURCE_MMU(mmu_addr, mmu_irq) \
{ \
.name = "Mali_MMU", \
.flags = IORESOURCE_MEM, \
.start = mmu_addr, \
.end = mmu_addr + 0x100, \
}, \
{ \
.name = "Mali_MMU_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = mmu_irq, \
.end = mmu_irq, \
},
#define MALI_GPU_RESOURCE_PMU(pmu_addr) \
{ \
.name = "Mali_PMU", \
.flags = IORESOURCE_MEM, \
.start = pmu_addr, \
.end = pmu_addr + 0x100, \
},
#define MALI_GPU_RESOURCE_DLBU(dlbu_addr) \
{ \
.name = "Mali_DLBU", \
.flags = IORESOURCE_MEM, \
.start = dlbu_addr, \
.end = dlbu_addr + 0x100, \
},
#define MALI_GPU_RESOURCE_BCAST(bcast_addr) \
{ \
.name = "Mali_Broadcast", \
.flags = IORESOURCE_MEM, \
.start = bcast_addr, \
.end = bcast_addr + 0x100, \
},
#define MALI_GPU_RESOURCE_PP_BCAST(pp_addr, pp_irq) \
{ \
.name = "Mali_PP_Broadcast", \
.flags = IORESOURCE_MEM, \
.start = pp_addr, \
.end = pp_addr + 0x1100, \
}, \
{ \
.name = "Mali_PP_Broadcast_IRQ", \
.flags = IORESOURCE_IRQ, \
.start = pp_irq, \
.end = pp_irq, \
}, \
#define MALI_GPU_RESOURCE_PP_MMU_BCAST(pp_mmu_bcast_addr) \
{ \
.name = "Mali_PP_MMU_Broadcast", \
.flags = IORESOURCE_MEM, \
.start = pp_mmu_bcast_addr, \
.end = pp_mmu_bcast_addr + 0x100, \
},
struct mali_gpu_utilization_data
{
unsigned int utilization_gpu; /* Utilization for GP and all PP cores combined, 0 = no utilization, 256 = full utilization */
unsigned int utilization_gp; /* Utilization for GP core only, 0 = no utilization, 256 = full utilization */
unsigned int utilization_pp; /* Utilization for all PP cores combined, 0 = no utilization, 256 = full utilization */
};
struct mali_gpu_device_data
{
/* Dedicated GPU memory range (physical). */
unsigned long dedicated_mem_start;
unsigned long dedicated_mem_size;
/* Shared GPU memory */
unsigned long shared_mem_size;
/* Frame buffer memory to be accessible by Mali GPU (physical) */
unsigned long fb_start;
unsigned long fb_size;
/* Report GPU utilization in this interval (specified in ms) */
unsigned long utilization_interval;
/* Function that will receive periodic GPU utilization numbers */
void (*utilization_callback)(struct mali_gpu_utilization_data *data);
/*
* Mali PMU switch delay.
* Only needed if the power gates are connected to the PMU in a high fanout
* network. This value is the number of Mali clock cycles it takes to
* enable the power gates and turn on the power mesh.
* This value will have no effect if a daisy chain implementation is used.
*/
unsigned long pmu_switch_delay;
};
/** @brief MALI GPU power down using MALI in-built PMU
*
* called to power down all cores
*/
int mali_pmu_powerdown(void);
/** @brief MALI GPU power up using MALI in-built PMU
*
* called to power up all cores
*/
int mali_pmu_powerup(void);
/**
* Pause the scheduling and power state changes of Mali device driver.
* mali_dev_resume() must always be called as soon as possible after this function
* in order to resume normal operation of the Mali driver.
*/
void mali_dev_pause(void);
/**
* Resume scheduling and allow power changes in Mali device driver.
* This must always be called after mali_dev_pause().
*/
void mali_dev_resume(void);
/** @brief Set the desired number of PP cores to use.
*
* The internal Mali PMU will be used, if present, to physically power off the PP cores.
*
* @param num_cores The number of desired cores
* @return 0 on success, otherwise error. -EINVAL means an invalid number of cores was specified.
*/
int mali_perf_set_num_pp_cores(unsigned int num_cores);
#endif
|
