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/*
* Register interface file for Samsung Camera Interface (FIMC-Lite) driver
*
* Copyright (c) 2011 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef FIMC_LITE_REG_H_
#define FIMC_LITE_REG_H_
/* Camera Source size */
#define FLITE_REG_CISRCSIZE 0x00
#define FLITE_REG_CISRCSIZE_SIZE_H(x) ((x) << 16)
#define FLITE_REG_CISRCSIZE_SIZE_V(x) ((x) << 0)
#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14)
#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14)
#define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14)
#define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14)
/* Global control */
#define FLITE_REG_CIGCTRL 0x04
#define FLITE_REG_CIGCTRL_OUT_GSCL_ENABLE (1 << 30)
#define FLITE_REG_CIGCTRL_YUV422_1P (0x1E << 24)
#define FLITE_REG_CIGCTRL_RAW8 (0x2A << 24)
#define FLITE_REG_CIGCTRL_RAW10 (0x2B << 24)
#define FLITE_REG_CIGCTRL_RAW12 (0x2C << 24)
#define FLITE_REG_CIGCTRL_RAW14 (0x2D << 24)
/* User defined formats. x = 0...0xF. */
#define FLITE_REG_CIGCTRL_USER(x) (0x30 + x - 1)
#define FLITE_REG_CIGCTRL_OUT_LOCAL_ENABLE (1 << 22)
#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE (1 << 21)
#define FLITE_REG_CIGCTRL_ODMA_DISABLE (1 << 20)
#define FLITE_REG_CIGCTRL_SWRST_REQ (1 << 19)
#define FLITE_REG_CIGCTRL_SWRST_RDY (1 << 18)
#define FLITE_REG_CIGCTRL_SWRST (1 << 17)
#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR (1 << 15)
#define FLITE_REG_CIGCTRL_INVPOLPCLK (1 << 14)
#define FLITE_REG_CIGCTRL_INVPOLVSYNC (1 << 13)
#define FLITE_REG_CIGCTRL_INVPOLHREF (1 << 12)
#define FLITE_REG_CIGCTRL_IRQ_LASTEN0_ENABLE (0 << 8)
#define FLITE_REG_CIGCTRL_IRQ_LASTEN0_DISABLE (1 << 8)
#define FLITE_REG_CIGCTRL_IRQ_ENDEN0_ENABLE (0 << 7)
#define FLITE_REG_CIGCTRL_IRQ_ENDEN0_DISABLE (1 << 7)
#define FLITE_REG_CIGCTRL_IRQ_STARTEN0_ENABLE (0 << 6)
#define FLITE_REG_CIGCTRL_IRQ_STARTEN0_DISABLE (1 << 6)
#define FLITE_REG_CIGCTRL_IRQ_OVFEN0_ENABLE (0 << 5)
#define FLITE_REG_CIGCTRL_IRQ_OVFEN0_DISABLE (1 << 5)
#define FLITE_REG_CIGCTRL_SELCAM_MIPI (1 << 3)
/* Image Capture Enable */
#define FLITE_REG_CIIMGCPT 0x08
#define FLITE_REG_CIIMGCPT_IMGCPTEN (1 << 31)
#define FLITE_REG_CIIMGCPT_CPT_FREN (1 << 25)
#define FLITE_REG_CIIMGCPT_CPT_FRPTR(x) ((x) << 19)
#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18)
#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18)
#define FLITE_REG_CIIMGCPT_CPT_FRCNT(x) ((x) << 10)
/* Capture Sequence */
#define FLITE_REG_CICPTSEQ 0x0C
#define FLITE_REG_CPT_FRSEQ(x) ((x) << 0)
/* Camera Window Offset */
#define FLITE_REG_CIWDOFST 0x10
#define FLITE_REG_CIWDOFST_WINOFSEN (1 << 31)
#define FLITE_REG_CIWDOFST_CLROVIY (1 << 31)
#define FLITE_REG_CIWDOFST_WINHOROFST(x) ((x) << 16)
#define FLITE_REG_CIWDOFST_HOROFF_MASK (0x1fff << 16)
#define FLITE_REG_CIWDOFST_CLROVFICB (1 << 15)
#define FLITE_REG_CIWDOFST_CLROVFICR (1 << 14)
#define FLITE_REG_CIWDOFST_WINVEROFST(x) ((x) << 0)
#define FLITE_REG_CIWDOFST_VEROFF_MASK (0x1fff << 0)
/* Cmaera Window Offset2 */
#define FLITE_REG_CIWDOFST2 0x14
#define FLITE_REG_CIWDOFST2_WINHOROFST2(x) ((x) << 16)
#define FLITE_REG_CIWDOFST2_WINVEROFST2(x) ((x) << 0)
/* Camera Output DMA Format */
#define FLITE_REG_CIODMAFMT 0x18
#define FLITE_REG_CIODMAFMT_1D_DMA (1 << 15)
#define FLITE_REG_CIODMAFMT_2D_DMA (0 << 15)
#define FLITE_REG_CIODMAFMT_PACK12 (1 << 14)
#define FLITE_REG_CIODMAFMT_NORMAL (0 << 14)
#define FLITE_REG_CIODMAFMT_CRYCBY (0 << 4)
#define FLITE_REG_CIODMAFMT_CBYCRY (1 << 4)
#define FLITE_REG_CIODMAFMT_YCRYCB (2 << 4)
#define FLITE_REG_CIODMAFMT_YCBYCR (3 << 4)
/* Camera Output Canvas */
#define FLITE_REG_CIOCAN 0x20
#define FLITE_REG_CIOCAN_OCAN_V(x) ((x) << 16)
#define FLITE_REG_CIOCAN_OCAN_H(x) ((x) << 0)
/* Camera Output DMA Offset */
#define FLITE_REG_CIOOFF 0x24
#define FLITE_REG_CIOOFF_OOFF_V(x) ((x) << 16)
#define FLITE_REG_CIOOFF_OOFF_H(x) ((x) << 0)
/* Camera Status */
#define FLITE_REG_CISTATUS 0x40
#define FLITE_REG_CISTATUS_MIPI_VVALID (1 << 22)
#define FLITE_REG_CISTATUS_MIPI_HVALID (1 << 21)
#define FLITE_REG_CISTATUS_MIPI_DVALID (1 << 20)
#define FLITE_REG_CISTATUS_ITU_VSYNC (1 << 14)
#define FLITE_REG_CISTATUS_ITU_HREFF (1 << 13)
#define FLITE_REG_CISTATUS_OVFIY (1 << 10)
#define FLITE_REG_CISTATUS_OVFICB (1 << 9)
#define FLITE_REG_CISTATUS_OVFICR (1 << 8)
#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW (1 << 7)
#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND (1 << 6)
#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART (1 << 5)
#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND (1 << 4)
#define FLITE_REG_CISTATUS_IRQ_CAM (1 << 0)
#define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4)
/* Camera Status2 */
#define FLITE_REG_CISTATUS2 0x44
#define FLITE_REG_CISTATUS2_LASTCAPEND (1 << 1)
#define FLITE_REG_CISTATUS2_FRMEND (1 << 0)
/* Camera Status3 */
#define FLITE_REG_CISTATUS3 0x48
#define FLITE_REG_CISTATUS3_FRAMECNT_BEFORE (0x3F << 7)
#define FLITE_REG_CISTATUS3_FRAMECNT_PRESENT (0x3F << 0)
/* Camera Status4 */
#define FLITE_REG_CISTATUS4 0x4C
#define FLITE_REG_CISTATUS4_VSYNC_CNT 0x0
/* Qos Threshold */
#define FLITE_REG_CITHOLD 0xF0
#define FLITE_REG_CITHOLD_W_QOS_EN (1 << 30)
#define FLITE_REG_CITHOLD_WTH_QOS(x) ((x) << 0)
/* Camera General Purpose */
#define FLITE_REG_CIGENERAL 0xFC
#define FLITE_REG_CIGENERAL0_MASK 0x3
#define FLITE_REG_CIGENERAL0_CAM_A (0 << 0)
#define FLITE_REG_CIGENERAL0_CAM_B (1 << 0)
#define FLITE_REG_CIGENERAL0_CAM_C (2 << 0)
/* Camera Frame Count Sequence */
#define FLITE_REG_CIFCNTSEQ 0x100
/* Version Info */
#define FLITE_REG_CIVERINFO 0x104
/* Camera Output DMA Address (0~31)*/
#define FLITE_REG_CIOSA(n) (n ? \
0x1FC + (n * 0x4) : \
0x30)
#endif /* FIMC_LITE_REG_H */
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