blob: 0a9f7f99ec52998dc05fe41618d8ef4f151ae409 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
/*
* include/asm-arm/arch-ks8695/regs-timer.h
*
* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
* Copyright (C) 2006 Simtec Electronics
*
* KS8695 - Timer registers and bit definitions.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef KS8695_TIMER_H
#define KS8695_TIMER_H
#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
/*
* Timer registers
*/
#define KS8695_TMCON (0x00) /* Timer Control Register */
#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
/* Timer Control Register */
#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
/* Timer0 Timeout Counter Register */
#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
#endif
|
