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author | Yiran Wang <yiran@google.com> | 2015-06-23 15:33:17 -0700 |
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committer | Yiran Wang <yiran@google.com> | 2015-06-29 10:56:28 -0700 |
commit | 1d9fec7937f45dde5e04cac966a2d9a12f2fc15a (patch) | |
tree | 3fbcd18a379a05fd6d43491a107e1f36bc61b185 /gcc-4.9/gcc/config/aarch64/aarch64.c | |
parent | f378ebf14df0952eae870c9865bab8326aa8f137 (diff) | |
download | toolchain_gcc-1d9fec7937f45dde5e04cac966a2d9a12f2fc15a.zip toolchain_gcc-1d9fec7937f45dde5e04cac966a2d9a12f2fc15a.tar.gz toolchain_gcc-1d9fec7937f45dde5e04cac966a2d9a12f2fc15a.tar.bz2 |
Synchronize with google/gcc-4_9 to r224707 (from r214835)
Change-Id: I3d6f06fc613c8f8b6a82143dc44b7338483aac5d
Diffstat (limited to 'gcc-4.9/gcc/config/aarch64/aarch64.c')
-rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.c b/gcc-4.9/gcc/config/aarch64/aarch64.c index 2ff6c7c..029c54c 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64.c +++ b/gcc-4.9/gcc/config/aarch64/aarch64.c @@ -3874,7 +3874,7 @@ aarch64_print_operand_address (FILE *f, rtx x) switch (GET_CODE (x)) { case PRE_INC: - asm_fprintf (f, "[%s,%d]!", reg_names [REGNO (addr.base)], + asm_fprintf (f, "[%s,%d]!", reg_names [REGNO (addr.base)], GET_MODE_SIZE (aarch64_memory_reference_mode)); return; case POST_INC: @@ -5152,7 +5152,6 @@ aarch64_parse_cpu (void) if (strlen (cpu->name) == len && strncmp (cpu->name, str, len) == 0) { selected_cpu = cpu; - selected_tune = cpu; aarch64_isa_flags = selected_cpu->flags; if (ext != NULL) @@ -5248,9 +5247,8 @@ aarch64_override_options (void) gcc_assert (selected_cpu); - /* The selected cpu may be an architecture, so lookup tuning by core ID. */ if (!selected_tune) - selected_tune = &all_cores[selected_cpu->core]; + selected_tune = selected_cpu; aarch64_tune_flags = selected_tune->flags; aarch64_tune = selected_tune->core; @@ -7194,7 +7192,7 @@ aarch64_expand_vector_init (rtx target, rtx vals) x = XVECEXP (vals, 0, 0); if (!CONST_INT_P (x) && !CONST_DOUBLE_P (x)) n_var = 1, one_var = 0; - + for (i = 1; i < n_elts; ++i) { x = XVECEXP (vals, 0, i); @@ -8642,6 +8640,10 @@ aarch64_cannot_change_mode_class (enum machine_mode from, #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \ aarch64_autovectorize_vector_sizes +#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV +#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \ + aarch64_atomic_assign_expand_fenv + /* Section anchor support. */ #undef TARGET_MIN_ANCHOR_OFFSET |