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authorRabin Vincent <rabin.vincent@stericsson.com>2010-12-08 17:18:46 +0530
committerLinus Walleij <linus.walleij@stericsson.com>2010-12-08 13:38:02 +0100
commit20e218a77fc0b0576817b6b204fe5b9391a5b209 (patch)
treece021b3176ed4af3705e20b7db8887f2be0e0761
parent22039b7cc54a636f80434e9b149fcdec148c4cb9 (diff)
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ux500: fix 5500 PER6 clock rate
The DB5500 PER6 clock rate is the same as the DB8500 one, i.e. 133.33 MHz. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
-rw-r--r--arch/arm/mach-ux500/clock.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 598902d..00e9ab3 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -578,7 +578,6 @@ int __init clk_init(void)
/* Clock tree for U5500 not implemented yet */
clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
- clk_per6clk.rate = 26000000;
clk_uartclk.rate = 36360000;
clk_sdmmcclk.rate = 99900000;
}