diff options
Diffstat (limited to 'arch/arm/mach-exynos/include/mach')
51 files changed, 5138 insertions, 2711 deletions
diff --git a/arch/arm/mach-exynos/include/mach/bcm4752.h b/arch/arm/mach-exynos/include/mach/bcm4752.h new file mode 100644 index 0000000..832b4d7 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/bcm4752.h @@ -0,0 +1,26 @@ +/* linux/arm/arch/mach-exynos/include/mach/bcm47511.h + * + * Platform data Header for BCM47511(GPS) driver. + * + * Copyright (c) 2011 Samsung Electronics + * Minho Ban <mhban@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _BCM4752_H +#define _BCM4752_H + +struct bcm4752_platform_data { + unsigned int regpu; /* Power */ + unsigned int uart_rxd; /* Start gpio number of uart */ + /* Below are machine dependant */ + unsigned int gps_cntl; /* Request 26MHz CP clock */ + const char *reg32khz; /* regulator id for 32KHz clk */ +}; + +#endif /* _BCM47511_H */ + + diff --git a/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h b/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h index fabd1e8..f8f377d 100644 --- a/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h +++ b/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h @@ -24,6 +24,7 @@ #define TIMINGROW_OFFSET 0x34 +#define PRIME_DMC_MAX_THRESHOLD 30 #define EXYNOS4412_DMC_MAX_THRESHOLD 30 #define EXYNOS4212_DMC_MAX_THRESHOLD 30 diff --git a/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h b/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h deleted file mode 100644 index fe00bd1..0000000 --- a/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h +++ /dev/null @@ -1,93 +0,0 @@ -/* linux/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - BUSFreq support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BUSFREQ_H -#define __ASM_ARCH_BUSFREQ_H __FILE__ - -#include <linux/notifier.h> -#include <linux/earlysuspend.h> - -#include <mach/ppmu.h> - -#define MAX_LOAD 100 -#define LOAD_HISTORY_SIZE 5 -#define DIVIDING_FACTOR 10000 - -#define TIMINGROW_OFFSET 0x34 - -enum busfreq_level_idx { - LV_0, - LV_1, - LV_2, - LV_3, - LV_INT_END, - LV_MIF_END = LV_3, -}; - -struct opp; -struct device; -struct busfreq_table; - -struct busfreq_data { - bool use; - struct device *dev[PPMU_TYPE_END]; - struct delayed_work worker; - unsigned long curr_freq[PPMU_TYPE_END]; - unsigned long max_freq[PPMU_TYPE_END]; - unsigned long min_freq[PPMU_TYPE_END]; - struct regulator *vdd_reg[PPMU_TYPE_END]; - unsigned int sampling_rate; - struct kobject *busfreq_kobject; - struct busfreq_table *table[PPMU_TYPE_END]; - unsigned long long time_in_state[PPMU_TYPE_END][LV_INT_END]; - unsigned long long last_time[PPMU_TYPE_END]; - unsigned int load_history[PPMU_END][LOAD_HISTORY_SIZE]; - int index; - - struct notifier_block exynos_buspm_notifier; - struct notifier_block exynos_reboot_notifier; - struct notifier_block exynos_request_notifier; - struct early_suspend busfreq_early_suspend_handler; - struct attribute_group busfreq_attr_group; - int (*init) (struct device *dev, struct busfreq_data *data); - void (*monitor) (struct busfreq_data *data, struct opp **mif_opp, - struct opp **int_opp); - void (*target) (struct busfreq_data *data, enum ppmu_type type, int index); - unsigned int (*get_int_volt) (unsigned long freq); - int (*get_table_index) (unsigned long freq, enum ppmu_type type); - void (*busfreq_prepare) (int index); - void (*busfreq_post) (int index); - void (*busfreq_suspend) (void); - void (*busfreq_resume) (void); - - /* Dividers calculated at boot/probe-time */ - unsigned int lex_divtable[LV_INT_END]; - unsigned int r0x_divtable[LV_INT_END]; - unsigned int r1x_divtable[LV_INT_END]; - unsigned int cdrex_divtable[LV_MIF_END]; - unsigned int cdrex2_divtable[LV_MIF_END]; -}; - -struct busfreq_table { - unsigned int idx; - unsigned int mem_clk; - unsigned int volt; - unsigned int clk_topdiv; - unsigned int clk_dmc0div; - unsigned int clk_dmc1div; -}; - -void exynos_request_apply(unsigned long freq); -unsigned long step_down(struct busfreq_data *data, enum ppmu_type type, int step); - -int exynos5250_init(struct device *dev, struct busfreq_data *data); -#endif /* __ASM_ARCH_BUSFREQ_H */ diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h index 9ef27df..a799365 100644 --- a/arch/arm/mach-exynos/include/mach/cpufreq.h +++ b/arch/arm/mach-exynos/include/mach/cpufreq.h @@ -23,9 +23,13 @@ enum cpufreq_level_index { }; enum busfreq_level_request { - BUS_L0, /* MEM 400MHz BUS 200MHz */ - BUS_L1, /* MEM 267MHz BUS 160MHz */ - BUS_L2, /* MEM 133MHz BUS 133MHz */ + BUS_L0, /* MEM 400MHz BUS 266MHz */ + BUS_L1, /* MEM 400MHz BUS 200MHz */ + BUS_L2, /* MEM 267MHz BUS 200MHz */ + BUS_L3, /* MEM 267MHz BUS 160MHz */ + BUS_L4, /* MEM 160MHz BUS 160MHz */ + BUS_L5, /* MEM 133MHz BUS 133MHz */ + BUS_L6, /* MEM 100MHz BUS 100MHz */ BUS_LEVEL_END, }; diff --git a/arch/arm/mach-exynos/include/mach/gc1-jack.h b/arch/arm/mach-exynos/include/mach/gc1-jack.h new file mode 100644 index 0000000..ce915fd --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gc1-jack.h @@ -0,0 +1,25 @@ +/* + * gc1-jack.h - Jack Management of GC1 Project + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __GC1_JACK_H__ +#define __GC1_JACK_H__ __FILE__ + +void gc1_jack_init(void); +extern void set_wm1811_micbias2(bool on); + +#endif /* __GC1_JACK_H__ */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-exynos4.h b/arch/arm/mach-exynos/include/mach/gpio-exynos4.h index 93b5b7b..3d7368d 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-exynos4.h +++ b/arch/arm/mach-exynos/include/mach/gpio-exynos4.h @@ -205,8 +205,9 @@ enum exynos4212_gpio_number { #include <asm-generic/gpio.h> #if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_MACH_SLP_MIDAS) \ - || defined(CONFIG_MACH_SLP_PQ) \ - || defined(CONFIG_MACH_SLP_PQ_LTE) + || defined(CONFIG_MACH_SLP_PQ) \ + || defined(CONFIG_MACH_SLP_PQ_LTE)\ + || defined(CONFIG_MACH_SLP_T0_LTE) #include "gpio-midas.h" #endif @@ -214,14 +215,10 @@ enum exynos4212_gpio_number { #include "gpio-naples.h" #endif -#if defined(CONFIG_MACH_U1) +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) #include "gpio-u1.h" #endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -#include "gpio-u1camera.h" -#endif - #if defined(CONFIG_MACH_Q1_BD) #include "gpio-q1.h" #endif @@ -238,4 +235,7 @@ enum exynos4212_gpio_number { #include "gpio-p8.h" #endif +#if defined(CONFIG_MACH_P8LTE) +#include "gpio-p8lte.h" +#endif #endif /* __ASM_ARCH_GPIO_EXYNOS4_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1ctc.h b/arch/arm/mach-exynos/include/mach/gpio-iron.h index e7c17d0..a874815 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1ctc.h +++ b/arch/arm/mach-exynos/include/mach/gpio-iron.h @@ -10,20 +10,13 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BOOT_MODE EXYNOS4_GPX0(3) +#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) +#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) +#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) +#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) #define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) #define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) #define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) #define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) @@ -34,23 +27,33 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) +#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) +#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) #define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) +/* keys */ +#define GPIO_KBR_0 EXYNOS4_GPX2(2) +#define GPIO_KBR_1 EXYNOS4_GPX2(4) +#define GPIO_KBR_2 EXYNOS4_GPX3(0) +#define GPIO_KBR_3 EXYNOS4_GPX3(3) +#define GPIO_KBR_4 EXYNOS4_GPX3(4) + +#define GPIO_KBC_0 EXYNOS4_GPL2(3) +#define GPIO_KBC_1 EXYNOS4_GPL2(4) +#define GPIO_KBC_2 EXYNOS4_GPL2(5) +#define GPIO_KBC_3 EXYNOS4_GPL2(6) +#define GPIO_KBC_4 EXYNOS4_GPL2(7) + /* Sensors & NFC*/ #define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) +#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPF0(0) +#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPF0(1) #define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) #define GPIO_ACC_INT EXYNOS4_GPX0(0) - #define GPIO_GYRO_DE EXYNOS4_GPL2(0) #define GPIO_GPS_nRST EXYNOS4_GPL2(1) #define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) @@ -62,26 +65,16 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPM4(4) #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY0(1) -#define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) -#define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ -#define GPIO_DET_35 EXYNOS4_GPX0(1) +#define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(3) #define GPIO_PMU_RST EXYNOS4_GPX3(2) @@ -89,8 +82,12 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) #define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_EN EXYNOS4_GPL0(3) + #define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) #define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_HALL_SW EXYNOS4_GPX3(7) + #define GPIO_BT_EN EXYNOS4_GPL0(6) #define GPIO_BT_WAKE EXYNOS4_GPX3(1) @@ -129,17 +126,14 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) #define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) +#define GPIO_3_TOUCH_EN EXYNOS4_GPC1(0) #define GPIO_PWM0 EXYNOS4_GPD0(0) #define GPIO_PWM1 EXYNOS4_GPD0(1) #define GPIO_PWM2 EXYNOS4_GPD0(2) #define GPIO_PWM3 EXYNOS4_GPD0(3) -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - #define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) #define GPIO_WLAN_EN_AF 1 #define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) @@ -157,54 +151,47 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) #define GPIO_WLAN_SDIO_D3_AF 2 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) +#define GPIO_USB_SEL EXYNOS4212_GPJ1(4) -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) #define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - #define GPIO_OTG_EN EXYNOS4_GPF0(7) -#define GPIO_OLED_ID EXYNOS4_GPF1(0) #define GPIO_ISP_RESET EXYNOS4_GPF1(3) #define GPIO_FUEL_SCL EXYNOS4_GPF1(4) #define GPIO_FUEL_SDA EXYNOS4_GPF1(5) #define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#define GPIO_S_LED_I2C_SCL +#define GPIO_S_LED_I2C_SDA #define GPIO_OLED_DET EXYNOS4_GPF3(0) +#define GPIO_LCD_SEL EXYNOS4_GPF2(6) +#define GPIO_LCD_OE EXYNOS4_GPF2(7) +#define GPIO_TSP_SEL EXYNOS4_GPF2(7) + #define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) #define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#if defined(CONFIG_REGULATOR_LP8720) +#define GPIO_FOLDER_PMIC_EN EXYNOS4_GPL0(4) +#define GPIO_FOLDER_PMIC_SDA EXYNOS4_GPF0(4) +#define GPIO_FOLDER_PMIC_SCL EXYNOS4_GPF0(6) + +#if defined(CONFIG_MACH_GRANDE) +#define GPIO_SUB_PMIC_EN EXYNOS4_GPF0(2) +#define GPIO_SUB_PMIC_SDA EXYNOS4_GPF0(7) +#define GPIO_SUB_PMIC_SCL EXYNOS4_GPF1(0) +#endif +#endif + /* Definitions for Sii 9244B0 */ #define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) #define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) #define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) #define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) + #define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) #define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) @@ -212,26 +199,20 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) #define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - #define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) #define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - #define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_UP EXYNOS4_GPX1(3) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(5) +#define GPIO_HOLD EXYNOS4_GPX0(5) #define GPIO_OK_KEY EXYNOS4_GPX3(5) - +#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) /*system_rev == 11*/ +#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3) /*system_rev >= 15*/ #define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - #define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) #define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) #define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) @@ -239,10 +220,21 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_FM_INT EXYNOS4_GPX1(3) +/* Modem Interface GPIOs - M0 HSIC */ +#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_PHONE_ON EXYNOS4212_GPM1(1) +#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) +#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) +#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_CP_RST EXYNOS4_GPX3(2) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) +#if defined(CONFIG_GSM_MODEM_ESC6270) /* Definitions for DPRAM */ #define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) #define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) @@ -255,33 +247,18 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) #define GPIO_DPRAM_BUSY EXYNOS4_GPY1(2) -/* Definitions for CMC221 */ -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_AP_CP_INT EXYNOS4_GPF2(2) - -#define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) -#define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) -#define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) -#define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) -#define GPIO_USB_HUB_CONNECT EXYNOS4212_GPV3(5) -#define GPIO_USB_BOOT_EN EXYNOS4212_GPV3(7) - -#define GPIO_BOOT_SW_SEL EXYNOS4212_GPV3(6) - -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) - -#define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) - #define GPIO_CP_MSM_RST EXYNOS4_GPL2(4) -#define GPIO_CP_MSM_PMU_RST EXYNOS4_GPX3(2) -#define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) - -#define GPIO_MSM_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ - -#define GPIO_MSM_DPRAM_INT EXYNOS4_GPX2(0) -#define MSM_DPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ - +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(6) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(5) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(4) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(12) +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX1(7) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(15) +#endif + +/* DUMMY GPIOS */ +#define GPIO_HDMI_HPD EXYNOS4_GPA1(4) +#define GPIO_HDMI_EN EXYNOS4_GPA1(4) +#define GPIO_V_BUS_INT EXYNOS4_GPA1(4) #endif /* __MACH_GPIO_C1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-midas.h b/arch/arm/mach-exynos/include/mach/gpio-midas.h index 894c1cf..2ed73f2 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-midas.h +++ b/arch/arm/mach-exynos/include/mach/gpio-midas.h @@ -13,40 +13,43 @@ #ifndef __ASM_ARCH_GPIO_MIDAS_H #define __ASM_ARCH_GPIO_MIDAS_H __FILE__ -#if defined(CONFIG_MACH_MIDAS_01_BD) || defined(CONFIG_GPIO_MIDAS_01_BD) +/* MACH_MIDAS_01_BD nor MACH_MIDAS_01_BD nomore exists + but SLP use GPIO_MIDAS_01_BD, GPIO_MIDAS_02_BD */ +#if defined(CONFIG_GPIO_MIDAS_01_BD) #include "gpio-rev01-midas.h" -#elif defined(CONFIG_MACH_MIDAS_02_BD) || defined(CONFIG_GPIO_MIDAS_02_BD) +#elif defined(CONFIG_GPIO_MIDAS_02_BD) #include "gpio-rev02-midas.h" -#elif defined(CONFIG_MACH_M0_GRANDECTC) +#elif defined(CONFIG_MACH_IRON) +#include "gpio-iron.h" +#elif defined(CONFIG_MACH_GRANDE) #include "gpio-rev00-m0grandectc.h" #elif defined(CONFIG_MACH_M0_CTC) #include "gpio-rev00-m0ctc.h" #elif defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) #include "gpio-rev00-m0.h" -#elif defined(CONFIG_MACH_M3) -#include "gpio-rev00-m3.h" #elif defined(CONFIG_MACH_C1) && !defined(CONFIG_TARGET_LOCALE_KOR) #include "gpio-rev00-c1.h" -#elif defined(CONFIG_MACH_C1CTC) -#include "gpio-rev00-c1ctc.h" -#elif (defined(CONFIG_MACH_C1VZW) || defined(CONFIG_MACH_SLP_PQ_LTE)) && \ - !defined(CONFIG_TARGET_LOCALE_KOR) +#elif defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) +#include "gpio-rev03-c1kor.h" +#elif defined(CONFIG_MACH_SLP_PQ_LTE) && !defined(CONFIG_TARGET_LOCALE_KOR) #include "gpio-rev00-c1vzw.h" -#elif defined(CONFIG_MACH_JENGA) -#include "gpio-rev00-jenga.h" -#elif defined(CONFIG_MACH_S2PLUS) -#include "gpio-rev00-s2plus.h" +#elif defined(CONFIG_MACH_M3) +#include "gpio-rev00-m3.h" #elif defined(CONFIG_GPIO_NAPLES_00_BD) #include "gpio-rev00-naples.h" -#elif (defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)) && \ - defined(CONFIG_TARGET_LOCALE_KOR) -#include "gpio-rev03-c1kor.h" #elif defined(CONFIG_MACH_P4NOTE) #include "gpio-rev00-p4notepq.h" #elif defined(CONFIG_MACH_GC1) #include "gpio-rev00-gc1.h" -#elif defined(CONFIG_MACH_T0) +#elif defined(CONFIG_MACH_T0_CHN_CTC) +#include "gpio-rev00-t0ctc.h" +#elif defined(CONFIG_MACH_T0_CHN_CU_DUOS) || \ + defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#include "gpio-rev00-t0cu-duos.h" +#elif defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_SLP_T0_LTE) #include "gpio-rev00-t0.h" +#elif defined(CONFIG_MACH_BAFFIN) +#include "gpio-rev00-baffin.h" #endif #endif /* __ASM_ARCH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-p2.h b/arch/arm/mach-exynos/include/mach/gpio-p2.h index 986bed3..ab65a4d 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-p2.h +++ b/arch/arm/mach-exynos/include/mach/gpio-p2.h @@ -129,6 +129,8 @@ #define IRQ_SUSPEND_REQUEST IRQ_EINT11 #define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 +#define GPIO_LCD_BACKLIGHT_PWM EXYNOS4_GPD0(1) + #define EXYNOS4_GPD_0_0_TOUT_0 (0x2 << 0) #if defined(CONFIG_FB_MDNIE_PWM) #define EXYNOS4_GPD_0_1_TOUT_1 (0x3 << 4) diff --git a/arch/arm/mach-exynos/include/mach/gpio-p8lte.h b/arch/arm/mach-exynos/include/mach/gpio-p8lte.h new file mode 100644 index 0000000..18458a1 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gpio-p8lte.h @@ -0,0 +1,265 @@ +#ifndef __MACH_GPIO_P8LTE_H +#define __MACH_GPIO_P8LTE_H __FILE__ + +#define GPIO_XMMC0_CDn EXYNOS4_GPK0(2) + +#define GPIO_PS_ALS_SDA EXYNOS4_GPK2(2) +#define GPIO_PS_ALS_SCL EXYNOS4_GPK3(2) + +#define GPIO_GYRO_INT EXYNOS4_GPX0(0) +#define GPIO_PS_VOUT EXYNOS4_GPL0(6) + +#define GPIO_BUCK1_EN_A EXYNOS4_GPX0(5) +#define GPIO_BUCK1_EN_B EXYNOS4_GPX0(6) +#define GPIO_BUCK2_EN EXYNOS4_GPL0(0) +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) + + +#define GPIO_VOL_UP EXYNOS4_GPX2(0) +#define GPIO_VOL_DOWN EXYNOS4_GPX2(1) + +#define GPIO_nPOWER EXYNOS4_GPX2(7) +/* +#define VT_CAM_SDA_18V EXYNOS4_GPC1(0) +#define VT_CAM_SCL_18V EXYNOS4_GPC1(2) + +#define GPIO_CAM_SENSOR_CORE EXYNOS4210_GPE2(5) +#define GPIO_VT_CAM_15V EXYNOS4210_GPE2(2) +#define GPIO_CAM_IO_EN EXYNOS4210_GPE2(1) +*/ +#define CODEC_VT_SDA_18V EXYNOS4_GPC1(3) +#define CODEC_VT_SCL_18V EXYNOS4_GPC1(4) + +/*#define GPIO_ISP_RESET EXYNOS4_GPY3(7)*/ +#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) +#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) + +#define GPIO_MASSMEM_EN_LEVEL 0 + +#define GPIO_CAM_MOVIE_EN EXYNOS4_GPL0(1) +#define GPIO_CAM_FLASH_EN EXYNOS4_GPL0(2) + +#define GPIO_TSP_LDO_ON EXYNOS4_GPY0(1) +/* +#define GPIO_CAM_FLASH_SET EXYNOS4210_GPE0(2) +#define GPIO_TSP_RST EXYNOS4_GPL0(5) +#define GPIO_TSP_INT EXYNOS4_GPX0(4) +*/ +#define GPIO_TSP_SDA EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL EXYNOS4_GPA1(3) +#define GPIO_TSP_VENDOR EXYNOS4_GPY5(6) +#define GPIO_TSP_INT_18V EXYNOS4_GPL2(5) + +#define GPIO_LCD_RST EXYNOS4_GPF0(1) +#define GPIO_LCD_EN EXYNOS4_GPL0(7) +#define GPIO_LCD_LDO_EN EXYNOS4_GPK1(1) +#define GPIO_UART_SEL1 EXYNOS4_GPY4(7) +#define GPIO_UART_SEL2 EXYNOS4_GPY0(0) +/* +#define GPIO_CAM_PCLK EXYNOS4210_GPJ0(0) +#define GPIO_CAM_VSYNC EXYNOS4210_GPJ0(1) +#define GPIO_CAM_HSYNC EXYNOS4210_GPJ0(2) +*/ +#define GPIO_CAM_MCLK EXYNOS4210_GPJ1(3) +/* +#define GPIO_CAM_AVDD_EN EXYNOS4210_GPJ1(4) + +#define GPIO_CAM_VGA_nSTBY EXYNOS4_GPL2(0) +#define GPIO_CAM_VGA_nRST EXYNOS4_GPL2(1) +*/ +#define GPIO_2M_nSTBY EXYNOS4_GPL2(0) +#define GPIO_2M_nRST EXYNOS4_GPL2(1) +#define GPIO_3M_nSTBY EXYNOS4_GPL2(2) +#define GPIO_3M_nRST EXYNOS4_GPL2(7) + +#define GPIO_DET_35 EXYNOS4_GPX3(2) +#define GPIO_DET_35_AF 0xF + +#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) +#define GPIO_EAR_SEND_END_AF 0xF + +#define GPIO_GPS_nRST EXYNOS4_GPY5(4) +#define GPIO_GPS_PWR_EN EXYNOS4_GPY5(5) + +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_RXD_AF 2 + +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_TXD_AF 2 + +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_CTS_AF 2 + +#define GPIO_BT_RTS EXYNOS4_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD EXYNOS4_GPA0(4) +#define GPIO_GPS_RXD_AF 2 + +#define GPIO_GPS_TXD EXYNOS4_GPA0(5) +#define GPIO_GPS_TXD_AF 2 + +#define GPIO_GPS_CTS EXYNOS4_GPA0(6) +#define GPIO_GPS_CTS_AF 2 + +#define GPIO_GPS_RTS EXYNOS4_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +/*#define GPIO_ALC_nRST EXYNOS4_GPX1(7)*/ + +#define GPIO_DOUBLE_RR EXYNOS4_GPL2(3) +/*#define GPIO_2MIC_EN EXYNOS4_GPL2(5)*/ + +#define GPIO_CURR_ADJ EXYNOS4_GPY5(7) +#define GPIO_TA_EN EXYNOS4_GPY6(6) +#define GPIO_TA_nCHG EXYNOS4_GPX0(4) +#define GPIO_TA_nCONNECTED EXYNOS4_GPX0(1) +/* +//#define GPIO_CHG_SDA_28V EXYNOS4_GPB(2) +//#define GPIO_CHG_SCL_28V EXYNOS4_GPB(3) +*/ +#define GPIO_IPC_RXD EXYNOS4_GPA1(4) +#define GPIO_IPC_RXD_AF 2 + +#define GPIO_IPC_TXD EXYNOS4_GPA1(5) +#define GPIO_IPC_TXD_AF 2 + +/*dpram setting for VIA CP Modem*/ + +#define GPIO_PHONE_ON EXYNOS4_GPC1(1) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) + +#define GPIO_VIA_PS_HOLD_OFF EXYNOS4_GPX2(6) +#define GPIO_CP_AP_DPRAM_INT EXYNOS4_GPX3(5) +#define GPIO_VIA_DPRAM_INT_N EXYNOS4210_GPE0(3) +#define GPIO_CP_RST EXYNOS4_GPX2(5) + +/*#define GPIO_LVDS_NSHDN EXYNOS4_GPX1(5)*/ +#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) + +#define IRQ_PHONE_ACTIVE IRQ_EINT14 +#define IRQ_SUSPEND_REQUEST IRQ_EINT11 +#define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 + +#define EXYNOS4_GPD_0_0_TOUT_0 (0x2 << 0) +#define EXYNOS4_GPD_0_1_TOUT_1 (0x2 << 4) +#define EXYNOS4_GPD_0_2_TOUT_2 (0x2 << 8) +#define EXYNOS4_GPD_0_3_TOUT_3 (0x2 << 12) + +#define GPIO_WLAN_EN EXYNOS4_GPL1(2) +#define GPIO_WLAN_EN2 EXYNOS4_GPK1(0) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_nRST EXYNOS4_GPL0(4) + +/* CSR8811 Project(Alan.Ko) 2011.07.02 */ +/*#define GPIO_BT_EN EXYNOS4_GPL0(4)*/ +/* CSR8811 Project(Alan.Ko) end */ + +#define GPIO_BT_nRST EXYNOS4_GPY6(1) + +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX1(0) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX1(1) +#define GPIO_BT_HOST_WAKE_AF 0xF + +/* CSR8811 Project(Alan.Ko) 2011.07.02 */ +/*#define GPIO_BT_WAKE EXYNOS4_GPX3(1)*/ +/* CSR8811 Project(Alan.Ko) end */ + +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_HW_REV0 EXYNOS4_GPY5(0) +#define GPIO_HW_REV1 EXYNOS4_GPY5(1) +#define GPIO_HW_REV2 EXYNOS4_GPY5(2) +#define GPIO_HW_REV3 EXYNOS4_GPY5(3) + +#define GPIO_HDMI_EN1 EXYNOS4_GPL1(1) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_MHL_WAKE_UP_AF S3C_GPIO_SFN(0xF) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + +/*IR*/ +#define GPIO_IRDA_EN EXYNOS4_GPX3(0) +#define GPIO_IRDA_nINT EXYNOS4_GPB(4) + +#define GPIO_SIM_DETECT EXYNOS4_GPX0(3) + +#define GPIO_MSENSE_INT EXYNOS4_GPX2(2) +#define GPIO_DOCK_INT EXYNOS4_GPX2(4) + +#define GPIO_USB_OTG_EN EXYNOS4_GPX3(3) +#define GPIO_USB_SEL1 EXYNOS4_GPY6(4) +#define GPIO_USB_SEL2 EXYNOS4_GPY4(6) +#define GPIO_USB_SEL3 EXYNOS4_GPY4(5) +#define GPIO_IF_CON_SENSE EXYNOS4_GPY3(3) +#define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) + +#define GPIO_MSENSOR_MHL_SDA_28V EXYNOS4_GPD0(2) +#define GPIO_MSENSOR_MHL_SDA_AF 0x3 +#define GPIO_MSENSOR_MHL_SCL_28V EXYNOS4_GPD0(3) +#define GPIO_MSENSOR_MHL_SCL_AF 0x3 +#define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) +#define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN +#define GPIO_USB_HUB_I2C_SDA EXYNOS4_GPY3(4) +#define GPIO_USB_HUB_I2C_SCL EXYNOS4_GPY3(5) +#define GPIO_USB_HUB_RST EXYNOS4_GPY3(6) +#endif + +#define GPIO_AP_HDMI_SDA GPIO_MSENSOR_MHL_SDA_28V +#define GPIO_AP_HDMI_SDA_AF GPIO_MSENSOR_MHL_SDA_AF +#define GPIO_AP_HDMI_SCL GPIO_MSENSOR_MHL_SCL_28V +#define GPIO_AP_HDMI_SCL_AF GPIO_MSENSOR_MHL_SCL_AF +#define GPIO_AP_SDA_18V GPIO_MHL_SDA_18V +#define GPIO_AP_SCL_18V GPIO_MHL_SCL_18V + +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +/*#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP)*/ + +#define GPIO_MIC_BIAS_EN EXYNOS4_GPY6(7) +#define GPIO_EAR_MIC_BIAS_EN EXYNOS4_GPL2(6) + +#define GPIO_REMOTE_SENSE_IRQ EXYNOS4_GPX0(2) + +#define GPIO_ACCESSORY_EN EXYNOS4_GPL1(0) +#define GPIO_ACCESSORY_INT EXYNOS4_GPX1(7) +#define GPIO_ACCESSORY_OUT_5V EXYNOS4_GPY3(1) + + +#define GPIO_220_PMIC_PWRON EXYNOS4_GPY6(2) +#define GPIO_LTE_PS_HOLD_OFF EXYNOS4_GPL0(5) +#define GPIO_CMC_RST EXYNOS4_GPY6(3) + +#define GPIO_LTE_ACTIVE EXYNOS4_GPX1(2) + +#define GPIO_LTE2AP_STATUS EXYNOS4_GPX1(4) +#define GPIO_AP2LTE_STATUS EXYNOS4_GPY4(3) +#define GPIO_LTE2AP_WAKEUP EXYNOS4_GPX1(3) +#define GPIO_AP2LTE_WAKEUP EXYNOS4_GPY4(4) + +#define IRQ_LTE_ACTIVE IRQ_EINT10 +#define IRQ_LTE2AP_WAKEUP IRQ_EINT11 + + +#endif /* __MACH_GPIO_P8LTE_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1vzw.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-baffin.h index 605b70c..15e3ff6 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1vzw.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-baffin.h @@ -1,5 +1,5 @@ -#ifndef __MACH_GPIO_C1VZW_H -#define __MACH_GPIO_C1VZW_H __FILE__ +#ifndef __MACH_GPIO_BAFFIN_H +#define __MACH_GPIO_BAFFIN_H __FILE__ #include <mach/gpio.h> @@ -15,17 +15,6 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FM_I2S_DI EXYNOS4_GPC0(3) #define GPIO_FM_I2S_DO EXYNOS4_GPC0(4) -#ifdef CONFIG_AUDIENCE_ES305 -#define GPIO_ES305_WAKEUP EXYNOS4_GPC0(4) -#define GPIO_ES305_RESET EXYNOS4_GPF2(5) -#endif - -#define GPIO_FM34_PWDN EXYNOS4_GPL0(3) -#define GPIO_FM34_RESET EXYNOS4_GPY1(3) -#define GPIO_FM34_BYPASS EXYNOS4_GPY1(2) -#define GPIO_FM34_SCL EXYNOS4212_GPM4(0) -#define GPIO_FM34_SDA EXYNOS4212_GPM4(1) - #define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) #define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) #define GPIO_PMIC_SDA EXYNOS4_GPB(2) @@ -43,16 +32,15 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) #define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM0(7) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) +#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) +#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) @@ -82,7 +70,8 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) #define GPIO_BARO_INT EXYNOS4_GPF0(5) -#define GPIO_TF_EN EXYNOS4_GPY0(1) +#define GPIO_TF_EN EXYNOS4_GPY2(0) + #define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) #define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) #define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) @@ -96,10 +85,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_DET_35 EXYNOS4_GPX0(1) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPC0(3) -#define GPIO_THIRD_MIC_BIAS_EN EXYNOS4_GPF2(0) - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) #define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) @@ -143,11 +129,25 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FLM_TXD EXYNOS4_GPA1(5) #define GPIO_FLM_TXD_AF 2 +#ifdef CONFIG_FM34_WE395 +#define GPIO_FM34_PWDN EXYNOS4_GPL0(3) +#define GPIO_FM34_RESET EXYNOS4_GPL0(1) +#define GPIO_FM34_BYPASS EXYNOS4_GPL0(2) +#define GPIO_FM34_RESET_05 EXYNOS4_GPY1(3) +#define GPIO_FM34_BYPASS_05 EXYNOS4_GPY1(2) +#define GPIO_FM34_SCL EXYNOS4212_GPM4(0) +#define GPIO_FM34_SDA EXYNOS4212_GPM4(1) +#endif + #define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) #define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) + + #define GPIO_HDMI_EN EXYNOS4_GPL0(4) + #define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) -#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(0) +#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(0) #define GPIO_PWM0 EXYNOS4_GPD0(0) #define GPIO_PWM1 EXYNOS4_GPD0(1) @@ -183,8 +183,6 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_TA_EN EXYNOS4_GPL2(2) -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - #define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) #define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) #define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) @@ -197,9 +195,12 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FUEL_SCL EXYNOS4_GPF1(4) #define GPIO_FUEL_SDA EXYNOS4_GPF1(5) +#define GPIO_LCD_BL_EN EXYNOS4_GPF0(5) #define GPIO_MLCD_RST EXYNOS4_GPF2(1) #define GPIO_UART_SEL EXYNOS4_GPF2(3) +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) #define GPIO_LTE_VIA_UART_SEL EXYNOS4212_GPJ0(6) +#endif #define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) #define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) #define GPIO_OLED_DET EXYNOS4_GPF3(0) @@ -235,16 +236,15 @@ extern void midas_config_sleep_gpio_table(void); #define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) #define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) #define GPIO_HDMI_HPD EXYNOS4_GPX3(7) #define GPIO_nPOWER EXYNOS4_GPX2(7) #define GPIO_OK_KEY EXYNOS4_GPX3(5) -#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) - -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) /* rev0.9 ~ */ -#define GPIO_WPC_INT EXYNOS4_GPX3(0) +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) #define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) @@ -279,8 +279,13 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_LTE_ACTIVE EXYNOS4_GPX1(6) #define LTE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) #define GPIO_CMC_IDPRAM_INT_00 EXYNOS4_GPX3(3) #define CMC_IDPRAM_INT_IRQ_00 IRQ_EINT(27) /* IRQ of GPX3[3] */ +#else +#define GPIO_CMC_IDPRAM_INT_00 EXYNOS4_GPX2(0) +#define CMC_IDPRAM_INT_IRQ_00 IRQ_EINT(16) /* IRQ of GPX2[0] */ +#endif #define GPIO_CMC_IDPRAM_INT_01 EXYNOS4_GPX2(0) #define CMC_IDPRAM_INT_IRQ_01 IRQ_EINT(16) /* IRQ of GPX2[0] */ @@ -291,17 +296,22 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_AP2CMC_INT2 EXYNOS4_GPX1(2) + /* Definitions for an USB HUB for CMC221 */ #define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) #define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) +/* Definitions for PDA_ACTIVE for CMC221 & CBP7.2 */ +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) /* Definitions for CBP7.2 */ #define GPIO_CBP_PMIC_PWRON EXYNOS4212_GPM0(6) #define GPIO_CBP_PS_HOLD_OFF EXYNOS4212_GPM1(0) #define GPIO_CBP_CP_RST EXYNOS4_GPF2(4) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) #define GPIO_CBP_PHONE_ACTIVE EXYNOS4_GPX1(3) #define CBP_PHONE_ACTIVE_IRQ IRQ_EINT(11) @@ -312,5 +322,17 @@ extern void midas_config_sleep_gpio_table(void); #define CBP_DPRAM_INT_IRQ_01 IRQ_EINT(29) /* IRQ of GPX3[5] */ #define GPIO_CBP_BOOT_SEL EXYNOS4212_GPM0(5) +#endif + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#define GPIO_TDMB_EN EXYNOS4_GPC0(0) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) +#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) +#define GPIO_TDMB_INT_AF 0xf +#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#endif -#endif /* __MACH_GPIO_C1VZW_H */ +#endif /* __MACH_GPIO_BAFFIN_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h index 827f1f9..fc4004c 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h @@ -36,17 +36,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) #define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) #define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPJ0(6) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) -#if 1 #define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) #define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#else -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) -#endif #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) @@ -76,7 +70,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) #define GPIO_BARO_INT EXYNOS4_GPF0(5) -#define GPIO_TF_EN EXYNOS4_GPY0(1) +#define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) #define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h index 04e3fb8..57f75a6 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h @@ -66,21 +66,27 @@ extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); /* Sensors */ #define GPIO_ACC_INT EXYNOS4_GPX0(0) +#define GPIO_GYRO_INT EXYNOS4_GPF0(3) +#define GPIO_GYRO_DE EXYNOS4_GPL2(0) + #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) #define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPJ0(5) /* Sensors */ #define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_DET_35 EXYNOS4_GPX0(1) +#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) #define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) +#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPJ0(3) #define GPIO_PMU_RST EXYNOS4_GPX3(2) @@ -258,6 +264,8 @@ extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); #define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) #define GPIO_CP_RST EXYNOS4_GPX3(2) +#define GPIO_SIM_DETECT EXYNOS4_GPX3(5) + #define GPIO_FM_RST EXYNOS4_GPC1(1) #else @@ -299,8 +307,10 @@ extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); #define GPIO_PLAY_KEY EXYNOS4_GPX1(4) #define GPIO_S1_KEY EXYNOS4_GPX2(0) #define GPIO_S2_KEY EXYNOS4_GPX2(1) -#define GPIO_WIDE_KEY EXYNOS4_GPX2(2) -#define GPIO_TELE_KEY EXYNOS4_GPX3(3) +#define GPIO_TELE_KEY EXYNOS4_GPX2(2) +#define GPIO_WIDE_KEY EXYNOS4_GPX3(3) +#define GPIO_FAST_TELE_KEY EXYNOS4_GPX1(4) +#define GPIO_FAST_WIDE_KEY EXYNOS4_GPX0(4) #define GPIO_FM_INT_REV15 EXYNOS4_GPX1(4) #define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h deleted file mode 100644 index 42d1f08..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h +++ /dev/null @@ -1,265 +0,0 @@ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) -#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) -#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) - -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) - -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) -#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) - -/* Sensors & NFC*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) - -#define GPIO_GYRO_INT EXYNOS4_GPF0(3) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY0(1) -#define GPIO_NFC_SCL_18V EXYNOS4_GPZ(6) -#define GPIO_NFC_SDA_18V EXYNOS4_GPZ(5) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ - -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM4(5) -#define GPIO_MIC_BIAS_EN_00 EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4212_GPM4(6) -#define GPIO_SUB_MIC_BIAS_EN_00 EXYNOS4_GPF2(0) -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPM4(7) -#define GPIO_EAR_MIC_BIAS_EN_00 EXYNOS4212_GPJ0(2) - - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) - -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) - -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - -#define GPIO_BT_EN EXYNOS4_GPL0(6) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) - -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) - -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) - -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) -#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) - -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) - - -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) - -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) - -/* Modem Interface GPIOs - M0 HSIC */ -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) -#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_CP_RST EXYNOS4_GPX3(2) - -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_INT EXYNOS4_GPX1(3) - -#endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h index 13fdb3d..cd778f2 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h @@ -20,8 +20,8 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_PMIC_SDA EXYNOS4_GPB(2) #define GPIO_PMIC_SCL EXYNOS4_GPB(3) -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) #define GPIO_ADC_INT EXYNOS4_GPX2(4) /* rev0.0, 0.1 */ #define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) @@ -71,6 +71,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4_GPC1(1) #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h index 2b36a60..e8cc1aa 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h @@ -16,8 +16,8 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_PMIC_SDA EXYNOS4_GPB(2) #define GPIO_PMIC_SCL EXYNOS4_GPB(3) -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) #define GPIO_ADC_INT EXYNOS4_GPX2(4) #define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) @@ -52,8 +52,10 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ACC_INT EXYNOS4_GPX0(0) #define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#if !defined(CONFIG_MACH_M0_DUOSCTC) #define GPIO_GPS_nRST EXYNOS4_GPL2(1) #define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +#endif #define GPIO_GYRO_INT EXYNOS4_GPF0(3) #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) @@ -62,6 +64,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPM4(4) +#endif #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) @@ -83,7 +88,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) #define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) - +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(3) +#endif #define GPIO_PMU_RST EXYNOS4_GPX3(2) #define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) @@ -166,7 +173,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ISP_TXD EXYNOS4212_GPM4(5) #define GPIO_ISP_RXD EXYNOS4212_GPM4(6) +#if !defined(CONFIG_MACH_M0_DUOSCTC) #define GPIO_TA_EN EXYNOS4_GPL2(2) +#endif #define GPIO_MHL_SEL EXYNOS4_GPL0(3) @@ -183,7 +192,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FUEL_SDA EXYNOS4_GPF1(5) #define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#else #define GPIO_UART_SEL EXYNOS4_GPF2(3) +#endif #define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) #define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) #define GPIO_OLED_DET EXYNOS4_GPF3(0) @@ -241,11 +254,17 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) #define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) - +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_FM_RST EXYNOS4_GPC1(0) +#define GPIO_FM_INT_REV15 EXYNOS4_GPX0(4) +#define GPIO_FM_INT_REV07 EXYNOS4_GPX0(4) +#define GPIO_FM_INT EXYNOS4_GPX0(4) +#else #define GPIO_FM_RST EXYNOS4_GPC1(1) #define GPIO_FM_INT_REV15 EXYNOS4_GPX1(3) #define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) #define GPIO_FM_INT EXYNOS4_GPX1(3) +#endif #define GPIO_FM_MIC_SW EXYNOS4_GPL0(3) /* Definitions for DPRAM */ @@ -269,10 +288,16 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) + +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_USB_HUB_CONNECT EXYNOS4_GPF1(0) /* dummy */ +#define GPIO_USB_BOOT_EN EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL EXYNOS4_GPF1(1) +#else #define GPIO_USB_HUB_CONNECT EXYNOS4212_GPV3(5) #define GPIO_USB_BOOT_EN EXYNOS4212_GPV3(7) - #define GPIO_BOOT_SW_SEL EXYNOS4212_GPV3(6) +#endif /* for revesion 06 higher */ #define GPIO_USB_BOOT_EN_REV06 EXYNOS4_GPF2(2) @@ -280,6 +305,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) #define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) #define GPIO_CP_MSM_RST EXYNOS4_GPL2(4) @@ -287,10 +313,20 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) #define GPIO_MSM_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ +#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) #define GPIO_MSM_DPRAM_INT EXYNOS4_GPX2(0) -#define MSM_DPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ - +#define MSM_DPRAM_INT_IRQ IRQ_EINT(16) + +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_CP2_MSM_PWRON EXYNOS4_GPL2(2) +#define GPIO_CP2_MSM_RST EXYNOS4_GPL2(1) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) + +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(4) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(12) +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX3(5) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(29) +#endif #endif /* __MACH_GPIO_C1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h index e5c96b4..17d9586 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h @@ -19,7 +19,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) #define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) +#if defined(CONFIG_MACH_GRANDE) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPJ0(1) +#else #define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) +#endif #define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) @@ -29,10 +33,28 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) -#define GPIO_ACC_INT EXYNOS4_GPX0(0) +/* keys */ +#define GPIO_KBR_0 EXYNOS4_GPX2(2) +#define GPIO_KBR_1 EXYNOS4_GPX2(4) +#define GPIO_KBR_2 EXYNOS4_GPX3(0) +#define GPIO_KBR_3 EXYNOS4_GPX3(3) +#define GPIO_KBR_4 EXYNOS4_GPX3(4) -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#define GPIO_KBC_0 EXYNOS4_GPL2(3) +#define GPIO_KBC_1 EXYNOS4_GPL2(4) +#define GPIO_KBC_2 EXYNOS4_GPL2(5) +#define GPIO_KBC_3 EXYNOS4_GPL2(6) +#define GPIO_KBC_4 EXYNOS4_GPL2(7) + + +/* Sensors & NFC*/ +#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) +#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPF0(0) +#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPF0(1) +#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) +#define GPIO_ACC_INT EXYNOS4_GPX0(0) +#define GPIO_GYRO_DE EXYNOS4_GPL2(0) #define GPIO_GYRO_INT EXYNOS4_GPF0(3) #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) #define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) @@ -40,14 +62,16 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPM4(4) #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) - +#define GPIO_3G_DET EXYNOS4_GPX0(6) #define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(3) #define GPIO_PMU_RST EXYNOS4_GPX3(2) @@ -55,8 +79,12 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) #define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_EN EXYNOS4_GPL0(3) + #define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) #define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_HALL_SW EXYNOS4_GPX3(7) + #define GPIO_BT_EN EXYNOS4_GPL0(6) #define GPIO_BT_WAKE EXYNOS4_GPX3(1) @@ -93,6 +121,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FLM_TXD EXYNOS4_GPA1(5) #define GPIO_FLM_TXD_AF 2 +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) +#define GPIO_3_TOUCH_EN EXYNOS4_GPC1(0) + #define GPIO_PWM0 EXYNOS4_GPD0(0) #define GPIO_PWM1 EXYNOS4_GPD0(1) #define GPIO_PWM2 EXYNOS4_GPD0(2) @@ -133,18 +166,29 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_LCD_SEL EXYNOS4_GPF2(6) #define GPIO_LCD_OE EXYNOS4_GPF2(7) +#define GPIO_TSP_SEL EXYNOS4_GPF2(7) #define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) #define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#if defined(CONFIG_REGULATOR_LP8720) +#define GPIO_FOLDER_PMIC_EN EXYNOS4_GPL0(4) +#define GPIO_FOLDER_PMIC_SDA EXYNOS4_GPF0(4) +#define GPIO_FOLDER_PMIC_SCL EXYNOS4_GPF0(6) + +#if defined(CONFIG_MACH_GRANDE) +#define GPIO_SUB_PMIC_EN EXYNOS4_GPF0(2) +#define GPIO_SUB_PMIC_SDA EXYNOS4_GPF0(7) +#define GPIO_SUB_PMIC_SCL EXYNOS4_GPF1(0) +#endif +#endif + /* Definitions for Sii 9244B0 */ #define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) #define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) #define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) #define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_VOL_UP EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) #define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) #define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) @@ -156,13 +200,14 @@ extern void midas_config_sleep_gpio_table(void); #define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) #define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_UP EXYNOS4_GPX1(3) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(5) +#define GPIO_HOLD EXYNOS4_GPX0(5) #define GPIO_OK_KEY EXYNOS4_GPX3(5) #define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) /*system_rev == 11*/ #define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3) /*system_rev >= 15*/ #define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - #define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) #define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) @@ -187,26 +232,27 @@ extern void midas_config_sleep_gpio_table(void); /* Definitions for CMC221 */ #define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) #define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_AP_CP_INT EXYNOS4_GPF2(2) +/* #define GPIO_AP_CP_INT EXYNOS4_GPF2(2) */ #define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) #define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) #define GPIO_USB_HUB_CONNECT EXYNOS4212_GPV3(5) -#define GPIO_USB_BOOT_EN EXYNOS4212_GPV3(7) +#define GPIO_USB_BOOT_EN EXYNOS4_GPF2(2) -#define GPIO_BOOT_SW_SEL EXYNOS4212_GPV3(6) +#define GPIO_BOOT_SW_SEL EXYNOS4_GPF2(5) /* for revesion 06 higher */ -#define GPIO_USB_BOOT_EN_REV06 EXYNOS4212_GPV3(7) -#define GPIO_BOOT_SW_SEL_REV06 EXYNOS4212_GPV3(6) +#define GPIO_USB_BOOT_EN_REV06 EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL_REV06 EXYNOS4_GPF2(5) #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) -#define GPIO_CP_MSM_RST EXYNOS4_GPL2(4) +#define GPIO_CP_MSM_PWRON EXYNOS4212_GPM1(1) +#define GPIO_CP_MSM_RST EXYNOS4_GPL2(1) #define GPIO_CP_MSM_PMU_RST EXYNOS4_GPX3(2) #define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) @@ -216,12 +262,28 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSM_DPRAM_INT EXYNOS4_GPX2(0) #define MSM_DPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ -#define GPIO_CP2_MSM_PWRON EXYNOS4_GPL2(1) -#define GPIO_CP2_MSM_RST EXYNOS4_GPL2(2) - -/* DUMP GPIOS */ +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(6) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(5) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(4) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(12) +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX1(7) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(15) + +#if defined(CONFIG_SIM_DETECT) +#define GPIO_CP_SIM_DETECT EXYNOS4_GPX0(1) +#define CP_SIM_DETECT_IRQ IRQ_EINT(1) +#define GPIO_ESC_SIM_DETECT EXYNOS4_GPX3(6) +#define ESC_SIM_DETECT_IRQ IRQ_EINT(30) +#endif + +/* DUMMY GPIOS */ #define GPIO_HDMI_HPD EXYNOS4_GPA1(4) #define GPIO_HDMI_EN EXYNOS4_GPA1(4) #define GPIO_V_BUS_INT EXYNOS4_GPA1(4) +#if defined(CONFIG_SIM_SLOT_SWITCH) +#define GPIO_UIM_SIM_SEL EXYNOS4212_GPM0(7) +#endif + #endif /* __MACH_GPIO_C1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h index cd3bc9c..1e7626c 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h @@ -1,291 +1,264 @@ -#ifndef __MACH_GPIO_M3_H -#define __MACH_GPIO_M3_H __FILE__ +#ifndef __MACH_GPIO_C2_H +#define __MACH_GPIO_C2_H __FILE__ + #include <mach/gpio.h> extern void midas_config_gpio_table(void); extern void midas_config_sleep_gpio_table(void); -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYNOS4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYNOS4_GPC0(2) -#define GPIO_FM_I2S_DI EXYNOS4_GPC0(3) -#define GPIO_FM_I2S_DO EXYNOS4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) - -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) - -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) -#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) - -/* Sensors & NFC*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) - -#define GPIO_GYRO_INT EXYNOS4_GPF0(3) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY0(1) -#define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) -#define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ - -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) - -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) - -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - -#define GPIO_BT_EN EXYNOS4_GPL0(6) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) - -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) - -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) -#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) -#define GPIO_OLED_DET EXYNOS4_GPF3(0) - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) - -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) - -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) - -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) - -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) - -/* Definitions for DPRAM */ -#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) -#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) -#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) -#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) -#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) - -/* Definitions for CMC221 */ -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_AP_CP_INT EXYNOS4_GPF2(2) -#define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) -#define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) -#define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) -#define CP_CMC221_CPU_RST EXYNOS4_GPL2(4) -#define CP_CMC221_PMIC_PWRON EXYNOS4_GPL2(5) -#define GPIO_CMC2AP_INT1_18V EXYNOS4_GPX0(5) -#define GPIO_AP2CMC_DP_INT3_18V EXYNOS4_GPX3(2) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) - -#define GPIO_LTE_ACTIVE EXYNOS4_GPX1(6) -#define LTE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ - -#define GPIO_CMC_IDPRAM_INT EXYNOS4_GPX2(0) -#define CMC_IDPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ - -#define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) - -#define GPIO_CMC2AP_STATUS EXYNOS4_GPX0(5) -#define GPIO_AP2CMC_WAKEUP EXYNOS4_GPX1(2) - -#define ACTIVE_STATE_HSIC EXYNOS4_GPF1(1) -#define MDM_LTE_ACTIVE EXYNOS4_GPF2(0) -#define PDA_ACTIVE EXYNOS4_GPF1(6) -#define AP2MDM_PMIC_RESET_N EXYNOS4_GPL2(4) -#define MDM2AP_STATUS EXYNOS4212_GPM1(1) -#define AP2MDM_STATUS EXYNOS4212_GPM2(4) -#define MDM2AP_HSIC_READY EXYNOS4_GPX0(4) -#define AP2MDM_HSIC_READY EXYNOS4_GPX0(5) -#define AP2MDM_ERRFATAL EXYNOS4_GPX1(0) -#define MDM2AP_ERRFATAL EXYNOS4_GPX1(1) -#define MDM_DUMP_INT EXYNOS4_GPX1(2) - -#endif /* __MACH_GPIO_M3_H */ +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_RTS EXYNOS4_GPA0(3) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPA0(6) +#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPA0(7) +#else +#define GPIO_NFC_SDA_18V EXYNOS4_GPA0(6) +#define GPIO_NFC_SCL_18V EXYNOS4_GPA0(7) +#endif + +#define GPIO_AP_RXD_18V EXYNOS4_GPA1(0) +#define GPIO_AP_TXD_18V EXYNOS4_GPA1(1) +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) + +#define GPIO_CODEC_SDA_18V EXYNOS4_GPB(0) +#define GPIO_CODEC_SCL_18V EXYNOS4_GPB(1) +#define GPIO_MHL_DSDA_18V EXYNOS4_GPB(2) +#define GPIO_MHL_DSCL_18V EXYNOS4_GPB(3) +#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) +#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) +#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) +#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) + +#define GPIO_LCD_22V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 GPIO_LCD_22V_EN + +#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(0) +#define GPIO_MODEM_BOOT_MODE EXYNOS4_GPD0(1) +#define GPIO_PMIC_SDA EXYNOS4_GPD0(2) +#define GPIO_PMIC_SCL EXYNOS4_GPD0(3) + +#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(0) +#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(1) +#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) +#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) + +#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) +#define GPIO_GYRO_INT EXYNOS4_GPF0(3) +#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) +#define GPIO_BARO_INT EXYNOS4_GPF0(5) +#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) +#define GPIO_OTG_EN EXYNOS4_GPF0(7) + +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) + +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) + +#define GPIO_OLED_DET EXYNOS4_GPF3(0) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) + +#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) +#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) +#define GPIO_WM8994_LDO GPIO_CODEC_LDO_EN +#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) +#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) + +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) +#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) + +#define GPIO_NAND_CLK EXYNOS4_GPK0(0) +#define GPIO_NAND_CMD EXYNOS4_GPK0(1) +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) +#define GPIO_NAND_D0 EXYNOS4_GPK0(3) +#define GPIO_NAND_D1 EXYNOS4_GPK0(4) +#define GPIO_NAND_D2 EXYNOS4_GPK0(5) +#define GPIO_NAND_D3 EXYNOS4_GPK0(6) + +#define GPIO_NAND_D4 EXYNOS4_GPK1(3) +#define GPIO_NAND_D5 EXYNOS4_GPK1(4) +#define GPIO_NAND_D6 EXYNOS4_GPK1(5) +#define GPIO_NAND_D7 EXYNOS4_GPK1(6) + +#define GPIO_T_FLASH_CLK EXYNOS4_GPK2(0) +#define GPIO_T_FLASH_CMD EXYNOS4_GPK2(1) +#define GPIO_T_FLASH_D0 EXYNOS4_GPK2(3) +#define GPIO_T_FLASH_D1 EXYNOS4_GPK2(4) +#define GPIO_T_FLASH_D2 EXYNOS4_GPK2(5) +#define GPIO_T_FLASH_D3 EXYNOS4_GPK2(6) + +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) + +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#ifdef CONFIG_TARGET_LOCALE_EUR +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) +#endif +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_BT_EN EXYNOS4_GPL0(6) + +#define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_LED_VDD_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_EN GPIO_LED_VDD_EN +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) +#else +#define GPIO_LED_VDD_EN EXYNOS4212_GPM0(0) +#define GPIO_3_TOUCH_EN GPIO_LED_VDD_EN +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#endif + +#define GPIO_HW_REV0 EXYNOS4212_GPM1(2) +#define GPIO_HW_REV1 EXYNOS4212_GPM1(3) +#define GPIO_HW_REV2 EXYNOS4212_GPM1(4) +#define GPIO_HW_REV3 EXYNOS4212_GPM1(5) +#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) + +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) +#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) + +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) + +#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) +#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) + +#define GPIO_ACC_INT EXYNOS4_GPX0(0) +#define GPIO_OK_KEY EXYNOS4_GPX0(1) +#define GPIO_RGB_INT_N EXYNOS4_GPX0(2) +#define GPIO_PS_ALS_INT GPIO_RGB_INT_N +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) + +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) + +#define GPIO_VOL_UP EXYNOS4_GPX2(2) +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) +#else +#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) +#endif + +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) +#define GPIO_nPOWER EXYNOS4_GPX2(7) + +#define GPIO_WPC_INT EXYNOS4_GPX3(0) +#define GPIO_BT_WAKE EXYNOS4_GPX3(1) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) +#define GPIO_T_FLASH_DETECT EXYNOS4_GPX3(4) +#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + +#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY1(0) +#define GPIO_BENSE_SCL_18V EXYNOS4_GPY1(1) + +#define GPIO_TF_EN EXYNOS4_GPY2(0) +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4_GPY2(3) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) +#else +#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) +#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#endif + +#define GPIO_MM_I2S_CLK EXYNOS5_GPZ(0) +#define GPIO_MM_I2S_SYNC EXYNOS5_GPZ(2) +#define GPIO_MM_I2S_DI EXYNOS5_GPZ(3) +#define GPIO_MM_I2S_DO EXYNOS5_GPZ(4) + + +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_HOST_WAKE_AF 0xF +#define GPIO_WLAN_SDIO_CLK_AF 2 +#define GPIO_WLAN_SDIO_CMD_AF 2 +#define GPIO_WLAN_SDIO_D0_AF 2 +#define GPIO_WLAN_SDIO_D1_AF 2 +#define GPIO_WLAN_SDIO_D2_AF 2 +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define IRQ_BT_HOST_WAKE IRQ_EINT(22) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) + +#if defined(CONFIG_FELICA) +#define FELICA_GPIO_I2C_SDA EXYNOS4_GPY2(4) +#define FELICA_GPIO_I2C_SCL EXYNOS4_GPY2(5) +#define FELICA_UART3RX EXYNOS4_GPA1(4) +#define FELICA_GPIO_RFS EXYNOS4_GPL2(6) +#define FELICA_GPIO_PON EXYNOS4_GPL2(7) +#define FELICA_GPIO_INT EXYNOS4_GPX1(7) +#endif + +#if defined(CONFIG_ISDBT) +#define GPIO_ISDBT_RST_N EXYNOS4_GPC0(0) +#define GPIO_ISDBT_EN EXYNOS4_GPC0(2) +#define GPIO_ISDBT_INT EXYNOS4_GPC0(4) +#define GPIO_ISDBT_IRQ gpio_to_irq(GPIO_ISDBT_INT) +#define GPIO_ISDBT_INT_AF 0xf +#define GPIO_ISDBT_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_ISDBT_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_ISDBT_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_ISDBT_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +#endif /* __MACH_GPIO_C2_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h deleted file mode 100644 index b5dc8a7..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) -#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) -#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) - -#define GPIO_3M_nRST EXYNOS4_GPL1(1) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) -#define GPIO_3M_nSTBY EXYNOS4212_GPM0(6) -#define GPIO_2M_nRST EXYNOS4212_GPM1(6) - -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) - -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_2M_nSTBY EXYNOS4212_GPM4(3) -#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) - -/* 30pin Accessory */ -/* -#define GPIO_ACCESSORY_CHECK EXYNOS4_GPE0(4) -#define GPIO_ACCESSORY_EN EXYNOS4_GPL2(6) -#define GPIO_ACCESSORY_OUT_5V EXYNOS4_GPY4(4) -*/ -#define GPIO_ACCESSORY_INT EXYNOS4_GPX1(3) -#define GPIO_DOCK_INT EXYNOS4_GPX0(4) - -/* Sensors & NFC*/ -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPL0(2) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPL0(1) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) - -#define GPIO_GYRO_INT EXYNOS4_GPX0(6) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - -#define GPIO_MSENSOR_INT EXYNOS4212_GPM4(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_NFC_SCL_18V EXYNOS4_GPZ(6) -#define GPIO_NFC_SDA_18V EXYNOS4_GPZ(5) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(6) /*tmp*/ -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ - -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM0(0) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) -#define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) - -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) - -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) -#define GPIO_TSP_LDO_ON EXYNOS4_GPL0(3) -#define GPIO_TSP_RST EXYNOS4_GPL0(5) - -#define GPIO_PEN_PDCT_18V EXYNOS4_GPC1(0) -#define GPIO_PEN_LDO_EN EXYNOS4_GPC1(1) -#define GPIO_PEN_IRQ_18V EXYNOS4_GPC1(2) -#define GPIO_PEN_SDA_28V EXYNOS4_GPC1(3) -#define GPIO_PEN_SCL_28V EXYNOS4_GPC1(4 - -#define GPIO_BT_EN EXYNOS4_GPL0(6) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_3_TOUCH_SCL EXYNOS4212_GPM0(0) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL2(3) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4_GPC1(3) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) - -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) - -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - -#define GPIO_WLAN_EN EXYNOS4212_GPM3(5) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_USB_SEL0 EXYNOS4_GPY0(4) -#define GPIO_USB_SEL1 EXYNOS4_GPY0(5) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) - -/* charger */ -#define GPIO_CHG_SDA EXYNOS4212_GPM2(0) -#define GPIO_CHG_SCL EXYNOS4212_GPM2(1) -#define GPIO_TA_EN EXYNOS4_GPY1(3) -#define GPIO_TA_nCHG EXYNOS4_GPL2(1) -#define GPIO_TA_nCONNECTED EXYNOS4_GPX1(4) - -/* adc */ -#define GPIO_ADC_SCL EXYNOS4212_GPM4(0) -#define GPIO_ADC_SDA EXYNOS4212_GPM4(1) -#define GPIO_ADC_INT EXYNOS4_GPX0(1) - -/* fuelgauge */ -#define GPIO_FUEL_SCL EXYNOS4_GPY0(3) -#define GPIO_FUEL_SDA EXYNOS4_GPY0(2) -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_IF_CON_SENSE EXYNOS4_GPY4(3) - -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPL2(7) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) -#define GPIO_OLED_DET EXYNOS4_GPF3(0) - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPX2(4) -#define GPIO_BUCK3_SEL EXYNOS4_GPX2(0) -#define GPIO_BUCK4_SEL EXYNOS4_GPX2(1) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) - -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) /* rev0.9 ~ */ -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) - - -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPM4(4) -#define GPIO_WM8994_LDO EXYNOS4212_GPM4(4) - -/* Modem Interface GPIOs - M0 HSIC */ -#if !defined(CONFIG_SEC_MODEM_M0_TD) -#define GPIO_ACTIVE_STATE EXYNOS4_GPL0(0) -#define GPIO_PDA_ACTIVE EXYNOS4_GPL1(0) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) -#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_CP_RST EXYNOS4_GPX3(2) - -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#else - -/* Modem Interface GPIOs - M0 SPI */ -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_AP_CP_INT1 EXYNOS4_GPX0(5) -#define GPIO_AP_CP_INT2 EXYNOS4_GPX3(5) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_IPC_MRDY EXYNOS4_GPX0(4) -#define GPIO_IPC_SRDY EXYNOS4_GPX1(0) -#define GPIO_IPC_SUB_MRDY EXYNOS4_GPX3(2) -#define GPIO_IPC_SUB_SRDY EXYNOS4_GPX1(1) - -#define GPIO_CP_RST EXYNOS4_GPF1(1) -#define GPIO_CP_REQ_RESET EXYNOS4_GPF1(1) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_SUSPEND_REQUEST EXYNOS4_GPF1(1) -#define GPIO_ISP_INT EXYNOS4_GPF1(1) -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) - -#define GPIO_FM_RST EXYNOS4_GPC1(0) - -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_PHONE_ACTIVE IRQ_EINT14 -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_IPC_SUB_SRDY IRQ_EINT9 -#define IRQ_CP_DUMP_INT IRQ_EINT10 -#endif - -#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX1(3) - -#define GPIO_FM_INT_REV15 EXYNOS4_GPX1(4) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_MIC_SW EXYNOS4_GPL0(3) - -#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) -#define GPIO_TDMB_EN EXYNOS4_GPL0(0) -#define GPIO_TDMB_INT EXYNOS4_GPF0(2) -#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) -#define GPIO_TDMB_INT_AF 0xf -#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) -#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) -#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) -#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) -#endif - -#if defined(CONFIG_FB_S5P_S6C1372) -#define GPIO_LCD_EN EXYNOS4_GPC0(1) -#define GPIO_LED_BACKLIGHT_PWM EXYNOS4_GPD0(1) -#define GPIO_LED_BACKLIGHT_RESET EXYNOS4212_GPM0(1) -#define GPIO_LVDS_NSHDN EXYNOS4212_GPM0(5) -#endif - -#endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h index 3c62331..c44ac94 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h @@ -74,8 +74,10 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_PS_ALS_SCL_28V EXYNOS4_GPL0(1) #define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#if !defined(CONFIG_QC_MODEM) #define GPIO_GPS_nRST EXYNOS4_GPL2(1) #define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +#endif #define GPIO_GYRO_INT EXYNOS4_GPX0(6) #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) @@ -147,13 +149,19 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) #define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) #define GPIO_TSP_LDO_ON EXYNOS4212_GPM4(5) -#define GPIO_TSP_RST EXYNOS4_GPL0(5) +#define GPIO_TSP_RST EXYNOS4212_GPM0(4) +#define GPIO_TSP_LDO_ON1 EXYNOS4_GPB(5) +#define GPIO_TSP_LDO_ON2 EXYNOS4_GPB(7) #define GPIO_PEN_PDCT_18V EXYNOS4_GPC1(0) #define GPIO_PEN_LDO_EN EXYNOS4_GPC1(1) #define GPIO_PEN_IRQ_18V EXYNOS4_GPC1(2) #define GPIO_PEN_SDA_28V EXYNOS4_GPC1(3) #define GPIO_PEN_SCL_28V EXYNOS4_GPC1(4) +#define GPIO_S_PEN_IRQ EXYNOS4_GPX1(5) +#if defined(CONFIG_QC_MODEM) +#define GPIO_PEN_FWE0 EXYNOS4_GPA0(5) +#endif #define GPIO_nPOWER EXYNOS4_GPX2(7) #define GPIO_VOL_DOWN EXYNOS4_GPX2(2) @@ -187,7 +195,14 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ISP_TXD EXYNOS4212_GPM4(5) #define GPIO_ISP_RXD EXYNOS4212_GPM4(6) +#if defined(CONFIG_IR_REMOCON_GPIO) #define GPIO_IRDA_CONTROL EXYNOS4_GPL0(3) +#elif defined(CONFIG_IR_REMOCON_MC96) +#define GPIO_IRDA_WAKE EXYNOS4_GPL0(3) +#define GPIO_IRDA_IRQ EXYNOS4_GPM0(6) +#define GPIO_IRDA_SDA EXYNOS4_GPY0(0) +#define GPIO_IRDA_SCL EXYNOS4_GPY0(1) +#endif #define GPIO_MHL_SDA_1_8V EXYNOS4_GPY2(2) #define GPIO_MHL_SCL_1_8V EXYNOS4_GPY2(3) @@ -201,6 +216,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_USB_SEL1 EXYNOS4_GPY0(5) #define GPIO_USB_SEL_CP EXYNOS4212_GPM0(7) #define GPIO_UART_SEL EXYNOS4_GPL2(7) +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) +#define GPIO_UART_SEL2 EXYNOS4212_GPJ0(0) +#endif /* charger */ #define GPIO_CHG_SDA EXYNOS4212_GPM2(0) @@ -231,9 +249,15 @@ extern void midas_config_sleep_gpio_table(void); /* Definitions for Sii 9244B0 */ #define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#if !defined(CONFIG_QC_MODEM) #define GPIO_BUCK2_SEL EXYNOS4_GPX2(4) #define GPIO_BUCK3_SEL EXYNOS4_GPX2(0) #define GPIO_BUCK4_SEL EXYNOS4_GPX2(1) +#else +#define GPIO_BUCK2_SEL EXYNOS4_GPL2(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPL2(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPX2(4) +#endif #define GPIO_MHL_RST EXYNOS4_GPF3(4) #define GPIO_MHL_INT EXYNOS4_GPF3(5) #define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) @@ -333,4 +357,26 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_LVDS_NSHDN EXYNOS4212_GPM0(5) #endif +#if defined(CONFIG_QC_MODEM) +/* Modem Interface GPIOs - MDM */ +#define GPIO_MODEM_BOOT_MODE EXYNOS4_GPD0(1) +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPL0(0) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPL1(0) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPC0(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPC0(0) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPC0(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4_GPC0(3) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4212_GPM3(4) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX2(0) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX2(1) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ +#endif + #endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h deleted file mode 100644 index 3423451..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h +++ /dev/null @@ -1,715 +0,0 @@ -#if 1 -/* - * Gpio-rev00-s2plus.h - * - * 2011. 12.21 Sexykyu - * - * S2Plus H/W REV00 Board Gpio Setup - * - */ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_DUMMP EXYNOS4212_GPM3(4) - -/*********************** GPA0 Block *********/ - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - - -/*********************** GPA1 Block *********/ -#define GPIO_AP_RXD EXYNOS4_GPA1(0) -#define GPIO_AP_TXD EXYNOS4_GPA1(1) - -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - - -/*********************** GPB Block *********/ - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPB(1) - -#define GPIO_NFC_SDA_18V EXYNOS4_GPB(2) -#define GPIO_NFC_SCL_18V EXYNOS4_GPB(3) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -/*********************** GPC0 Block *********/ - -#define GPIO_REC_PCM_CLK EXYNOS4_GPC0(0) -#define GPIO_REC_PCM_SYNC EXYNOS4_GPC0(2) -#define GPIO_REC_PCM_IN EXYNOS4_GPC0(3) -#define GPIO_REC_PCM_OUT EXYNOS4_GPC0(4) - - -/*********************** GPC1 Block *********/ - -#define GPIO_FM_I2S_CLK EXYNOS4_GPC1(0) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_I2S_SYNC EXYNOS4_GPC1(2) -#define GPIO_FM_I2S_DI EXYNOS4_GPC1(3) -#define GPIO_FM_I2S_DO EXYNOS4_GPC1(4) - - -/*********************** GPD0 Block *********/ - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(0) -#define GPIO_PMIC_SDA EXYNOS4_GPD0(2) -#define GPIO_PMIC_SCL EXYNOS4_GPD0(3) - - -/*********************** GPD1 Block *********/ - -#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - - -/*********************** GPF0 Block *********/ -#define GPIO_LCD_HYNC EXYNOS4_GPF0(0) -#define GPIO_LCD_VSYNC EXYNOS4_GPF0(1) -#define GPIO_LCD_DE EXYNOS4_GPF0(2) -#define GPIO_LCD_PCLK EXYNOS4_GPF0(3) -#define GPIO_LCD_D_0 EXYNOS4_GPF0(4) -#define GPIO_LCD_D_1 EXYNOS4_GPF0(5) -#define GPIO_LCD_D_2 EXYNOS4_GPF0(6) -#define GPIO_LCD_D_3 EXYNOS4_GPF0(7) - - -/*********************** GPF1 Block *********/ -#define GPIO_LCD_D_4 EXYNOS4_GPF1(0) -#define GPIO_LCD_D_5 EXYNOS4_GPF1(1) -#define GPIO_LCD_D_6 EXYNOS4_GPF1(2) -#define GPIO_LCD_D_7 EXYNOS4_GPF1(3) -#define GPIO_LCD_D_8 EXYNOS4_GPF1(4) -#define GPIO_LCD_D_9 EXYNOS4_GPF1(5) -#define GPIO_LCD_D_10 EXYNOS4_GPF1(6) -#define GPIO_LCD_D_11 EXYNOS4_GPF1(7) - -/*********************** GPF2 Block *********/ -#define GPIO_LCD_D_12 EXYNOS4_GPF2(0) -#define GPIO_LCD_D_13 EXYNOS4_GPF2(1) -#define GPIO_LCD_D_14 EXYNOS4_GPF2(2) -#define GPIO_LCD_D_15 EXYNOS4_GPF2(3) -#define GPIO_LCD_D_16 EXYNOS4_GPF2(4) -#define GPIO_LCD_D_17 EXYNOS4_GPF2(5) -#define GPIO_LCD_D_18 EXYNOS4_GPF2(6) -#define GPIO_LCD_D_19 EXYNOS4_GPF2(7) - - -/*********************** GPF3 Block *********/ -#define GPIO_LCD_D_20 EXYNOS4_GPF3(0) -#define GPIO_LCD_D_21 EXYNOS4_GPF3(1) -#define GPIO_LCD_D_22 EXYNOS4_GPF3(2) -#define GPIO_LCD_D_23 EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) - - -/*********************** GPJ0 Block *********/ -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPJ0(2) -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) /*old name*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) - -/*********************** GPJ1 Block *********/ -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - - -/*********************** GPK0 Block *********/ -#define GPIO_NAND_CLK EXYNOS4_GPK0(0) -#define GPIO_NAND_CMD EXYNOS4_GPK0(1) -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) -#define GPIO_NAND_D_0 EXYNOS4_GPK0(3) -#define GPIO_NAND_D_1 EXYNOS4_GPK0(4) -#define GPIO_NAND_D_2 EXYNOS4_GPK0(5) -#define GPIO_NAND_D_3 EXYNOS4_GPK0(6) - - -/*********************** GPK1 Block *********/ -#define GPIO_NAND_D_4 EXYNOS4_GPK1(3) -#define GPIO_NAND_D_5 EXYNOS4_GPK1(4) -#define GPIO_NAND_D_6 EXYNOS4_GPK1(5) -#define GPIO_NAND_D_7 EXYNOS4_GPK1(6) - - -/*********************** GPK2 Block *********/ -#define GPIO_T_FLASH_CLK EXYNOS4_GPK2(0) -#define GPIO_T_FLASH_CMD EXYNOS4_GPK2(1) - -#define GPIO_T_FLASH_D_0 EXYNOS4_GPK2(3) -#define GPIO_T_FLASH_D_1 EXYNOS4_GPK2(4) -#define GPIO_T_FLASH_D_2 EXYNOS4_GPK2(5) -#define GPIO_T_FLASH_D_3 EXYNOS4_GPK2(6) - -/*********************** GPK3 Block *********/ -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -/*********************** GPL0 Block *********/ -#define GPIO_BUCK2_SEL EXYNOS4_GPL0(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPL0(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPL0(3) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_BT_EN EXYNOS4_GPL0(6) - -/*********************** GPL1 Block *********/ -#define GPIO_PS_ALS_SCL_18V EXYNOS4_GPL1(0) -#define GPIO_PS_ALS_SDA_18V EXYNOS4_GPL1(1) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPL1(0) -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPL1(1) - -/*********************** GPL2 Block *********/ -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) -#define GPIO_WLAN_WAKE EXYNOS4_GPL2(3) -#define GPIO_CHG_EN EXYNOS4_GPL2(4) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) - - -/*********************** GPM0 Block *********/ -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_VT_nSTBY EXYNOS4212_GPM0(5) -#define GPIO_TA_nCONNECTED EXYNOS4212_GPM0(6) -#define GPIO_CHG_ING_N EXYNOS4212_GPM0(7) - - -/*********************** GPM1 Block *********/ -#define GPIO_HW_REV0 EXYNOS4212_GPM1(2) -#define GPIO_HW_REV1 EXYNOS4212_GPM1(3) -#define GPIO_HW_REV2 EXYNOS4212_GPM1(4) -#define GPIO_HW_REV3 EXYNOS4212_GPM1(5) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - - -/*********************** GPM2 Block *********/ - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_TP_VT_CAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) - - -/*********************** GPM3 Block *********/ -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) - - -/*********************** GPM4 Block *********/ -#define GPIO_3_TOUCH_SCL EXYNOS4212_GPM4(0) -#define GPIO_3_TOUCH_SDA EXYNOS4212_GPM4(1) -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM4(5) -#define GPIO_MIC_BIAS_EN_00 EXYNOS4212_GPM4(5) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4212_GPM4(6) -#define GPIO_SUB_MIC_BIAS_EN_00 EXYNOS4212_GPM4(6) - - -/*********************** GPX0 Block *********/ -#define GPIO_ACC_INT EXYNOS4_GPX0(0) -#define GPIO_DET_35 EXYNOS4_GPX0(1) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) -#define GPIO_GYRO_INT EXYNOS4_GPX0(4) -#define GPIO_OLED_DET EXYNOS4_GPX0(5) -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) - - -/*********************** GPX1 Block *********/ -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) /*old name*/ -#define GPIO_BARO_INT EXYNOS4_GPX1(4) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) - - -/*********************** GPX2 Block *********/ -#define GPIO_VOL_UP GPIO_DUMMP -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define GPIO_nPOWER EXYNOS4_GPX2(7) - - - -/*********************** GPX3 Block *********/ -#define GPIO_ISP_INT EXYNOS4_GPX3(0) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_CP_RST EXYNOS4_GPX3(2) -#define GPIO_VOL_DOWN GPIO_DUMMP -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) -#define GPIO_T_FLASH_DETECT EXYNOS4_GPX3(4) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) -#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -/*********************** GPY0 Block *********/ -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) - -/*********************** GPY2 Block *********/ -#define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BSENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - - -/*********************** GPY3 Block *********/ - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPY3(0) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_LCD_SCLK EXYNOS4_GPY3(1) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPY3(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) -#define GPIO_LCD_SDI EXYNOS4_GPY3(3) -#define GPIO_OLED_ID EXYNOS4_GPY3(4) -#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) -#define GPIO_ISP_RESET EXYNOS4_GPY3(7) - - -/*********************** GPY4 Block *********/ -#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) -#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) -#define GPIO_LCD_nCS EXYNOS4_GPY4(3) -#define GPIO_3_TOUCH_EN EXYNOS4_GPY4(4) -#define GPIO_MLCD_RST EXYNOS4_GPY4(5) -#define GPIO_MHL_SEL EXYNOS4_GPY4(6) -#define GPIO_UART_SEL EXYNOS4_GPY4(7) - - -/****************** DUMMP ********************/ -#define GPIO_MHL_DSDA_2_8V GPIO_DUMMP -#define GPIO_MHL_DSCL_2_8V GPIO_DUMMP -#define GPIO_WPC_INT GPIO_DUMMP -#define GPIO_OTG_EN GPIO_DUMMP /*don't used pin*/ -#define GPIO_CAM_IO_EN GPIO_DUMMP -#define GPIO_VTCAM_MCLK GPIO_DUMMP -#define GPIO_CAM_AF_EN GPIO_DUMMP -#define GPIO_FLM_RXD GPIO_DUMMP -#define GPIO_FLM_RXD_AF 2 -#define GPIO_FLM_TXD GPIO_DUMMP -#define GPIO_FLM_TXD_AF 2 -#define GPIO_GPS_CNTL GPIO_DUMMP -#define GPIO_PS_ALS_SDA_28V GPIO_DUMMP -#define GPIO_PS_ALS_SCL_28V GPIO_DUMMP -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - - - -#endif /* __MACH_GPIO_MIDAS_H */ - -#else - -/* linux/arch/arm/mach-exynos/include/mach/gpio-exynos4.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S2Plus GPIO common lib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_DUMMP EXYNOS4212_GPM3(4) - - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - - -#define GPIO_AP_RXD EXYNOS4_GPA1(0) -#define GPIO_AP_TXD EXYNOS4_GPA1(1) - -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - - - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPB(1) - -#define GPIO_NFC_SDA_18V EXYNOS4_GPB(2) -#define GPIO_NFC_SCL_18V EXYNOS4_GPB(3) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - - -#define GPIO_REC_PCM_CLK EXYNOS4_GPC0(0) -#define GPIO_REC_PCM_SYNC EXYNOS4_GPC0(2) -#define GPIO_REC_PCM_IN EXYNOS4_GPC0(3) -#define GPIO_REC_PCM_OUT EXYNOS4_GPC0(4) - - - -#define GPIO_FM_I2S_CLK EXYNOS4_GPC1(0) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_I2S_SYNC EXYNOS4_GPC1(2) -#define GPIO_FM_I2S_DI EXYNOS4_GPC1(3) -#define GPIO_FM_I2S_DO EXYNOS4_GPC1(4) - - - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(0) -#define GPIO_PMIC_SDA EXYNOS4_GPD0(2) -#define GPIO_PMIC_SCL EXYNOS4_GPD0(3) - - - -#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - - -#define GPIO_LCD_HYNC EXYNOS4_GPF0(0) -#define GPIO_LCD_VSYNC EXYNOS4_GPF0(1) -#define GPIO_LCD_DE EXYNOS4_GPF0(2) -#define GPIO_LCD_PCLK EXYNOS4_GPF0(3) -#define GPIO_LCD_D_0 EXYNOS4_GPF0(4) -#define GPIO_LCD_D_1 EXYNOS4_GPF0(5) -#define GPIO_LCD_D_2 EXYNOS4_GPF0(6) -#define GPIO_LCD_D_3 EXYNOS4_GPF0(7) - - -#define GPIO_LCD_D_4 EXYNOS4_GPF1(0) -#define GPIO_LCD_D_5 EXYNOS4_GPF1(1) -#define GPIO_LCD_D_6 EXYNOS4_GPF1(2) -#define GPIO_LCD_D_7 EXYNOS4_GPF1(3) -#define GPIO_LCD_D_8 EXYNOS4_GPF1(4) -#define GPIO_LCD_D_9 EXYNOS4_GPF1(5) -#define GPIO_LCD_D_10 EXYNOS4_GPF1(6) -#define GPIO_LCD_D_11 EXYNOS4_GPF1(7) - -#define GPIO_LCD_D_12 EXYNOS4_GPF2(0) -#define GPIO_LCD_D_13 EXYNOS4_GPF2(1) -#define GPIO_LCD_D_14 EXYNOS4_GPF2(2) -#define GPIO_LCD_D_15 EXYNOS4_GPF2(3) -#define GPIO_LCD_D_16 EXYNOS4_GPF2(4) -#define GPIO_LCD_D_17 EXYNOS4_GPF2(5) -#define GPIO_LCD_D_18 EXYNOS4_GPF2(6) -#define GPIO_LCD_D_19 EXYNOS4_GPF2(7) - - -#define GPIO_LCD_D_20 EXYNOS4_GPF3(0) -#define GPIO_LCD_D_21 EXYNOS4_GPF3(1) -#define GPIO_LCD_D_22 EXYNOS4_GPF3(2) -#define GPIO_LCD_D_23 EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) - - -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPJ0(2) -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) - -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - - -#define GPIO_NAND_CLK EXYNOS4_GPK0(0) -#define GPIO_NAND_CMD EXYNOS4_GPK0(1) -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) -#define GPIO_NAND_D_0 EXYNOS4_GPK0(3) -#define GPIO_NAND_D_1 EXYNOS4_GPK0(4) -#define GPIO_NAND_D_2 EXYNOS4_GPK0(5) -#define GPIO_NAND_D_3 EXYNOS4_GPK0(6) - - -#define GPIO_NAND_D_4 EXYNOS4_GPK1(3) -#define GPIO_NAND_D_5 EXYNOS4_GPK1(4) -#define GPIO_NAND_D_6 EXYNOS4_GPK1(5) -#define GPIO_NAND_D_7 EXYNOS4_GPK1(6) - - -#define GPIO_T_FLASH_CLK EXYNOS4_GPK2(0) -#define GPIO_T_FLASH_CMD EXYNOS4_GPK2(1) - -#define GPIO_T_FLASH_D_0 EXYNOS4_GPK2(3) -#define GPIO_T_FLASH_D_1 EXYNOS4_GPK2(4) -#define GPIO_T_FLASH_D_2 EXYNOS4_GPK2(5) -#define GPIO_T_FLASH_D_3 EXYNOS4_GPK2(6) - -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_BUCK2_SEL EXYNOS4_GPL0(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPL0(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPL0(3) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_BT_EN EXYNOS4_GPL0(6) - -#define GPIO_PS_ALS_SCL_18V EXYNOS4_GPL1(0) -#define GPIO_PS_ALS_SDA_18V EXYNOS4_GPL1(1) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPL1(0) -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPL1(1) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) -#define GPIO_WLAN_WAKE EXYNOS4_GPL2(3) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) - - -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_VT_nSTBY EXYNOS4212_GPM0(5) - - -#define GPIO_HW_REV0 EXYNOS4212_GPM1(2) -#define GPIO_HW_REV1 EXYNOS4212_GPM1(3) -#define GPIO_HW_REV2 EXYNOS4212_GPM1(4) -#define GPIO_HW_REV3 EXYNOS4212_GPM1(5) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - - - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_TP_VT_CAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) - - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) - - -#define GPIO_3_TOUCH_SCL EXYNOS4212_GPM4(0) -#define GPIO_3_TOUCH_SDA EXYNOS4212_GPM4(1) -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM4(5) -#define GPIO_MIC_BIAS_EN_00 EXYNOS4212_GPM4(5) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4212_GPM4(6) -#define GPIO_SUB_MIC_BIAS_EN_00 EXYNOS4212_GPM4(6) - - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) -#define GPIO_DET_35 EXYNOS4_GPX0(1) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) -#define GPIO_GYRO_INT EXYNOS4_GPX0(4) -#define GPIO_OLED_DET EXYNOS4_GPX0(5) -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) - - -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_BARO_INT EXYNOS4_GPX1(4) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) - - -#define GPIO_VOL_UP GPIO_DUMMP -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define GPIO_nPOWER EXYNOS4_GPX2(7) - - - -#define GPIO_WPC_INT EXYNOS4_GPX3(0) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_CP_RST EXYNOS4_GPX3(2) -#define GPIO_VOL_DOWN GPIO_DUMMP -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) -#define GPIO_T_FLASH_DETECT EXYNOS4_GPX3(4) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) -#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) - - -#define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - - - -#define GPIO_MHL_SDA_1_8V GPIO_DUMMP -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPY3(0) -#define GPIO_LCD_SCLK EXYNOS4_GPY3(1) -#define GPIO_MHL_SCL_1_8V GPIO_DUMMP -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPY3(2) -#define GPIO_LCD_SDI EXYNOS4_GPY3(3) -#define GPIO_OLED_ID EXYNOS4_GPY3(4) -#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) -#define GPIO_ISP_RESET EXYNOS4_GPY3(7) - - -#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) -#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) -#define GPIO_LCD_nCS EXYNOS4_GPY4(3) -#define GPIO_3_TOUCH_EN EXYNOS4_GPY4(4) -#define GPIO_MLCD_RST EXYNOS4_GPY4(5) -#define GPIO_MHL_SEL EXYNOS4_GPY4(6) -#define GPIO_UART_SEL EXYNOS4_GPY4(7) - - - -#define GPIO_MHL_DSCL_2_8V GPIO_DUMMP -#define GPIO_MHL_DSDA_2_8V GPIO_DUMMP -#define GPIO_OTG_EN GPIO_DUMMP -#define GPIO_CAM_IO_EN GPIO_DUMMP -#define GPIO_VTCAM_MCLK GPIO_DUMMP -#define GPIO_CAM_AF_EN GPIO_DUMMP -#define GPIO_FLM_RXD GPIO_DUMMP -#define GPIO_FLM_RXD_AF 2 -#define GPIO_FLM_TXD GPIO_DUMMP -#define GPIO_FLM_TXD_AF 2 -#define GPIO_GPS_CNTL GPIO_DUMMP -#define GPIO_PS_ALS_SDA_28V GPIO_DUMMP -#define GPIO_PS_ALS_SCL_28V GPIO_DUMMP -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - - - -#endif /* __MACH_GPIO_MIDAS_H */ - -#endif diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h index 13fdb3d..2095f64 100644..100755 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h @@ -6,102 +6,71 @@ extern void midas_config_gpio_table(void); extern void midas_config_sleep_gpio_table(void); -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) -#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) -#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) /* rev0.0, 0.1 */ +/* Camera */ #define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) #define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) #define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) #define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) #define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) #define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#if 1 -#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#else -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) -#endif - +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM4(1) #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) #define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) -/* Sensors & NFC*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +/* NFC */ +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) /* above rev0.1 */ +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) /* above rev0.1 */ -#define GPIO_GYRO_INT EXYNOS4_GPF0(3) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +/* Sensor Hub */ +#define GPIO_MCU_AP_INT EXYNOS4_GPX0(0) +#define GPIO_AP_MCU_INT EXYNOS4_GPX0(2) +#define GPIO_MCU_AP_INT_2 EXYNOS4_GPX2(1) +#define GPIO_MCU_NRST EXYNOS4_GPY2(2) -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) +/* PMIC */ +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) #define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_NFC_SCL_18V EXYNOS4_GPZ(6) -#define GPIO_NFC_SDA_18V EXYNOS4_GPZ(5) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) -#define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMU_RST EXYNOS4_GPX3(2) +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) #define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) + +/* BT */ #define GPIO_BT_EN EXYNOS4_GPL0(6) #define GPIO_BT_WAKE EXYNOS4_GPX3(1) #define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) @@ -119,37 +88,30 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BT_RTS EXYNOS4_GPA0(3) #define GPIO_BT_RTS_AF 2 + +/* GPS */ #define GPIO_GPS_RXD EXYNOS4_GPA0(4) #define GPIO_GPS_RXD_AF 2 #define GPIO_GPS_TXD EXYNOS4_GPA0(5) #define GPIO_GPS_TXD_AF 2 +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_TARGET_LOCALE_CHN) #define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - #define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 +#else +#define GPIO_GPS_CTS -1 +#define GPIO_GPS_RTS -1 +#endif -#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) -#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(0) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS_AF 2 -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) +#define GPIO_GPS_nRST EXYNOS4_GPL2(1) +#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) +/* WIFI */ #define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) #define GPIO_WLAN_EN_AF 1 #define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) @@ -167,156 +129,245 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) #define GPIO_WLAN_SDIO_D3_AF 2 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - +#ifdef CONFIG_SAMSUNG_MHL +/* Definitions for Sii 9244B0 */ #define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) #define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) - -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) -#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) -#define GPIO_OLED_DET EXYNOS4_GPF3(0) - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) #define GPIO_MHL_RST EXYNOS4_GPF3(4) #define GPIO_MHL_INT EXYNOS4_GPF3(5) #define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) #define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#endif +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +/* Touch key */ +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +/* TSP */ +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_LDO_28V_EN EXYNOS4212_GPM4(0) -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) +/* Keys */ +#define GPIO_OK_KEY EXYNOS4_GPX0(1) /* above 0.1 */ +#define GPIO_VOL_UP EXYNOS4_GPX2(2) #define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) + +/* Pen */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_TARGET_LOCALE_CHN) +#define GPIO_PEN_SDA EXYNOS4_GPB(2) +#define GPIO_PEN_SCL EXYNOS4_GPB(3) +#else +#define GPIO_PEN_SDA EXYNOS4_GPA0(6) +#define GPIO_PEN_SCL EXYNOS4_GPA0(7) +#endif + +#define GPIO_WACOM_LDO_EN EXYNOS4_GPF2(5) +#define GPIO_PEN_IRQ EXYNOS4_GPX0(4) +#define GPIO_WACOM_SENSE EXYNOS4_GPX2(4) +#define GPIO_PEN_PDCT EXYNOS4_GPX3(5) +#define GPIO_PEN_SLP EXYNOS4_GPY1(3) +#define GPIO_PEN_FWE1 EXYNOS4_GPY1(3) +#define GPIO_PEN_RESET_N EXYNOS4_GPY2(1) + +/* battery */ #define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#if defined(CONFIG_TARGET_LOCALE_USA) +#define GPIO_BATT_PRESENT_N_INT EXYNOS4_GPX1(3) /* rev0.2 ~ */ +#endif +#if defined(CONFIG_BATTERY_WPC_CHARGER) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) /* rev0.2 ~ */ +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) /* rev0.2 ~ */ +#endif + +/* Others */ +#define GPIO_LCD_18V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) /* obsoleted */ + +#define GPIO_OTG_EN EXYNOS4_GPF0(7) -#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) /* rev0.9 ~ */ -#define GPIO_WPC_INT EXYNOS4_GPX3(0) +#define GPIO_OLED_ID EXYNOS4_GPF1(0) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) +#if defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(2) +#endif -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_AUDIO_PCM_SEL EXYNOS4212_GPM0(3) +#endif +#if defined(CONFIG_SWITCH_DUAL_MODEM) +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_UART_SEL EXYNOS4212_GPM3(6) +#define GPIO_USB_SEL EXYNOS4212_GPM4(0) +#define GPIO_CP_USB_ON EXYNOS4212_GPM0(2) +#endif +#endif -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_OLED_DET EXYNOS4_GPF3(0) #define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) +#define GPIO_ERR_FG EXYNOS4212_GPJ0(7) + +#define GPIO_G_DET_N EXYNOS4_GPX3(0) +#define GPIO_G_DET_N_REV03 EXYNOS4_GPX2(0) +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) + +#ifdef CONFIG_JACK_FET +#define GPIO_EAR_BIAS_DISCHARGE EXYNOS4_GPC1(0) +#endif + +/** Previous revision **/ +/* rev0.0 */ +#define GPIO_TSP_LDO_EN EXYNOS4212_GPJ0(6) +/* GPIO_MHL_SEL EXYNOS4212_GPJ0(5) */ +/* GPIO_LCD_22V_EN EXYNOS4_GPC0(1) */ + /* Modem Interface GPIOs - M0 HSIC */ -#if !defined(CONFIG_SEC_MODEM_M0_TD) #define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) #define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) #define GPIO_PHONE_ON EXYNOS4_GPL2(5) #define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) #define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) -#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) #define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) #define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) #define GPIO_CP_RST EXYNOS4_GPX3(2) -#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#else -/* Modem Interface GPIOs - M0 SPI */ -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_AP_CP_INT1 EXYNOS4_GPX0(5) -#define GPIO_AP_CP_INT2 EXYNOS4_GPX3(5) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_IPC_MRDY EXYNOS4_GPX0(4) -#define GPIO_IPC_SRDY EXYNOS4_GPX1(0) -#define GPIO_IPC_SUB_MRDY EXYNOS4_GPX3(2) -#define GPIO_IPC_SUB_SRDY EXYNOS4_GPX1(1) - -#define GPIO_CP_RST EXYNOS4_GPF1(1) -#define GPIO_CP_REQ_RESET EXYNOS4_GPF1(1) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_SUSPEND_REQUEST EXYNOS4_GPF1(1) -#define GPIO_ISP_INT EXYNOS4_GPF1(1) -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +/* Modem Interface GPIOs - MDM */ +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4_GPY2(3) + +#if defined(CONFIG_MACH_T0_CHN_CMCC) +/* Modem Interface GPIOs - T0 SPI */ +#define GPIO_TD_PDA_ACTIVE EXYNOS4_GPF3(4) +#define GPIO_TD_PHONE_ON EXYNOS4212_GPM0(1) +#define GPIO_TD_PHONE_ACTIVE EXYNOS4_GPX1(3) +#define GPIO_AP_TD_INT1 EXYNOS4_GPF0(6) +#define GPIO_AP_TD_INT2 EXYNOS4_GPF0(4) +#define GPIO_TD_DUMP_INT EXYNOS4_GPX0(5) +#define GPIO_IPC_MRDY EXYNOS4_GPF2(4) +#define GPIO_IPC_SRDY EXYNOS4_GPX0(6) +#define GPIO_IPC_SUB_MRDY EXYNOS4_GPF2(2) +#define GPIO_IPC_SUB_SRDY EXYNOS4_GPX3(0) + +#define IRQ_PHONE_ACTIVE gpio_to_irq(GPIO_TD_PHONE_ACTIVE) +#define IRQ_IPC_SRDY gpio_to_irq(GPIO_IPC_SRDY) +#define IRQ_IPC_SUB_SRDY gpio_to_irq(GPIO_IPC_SUB_SRDY) +#define IRQ_TD_DUMP_INT gpio_to_irq(GPIO_TD_DUMP_INT) -#define GPIO_FM_RST EXYNOS4_GPC1(0) +#endif -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_PHONE_ACTIVE IRQ_EINT14 -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_IPC_SUB_SRDY IRQ_EINT9 -#define IRQ_CP_DUMP_INT IRQ_EINT10 +#ifdef CONFIG_SEC_DUAL_MODEM_MODE +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_SIM_IO_SEL EXYNOS4_GPL2(0) +#define GPIO_CP_CTRL1 EXYNOS4_GPL2(3) +#define GPIO_CP_CTRL2 EXYNOS4_GPL2(4) +#endif #endif -#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) /*system_rev == 11*/ -#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3) /*system_rev >= 15*/ -#define GPIO_FM_INT_REV15 EXYNOS4_GPX1(4) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) +#if !defined(CONFIG_MACH_T0_CHN_CMCC) +/* FM (Eur) */ #define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_MIC_SW EXYNOS4_GPL0(3) +#define GPIO_FM_RST EXYNOS4_GPX1(4) +#define GPIO_FM_RST_REV03 EXYNOS4_GPY0(1) +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) +#endif #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) -#define GPIO_TDMB_EN EXYNOS4_GPL0(0) -#define GPIO_TDMB_INT EXYNOS4_GPF0(2) +#define GPIO_TDMB_RST_N EXYNOS4_GPC0(0) +#define GPIO_TDMB_EN EXYNOS4_GPC0(2) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) #define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) -#define GPIO_TDMB_INT_AF 0xf #define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) #define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) #define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) #define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#if defined(CONFIG_TDMB_ANT_DET) +#define GPIO_TDMB_ANT_DET EXYNOS4_GPF2(0) +#define GPIO_TDMB_IRQ_ANT_DET gpio_to_irq(GPIO_TDMB_ANT_DET) +#define GPIO_TDMB_ANT_DET_REV08 EXYNOS4_GPX1(3) +#define GPIO_TDMB_IRQ_ANT_DET_REV08 gpio_to_irq(GPIO_TDMB_ANT_DET_REV08) +#endif + +#elif defined(CONFIG_ISDBT) +#define GPIO_ISDBT_RST_N EXYNOS4_GPC0(0) +#define GPIO_ISDBT_EN EXYNOS4_GPC0(2) +#define GPIO_ISDBT_INT EXYNOS4_GPC0(4) +#define GPIO_ISDBT_IRQ gpio_to_irq(GPIO_ISDBT_INT) +#define GPIO_ISDBT_INT_AF 0xf +#define GPIO_ISDBT_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_ISDBT_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_ISDBT_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_ISDBT_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +/*BARCODE_EMUL*/ +#if defined(CONFIG_BARCODE_EMUL_ICE4) +#define GPIO_BARCODE_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_BARCODE_SCL_1_8V EXYNOS4_GPF0(1) + +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) +#define GPIO_FPGA_CDONE EXYNOS4_GPF3(4) +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF3(5) +#else +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF0(2) +#define GPIO_FPGA_CDONE EXYNOS4_GPF0(3) +#endif + +#define GPIO_FPGA_RST_N EXYNOS4_GPF0(5) +#define GPIO_FPGA_SPI_CLK EXYNOS4212_GPM4(4) +#define GPIO_FPGA_SPI_SI EXYNOS4212_GPM4(6) +#define GPIO_FPGA_SPI_EN EXYNOS4212_GPM4(5) +#endif + +#if defined(CONFIG_FELICA) +#define FELICA_GPIO_I2C_SDA EXYNOS4_GPY2(4) +#define FELICA_GPIO_I2C_SCL EXYNOS4_GPY2(5) +#define FELICA_UART3RX EXYNOS4_GPA1(4) +#define FELICA_GPIO_RFS EXYNOS4_GPL2(6) +#define FELICA_GPIO_PON EXYNOS4_GPL2(7) +#define FELICA_GPIO_INT EXYNOS4_GPX1(7) #endif #endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0ctc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0ctc.h new file mode 100644 index 0000000..61315f8 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0ctc.h @@ -0,0 +1,383 @@ +#ifndef __MACH_GPIO_T0CTC_H +#define __MACH_GPIO_T0CTC_H __FILE__ + +#include <mach/gpio.h> + +extern void midas_config_gpio_table(void); +extern void midas_config_sleep_gpio_table(void); + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + + +/* Camera */ +#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) +#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) +#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) +#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) + +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) +#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) + +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) +#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) + +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM4(1) +#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) +#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) +#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) + + +/* NFC */ +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) /* above rev0.1 */ +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) /* above rev0.1 */ + + +/* Sensor Hub */ +#define GPIO_MCU_AP_INT EXYNOS4_GPX0(0) +#define GPIO_AP_MCU_INT EXYNOS4_GPX0(2) +#define GPIO_MCU_AP_INT_2 EXYNOS4_GPX2(1) +#define GPIO_MCU_NRST EXYNOS4_GPY2(2) + + +/* PMIC */ +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) +#define GPIO_TF_EN EXYNOS4_GPY2(0) + +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) + +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) + +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) +#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) + +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) + + +/* BT */ +#define GPIO_BT_EN EXYNOS4_GPL0(6) +#define GPIO_BT_WAKE EXYNOS4_GPX3(1) +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) +#define IRQ_BT_HOST_WAKE IRQ_EINT(22) + +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_RXD_AF 2 + +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_TXD_AF 2 + +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_CTS_AF 2 + +#define GPIO_BT_RTS EXYNOS4_GPA0(3) +#define GPIO_BT_RTS_AF 2 + + +/* GPS */ +#define GPIO_GPS_RXD EXYNOS4_GPA0(4) +#define GPIO_GPS_RXD_AF 2 + +#define GPIO_GPS_TXD EXYNOS4_GPA0(5) +#define GPIO_GPS_TXD_AF 2 + +#if defined(CONFIG_MACH_T0_EUR_OPEN) +#define GPIO_GPS_CTS EXYNOS4_GPA0(6) +#define GPIO_GPS_RTS EXYNOS4_GPA0(7) +#else +#define GPIO_GPS_CTS -1 +#define GPIO_GPS_RTS -1 +#endif + +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS_AF 2 + +#if defined(CONFIG_MACH_T0_EUR_OPEN) +#define GPIO_GPS_nRST EXYNOS4_GPL2(1) +#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +#else +#define GPIO_GPS_nRST -1 +#define GPIO_GPS_PWR_EN -1 +#endif + +/* WIFI */ +#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) +#define GPIO_WLAN_HOST_WAKE_AF 0xF +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + + +#ifdef CONFIG_SAMSUNG_MHL +/* Definitions for Sii 9244B0 */ +#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) +#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#endif + +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + +/* Touch key */ +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) + + +/* TSP */ +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) + + +/* Keys */ +#define GPIO_OK_KEY EXYNOS4_GPX0(1) /* above 0.1 */ +#define GPIO_VOL_UP EXYNOS4_GPX2(2) +#define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) + + +/* Pen */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) +#define GPIO_PEN_SDA EXYNOS4_GPB(2) +#define GPIO_PEN_SCL EXYNOS4_GPB(3) +#else +#define GPIO_PEN_SDA EXYNOS4_GPA0(6) +#define GPIO_PEN_SCL EXYNOS4_GPA0(7) +#endif + +#define GPIO_WACOM_LDO_EN EXYNOS4_GPF2(5) +#define GPIO_PEN_IRQ EXYNOS4_GPX0(4) +#define GPIO_WACOM_SENSE EXYNOS4_GPX2(4) +#define GPIO_PEN_PDCT EXYNOS4_GPX3(5) +#define GPIO_PEN_SLP EXYNOS4_GPY1(3) +#define GPIO_PEN_FWE1 EXYNOS4_GPY1(3) +#define GPIO_PEN_RESET_N EXYNOS4_GPY2(1) + +#if defined(CONFIG_BATTERY_WPC_CHARGER) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) /* rev0.2 ~ */ +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) /* rev0.2 ~ */ +#endif + +/* Others */ +#define GPIO_LCD_18V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) /* obsoleted */ + +#define GPIO_OTG_EN EXYNOS4_GPF0(7) + +#define GPIO_OLED_ID EXYNOS4_GPF1(0) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) + +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) + +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF1(1) + +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_OLED_DET EXYNOS4_GPF3(0) + +#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) +#define GPIO_ERR_FG EXYNOS4212_GPJ0(7) + +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#define GPIO_G_DET_N EXYNOS4_GPX3(0) +#define GPIO_G_DET_N_REV03 EXYNOS4_GPX2(0) +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) + +#ifdef CONFIG_JACK_FET +#define GPIO_EAR_BIAS_DISCHARGE EXYNOS4_GPC1(0) +#endif + +/** Previous revision **/ +/* rev0.0 */ +#define GPIO_TSP_LDO_EN EXYNOS4212_GPJ0(6) +/* GPIO_MHL_SEL EXYNOS4212_GPJ0(5) */ +/* GPIO_LCD_22V_EN EXYNOS4_GPC0(1) */ + + +#if !defined(CONFIG_MACH_T0_CHN_CTC) +/* Modem Interface GPIOs - M0 HSIC */ +#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) +#define GPIO_PHONE_ON EXYNOS4_GPL2(5) +#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) +#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_CP_RST EXYNOS4_GPX3(2) + + +/* Modem Interface GPIOs - MDM */ +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4_GPY2(3) + + +/* FM (Eur) */ +#define GPIO_FM_INT EXYNOS4_GPX1(3) +#define GPIO_FM_RST EXYNOS4_GPX1(4) +#define GPIO_FM_RST_REV03 EXYNOS4_GPY0(1) +#define GPIO_ADC_SCL EXYNOS4_GPY0(2) /* obsoleted */ +#define GPIO_ADC_SDA EXYNOS4_GPY0(3) /* obsoleted */ +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) +#endif + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#define GPIO_TDMB_RST_N EXYNOS4_GPC0(0) +#define GPIO_TDMB_EN EXYNOS4_GPC0(2) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) +#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) +#define GPIO_TDMB_INT_AF 0xf +#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +/*BARCODE_EMUL*/ +#if defined(CONFIG_BARCODE_EMUL_ICE4) +#define GPIO_BARCODE_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_BARCODE_SCL_1_8V EXYNOS4_GPF0(1) +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF0(2) +#define GPIO_FPGA_CDONE EXYNOS4_GPF0(3) +#define GPIO_FPGA_RST_N EXYNOS4_GPF0(5) +#define GPIO_FPGA_SPI_CLK EXYNOS4212_GPM4(4) +#define GPIO_FPGA_SPI_SI EXYNOS4212_GPM4(6) +#define GPIO_FPGA_SPI_EN EXYNOS4212_GPM4(5) +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define GPIO_FPGA1_CRESET EXYNOS4_GPF0(2) +#define GPIO_FPGA1_CDONE EXYNOS4_GPF0(3) +#define GPIO_FPGA1_RST_N EXYNOS4_GPF0(6) +#define GPIO_FPGA1_CS_N EXYNOS4_GPC1(2) + +#define GPIO_FPGA2_CRESET EXYNOS4_GPF0(0) +#define GPIO_FPGA2_CDONE EXYNOS4_GPF0(1) +#define GPIO_FPGA2_RST_N EXYNOS4_GPF2(3) +#define GPIO_FPGA2_CS_N EXYNOS4_GPC0(2) +#endif + +/* Definitions for DPRAM */ +#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) +#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) +#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) +#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) +#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) +#define GPIO_DPRAM_LBN EXYNOS4_GPY1(0) +#define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) +#define GPIO_DPRAM_BUSY EXYNOS4_GPY1(2) + + +/* Definitions for MDM6600 */ +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) + +#define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) +#define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) +#define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) +#define GPIO_USB_HUB_INT EXYNOS4_GPX1(3) + +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#define GPIO_BOOT_SW_SEL_CP1 EXYNOS4_GPF3(4) +#define GPIO_USB_SEL EXYNOS4212_GPJ1(4) + +#define GPIO_USB_BOOT_EN EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL EXYNOS4_GPF3(4) + +/* for revesion 06 higher */ +#define GPIO_USB_BOOT_EN_REV06 EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL_REV06 EXYNOS4_GPF3(4) + +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPC0(3) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPC0(0) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) + +#define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) +#define GPIO_CP_MSM_RST EXYNOS4_GPL2(1) +#define GPIO_CP_MSM_PMU_RST EXYNOS4_GPC0(0) +#define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) + +#define GPIO_MSM_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) + +#define GPIO_MSM_DPRAM_INT EXYNOS4_GPX1(1) +#define MSM_DPRAM_INT_IRQ IRQ_EINT(9) + + +/* Definitions for ESC6270 */ +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(3) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(2) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) + +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX3(2) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(26) + +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX1(0) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(8) + +#if defined(CONFIG_SIM_SLOT_SWITCH) +#define GPIO_UIM_SIM_SEL EXYNOS4_GPL0(4) +#endif + +/* DUMMY GPIOS */ +#define GPIO_MHL_SEL EXYNOS4_GPC0(0) +#define GPIO_HDMI_HPD EXYNOS4_GPC0(0) +#define GPIO_HDMI_EN EXYNOS4_GPC0(0) +#define GPIO_USB_HUB_CONNECT EXYNOS4_GPC0(0) + +#endif /* __MACH_GPIO_T0CTC_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0cu-duos.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0cu-duos.h new file mode 100644 index 0000000..e477c7e --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0cu-duos.h @@ -0,0 +1,354 @@ +#ifndef __MACH_GPIO_MIDAS_H +#define __MACH_GPIO_MIDAS_H __FILE__ + +#include <mach/gpio.h> + +extern void midas_config_gpio_table(void); +extern void midas_config_sleep_gpio_table(void); + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + + +/* Camera */ +#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) +#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) +#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) +#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) + +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) +#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) + +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) +#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) + +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM4(1) +#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) +#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) +#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) + + +/* NFC */ +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) /* above rev0.1 */ +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) /* above rev0.1 */ + + +/* Sensor Hub */ +#define GPIO_MCU_AP_INT EXYNOS4_GPX0(0) +#define GPIO_AP_MCU_INT EXYNOS4_GPX0(2) +#define GPIO_MCU_AP_INT_2 EXYNOS4_GPX2(1) +#define GPIO_MCU_NRST EXYNOS4_GPY2(2) + + +/* PMIC */ +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) +#define GPIO_TF_EN EXYNOS4_GPY2(0) + +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) + +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) + +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) +#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) + +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) + + +/* BT */ +#define GPIO_BT_EN EXYNOS4_GPL0(6) +#define GPIO_BT_WAKE EXYNOS4_GPX3(1) +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) +#define IRQ_BT_HOST_WAKE IRQ_EINT(22) + +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_RXD_AF 2 + +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_TXD_AF 2 + +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_CTS_AF 2 + +#define GPIO_BT_RTS EXYNOS4_GPA0(3) +#define GPIO_BT_RTS_AF 2 + + +/* GPS */ +#define GPIO_GPS_RXD EXYNOS4_GPA0(4) +#define GPIO_GPS_RXD_AF 2 + +#define GPIO_GPS_TXD EXYNOS4_GPA0(5) +#define GPIO_GPS_TXD_AF 2 + +#define GPIO_GPS_CTS EXYNOS4_GPA0(6) +#define GPIO_GPS_RTS EXYNOS4_GPA0(7) + +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_GPS_nRST EXYNOS4_GPL2(1) +#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) + + +/* WIFI */ +#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) +#define GPIO_WLAN_HOST_WAKE_AF 0xF +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + + +/* Definitions for Sii 9244B0 */ +#ifdef CONFIG_SAMSUNG_MHL +#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) +#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#endif + +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + + +/* Touch key */ +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) + + +/* TSP */ +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_LDO_28V_EN EXYNOS4212_GPM4(0) + + +/* Keys */ +#define GPIO_OK_KEY EXYNOS4_GPX0(1) /* above 0.1 */ +#define GPIO_VOL_UP EXYNOS4_GPX2(2) +#define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) + + +/* Pen */ +#define GPIO_PEN_SDA EXYNOS4_GPB(2) +#define GPIO_PEN_SCL EXYNOS4_GPB(3) + +#define GPIO_WACOM_LDO_EN EXYNOS4_GPF2(5) +#define GPIO_PEN_IRQ EXYNOS4_GPX0(4) +#define GPIO_WACOM_SENSE EXYNOS4_GPX2(4) +#define GPIO_PEN_PDCT EXYNOS4_GPX3(5) +#define GPIO_PEN_SLP EXYNOS4_GPY1(3) +#define GPIO_PEN_FWE1 EXYNOS4_GPY1(3) +#define GPIO_PEN_RESET_N EXYNOS4_GPY2(1) + +/* battery */ +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#if defined(CONFIG_TARGET_LOCALE_USA) +#define GPIO_BATT_PRESENT_N_INT EXYNOS4_GPX1(3) /* rev0.2 ~ */ +#endif +#if defined(CONFIG_BATTERY_WPC_CHARGER) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) /* rev0.2 ~ */ +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) /* rev0.2 ~ */ +#endif + +/* Others */ +#define GPIO_LCD_18V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) /* obsoleted */ + +#define GPIO_OTG_EN EXYNOS4_GPF0(7) + +#define GPIO_OLED_ID EXYNOS4_GPF1(0) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) + +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) + + +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(2) +#endif + +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_AUDIO_PCM_SEL EXYNOS4212_GPM0(3) +#endif + +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_OLED_DET EXYNOS4_GPF3(0) + +#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) +#define GPIO_ERR_FG EXYNOS4212_GPJ0(7) + +#define GPIO_G_DET_N EXYNOS4_GPX3(0) +#define GPIO_G_DET_N_REV03 EXYNOS4_GPX2(0) +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) + +#ifdef CONFIG_JACK_FET +#define GPIO_EAR_BIAS_DISCHARGE EXYNOS4_GPC1(0) +#endif + +/** Previous revision **/ +/* rev0.0 */ +#define GPIO_TSP_LDO_EN EXYNOS4212_GPJ0(6) +/* GPIO_MHL_SEL EXYNOS4212_GPJ0(5) */ +/* GPIO_LCD_22V_EN EXYNOS4_GPC0(1) */ + + +/* Modem Interface GPIOs - M0 HSIC */ +#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) +#define GPIO_PHONE_ON EXYNOS4_GPL2(5) +#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) +#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_CP_RST EXYNOS4_GPX3(2) + + +/* Modem Interface GPIOs - MDM */ +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ + + +/* FM (Eur) */ +#define GPIO_FM_INT EXYNOS4_GPX1(3) +#define GPIO_FM_RST EXYNOS4_GPX1(4) +#define GPIO_FM_RST_REV03 EXYNOS4_GPY0(1) +#define GPIO_ADC_SCL EXYNOS4_GPY0(2) /* obsoleted */ +#define GPIO_ADC_SDA EXYNOS4_GPY0(3) /* obsoleted */ +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#define GPIO_TDMB_RST_N EXYNOS4_GPC0(0) +#define GPIO_TDMB_EN EXYNOS4_GPC0(2) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) +#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) +#define GPIO_TDMB_INT_AF 0xf +#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#elif defined(CONFIG_ISDBT) +#define GPIO_ISDBT_RST_N EXYNOS4_GPC0(0) +#define GPIO_ISDBT_EN EXYNOS4_GPC0(2) +#define GPIO_ISDBT_INT EXYNOS4_GPC0(4) +#define GPIO_ISDBT_IRQ gpio_to_irq(GPIO_ISDBT_INT) +#define GPIO_ISDBT_INT_AF 0xf +#define GPIO_ISDBT_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_ISDBT_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_ISDBT_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_ISDBT_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +/*BARCODE_EMUL*/ +#if defined(CONFIG_BARCODE_EMUL_ICE4) +#define GPIO_BARCODE_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_BARCODE_SCL_1_8V EXYNOS4_GPF0(1) + +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#define GPIO_FPGA_CDONE EXYNOS4_GPF3(4) +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF3(5) +#else +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF0(2) +#define GPIO_FPGA_CDONE EXYNOS4_GPF0(3) +#endif + +#define GPIO_FPGA_RST_N EXYNOS4_GPF0(5) +#define GPIO_FPGA_SPI_CLK EXYNOS4212_GPM4(4) +#define GPIO_FPGA_SPI_SI EXYNOS4212_GPM4(6) +#define GPIO_FPGA_SPI_EN EXYNOS4212_GPM4(5) +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define GPIO_FPGA1_CRESET EXYNOS4_GPF0(2) +#define GPIO_FPGA1_CDONE EXYNOS4_GPF0(3) +#define GPIO_FPGA1_RST_N EXYNOS4_GPF0(6) +#define GPIO_FPGA1_CS_N EXYNOS4_GPC1(2) +#endif + +/* Definitions for DPRAM */ +#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) +#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) +#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) +#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) +#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) +#define GPIO_DPRAM_LBN EXYNOS4_GPY1(0) +#define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) +#define GPIO_DPRAM_BUSY EXYNOS4_GPY1(2) + +#if defined(CONFIG_SWITCH_DUAL_MODEM) +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#define GPIO_USB_SEL EXYNOS4212_GPJ1(4) +#endif + +#if defined(CONFIG_GSM_MODEM_ESC6270) +/* Definitions for ESC6270 */ +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(3) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(2) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) + +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(3) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(11) + +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX0(5) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(5) +#endif + +#endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h b/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h index 809b19d..5e020ad 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h @@ -310,12 +310,14 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) +/* Definitions for PDA_ACTIVE for CMC221 & CBP7.2 */ +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) + #if defined(CONFIG_MACH_C1_KOR_LGT) /* Definitions for CBP7.2 */ #define GPIO_CBP_PMIC_PWRON EXYNOS4212_GPM0(6) #define GPIO_CBP_PS_HOLD_OFF EXYNOS4212_GPM1(0) #define GPIO_CBP_CP_RST EXYNOS4_GPF2(4) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) #define GPIO_CBP_PHONE_ACTIVE EXYNOS4_GPX1(3) #define CBP_PHONE_ACTIVE_IRQ IRQ_EINT(11) diff --git a/arch/arm/mach-exynos/include/mach/gpio-u1.h b/arch/arm/mach-exynos/include/mach/gpio-u1.h index a4b85ac..6b8abb2 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-u1.h +++ b/arch/arm/mach-exynos/include/mach/gpio-u1.h @@ -55,6 +55,11 @@ #define GPIO_CAM_SENSOR_CORE EXYNOS4210_GPE2(5) #define GPIO_TSP_LDO_ON EXYNOS4_GPL0(3) +#ifdef CONFIG_MACH_TRATS +#define GPIO_TSP_SDA EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL EXYNOS4_GPA1(3) +#endif + #define GPIO_USB_SEL EXYNOS4_GPL0(6) #if !defined(CONFIG_MACH_U1_KOR_LGT) #define GPIO_UART_SEL EXYNOS4_GPY4(7) @@ -162,11 +167,19 @@ #define GPIO_2MIC_SDA EXYNOS4_GPC1(2) #define GPIO_2MIC_SCL EXYNOS4_GPC1(0) +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#if defined(CONFIG_LEDS_GPIO) +/* GPIO's for SVC LED */ +#define GPIO_SVC_LED_BLUE EXYNOS4_GPA1(5) +#define GPIO_SVC_LED_RED EXYNOS4_GPB(1) +#endif +#else #define GPIO_FLM_RXD EXYNOS4_GPA1(4) #define GPIO_FLM_RXD_AF 2 #define GPIO_FLM_TXD EXYNOS4_GPA1(5) #define GPIO_FLM_TXD_AF 2 +#endif #if defined(CONFIG_MACH_U1_KOR_LGT) #define GPIO_DPRAM_INT_N EXYNOS4_GPX1(0) @@ -182,7 +195,11 @@ #define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) #define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) #else +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) +#else #define GPIO_PDA_ACTIVE EXYNOS4_GPX1(7) +#endif #define GPIO_CP_DUMP_INT DUMMY_GPIO #endif #define GPIO_CP_RST EXYNOS4_GPX1(4) @@ -208,6 +225,16 @@ #define IRQ_SUSPEND_REQUEST IRQ_EINT11 #define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 + +#ifdef CONFIG_USBHUB_USB3803 +#define GPIO_USB_RESET_N EXYNOS4210_GPE1(5) +#define GPIO_USB_BYPASS_N EXYNOS4_GPX1(7) +#define GPIO_USB_CLOCK_EN EXYNOS4_GPA1(4) +#define GPIO_USB_I2C_SDA EXYNOS4_GPY1(1) +#define GPIO_USB_I2C_SCL EXYNOS4_GPY1(0) +#endif /* CONFIG_USBHUB_USB3803 */ + + #define GPIO_WLAN_EN EXYNOS4_GPL1(2) #define GPIO_WLAN_EN_AF 1 @@ -223,22 +250,27 @@ #define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK2(0) +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK2(1) +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK2(3) +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK2(4) +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK2(5) +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK2(6) +#else +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#endif -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CLK_AF 2 #define GPIO_WLAN_SDIO_CMD_AF 2 - -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) #define GPIO_WLAN_SDIO_D0_AF 2 - -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) #define GPIO_WLAN_SDIO_D1_AF 2 - -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) #define GPIO_WLAN_SDIO_D2_AF 2 - -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) #define GPIO_WLAN_SDIO_D3_AF 2 #define GPIO_HW_REV0 EXYNOS4210_GPE1(0) @@ -272,9 +304,14 @@ #define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) #define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) #else +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) +#define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) +#else #define GPIO_MHL_SDA_18V EXYNOS4210_GPE1(6) #define GPIO_MHL_SCL_18V EXYNOS4210_GPE1(5) #endif +#endif #define GPIO_AP_HDMI_SDA GPIO_MSENSOR_MHL_SDA_28V #define GPIO_AP_HDMI_SDA_AF GPIO_MSENSOR_MHL_SDA_AF @@ -333,5 +370,24 @@ #define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) #endif +#if defined(CONFIG_TARGET_LOCALE_NA) && defined(CONFIG_WIMAX_CMC) +#define GPIO_WIMAX_USB_EN EXYNOS4_GPB(4) +#define GPIO_WIMAX_EN EXYNOS4210_GPE1(7) +#define GPIO_WIMAX_RESET_N EXYNOS4_GPA0(5) +#define GPIO_WIMAX_USB_EN EXYNOS4_GPB(4) +#define GPIO_WIMAX_WAKEUP EXYNOS4_GPX1(3) +#define GPIO_WIMAX_IF_MODE0 EXYNOS4_GPY3(5) +#define GPIO_WIMAX_IF_MODE1 EXYNOS4_GPY3(6) +#define GPIO_WIMAX_CON0 EXYNOS4_GPL2(6) +#define GPIO_WIMAX_CON1 EXYNOS4_GPL2(7) +#define GPIO_WIMAX_CON2 EXYNOS4210_GPE2(3) +#define GPIO_WIMAX_INT EXYNOS4_GPX1(1) +#define GPIO_WIMAX_I2C_CON EXYNOS4210_GPE1(6) +#define GPIO_WIMAX_DBGEN_28V EXYNOS4_GPA0(4) +#define GPIO_UART_SEL1 EXYNOS4_GPB(0) +#define GPIO_CMC_SCL_18V EXYNOS4_GPY0(0) +#define GPIO_CMC_SDA_18V EXYNOS4_GPY0(1) +#endif + #endif #endif /* __MACH_GPIO_U1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-u1camera.h b/arch/arm/mach-exynos/include/mach/gpio-u1camera.h deleted file mode 100644 index 5d7b8c5..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-u1camera.h +++ /dev/null @@ -1,296 +0,0 @@ -#ifndef __MACH_GPIO_U1CAMERA_H -#define __MACH_GPIO_U1CAMERA_H __FILE__ - -#ifdef CONFIG_MACH_U1_KOR_LGT -#define DUMMY_GPIO EXYNOS4_GPL2(2) -#endif -#if defined(CONFIG_MACH_U1CAMERA_BD) - -#define GPIO_XMMC0_CDn EXYNOS4_GPK0(2) - -#define GPIO_PS_ALS_SDA EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_SCL EXYNOS4_GPK3(2) - -#define GPIO_GYRO_INT 0/*EXYNOS4_GPX0(0)*/ -#define GPIO_GYRO_FIFOP_INT 0/*EXYNOS4_GPX0(1)*/ -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_BUCK1_EN_A EXYNOS4_GPX0(5) -#define GPIO_BUCK1_EN_B EXYNOS4_GPX0(6) -#define GPIO_BUCK2_EN EXYNOS4_GPL0(0) -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) - -#define GPIO_VOL_UP EXYNOS4_GPX2(0) -#define GPIO_VOL_DOWN EXYNOS4_GPX2(1) -#define GPIO_nPOWER EXYNOS4_GPX2(7) - -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define VT_CAM_SDA_18V EXYNOS4_GPC1(0) -#define VT_CAM_SCL_18V EXYNOS4_GPC1(2) - -#define CODEC_VT_SDA_18V EXYNOS4_GPC1(3) -#define CODEC_VT_SCL_18V EXYNOS4_GPC1(4) -#ifdef CONFIG_MACH_U1_KOR_LGT -#define GPIO_ISP_RESET EXYNOS4210_GPE0(4) -#else -#define GPIO_ISP_RESET EXYNOS4_GPY3(7) -#endif -#ifdef CONFIG_MACH_U1_KOR_LGT -#define GPIO_FUEL_SDA EXYNOS4210_GPE1(7) -#define GPIO_FUEL_SCL EXYNOS4210_GPE2(0) -#else -#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) -#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) -#endif -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) - -#define GPIO_USB_SDA EXYNOS4210_GPE1(0) -#define GPIO_USB_SCL EXYNOS4210_GPE1(1) -#define GPIO_MASSMEM_EN EXYNOS4_GPL1(1) -#define GPIO_MASSMEM_EN_LEVEL 0 -#define GPIO_TSP_INT EXYNOS4_GPX0(4) - -#define GPIO_CAM_IO_EN EXYNOS4210_GPE2(1) -#define GPIO_CAM_SENSOR_CORE EXYNOS4210_GPE2(5) -#define GPIO_TSP_LDO_ON EXYNOS4_GPL0(3) - -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_UART_SEL EXYNOS4_GPY4(7) -#else -#define GPIO_UART_SEL EXYNOS4_GPL2(7) -#endif - -#define GPIO_3_TOUCH_SCL EXYNOS4_GPK1(0) -#define GPIO_8M_AF_EN EXYNOS4_GPK1(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPK1(2) -#define GPIO_3_TOUCH_INT EXYNOS4_GPL0(5) - -#define GPIO_VT_CAM_15V EXYNOS4210_GPE2(2) - -#define GPIO_CAM_MCLK EXYNOS4210_GPJ1(3) - -#define GPIO_CAM_VGA_nSTBY EXYNOS4_GPL2(0) -#define GPIO_CAM_VGA_nRST EXYNOS4_GPL2(1) - -#define GPIO_DET_35 EXYNOS4_GPX3(2) -#define GPIO_DET_35_AF 0xF - -#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) -#define GPIO_EAR_SEND_END_AF 0xF - -#define GPIO_GPS_nRST EXYNOS4_GPL0(6) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL0(7) - -#define GPIO_GPS_RXD EXYNOS4_GPA0(0) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(1) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(2) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(3) -#define GPIO_GPS_RTS_AF 2 - - -#if defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_BOOT_SW_SEL EXYNOS4_GPA0(6) -#define GPIO_USB_BOOT_EN EXYNOS4_GPA0(7) -#endif - -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_NFC_SCL EXYNOS4_GPY0(0) -#else -#define GPIO_NFC_SCL DUMMY_GPIO -#endif -#define GPIO_NFC_SDA EXYNOS4_GPY0(1) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRM EXYNOS4_GPL2(7) - -#define GPIO_2MIC_PWDN EXYNOS4_GPL2(3) -#define GPIO_2MIC_RST EXYNOS4_GPL2(4) -#define GPIO_2MIC_EN EXYNOS4_GPL2(5) - -#ifdef CONFIG_CHARGER_MAX8922_U1 /* sub-charger */ -#define GPIO_CHG_EN EXYNOS4_GPL2(2) -#define GPIO_CHG_ING_N EXYNOS4_GPL2(4) -#define GPIO_TA_nCONNECTED EXYNOS4_GPL2(5) -#endif - -#define GPIO_2MIC_SDA EXYNOS4_GPC1(2) -#define GPIO_2MIC_SCL EXYNOS4_GPC1(0) - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_PHONE_ON EXYNOS4_GPC1(1) - -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) -#else -#define GPIO_CP_DUMP_INT DUMMY_GPIO -#endif -#if defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_CP_RST_MSM EXYNOS4_GPL2(6) -#endif -#define GPIO_CP_REQ_RESET EXYNOS4_GPY4(6) - -#define GPIO_S1_KEY EXYNOS4_GPX0(0) -#define GPIO_S2_KEY EXYNOS4_GPX0(1) - -#define GPIO_TELE_KEY EXYNOS4_GPX2(6) -#define GPIO_WIDE_KEY EXYNOS4_GPX3(1) -#define GPIO_RSERVED_KEY EXYNOS4_GPX1(0) -#define GPIO_PLAY_KEY EXYNOS4_GPX1(1) -#define GPIO_RECORD_KEY EXYNOS4_GPX1(2) -#define GPIO_MENU_KEY EXYNOS4_GPX1(3) -#define GPIO_ROTARY_PUSH EXYNOS4_GPX1(4) -#define GPIO_ISP_INT EXYNOS4_GPX1(5) -#define GPIO_HOME_KEY EXYNOS4_GPX1(6) -#define GPIO_BACK_KEY EXYNOS4_GPX1(7) -#define GPIO_NFC_IRQ EXYNOS4_GPL2(6) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPL2(6) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPL2(6) -#define GPIO_CP_RST EXYNOS4_GPL2(6) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPL2(6) -#define GPIO_CP_DUMP_INT EXYNOS4_GPL2(6) - - -#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) - -#define IRQ_PHONE_ACTIVE IRQ_EINT14 -#define IRQ_SUSPEND_REQUEST IRQ_EINT11 -#define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 - -#define GPIO_WLAN_EN EXYNOS4_GPL1(2) -#define GPIO_WLAN_EN_AF 1 - -#define GPIO_BT_EN EXYNOS4_GPL0(4) -#define GPIO_BT_nRST EXYNOS4_GPL1(0) - -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF - -#define GPIO_BT_HOST_WAKE 0/*EXYNOS4_GPX2(6)*/ -#define GPIO_BT_HOST_WAKE_AF 0xF -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_WAKE 0/*EXYNOS4_GPX3(1)*/ - -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 - -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 - -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 - -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 - -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 - -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_HW_REV0 EXYNOS4210_GPE1(0) -#define GPIO_HW_REV1 EXYNOS4210_GPE1(1) -#define GPIO_HW_REV2 EXYNOS4210_GPE1(2) -#define GPIO_HW_REV3 EXYNOS4210_GPE1(3) - -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4210_GPJ1(4) -#define GPIO_MHL_WAKE_UP_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_SEL EXYNOS4_GPL0(1) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_MSENSE_INT EXYNOS4_GPX2(2) -#define GPIO_HDMI_EN EXYNOS4_GPX2(4) -#define GPIO_HDMI_EN_REV07 EXYNOS4_GPL1(1) -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_ACC_INT EXYNOS4_GPX3(0) -#define GPIO_USB_OTG_EN EXYNOS4_GPX3(3) - -#define GPIO_MSENSOR_MHL_SDA_28V EXYNOS4_GPD0(2) -#define GPIO_MSENSOR_MHL_SDA_AF 0x3 -#define GPIO_MSENSOR_MHL_SCL_28V EXYNOS4_GPD0(3) -#define GPIO_MSENSOR_MHL_SCL_AF 0x3 -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) -#define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) -#else -#define GPIO_MHL_SDA_18V EXYNOS4210_GPE1(6) -#define GPIO_MHL_SCL_18V EXYNOS4210_GPE1(5) -#endif - -#define GPIO_AP_HDMI_SDA GPIO_MSENSOR_MHL_SDA_28V -#define GPIO_AP_HDMI_SDA_AF GPIO_MSENSOR_MHL_SDA_AF -#define GPIO_AP_HDMI_SCL GPIO_MSENSOR_MHL_SCL_28V -#define GPIO_AP_HDMI_SCL_AF GPIO_MSENSOR_MHL_SCL_AF -#define GPIO_AP_SDA_18V GPIO_MHL_SDA_18V -#define GPIO_AP_SCL_18V GPIO_MHL_SCL_18V - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_MIC_BIAS_EN EXYNOS4210_GPE1(4) -#ifdef CONFIG_MACH_U1_KOR_LGT -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4210_GPE0(2) -#else -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4210_GPE2(0) -#endif -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4210_GPE2(4) - -#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) -#define GPIO_TDMB_EN EXYNOS4_GPC0(1) -#define GPIO_TDMB_RST_N EXYNOS4_GPB(5) -#define GPIO_TDMB_INT EXYNOS4_GPB(4) -#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) -#define GPIO_TDMB_INT_AF 0xf -#define GPIO_TDMB_SPI_CLK EXYNOS4_GPB(0) -#define GPIO_TDMB_SPI_CS EXYNOS4_GPB(1) -#define GPIO_TDMB_SPI_MISO EXYNOS4_GPB(2) -#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPB(3) -#endif -#ifdef CONFIG_FM_SI4709_MODULE -#define GPIO_FM_RST EXYNOS4_GPB(0) -#define GPIO_FM_INT EXYNOS4_GPB(1) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX2(4) -#define GPIO_FM_SDA_28V EXYNOS4_GPB(2) -#define GPIO_FM_SCL_28V EXYNOS4_GPB(3) -#endif - -#ifdef CONFIG_ISDBT_FC8100 -#define GPIO_ISDBT_SCL_28V EXYNOS4210_GPE1(6) -#define GPIO_ISDBT_SDA_28V EXYNOS4210_GPE1(7) -#define GPIO_ISDBT_PWR_EN EXYNOS4_GPC0(1) -#define GPIO_ISDBT_RST EXYNOS4210_GPE1(5) -#endif - -#if defined(CONFIG_MACH_U1_KOR_LGT) -/* Definitions for DPRAM */ -#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) -#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) -#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) -#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) -#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) -#define GPIO_DPRAM_LBN EXYNOS4_GPY1(0) -#define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) -#endif - -#endif -#endif /* __MACH_GPIO_U1CAMERA_H */ diff --git a/arch/arm/mach-exynos/include/mach/grande-jack.h b/arch/arm/mach-exynos/include/mach/grande-jack.h new file mode 100644 index 0000000..055bc49 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/grande-jack.h @@ -0,0 +1,25 @@ +/* + * grande-jack.h - Jack Management of GRANDE Project + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __GRANDE_H__ +#define __GRANDE_H__ __FILE__ + +void grande_jack_init(void); +void sec_set_jack_micbias(bool); + +#endif /* __GRANDE_JACK_H__ */ diff --git a/arch/arm/mach-exynos/include/mach/grande-power.h b/arch/arm/mach-exynos/include/mach/grande-power.h new file mode 100644 index 0000000..2512f4d --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/grande-power.h @@ -0,0 +1,39 @@ +/* + * grande-power.h - Power Management of MIDAS Project + * + * Copyright (C) 2011 Samsung Electrnoics + * Chiwoong Byun <woong.byun@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __GRANDE_POWER_H +#define __GRANDE_POWER_H __FILE__ + +#if defined(CONFIG_MFD_S5M_CORE) +extern struct s5m_platform_data exynos4_s5m8767_info; +#else +#ifdef CONFIG_REGULATOR_LP8720 +extern struct lp8720_platform_data folder_pmic_info; +extern struct lp8720_platform_data sub_pmic_info; +#endif +extern struct max77686_platform_data exynos4_max77686_info; +extern struct max8997_platform_data exynos4_max8997_info; +#endif + +void midas_power_init(void); +void midas_power_set_muic_pdata(void *, int); +void midas_power_gpio_init(void); +#endif /* __GRANDE_POWER_H */ diff --git a/arch/arm/mach-exynos/include/mach/gsd4t.h b/arch/arm/mach-exynos/include/mach/gsd4t.h new file mode 100644 index 0000000..d12d9f1 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gsd4t.h @@ -0,0 +1,28 @@ +/* linux/arm/arch/mach-s5pv310/gsd4t.h + * + * GSD4T(GPS) platform driver data + * + * Copyright (c) 2011 Samsung Electronics + * Minho Ban <mhban@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _GSD4T_H +#define _GSD4T_H + +struct gsd4t_platform_data { + unsigned int onoff; + unsigned int nrst; + unsigned int tsync; + unsigned int uart_rxd; + unsigned int uart_txd; + unsigned int uart_cts; + unsigned int uart_rts; +}; + +#endif /* _GSD4T_H */ + + diff --git a/arch/arm/mach-exynos/include/mach/map-exynos4.h b/arch/arm/mach-exynos/include/mach/map-exynos4.h index 0a22891..666a824 100644..100755 --- a/arch/arm/mach-exynos/include/mach/map-exynos4.h +++ b/arch/arm/mach-exynos/include/mach/map-exynos4.h @@ -32,6 +32,10 @@ #define EXYNOS4212_PA_I2S1 0x13960000 #define EXYNOS4212_PA_I2S2 0x13970000 +/* NAND */ +#define EXYNOS4_PA_NAND (0x0CE00000) +#define S5P_PA_NAND EXYNOS4_PA_NAND + #define EXYNOS4_PA_PCM0 0x03840000 #define EXYNOS4_PA_PCM1 0x13980000 #define EXYNOS4_PA_PCM2 0x13990000 @@ -316,4 +320,9 @@ #define S5P_SZ_UART SZ_256 +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define EXYNOS4_PA_MODEMIF (0x13A00000) +#define S5P_PA_MODEMIF EXYNOS4_PA_MODEMIF +#endif + #endif /* __ASM_ARCH_MAP_EXYNOS4_H */ diff --git a/arch/arm/mach-exynos/include/mach/map-exynos5.h b/arch/arm/mach-exynos/include/mach/map-exynos5.h deleted file mode 100644 index 536356e..0000000 --- a/arch/arm/mach-exynos/include/mach/map-exynos5.h +++ /dev/null @@ -1,295 +0,0 @@ -/* linux/arch/arm/mach-exynos/include/mach/map-exynos5.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS5 - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_MAP_EXYNOS5_H -#define __ASM_ARCH_MAP_EXYNOS5_H __FILE__ - -#define EXYNOS5_PA_SYSRAM 0x02020000 -#define EXYNOS5_PA_SYSRAM_NS 0x0204F000 - -#define EXYNOS5_PA_CHIPID 0x10000000 - -#define EXYNOS5_PA_CMU 0x10010000 - -#define EXYNOS5_PA_PMU 0x10040000 - -#define EXYNOS5_PA_HDMI_CEC 0x101B0000 -#define EXYNOS5_PA_SYSTIMER 0x101C0000 -#define EXYNOS5_PA_WATCHDOG 0x101D0000 -#define EXYNOS5_PA_RTC 0x101E0000 - -#define EXYNOS5_PA_COMBINER 0x10440000 - -#define EXYNOS5250_REV0_PA_GIC_CPU 0x10480000 -#define EXYNOS5250_REV0_PA_GIC_DIST 0x10490000 -#define EXYNOS5250_REV1_PA_GIC_CPU 0x10482000 -#define EXYNOS5250_REV1_PA_GIC_DIST 0x10481000 - -#define EXYNOS5_PA_SYSCON 0x10050000 -#define EXYNOS5_PA_TMU 0x10060000 -#define EXYNOS5_PA_ACE 0x10830000 - -#define EXYNOS5_PA_DMC_PHY0 0x10C00000 -#define EXYNOS5_PA_DMC_PHY1 0x10C10000 -#define EXYNOS5_PA_DMC 0x10DD0000 - -#define EXYNOS5_PA_PPMU_DDR_C 0x10C40000 -#define EXYNOS5_PA_PPMU_DDR_R1 0x10C50000 -#define EXYNOS5_PA_PPMU_CPU 0x10C60000 -#define EXYNOS5_PA_PPMU_DDR_L 0x10CB0000 -#define EXYNOS5_PA_PPMU_RIGHT0_BUS 0x13660000 - -#define EXYNOS5_PA_C2C 0x10E00000 -#define EXYNOS5_PA_C2C_CP 0x10E40000 - -#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000 -#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000 -#define EXYNOS5_PA_SYSMMU_2D 0x10A60000 -#define EXYNOS5_PA_SYSMMU_MFC_R 0x11200000 -#define EXYNOS5_PA_SYSMMU_MFC_L 0x11210000 -#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000 -#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000 -#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000 -#define EXYNOS5_PA_SYSMMU_IOP 0x12360000 -#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000 -#define EXYNOS5_PA_SYSMMU_GPS 0x12630000 -#define EXYNOS5_PA_SYSMMU_ISP 0x13260000 -#define EXYNOS5_PA_SYSMMU_DRC 0x13270000 -#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000 -#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000 -#define EXYNOS5_PA_SYSMMU_FD 0x132A0000 -#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000 -#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000 -#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000 -#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000 -#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000 -#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000 -#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000 -#define EXYNOS5_PA_SYSMMU_LITE2 0x13CA0000 -#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000 -#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000 -#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000 -#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000 -#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000 -#define EXYNOS5_PA_SYSMMU_TV 0x14650000 - -#define EXYNOS5_PA_FIMG2D 0x10850000 -#define EXYNOS5_PA_MFC 0x11000000 - -#define EXYNOS5_PA_GPIO1 0x11400000 -#define EXYNOS5_PA_GPIO2 0x13400000 -#define EXYNOS5_PA_GPIO3 0x10D10000 -#define EXYNOS5_PA_GPIO4 0x03860000 - -#define EXYNOS5_PA_G3D 0x11800000 - -#define EXYNOS5_PA_HSMMC(x) (0x12200000 + ((x) * 0x10000)) -#define EXYNOS5_PA_DWMCI 0x12240000 - -#define EXYNOS5_PA_SS_UDC 0x1200C100 -#define EXYNOS5_PA_SS_DRD 0x12000000 -#define EXYNOS5_PA_SS_PHY 0x12100000 -#define EXYNOS5_PA_EHCI 0x12110000 -#define EXYNOS5_PA_OHCI 0x12120000 -#define EXYNOS5_PA_HSPHY 0x12130000 -#define EXYNOS5_PA_HSOTG 0x12140000 - -#define EXYNOS5_PA_SATA_PHY_CTRL 0x12170000 -#define EXYNOS5_PA_SATA_PHY_I2C 0x121D0000 -#define EXYNOS5_PA_SATA_BASE 0x122F0000 - -#define EXYNOS5_PA_SROMC 0x12250000 -#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) - -#define EXYNOS5_PA_UART 0x12C00000 - -#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000)) -#define EXYNOS5_PA_IIC_HDMIPHY 0x12CE0000 - -#define EXYNOS5_PA_ADC 0x12D10000 - -#define EXYNOS5_PA_SPI0 0x12D20000 -#define EXYNOS5_PA_SPI1 0x12D30000 -#define EXYNOS5_PA_SPI2 0x12D40000 - -#define EXYNOS5_PA_TIMER 0x12DD0000 - -#define EXYNOS5_PA_FIMD0 0x13800000 -#define EXYNOS5_PA_FIMD1 0x14400000 -#define EXYNOS5_PA_MIXER 0x14450000 -#define EXYNOS5_PA_DSIM0 0x14500000 -#define EXYNOS5_PA_DP 0x145B0000 -#define EXYNOS5_PA_HDMI 0x14530000 - -#define EXYNOS5_PA_FIMC_IS 0x13000000 - -#define EXYNOS5_PA_FIMC_LITE0 0x13C00000 -#define EXYNOS5_PA_FIMC_LITE1 0x13C10000 -#define EXYNOS5_PA_FIMC_LITE2 0x13C90000 - -#define EXYNOS5_PA_MIPI_CSIS0 0x13C20000 -#define EXYNOS5_PA_MIPI_CSIS1 0x13C30000 - -#define EXYNOS5_PA_GSC0 0x13E00000 -#define EXYNOS5_PA_GSC1 0x13E10000 -#define EXYNOS5_PA_GSC2 0x13E20000 -#define EXYNOS5_PA_GSC3 0x13E30000 - -#define EXYNOS5_PA_ROTATOR 0x11c00000 - -#define EXYNOS5_PA_SDRAM 0x40000000 - -#define EXYNOS5_PA_NS_MDMA0 0x10800000 -#define EXYNOS5_PA_NS_MDMA1 0x11c10000 -#define EXYNOS5_PA_PDMA0 0x121a0000 -#define EXYNOS5_PA_PDMA1 0x121b0000 - -#define EXYNOS5_PA_AUDSS 0x03810000 -#define EXYNOS5_PA_I2S0 0x03830000 -#define EXYNOS5_PA_I2S1 0x12D60000 -#define EXYNOS5_PA_I2S2 0x12D70000 - -#define EXYNOS5_PA_PCM0 0x03840000 -#define EXYNOS5_PA_PCM1 0x12D80000 -#define EXYNOS5_PA_PCM2 0x12D90000 - -#define EXYNOS5_PA_AC97 0x12DA0000 - -#define EXYNOS5_PA_SPDIF 0x12DB0000 -#define EXYNOS4_PA_JPEG 0x11E00000 - -#define EXYNOS5_PA_BTS_CPU 0x10C80000 -#define EXYNOS5_PA_BTS_G3D_ACP 0x10EA0000 -#define EXYNOS5_PA_BTS_MFC0 0x11220000 -#define EXYNOS5_PA_BTS_MFC1 0x11230000 -#define EXYNOS5_PA_BTS_ROTATOR 0x11D60000 -#define EXYNOS5_PA_BTS_MDMA1 0x11D70000 -#define EXYNOS5_PA_BTS_JPEG 0x11F40000 -#define EXYNOS5_PA_BTS_GSCL0 0x13EC0000 -#define EXYNOS5_PA_BTS_GSCL1 0x13ED0000 -#define EXYNOS5_PA_BTS_GSCL2 0x13EE0000 -#define EXYNOS5_PA_BTS_GSCL3 0x13EF0000 -#define EXYNOS5_PA_BTS_DISP10 0x14660000 -#define EXYNOS5_PA_BTS_DISP11 0x14670000 -#define EXYNOS5_PA_BTS_TV0 0x14690000 -#define EXYNOS5_PA_BTS_TV1 0x146A0000 -#define EXYNOS5_PA_BTS_C2C 0x10c90000 -#define EXYNOS5_PA_FBM_DDR_R1 0x10c30000 -#define EXYNOS5_PA_FBM_DDR_R0 0x10dc0000 -#define EXYNOS5_PA_BTS_FIMC_ISP 0x13300000 -#define EXYNOS5_PA_BTS_FIMC_SCALER_C 0x13320000 -#define EXYNOS5_PA_BTS_FIMC_SCALER_P 0x13330000 -#define EXYNOS5_PA_BTS_FIMC_FD 0x13340000 -#define EXYNOS5_PA_BTS_FIMC_ODC 0x13370000 -#define EXYNOS5_PA_BTS_FIMC_DIS0 0x13380000 -#define EXYNOS5_PA_BTS_FIMC_DIS1 0x13390000 -#define EXYNOS5_PA_BTS_FIMC_3DNR 0x133A0000 - -/* Compatibiltiy Defines */ - -#define EXYNOS_PA_DWMCI EXYNOS5_PA_DWMCI - -#define EXYNOS_PA_SPI0 EXYNOS5_PA_SPI0 -#define EXYNOS_PA_SPI1 EXYNOS5_PA_SPI1 -#define EXYNOS_PA_SPI2 EXYNOS5_PA_SPI2 - -#define S5P_PA_HDMI_CEC EXYNOS5_PA_HDMI_CEC - -#define S3C_PA_HSMMC0 EXYNOS5_PA_HSMMC(0) -#define S3C_PA_HSMMC1 EXYNOS5_PA_HSMMC(1) -#define S3C_PA_HSMMC2 EXYNOS5_PA_HSMMC(2) -#define S3C_PA_HSMMC3 EXYNOS5_PA_HSMMC(3) - -#define EXYNOS_PA_AUDSS EXYNOS5_PA_AUDSS -#define EXYNOS_PA_I2S0 EXYNOS5_PA_I2S0 -#define EXYNOS_PA_I2S1 EXYNOS5_PA_I2S1 -#define EXYNOS_PA_I2S2 EXYNOS5_PA_I2S2 - -#define EXYNOS_PA_PCM0 EXYNOS5_PA_PCM0 -#define EXYNOS_PA_PCM1 EXYNOS5_PA_PCM1 -#define EXYNOS_PA_PCM2 EXYNOS5_PA_PCM2 - -#define EXYNOS_PA_AC97 EXYNOS5_PA_AC97 - -#define EXYNOS_PA_SPDIF EXYNOS5_PA_SPDIF - -#define EXYNOS_PA_FIMC_LITE0 EXYNOS5_PA_FIMC_LITE0 -#define EXYNOS_PA_FIMC_LITE1 EXYNOS5_PA_FIMC_LITE1 -#define EXYNOS_PA_FIMC_LITE2 EXYNOS5_PA_FIMC_LITE2 - -#define EXYNOS_PA_ROTATOR EXYNOS5_PA_ROTATOR - -#define EXYNOS_PA_C2C EXYNOS5_PA_C2C -#define EXYNOS_PA_C2C_CP EXYNOS5_PA_C2C_CP - -#define S3C_PA_IIC EXYNOS5_PA_IIC(0) -#define S3C_PA_IIC1 EXYNOS5_PA_IIC(1) -#define S3C_PA_IIC2 EXYNOS5_PA_IIC(2) -#define S3C_PA_IIC3 EXYNOS5_PA_IIC(3) -#define S3C_PA_IIC4 EXYNOS5_PA_IIC(4) -#define S3C_PA_IIC5 EXYNOS5_PA_IIC(5) -#define S3C_PA_IIC6 EXYNOS5_PA_IIC(6) -#define S3C_PA_IIC7 EXYNOS5_PA_IIC(7) -#define SAMSUNG_PA_ADC EXYNOS5_PA_ADC -#define S5P_PA_IIC_HDMIPHY EXYNOS5_PA_IIC_HDMIPHY -#define S3C_PA_WDT EXYNOS5_PA_WATCHDOG -#define S3C_PA_RTC EXYNOS5_PA_RTC -#define S5P_PA_CHIPID EXYNOS5_PA_CHIPID -#define S5P_PA_SYSCON EXYNOS5_PA_SYSCON -#define S5P_PA_SROMC EXYNOS5_PA_SROMC -#define S5P_PA_TIMER EXYNOS5_PA_TIMER -#define S5P_PA_HSOTG EXYNOS5_PA_HSOTG -#define S5P_PA_MFC EXYNOS5_PA_MFC -#define S5P_PA_HSPHY EXYNOS5_PA_HSPHY -#define S5P_PA_EHCI EXYNOS5_PA_EHCI -#define S5P_PA_OHCI EXYNOS5_PA_OHCI -#define S5P_PA_FIMD0 EXYNOS5_PA_FIMD0 -#define S5P_PA_FIMD1 EXYNOS5_PA_FIMD1 -#define S5P_PA_MIXER EXYNOS5_PA_MIXER -#define S5P_PA_DP EXYNOS5_PA_DP -#define S5P_PA_HDMI EXYNOS5_PA_HDMI -#define S5P_PA_SDRAM EXYNOS5_PA_SDRAM -#define S5P_PA_FIMG2D EXYNOS5_PA_FIMG2D - -#define S5P_PA_MDMA0 EXYNOS5_PA_NS_MDMA0 -#define S5P_PA_MDMA1 EXYNOS5_PA_NS_MDMA1 -#define S5P_PA_PDMA0 EXYNOS5_PA_PDMA0 -#define S5P_PA_PDMA1 EXYNOS5_PA_PDMA1 -#define S5P_PA_DSIM0 EXYNOS5_PA_DSIM0 -#define S5P_PA_JPEG EXYNOS4_PA_JPEG -#define S5P_PA_MIPI_CSIS0 EXYNOS5_PA_MIPI_CSIS0 -#define S5P_PA_MIPI_CSIS1 EXYNOS5_PA_MIPI_CSIS1 - -#define S5P_PA_ACE EXYNOS5_PA_ACE -#define S5P_PA_TMU EXYNOS5_PA_TMU -/* UART */ - -#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) - -#define S3C_PA_UART EXYNOS5_PA_UART - -#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) -#define S5P_PA_UART0 S5P_PA_UART(0) -#define S5P_PA_UART1 S5P_PA_UART(1) -#define S5P_PA_UART2 S5P_PA_UART(2) -#define S5P_PA_UART3 S5P_PA_UART(3) -#define S5P_PA_UART4 S5P_PA_UART(4) - -#define S5P_SZ_HDMI_CEC SZ_64K - -#define S5P_SZ_UART SZ_256 - -#define S5P_SZ_MIXER SZ_64K -#define S5P_SZ_HDMI SZ_1M -#define S5P_SZ_IIC_HDMIPHY SZ_64K - -#endif /* __ASM_ARCH_MAP_EXYNOS5_H */ diff --git a/arch/arm/mach-exynos/include/mach/mdm2.h b/arch/arm/mach-exynos/include/mach/mdm2.h index 78ca88f..61d875c 100644 --- a/arch/arm/mach-exynos/include/mach/mdm2.h +++ b/arch/arm/mach-exynos/include/mach/mdm2.h @@ -13,10 +13,34 @@ #ifndef _ARCH_ARM_MACH_MSM_MDM2_H #define _ARCH_ARM_MACH_MSM_MDM2_H +struct mdm_vddmin_resource { + int rpm_id; + int ap2mdm_vddmin_gpio; + unsigned int modes; + unsigned int drive_strength; + int mdm2ap_vddmin_gpio; +}; + struct mdm_platform_data { char *mdm_version; int ramdump_delay_ms; - struct platform_device *peripheral_platform_device; + int soft_reset_inverted; + int early_power_on; + int sfr_query; + int no_powerdown_after_ramdumps; + struct mdm_vddmin_resource *vddmin_resource; + struct platform_device *peripheral_platform_device_ehci; + struct platform_device *peripheral_platform_device_ohci; + const unsigned int ramdump_timeout_ms; +}; + +struct mdm_hsic_pm_platform_data { + /* cpu/bus frequency lock */ + atomic_t freqlock; + int (*freq_lock)(struct device *dev); + int (*freq_unlock)(struct device *dev); + + struct device *dev; }; #endif diff --git a/arch/arm/mach-exynos/include/mach/media.h b/arch/arm/mach-exynos/include/mach/media.h index ce0e53e..366d0fe 100644 --- a/arch/arm/mach-exynos/include/mach/media.h +++ b/arch/arm/mach-exynos/include/mach/media.h @@ -26,7 +26,7 @@ #define S5P_MDEV_TVOUT 9 -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) #define S5P_MDEV_PMEM 10 #endif diff --git a/arch/arm/mach-exynos/include/mach/midas-tsp.h b/arch/arm/mach-exynos/include/mach/midas-tsp.h index 4cbee4c..6e71902 100644 --- a/arch/arm/mach-exynos/include/mach/midas-tsp.h +++ b/arch/arm/mach-exynos/include/mach/midas-tsp.h @@ -13,6 +13,8 @@ #if defined(CONFIG_TOUCHSCREEN_MELFAS) #include <linux/platform_data/mms_ts.h> +#elif defined(CONFIG_TOUCHSCREEN_CYTTSP4) +#include <linux/platform_data/cypress_cyttsp4.h> #else #include <linux/melfas_ts.h> #endif @@ -20,7 +22,15 @@ extern int melfas_power(int on); void melfas_set_touch_i2c(void); void melfas_set_touch_i2c_to_gpio(void); +#if defined(CONFIG_TOUCHSCREEN_CYTTSP4) +int cyttsp4_hw_reset(void); +int cyttsp4_hw_power(int on); +int cyttsp4_hw_recov(int on); +int cyttsp4_irq_stat(void); +void midas_tsp_set_platdata(struct touch_platform_data *pdata); +#else void midas_tsp_set_platdata(struct melfas_tsi_platform_data *pdata); +#endif void midas_tsp_init(void); int is_melfas_vdd_on(void); int melfas_mux_fw_flash(bool to_gpios); diff --git a/arch/arm/mach-exynos/include/mach/midas-wacom.h b/arch/arm/mach-exynos/include/mach/midas-wacom.h new file mode 100644 index 0000000..24a0e1c --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/midas-wacom.h @@ -0,0 +1,24 @@ +/* + * linux/arch/arm/mach-exynos/include/mach/midas-wacom.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MIDAS_WACOM_H +#define __MIDAS_WACOM_H __FILE__ + +#include <linux/wacom_i2c.h> + +void midas_wacom_init(void); + +#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_FLEXRATE +extern void midas_wacom_request_qos(void *data); +#else +#define midas_wacom_request_qos NULL +#endif + +#endif /* __MIDAS_WACOM_H */ diff --git a/arch/arm/mach-exynos/include/mach/mipi_ddi.h b/arch/arm/mach-exynos/include/mach/mipi_ddi.h index 17fae16..0b8deb1 100644 --- a/arch/arm/mach-exynos/include/mach/mipi_ddi.h +++ b/arch/arm/mach-exynos/include/mach/mipi_ddi.h @@ -58,6 +58,9 @@ struct mipi_ddi_platform_data { unsigned int reset_delay; unsigned int power_on_delay; unsigned int power_off_delay; +#if defined(CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD) + unsigned int lcd_sel_pin; +#endif /* CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD */ }; #endif /* _MIPI_DDI_H */ diff --git a/arch/arm/mach-exynos/include/mach/msm_smd.h b/arch/arm/mach-exynos/include/mach/msm_smd.h new file mode 100644 index 0000000..d896013 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/msm_smd.h @@ -0,0 +1,383 @@ +/* linux/include/asm-arm/arch-msm/msm_smd.h + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_SMD_H +#define __ASM_ARCH_MSM_SMD_H + +#include <linux/io.h> +#include <mach/msm_smsm.h> + +typedef struct smd_channel smd_channel_t; + +#define SMD_MAX_CH_NAME_LEN 20 /* includes null char at end */ + +#define SMD_EVENT_DATA 1 +#define SMD_EVENT_OPEN 2 +#define SMD_EVENT_CLOSE 3 +#define SMD_EVENT_STATUS 4 +#define SMD_EVENT_REOPEN_READY 5 + +/* + * SMD Processor ID's. + * + * For all processors that have both SMSM and SMD clients, + * the SMSM Processor ID and the SMD Processor ID will + * be the same. In cases where a processor only supports + * SMD, the entry will only exist in this enum. + */ +enum { + SMD_APPS = SMSM_APPS, + SMD_MODEM = SMSM_MODEM, + SMD_Q6 = SMSM_Q6, + SMD_WCNSS = SMSM_WCNSS, + SMD_DSPS = SMSM_DSPS, + SMD_MODEM_Q6_FW, + SMD_RPM, + NUM_SMD_SUBSYSTEMS, +}; + +enum { + SMD_APPS_MODEM = 0, + SMD_APPS_QDSP, + SMD_MODEM_QDSP, + SMD_APPS_DSPS, + SMD_MODEM_DSPS, + SMD_QDSP_DSPS, + SMD_APPS_WCNSS, + SMD_MODEM_WCNSS, + SMD_QDSP_WCNSS, + SMD_DSPS_WCNSS, + SMD_APPS_Q6FW, + SMD_MODEM_Q6FW, + SMD_QDSP_Q6FW, + SMD_DSPS_Q6FW, + SMD_WCNSS_Q6FW, + SMD_APPS_RPM, + SMD_MODEM_RPM, + SMD_QDSP_RPM, + SMD_WCNSS_RPM, + SMD_NUM_TYPE, + SMD_LOOPBACK_TYPE = 100, + +}; + +/* + * SMD IRQ Configuration + * + * Used to initialize IRQ configurations from platform data + * + * @irq_name: irq_name to query platform data + * @irq_id: initialized to -1 in platform data, stores actual irq id on + * successful registration + * @out_base: if not null then settings used for outgoing interrupt + * initialied from platform data + */ + +struct smd_irq_config { + /* incoming interrupt config */ + const char *irq_name; + unsigned long flags; + int irq_id; + const char *device_name; + const void *dev_id; + + /* outgoing interrupt config */ + uint32_t out_bit_pos; + void __iomem *out_base; + uint32_t out_offset; +}; + +/* + * SMD subsystem configurations + * + * SMD subsystems configurations for platform data. This contains the + * M2A and A2M interrupt configurations for both SMD and SMSM per + * subsystem. + * + * @subsys_name: name of subsystem passed to PIL + * @irq_config_id: unique id for each subsystem + * @edge: maps to actual remote subsystem edge + * + */ +struct smd_subsystem_config { + unsigned irq_config_id; + const char *subsys_name; + int edge; + + struct smd_irq_config smd_int; + struct smd_irq_config smsm_int; + +}; + +/* + * Subsystem Restart Configuration + * + * @disable_smsm_reset_handshake + */ +struct smd_subsystem_restart_config { + int disable_smsm_reset_handshake; +}; + +struct smd_platform { + uint32_t num_ss_configs; + struct smd_subsystem_config *smd_ss_configs; + struct smd_subsystem_restart_config *smd_ssr_config; +}; + +#ifdef CONFIG_MSM_SMD +/* warning: notify() may be called before open returns */ +int smd_open(const char *name, smd_channel_t **ch, void *priv, + void (*notify)(void *priv, unsigned event)); + +int smd_close(smd_channel_t *ch); + +/* passing a null pointer for data reads and discards */ +int smd_read(smd_channel_t *ch, void *data, int len); +int smd_read_from_cb(smd_channel_t *ch, void *data, int len); +/* Same as smd_read() but takes a data buffer from userspace + * The function might sleep. Only safe to call from user context + */ +int smd_read_user_buffer(smd_channel_t *ch, void *data, int len); + +/* Write to stream channels may do a partial write and return +** the length actually written. +** Write to packet channels will never do a partial write -- +** it will return the requested length written or an error. +*/ +int smd_write(smd_channel_t *ch, const void *data, int len); +/* Same as smd_write() but takes a data buffer from userspace + * The function might sleep. Only safe to call from user context + */ +int smd_write_user_buffer(smd_channel_t *ch, const void *data, int len); + +int smd_write_avail(smd_channel_t *ch); +int smd_read_avail(smd_channel_t *ch); + +/* Returns the total size of the current packet being read. +** Returns 0 if no packets available or a stream channel. +*/ +int smd_cur_packet_size(smd_channel_t *ch); + + +#if 0 +/* these are interruptable waits which will block you until the specified +** number of bytes are readable or writable. +*/ +int smd_wait_until_readable(smd_channel_t *ch, int bytes); +int smd_wait_until_writable(smd_channel_t *ch, int bytes); +#endif + +/* these are used to get and set the IF sigs of a channel. + * DTR and RTS can be set; DSR, CTS, CD and RI can be read. + */ +int smd_tiocmget(smd_channel_t *ch); +int smd_tiocmset(smd_channel_t *ch, unsigned int set, unsigned int clear); +int +smd_tiocmset_from_cb(smd_channel_t *ch, unsigned int set, unsigned int clear); +int smd_named_open_on_edge(const char *name, uint32_t edge, smd_channel_t **_ch, + void *priv, void (*notify)(void *, unsigned)); + +/* Tells the other end of the smd channel that this end wants to recieve + * interrupts when the written data is read. Read interrupts should only + * enabled when there is no space left in the buffer to write to, thus the + * interrupt acts as notification that space may be avaliable. If the + * other side does not support enabling/disabling interrupts on demand, + * then this function has no effect if called. + */ +void smd_enable_read_intr(smd_channel_t *ch); + +/* Tells the other end of the smd channel that this end does not want + * interrupts when written data is read. The interrupts should be + * disabled by default. If the other side does not support enabling/ + * disabling interrupts on demand, then this function has no effect if + * called. + */ +void smd_disable_read_intr(smd_channel_t *ch); + +/* Starts a packet transaction. The size of the packet may exceed the total + * size of the smd ring buffer. + * + * @ch: channel to write the packet to + * @len: total length of the packet + * + * Returns: + * 0 - success + * -ENODEV - invalid smd channel + * -EACCES - non-packet channel specified + * -EINVAL - invalid length + * -EBUSY - transaction already in progress + * -EAGAIN - no enough memory in ring buffer to start transaction + * -EPERM - unable to sucessfully start transaction due to write error + */ +int smd_write_start(smd_channel_t *ch, int len); + +/* Writes a segment of the packet for a packet transaction. + * + * @ch: channel to write packet to + * @data: buffer of data to write + * @len: length of data buffer + * @user_buf: (0) - buffer from kernelspace (1) - buffer from userspace + * + * Returns: + * number of bytes written + * -ENODEV - invalid smd channel + * -EINVAL - invalid length + * -ENOEXEC - transaction not started + */ +int smd_write_segment(smd_channel_t *ch, void *data, int len, int user_buf); + +/* Completes a packet transaction. Do not call from interrupt context. + * + * @ch: channel to complete transaction on + * + * Returns: + * 0 - success + * -ENODEV - invalid smd channel + * -E2BIG - some ammount of packet is not yet written + */ +int smd_write_end(smd_channel_t *ch); + +/* + * Returns a pointer to the subsystem name or NULL if no + * subsystem name is available. + * + * @type - Edge definition + */ +const char *smd_edge_to_subsystem(uint32_t type); + +/* + * Returns a pointer to the subsystem name given the + * remote processor ID. + * + * @pid Remote processor ID + * @returns Pointer to subsystem name or NULL if not found + */ +const char *smd_pid_to_subsystem(uint32_t pid); +#else + +static inline int smd_open(const char *name, smd_channel_t **ch, void *priv, + void (*notify)(void *priv, unsigned event)) +{ + return -ENODEV; +} + +static inline int smd_close(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_read(smd_channel_t *ch, void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_read_from_cb(smd_channel_t *ch, void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_read_user_buffer(smd_channel_t *ch, void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_write(smd_channel_t *ch, const void *data, int len) +{ + return -ENODEV; +} + +static inline int +smd_write_user_buffer(smd_channel_t *ch, const void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_write_avail(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_read_avail(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_cur_packet_size(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_tiocmget(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int +smd_tiocmset(smd_channel_t *ch, unsigned int set, unsigned int clear) +{ + return -ENODEV; +} + +static inline int +smd_tiocmset_from_cb(smd_channel_t *ch, unsigned int set, unsigned int clear) +{ + return -ENODEV; +} + +static inline int +smd_named_open_on_edge(const char *name, uint32_t edge, smd_channel_t **_ch, + void *priv, void (*notify)(void *, unsigned)) +{ + return -ENODEV; +} + +static inline void smd_enable_read_intr(smd_channel_t *ch) +{ +} + +static inline void smd_disable_read_intr(smd_channel_t *ch) +{ +} + +static inline int smd_write_start(smd_channel_t *ch, int len) +{ + return -ENODEV; +} + +static inline int +smd_write_segment(smd_channel_t *ch, void *data, int len, int user_buf) +{ + return -ENODEV; +} + +static inline int smd_write_end(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline const char *smd_edge_to_subsystem(uint32_t type) +{ + return NULL; +} + +static inline const char *smd_pid_to_subsystem(uint32_t pid) +{ + return NULL; +} +#endif + +#endif diff --git a/arch/arm/mach-exynos/include/mach/msm_smsm.h b/arch/arm/mach-exynos/include/mach/msm_smsm.h new file mode 100644 index 0000000..5c3307e --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/msm_smsm.h @@ -0,0 +1,250 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ARCH_ARM_MACH_MSM_SMSM_H_ +#define _ARCH_ARM_MACH_MSM_SMSM_H_ + +#include <linux/notifier.h> +#if defined(CONFIG_MSM_N_WAY_SMSM) +enum { + SMSM_APPS_STATE, + SMSM_MODEM_STATE, + SMSM_Q6_STATE, + SMSM_APPS_DEM, + SMSM_WCNSS_STATE = SMSM_APPS_DEM, + SMSM_MODEM_DEM, + SMSM_DSPS_STATE = SMSM_MODEM_DEM, + SMSM_Q6_DEM, + SMSM_POWER_MASTER_DEM, + SMSM_TIME_MASTER_DEM, +}; +extern uint32_t SMSM_NUM_ENTRIES; +#else +enum { + SMSM_APPS_STATE = 1, + SMSM_MODEM_STATE = 3, + SMSM_NUM_ENTRIES, +}; +#endif + +enum { + SMSM_APPS, + SMSM_MODEM, + SMSM_Q6, + SMSM_WCNSS, + SMSM_DSPS, +}; +extern uint32_t SMSM_NUM_HOSTS; + +#define SMSM_INIT 0x00000001 +#define SMSM_OSENTERED 0x00000002 +#define SMSM_SMDWAIT 0x00000004 +#define SMSM_SMDINIT 0x00000008 +#define SMSM_RPCWAIT 0x00000010 +#define SMSM_RPCINIT 0x00000020 +#define SMSM_RESET 0x00000040 +#define SMSM_RSA 0x00000080 +#define SMSM_RUN 0x00000100 +#define SMSM_PWRC 0x00000200 +#define SMSM_TIMEWAIT 0x00000400 +#define SMSM_TIMEINIT 0x00000800 +#define SMSM_PWRC_EARLY_EXIT 0x00001000 +#define SMSM_WFPI 0x00002000 +#define SMSM_SLEEP 0x00004000 +#define SMSM_SLEEPEXIT 0x00008000 +#define SMSM_OEMSBL_RELEASE 0x00010000 +#define SMSM_APPS_REBOOT 0x00020000 +#define SMSM_SYSTEM_POWER_DOWN 0x00040000 +#define SMSM_SYSTEM_REBOOT 0x00080000 +#define SMSM_SYSTEM_DOWNLOAD 0x00100000 +#define SMSM_PWRC_SUSPEND 0x00200000 +#define SMSM_APPS_SHUTDOWN 0x00400000 +#define SMSM_SMD_LOOPBACK 0x00800000 +#define SMSM_RUN_QUIET 0x01000000 +#define SMSM_MODEM_WAIT 0x02000000 +#define SMSM_MODEM_BREAK 0x04000000 +#define SMSM_MODEM_CONTINUE 0x08000000 +#define SMSM_SYSTEM_REBOOT_USR 0x20000000 +#define SMSM_SYSTEM_PWRDWN_USR 0x40000000 +#define SMSM_UNKNOWN 0x80000000 + +#define SMSM_WKUP_REASON_RPC 0x00000001 +#define SMSM_WKUP_REASON_INT 0x00000002 +#define SMSM_WKUP_REASON_GPIO 0x00000004 +#define SMSM_WKUP_REASON_TIMER 0x00000008 +#define SMSM_WKUP_REASON_ALARM 0x00000010 +#define SMSM_WKUP_REASON_RESET 0x00000020 +#define SMSM_A2_FORCE_SHUTDOWN 0x00002000 +#define SMSM_A2_RESET_BAM 0x00004000 + +#define SMSM_VENDOR 0x00020000 + +#define SMSM_A2_POWER_CONTROL 0x00000002 +#define SMSM_A2_POWER_CONTROL_ACK 0x00000800 + +#define SMSM_WLAN_TX_RINGS_EMPTY 0x00000200 +#define SMSM_WLAN_TX_ENABLE 0x00000400 + + +void *smem_alloc(unsigned id, unsigned size); +void *smem_alloc2(unsigned id, unsigned size_in); +void *smem_get_entry(unsigned id, unsigned *size); +int smsm_change_state(uint32_t smsm_entry, + uint32_t clear_mask, uint32_t set_mask); + +/* + * Changes the global interrupt mask. The set and clear masks are re-applied + * every time the global interrupt mask is updated for callback registration + * and de-registration. + * + * The clear mask is applied first, so if a bit is set to 1 in both the clear + * mask and the set mask, the result will be that the interrupt is set. + * + * @smsm_entry SMSM entry to change + * @clear_mask 1 = clear bit, 0 = no-op + * @set_mask 1 = set bit, 0 = no-op + * + * @returns 0 for success, < 0 for error + */ +int smsm_change_intr_mask(uint32_t smsm_entry, + uint32_t clear_mask, uint32_t set_mask); +int smsm_get_intr_mask(uint32_t smsm_entry, uint32_t *intr_mask); +uint32_t smsm_get_state(uint32_t smsm_entry); +int smsm_state_cb_register(uint32_t smsm_entry, uint32_t mask, + void (*notify)(void *, uint32_t old_state, uint32_t new_state), + void *data); +int smsm_state_cb_deregister(uint32_t smsm_entry, uint32_t mask, + void (*notify)(void *, uint32_t, uint32_t), void *data); +int smsm_driver_state_notifier_register(struct notifier_block *nb); +int smsm_driver_state_notifier_unregister(struct notifier_block *nb); +void smsm_print_sleep_info(uint32_t sleep_delay, uint32_t sleep_limit, + uint32_t irq_mask, uint32_t wakeup_reason, uint32_t pending_irqs); +void smsm_reset_modem(unsigned mode); +void smsm_reset_modem_cont(void); +void smd_sleep_exit(void); + +#define SMEM_NUM_SMD_STREAM_CHANNELS 64 +#define SMEM_NUM_SMD_BLOCK_CHANNELS 64 + +enum { + /* fixed items */ + SMEM_PROC_COMM = 0, + SMEM_HEAP_INFO, + SMEM_ALLOCATION_TABLE, + SMEM_VERSION_INFO, + SMEM_HW_RESET_DETECT, + SMEM_AARM_WARM_BOOT, + SMEM_DIAG_ERR_MESSAGE, + SMEM_SPINLOCK_ARRAY, + SMEM_MEMORY_BARRIER_LOCATION, + SMEM_FIXED_ITEM_LAST = SMEM_MEMORY_BARRIER_LOCATION, + + /* dynamic items */ + SMEM_AARM_PARTITION_TABLE, + SMEM_AARM_BAD_BLOCK_TABLE, + SMEM_RESERVE_BAD_BLOCKS, + SMEM_WM_UUID, + SMEM_CHANNEL_ALLOC_TBL, + SMEM_SMD_BASE_ID, + SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_STREAM_CHANNELS, + SMEM_SMEM_LOG_EVENTS, + SMEM_SMEM_STATIC_LOG_IDX, + SMEM_SMEM_STATIC_LOG_EVENTS, + SMEM_SMEM_SLOW_CLOCK_SYNC, + SMEM_SMEM_SLOW_CLOCK_VALUE, + SMEM_BIO_LED_BUF, + SMEM_SMSM_SHARED_STATE, + SMEM_SMSM_INT_INFO, + SMEM_SMSM_SLEEP_DELAY, + SMEM_SMSM_LIMIT_SLEEP, + SMEM_SLEEP_POWER_COLLAPSE_DISABLED, + SMEM_KEYPAD_KEYS_PRESSED, + SMEM_KEYPAD_STATE_UPDATED, + SMEM_KEYPAD_STATE_IDX, + SMEM_GPIO_INT, + SMEM_MDDI_LCD_IDX, + SMEM_MDDI_HOST_DRIVER_STATE, + SMEM_MDDI_LCD_DISP_STATE, + SMEM_LCD_CUR_PANEL, + SMEM_MARM_BOOT_SEGMENT_INFO, + SMEM_AARM_BOOT_SEGMENT_INFO, + SMEM_SLEEP_STATIC, + SMEM_SCORPION_FREQUENCY, + SMEM_SMD_PROFILES, + SMEM_TSSC_BUSY, + SMEM_HS_SUSPEND_FILTER_INFO, + SMEM_BATT_INFO, + SMEM_APPS_BOOT_MODE, + SMEM_VERSION_FIRST, + SMEM_VERSION_SMD = SMEM_VERSION_FIRST, + SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24, + SMEM_OSS_RRCASN1_BUF1, + SMEM_OSS_RRCASN1_BUF2, + SMEM_ID_VENDOR0, + SMEM_ID_VENDOR1, + SMEM_ID_VENDOR2, + SMEM_HW_SW_BUILD_ID, + SMEM_SMD_BLOCK_PORT_BASE_ID, + SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + + SMEM_NUM_SMD_BLOCK_CHANNELS, + SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + + SMEM_NUM_SMD_BLOCK_CHANNELS, + SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + + SMEM_NUM_SMD_BLOCK_CHANNELS, + SMEM_SCLK_CONVERSION, + SMEM_SMD_SMSM_INTR_MUX, + SMEM_SMSM_CPU_INTR_MASK, + SMEM_APPS_DEM_SLAVE_DATA, + SMEM_QDSP6_DEM_SLAVE_DATA, + SMEM_CLKREGIM_BSP, + SMEM_CLKREGIM_SOURCES, + SMEM_SMD_FIFO_BASE_ID, + SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + + SMEM_NUM_SMD_STREAM_CHANNELS, + SMEM_POWER_ON_STATUS_INFO, + SMEM_DAL_AREA, + SMEM_SMEM_LOG_POWER_IDX, + SMEM_SMEM_LOG_POWER_WRAP, + SMEM_SMEM_LOG_POWER_EVENTS, + SMEM_ERR_CRASH_LOG, + SMEM_ERR_F3_TRACE_LOG, + SMEM_SMD_BRIDGE_ALLOC_TABLE, + SMEM_SMDLITE_TABLE, + SMEM_SD_IMG_UPGRADE_STATUS, + SMEM_SEFS_INFO, + SMEM_RESET_LOG, + SMEM_RESET_LOG_SYMBOLS, + SMEM_MODEM_SW_BUILD_ID, + SMEM_SMEM_LOG_MPROC_WRAP, + SMEM_BOOT_INFO_FOR_APPS, + SMEM_SMSM_SIZE_INFO, + SMEM_SMD_LOOPBACK_REGISTER, + SMEM_SSR_REASON_MSS0, + SMEM_SSR_REASON_WCNSS0, + SMEM_SSR_REASON_LPASS0, + SMEM_SSR_REASON_DSPS0, + SMEM_SSR_REASON_VCODEC0, + SMEM_MEM_LAST = SMEM_SSR_REASON_VCODEC0, + SMEM_NUM_ITEMS, +}; + +enum { + SMEM_APPS_Q6_SMSM = 3, + SMEM_Q6_APPS_SMSM = 5, + SMSM_NUM_INTR_MUX = 8, +}; + +int smsm_check_for_modem_crash(void); +void *smem_find(unsigned id, unsigned size); +void *smem_get_entry(unsigned id, unsigned *size); + +#endif diff --git a/arch/arm/mach-exynos/include/mach/p4-input.h b/arch/arm/mach-exynos/include/mach/p4-input.h index b7ecddb..37c71c7 100644 --- a/arch/arm/mach-exynos/include/mach/p4-input.h +++ b/arch/arm/mach-exynos/include/mach/p4-input.h @@ -18,4 +18,8 @@ void p4_key_init(void); extern void synaptics_ts_charger_infom(bool en); #endif +#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S) +extern void ts_charger_infom(bool en); +#endif + #endif /* __P4_INPUT_H */ diff --git a/arch/arm/mach-exynos/include/mach/pld_pdata.h b/arch/arm/mach-exynos/include/mach/pld_pdata.h new file mode 100644 index 0000000..da0c064 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/pld_pdata.h @@ -0,0 +1,2015 @@ +unsigned char fpga_bin[] = { +0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, +0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x22, 0x11, 0x8B, 0x01, 0x06, 0x00}; diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index a0aab7c..a8ce9ff 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -148,6 +148,8 @@ #define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) #define EXYNOS4_CLKOUT_CMU_CPU EXYNOS_CLKREG(0x14A00) +#define EXYNOS4_EMA_CONF EXYNOS_CLKREG(0x15008) + #define EXYNOS4_PMREG(x) (S5P_VA_PMU + (x)) #define EXYNOS4_MIPI_CONTROL0 EXYNOS4_PMREG(0x0710) diff --git a/arch/arm/mach-exynos/include/mach/sec_debug.h b/arch/arm/mach-exynos/include/mach/sec_debug.h index 53ca0cb..1beb973 100644 --- a/arch/arm/mach-exynos/include/mach/sec_debug.h +++ b/arch/arm/mach-exynos/include/mach/sec_debug.h @@ -80,6 +80,8 @@ extern void __sec_debug_task_log(int cpu, struct task_struct *task); extern void __sec_debug_irq_log(unsigned int irq, void *fn, int en); extern void __sec_debug_work_log(struct worker *worker, struct work_struct *work, work_func_t f); +extern void __sec_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en); static inline void sec_debug_task_log(int cpu, struct task_struct *task) { @@ -100,18 +102,25 @@ static inline void sec_debug_work_log(struct worker *worker, __sec_debug_work_log(worker, work, f); } -#ifdef CONFIG_SEC_DEBUG_SOFTIRQ_LOG -static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en) +static inline void sec_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en) { +#ifdef CONFIG_SEC_DEBUG_HRTIMER_LOG if (unlikely(sec_debug_level.en.kernel_fault)) - __sec_debug_irq_log(irq, fn, en); + __sec_debug_hrtimer_log(timer, fn, en); +#endif } -#else + static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en) { -} +#ifdef CONFIG_SEC_DEBUG_SOFTIRQ_LOG + if (unlikely(sec_debug_level.en.kernel_fault)) + __sec_debug_irq_log(irq, fn, en); #endif +} + #else + static inline void sec_debug_task_log(int cpu, struct task_struct *task) { } @@ -125,6 +134,11 @@ static inline void sec_debug_work_log(struct worker *worker, { } +static inline void sec_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en) +{ +} + static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en) { } @@ -181,7 +195,6 @@ static inline void debug_rwsemaphore_up_log(struct rw_semaphore *sem) enum sec_debug_aux_log_idx { SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE, - SEC_DEBUG_AUXLOG_LOGBUF_LOCK_CHANGE, SEC_DEBUG_AUXLOG_ITEM_MAX, }; @@ -191,6 +204,10 @@ extern void sec_debug_aux_log(int idx, char *fmt, ...); #define sec_debug_aux_log(idx, ...) do { } while (0) #endif +#if defined(CONFIG_MACH_Q1_BD) +extern int sec_debug_panic_handler_safe(void *buf); +#endif + extern void read_lcd_register(void); #endif /* SEC_DEBUG_H */ diff --git a/arch/arm/mach-exynos/include/mach/sec_modem.h b/arch/arm/mach-exynos/include/mach/sec_modem.h index 097726b..4a7fbe8 100644 --- a/arch/arm/mach-exynos/include/mach/sec_modem.h +++ b/arch/arm/mach-exynos/include/mach/sec_modem.h @@ -5,14 +5,23 @@ enum hsic_lpa_states { STATE_HSIC_LPA_ENTER, STATE_HSIC_LPA_WAKE, STATE_HSIC_LPA_PHY_INIT, + STATE_HSIC_LPA_CHECK, }; #if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) void set_host_states(struct platform_device *pdev, int type); void set_hsic_lpa_states(int states); int get_cp_active_state(void); +#elif defined(CONFIG_MDM_HSIC_PM) +int set_hsic_lpa_states(int states); #else #define set_hsic_lpa_states(states) do {} while (0); #endif +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_BAFFIN) +bool modem_using_hub(void); +#else +static inline bool modem_using_hub(void) { return false; } +#endif + #endif diff --git a/arch/arm/mach-exynos/include/mach/secmem.h b/arch/arm/mach-exynos/include/mach/secmem.h index 42a8575..dfa86a4 100644 --- a/arch/arm/mach-exynos/include/mach/secmem.h +++ b/arch/arm/mach-exynos/include/mach/secmem.h @@ -40,7 +40,7 @@ struct secmem_crypto_driver_ftn { struct secmem_region { char *virt_addr; - unsigned long phys_addr; + dma_addr_t phys_addr; unsigned long len; }; diff --git a/arch/arm/mach-exynos/include/mach/sromc-exynos4.h b/arch/arm/mach-exynos/include/mach/sromc-exynos4.h new file mode 100644 index 0000000..69e2550 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/sromc-exynos4.h @@ -0,0 +1,253 @@ +/* + * arch/arm/mach-exynos/sromc.h + */ + +#ifndef __SROMC_H__ +#define __SROMC_H__ + +#include <linux/clk.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-srom.h> +#include <mach/gpio.h> +#include <mach/gpio-exynos4.h> +#include <mach/regs-mem.h> + +#define SROM_CS0_BASE 0x04000000 +#define SROM_CS1_BASE 0x05000000 +#define SROM_CS2_BASE 0x06000000 +#define SROM_CS3_BASE 0x07000000 +#define SROM_WIDTH 0x01000000 + +#define GPIO_SFN_SROMC S3C_GPIO_SFN(2) + +#define GPIO_SROMC_CSN EXYNOS4_GPY0(0) +#define GPIO_SROMC_CSN0 EXYNOS4_GPY0(0) +#define GPIO_SROMC_CSN1 EXYNOS4_GPY0(1) +#define GPIO_SROMC_CSN2 EXYNOS4_GPY0(2) +#define GPIO_SROMC_CSN3 EXYNOS4_GPY0(3) +#define GPIO_SROMC_REN EXYNOS4_GPY0(4) +#define GPIO_SROMC_WEN EXYNOS4_GPY0(5) +#define GPIO_SROMC_LBN EXYNOS4_GPY1(0) +#define GPIO_SROMC_UBN EXYNOS4_GPY1(1) +#define GPIO_SROMC_ADDR_BUS_L EXYNOS4_GPY3(0) +#define GPIO_SROMC_ADDR_BUS_H EXYNOS4_GPY4(0) +#define GPIO_SROMC_DATA_BUS_L EXYNOS4_GPY5(0) +#define GPIO_SROMC_DATA_BUS_H EXYNOS4_GPY6(0) + +/* SROMC configuration */ +struct sromc_bus_cfg { + unsigned addr_bits; /* Width of address bus in bits */ + unsigned data_bits; /* Width of data bus in bits */ + unsigned byte_acc; /* Byte access */ +}; + +/* SROMC bank attributes in BW (Bus width and Wait control) register */ +enum sromc_bank_attr { + SROMC_DATA_16 = 0x1, /* 16-bit data bus */ + SROMC_BYTE_ADDR = 0x2, /* Byte base address */ + SROMC_WAIT_EN = 0x4, /* Wait enabled */ + SROMC_BYTE_EN = 0x8, /* Byte access enabled */ + SROMC_ATTR_MASK = 0xF +}; + +/* SROMC bank configuration */ +struct sromc_bank_cfg { + unsigned csn; /* CSn # */ + unsigned attr; /* SROMC bank attributes */ + unsigned size; /* Size of a memory */ + unsigned addr; /* Start address (physical) */ +}; + +/* SROMC bank access timing configuration */ +struct sromc_timing_cfg { + u32 tacs; /* Address set-up before CSn */ + u32 tcos; /* Chip selection set-up before OEn */ + u32 tacc; /* Access cycle */ + u32 tcoh; /* Chip selection hold on OEn */ + u32 tcah; /* Address holding time after CSn */ + u32 tacp; /* Page mode access cycle at Page mode */ + u32 pmc; /* Page Mode config */ +}; + +static unsigned int sfn = GPIO_SFN_SROMC; + +/** + * sromc_enable + * + * Enables SROM controller (SROMC) block + * + */ +static int sromc_enable(void) +{ + struct clk *clk = NULL; + + /* SROMC clk enable */ + clk = clk_get(NULL, "sromc"); + if (!clk) { + pr_err("%s: ERR! SROMC clock gate fail\n", __func__); + return -EINVAL; + } + + clk_enable(clk); + return 0; +} + +/** + * sromc_config_demux_gpio + * @bc: pointer to an sromc_bus_cfg + * + * Configures GPIO pins for REn, WEn, LBn, UBn, address bus, and data bus + * as demux mode + * + * Returns 0 if there is no error + * + */ +static int sromc_config_demux_gpio(struct sromc_bus_cfg *bc) +{ + unsigned int addr_bits = bc->addr_bits; + unsigned int data_bits = bc->data_bits; + unsigned int byte_acc = bc->byte_acc; + unsigned int bits; + + pr_err("[SROMC] %s: addr_bits %d, data_bits %d, byte_acc %d\n", + __func__, addr_bits, data_bits, byte_acc); + + /* Configure address bus */ + switch (addr_bits) { + case 1 ... EXYNOS4_GPIO_Y3_NR: + bits = addr_bits; + s3c_gpio_cfgrange_nopull(GPIO_SROMC_ADDR_BUS_L, bits, sfn); + break; + + case (EXYNOS4_GPIO_Y3_NR + 1) ... 16: + bits = EXYNOS4_GPIO_Y3_NR; + s3c_gpio_cfgrange_nopull(GPIO_SROMC_ADDR_BUS_L, bits, sfn); + bits = (addr_bits - EXYNOS4_GPIO_Y3_NR); + s3c_gpio_cfgrange_nopull(GPIO_SROMC_ADDR_BUS_H, bits, sfn); + break; + + default: + pr_err("[SROMC] %s: ERR! invalid addr_bits %d\n", + __func__, addr_bits); + return -EINVAL; + } + + /* Configure data bus (8 or 16 bits) */ + switch (data_bits) { + case 8: + s3c_gpio_cfgrange_nopull(GPIO_SROMC_DATA_BUS_L, 8, sfn); + break; + + case 16: + s3c_gpio_cfgrange_nopull(GPIO_SROMC_DATA_BUS_L, 8, sfn); + s3c_gpio_cfgrange_nopull(GPIO_SROMC_DATA_BUS_H, 8, sfn); + break; + + default: + pr_err("[SROMC] %s: ERR! invalid data_bits %d\n", + __func__, data_bits); + return -EINVAL; + } + + /* Configure REn */ + s3c_gpio_cfgpin(GPIO_SROMC_REN, sfn); + s3c_gpio_setpull(GPIO_SROMC_REN, S3C_GPIO_PULL_NONE); + + /* Configure WEn */ + s3c_gpio_cfgpin(GPIO_SROMC_WEN, sfn); + s3c_gpio_setpull(GPIO_SROMC_WEN, S3C_GPIO_PULL_NONE); + + /* Configure LBn, UBn */ + if (byte_acc) { + s3c_gpio_cfgpin(GPIO_SROMC_LBN, sfn); + s3c_gpio_setpull(GPIO_SROMC_LBN, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_SROMC_UBN, sfn); + s3c_gpio_setpull(GPIO_SROMC_UBN, S3C_GPIO_PULL_NONE); + } + + return 0; +} + +/** + * sromc_config_csn_gpio + * @csn: CSn number (0 to 3) + * + * Configures GPIO pins for CSn + * + * Returns 0 if there is no error + * + */ +static int sromc_config_csn_gpio(unsigned int csn) +{ + unsigned int pin = GPIO_SROMC_CSN + csn; + + pr_err("[SROMC] %s: for CSn%d\n", __func__, csn); + + if (csn > 4) { + pr_err("[SROMC] %s: ERR! CSn%d invalid\n", __func__, csn); + return -EINVAL; + } + + /* Configure CSn GPIO pin */ + s3c_gpio_cfgpin(pin, sfn); + s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); + + return 0; +} + +/** + * sromc_config_access_attr + * @csn: CSn number + * @attr: SROMC attribute for this CSn + * + * Configures SROMC attribute for a CSn + * + */ +static void sromc_config_access_attr(unsigned int csn, unsigned int attr) +{ + unsigned int bw = 0; /* Bus width and Wait control */ + + pr_err("[SROMC] %s: for CSn%d\n", __func__, csn); + + bw = __raw_readl(S5P_SROM_BW); + pr_err("[SROMC] %s: old BW setting = 0x%08X\n", __func__, bw); + + /* Configure BW control field for the CSn */ + bw &= ~(SROMC_ATTR_MASK << (csn << 2)); + bw |= (attr << (csn << 2)); + writel(bw, S5P_SROM_BW); + + /* Verify SROMC settings */ + bw = __raw_readl(S5P_SROM_BW); + pr_err("[SROMC] %s: new BW setting = 0x%08X\n", __func__, bw); +} + +/** + * sromc_config_access_timing + * @csn: CSn number + * @tm_cfg: pointer to an sromc_timing_cfg + * + * Configures SROMC access timing register + * + */ +static void sromc_config_access_timing(unsigned int csn, + struct sromc_timing_cfg *tm_cfg) +{ + void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); + unsigned int bc = 0; /* Bank Control */ + + bc = __raw_readl(bank_sfr); + pr_err("[SROMC] %s: old BC%d setting = 0x%08X\n", __func__, csn, bc); + + /* Configure memory access timing for the CSn */ + bc = tm_cfg->tacs | tm_cfg->tcos | tm_cfg->tacc | + tm_cfg->tcoh | tm_cfg->tcah | tm_cfg->tacp | tm_cfg->pmc; + writel(bc, bank_sfr); + + /* Verify SROMC settings */ + bc = __raw_readl(bank_sfr); + pr_err("[SROMC] %s: new BC%d setting = 0x%08X\n", __func__, csn, bc); +} + +#endif + diff --git a/arch/arm/mach-exynos/include/mach/subsystem_restart.h b/arch/arm/mach-exynos/include/mach/subsystem_restart.h index f7becef..a72fa62 100644 --- a/arch/arm/mach-exynos/include/mach/subsystem_restart.h +++ b/arch/arm/mach-exynos/include/mach/subsystem_restart.h @@ -39,6 +39,7 @@ struct subsys_data { struct mutex shutdown_lock; struct mutex powerup_lock; + bool ongoing; void *restart_order; struct subsys_data *single_restart_list[1]; diff --git a/arch/arm/mach-exynos/include/mach/t0-power.h b/arch/arm/mach-exynos/include/mach/t0-power.h new file mode 100644 index 0000000..1bd3a53 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/t0-power.h @@ -0,0 +1,37 @@ +/* + * t0-power.h - Power Management of T0 Project + * + * Copyright (C) 2011 Samsung Electrnoics + * Chiwoong Byun <woong.byun@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MIDAS_POWER_H +#define __MIDAS_POWER_H __FILE__ + +#if defined(CONFIG_MFD_S5M_CORE) && defined(CONFIG_MFD_MAX77686) +extern struct s5m_platform_data exynos4_s5m8767_info; +extern struct max77686_platform_data exynos4_max77686_info; +#elif defined(CONFIG_MFD_S5M_CORE) +extern struct s5m_platform_data exynos4_s5m8767_info; +#else +extern struct max77686_platform_data exynos4_max77686_info; +#endif + +void midas_power_init(void); +void midas_power_set_muic_pdata(void *, int); +void midas_power_gpio_init(void); +#endif /* __MIDAS_POWER_H */ diff --git a/arch/arm/mach-exynos/include/mach/tdmb_pdata.h b/arch/arm/mach-exynos/include/mach/tdmb_pdata.h index ce8a986..eb5c162 100644 --- a/arch/arm/mach-exynos/include/mach/tdmb_pdata.h +++ b/arch/arm/mach-exynos/include/mach/tdmb_pdata.h @@ -25,7 +25,11 @@ struct tdmb_platform_data { void (*gpio_on) (void); void (*gpio_off)(void); - int irq; + unsigned int irq; +#if defined(CONFIG_TDMB_ANT_DET) + unsigned int gpio_ant_det; + unsigned int irq_ant_det; +#endif }; #endif #endif diff --git a/arch/arm/mach-exynos/include/mach/usb_switch.h b/arch/arm/mach-exynos/include/mach/usb_switch.h index de054b6..a5340e5 100644 --- a/arch/arm/mach-exynos/include/mach/usb_switch.h +++ b/arch/arm/mach-exynos/include/mach/usb_switch.h @@ -20,9 +20,14 @@ extern int usb_switch_lock(void); extern int usb_switch_trylock(void); extern void usb_switch_unlock(void); +extern enum usb_path_t usb_switch_get_path(void); extern void usb_switch_set_path(enum usb_path_t path); extern void usb_switch_clr_path(enum usb_path_t path); extern void set_usb_connection_state(bool connected); +#ifdef CONFIG_TARGET_LOCALE_KOR +extern int px_switch_get_usb_lock_state(void); +#endif + #endif diff --git a/arch/arm/mach-exynos/include/mach/usbdiag.h b/arch/arm/mach-exynos/include/mach/usbdiag.h index d1e3605..5f0cecf 100644 --- a/arch/arm/mach-exynos/include/mach/usbdiag.h +++ b/arch/arm/mach-exynos/include/mach/usbdiag.h @@ -28,6 +28,8 @@ #define USB_DIAG_DISCONNECT 1 #define USB_DIAG_WRITE_DONE 2 #define USB_DIAG_READ_DONE 3 +// zero_pky.patch by jagadish +#define USB_DIAG_QXDM_DISCONNECT 4 struct diag_request { char *buf; |