diff options
Diffstat (limited to 'arch/arm/mach-exynos')
195 files changed, 52527 insertions, 29729 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 864bf02..fb936b0 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -371,7 +371,7 @@ config EXYNOS4_SETUP_FB_S5P Setup code for EXYNOS4 FIMD config EXYNOS4_SETUP_TVOUT - bool + bool "enabel EXYNOS4_SETUP_TVOUT" default y help Common setup code for TVOUT @@ -572,6 +572,10 @@ config BUSFREQ_OPP bool "Busfreq with OPP" depends on EXYNOS4_CPUFREQ || EXYNOS5_CPUFREQ +config DISPFREQ_OPP + bool "Dispfreq with OPP" + depends on EXYNOS4_CPUFREQ || EXYNOS5_CPUFREQ + config DEVFREQ_BUS bool "Busfreq support with Devfreq framework & Simple-Ondemand" depends on EXYNOS4_CPUFREQ @@ -798,7 +802,16 @@ config MACH_NURI select SAMSUNG_DEV_PWM help Machine support for Samsung Mobile NURI Board. - +config MACH_U1_NA_SPR + bool "NA" + select S3C_DEV_I2C17_EMUL + select S3C_DEV_I2C4 + select EXYNOS4_SETUP_I2C4 +config MACH_U1_NA_USCC + bool "NA" + select S3C_DEV_I2C17_EMUL + select S3C_DEV_I2C4 + select EXYNOS4_SETUP_I2C4 config MACH_U1 bool "U1 board" select CPU_EXYNOS4210 @@ -848,15 +861,12 @@ config MACH_U1 choice prompt "U1 board" - depends on MACH_U1 + depends on MACH_U1 || MACH_TRATS default MACH_U1_BD config MACH_U1_BD bool "U1 Board" -config MACH_U1CAMERA_BD - bool "U1CAMERA Board" - config MACH_Q1_BD bool "Q1 Board" @@ -931,18 +941,18 @@ endchoice choice prompt "LCD panel select" - depends on MACH_U1 + depends on MACH_U1 || MACH_TRATS default PANEL_U1 config PANEL_U1 bool "U1/Q1 default panel" -endchoice +config PANEL_U1_NA_SPR + bool "D710 panel" -config PANEL_S2PLUS - bool "s2plus panel" +endchoice -if MACH_U1 || MACH_C1 || MACH_C1VZW || MACH_M0 || MACH_P4 || MACH_P2 || MACH_P4NOTE || MACH_T0 +if MACH_U1 || MACH_C1 || MACH_M3 || MACH_M0 || MACH_P4 || MACH_P2 || MACH_P4NOTE || MACH_T0 || MACH_TRATS || MACH_GRANDE || MACH_GC1 || MACH_BAFFIN source "arch/arm/mach-exynos/Kconfig.local" endif @@ -1006,7 +1016,6 @@ config MACH_MIDAS select S3C_DEV_I2C7 select S5P_GPIO_INT select S5P_DEV_MFC - select S5P_DEV_TVOUT select S5P_DEV_FIMG2D select S5P_DEV_FIMD_S5P select S5P_DEV_USB_EHCI @@ -1038,15 +1047,7 @@ config MACH_MIDAS choice prompt "EXYNOS4212 board" depends on MACH_MIDAS - default MACH_MIDAS_02_BD - -config MACH_MIDAS_01_BD - bool "Midas Rev 0.1 board" - -config MACH_MIDAS_02_BD - bool "Midas Rev 0.2 board" - select S3C_DEV_I2C4 - select S3C_DEV_I2C5 + default MACH_M0 config MACH_M0 bool "M0 board" @@ -1054,46 +1055,16 @@ config MACH_M0 select S3C_DEV_I2C5 select MIDAS_COMMON_BD -config MACH_M3 - bool "M3 board" - select S3C_DEV_I2C4 - select S3C_DEV_I2C5 - select MIDAS_COMMON_BD - config MACH_C1 bool "C1 board" select S3C_DEV_I2C4 select S3C_DEV_I2C5 select MIDAS_COMMON_BD -config MACH_C1VZW - bool "C1 VZW board" - select S3C_DEV_I2C4 - select S3C_DEV_I2C5 - select MIDAS_COMMON_BD - -config MACH_C1CTC - bool "C1 CTC board" - select S3C_DEV_I2C4 - select S3C_DEV_I2C5 - select MIDAS_COMMON_BD - -config MACH_JENGA - bool "Jenga board" - select S3C_DEV_I2C4 - select S3C_DEV_I2C5 - select MIDAS_COMMON_BD - -config MACH_S2PLUS - bool "S2PLUS board" +config MACH_M3 + bool "C2 board" select S3C_DEV_I2C4 select S3C_DEV_I2C5 - select PANEL_S2PLUS - select MIDAS_COMMON_BD - -config MACH_S2PLUS - bool "S2 Plus board" - select S3C_DEV_I2C4 select MIDAS_COMMON_BD config MACH_P4NOTE @@ -1110,10 +1081,31 @@ config MACH_GC1 config MACH_T0 bool "T0 board" + select EXYNOS4_SETUP_I2C2 + select S3C_DEV_I2C2 select S3C_DEV_I2C4 select S3C_DEV_I2C5 - select T0_00_BD +config MACH_IRON + bool "Iron board" + select S3C_DEV_I2C4 + select S3C_DEV_I2C5 + select IRON_BD + select EXYNOS4_SETUP_KEYPAD + select SAMSUNG_DEV_KEYPAD + +config MACH_GRANDE + bool "Grande board" + select S3C_DEV_I2C4 + select S3C_DEV_I2C5 + select GRANDE_BD + select EXYNOS4_SETUP_KEYPAD + select SAMSUNG_DEV_KEYPAD + +config MACH_BAFFIN + bool "BAFFIN board" + select S3C_DEV_I2C4 + select S3C_DEV_I2C5 endchoice config MIDAS_COMMON_BD @@ -1126,7 +1118,18 @@ config GC1_00_BD bool "Galaxy Camera common Board" config T0_00_BD - bool "T0 common Board" + bool "T0 Revison 00 board" + default n + +config T0_04_BD + bool "T0 Revison 04 board" + default n + +config IRON_BD + bool "Iron common Board" + +config GRANDE_BD + bool "Grande common Board" config WRITEBACK_ENABLED bool "Samsung Writeback Enable" @@ -1136,6 +1139,19 @@ config WRITEBACK_ENABLED writeback operations support final blended stream. when enable this options. +config EXYNOS_SOUND_PLATFORM_DATA + bool "Sound platform data" + +config JACK_FET + bool "Ear Micbias dischage Enable" + +config JACK_GROUND_DET + bool "Ear Ground Detection Enable" + +config SAMSUNG_ANALOG_UART_SWITCH + int "SAMSUNG analog switch for UART" + default 1 + endmenu menu "EXYNOS5 Machines" @@ -1361,6 +1377,11 @@ config EXYNOS4_MSHC_EPLL_45MHZ bool "EPLL" endchoice +config EXYNOS4_MSHC_SUPPORT_PQPRIME_EPLL + bool "Support EPLL 45MHz for PegasusQ Prime dynamically" + depends on PLAT_S5P && EXYNOS4_DEV_MSHC && EXYNOS4_MSHC_MPLL_40MHZ + default n + comment "Use 8-bit bus width" config EXYNOS4_MSHC_8BIT @@ -1441,6 +1462,14 @@ config SEC_DEBUG_SCHED_LOG help Samsung Scheduler Logging Feature for Debug use. +config SEC_DEBUG_HRTIMER_LOG + bool "Samsung hrtimer Logging Feature" + default n + depends on SEC_DEBUG_SCHED_LOG && !SAMSUNG_PRODUCT_SHIP + help + Samsung hrtimer Logging Feature for Debug use. + This option enables us to log hrtimer enter/exit. + config SEC_DEBUG_SOFTIRQ_LOG bool "Samsung Softirq Logging Feature" default n @@ -1503,6 +1532,15 @@ config SEC_DEBUG_FUPLOAD_DUMP_MORE More information is printed out when a forced upload happens. It uses customized dump functions instead of panic call. +config SEC_DEBUG_UMP_ALLOC_FAIL + bool "Show warning message when UMP allcation fails" + default n + help + When UMP allocation fails there's no way to figure out the reason. + For UMP and Mali is supposed to allocate per 1 page, + we should take a good look at this failure. + This only shows the alloc fail warning. + config SEC_DEBUG_LIST_CORRUPTION bool "Panic when list corruption detected" default n @@ -1512,15 +1550,6 @@ config SEC_DEBUG_LIST_CORRUPTION But it reports only with WARN level. This will immediately stop the system. -config SEC_DEBUG_SYSRQ_B - bool "Panic when sysrq(b) detected" - default n - help - Panic when sysrq('b') detected. - In current debuggin feature sysrq('b') will anyway lead us to upload - with unknown reset, we are not handling debug flags for this. - With this feature we can find out what situation sysrq('b') is used. - menuconfig SEC_WATCHDOG_RESET bool "S5PV310 watchdog reset to exit from lockup" depends on (CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412) @@ -1562,6 +1591,10 @@ config SEC_LOG_LAST_KMSG help This option enables /proc/last_kmsg support. +config EHCI_IRQ_DISTRIBUTION + bool "ehci irq distribution" + default n + if SEC_MODEM comment "Samsung Modem Feature" @@ -1569,6 +1602,10 @@ config LTE_VIA_SWITCH bool default n +config SEC_DUAL_MODEM_MODE + bool "sec dual modem mode" + default n + choice prompt "SEC MODEM CONFIG" depends on SEC_MODEM @@ -1581,24 +1618,40 @@ config SEC_MODEM_M0_C2C select LINK_DEVICE_C2C select SAMSUNG_C2C select C2C_DEUBG + select EHCI_IRQ_DISTRIBUTION config SEC_MODEM_M0 bool "M0 with xmm6262" select UMTS_MODEM_XMM6262 select LINK_DEVICE_HSIC + select EHCI_IRQ_DISTRIBUTION config SEC_MODEM_M0_CTC bool "M0 CTC with MDM6600" select CDMA_MODEM_MDM6600 - select LINK_DEVICE_DPRAM select USBHUB_USB3503 +config SEC_MODEM_T0_CU_DUOS + bool "T0 CU DUOS with ESC6270" + select GSM_MODEM_ESC6270 + select LINK_DEVICE_PLD + +config SEC_MODEM_T0_OPEN_DUOS + bool "T0 OPEN DUOS with ESC6270" + select GSM_MODEM_ESC6270 + select LINK_DEVICE_PLD + +config SEC_MODEM_M0_GRANDECTC + bool "M0 CTC with ESC6270" + select GSM_MODEM_ESC6270 + config SEC_MODEM_M1 bool "M1 with cmc221" select LTE_MODEM_CMC221 select LINK_DEVICE_DPRAM select LINK_DEVICE_USB select USBHUB_USB3503 + select EHCI_IRQ_DISTRIBUTION config SEC_MODEM_C1 bool "C1 with cmc221" @@ -1606,15 +1659,7 @@ config SEC_MODEM_C1 select LINK_DEVICE_DPRAM select LINK_DEVICE_USB select USBHUB_USB3503 - -config SEC_MODEM_C1_VZW - bool "C1 with CMC221 and CBP7.2" - select CDMA_MODEM_CBP72 - select LTE_MODEM_CMC221 - select LTE_VIA_SWITCH - select LINK_DEVICE_DPRAM - select LINK_DEVICE_USB - select USBHUB_USB3503 + select EHCI_IRQ_DISTRIBUTION config SEC_MODEM_C1_LGT bool "C1 with CMC221 and CBP7.2" @@ -1624,12 +1669,7 @@ config SEC_MODEM_C1_LGT select LINK_DEVICE_DPRAM select LINK_DEVICE_USB select USBHUB_USB3503 - -config SEC_MODEM_C1_CTC - bool "C1 with MDM6600" - select CDMA_MODEM_MDM6600 - select LINK_DEVICE_DPRAM - select USBHUB_USB3503 + select EHCI_IRQ_DISTRIBUTION config SEC_MODEM_M2 bool "M2 with MDM9x15" @@ -1638,16 +1678,7 @@ config SEC_MODEM_U1 bool "U1 with xmm6260" select UMTS_MODEM_XMM6260 select LINK_DEVICE_HSIC - -config SEC_MODEM_JENGA - bool "JENGA with xmm6262" - select UMTS_MODEM_XMM6262 - select LINK_DEVICE_HSIC - -config SEC_MODEM_S2PLUS - bool "S2PLUS with xmm6262" - select UMTS_MODEM_XMM6262 - select LINK_DEVICE_HSIC + select EHCI_IRQ_DISTRIBUTION config SEC_MODEM_U1_LGT bool "U1 with mdm6600" @@ -1659,6 +1690,28 @@ config SEC_MODEM_GAIA select LTE_MODEM_CMC221 select LINK_DEVICE_DPRAM +config SEC_MODEM_IRON + bool "Iron with xmm6262" + select UMTS_MODEM_XMM6262 + select LINK_DEVICE_HSIC + select EHCI_IRQ_DISTRIBUTION + +config SEC_MODEM_P8LTE + bool "P8 VZW with CMC220 and CBP7.1" + select CDMA_MODEM_CBP71 + select LINK_DEVICE_DPRAM + select LTE_MODEM_CMC220 + select LINK_DEVICE_USB + select INTERNAL_MODEM_IF + +config SEC_MODEM_T0_TD_DUAL + bool "T0 with SPRD8803 & XMM6262" + select UMTS_MODEM_XMM6262 + select LINK_DEVICE_HSIC + select EHCI_IRQ_DISTRIBUTION + select TDSCDMA_MODEM_SPRD8803 + select LINK_DEVICE_SPI + endchoice endif @@ -1704,6 +1757,14 @@ config QC_MODEM_MDM9X15 bool "support QC mdm9x15 modem" default n +config MDM_HSIC_PM + bool "support QC mdm9x15 PM over HSIC" + default n + +config EMI_ERROR_RECOVERY + bool "unsuspected emi error recovery on HUB" + default n + if QC_MODEM choice prompt "QC MODEM CONFIG" @@ -1718,10 +1779,28 @@ config QC_MODEM_M3 select USB_QCOM_MDM_BRIDGE select QC_MODEM_MDM9X15 select MSM_RMNET_USB + select DIAG_CHAR + select MDM_HSIC_PM endchoice endif +config USB_CDFS_SUPPORT + bool "Auto install for cdfs" + default y + config SAMSUNG_PRODUCT_SHIP bool "set up for product shippling" default n + +config CORESIGHT_ETM + bool "CoreSight ETM debug system" + help + Enables the CoreSight ETM debug system. + +config CORESIGHT_ETM_DEFAULT_ENABLE + bool "Turn on ETM Tracing by Default" + depends on CORESIGHT_ETM + help + Turns on ETM tracing by default. Otherwise, tracing is + disabled by default but can be enabled by other means. diff --git a/arch/arm/mach-exynos/Kconfig.local b/arch/arm/mach-exynos/Kconfig.local index 0e22814..cf3f275 100644 --- a/arch/arm/mach-exynos/Kconfig.local +++ b/arch/arm/mach-exynos/Kconfig.local @@ -20,14 +20,20 @@ config TARGET_LOCALE_P2EUR_TEMP config TARGET_LOCALE_P2TMO_TEMP bool "P2TMO" +config TARGET_LOCALE_NA + bool "NA" + config TARGET_LOCALE_EUR_U1_NFC bool "Europe Open NFC" config TARGET_LOCALE_NTT + bool "JPN DCM" + +config TARGET_LOCALE_JPN bool "JPN" config TARGET_LOCALE_CHN - bool "Chinese" + bool "CHN" config TARGET_LOCALE_USA bool "USA" @@ -47,6 +53,82 @@ config MACH_C1_USA_VZW endchoice choice + prompt "C2 USA Target Carrier" + depends on MACH_M3 && \ + (TARGET_LOCALE_USA || TARGET_LOCALE_JPN) + default MACH_M3_USA_VZW + +config MACH_M3_USA_VZW + bool "C2 Verizon" + +config MACH_M3_USA_SPR + bool "C2 Sprint" + +config MACH_M3_JPN_DCM + bool "M3 JPN DCM" + +endchoice + +choice + prompt "T0 Target" + depends on MACH_T0 && \ + (TARGET_LOCALE_EUR || TARGET_LOCALE_USA || TARGET_LOCALE_KOR || TARGET_LOCALE_JPN || TARGET_LOCALE_CHN) + default MACH_T0_EUR_OPEN + +config MACH_T0_USA_ATT + bool "ATT" + +config MACH_T0_USA_TMO + bool "TMO" + +config MACH_T0_USA_VZW + bool "VZW" + +config MACH_T0_USA_SPR + bool "SPR" + +config MACH_T0_USA_USCC + bool "USCC" + +config MACH_T0_EUR_LTE + bool "EUR LTE" + +config MACH_T0_EUR_OPEN + bool "EUR OPEN" + +config MACH_T0_KOR_SKT + bool "SKT" + +config MACH_T0_KOR_KT + bool "KT" + +config MACH_T0_KOR_LGT + bool "LG U+" + +config MACH_T0_JPN_LTE_DCM + bool "JPN LTE DCM T0" + +config MACH_T0_CHN_OPEN + bool "CHN OPEN" + +config MACH_T0_CHN_CU + bool "CHN CU" + +config MACH_T0_CHN_CU_DUOS + bool "CHN CU DUOS" + +config MACH_T0_CHN_OPEN_DUOS + bool "CHN OPEN DUOS" + +config MACH_T0_CHN_CMCC + bool "CHN CMCC" + +config MACH_T0_CHN_CTC + bool "CHN CTC" + +endchoice + +choice prompt "U1 KOR Target Carrier" depends on MACH_U1 && TARGET_LOCALE_KOR default MACH_U1_KOR_SKT @@ -63,7 +145,7 @@ endchoice choice prompt "C1 KOR Target Carrier" - depends on (MACH_C1 || MACH_C1VZW) && TARGET_LOCALE_KOR + depends on MACH_C1 && TARGET_LOCALE_KOR default MACH_C1_KOR_SKT config MACH_C1_KOR_SKT @@ -93,16 +175,31 @@ endchoice choice prompt "P4 KOR Target Carrier" - depends on MACH_P4 && TARGET_LOCALE_KOR - default MACH_P4_KOR_ANY + depends on MACH_P4NOTE && TARGET_LOCALE_KOR + default MACH_P4NOTE_KOR_ANY + +config MACH_P4NOTE_KOR_ANY + bool "P4NOTE KOR OPEN Board" + +config MACH_P4NOTE_KOR_SKT + bool "P4NOTE KOR SKT Board" + +config MACH_P4NOTE_KOR_KT + bool "P4NOTE KOR KT Board" -config MACH_P4_KOR_ANY - bool "P4 KOR OPEN Board" +config MACH_P4NOTELTE_KOR_SKT + bool "P4NOTELTE KOR SKT Board" + +config MACH_P4NOTELTE_KOR_KT + bool "P4NOTELTE KOR KT Board" + +config MACH_P4NOTELTE_KOR_LGT + bool "P4NOTELTE KOR LGT Board" endchoice choice prompt "M0 Chinese Target Carrier" - depends on MACH_M0 && TARGET_LOCALE_CHN + depends on (MACH_M0 || MACH_GRANDE) && TARGET_LOCALE_CHN config MACH_M0_CMCC bool "M0 CHN CMCC board" @@ -125,12 +222,28 @@ config MACH_Q1_CMCC_BD bool "Q1 CHN CMCC board" endchoice +choice + prompt "BAFFIN KOR Target Carrier" + depends on MACH_BAFFIN && TARGET_LOCALE_KOR + default MACH_BAFFIN_KOR_SKT + +config MACH_BAFFIN_KOR_SKT + bool "SKT" + +config MACH_BAFFIN_KOR_KT + bool "KT" + +config MACH_BAFFIN_KOR_LGT + bool "LG U+" +endchoice menu "M0 CTC based models" depends on MACH_M0_CTC && TARGET_LOCALE_CHN config MACH_M0_GRANDECTC bool "M0 CHN GRANDE CTC board" -endmenu +config MACH_M0_DUOSCTC + bool "M0 CHN DUOS CTC board" +endmenu diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index cf1d352..47aedaf 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -44,6 +44,8 @@ ifeq ($(CONFIG_BUSFREQ_OPP),y) obj-$(CONFIG_ARCH_EXYNOS4) += busfreq_opp_exynos4.o busfreq_opp_4x12.o obj-$(CONFIG_ARCH_EXYNOS5) += busfreq_opp_exynos5.o busfreq_opp_5250.o endif +obj-$(CONFIG_DISPFREQ_OPP) += dispfreq_opp_exynos4.o +obj-$(CONFIG_BUSFREQ_LOCK_WRAPPER) += dev-slp.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o @@ -63,23 +65,29 @@ obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o -ifeq ($(CONFIG_MACH_U1CAMERA_BD),y) -obj-$(CONFIG_MACH_U1) += mach-u1cam.o +obj-$(CONFIG_MACH_TRATS) += board-trats.o sec-common.o sec-switch_max8997.o \ + u1-wlan.o u1_regulator_consumer.o sec-reboot.o +obj-$(CONFIG_MACH_U1) += mach-u1.o sec-common.o sec-switch_max8997.o +obj-$(CONFIG_WIMAX_CMC) += u1-wimax.o +ifneq ($(CONFIG_MACH_U1_NA_SPR),y) +ifneq ($(CONFIG_MACH_U1_NA_USCC),y) +obj-$(CONFIG_MACH_U1_BD) += u1-gpio.o board-gps-gsd4t.o else -obj-$(CONFIG_MACH_U1) += mach-u1.o +obj-$(CONFIG_MACH_U1_BD) += u1-gpio.o +endif +else +obj-$(CONFIG_MACH_U1_BD) += u1-gpio.o endif -obj-$(CONFIG_MACH_U1) += sec-common.o sec-switch_max8997.o -obj-$(CONFIG_MACH_U1_BD) += u1-gpio.o board-gps-gsd4t.o obj-$(CONFIG_MACH_Q1_BD) += q1-gpio.o board-gps-bcm475x.o -obj-$(CONFIG_MACH_U1CAMERA_BD) += u1camera-gpio.o board-gps-bcm475x.o obj-$(CONFIG_MACH_U1) += u1-wlan.o obj-$(CONFIG_MACH_PX) += mach-px.o sec-common.o board-gps-bcm475x.o px-switch.o obj-$(CONFIG_MACH_P2) += p2-gpio.o obj-$(CONFIG_MACH_P4) += p4-gpio.o obj-$(CONFIG_MACH_P8) += p8-gpio.o +obj-$(CONFIG_MACH_P8LTE) += p8lte-gpio.o obj-$(CONFIG_MACH_P10) += board-p10-wlan.o board-gps-bcm475x.o obj-$(CONFIG_PANEL_U1) += u1-panel.o u1-panel_a2.o u1-panel_m2.o -obj-$(CONFIG_PANEL_S2PLUS) += s2plus-panel.o +obj-$(CONFIG_PANEL_U1_NA_SPR) += u1-na-spr-panel.o obj-$(CONFIG_MACH_U1) += u1_regulator_consumer.o obj-$(CONFIG_MACH_PX) += u1_regulator_consumer.o obj-$(CONFIG_MACH_NURI) += mach-nuri.o @@ -87,8 +95,24 @@ obj-$(CONFIG_MACH_SMDK4X12) += mach-smdk4x12.o ifeq ($(CONFIG_MACH_P4NOTE),y) obj-$(CONFIG_MACH_MIDAS) += mach-p4notepq.o px-switch.o p4note-jack.o else +ifeq ($(CONFIG_MACH_IRON),y) +obj-$(CONFIG_MACH_MIDAS) += board-grande.o grande-jack.o +else +ifeq ($(CONFIG_MACH_GRANDE),y) +obj-$(CONFIG_MACH_MIDAS) += board-grande.o grande-jack.o +else obj-$(CONFIG_MACH_MIDAS) += mach-midas.o endif +endif +endif +obj-$(CONFIG_MACH_SLP_MIDAS) += board-slp-midas.o midas-sensor.o +obj-$(CONFIG_MACH_SLP_PQ) += board-slp-pq.o +obj-$(CONFIG_MACH_REDWOOD) += board-redwood.o +obj-$(CONFIG_MACH_SLP_PQ_LTE) += board-slp-pq.o +obj-$(CONFIG_MACH_SLP_NAPLES) += board-slp-naples.o +obj-$(CONFIG_MACH_SLP_T0_LTE) += board-slp-t0-lte.o +obj-$(CONFIG_CHARGER_MANAGER) += charger-slp.o +obj-$(CONFIG_SLP) += sec-reboot.o obj-$(CONFIG_MACH_SMDK5210) += mach-smdk5210.o obj-$(CONFIG_MACH_SMDK5250) += mach-smdk5250.o obj-$(CONFIG_MACH_SMDK5250) += board-smdk5250-mmc.o @@ -101,15 +125,72 @@ obj-$(CONFIG_MACH_SMDK5250) += board-smdk5250-spi.o obj-$(CONFIG_MACH_P4NOTE) += p4-input.o +ifeq ($(CONFIG_MACH_GRANDE),y) +obj-$(CONFIG_MIDAS_COMMON) += sec-common.o board-gps-bcm475x.o \ + board-grande-tsp.o board-midas-wlan.o \ + board-grande-camera.o board-grande-thermistor.o \ + board-grande-lcd.o board-grande-sound.o +else +ifeq ($(CONFIG_MACH_IRON),y) obj-$(CONFIG_MIDAS_COMMON) += sec-common.o board-gps-bcm475x.o \ + board-grande-tsp.o board-midas-wlan.o \ + board-grande-camera.o board-grande-thermistor.o \ + board-grande-lcd.o board-grande-sound.o +else +ifeq ($(CONFIG_MACH_M3),y) +obj-$(CONFIG_MIDAS_COMMON) += sec-common.o \ midas-tsp.o board-midas-wlan.o \ midas-camera.o midas-thermistor.o \ midas-mhl.o midas-lcd.o midas-sound.o - +else +ifeq ($(CONFIG_MACH_T0),y) +obj-$(CONFIG_MIDAS_COMMON) += sec-common.o \ + midas-tsp.o board-midas-wlan.o \ + midas-camera.o midas-thermistor.o \ + midas-mhl.o midas-lcd.o t0-sound.o +obj-$(CONFIG_SEC_MODEM) += board-gps-bcm475x.o +else +ifeq ($(CONFIG_MACH_P4NOTE),y) +obj-$(CONFIG_MIDAS_COMMON) += sec-common.o\ + midas-tsp.o board-midas-wlan.o \ + midas-camera.o midas-thermistor.o \ + midas-mhl.o midas-lcd.o midas-sound.o +obj-$(CONFIG_SEC_MODEM) += board-gps-bcm475x.o +else +ifeq ($(CONFIG_MACH_SLP_T0_LTE),y) +obj-$(CONFIG_MIDAS_COMMON) += sec-common.o \ + board-midas-wlan.o \ + midas-camera.o midas-thermistor.o \ + midas-mhl.o midas-lcd.o +else +ifeq ($(CONFIG_MACH_SLP_PQ),y) +obj-$(CONFIG_MIDAS_COMMON) += sec-common.o board-gps-bcm475x.o \ + board-midas-wlan.o \ + midas-camera.o midas-thermistor.o \ + midas-mhl.o midas-lcd.o +else +obj-$(CONFIG_MIDAS_COMMON) += sec-common.o board-gps-bcm475x.o \ + midas-tsp.o board-midas-wlan.o \ + midas-camera.o midas-thermistor.o \ + midas-mhl.o midas-lcd.o midas-sound.o +endif +endif +endif +endif +endif +endif +endif +obj-$(CONFIG_IRON_BD) += board-iron-gpio.o board-grande-power.o +obj-$(CONFIG_GRANDE_BD) += board-grande-gpio.o board-grande-power.o obj-$(CONFIG_P4NOTE_00_BD) += p4note-gpio.o p4note-power.o -obj-$(CONFIG_GC1_00_BD) += gc1-gpio.o gc1-power.o -obj-$(CONFIG_T0_00_BD) += midas-gpio.o midas-power.o -obj-$(CONFIG_MIDAS_COMMON_BD) += midas-gpio.o midas-power.o +obj-$(CONFIG_GC1_00_BD) += gc1-gpio.o gc1-power.o gc1-jack.o +obj-$(CONFIG_MACH_T0) += t0-gpio.o t0-power.o +obj-$(CONFIG_MACH_BAFFIN) += baffin-gpio.o baffin-power.o +ifeq ($(CONFIG_MACH_M3),y) +obj-$(CONFIG_MIDAS_COMMON_BD) += m3-gpio.o midas-power.o +else +obj-$(CONFIG_MIDAS_COMMON_BD) += midas-gpio.o midas-power.o +endif obj-$(CONFIG_EXTCON) += midas-extcon.o obj-$(CONFIG_NAPLES_COMMON) += naples-gpio.o sec-common.o midas-gps.o \ @@ -118,12 +199,19 @@ obj-$(CONFIG_NAPLES_COMMON) += naples-gpio.o sec-common.o midas-gps.o \ midas-mhl.o obj-$(CONFIG_PN65N_NFC) += midas-nfc.o -obj-$(CONFIG_MACH_MIDAS) += midas-sensor.o +ifeq ($(CONFIG_MACH_GRANDE),y) +obj-$(CONFIG_MACH_MIDAS) += sec-reboot.o board-grande-sensor.o +else +ifeq ($(CONFIG_MACH_IRON),y) +obj-$(CONFIG_MACH_MIDAS) += sec-reboot.o board-grande-sensor.o +else +obj-$(CONFIG_MACH_MIDAS) += sec-reboot.o midas-sensor.o +endif +endif obj-$(CONFIG_LEDS_LP5521) += midas-leds.o obj-$(CONFIG_MACH_U1) += sec-reboot.o obj-$(CONFIG_MACH_PX) += sec-reboot.o -obj-$(CONFIG_MACH_MIDAS) += sec-reboot.o obj-$(CONFIG_MACH_P10) += mach-p10.o p10-gpio.o sec-common.o p10-input.o \ p10-switch.o p10-battery.o midas-sound.o p10-mhl.o @@ -186,24 +274,21 @@ obj-$(CONFIG_EXYNOS4_SETUP_MIPI_DSIM) += setup-mipidsim.o obj-$(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) += secmem-allocdev.o obj-$(CONFIG_EXYNOS_C2C) += setup-c2c.o obj-$(CONFIG_SEC_MODEM_M0_C2C) += board-midas-modems.o -ifeq ($(CONFIG_MACH_P4NOTE),y) -obj-$(CONFIG_SEC_MODEM_M0) += board-p4notepq-modems.o -else obj-$(CONFIG_SEC_MODEM_M0) += board-m0-modems.o -endif obj-$(CONFIG_SEC_MODEM_M0_TD) += board-m0-td-modems.o +obj-$(CONFIG_SEC_MODEM_T0_TD_DUAL) += board-m0-modems.o board-m0-td-modems.o obj-$(CONFIG_SEC_MODEM_M0_CTC) += board-m0ctc-modems.o +obj-$(CONFIG_SEC_MODEM_T0_CU_DUOS) += board-m0-modems.o board-t0cu-duos-modems.o +obj-$(CONFIG_SEC_MODEM_T0_OPEN_DUOS) += board-m0-modems.o board-t0cu-duos-modems.o +obj-$(CONFIG_SEC_MODEM_IRON) += board-iron-modems.o #obj-$(CONFIG_SEC_MODEM_M1) += board-m1-modems.o obj-$(CONFIG_SEC_MODEM_GAIA) += board-gaia-modems.o obj-$(CONFIG_SEC_MODEM_M1) += board-c1-modems.o obj-$(CONFIG_SEC_MODEM_C1) += board-c1-modems.o -obj-$(CONFIG_SEC_MODEM_C1_VZW) += board-c1vzw-modems.o obj-$(CONFIG_SEC_MODEM_C1_LGT) += board-c1lgt-modems.o -obj-$(CONFIG_SEC_MODEM_C1_CTC) += board-c1ctc-modems.o obj-$(CONFIG_SEC_MODEM_U1) += board-u1-modems.o -obj-$(CONFIG_SEC_MODEM_JENGA) += board-jenga-modems.o -obj-$(CONFIG_SEC_MODEM_S2PLUS) += board-s2plus-modems.o obj-$(CONFIG_SEC_MODEM_U1_LGT) += board-u1-lgt-modems.o +obj-$(CONFIG_SEC_MODEM_P8LTE) += board-p8ltevzw-modems.o obj-$(CONFIG_SEC_DEBUG) += sec_debug.o sec_getlog.o sec_gaf.o obj-$(CONFIG_SEC_WATCHDOG_RESET) += sec_watchdog.o obj-$(CONFIG_SEC_LOG) += sec_log.o @@ -217,8 +302,20 @@ obj-$(CONFIG_BT_BCM4330) += board-bluetooth-bcm4330.o obj-$(CONFIG_BT_BCM4334) += board-bluetooth-bcm4334.o obj-$(CONFIG_BT_BCM43241) += board-bluetooth-bcm43241.o obj-$(CONFIG_GPS_BCM47511) += bcm47511.o +obj-$(CONFIG_GPS_BCM4752) += bcm4752.o +obj-$(CONFIG_GPS_GSD4T) += gsd4t.o obj-$(CONFIG_SEC_THERMISTOR) += sec_thermistor.o obj-$(CONFIG_EXYNOS_SYSREG_PM) += sysreg.o +obj-$(CONFIG_EXYNOS4_DEV_TMU) += dev-slp-tmu.o obj-$(CONFIG_QC_MODEM_MDM9X15) += mdm2.o mdm_common.o mdm_device.o -obj-$(CONFIG_MSM_SUBSYSTEM_RESTART) += subsystem_notif.o subsystem_restart.o +obj-$(CONFIG_MSM_SUBSYSTEM_RESTART) += subsystem_restart.o +obj-$(CONFIG_MDM_HSIC_PM) += mdm_hsic_pm.o +ifeq ($(CONFIG_MACH_T0),y) +obj-$(CONFIG_INPUT_WACOM) += midas-wacom.o +endif + +obj-$(CONFIG_CORESIGHT_ETM) += coresight.o coresight-etb.o coresight-tpiu.o coresight-funnel.o coresight-etm.o + +# for audio platform data driver +obj-$(CONFIG_EXYNOS_SOUND_PLATFORM_DATA) += exynos_sound_platform_data.o diff --git a/arch/arm/mach-exynos/asv-4x12.c b/arch/arm/mach-exynos/asv-4x12.c index 4953af7..db5f83b 100644 --- a/arch/arm/mach-exynos/asv-4x12.c +++ b/arch/arm/mach-exynos/asv-4x12.c @@ -61,6 +61,41 @@ struct asv_judge_table exynos4x12_limit[] = { {999, 999}, /* Reserved Group */ }; +struct asv_judge_table exynos4x12_limit_rev2[] = { +#if 0 + /* 0705 dvfs table */ + /* HPM, IDS */ + { 0, 0}, /* Reserved Group */ + { 15, 8}, /* ASV1 Group */ + { 16, 11}, + { 18, 14}, + { 19, 18}, + { 20, 22}, + { 21, 26}, + { 22, 29}, + { 23, 36}, + { 24, 44}, + { 25, 56}, + {999, 999}, /* ASV11 Group */ +#else + /* 0725 dvfs table */ + /* HPM, IDS */ + { 0, 0}, /* Reserved Group */ + { 15, 8}, /* ASV1 Group */ + { 16, 11}, + { 18, 14}, + { 19, 18}, + { 20, 22}, + { 21, 26}, + { 22, 29}, + { 23, 36}, + { 24, 40}, + { 25, 45}, + { 26, 50}, + {999, 999}, /* ASV11 Group */ +#endif +}; + struct asv_judge_table exynos4212_limit[] = { /* HPM, IDS */ { 0, 0}, /* Reserved Group */ @@ -93,17 +128,63 @@ static int exynos4x12_get_ids(struct samsung_asv *asv_info) static void exynos4x12_pre_set_abb(void) { - switch (exynos_result_of_asv) { - case 0: - case 1: - case 2: - case 3: - exynos4x12_set_abb(ABB_MODE_100V); - break; - - default: - exynos4x12_set_abb(ABB_MODE_130V); - break; + if (samsung_rev() >= EXYNOS4412_REV_2_0) { + switch (exynos_result_of_asv) { + case 0: + case 1: + exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_075V); + exynos4x12_set_abb_member(ABB_INT, ABB_MODE_100V); + exynos4x12_set_abb_member(ABB_MIF, ABB_MODE_100V); + exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); + break; + case 2: + exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_100V); + exynos4x12_set_abb_member(ABB_INT, ABB_MODE_100V); + exynos4x12_set_abb_member(ABB_MIF, ABB_MODE_140V); + exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); + break; + case 3: + case 4: + case 5: + case 6: + case 7: + exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V); + exynos4x12_set_abb_member(ABB_INT, ABB_MODE_130V); + exynos4x12_set_abb_member(ABB_MIF, ABB_MODE_140V); + exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); + break; + case 8: + case 9: + case 10: + case 11: + case 12: + exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V); + exynos4x12_set_abb_member(ABB_INT, ABB_MODE_130V); + exynos4x12_set_abb_member(ABB_MIF, ABB_MODE_140V); + exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V); + break; + default: + exynos4x12_set_abb(ABB_MODE_130V); + break; + } + } else { + switch (exynos_result_of_asv) { + case 0: + case 1: + case 2: + case 3: + exynos4x12_set_abb(ABB_MODE_100V); + break; + case 4: + case 5: + case 6: + case 7: + exynos4x12_set_abb(ABB_MODE_130V); + break; + default: + exynos4x12_set_abb(ABB_MODE_130V); + break; + } } } @@ -112,11 +193,21 @@ static int exynos4x12_asv_store_result(struct samsung_asv *asv_info) unsigned int i; if (soc_is_exynos4412()) { - for (i = 0; i < ARRAY_SIZE(exynos4x12_limit); i++) { - if ((asv_info->ids_result <= exynos4x12_limit[i].ids_limit) || - (asv_info->hpm_result <= exynos4x12_limit[i].hpm_limit)) { - exynos_result_of_asv = i; - break; + if (samsung_rev() >= EXYNOS4412_REV_2_0) { + for (i = 0; i < ARRAY_SIZE(exynos4x12_limit_rev2); i++) { + if ((asv_info->ids_result <= exynos4x12_limit_rev2[i].ids_limit) || + (asv_info->hpm_result <= exynos4x12_limit_rev2[i].hpm_limit)) { + exynos_result_of_asv = i; + break; + } + } + } else { + for (i = 0; i < ARRAY_SIZE(exynos4x12_limit); i++) { + if ((asv_info->ids_result <= exynos4x12_limit[i].ids_limit) || + (asv_info->hpm_result <= exynos4x12_limit[i].hpm_limit)) { + exynos_result_of_asv = i; + break; + } } } } else { @@ -137,8 +228,10 @@ static int exynos4x12_asv_store_result(struct samsung_asv *asv_info) if (exynos_result_of_asv < DEFAULT_ASV_GROUP) exynos_result_of_asv = DEFAULT_ASV_GROUP; +#ifndef CONFIG_SAMSUNG_PRODUCT_SHIP pr_info("EXYNOS4X12(NO SG): IDS : %d HPM : %d RESULT : %d\n", asv_info->ids_result, asv_info->hpm_result, exynos_result_of_asv); +#endif exynos4x12_pre_set_abb(); @@ -153,6 +246,8 @@ int exynos4x12_asv_init(struct samsung_asv *asv_info) int exynos_cal_asv; exynos_result_of_asv = 0; + exynos_special_flag = 0; + exynos_dynamic_ema = false; pr_info("EXYNOS4X12: Adaptive Support Voltage init\n"); @@ -161,6 +256,31 @@ int exynos4x12_asv_init(struct samsung_asv *asv_info) /* Store PKG_ID */ asv_info->pkg_id = tmp; +#ifdef CONFIG_EXYNOS4X12_1000MHZ_SUPPORT + exynos_armclk_max = 1000000; +#else + /* If maximum armclock is fused, set its value */ + if (samsung_rev() < EXYNOS4412_REV_2_0) { + switch (tmp & MOD_SG_MASK) { + case 0: + case 3: + exynos_armclk_max = 1400000; + break; + case 2: + exynos_armclk_max = 1000000; + break; + default: + exynos_armclk_max = 1400000; + break; + } + } +#endif + + if ((tmp >> EMA_OFFSET) & EMA_MASK) + exynos_dynamic_ema = true; + else + exynos_dynamic_ema = false; + /* If Speed group is fused, get speed group from */ if ((tmp >> FUSED_SG_OFFSET) & 0x1) { exynos_orig_sp = (tmp >> ORIG_SG_OFFSET) & ORIG_SG_MASK; @@ -185,11 +305,17 @@ int exynos4x12_asv_init(struct samsung_asv *asv_info) pr_info("EXYNOS4X12(SG): ORIG : %d MOD : %d RESULT : %d\n", exynos_orig_sp, exynos_mod_sp, exynos_result_of_asv); + /* set Special flag into exynos_special_flag */ + exynos_special_flag = (tmp >> LOCKING_OFFSET) & LOCKING_MASK; + exynos4x12_pre_set_abb(); return -EEXIST; } + /* set Special flag into exynos_special_flag */ + exynos_special_flag = (tmp >> LOCKING_OFFSET) & LOCKING_MASK; + asv_info->get_ids = exynos4x12_get_ids; asv_info->get_hpm = exynos4x12_get_hpm; asv_info->store_result = exynos4x12_asv_store_result; diff --git a/arch/arm/mach-exynos/asv-5250.c b/arch/arm/mach-exynos/asv-5250.c deleted file mode 100644 index 867154f..0000000 --- a/arch/arm/mach-exynos/asv-5250.c +++ /dev/null @@ -1,200 +0,0 @@ -/* linux/arch/arm/mach-exynos/asv-4x12.c - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS5250 - ASV(Adaptive Supply Voltage) driver - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/string.h> - -#include <mach/asv.h> -#include <mach/map.h> - -#include <plat/cpu.h> - -/* ASV function for Fused Chip */ -#define IDS_ARM_OFFSET 24 -#define IDS_ARM_MASK 0xFF -#define HPM_OFFSET 12 -#define HPM_MASK 0x1F - -#define FUSED_SG_OFFSET 3 -#define ORIG_SG_OFFSET 17 -#define ORIG_SG_MASK 0xF -#define MOD_SG_OFFSET 21 -#define MOD_SG_MASK 0x7 - -#define DEFAULT_ASV_GROUP 1 - -#define CHIP_ID_REG (S5P_VA_CHIPID + 0x4) -#define LOT_ID_REG (S5P_VA_CHIPID + 0x14) - -struct asv_judge_table exynos5250_limit[] = { - /* HPM, IDS */ - { 0, 0}, /* Reserved Group */ - { 9, 7}, - { 10, 9}, - { 12, 11}, - { 14, 14}, - { 15, 17}, - { 16, 20}, - { 17, 23}, - { 18, 27}, - { 19, 30}, - {100, 100}, - {999, 999}, /* Reserved Group */ -}; - -static int exynos5250_get_hpm(struct samsung_asv *asv_info) -{ - asv_info->hpm_result = (asv_info->pkg_id >> HPM_OFFSET) & HPM_MASK; - - return 0; -} - -static int exynos5250_get_ids(struct samsung_asv *asv_info) -{ - asv_info->ids_result = (asv_info->pkg_id >> IDS_ARM_OFFSET) & IDS_ARM_MASK; - - return 0; -} - -/* - * If lot id is "NZVPU", it is need to modify for ARM_IDS value - */ -static int exynos5250_check_lot_id(void) -{ - unsigned int lid_reg = 0; - unsigned int rev_lid = 0; - unsigned int i; - unsigned int tmp; - char lot_id[5]; - - lid_reg = __raw_readl(LOT_ID_REG); - - for (i = 0; i < 32; i++) { - tmp = (lid_reg >> i) & 0x1; - rev_lid += tmp << (31 - i); - } - - lot_id[0] = 'N'; - lid_reg = (rev_lid >> 11) & 0x1FFFFF; - - for (i = 4; i >= 1; i--) { - tmp = lid_reg % 36; - lid_reg /= 36; - lot_id[i] = (tmp < 10) ? (tmp + '0') : ((tmp - 10) + 'A'); - } - - return strncmp(lot_id, "NZVPU", ARRAY_SIZE(lot_id)); -} - -static void exynos5250_pre_set_abb(void) -{ - switch (exynos_result_of_asv) { - case 0: - case 1: - case 2: - exynos4x12_set_abb(ABB_MODE_080V); - break; - case 3: - case 4: - exynos4x12_set_abb(ABB_MODE_BYPASS); - break; - default: - exynos4x12_set_abb(ABB_MODE_130V); - break; - } -} - -static int exynos5250_asv_store_result(struct samsung_asv *asv_info) -{ - unsigned int i; - - if (!exynos5250_check_lot_id()) - asv_info->ids_result -= 15; - - if (soc_is_exynos5250()) { - for (i = 0; i < ARRAY_SIZE(exynos5250_limit); i++) { - if ((asv_info->ids_result <= exynos5250_limit[i].ids_limit) || - (asv_info->hpm_result <= exynos5250_limit[i].hpm_limit)) { - exynos_result_of_asv = i; - break; - } - } - } - - /* - * If ASV result value is lower than default value - * Fix with default value. - */ - if (exynos_result_of_asv < DEFAULT_ASV_GROUP) - exynos_result_of_asv = DEFAULT_ASV_GROUP; - - pr_info("EXYNOS5250(NO SG): IDS : %d HPM : %d RESULT : %d\n", - asv_info->ids_result, asv_info->hpm_result, exynos_result_of_asv); - - exynos5250_pre_set_abb(); - - return 0; -} - -int exynos5250_asv_init(struct samsung_asv *asv_info) -{ - unsigned int tmp; - unsigned int exynos_orig_sp; - unsigned int exynos_mod_sp; - int exynos_cal_asv; - - exynos_result_of_asv = 0; - - pr_info("EXYNOS5250: Adaptive Support Voltage init\n"); - - tmp = __raw_readl(CHIP_ID_REG); - - /* Store PKG_ID */ - asv_info->pkg_id = tmp; - - /* If Speed group is fused, get speed group from */ - if ((tmp >> FUSED_SG_OFFSET) & 0x1) { - exynos_orig_sp = (tmp >> ORIG_SG_OFFSET) & ORIG_SG_MASK; - exynos_mod_sp = (tmp >> MOD_SG_OFFSET) & MOD_SG_MASK; - - exynos_cal_asv = exynos_orig_sp - exynos_mod_sp; - /* - * If There is no origin speed group, - * store 1 asv group into exynos_result_of_asv. - */ - if (!exynos_orig_sp) { - pr_info("EXYNOS5250: No Origin speed Group\n"); - exynos_result_of_asv = DEFAULT_ASV_GROUP; - } else { - if (exynos_cal_asv < DEFAULT_ASV_GROUP) - exynos_result_of_asv = DEFAULT_ASV_GROUP; - else - exynos_result_of_asv = exynos_cal_asv; - } - - pr_info("EXYNOS5250(SG): ORIG : %d MOD : %d RESULT : %d\n", - exynos_orig_sp, exynos_mod_sp, exynos_result_of_asv); - - return -EEXIST; - } - - asv_info->get_ids = exynos5250_get_ids; - asv_info->get_hpm = exynos5250_get_hpm; - asv_info->store_result = exynos5250_asv_store_result; - - return 0; -} diff --git a/arch/arm/mach-exynos/asv.c b/arch/arm/mach-exynos/asv.c index 7812009..7fa388d 100644 --- a/arch/arm/mach-exynos/asv.c +++ b/arch/arm/mach-exynos/asv.c @@ -104,6 +104,6 @@ static int __init exynos4_asv_init(void) out2: kfree(exynos_asv); out1: - return -EINVAL; + return ret; } device_initcall_sync(exynos4_asv_init); diff --git a/arch/arm/mach-exynos/baffin-gpio.c b/arch/arm/mach-exynos/baffin-gpio.c new file mode 100644 index 0000000..98284b9 --- /dev/null +++ b/arch/arm/mach-exynos/baffin-gpio.c @@ -0,0 +1,586 @@ +/* + * linux/arch/arm/mach-exynos/baffin-gpio.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - GPIO setting in set board + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/serial_core.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-serial.h> +#include <mach/gpio-midas.h> +#include <plat/cpu.h> +#include <mach/pmu.h> + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + +/* + * baffin GPIO Init Table + */ +static struct gpio_init_data baffin_init_gpios[] = { + {EXYNOS4_GPA1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + + {EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */ + {EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SCL_1.8V */ + + {EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */ + {EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */ + + {EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* DET_3.5 */ + {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */ + {EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + + {EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */ + + {EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */ + + {EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* V_BUS_INT */ + {EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */ + {EXYNOS4_GPX2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_HOST_WAKEUP */ + {EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */ + {EXYNOS4_GPX2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* nPower */ + + {EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */ + {EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */ + {EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */ + {EXYNOS4_GPK3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CLK */ + {EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */ + {EXYNOS4_GPK3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */ + {EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */ + {EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */ + {EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */ + + {EXYNOS4212_GPM3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PMIC_DVS1 */ + {EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + + {EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* CAM_MCLK */ + {EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* VTCAM_MCLK */ + + {EXYNOS4_GPK2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV4}, /* SD_CLK */ + {EXYNOS4_GPK2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV4}, /* SD_CMD */ + {EXYNOS4_GPK2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV4}, /* SD_nCD(NC) */ + {EXYNOS4_GPK2(3), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT0 */ + {EXYNOS4_GPK2(4), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT1 */ + {EXYNOS4_GPK2(5), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT2 */ + {EXYNOS4_GPK2(6), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT3 */ +}; + +/* + * BAFFIN GPIO Sleep Table + */ +static unsigned int baffin_sleep_gpio_table[][3] = { + {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_RXD */ + {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* BT_UART_TXD */ + {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_CTS */ + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* BT_UART_RTS */ + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GPS_UART_RXD */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_TXD */ + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_CTS */ + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* GPS_UART_RTS */ + + {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_RXD */ + {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_TXD */ + {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SDA_1.8V */ + {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SCL_1.8V */ +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4_GPA1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_TXD_1.8V */ + {EXYNOS4_GPA1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_RXD_1.8V */ +#else + {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + + {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SDA_1.8V */ + {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SCL_1.8V */ + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSCL_1.8V,NFC_SCL_1.8V */ + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSDA_1.8V,NFC_SDA_1.8V */ + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_SCLK */ + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* CAM_SPI_SSN */ + {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MISO */ + {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MOSI */ + + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */ + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_2.2V_EN */ +#if defined(CONFIG_MACH_BAFFIN_KOR_SKT) || defined(CONFIG_MACH_BAFFIN_KOR_KT) + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CP_WAKEUP_1.8V */ +#endif + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_INT */ + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CP_RST_INDICATE_1.8V */ +#else + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_CLK */ + {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_CS */ + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_DI */ + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_SPI_DO */ + + {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VIBTONE_PWM */ + {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SDA_1.8V */ + {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SCL_1.8V */ + + {EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SDA_1.8V */ + {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SCL_1.8V */ + {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GSENSE_SDA_1.8V */ + {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GSENSE_SCL_1.8V */ + + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* RGB_SDA_1.8V_AP */ + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* RGB_SCL_1.8V_AP */ + {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GYRO_INT */ + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_SDA_1.8V */ + {EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* BARO_INT */ + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_SCL_1.8V */ + {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OTG_EN */ + + {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OLED_ID */ + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* ACTIVE_STATE_HSIC */ + {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_ID */ + {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RESET */ + {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SCL_1.8V */ + {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SDA_1.8V */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */ + {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBIAS_EN */ + + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MICBIAS_EN */ + {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MLCD_RST */ + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CMC_INT */ +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AUTO_DFS */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_RST_1.8V */ +#else + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */ + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */ + + {EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* OLED_DET */ + {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */ + {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */ + {EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */ + {EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_RST */ + {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_INT */ + + {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */ + {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */ + {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */ + {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */ + {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */ + {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */ + {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */ + + {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */ + {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */ + {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */ + {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */ + + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CLK */ + {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CMD */ + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(0) */ + {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(1) */ + {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(2) */ + {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(3) */ + + {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CLK */ + {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CMD */ + {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(0) */ + {EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(1) */ + {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(2) */ + {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(3) */ + + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* USB_HUB_RST */ + {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* GPIO_FM34_PWDN */ +#else + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */ +/* {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ + {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BT_EN */ +/* {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ + + {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_HUB_SCL */ + {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* USB_HUB_SDA */ +/* {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, */ + + {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GYRO_DE */ + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_nRST */ + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_EN */ + {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC221_CPU_RST */ + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_PMIC_PWRON */ + {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NFC_EN */ + {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NFC_FIRMWARE */ + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_CSN */ + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* VIA_DPRAM_CSN */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_REN */ + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_WEN */ +#else + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_CSN */ + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_REN */ + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_WEN */ +#endif + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_LBN */ + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_UBN */ +#else + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VP_BP_N */ + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VP_RST_N */ +#else + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ + {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BSENSE_SDA_1.8V */ + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BSENSE_SCL_1.8V */ + {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MSENSE_SDA_1.8V */ + {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MSENSE_SCL_1.8V */ + + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(0) */ + {EXYNOS4_GPY3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(1) */ + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(2) */ + {EXYNOS4_GPY3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(3) */ + {EXYNOS4_GPY3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(4) */ + {EXYNOS4_GPY3(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(5) */ + {EXYNOS4_GPY3(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(6) */ + {EXYNOS4_GPY3(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(7) */ + + {EXYNOS4_GPY4(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(8) */ + {EXYNOS4_GPY4(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(9) */ + {EXYNOS4_GPY4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(10) */ + {EXYNOS4_GPY4(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(11) */ + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(12) */ + {EXYNOS4_GPY4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* DPRAM_A(13) */ + {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(0) */ + {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(1) */ + {EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(2) */ + {EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(3) */ + {EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(4) */ + {EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(5) */ + {EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(6) */ + {EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(7) */ + + {EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(8) */ + {EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(9) */ + {EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(10) */ + {EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(11) */ + {EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(12) */ + {EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(13) */ + {EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(14) */ + {EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* DPRAM_D(15) */ + + {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_CLK */ + {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_SYNC */ + {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DI */ + {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DO */ + {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + /* Exynos4212 specific gpio */ + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WLAN_EN */ + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_USB_DETECT(Cur NC) */ + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */ + {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PS_ALS_EN */ +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* LTE_VIA_UART_SEL */ +#else + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MSENSE_INT */ + + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_EN */ + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_SET */ + {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_MCLK */ + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_WAKE_UP */ + + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* LED_VDD_EN */ + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_STANDBY */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_IO_EN */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_ISP_CORE_EN */ + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_AF_EN */ +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_BOOT_SEL_1.8V */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_ON */ +#else + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* CAM_SENSOR_CORE_EN */ + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_PS_HOLD_OFF */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_USB_OFF */ +#else + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV0 */ + {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV1 */ + {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV2 */ + {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* HW_REV3 */ + {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_VT_nRST */ + + {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SDA_1.8V */ + {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SCL_1.8V */ + {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* CAM_MCLK_VGA */ + {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_nINT */ + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* SUSPEND_REQUEST_HSIC */ + + {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */ + {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */ + {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(SKT,KT),ISP_TXD(LGT) */ + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_SPI_CLK_REQ */ + {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(SKT,KT),ISP_RXD(LGT) */ + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* VP_SCL */ + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* VP_SDA */ +#else + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */ + {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */ + {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_CLK_1.8V */ + {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_CS_1.8V */ + {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_DI_1.8V */ + {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_DO_1.8V */ + + {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +}; /* baffin_sleep_gpio_table */ + +struct baffin_sleep_table { + unsigned int (*ptr)[3]; + int size; +}; + +#define GPIO_TABLE(_ptr) \ + {.ptr = _ptr, \ + .size = ARRAY_SIZE(_ptr)} \ + + #define GPIO_TABLE_NULL \ + {.ptr = NULL, \ + .size = 0} \ + +static struct baffin_sleep_table baffin_sleep_table[] = { + GPIO_TABLE(baffin_sleep_gpio_table),/* Rev0.0 (0x00) */ + GPIO_TABLE_NULL, +}; + +static void config_sleep_gpio_table(int array_size, + unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +/* To save power consumption, gpio pin set before enterling sleep */ +void midas_config_sleep_gpio_table(void) +{ + int i; + int index = min(ARRAY_SIZE(baffin_sleep_table), system_rev + 1); + + for (i = 0; i < index; i++) { + if (baffin_sleep_table[i].ptr == NULL) + continue; + + config_sleep_gpio_table(baffin_sleep_table[i].size, + baffin_sleep_table[i].ptr); + } +} + +/* Intialize gpio set in midas board */ +void midas_config_gpio_table(void) +{ + u32 i, gpio; + + printk(KERN_DEBUG "%s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(baffin_init_gpios); i++) { + gpio = baffin_init_gpios[i].num; + if (gpio <= EXYNOS4212_GPV4(1)) { + s3c_gpio_cfgpin(gpio, baffin_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, baffin_init_gpios[i].pud); + + if (baffin_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, baffin_init_gpios[i].val); + + s5p_gpio_set_drvstr(gpio, baffin_init_gpios[i].drv); + } + } +} diff --git a/arch/arm/mach-exynos/baffin-power.c b/arch/arm/mach-exynos/baffin-power.c new file mode 100644 index 0000000..537f43a --- /dev/null +++ b/arch/arm/mach-exynos/baffin-power.c @@ -0,0 +1,1131 @@ +/* + * midas-power.c - Power Management of MIDAS Project + * + * Copyright (C) 2011 Samsung Electrnoics + * Chiwoong Byun <woong.byun@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/i2c.h> +#include <linux/regulator/machine.h> +#include <plat/gpio-cfg.h> +#include <mach/gpio-midas.h> +#include <mach/irqs.h> +#if defined(CONFIG_MACH_SLP_PQ) +#include <asm/mach-types.h> +#endif +#include <linux/mfd/max8997.h> +#include <linux/mfd/max77686.h> +#include <linux/mfd/max77693.h> + +#if defined(CONFIG_REGULATOR_S5M8767) +#include <linux/mfd/s5m87xx/s5m-pmic.h> +#include <linux/mfd/s5m87xx/s5m-core.h> +#endif + +#ifdef CONFIG_REGULATOR_MAX8997 +/* MOTOR */ +#ifdef CONFIG_VIBETONZ +static void max8997_motor_init(void) +{ + gpio_request(GPIO_VIBTONE_EN, "VIBTONE_EN"); + s3c_gpio_cfgpin(GPIO_VIBTONE_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_VIBTONE_EN, S3C_GPIO_PULL_NONE); +} + +static void max8997_motor_en(bool en) +{ + gpio_direction_output(GPIO_VIBTONE_EN, en); +} + +static struct max8997_motor_data max8997_motor = { + .max_timeout = 10000, + .duty = 44000, + .period = 44642, + .reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128, + .init_hw = max8997_motor_init, + .motor_en = max8997_motor_en, + .pwm_id = 1, +}; +#endif + +/* max8997 */ +static struct regulator_consumer_supply ldo1_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim"), +}; + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo6_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo7_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("votg_3.0v", NULL), +}; + +static struct regulator_consumer_supply ldo11_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim"), +}; + +static struct regulator_consumer_supply ldo13_supply[] = { + REGULATOR_SUPPLY("vlcd_3.3v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo14_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo15_supply[] = { + REGULATOR_SUPPLY("vlcd_2.2v", NULL), + REGULATOR_SUPPLY("VDD3", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo12_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo16_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo17_supply[] = { + REGULATOR_SUPPLY("cam_af_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo18_supply[] = { + REGULATOR_SUPPLY("touch", NULL), +}; + +static struct regulator_consumer_supply max8997_buck1 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max8997_buck2[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynos4412-busfreq"), +}; + +static struct regulator_consumer_supply max8997_buck3 = + REGULATOR_SUPPLY("vdd_g3d", NULL); + +static struct regulator_consumer_supply max8997_buck4 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo1, "VMIPI_1.8V", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo6, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo7, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo8, "VUOTG_3.0V", 3000000, 3000000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo11, "VMIPI_1.0V", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo13, "VCC_3.3V_LCD", 3300000, 3300000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo14, "VCC_1.8V_IO", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo15, "VDD_2.2V_LCD", 2200000, 2200000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo16, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo17, "CAM_AF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo18, "TSP_AVDD_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data max8997_buck1_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 950000, + .max_uV = 1100000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck1, +}; + +static struct regulator_init_data max8997_buck2_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 900000, + .max_uV = 1100000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(max8997_buck2), + .consumer_supplies = max8997_buck2, +}; + +static struct regulator_init_data max8997_buck3_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 950000, + .max_uV = 1150000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck3, +}; + +static struct regulator_init_data max8997_buck4_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck4, +}; + +static struct max8997_regulator_data max8997_regulators[] = { + { MAX8997_BUCK1, &max8997_buck1_data, }, + { MAX8997_BUCK2, &max8997_buck2_data, }, + { MAX8997_BUCK3, &max8997_buck3_data, }, + { MAX8997_BUCK4, &max8997_buck4_data, }, + { MAX8997_LDO1, &ldo1_init_data, }, + { MAX8997_LDO6, &ldo6_init_data, }, + { MAX8997_LDO7, &ldo7_init_data, }, + { MAX8997_LDO8, &ldo8_init_data, }, + { MAX8997_LDO11, &ldo11_init_data, }, + { MAX8997_LDO12, &ldo12_init_data, }, + { MAX8997_LDO13, &ldo13_init_data, }, + { MAX8997_LDO14, &ldo14_init_data, }, + { MAX8997_LDO15, &ldo15_init_data, }, + { MAX8997_LDO16, &ldo16_init_data, }, + { MAX8997_LDO17, &ldo17_init_data, }, + { MAX8997_LDO18, &ldo18_init_data, }, +}; + +struct max8997_platform_data exynos4_max8997_info = { + .irq_base = IRQ_BOARD_PMIC_START, + .num_regulators = ARRAY_SIZE(max8997_regulators), + .regulators = max8997_regulators, + .buck1_max_vol = 1100000, + .buck2_max_vol = 1100000, + .buck5_max_vol = 1100000, + .buck_set1 = EXYNOS4212_GPJ1(1), + .buck_set2 = EXYNOS4212_GPJ1(2), + .buck_set3 = EXYNOS4_GPL0(0), +#ifdef CONFIG_VIBETONZ + .motor = &max8997_motor, +#endif +}; +#elif defined(CONFIG_REGULATOR_MAX77686) +/* max77686 */ + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo3_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +#ifdef CONFIG_MACH_REDWOOD + REGULATOR_SUPPLY("VDDI", "s6d6aa1"), +#endif +}; +#else +static struct regulator_consumer_supply ldo3_supply[] = {}; +#endif + +static struct regulator_consumer_supply ldo5_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v", NULL), + REGULATOR_SUPPLY("touchkey", NULL), +}; + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), + REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), +}; + +static struct regulator_consumer_supply ldo9_supply[] = { + REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo10_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), +}; + +static struct regulator_consumer_supply ldo11_supply[] = { + REGULATOR_SUPPLY("vabb1_1.95v", NULL), +}; + +static struct regulator_consumer_supply ldo12_supply[] = { + REGULATOR_SUPPLY("votg_3.0v", NULL), +}; + +static struct regulator_consumer_supply ldo14_supply[] = { + REGULATOR_SUPPLY("vabb2_1.95v", NULL), +}; + +static struct regulator_consumer_supply ldo17_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo18_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo19_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo21_supply[] = { + REGULATOR_SUPPLY("vtf_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo23_supply[] = { + REGULATOR_SUPPLY("touch", NULL), +}; + +static struct regulator_consumer_supply ldo24_supply[] = { + REGULATOR_SUPPLY("touch_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo25_supply[] = { + REGULATOR_SUPPLY("vlcd_3.3v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +#if defined(CONFIG_MACH_SLP_T0_LTE) + REGULATOR_SUPPLY("VCI", "ea8061"), +#endif +}; + +static struct regulator_consumer_supply ldo26_supply[] = { + REGULATOR_SUPPLY("vmotor", NULL), +}; + +static struct regulator_consumer_supply max77686_buck1[] = { + REGULATOR_SUPPLY("vdd_mif", NULL), + REGULATOR_SUPPLY("vdd_mif", "exynos4412-busfreq"), +}; + +static struct regulator_consumer_supply max77686_buck2 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max77686_buck3[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"), +}; + +static struct regulator_consumer_supply max77686_buck4[] = { + REGULATOR_SUPPLY("vdd_g3d", NULL), + REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"), +}; + +static struct regulator_consumer_supply max77686_buck9 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); + +static struct regulator_consumer_supply max77686_enp32khz[] = { + REGULATOR_SUPPLY("lpo_in", "bcm47511"), + REGULATOR_SUPPLY("lpo_in", "bcm4752"), + REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"), +}; + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo5, "VCC_1.8V_IO", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo9, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo11, "VABB1_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo14, "VABB2_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo17, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo18, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo19, "VT_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo23, "TSP_AVDD_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo24, "VDD_1.8V_TSP", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo25, "VCC_3.3V_LCD", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo26, "VCC_MOTOR_3.0V", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); + +#if defined(CONFIG_MACH_SLP_PQ) +static struct regulator_init_data ldo24_pq11_init_data = { + .constraints = { + .name = "VDD_1.8V_TSP", + .min_uV = 1800000, + .max_uV = 1800000, + .always_on = 0, + .boot_on = 0, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 0, + .disabled = 1, + } + }, + .num_consumer_supplies = 1, + .consumer_supplies = ldo24_supply, +}; + +static struct regulator_init_data ldo25_redwood_init_data = { + .constraints = { + .name = "LED_A_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .always_on = 0, + .boot_on = 0, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 0, + .disabled = 1, + } + }, + .num_consumer_supplies = 1, + .consumer_supplies = ldo25_supply, +}; + +#endif + +static struct regulator_init_data max77686_buck1_data = { + .constraints = { + .name = "vdd_mif range", + .min_uV = 850000, +#ifdef CONFIG_SLP + .max_uV = 1100000, +#else + .max_uV = 1050000, +#endif + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck1), + .consumer_supplies = max77686_buck1, +}; + +static struct regulator_init_data max77686_buck2_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 850000, + .max_uV = 1500000, + .apply_uV = 1, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max77686_buck2, +}; + +static struct regulator_init_data max77686_buck3_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 850000, +#ifdef CONFIG_SLP + .max_uV = 1150000, +#else + .max_uV = 1100000, +#endif + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck3), + .consumer_supplies = max77686_buck3, +}; + +static struct regulator_init_data max77686_buck4_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 850000, +#ifdef CONFIG_SLP + .max_uV = 1100000, +#else + .max_uV = 1075000, +#endif + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck4), + .consumer_supplies = max77686_buck4, +}; + +static struct regulator_init_data max77686_buck9_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1000000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max77686_buck9, +}; + +static struct regulator_init_data max77686_enp32khz_data = { + .constraints = { + .name = "32KHZ_PMIC", + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz), + .consumer_supplies = max77686_enp32khz, +}; + +static struct max77686_regulator_data max77686_regulators[] = { + {MAX77686_BUCK1, &max77686_buck1_data,}, + {MAX77686_BUCK2, &max77686_buck2_data,}, + {MAX77686_BUCK3, &max77686_buck3_data,}, + {MAX77686_BUCK4, &max77686_buck4_data,}, + {MAX77686_BUCK9, &max77686_buck9_data,}, + {MAX77686_LDO3, &ldo3_init_data,}, + {MAX77686_LDO5, &ldo5_init_data,}, + {MAX77686_LDO8, &ldo8_init_data,}, + {MAX77686_LDO9, &ldo9_init_data,}, + {MAX77686_LDO10, &ldo10_init_data,}, + {MAX77686_LDO11, &ldo11_init_data,}, + {MAX77686_LDO12, &ldo12_init_data,}, + {MAX77686_LDO14, &ldo14_init_data,}, + {MAX77686_LDO17, &ldo17_init_data,}, + {MAX77686_LDO18, &ldo18_init_data,}, + {MAX77686_LDO19, &ldo19_init_data,}, + {MAX77686_LDO21, &ldo21_init_data,}, + {MAX77686_LDO23, &ldo23_init_data,}, + {MAX77686_LDO24, &ldo24_init_data,}, + {MAX77686_LDO25, &ldo25_init_data,}, + {MAX77686_LDO26, &ldo26_init_data,}, + {MAX77686_P32KH, &max77686_enp32khz_data,}, +}; + +struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = { + [MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL}, + [MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY}, +}; + +struct max77686_platform_data exynos4_max77686_info = { + .num_regulators = ARRAY_SIZE(max77686_regulators), + .regulators = max77686_regulators, + .irq_gpio = GPIO_PMIC_IRQ, + .irq_base = IRQ_BOARD_PMIC_START, + .wakeup = 1, + + .opmode_data = max77686_opmode_data, + .ramp_rate = MAX77686_RAMP_RATE_27MV, + .wtsr_smpl = MAX77686_WTSR_ENABLE | MAX77686_SMPL_ENABLE, + + .buck234_gpio_dvs = { + /* Use DVS2 register of each bucks to supply stable power + * after sudden reset */ + {GPIO_PMIC_DVS1, 1}, + {GPIO_PMIC_DVS2, 0}, + {GPIO_PMIC_DVS3, 0}, + }, + .buck234_gpio_selb = { + GPIO_BUCK2_SEL, + GPIO_BUCK3_SEL, + GPIO_BUCK4_SEL, + }, + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1100000, /* 1.1V */ + .buck2_voltage[2] = 1100000, /* 1.1V */ + .buck2_voltage[3] = 1100000, /* 1.1V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1100000, /* 1.1V */ + .buck2_voltage[6] = 1100000, /* 1.1V */ + .buck2_voltage[7] = 1100000, /* 1.1V */ + + .buck3_voltage[0] = 1100000, /* 1.1V */ + .buck3_voltage[1] = 1000000, /* 1.0V */ + .buck3_voltage[2] = 1100000, /* 1.1V */ + .buck3_voltage[3] = 1100000, /* 1.1V */ + .buck3_voltage[4] = 1100000, /* 1.1V */ + .buck3_voltage[5] = 1100000, /* 1.1V */ + .buck3_voltage[6] = 1100000, /* 1.1V */ + .buck3_voltage[7] = 1100000, /* 1.1V */ + + .buck4_voltage[0] = 1100000, /* 1.1V */ + .buck4_voltage[1] = 1000000, /* 1.0V */ + .buck4_voltage[2] = 1100000, /* 1.1V */ + .buck4_voltage[3] = 1100000, /* 1.1V */ + .buck4_voltage[4] = 1100000, /* 1.1V */ + .buck4_voltage[5] = 1100000, /* 1.1V */ + .buck4_voltage[6] = 1100000, /* 1.1V */ + .buck4_voltage[7] = 1100000, /* 1.1V */ +}; + +void midas_power_init(void) +{ + printk(KERN_INFO "%s\n", __func__); +} +#endif /* CONFIG_REGULATOR_MAX77686 */ + +void midas_power_set_muic_pdata(void *pdata, int gpio) +{ + gpio_request(gpio, "AP_PMIC_IRQ"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + +#ifdef CONFIG_REGULATOR_MAX8997 + exynos4_max8997_info.muic = pdata; +#endif +} + +void midas_power_gpio_init(void) +{ +#ifdef CONFIG_REGULATOR_MAX8997 + int gpio; + + gpio = EXYNOS4212_GPJ1(1); + gpio_request(gpio, "BUCK_SET1"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + gpio = EXYNOS4212_GPJ1(2); + gpio_request(gpio, "BUCK_SET2"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + gpio = EXYNOS4_GPL0(0); + gpio_request(gpio, "BUCK_SET3"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); +#endif +} + +#ifdef CONFIG_MFD_MAX77693 +static struct regulator_consumer_supply safeout1_supply[] = { + REGULATOR_SUPPLY("safeout1", NULL), +}; + +static struct regulator_consumer_supply safeout2_supply[] = { + REGULATOR_SUPPLY("safeout2", NULL), +}; + +static struct regulator_consumer_supply charger_supply[] = { + REGULATOR_SUPPLY("vinchg1", "charger-manager.0"), + REGULATOR_SUPPLY("vinchg1", NULL), +}; + +static struct regulator_init_data safeout1_init_data = { + .constraints = { + .name = "safeout1 range", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 1, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout1_supply), + .consumer_supplies = safeout1_supply, +}; + +static struct regulator_init_data safeout2_init_data = { + .constraints = { + .name = "safeout2 range", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 0, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout2_supply), + .consumer_supplies = safeout2_supply, +}; + +static struct regulator_init_data charger_init_data = { + .constraints = { + .name = "CHARGER", + .valid_ops_mask = REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_CURRENT, + .boot_on = 1, + .min_uA = 60000, + .max_uA = 2580000, + }, + .num_consumer_supplies = ARRAY_SIZE(charger_supply), + .consumer_supplies = charger_supply, +}; + +struct max77693_regulator_data max77693_regulators[] = { + {MAX77693_ESAFEOUT1, &safeout1_init_data,}, + {MAX77693_ESAFEOUT2, &safeout2_init_data,}, + {MAX77693_CHARGER, &charger_init_data,}, +}; + +#if defined(CONFIG_MACH_SLP_PQ) +/* this initcall replace ldo24 from VDD 2.2 to VDD 1.8 for evt1.1 board. */ +static int __init regulator_init_with_rev(void) +{ + /* SLP PQ Promixa evt1.1 */ + if (system_rev != 3) { + ldo24_supply[0].supply = "touch_1.8v"; + ldo24_supply[0].dev_name = NULL; + + memcpy(&ldo24_init_data, &ldo24_pq11_init_data, + sizeof(struct regulator_init_data)); + } + return 0; +} + +postcore_initcall(regulator_init_with_rev); + +static const char redwood_ldo25_name[] = "led_a_2.8v"; +static int __init regulator_init_with_redwood(void) +{ + /* SLP PQ redwood */ + if (__machine_arch_type == MACH_TYPE_REDWOOD) { + ldo25_supply[0].supply = redwood_ldo25_name; + + memcpy(&ldo25_init_data, &ldo25_redwood_init_data, + sizeof(struct regulator_init_data)); + } + + return 0; +} + +postcore_initcall(regulator_init_with_redwood); + + + +#endif /* CONFIG_MACH_SLP_PQ */ +#endif /* CONFIG_MFD_MAX77693 */ + +#if defined(CONFIG_REGULATOR_S5M8767) +/* S5M8767 Regulator */ + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo3_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"), +}; + +static struct regulator_consumer_supply ldo9_supply[] = { + REGULATOR_SUPPLY("cam_isp_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo10_supply[] = { + REGULATOR_SUPPLY("vt_cam_dvdd_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo13_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"), +}; + +static struct regulator_consumer_supply ldo19_supply[] = { + REGULATOR_SUPPLY("cam_af_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo20_supply[] = { + REGULATOR_SUPPLY("vlcd_3.0v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo21_supply[] = { + REGULATOR_SUPPLY("vmotor", NULL), +}; + +static struct regulator_consumer_supply ldo22_supply[] = { + REGULATOR_SUPPLY("cam_sensor_a2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo23_supply[] = { + REGULATOR_SUPPLY("vtf_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo24_supply[] = { + REGULATOR_SUPPLY("touch", NULL), +}; + +static struct regulator_consumer_supply ldo25_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo26_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo27_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo28_supply[] = { + REGULATOR_SUPPLY("3_touch_1.8v", NULL), +}; + +static struct regulator_consumer_supply s5m8767_buck1[] = { + REGULATOR_SUPPLY("vdd_mif", NULL), + REGULATOR_SUPPLY("vdd_mif", "exynos4212-busfreq"), +}; + +static struct regulator_consumer_supply s5m8767_buck2 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply s5m8767_buck3[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynos4212-busfreq"), +}; + +static struct regulator_consumer_supply s5m8767_buck4[] = { + REGULATOR_SUPPLY("vdd_g3d", NULL), + REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"), +}; + +static struct regulator_consumer_supply s5m8767_buck6 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); + +static struct regulator_consumer_supply s5m8767_enp32khz[] = { + REGULATOR_SUPPLY("lpo_in", "bcm47511"), + REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"), +}; + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo9, "CAM_ISP_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo10, "VT_CAM_DVDD_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo13, "VMIPI_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo19, "CAM_AF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo20, "VCC_3.0V_LCD", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo21, "VCC_MOTOR_3.0V", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo22, "CAM_SENSOR_A2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo23, "VTF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo24, "TSP_AVDD_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo26, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo27, "VT_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo28, "3_TOUCH_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data s5m8767_buck1_data = { + .constraints = { + .name = "vdd_mif range", + .min_uV = 850000, + .max_uV = 1100000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck1), + .consumer_supplies = s5m8767_buck1, +}; + +static struct regulator_init_data s5m8767_buck2_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 850000, + .max_uV = 1500000, + .apply_uV = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck2, +}; + +static struct regulator_init_data s5m8767_buck3_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 850000, + .max_uV = 1300000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck3), + .consumer_supplies = s5m8767_buck3, +}; + +static struct regulator_init_data s5m8767_buck4_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 850000, + .max_uV = 1150000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck4), + .consumer_supplies = s5m8767_buck4, +}; + +static struct regulator_init_data s5m8767_buck6_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1000000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck6, +}; + +static struct regulator_init_data s5m8767_enp32khz_data = { + .constraints = { + .name = "32KHZ_PMIC", + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_enp32khz), + .consumer_supplies = s5m8767_enp32khz, +}; + +static struct s5m_regulator_data s5m8767_regulators[] = { + {S5M8767_BUCK1, &s5m8767_buck1_data,}, + {S5M8767_BUCK2, &s5m8767_buck2_data,}, + {S5M8767_BUCK3, &s5m8767_buck3_data,}, + {S5M8767_BUCK4, &s5m8767_buck4_data,}, + {S5M8767_BUCK6, &s5m8767_buck6_data,}, + {S5M8767_LDO3, &ldo3_init_data,}, + {S5M8767_LDO8, &ldo8_init_data,}, + {S5M8767_LDO9, &ldo9_init_data,}, + {S5M8767_LDO10, &ldo10_init_data,}, + {S5M8767_LDO13, &ldo13_init_data,}, + {S5M8767_LDO19, &ldo19_init_data,}, + {S5M8767_LDO20, &ldo20_init_data,}, + {S5M8767_LDO21, &ldo21_init_data,}, + {S5M8767_LDO22, &ldo22_init_data,}, + {S5M8767_LDO23, &ldo23_init_data,}, + {S5M8767_LDO24, &ldo24_init_data,}, + {S5M8767_LDO25, &ldo25_init_data,}, + {S5M8767_LDO26, &ldo26_init_data,}, + {S5M8767_LDO27, &ldo27_init_data,}, + {S5M8767_LDO28, &ldo28_init_data,}, +}; + +struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = { + [S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK6] = {S5M8767_BUCK6, S5M_OPMODE_STANDBY}, + [S5M8767_LDO3] = {S5M8767_LDO3, S5M_OPMODE_NORMAL}, + [S5M8767_LDO8] = {S5M8767_LDO8, S5M_OPMODE_NORMAL}, + [S5M8767_LDO9] = {S5M8767_LDO9, S5M_OPMODE_NORMAL}, + [S5M8767_LDO10] = {S5M8767_LDO10, S5M_OPMODE_NORMAL}, + [S5M8767_LDO19] = {S5M8767_LDO19, S5M_OPMODE_NORMAL}, + [S5M8767_LDO20] = {S5M8767_LDO20, S5M_OPMODE_NORMAL}, + [S5M8767_LDO21] = {S5M8767_LDO21, S5M_OPMODE_NORMAL}, + [S5M8767_LDO22] = {S5M8767_LDO22, S5M_OPMODE_NORMAL}, + [S5M8767_LDO23] = {S5M8767_LDO23, S5M_OPMODE_STANDBY}, + [S5M8767_LDO24] = {S5M8767_LDO24, S5M_OPMODE_NORMAL}, + [S5M8767_LDO25] = {S5M8767_LDO25, S5M_OPMODE_NORMAL}, + [S5M8767_LDO26] = {S5M8767_LDO26, S5M_OPMODE_NORMAL}, + [S5M8767_LDO27] = {S5M8767_LDO27, S5M_OPMODE_NORMAL}, + [S5M8767_LDO28] = {S5M8767_LDO28, S5M_OPMODE_NORMAL}, +}; + +struct s5m_platform_data exynos4_s5m8767_info = { + .device_type = S5M8767X, + .num_regulators = ARRAY_SIZE(s5m8767_regulators), + .regulators = s5m8767_regulators, + .buck2_ramp_enable = true, + .buck3_ramp_enable = true, + .buck4_ramp_enable = true, + .irq_gpio = GPIO_PMIC_IRQ, + .irq_base = IRQ_BOARD_PMIC_START, + .wakeup = 1, + + .opmode_data = s5m8767_opmode_data, + .wtsr_smpl = 1, + + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1100000, /* 1.1V */ + .buck2_voltage[2] = 1100000, /* 1.1V */ + .buck2_voltage[3] = 1100000, /* 1.1V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1100000, /* 1.1V */ + .buck2_voltage[6] = 1100000, /* 1.1V */ + .buck2_voltage[7] = 1100000, /* 1.1V */ + + .buck3_voltage[0] = 1100000, /* 1.1V */ + .buck3_voltage[1] = 1100000, /* 1.1V */ + .buck3_voltage[2] = 1100000, /* 1.1V */ + .buck3_voltage[3] = 1100000, /* 1.1V */ + .buck3_voltage[4] = 1100000, /* 1.1V */ + .buck3_voltage[5] = 1100000, /* 1.1V */ + .buck3_voltage[6] = 1100000, /* 1.1V */ + .buck3_voltage[7] = 1100000, /* 1.1V */ + + .buck4_voltage[0] = 1100000, /* 1.1V */ + .buck4_voltage[1] = 1100000, /* 1.1V */ + .buck4_voltage[2] = 1100000, /* 1.1V */ + .buck4_voltage[3] = 1100000, /* 1.1V */ + .buck4_voltage[4] = 1100000, /* 1.1V */ + .buck4_voltage[5] = 1100000, /* 1.1V */ + .buck4_voltage[6] = 1100000, /* 1.1V */ + .buck4_voltage[7] = 1100000, /* 1.1V */ + + .buck_ramp_delay = 10, + .buck_default_idx = 3, + + .buck_gpios[0] = GPIO_BUCK2_SEL, + .buck_gpios[1] = GPIO_BUCK3_SEL, + .buck_gpios[2] = GPIO_BUCK4_SEL, +}; + +void midas_power_init(void) +{ + ldo8_init_data.constraints.always_on = 1; + ldo10_init_data.constraints.always_on = 1; +} + +/* End of S5M8767 */ +#endif diff --git a/arch/arm/mach-exynos/bcm4752.c b/arch/arm/mach-exynos/bcm4752.c new file mode 100644 index 0000000..a4671a8 --- /dev/null +++ b/arch/arm/mach-exynos/bcm4752.c @@ -0,0 +1,243 @@ +/* + * bcm4752.c: Machine specific driver for GPS module + * + * Copyright (c) 2011 Samsung Electronics + * Minho Ban <mhban@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/rfkill.h> +#include <linux/regulator/machine.h> + +#include <mach/gpio.h> +#include <mach/bcm4752.h> + +#include <plat/gpio-cfg.h> + +struct bcm4752_data { + struct bcm4752_platform_data *pdata; + struct rfkill *rfk; + bool in_use; + bool regulator_state; + struct regulator *regulator; +}; + +static void bcm4752_enable(void *data) +{ + struct bcm4752_data *bd = data; + struct bcm4752_platform_data *pdata = bd->pdata; + + if (bd->regulator && !bd->regulator_state) { + regulator_enable(bd->regulator); + bd->regulator_state = true; + } + + gpio_set_value(pdata->regpu, 1); + + if (gpio_is_valid(pdata->gps_cntl)) + gpio_set_value(pdata->gps_cntl, 1); + + bd->in_use = true; +} + +static void bcm4752_disable(void *data) +{ + struct bcm4752_data *bd = data; + struct bcm4752_platform_data *pdata = bd->pdata; + + gpio_set_value(pdata->regpu, 0); + + if (gpio_is_valid(pdata->gps_cntl)) + gpio_set_value(pdata->gps_cntl, 0); + + if (bd->regulator && bd->regulator_state) { + regulator_disable(bd->regulator); + bd->regulator_state = false; + } + + bd->in_use = false; +} + +static int bcm4752_set_block(void *data, bool blocked) +{ + if (!blocked) { + printk(KERN_INFO "%s : Enable GPS chip\n", __func__); + bcm4752_enable(data); + } else { + printk(KERN_INFO "%s : Disable GPS chip\n", __func__); + bcm4752_disable(data); + } + return 0; +} + +static const struct rfkill_ops bcm4752_rfkill_ops = { + .set_block = bcm4752_set_block, +}; + +static int __devinit bcm4752_probe(struct platform_device *dev) +{ + struct bcm4752_platform_data *pdata; + struct bcm4752_data *bd; + int gpio; + int ret = 0; + + pdata = dev->dev.platform_data; + if (!pdata) { + dev_err(&dev->dev, "No plat data.\n"); + return -EINVAL; + } + + if (!pdata->reg32khz) { + dev_err(&dev->dev, "No 32KHz clock id.\n"); + return -EINVAL; + } + + bd = kzalloc(sizeof(struct bcm4752_data), GFP_KERNEL); + if (!bd) + return -ENOMEM; + + bd->pdata = pdata; + + if (gpio_is_valid(pdata->regpu)) { + gpio = pdata->regpu; + + /* GPS_EN is low */ + gpio_request(gpio, "GPS_EN"); + gpio_direction_output(gpio, 0); + } + + + /* GPS_UART_RXD */ + if (gpio_is_valid(pdata->uart_rxd)) + s3c_gpio_setpull(pdata->uart_rxd, S3C_GPIO_PULL_UP); + + if (gpio_is_valid(pdata->gps_cntl)) { + gpio = pdata->gps_cntl; + gpio_request(gpio, "GPS_CNTL"); + gpio_direction_output(gpio, 0); + } + + /* Register bcm4752 to RFKILL class */ + bd->rfk = rfkill_alloc("bcm4752", &dev->dev, RFKILL_TYPE_GPS, + &bcm4752_rfkill_ops, bd); + if (!bd->rfk) { + ret = -ENOMEM; + goto err_rfk_alloc; + } + + bd->regulator = regulator_get(&dev->dev, pdata->reg32khz); + if (IS_ERR_OR_NULL(bd->regulator)) { + dev_err(&dev->dev, "regulator_get error (%ld)\n", + PTR_ERR(bd->regulator)); + goto err_regulator; + } + + bd->regulator_state = false; + + /* + * described by the comment in rfkill.h + * true : turn off + * false : turn on + */ + rfkill_init_sw_state(bd->rfk, true); + bd->in_use = false; + + ret = rfkill_register(bd->rfk); + if (ret) + goto err_rfkill; + + platform_set_drvdata(dev, bd); + + dev_info(&dev->dev, "ready\n"); + + return 0; + +err_rfkill: + rfkill_destroy(bd->rfk); +err_regulator: +err_rfk_alloc: + kfree(bd); + return ret; +} + +static int __devexit bcm4752_remove(struct platform_device *dev) +{ + struct bcm4752_data *bd = platform_get_drvdata(dev); + struct bcm4752_platform_data *pdata = bd->pdata; + + rfkill_unregister(bd->rfk); + rfkill_destroy(bd->rfk); + gpio_free(pdata->regpu); + kfree(bd); + platform_set_drvdata(dev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int bcm4752_suspend(struct platform_device *dev, pm_message_t stata) +{ + struct bcm4752_data *bd = platform_get_drvdata(dev); + struct bcm4752_platform_data *pdata = bd->pdata; + + if (bd->in_use) { + s5p_gpio_set_pd_cfg(pdata->regpu, S5P_GPIO_PD_OUTPUT1); + if (gpio_is_valid(pdata->gps_cntl)) + s5p_gpio_set_pd_cfg(pdata->gps_cntl, + S5P_GPIO_PD_OUTPUT1); + } else { + s5p_gpio_set_pd_cfg(pdata->regpu, S5P_GPIO_PD_OUTPUT0); + if (gpio_is_valid(pdata->gps_cntl)) + s5p_gpio_set_pd_cfg(pdata->gps_cntl, + S5P_GPIO_PD_OUTPUT0); + } + + return 0; +} + +static int bcm4752_resume(struct platform_device *dev) +{ + return 0; +} +#else +#define bcm4752_suspend NULL +#define bcm4752_resume NULL +#endif + +static struct platform_driver bcm4752_driver = { + .probe = bcm4752_probe, + .remove = __devexit_p(bcm4752_remove), + .suspend = bcm4752_suspend, + .resume = bcm4752_resume, + .driver = { + .name = "bcm4752", + }, +}; + +static int __init bcm4752_init(void) +{ + return platform_driver_register(&bcm4752_driver); +} + +static void __exit bcm4752_exit(void) +{ + platform_driver_unregister(&bcm4752_driver); +} + +module_init(bcm4752_init); +module_exit(bcm4752_exit); + +MODULE_AUTHOR("Minho Ban <mhban@samsung.com>"); +MODULE_DESCRIPTION("BCM4752 GPS module driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-exynos/board-bluetooth-csr8811.c b/arch/arm/mach-exynos/board-bluetooth-csr8811.c index c3f46bb..6df313a 100644 --- a/arch/arm/mach-exynos/board-bluetooth-csr8811.c +++ b/arch/arm/mach-exynos/board-bluetooth-csr8811.c @@ -213,7 +213,7 @@ static int csr_bt_lpm_init(struct platform_device *pdev) bt_lpm.host_wake = 0; bt_is_running = 0; - irq = IRQ_BT_HOST_WAKE; + irq = gpio_to_irq(GPIO_BT_HOST_WAKE); ret = request_irq(irq, host_wake_isr, IRQF_TRIGGER_HIGH, "bt host_wake", NULL); if (ret) { diff --git a/arch/arm/mach-exynos/board-c1-modems.c b/arch/arm/mach-exynos/board-c1-modems.c index 9c33fda..f8cd0ce 100644 --- a/arch/arm/mach-exynos/board-c1-modems.c +++ b/arch/arm/mach-exynos/board-c1-modems.c @@ -24,281 +24,33 @@ #include <linux/clk.h> /* inlcude platform specific file */ +#include <linux/cpufreq_pegasusq.h> #include <linux/platform_data/modem.h> -#include <mach/sec_modem.h> + +#include <plat/gpio-cfg.h> +#include <plat/regs-srom.h> +#include <plat/devs.h> +#include <plat/ehci.h> + +#include <mach/dev.h> #include <mach/gpio.h> #include <mach/gpio-exynos4.h> -#include <plat/gpio-cfg.h> #include <mach/regs-mem.h> -#include <plat/regs-srom.h> +#include <mach/cpufreq.h> +#include <mach/sec_modem.h> +#include <mach/sromc-exynos4.h> #ifdef CONFIG_USBHUB_USB3503 #include <linux/i2c.h> #include <linux/i2c-gpio.h> #include <linux/platform_data/usb3503.h> -#include <mach/cpufreq.h> #include <plat/usb-phy.h> #endif -#include <plat/devs.h> -#include <plat/ehci.h> - -#define SROM_CS0_BASE 0x04000000 -#define SROM_WIDTH 0x01000000 -#define SROM_NUM_ADDR_BITS 14 - -/* For "bus width and wait control (BW)" register */ -enum sromc_attr { - SROMC_DATA_16 = 0x1, /* 16-bit data bus */ - SROMC_BYTE_ADDR = 0x2, /* Byte base address */ - SROMC_WAIT_EN = 0x4, /* Wait enabled */ - SROMC_BYTE_EN = 0x8, /* Byte access enabled */ - SROMC_MASK = 0xF -}; -/* DPRAM configuration */ -struct sromc_cfg { - enum sromc_attr attr; - unsigned size; - unsigned csn; /* CSn # */ - unsigned addr; /* Start address (physical) */ - unsigned end; /* End address (physical) */ -}; +#define C1ATT_REV_0_7 9 /* rev0.7 == system_rev:9 */ -/* DPRAM access timing configuration */ -struct sromc_access_cfg { - u32 tacs; /* Address set-up before CSn */ - u32 tcos; /* Chip selection set-up before OEn */ - u32 tacc; /* Access cycle */ - u32 tcoh; /* Chip selection hold on OEn */ - u32 tcah; /* Address holding time after CSn */ - u32 tacp; /* Page mode access cycle at Page mode */ - u32 pmc; /* Page Mode config */ -}; - -/* For CMC221 IDPRAM (Internal DPRAM) */ -#define CMC_IDPRAM_SIZE 0x4000 /* 16 KB */ - -/* FOR CMC221 SFR for IDPRAM */ -#define CMC_INT2CP_REG 0x10 /* Interrupt to CP */ -#define CMC_INT2AP_REG 0x50 -#define CMC_CLR_INT_REG 0x28 /* Clear Interrupt to AP */ -#define CMC_RESET_REG 0x3C -#define CMC_PUT_REG 0x40 /* AP->CP reg for hostbooting */ -#define CMC_GET_REG 0x50 /* CP->AP reg for hostbooting */ - -#define INT_MASK_REQ_ACK_F 0x0020 -#define INT_MASK_REQ_ACK_R 0x0010 -#define INT_MASK_RES_ACK_F 0x0008 -#define INT_MASK_RES_ACK_R 0x0004 -#define INT_MASK_SEND_F 0x0002 -#define INT_MASK_SEND_R 0x0001 - -/* Function prototypes */ -static void config_dpram_port_gpio(void); -static void init_sromc(void); -static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg); -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg); static int __init init_modem(void); -#ifdef CONFIG_USBHUB_USB3503 -static int host_port_enable(int port, int enable); -#else -static int host_port_enable(int port, int enable) -{ - return s5p_ehci_port_control(&s5p_device_ehci, port, enable); -} -#endif - -static struct sromc_cfg cmc_idpram_cfg = { - .attr = SROMC_DATA_16, - .size = CMC_IDPRAM_SIZE, -}; - -static struct sromc_access_cfg cmc_idpram_access_cfg[] = { - [DPRAM_SPEED_LOW] = { - /* for 33 MHz clock, 64 cycles */ - .tacs = 0x08 << 28, - .tcos = 0x08 << 24, - .tacc = 0x1F << 16, - .tcoh = 0x08 << 12, - .tcah = 0x08 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, - [DPRAM_SPEED_MID] = { - /* for 66 MHz clock, 32 cycles */ - .tacs = 0x01 << 28, - .tcos = 0x01 << 24, - .tacc = 0x1B << 16, - .tcoh = 0x01 << 12, - .tcah = 0x01 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, - [DPRAM_SPEED_HIGH] = { - /* for 133 MHz clock, 16 cycles */ - .tacs = 0x01 << 28, - .tcos = 0x01 << 24, - .tacc = 0x0B << 16, - .tcoh = 0x01 << 12, - .tcah = 0x01 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, -}; - -/* - magic_code + - access_enable + - fmt_tx_head + fmt_tx_tail + fmt_tx_buff + - raw_tx_head + raw_tx_tail + raw_tx_buff + - fmt_rx_head + fmt_rx_tail + fmt_rx_buff + - raw_rx_head + raw_rx_tail + raw_rx_buff + - mbx_cp2ap + - mbx_ap2cp - = 2 + - 2 + - 2 + 2 + 1336 + - 2 + 2 + 4564 + - 2 + 2 + 1336 + - 2 + 2 + 9124 + - 2 + - 2 - = 16384 -*/ - -#define DP_FMT_TX_BUFF_SZ 1336 -#define DP_RAW_TX_BUFF_SZ 4564 -#define DP_FMT_RX_BUFF_SZ 1336 -#define DP_RAW_RX_BUFF_SZ 9124 - -#define MAX_CMC_IDPRAM_IPC_DEV (IPC_RAW + 1) /* FMT, RAW */ - -struct dpram_ipc_cfg { - u16 magic; - u16 access; - - u16 fmt_tx_head; - u16 fmt_tx_tail; - u8 fmt_tx_buff[DP_FMT_TX_BUFF_SZ]; - - u16 raw_tx_head; - u16 raw_tx_tail; - u8 raw_tx_buff[DP_RAW_TX_BUFF_SZ]; - - u16 fmt_rx_head; - u16 fmt_rx_tail; - u8 fmt_rx_buff[DP_FMT_RX_BUFF_SZ]; - - u16 raw_rx_head; - u16 raw_rx_tail; - u8 raw_rx_buff[DP_RAW_RX_BUFF_SZ]; - - u16 mbx_cp2ap; - u16 mbx_ap2cp; -}; - -struct cmc221_idpram_sfr { - u16 __iomem *int2cp; - u16 __iomem *int2ap; - u16 __iomem *clr_int2ap; - u16 __iomem *reset; - u16 __iomem *msg2cp; - u16 __iomem *msg2ap; -}; - -static struct dpram_ipc_map cmc_ipc_map; -static u8 *cmc_sfr_base; -static struct cmc221_idpram_sfr cmc_sfr; - -/* Function prototypes */ -static void cmc_idpram_reset(void); -static void cmc_idpram_setup_speed(enum dpram_speed); -static int cmc_idpram_wakeup(void); -static void cmc_idpram_sleep(void); -static void cmc_idpram_clr_intr(void); -static u16 cmc_idpram_recv_intr(void); -static void cmc_idpram_send_intr(u16 irq_mask); -static u16 cmc_idpram_recv_msg(void); -static void cmc_idpram_send_msg(u16 msg); - -static u16 cmc_idpram_get_magic(void); -static void cmc_idpram_set_magic(u16 value); -static u16 cmc_idpram_get_access(void); -static void cmc_idpram_set_access(u16 value); - -static u32 cmc_idpram_get_tx_head(int dev_id); -static u32 cmc_idpram_get_tx_tail(int dev_id); -static void cmc_idpram_set_tx_head(int dev_id, u32 head); -static void cmc_idpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id); -static u32 cmc_idpram_get_tx_buff_size(int dev_id); - -static u32 cmc_idpram_get_rx_head(int dev_id); -static u32 cmc_idpram_get_rx_tail(int dev_id); -static void cmc_idpram_set_rx_head(int dev_id, u32 head); -static void cmc_idpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id); -static u32 cmc_idpram_get_rx_buff_size(int dev_id); - -static u16 cmc_idpram_get_mask_req_ack(int dev_id); -static u16 cmc_idpram_get_mask_res_ack(int dev_id); -static u16 cmc_idpram_get_mask_send(int dev_id); - -static struct modemlink_dpram_control cmc_idpram_ctrl = { - .reset = cmc_idpram_reset, - - .setup_speed = cmc_idpram_setup_speed, - - .wakeup = cmc_idpram_wakeup, - .sleep = cmc_idpram_sleep, - - .clear_intr = cmc_idpram_clr_intr, - .recv_intr = cmc_idpram_recv_intr, - .send_intr = cmc_idpram_send_intr, - .recv_msg = cmc_idpram_recv_msg, - .send_msg = cmc_idpram_send_msg, - - .get_magic = cmc_idpram_get_magic, - .set_magic = cmc_idpram_set_magic, - .get_access = cmc_idpram_get_access, - .set_access = cmc_idpram_set_access, - - .get_tx_head = cmc_idpram_get_tx_head, - .get_tx_tail = cmc_idpram_get_tx_tail, - .set_tx_head = cmc_idpram_set_tx_head, - .set_tx_tail = cmc_idpram_set_tx_tail, - .get_tx_buff = cmc_idpram_get_tx_buff, - .get_tx_buff_size = cmc_idpram_get_tx_buff_size, - - .get_rx_head = cmc_idpram_get_rx_head, - .get_rx_tail = cmc_idpram_get_rx_tail, - .set_rx_head = cmc_idpram_set_rx_head, - .set_rx_tail = cmc_idpram_set_rx_tail, - .get_rx_buff = cmc_idpram_get_rx_buff, - .get_rx_buff_size = cmc_idpram_get_rx_buff_size, - - .get_mask_req_ack = cmc_idpram_get_mask_req_ack, - .get_mask_res_ack = cmc_idpram_get_mask_res_ack, - .get_mask_send = cmc_idpram_get_mask_send, - - .dp_base = NULL, - .dp_size = 0, - .dp_type = CP_IDPRAM, - .aligned = 1, - - .dpram_irq = CMC_IDPRAM_INT_IRQ_00, - .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING), - .dpram_irq_name = "CMC221_IDPRAM_IRQ", - .dpram_wlock_name = "CMC221_IDPRAM_WLOCK", - - .max_ipc_dev = MAX_CMC_IDPRAM_IPC_DEV, -}; - -/* -** UMTS target platform data -*/ static struct modem_io_t umts_io_devices[] = { [0] = { .name = "umts_boot0", @@ -322,7 +74,7 @@ static struct modem_io_t umts_io_devices[] = { .links = LINKTYPE(LINKDEV_DPRAM), }, [3] = { - .name = "umts_multipdp", + .name = "multipdp", .id = 0, .format = IPC_MULTI_RAW, .io_type = IODEV_DUMMY, @@ -383,14 +135,15 @@ static struct modem_io_t umts_io_devices[] = { .links = LINKTYPE(LINKDEV_DPRAM), }, [11] = { - .name = "umts_loopback_ap2cp", + .name = "umts_loopback_cp2ap", .id = 30, .format = IPC_RAW, .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), + .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), + .tx_link = LINKDEV_DPRAM, }, [12] = { - .name = "umts_loopback_cp2ap", + .name = "umts_loopback_ap2cp", .id = 31, .format = IPC_RAW, .io_type = IODEV_MISC, @@ -404,6 +157,13 @@ static struct modem_io_t umts_io_devices[] = { .links = LINKTYPE(LINKDEV_DPRAM), }, [14] = { + .name = "umts_log", + .id = 0, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [15] = { .name = "lte_ipc0", .id = 235, .format = IPC_FMT, @@ -412,28 +172,134 @@ static struct modem_io_t umts_io_devices[] = { }, }; -static int exynos_cpu_frequency_lock(void); -static int exynos_cpu_frequency_unlock(void); +/* +** addr_bits: 14 bits = 13 bits (8K words) + 1 bit (SFR) +** data_bits: 16 bits +** byte_acc: N/A +*/ +static struct sromc_bus_cfg c1_sromc_bus_cfg = { + .addr_bits = 14, + .data_bits = 16, + .byte_acc = 0, +}; -static struct modemlink_pm_data umts_link_pm_data = { - .name = "umts_link_pm", +/* For CMC221 IDPRAM (Internal DPRAM) */ +#define CMC_IDPRAM_SIZE DPRAM_SIZE_16KB - .gpio_link_enable = 0, - .gpio_link_active = GPIO_ACTIVE_STATE, - .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, - .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, +/* For CMC221 SFR for IDPRAM */ +#define CMC_INT2CP_REG 0x10 /* Interrupt to CP */ +#define CMC_INT2AP_REG 0x50 +#define CMC_CLR_INT_REG 0x28 /* Clear Interrupt to AP */ +#define CMC_RESET_REG 0x3C +#define CMC_PUT_REG 0x40 /* AP->CP reg for hostbooting */ +#define CMC_GET_REG 0x50 /* CP->AP reg for hostbooting */ + +struct cmc22x_idpram_sfr { + u16 __iomem *int2cp; + u16 __iomem *int2ap; + u16 __iomem *clr_int2ap; + u16 __iomem *reset; + u16 __iomem *msg2cp; + u16 __iomem *msg2ap; +}; - .port_enable = host_port_enable, /* - .link_reconnect = umts_link_reconnect, +** Function prototypes for CMC221 */ - .freqlock = ATOMIC_INIT(0), - .cpufreq_lock = exynos_cpu_frequency_lock, - .cpufreq_unlock = exynos_cpu_frequency_unlock, +static void cmc_idpram_reset(void); +static void cmc_idpram_clr_intr(void); +static u16 cmc_idpram_recv_intr(void); +static void cmc_idpram_send_intr(u16 irq_mask); +static u16 cmc_idpram_recv_msg(void); +static void cmc_idpram_send_msg(u16 msg); - .autosuspend_delay_ms = 2000, +static int cmc_idpram_wakeup(void); +static void cmc_idpram_sleep(void); + +static void cmc_idpram_setup_speed(enum dpram_speed speed); + +/* +** Static variables +*/ +static struct sromc_bank_cfg cmc_idpram_bank_cfg = { + .csn = 0, + .attr = SROMC_DATA_16, + .size = CMC_IDPRAM_SIZE, + .addr = SROM_CS0_BASE, +}; + +static struct sromc_timing_cfg cmc_idpram_timing_cfg[] = { + [DPRAM_SPEED_LOW] = { + /* CP 33 MHz clk, 315 ns (63 cycles) with 200 MHz INT clk */ + .tacs = 0x0F << 28, + .tcos = 0x0F << 24, + .tacc = 0x1F << 16, + .tcoh = 0x01 << 12, + .tcah = 0x00 << 8, + .tacp = 0x00 << 4, + .pmc = 0x00 << 0, + }, + [DPRAM_SPEED_MID] = { + /* CP 66 MHz clk, 160 ns (32 cycles) with 200 MHz INT clk */ + .tacs = 0x01 << 28, + .tcos = 0x01 << 24, + .tacc = 0x1C << 16, + .tcoh = 0x01 << 12, + .tcah = 0x00 << 8, + .tacp = 0x00 << 4, + .pmc = 0x00 << 0, + }, + [DPRAM_SPEED_HIGH] = { + /* CP 133 MHz clk, 80 ns (16 cycles) with 200 MHz INT clk */ + .tacs = 0x01 << 28, + .tcos = 0x01 << 24, + .tacc = 0x0C << 16, + .tcoh = 0x01 << 12, + .tcah = 0x00 << 8, + .tacp = 0x00 << 4, + .pmc = 0x00 << 0, + }, +}; - .has_usbhub = true, +static struct modemlink_dpram_control cmc_idpram_ctrl = { + .reset = cmc_idpram_reset, + .clear_intr = cmc_idpram_clr_intr, + .recv_intr = cmc_idpram_recv_intr, + .send_intr = cmc_idpram_send_intr, + .recv_msg = cmc_idpram_recv_msg, + .send_msg = cmc_idpram_send_msg, + + .wakeup = cmc_idpram_wakeup, + .sleep = cmc_idpram_sleep, + + .setup_speed = cmc_idpram_setup_speed, + + .dp_type = CP_IDPRAM, + + .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING), +}; + +static struct cmc22x_idpram_sfr cmc_idpram_sfr; + +static struct resource umts_modem_res[] = { + [RES_CP_ACTIVE_IRQ_ID] = { + .name = "cp_active_irq", + .start = LTE_ACTIVE_IRQ, + .end = LTE_ACTIVE_IRQ, + .flags = IORESOURCE_IRQ, + }, + [RES_DPRAM_MEM_ID] = { + .name = "dpram_base", + .start = SROM_CS0_BASE, + .end = SROM_CS0_BASE + (CMC_IDPRAM_SIZE - 1), + .flags = IORESOURCE_MEM, + }, + [RES_DPRAM_IRQ_ID] = { + .name = "dpram_irq", + .start = CMC_IDPRAM_INT_IRQ_00, + .end = CMC_IDPRAM_INT_IRQ_00, + .flags = IORESOURCE_IRQ, + }, }; static struct modem_data umts_modem_data = { @@ -442,6 +308,9 @@ static struct modem_data umts_modem_data = { .gpio_cp_on = CP_CMC221_PMIC_PWRON, .gpio_cp_reset = CP_CMC221_CPU_RST, .gpio_phone_active = GPIO_LTE_ACTIVE, +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) + .gpio_pda_active = GPIO_PDA_ACTIVE, +#endif .gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00, .gpio_dpram_status = GPIO_CMC_IDPRAM_STATUS, @@ -461,21 +330,12 @@ static struct modem_data umts_modem_data = { .num_iodevs = ARRAY_SIZE(umts_io_devices), .iodevs = umts_io_devices, - .link_pm_data = &umts_link_pm_data, + .use_handover = false, .ipc_version = SIPC_VER_50, .use_mif_log = true, }; -static struct resource umts_modem_res[] = { - [0] = { - .name = "cp_active_irq", - .start = LTE_ACTIVE_IRQ, - .end = LTE_ACTIVE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - static struct platform_device umts_modem = { .name = "mif_sipc5", .id = 1, @@ -486,33 +346,38 @@ static struct platform_device umts_modem = { }, }; -#define HUB_STATE_OFF 0 -void set_hsic_lpa_states(int states) +/* +** Function definitions +*/ +static void cmc_idpram_reset(void) { - int val = gpio_get_value(umts_modem_data.gpio_cp_reset); + iowrite16(1, cmc_idpram_sfr.reset); +} - mif_trace("\n"); +static void cmc_idpram_clr_intr(void) +{ + iowrite16(0xFFFF, cmc_idpram_sfr.clr_int2ap); + iowrite16(0, cmc_idpram_sfr.int2ap); +} - if (val && states == STATE_HSIC_LPA_ENTER) { - mif_info("usb3503: hub off - lpa\n"); - host_port_enable(2, 0); - *(umts_link_pm_data.p_hub_status) = HUB_STATE_OFF; - } +static u16 cmc_idpram_recv_intr(void) +{ + return ioread16(cmc_idpram_sfr.int2ap); } -int get_cp_active_state(void) +static void cmc_idpram_send_intr(u16 irq_mask) { - return gpio_get_value(umts_modem_data.gpio_phone_active); + iowrite16(irq_mask, cmc_idpram_sfr.int2cp); } -static void cmc_idpram_reset(void) +static u16 cmc_idpram_recv_msg(void) { - iowrite16(1, cmc_sfr.reset); + return ioread16(cmc_idpram_sfr.msg2ap); } -static void cmc_idpram_setup_speed(enum dpram_speed speed) +static void cmc_idpram_send_msg(u16 msg) { - setup_dpram_speed(cmc_idpram_cfg.csn, &cmc_idpram_access_cfg[speed]); + iowrite16(msg, cmc_idpram_sfr.msg2cp); } static int cmc_idpram_wakeup(void) @@ -523,14 +388,18 @@ static int cmc_idpram_wakeup(void) while (!gpio_get_value(umts_modem_data.gpio_dpram_status)) { if (cnt++ > 10) { - mif_err("ERR: gpio_dpram_status == 0\n"); - return -EAGAIN; + if (in_irq()) + mif_err("ERR! gpio_dpram_status == 0 in IRQ\n"); + else + mif_err("ERR! gpio_dpram_status == 0\n"); + return -EACCES; } + mif_info("gpio_dpram_status == 0 (cnt %d)\n", cnt); if (in_interrupt()) - mdelay(1); + udelay(1000); else - msleep_interruptible(1); + usleep_range(1000, 2000); } return 0; @@ -541,196 +410,33 @@ static void cmc_idpram_sleep(void) gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 0); } -static void cmc_idpram_clr_intr(void) -{ - iowrite16(0xFFFF, cmc_sfr.clr_int2ap); - iowrite16(0, cmc_sfr.int2ap); -} - -static u16 cmc_idpram_recv_intr(void) -{ - return ioread16(cmc_sfr.int2ap); -} - -static void cmc_idpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, cmc_sfr.int2cp); -} - -static u16 cmc_idpram_recv_msg(void) -{ - return ioread16(cmc_sfr.msg2ap); -} - -static void cmc_idpram_send_msg(u16 msg) -{ - iowrite16(msg, cmc_sfr.msg2cp); -} - -static u16 cmc_idpram_get_magic(void) -{ - return ioread16(cmc_ipc_map.magic); -} - -static void cmc_idpram_set_magic(u16 value) -{ - iowrite16(value, cmc_ipc_map.magic); -} - -static u16 cmc_idpram_get_access(void) -{ - return ioread16(cmc_ipc_map.access); -} - -static void cmc_idpram_set_access(u16 value) -{ - iowrite16(value, cmc_ipc_map.access); -} - -static u32 cmc_idpram_get_tx_head(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].txq.head); -} - -static u32 cmc_idpram_get_tx_tail(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].txq.tail); -} - -static void cmc_idpram_set_tx_head(int dev_id, u32 head) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head); - - do { - /* Check head value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].txq.head); - if (val == head) - break; - - mif_err("ERR: txq.head(%d) != head(%d)\n", val, head); - - /* Write head value again */ - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head); - } while (cnt--); -} - -static void cmc_idpram_set_tx_tail(int dev_id, u32 tail) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail); - - do { - /* Check tail value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].txq.tail); - if (val == tail) - break; - - mif_err("ERR: txq.tail(%d) != tail(%d)\n", val, tail); - - /* Write tail value again */ - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail); - } while (cnt--); -} - -static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].txq.buff; -} - -static u32 cmc_idpram_get_tx_buff_size(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].txq.size; -} - -static u32 cmc_idpram_get_rx_head(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].rxq.head); -} - -static u32 cmc_idpram_get_rx_tail(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].rxq.tail); -} - -static void cmc_idpram_set_rx_head(int dev_id, u32 head) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head); - - do { - /* Check head value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].rxq.head); - if (val == head) - break; - - mif_err("ERR: rxq.head(%d) != head(%d)\n", val, head); - - /* Write head value again */ - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head); - } while (cnt--); -} - -static void cmc_idpram_set_rx_tail(int dev_id, u32 tail) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail); - - do { - /* Check tail value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].rxq.tail); - if (val == tail) - break; - - mif_err("ERR: rxq.tail(%d) != tail(%d)\n", val, tail); - - /* Write tail value again */ - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail); - } while (cnt--); -} - -static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].rxq.buff; -} - -static u32 cmc_idpram_get_rx_buff_size(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].rxq.size; -} - -static u16 cmc_idpram_get_mask_req_ack(int dev_id) +static void cmc_idpram_setup_speed(enum dpram_speed speed) { - return cmc_ipc_map.dev[dev_id].mask_req_ack; + sromc_config_access_timing(cmc_idpram_bank_cfg.csn, + &cmc_idpram_timing_cfg[speed]); } -static u16 cmc_idpram_get_mask_res_ack(int dev_id) +static u8 *cmc_idpram_remap_sfr_region(struct sromc_bank_cfg *cfg) { - return cmc_ipc_map.dev[dev_id].mask_res_ack; -} + int dp_addr = cfg->addr + cfg->size; + int dp_size = cfg->size; + u8 __iomem *sfr_base; -static u16 cmc_idpram_get_mask_send(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].mask_send; -} + /* Remap DPRAM SFR region */ + sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); + if (!sfr_base) { + mif_err("ERR: ioremap_nocache fail\n"); + return NULL; + } -/* Set dynamic environment for a modem */ -static void setup_umts_modem_env(void) -{ - /* Config DPRAM control structure */ - cmc_idpram_cfg.csn = 0; - cmc_idpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cmc_idpram_cfg.csn); - cmc_idpram_cfg.end = cmc_idpram_cfg.addr + cmc_idpram_cfg.size - 1; + cmc_idpram_sfr.int2cp = (u16 __iomem *)(sfr_base + CMC_INT2CP_REG); + cmc_idpram_sfr.int2ap = (u16 __iomem *)(sfr_base + CMC_INT2AP_REG); + cmc_idpram_sfr.clr_int2ap = (u16 __iomem *)(sfr_base + CMC_CLR_INT_REG); + cmc_idpram_sfr.reset = (u16 __iomem *)(sfr_base + CMC_RESET_REG); + cmc_idpram_sfr.msg2cp = (u16 __iomem *)(sfr_base + CMC_PUT_REG); + cmc_idpram_sfr.msg2ap = (u16 __iomem *)(sfr_base + CMC_GET_REG); - umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00; + return sfr_base; } static void config_umts_modem_gpio(void) @@ -869,290 +575,192 @@ static void config_umts_modem_gpio(void) } else { gpio_direction_input(gpio_dynamic_switching); s3c_gpio_setpull(gpio_dynamic_switching, - S3C_GPIO_PULL_NONE); + S3C_GPIO_PULL_DOWN); } } -} -static u8 *cmc_idpram_remap_mem_region(struct sromc_cfg *cfg) -{ - int dp_addr = cfg->addr; - int dp_size = cfg->size; - u8 __iomem *dp_base; - struct dpram_ipc_cfg *ipc_map; - struct dpram_ipc_device *dev; - - /* Remap DPRAM memory region */ - dp_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); - if (!dp_base) { - mif_err("ERR: ioremap_nocache for dp_base fail\n"); - return NULL; - } - mif_err("DPRAM VA=0x%08X\n", (int)dp_base); - - /* Remap DPRAM SFR region */ - dp_addr += dp_size; - cmc_sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); - if (cmc_sfr_base == NULL) { - iounmap(dp_base); - mif_err("ERR: ioremap_nocache for cmc_sfr_base fail\n"); - return NULL; - } - - cmc_sfr.int2cp = (u16 __iomem *)(cmc_sfr_base + CMC_INT2CP_REG); - cmc_sfr.int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_INT2AP_REG); - cmc_sfr.clr_int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_CLR_INT_REG); - cmc_sfr.reset = (u16 __iomem *)(cmc_sfr_base + CMC_RESET_REG); - cmc_sfr.msg2cp = (u16 __iomem *)(cmc_sfr_base + CMC_PUT_REG); - cmc_sfr.msg2ap = (u16 __iomem *)(cmc_sfr_base + CMC_GET_REG); + mif_info("done\n"); +} - cmc_idpram_ctrl.dp_base = (u8 __iomem *)dp_base; - cmc_idpram_ctrl.dp_size = dp_size; +static int host_port_enable(int port, int enable); +static int exynos_frequency_lock(struct device *dev); +static int exynos_frequency_unlock(struct device *dev); - /* Map for IPC */ - ipc_map = (struct dpram_ipc_cfg *)dp_base; +static struct modemlink_pm_data umts_link_pm_data = { + .name = "umts_link_pm", - /* Magic code and access enable fields */ - cmc_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; - cmc_ipc_map.access = (u16 __iomem *)&ipc_map->access; + .gpio_link_enable = 0, + .gpio_link_active = GPIO_ACTIVE_STATE, + .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, + .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, - /* FMT */ - dev = &cmc_ipc_map.dev[IPC_FMT]; + .port_enable = host_port_enable, +/* + .link_reconnect = umts_link_reconnect, +*/ + .freqlock = ATOMIC_INIT(0), + .freq_lock = exynos_frequency_lock, + .freq_unlock = exynos_frequency_unlock, - strcpy(dev->name, "FMT"); - dev->id = IPC_FMT; + .autosuspend_delay_ms = 2000, - dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; - dev->txq.size = DP_FMT_TX_BUFF_SZ; + .has_usbhub = true, /* change this in init_modem if C1-ATT >= rev0.7 */ +}; - dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; - dev->rxq.size = DP_FMT_RX_BUFF_SZ; +static struct modemlink_pm_link_activectl active_ctl; - dev->mask_req_ack = INT_MASK_REQ_ACK_F; - dev->mask_res_ack = INT_MASK_RES_ACK_F; - dev->mask_send = INT_MASK_SEND_F; +#ifdef CONFIG_EXYNOS4_CPUFREQ +static int exynos_frequency_lock(struct device *dev) +{ + unsigned int level, cpufreq = 600; /* 200 ~ 1400 */ + unsigned int busfreq = 400200; /* 100100 ~ 400200 */ + int ret = 0; + struct device *busdev = dev_get("exynos-busfreq"); - /* RAW */ - dev = &cmc_ipc_map.dev[IPC_RAW]; + if (atomic_read(&umts_link_pm_data.freqlock) == 0) { + /* cpu frequency lock */ + ret = exynos_cpufreq_get_level(cpufreq * 1000, &level); + if (ret < 0) { + mif_err("ERR: exynos_cpufreq_get_level fail: %d\n", + ret); + goto exit; + } - strcpy(dev->name, "RAW"); - dev->id = IPC_RAW; + ret = exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level); + if (ret < 0) { + mif_err("ERR: exynos_cpufreq_lock fail: %d\n", ret); + goto exit; + } - dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; - dev->txq.size = DP_RAW_TX_BUFF_SZ; + /* bus frequncy lock */ + if (!busdev) { + mif_err("ERR: busdev is not exist\n"); + ret = -ENODEV; + goto exit; + } - dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; - dev->rxq.size = DP_RAW_RX_BUFF_SZ; + ret = dev_lock(busdev, dev, busfreq); + if (ret < 0) { + mif_err("ERR: dev_lock error: %d\n", ret); + goto exit; + } - dev->mask_req_ack = INT_MASK_REQ_ACK_R; - dev->mask_res_ack = INT_MASK_RES_ACK_R; - dev->mask_send = INT_MASK_SEND_R; + /* lock minimum number of cpu cores */ + cpufreq_pegasusq_min_cpu_lock(2); - return dp_base; + atomic_set(&umts_link_pm_data.freqlock, 1); + mif_debug("level=%d, cpufreq=%d MHz, busfreq=%06d\n", + level, cpufreq, busfreq); + } +exit: + return ret; } -/** - * DPRAM GPIO settings - * - * SROM_NUM_ADDR_BITS value indicate the address line number or - * the mux/demux dpram type. if you want to set mux mode, define the - * SROM_NUM_ADDR_BITS to zero. - * - * for CMC22x - * CMC22x has 16KB + a SFR register address. - * It used 14 bits (13bits for 16KB word address and 1 bit for SFR - * register) - */ -static void config_dpram_port_gpio(void) +static int exynos_frequency_unlock(struct device *dev) { - int addr_bits = SROM_NUM_ADDR_BITS; + int ret = 0; + struct device *busdev = dev_get("exynos-busfreq"); - mif_info("address line = %d bits\n", addr_bits); - - /* - ** Config DPRAM address/data GPIO pins - */ + if (atomic_read(&umts_link_pm_data.freqlock) == 1) { + /* cpu frequency unlock */ + exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF); - /* Set GPIO for address bus (13 ~ 14 bits) */ - switch (addr_bits) { - case 0: - break; + /* bus frequency unlock */ + ret = dev_unlock(busdev, dev); + if (ret < 0) { + mif_err("ERR: dev_unlock error: %d\n", ret); + goto exit; + } - case 13 ... 14: - s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_LOW, - EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_HIGH, - (addr_bits - EXYNOS4_GPIO_Y3_NR), S3C_GPIO_SFN(2)); - break; + /* unlock minimum number of cpu cores */ + cpufreq_pegasusq_min_cpu_unlock(); - default: - mif_err("ERR: invalid addr_bits!!!\n"); - return; + atomic_set(&umts_link_pm_data.freqlock, 0); + mif_debug("success\n"); } - - /* Set GPIO for data bus (16 bits) */ - s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_LOW, 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_HIGH, 8, S3C_GPIO_SFN(2)); - - /* Setup SROMC CSn pins */ - s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2)); - - /* Config OEn, WEn */ - s3c_gpio_cfgpin(GPIO_DPRAM_REN, S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(GPIO_DPRAM_WEN, S3C_GPIO_SFN(2)); +exit: + return ret; } - -static void init_sromc(void) +#else +static int exynos_frequency_lock(void) { - struct clk *clk = NULL; - - /* SROMC clk enable */ - clk = clk_get(NULL, "sromc"); - if (!clk) { - mif_err("ERR: SROMC clock gate fail\n"); - return; - } - clk_enable(clk); + return 0; } -static void setup_sromc -( - unsigned csn, - struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg -) +static int exynos_frequency_unlock(void) { - unsigned bw = 0; /* Bus width and wait control */ - unsigned bc = 0; /* Vank control */ - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - - mif_err("SROMC settings for CS%d...\n", csn); - - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - mif_err("Old SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc); - - /* Set the BW control field for the CSn */ - bw &= ~(SROMC_MASK << (csn << 2)); - bw |= (cfg->attr << (csn << 2)); - writel(bw, S5P_SROM_BW); - - /* Set SROMC memory access timing for the CSn */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - - writel(bc, bank_sfr); - - /* Verify SROMC settings */ - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - mif_err("New SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc); + return 0; } +#endif -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg) +bool modem_using_hub(void) { - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - unsigned bc = 0; - - bc = __raw_readl(bank_sfr); - mif_info("Old CS%d setting = 0x%08X\n", csn, bc); - - /* SROMC memory access timing setting */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - writel(bc, bank_sfr); - - bc = __raw_readl(bank_sfr); - mif_info("New CS%d setting = 0x%08X\n", csn, bc); + return umts_link_pm_data.has_usbhub; } -static int __init init_modem(void) +void set_slave_wake(void) { - struct sromc_cfg *cfg = NULL; - struct sromc_access_cfg *acc_cfg = NULL; - - mif_err("System Revision = %d\n", system_rev); - - setup_umts_modem_env(); - - config_dpram_port_gpio(); + int slavewake = umts_link_pm_data.gpio_link_slavewake; - config_umts_modem_gpio(); - - init_sromc(); - - cfg = &cmc_idpram_cfg; - acc_cfg = &cmc_idpram_access_cfg[DPRAM_SPEED_LOW]; - - setup_sromc(cfg->csn, cfg, acc_cfg); - - if (!cmc_idpram_remap_mem_region(&cmc_idpram_cfg)) - return -1; - - platform_device_register(&umts_modem); - - return 0; + if (gpio_get_value(slavewake)) { + gpio_direction_output(slavewake, 0); + mif_info("> S-WUP 0\n"); + mdelay(10); + } + gpio_direction_output(slavewake, 1); + mif_info("> S-WUP 1\n"); } -late_initcall(init_modem); -/*device_initcall(init_modem);*/ - -#ifdef CONFIG_USBHUB_USB3503 -static int (*usbhub_set_mode)(struct usb3503_hubctl *, int); -static struct usb3503_hubctl *usbhub_ctl; -#ifdef CONFIG_EXYNOS4_CPUFREQ -static int exynos_cpu_frequency_lock(void) +void set_hsic_lpa_states(int states) { - unsigned int level, freq = 700; + int val = gpio_get_value(umts_modem_data.gpio_cp_reset); + struct modemlink_pm_data *pm_data = &umts_link_pm_data; - if (atomic_read(&umts_link_pm_data.freqlock) == 0) { - if (exynos_cpufreq_get_level(freq * 1000, &level)) { - mif_err("ERR: exynos_cpufreq_get_level fail\n"); - return -EINVAL; - } + mif_trace("\n"); - if (exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level)) { - mif_err("ERR: exynos_cpufreq_lock fail\n"); - return -EINVAL; + if (val) { + switch (states) { + case STATE_HSIC_LPA_ENTER: + mif_info("lpa_enter\n"); + /* gpio_link_active == gpio_host_active in C1 */ + gpio_set_value(umts_modem_data.gpio_host_active, 0); + mif_info("> H-ACT %d\n", 0); + if (pm_data->hub_standby && pm_data->hub_pm_data) + pm_data->hub_standby(pm_data->hub_pm_data); + break; + case STATE_HSIC_LPA_WAKE: + mif_info("lpa_wake\n"); + gpio_set_value(umts_modem_data.gpio_host_active, 1); + mif_info("> H-ACT %d\n", 1); + break; + case STATE_HSIC_LPA_PHY_INIT: + mif_info("lpa_phy_init\n"); + if (!modem_using_hub() && active_ctl.gpio_initialized) + set_slave_wake(); + break; } - - atomic_set(&umts_link_pm_data.freqlock, 1); - mif_debug("<%d> %d MHz\n", level, freq); } - return 0; } -static int exynos_cpu_frequency_unlock(void) -{ - if (atomic_read(&umts_link_pm_data.freqlock) == 1) { - exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF); - atomic_set(&umts_link_pm_data.freqlock, 0); - mif_debug("\n"); - } - return 0; -} -#else -static int exynos_cpu_frequency_lock(void) +int get_cp_active_state(void) { - return 0; + return gpio_get_value(umts_modem_data.gpio_phone_active); } -static int exynos_cpu_frequency_unlock(void) -{ - return 0; -} -#endif +static int (*usbhub_set_mode)(struct usb3503_hubctl *, int); +static struct usb3503_hubctl *usbhub_ctl; void set_host_states(struct platform_device *pdev, int type) { + if (modem_using_hub()) + return; + + if (active_ctl.gpio_initialized) { + mif_err("%s: > H-ACT %d\n", pdev->name, type); + gpio_direction_output(umts_link_pm_data.gpio_link_active, type); + } else { + active_ctl.gpio_request_host_active = 1; + } } static int usb3503_hub_handler(void (*set_mode)(void), void *ctl) @@ -1239,18 +847,6 @@ static struct platform_device s3c_device_i2c20 = { .dev.platform_data = &i2c20_platdata, }; -static int __init init_usbhub(void) -{ - usb3503_hw_config(); - i2c_register_board_info(20, i2c_devs20_emul, - ARRAY_SIZE(i2c_devs20_emul)); - - platform_device_register(&s3c_device_i2c20); - return 0; -} - -device_initcall(init_usbhub); - static int host_port_enable(int port, int enable) { int err; @@ -1258,10 +854,12 @@ static int host_port_enable(int port, int enable) mif_info("port(%d) control(%d)\n", port, enable); if (enable) { - err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB); - if (err < 0) { - mif_err("ERR: hub on fail\n"); - goto exit; + if (modem_using_hub()) { + err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB); + if (err < 0) { + mif_err("ERR: hub on fail\n"); + goto exit; + } } err = s5p_ehci_port_control(&s5p_device_ehci, port, 1); if (err < 0) { @@ -1269,16 +867,18 @@ static int host_port_enable(int port, int enable) goto exit; } } else { + if (modem_using_hub()) { + err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY); + if (err < 0) { + mif_err("ERR: hub off fail\n"); + goto exit; + } + } err = s5p_ehci_port_control(&s5p_device_ehci, port, 0); if (err < 0) { mif_err("ERR: port(%d) enable fail\n", port); goto exit; } - err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY); - if (err < 0) { - mif_err("ERR: hub off fail\n"); - goto exit; - } } err = gpio_direction_output(umts_modem_data.gpio_host_active, enable); @@ -1288,15 +888,78 @@ static int host_port_enable(int port, int enable) exit: return err; } -#else -void set_host_states(struct platform_device *pdev, int type) + +static int __init init_usbhub(void) { - if (active_ctl.gpio_initialized) { - mif_err("<%s> Active States =%d, %s\n", pdev->name, type); - gpio_direction_output(umts_link_pm_data.gpio_link_active, type); - } else { - active_ctl.gpio_request_host_active = 1; - } + usb3503_hw_config(); + i2c_register_board_info(20, i2c_devs20_emul, + ARRAY_SIZE(i2c_devs20_emul)); + + platform_device_register(&s3c_device_i2c20); + return 0; } +device_initcall(init_usbhub); + +static int __init init_modem(void) +{ + struct sromc_bus_cfg *bus_cfg; + struct sromc_bank_cfg *bnk_cfg; + struct sromc_timing_cfg *tm_cfg; + + mif_err("System Revision = %d\n", system_rev); + +#ifdef CONFIG_MACH_C1_USA_ATT + /* check C1-ATT rev >=0.7 + * <=rev0.6: <EXYNOS>--hsic--<HUB>--usb--<CMC221S> + * >=rev0.7: <EXYNOS>--hsic--------------<CMC221D> + */ + if (system_rev >= C1ATT_REV_0_7) + umts_link_pm_data.has_usbhub = false; #endif +#ifdef CONFIG_MACH_BAFFIN + umts_link_pm_data.has_usbhub = false; +#endif + /* + ** Complete modem_data configuration including link_pm_data + */ + umts_modem_data.link_pm_data = &umts_link_pm_data, + + /* + ** Configure GPIO pins for the modem + */ + config_umts_modem_gpio(); + active_ctl.gpio_initialized = 1; + + /* + ** Configure SROM controller + */ + if (sromc_enable() < 0) + return -1; + + bus_cfg = &c1_sromc_bus_cfg; + if (sromc_config_demux_gpio(bus_cfg) < 0) + return -1; + + bnk_cfg = &cmc_idpram_bank_cfg; + if (sromc_config_csn_gpio(bnk_cfg->csn) < 0) + return -1; + sromc_config_access_attr(bnk_cfg->csn, bnk_cfg->attr); + + tm_cfg = &cmc_idpram_timing_cfg[DPRAM_SPEED_LOW]; + sromc_config_access_timing(bnk_cfg->csn, tm_cfg); + + /* + ** Remap SFR region for CMC22x IDPRAM + */ + if (!cmc_idpram_remap_sfr_region(&cmc_idpram_bank_cfg)) + return -1; + + /* + ** Register the modem device + */ + platform_device_register(&umts_modem); + + return 0; +} +late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/board-c1ctc-modems.c b/arch/arm/mach-exynos/board-c1ctc-modems.c deleted file mode 100644 index 85e35f5..0000000 --- a/arch/arm/mach-exynos/board-c1ctc-modems.c +++ /dev/null @@ -1,1712 +0,0 @@ -/* linux/arch/arm/mach-xxxx/board-c1ctc-modems.c - * Copyright (C) 2010 Samsung Electronics. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/regulator/consumer.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/vmalloc.h> -#include <linux/if_arp.h> - -/* inlcude platform specific file */ -#include <linux/platform_data/modem.h> -#include <mach/sec_modem.h> -#include <mach/gpio.h> -#include <mach/gpio-exynos4.h> -#include <plat/gpio-cfg.h> -#include <mach/regs-mem.h> -#include <plat/regs-srom.h> - -#ifdef CONFIG_USBHUB_USB3503 -#include <linux/i2c.h> -#include <linux/i2c-gpio.h> -#include <linux/platform_data/usb3503.h> -#endif -#include <plat/devs.h> -#include <plat/ehci.h> - - -#define SROM_CS0_BASE 0x04000000 -#define SROM_WIDTH 0x01000000 -#define SROM_NUM_ADDR_BITS 14 - -/* - * For SROMC Configuration: - * SROMC_ADDR_BYTE enable for byte access - */ -#define SROMC_DATA_16 0x1 -#define SROMC_ADDR_BYTE 0x2 -#define SROMC_WAIT_EN 0x4 -#define SROMC_BYTE_EN 0x8 -#define SROMC_MASK 0xF - -/* Memory attributes */ -enum sromc_attr { - MEM_DATA_BUS_16BIT = 0x00000001, - MEM_BYTE_ADDRESSABLE = 0x00000002, - MEM_WAIT_EN = 0x00000004, - MEM_BYTE_EN = 0x00000008, - -}; - -/* DPRAM configuration */ -struct sromc_cfg { - enum sromc_attr attr; - unsigned size; - unsigned csn; /* CSn # */ - unsigned addr; /* Start address (physical) */ - unsigned end; /* End address (physical) */ -}; - -/* DPRAM access timing configuration */ -struct sromc_access_cfg { - u32 tacs; /* Address set-up before CSn */ - u32 tcos; /* Chip selection set-up before OEn */ - u32 tacc; /* Access cycle */ - u32 tcoh; /* Chip selection hold on OEn */ - u32 tcah; /* Address holding time after CSn */ - u32 tacp; /* Page mode access cycle at Page mode */ - u32 pmc; /* Page Mode config */ -}; - -/* For MDM6600 EDPRAM (External DPRAM) */ -#define MSM_EDPRAM_SIZE 0x4000 /* 16 KB */ - - -#define INT_MASK_REQ_ACK_F 0x0020 -#define INT_MASK_REQ_ACK_R 0x0010 -#define INT_MASK_RES_ACK_F 0x0008 -#define INT_MASK_RES_ACK_R 0x0004 -#define INT_MASK_SEND_F 0x0002 -#define INT_MASK_SEND_R 0x0001 - -#define INT_MASK_REQ_ACK_RFS 0x0400 /* Request RES_ACK_RFS */ -#define INT_MASK_RES_ACK_RFS 0x0200 /* Response of REQ_ACK_RFS */ -#define INT_MASK_SEND_RFS 0x0100 /* Indicate sending RFS data */ - - -/* Function prototypes */ -static void config_dpram_port_gpio(void); -static void init_sromc(void); -static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg); -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg); -static int __init init_modem(void); - -#ifdef CONFIG_USBHUB_USB3503 -static int host_port_enable(int port, int enable); -#else -static int host_port_enable(int port, int enable) -{ - return s5p_ehci_port_control(&s5p_device_ehci, port, enable); -} -#endif - -static struct sromc_cfg msm_edpram_cfg = { - .attr = (MEM_DATA_BUS_16BIT | MEM_WAIT_EN | MEM_BYTE_EN), - .size = MSM_EDPRAM_SIZE, -}; - -static struct sromc_access_cfg msm_edpram_access_cfg[] = { - [DPRAM_SPEED_LOW] = { - .tacs = 0x2 << 28, - .tcos = 0x2 << 24, - .tacc = 0x3 << 16, - .tcoh = 0x2 << 12, - .tcah = 0x2 << 8, - .tacp = 0x2 << 4, - .pmc = 0x0 << 0, - }, -}; - -/* - magic_code + - access_enable + - fmt_tx_head + fmt_tx_tail + fmt_tx_buff + - raw_tx_head + raw_tx_tail + raw_tx_buff + - fmt_rx_head + fmt_rx_tail + fmt_rx_buff + - raw_rx_head + raw_rx_tail + raw_rx_buff + - padding + - mbx_cp2ap + - mbx_ap2cp - = 2 + - 2 + - 2 + 2 + 2044 + - 2 + 2 + 6128 + - 2 + 2 + 2044 + - 2 + 2 + 6128 + - 16 + - 2 + - 2 - = 16384 -*/ - -#define MSM_DP_FMT_TX_BUFF_SZ 2044 -#define MSM_DP_RAW_TX_BUFF_SZ 6128 -#define MSM_DP_FMT_RX_BUFF_SZ 2044 -#define MSM_DP_RAW_RX_BUFF_SZ 6128 - -#define MAX_MSM_EDPRAM_IPC_DEV 2 /* FMT, RAW */ - -struct msm_edpram_ipc_cfg { - u16 magic; - u16 access; - - u16 fmt_tx_head; - u16 fmt_tx_tail; - u8 fmt_tx_buff[MSM_DP_FMT_TX_BUFF_SZ]; - - u16 raw_tx_head; - u16 raw_tx_tail; - u8 raw_tx_buff[MSM_DP_RAW_TX_BUFF_SZ]; - - u16 fmt_rx_head; - u16 fmt_rx_tail; - u8 fmt_rx_buff[MSM_DP_FMT_RX_BUFF_SZ]; - - u16 raw_rx_head; - u16 raw_rx_tail; - u8 raw_rx_buff[MSM_DP_RAW_RX_BUFF_SZ]; - - u8 padding[16]; - u16 mbx_ap2cp; - u16 mbx_cp2ap; -}; - -struct msm_edpram_circ { - u16 __iomem *head; - u16 __iomem *tail; - u8 __iomem *buff; - u32 size; -}; - -struct msm_edpram_ipc_device { - char name[16]; - int id; - - struct msm_edpram_circ txq; - struct msm_edpram_circ rxq; - - u16 mask_req_ack; - u16 mask_res_ack; - u16 mask_send; -}; - -struct msm_edpram_ipc_map { - u16 __iomem *magic; - u16 __iomem *access; - - struct msm_edpram_ipc_device dev[MAX_MSM_EDPRAM_IPC_DEV]; - - u16 __iomem *mbx_ap2cp; - u16 __iomem *mbx_cp2ap; -}; - - -struct msm_edpram_boot_map { - u8 __iomem *buff; - u16 __iomem *frame_size; - u16 __iomem *tag; - u16 __iomem *count; -}; - -static struct msm_edpram_ipc_map msm_ipc_map; - -struct _param_nv { - unsigned char *addr; - unsigned int size; - unsigned int count; - unsigned int tag; -}; - - -#if (MSM_EDPRAM_SIZE == 0x4000) -/* ------------------- -Buffer : 15KByte ------------------- -Reserved: 1014Byte ------------------- -SIZE: 2Byte ------------------- -TAG: 2Byte ------------------- -COUNT: 2Byte ------------------- -AP -> CP Intr : 2Byte ------------------- -CP -> AP Intr : 2Byte ------------------- -*/ -#define DP_BOOT_CLEAR_OFFSET 4 -#define DP_BOOT_RSRVD_OFFSET 0x3C00 -#define DP_BOOT_SIZE_OFFSET 0x3FF6 -#define DP_BOOT_TAG_OFFSET 0x3FF8 -#define DP_BOOT_COUNT_OFFSET 0x3FFA - - -#define DP_BOOT_FRAME_SIZE_LIMIT 0x3C00 /* 15KB = 15360byte = 0x3C00 */ -#else -/* ------------------- -Buffer : 31KByte ------------------- -Reserved: 1014Byte ------------------- -SIZE: 2Byte ------------------- -TAG: 2Byte ------------------- -COUNT: 2Byte ------------------- -AP -> CP Intr : 2Byte ------------------- -CP -> AP Intr : 2Byte ------------------- -*/ -#define DP_BOOT_CLEAR_OFFSET 4 -#define DP_BOOT_RSRVD_OFFSET 0x7C00 -#define DP_BOOT_SIZE_OFFSET 0x7FF6 -#define DP_BOOT_TAG_OFFSET 0x7FF8 -#define DP_BOOT_COUNT_OFFSET 0x7FFA - - -#define DP_BOOT_FRAME_SIZE_LIMIT 0x7C00 /* 31KB = 31744byte = 0x7C00 */ -#endif - -struct _param_check { - unsigned int total_size; - unsigned int rest_size; - unsigned int send_size; - unsigned int copy_start; - unsigned int copy_complete; - unsigned int boot_complete; -}; - -static struct _param_nv *data_param; -static struct _param_check check_param; - -static unsigned int boot_start_complete; -static struct msm_edpram_boot_map msm_edpram_bt_map; -static struct msm_edpram_ipc_map msm_ipc_map; - -static void msm_edpram_reset(void); -static void msm_edpram_clr_intr(void); -static u16 msm_edpram_recv_intr(void); -static void msm_edpram_send_intr(u16 irq_mask); -static u16 msm_edpram_recv_msg(void); -static void msm_edpram_send_msg(u16 msg); - -static u16 msm_edpram_get_magic(void); -static void msm_edpram_set_magic(u16 value); -static u16 msm_edpram_get_access(void); -static void msm_edpram_set_access(u16 value); - -static u32 msm_edpram_get_tx_head(int dev_id); -static u32 msm_edpram_get_tx_tail(int dev_id); -static void msm_edpram_set_tx_head(int dev_id, u32 head); -static void msm_edpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *msm_edpram_get_tx_buff(int dev_id); -static u32 msm_edpram_get_tx_buff_size(int dev_id); - -static u32 msm_edpram_get_rx_head(int dev_id); -static u32 msm_edpram_get_rx_tail(int dev_id); -static void msm_edpram_set_rx_head(int dev_id, u32 head); -static void msm_edpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *msm_edpram_get_rx_buff(int dev_id); -static u32 msm_edpram_get_rx_buff_size(int dev_id); - -static u16 msm_edpram_get_mask_req_ack(int dev_id); -static u16 msm_edpram_get_mask_res_ack(int dev_id); -static u16 msm_edpram_get_mask_send(int dev_id); - -static void msm_log_disp(struct modemlink_dpram_control *dpctl); -static int msm_uload_step1(struct modemlink_dpram_control *dpctl); -static int msm_uload_step2(void *arg, struct modemlink_dpram_control *dpctl); -static int msm_dload_prep(struct modemlink_dpram_control *dpctl); -static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl); -static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl); -static int msm_boot_start(struct modemlink_dpram_control *dpctl); -static int msm_boot_start_post_proc(void); -static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl); -static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd); -static void msm_bt_map_init(struct modemlink_dpram_control *dpctl); -static void msm_load_init(struct modemlink_dpram_control *dpctl); - -static struct modemlink_dpram_control msm_edpram_ctrl = { - .reset = msm_edpram_reset, - - .clear_intr = msm_edpram_clr_intr, - .recv_intr = msm_edpram_recv_intr, - .send_intr = msm_edpram_send_intr, - .recv_msg = msm_edpram_recv_msg, - .send_msg = msm_edpram_send_msg, - - .get_magic = msm_edpram_get_magic, - .set_magic = msm_edpram_set_magic, - .get_access = msm_edpram_get_access, - .set_access = msm_edpram_set_access, - - .get_tx_head = msm_edpram_get_tx_head, - .get_tx_tail = msm_edpram_get_tx_tail, - .set_tx_head = msm_edpram_set_tx_head, - .set_tx_tail = msm_edpram_set_tx_tail, - .get_tx_buff = msm_edpram_get_tx_buff, - .get_tx_buff_size = msm_edpram_get_tx_buff_size, - - .get_rx_head = msm_edpram_get_rx_head, - .get_rx_tail = msm_edpram_get_rx_tail, - .set_rx_head = msm_edpram_set_rx_head, - .set_rx_tail = msm_edpram_set_rx_tail, - .get_rx_buff = msm_edpram_get_rx_buff, - .get_rx_buff_size = msm_edpram_get_rx_buff_size, - - .get_mask_req_ack = msm_edpram_get_mask_req_ack, - .get_mask_res_ack = msm_edpram_get_mask_res_ack, - .get_mask_send = msm_edpram_get_mask_send, - - .log_disp = msm_log_disp, - .cpupload_step1 = msm_uload_step1, - .cpupload_step2 = msm_uload_step2, - .cpimage_load = msm_dload, - .nvdata_load = msm_nv_load, - .phone_boot_start = msm_boot_start, - .dload_cmd_hdlr = msm_dload_handler, - .bt_map_init = msm_bt_map_init, - .load_init = msm_load_init, - .cpimage_load_prepare = msm_dload_prep, - .phone_boot_start_post_process = msm_boot_start_post_proc, - .phone_boot_start_handler = msm_boot_start_handler, - - .dp_base = NULL, - .dp_size = 0, - .dp_type = EXT_DPRAM, - - .dpram_irq = MSM_DPRAM_INT_IRQ, - .dpram_irq_flags = IRQF_TRIGGER_FALLING, - .dpram_irq_name = "MDM6600_EDPRAM_IRQ", - .dpram_wlock_name = "MDM6600_EDPRAM_WLOCK", - - .max_ipc_dev = IPC_RFS, -}; - -/* -** CDMA target platform data -*/ -static struct modem_io_t cdma_io_devices[] = { - [0] = { - .name = "cdma_boot0", - .id = 0x1, - .format = IPC_BOOT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [1] = { - .name = "cdma_ipc0", - .id = 0x1, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [2] = { - .name = "cdma_multipdp", - .id = 0x1, - .format = IPC_MULTI_RAW, - .io_type = IODEV_DUMMY, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [3] = { - .name = "cdma_CSD", - .id = (1|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [4] = { - .name = "cdma_FOTA", - .id = (2|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [5] = { - .name = "cdma_GPS", - .id = (5|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [6] = { - .name = "cdma_XTRA", - .id = (6|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [7] = { - .name = "cdma_CDMA", - .id = (7|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [8] = { - .name = "cdma_EFS", - .id = (8|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [9] = { - .name = "cdma_TRFB", - .id = (9|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [10] = { - .name = "rmnet0", - .id = 0x2A, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [11] = { - .name = "rmnet1", - .id = 0x2B, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [12] = { - .name = "rmnet2", - .id = 0x2C, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [13] = { - .name = "rmnet3", - .id = 0x2D, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [14] = { - .name = "cdma_SMD", - .id = (25|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [15] = { - .name = "cdma_VTVD", - .id = (26|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [16] = { - .name = "cdma_VTAD", - .id = (27|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [17] = { - .name = "cdma_VTCTRL", - .id = (28|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [18] = { - .name = "cdma_VTENT", - .id = (29|0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [19] = { - .name = "cdma_ramdump0", - .id = 0x1, - .format = IPC_RAMDUMP, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, -}; - -static struct modem_data cdma_modem_data = { - .name = "mdm6600", - - .gpio_cp_on = GPIO_CP_MSM_PWRON, - .gpio_cp_off = 0, - .gpio_reset_req_n = GPIO_CP_MSM_PMU_RST, - .gpio_cp_reset = GPIO_CP_MSM_RST, - .gpio_pda_active = GPIO_PDA_ACTIVE, - .gpio_phone_active = GPIO_MSM_PHONE_ACTIVE, - .gpio_flm_uart_sel = GPIO_BOOT_SW_SEL, - - .gpio_cp_dump_int = 0, - .gpio_cp_warm_reset = 0, - - .use_handover = false, - - .modem_net = CDMA_NETWORK, - .modem_type = QC_MDM6600, - .link_types = LINKTYPE(LINKDEV_DPRAM), - .link_name = "mdm6600_edpram", - .dpram_ctl = &msm_edpram_ctrl, - - .num_iodevs = ARRAY_SIZE(cdma_io_devices), - .iodevs = cdma_io_devices, -}; - -static struct resource cdma_modem_res[] = { - [0] = { - .name = "cp_active_irq", - .start = MSM_PHONE_ACTIVE_IRQ, - .end = MSM_PHONE_ACTIVE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cdma_modem = { - .name = "modem_if", - .id = 2, - .num_resources = ARRAY_SIZE(cdma_modem_res), - .resource = cdma_modem_res, - .dev = { - .platform_data = &cdma_modem_data, - }, -}; - -static void msm_edpram_reset(void) -{ - return; -} - -static void msm_edpram_clr_intr(void) -{ - ioread16(msm_ipc_map.mbx_cp2ap); -} - -static u16 msm_edpram_recv_intr(void) -{ - return ioread16(msm_ipc_map.mbx_cp2ap); -} - -static void msm_edpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, msm_ipc_map.mbx_ap2cp); -} - -static u16 msm_edpram_recv_msg(void) -{ - return ioread16(msm_ipc_map.mbx_cp2ap); -} - -static void msm_edpram_send_msg(u16 msg) -{ - iowrite16(msg, msm_ipc_map.mbx_ap2cp); -} - -static u16 msm_edpram_get_magic(void) -{ - return ioread16(msm_ipc_map.magic); -} - -static void msm_edpram_set_magic(u16 value) -{ - iowrite16(value, msm_ipc_map.magic); -} - -static u16 msm_edpram_get_access(void) -{ - return ioread16(msm_ipc_map.access); -} - -static void msm_edpram_set_access(u16 value) -{ - iowrite16(value, msm_ipc_map.access); -} - -static u32 msm_edpram_get_tx_head(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].txq.head); -} - -static u32 msm_edpram_get_tx_tail(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].txq.tail); -} - -static void msm_edpram_set_tx_head(int dev_id, u32 head) -{ - iowrite16((u16)head, msm_ipc_map.dev[dev_id].txq.head); -} - -static void msm_edpram_set_tx_tail(int dev_id, u32 tail) -{ - iowrite16((u16)tail, msm_ipc_map.dev[dev_id].txq.tail); -} - -static u8 __iomem *msm_edpram_get_tx_buff(int dev_id) -{ - return msm_ipc_map.dev[dev_id].txq.buff; -} - -static u32 msm_edpram_get_tx_buff_size(int dev_id) -{ - return msm_ipc_map.dev[dev_id].txq.size; -} - -static u32 msm_edpram_get_rx_head(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].rxq.head); -} - -static u32 msm_edpram_get_rx_tail(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].rxq.tail); -} - -static void msm_edpram_set_rx_head(int dev_id, u32 head) -{ - return iowrite16((u16)head, msm_ipc_map.dev[dev_id].rxq.head); -} - -static void msm_edpram_set_rx_tail(int dev_id, u32 tail) -{ - return iowrite16((u16)tail, msm_ipc_map.dev[dev_id].rxq.tail); -} - -static u8 __iomem *msm_edpram_get_rx_buff(int dev_id) -{ - return msm_ipc_map.dev[dev_id].rxq.buff; -} - -static u32 msm_edpram_get_rx_buff_size(int dev_id) -{ - return msm_ipc_map.dev[dev_id].rxq.size; -} - -static u16 msm_edpram_get_mask_req_ack(int dev_id) -{ - return msm_ipc_map.dev[dev_id].mask_req_ack; -} - -static u16 msm_edpram_get_mask_res_ack(int dev_id) -{ - return msm_ipc_map.dev[dev_id].mask_res_ack; -} - -static u16 msm_edpram_get_mask_send(int dev_id) -{ - return msm_ipc_map.dev[dev_id].mask_send; -} - -static void msm_log_disp(struct modemlink_dpram_control *dpctl) -{ - static unsigned char buf[151]; - u8 __iomem *tmp_buff = NULL; - - tmp_buff = dpctl->get_rx_buff(IPC_FMT); - memcpy(buf, tmp_buff, (sizeof(buf)-1)); - - pr_info("[LNK] | PHONE ERR MSG\t| CDMA Crash\n"); - pr_info("[LNK] | PHONE ERR MSG\t| %s\n", buf); -} - -static int msm_data_upload(struct _param_nv *param, - struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - u16 in_interrupt = 0; - int count = 0; - - while (1) { - if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) { - in_interrupt = dpctl->recv_msg(); - if (in_interrupt == 0xDBAB) { - break; - } else { - pr_err("[LNK][intr]:0x%08x\n", in_interrupt); - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - msleep_interruptible(1); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - param->size = ioread16(msm_edpram_bt_map.frame_size); - memcpy(param->addr, msm_edpram_bt_map.buff, param->size); - param->tag = ioread16(msm_edpram_bt_map.tag); - param->count = ioread16(msm_edpram_bt_map.count); - - dpctl->clear_intr(); - dpctl->send_msg(0xDB12); - - return retval; - -} - -static int msm_data_load(struct _param_nv *param, - struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - - if (param->size <= DP_BOOT_FRAME_SIZE_LIMIT) { - memcpy(msm_edpram_bt_map.buff, param->addr, param->size); - iowrite16(param->size, msm_edpram_bt_map.frame_size); - iowrite16(param->tag, msm_edpram_bt_map.tag); - iowrite16(param->count, msm_edpram_bt_map.count); - - dpctl->clear_intr(); - dpctl->send_msg(0xDB12); - - } else { - pr_err("[LNK/E]<%s> size:0x%x\n", __func__, param->size); - } - - return retval; -} - -static int msm_uload_step1(struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - u16 in_interrupt = 0, out_interrupt = 0; - - pr_info("[LNK] +---------------------------------------------+\n"); - pr_info("[LNK] | UPLOAD PHONE SDRAM |\n"); - pr_info("[LNK] +---------------------------------------------+\n"); - - while (1) { - if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) { - in_interrupt = dpctl->recv_msg(); - pr_info("[LNK] [in_interrupt] 0x%04x\n", in_interrupt); - if (in_interrupt == 0x1234) { - break; - } else { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - msleep_interruptible(1); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - in_interrupt = dpctl->recv_msg(); - if (in_interrupt == 0x1234) { - pr_info("[LNK] [in_interrupt]: 0x%04x\n", - in_interrupt); - break; - } - return -1; - } - } - out_interrupt = 0xDEAD; - dpctl->send_msg(out_interrupt); - - return retval; -} - -static int msm_uload_step2(void *arg, - struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - struct _param_nv param; - - retval = copy_from_user((void *)¶m, (void *)arg, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - retval = msm_data_upload(¶m, dpctl); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - if (!(param.count % 500)) - pr_info("[LNK] [param->count]:%d\n", param.count); - - if (param.tag == 4) { - dpctl->clear_intr(); - enable_irq(msm_edpram_ctrl.dpram_irq); - pr_info("[LNK] [param->tag]:%d\n", param.tag); - } - - retval = copy_to_user((unsigned long *)arg, ¶m, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - return retval; -} - -static int msm_dload_prep(struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - - while (1) { - if (check_param.copy_start) { - check_param.copy_start = 0; - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - return retval; -} - -static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - unsigned char *img = NULL; - struct _param_nv param; - - retval = copy_from_user((void *)¶m, (void *)arg, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - img = vmalloc(param.size); - if (img == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - memset(img, 0, param.size); - memcpy(img, param.addr, param.size); - - data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL); - if (data_param == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(img); - return -1; - } - - check_param.total_size = param.size; - check_param.rest_size = param.size; - check_param.send_size = 0; - check_param.copy_complete = 0; - - data_param->addr = img; - data_param->size = DP_BOOT_FRAME_SIZE_LIMIT; - data_param->count = param.count; - - data_param->tag = 0x0001; - - if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT) - data_param->size = check_param.rest_size; - - retval = msm_data_load(data_param, dpctl); - - while (1) { - if (check_param.copy_complete) { - check_param.copy_complete = 0; - - vfree(img); - kfree(data_param); - - break; - } - msleep_interruptible(10); - count++; - if (count > 1000) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(img); - kfree(data_param); - return -1; - } - } - - return retval; - -} - -static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - unsigned char *img = NULL; - struct _param_nv param; - - retval = copy_from_user((void *)¶m, (void *)arg, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - img = vmalloc(param.size); - if (img == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - memset(img, 0, param.size); - memcpy(img, param.addr, param.size); - - data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL); - if (data_param == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(img); - return -1; - } - - check_param.total_size = param.size; - check_param.rest_size = param.size; - check_param.send_size = 0; - check_param.copy_complete = 0; - - data_param->addr = img; - data_param->size = DP_BOOT_FRAME_SIZE_LIMIT; - data_param->count = 1; - data_param->tag = 0x0002; - - if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT) - data_param->size = check_param.rest_size; - - retval = msm_data_load(data_param, dpctl); - - while (1) { - if (check_param.copy_complete) { - check_param.copy_complete = 0; - - vfree(img); - kfree(data_param); - - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(img); - kfree(data_param); - return -1; - } - } - - return retval; - -} - -static int msm_boot_start(struct modemlink_dpram_control *dpctl) -{ - - u16 out_interrupt = 0; - int count = 0; - - /* Send interrupt -> '0x4567' */ - out_interrupt = 0x4567; - dpctl->send_msg(out_interrupt); - - while (1) { - if (check_param.boot_complete) { - check_param.boot_complete = 0; - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - return 0; -} - -static struct modemlink_dpram_control *tasklet_dpctl; - -static void interruptable_load_tasklet_handler(unsigned long data); - -static DECLARE_TASKLET(interruptable_load_tasklet, - interruptable_load_tasklet_handler, (unsigned long) &tasklet_dpctl); - -static void interruptable_load_tasklet_handler(unsigned long data) -{ - struct modemlink_dpram_control *dpctl = - (struct modemlink_dpram_control *) - (*((struct modemlink_dpram_control **) data)); - - if (data_param == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return; - } - - check_param.send_size += data_param->size; - check_param.rest_size -= data_param->size; - data_param->addr += data_param->size; - - if (check_param.send_size < check_param.total_size) { - - if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT) - data_param->size = check_param.rest_size; - - - data_param->count += 1; - - msm_data_load(data_param, dpctl); - } else { - data_param->tag = 0; - check_param.copy_complete = 1; - } - -} - -static int msm_boot_start_post_proc(void) -{ - int count = 0; - - while (1) { - if (boot_start_complete) { - boot_start_complete = 0; - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - return 0; -} - -static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl) -{ - boot_start_complete = 1; - - /* Send INIT_END code to CP */ - pr_info("[LNK] <%s> Send 0x11C2 (INIT_END)\n", __func__); - - /* - * INT_MASK_VALID|INT_MASK_CMD|INT_MASK_CP_AIRPLANE_BOOT| - * INT_MASK_CP_AP_ANDROID|INT_MASK_CMD_INIT_END - */ - dpctl->send_intr((0x0080|0x0040|0x1000|0x0100|0x0002)); -} - -static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd) -{ - switch (cmd) { - case 0x1234: - check_param.copy_start = 1; - break; - - case 0xDBAB: - tasklet_schedule(&interruptable_load_tasklet); - break; - - case 0xABCD: - check_param.boot_complete = 1; - break; - - default: - pr_err("[LNK/Err] <%s> Unknown command.. %x\n", __func__, cmd); - } -} - -static void msm_bt_map_init(struct modemlink_dpram_control *dpctl) -{ - msm_edpram_bt_map.buff = (u8 *)(dpctl->dp_base); - msm_edpram_bt_map.frame_size = - (u16 *)(dpctl->dp_base + DP_BOOT_SIZE_OFFSET); - msm_edpram_bt_map.tag = - (u16 *)(dpctl->dp_base + DP_BOOT_TAG_OFFSET); - msm_edpram_bt_map.count = - (u16 *)(dpctl->dp_base + DP_BOOT_COUNT_OFFSET); -} - - -static void msm_load_init(struct modemlink_dpram_control *dpctl) -{ - tasklet_dpctl = dpctl; - if (tasklet_dpctl == NULL) - pr_err("[LNK/Err] failed tasklet_dpctl remap\n"); - - check_param.total_size = 0; - check_param.rest_size = 0; - check_param.send_size = 0; - check_param.copy_start = 0; - check_param.copy_complete = 0; - check_param.boot_complete = 0; - - dpctl->clear_intr(); -} - -static void config_cdma_modem_gpio(void) -{ - int err; - unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on; - unsigned gpio_cp_off = cdma_modem_data.gpio_cp_off; - unsigned gpio_rst_req_n = cdma_modem_data.gpio_reset_req_n; - unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset; - unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active; - unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active; - unsigned gpio_flm_uart_sel = cdma_modem_data.gpio_flm_uart_sel; - - pr_info("[MODEMS] <%s>\n", __func__); - - if (gpio_pda_active) { - err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); - if (err) { - pr_err("fail to request gpio %s\n", "PDA_ACTIVE"); - } else { - gpio_direction_output(gpio_pda_active, 1); - s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_pda_active, 0); - } - } - - if (gpio_phone_active) { - err = gpio_request(gpio_phone_active, "MSM_ACTIVE"); - if (err) { - pr_err("fail to request gpio %s\n", "MSM_ACTIVE"); - } else { - s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); - s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); - irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH); - } - } - - if (gpio_flm_uart_sel) { - err = gpio_request(gpio_flm_uart_sel, "BOOT_SW_SEL"); - if (err) { - pr_err("fail to request gpio %s\n", "BOOT_SW_SEL"); - } else { - gpio_direction_output(gpio_flm_uart_sel, 1); - s3c_gpio_setpull(gpio_flm_uart_sel, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_flm_uart_sel, 1); - } - } - - if (gpio_cp_on) { - err = gpio_request(gpio_cp_on, "MSM_ON"); - if (err) { - pr_err("fail to request gpio %s\n", "MSM_ON"); - } else { - gpio_direction_output(gpio_cp_on, 1); - s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_cp_on, 0); - } - } - - if (gpio_cp_off) { - err = gpio_request(gpio_cp_off, "MSM_OFF"); - if (err) { - pr_err("fail to request gpio %s\n", "MSM_OFF"); - } else { - gpio_direction_output(gpio_cp_off, 1); - s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_cp_off, 1); - } - } - - if (gpio_rst_req_n) { - err = gpio_request(gpio_rst_req_n, "MSM_RST_REQ"); - if (err) { - pr_err("fail to request gpio %s\n", "MSM_RST_REQ"); - } else { - gpio_direction_output(gpio_rst_req_n, 1); - s3c_gpio_setpull(gpio_rst_req_n, S3C_GPIO_PULL_NONE); - } - gpio_set_value(gpio_rst_req_n, 0); - } - - if (gpio_cp_rst) { - err = gpio_request(gpio_cp_rst, "MSM_RST"); - if (err) { - pr_err("fail to request gpio %s\n", "MSM_RST"); - } else { - gpio_direction_output(gpio_cp_rst, 1); - s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); - } - gpio_set_value(gpio_cp_rst, 0); - } -} - -static u8 *msm_edpram_remap_mem_region(struct sromc_cfg *cfg) -{ - int dp_addr = 0; - int dp_size = 0; - u8 __iomem *dp_base = NULL; - struct msm_edpram_ipc_cfg *ipc_map = NULL; - struct msm_edpram_ipc_device *dev = NULL; - - dp_addr = cfg->addr; - dp_size = cfg->size; - dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size); - if (!dp_base) { - pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__); - return NULL; - } - pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base); - - msm_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; - msm_edpram_ctrl.dp_size = dp_size; - - /* Map for IPC */ - ipc_map = (struct msm_edpram_ipc_cfg *)dp_base; - - /* Magic code and access enable fields */ - msm_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; - msm_ipc_map.access = (u16 __iomem *)&ipc_map->access; - - /* FMT */ - dev = &msm_ipc_map.dev[IPC_FMT]; - - strcpy(dev->name, "FMT"); - dev->id = IPC_FMT; - - dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; - dev->txq.size = MSM_DP_FMT_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; - dev->rxq.size = MSM_DP_FMT_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_F; - dev->mask_res_ack = INT_MASK_RES_ACK_F; - dev->mask_send = INT_MASK_SEND_F; - - /* RAW */ - dev = &msm_ipc_map.dev[IPC_RAW]; - - strcpy(dev->name, "RAW"); - dev->id = IPC_RAW; - - dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; - dev->txq.size = MSM_DP_RAW_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; - dev->rxq.size = MSM_DP_RAW_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_R; - dev->mask_res_ack = INT_MASK_RES_ACK_R; - dev->mask_send = INT_MASK_SEND_R; - -#if 0 - /* RFS */ - dev = &msm_ipc_map.dev[IPC_RFS]; - - strcpy(dev->name, "RFS"); - dev->id = IPC_RFS; - - dev->txq.head = (u16 __iomem *)&ipc_map->rfs_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->rfs_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->rfs_tx_buff[0]; - dev->txq.size = MSM_DP_RFS_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->rfs_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->rfs_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->rfs_rx_buff[0]; - dev->rxq.size = MSM_DP_RFS_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_RFS; - dev->mask_res_ack = INT_MASK_RES_ACK_RFS; - dev->mask_send = INT_MASK_SEND_RFS; -#endif - - /* Mailboxes */ - msm_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; - msm_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; - - return dp_base; -} - -/** - * DPRAM GPIO settings - * - * SROM_NUM_ADDR_BITS value indicate the address line number or - * the mux/demux dpram type. if you want to set mux mode, define the - * SROM_NUM_ADDR_BITS to zero. - * - * for CMC22x - * CMC22x has 16KB + a SFR register address. - * It used 14 bits (13bits for 16KB word address and 1 bit for SFR - * register) - */ -static void config_dpram_port_gpio(void) -{ - int addr_bits = SROM_NUM_ADDR_BITS; - - pr_info("[MDM] <%s> address line = %d bits\n", __func__, addr_bits); - - /* - ** Config DPRAM address/data GPIO pins - */ - - /* Set GPIO for dpram address */ - switch (addr_bits) { - case 0: - break; - - case 13 ... 14: - s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR, - S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0), - addr_bits - EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2)); - pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n", - __func__, addr_bits - EXYNOS4_GPIO_Y3_NR); - break; - - default: - pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__); - return; - } - - /* Set GPIO for dpram data - 16bit */ - s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(EXYNOS4_GPY6(0), 8, S3C_GPIO_SFN(2)); - - /* Setup SROMC CSn pins */ - s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2)); - - /* Config OEn, WEn */ - s3c_gpio_cfgrange_nopull(GPIO_DPRAM_REN, 2, S3C_GPIO_SFN(2)); - - /* Config LBn, UBn */ - s3c_gpio_cfgrange_nopull(GPIO_DPRAM_LBN, 2, S3C_GPIO_SFN(2)); - - /* Config BUSY */ - s3c_gpio_cfgpin(GPIO_DPRAM_BUSY, S3C_GPIO_SFN(2)); -} - -static void init_sromc(void) -{ - struct clk *clk = NULL; - - /* SROMC clk enable */ - clk = clk_get(NULL, "sromc"); - if (!clk) { - pr_err("[MDM/E] <%s> SROMC clock gate fail\n", __func__); - return; - } - clk_enable(clk); -} - -static void setup_sromc -( - unsigned csn, - struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg -) -{ - unsigned bw = 0; - unsigned bc = 0; - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - - pr_err("[MDM] <%s> SROMC settings for CS%d...\n", __func__, csn); - - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - pr_err("[MDM] <%s> Old SROMC settings = BW(0x%08X), BC%d(0x%08X)\n", - __func__, bw, csn, bc); - - /* Set the BW control field for the CSn */ - bw &= ~(SROMC_MASK << (csn * 4)); - - if (cfg->attr | MEM_DATA_BUS_16BIT) - bw |= (SROMC_DATA_16 << (csn * 4)); - - if (cfg->attr | MEM_WAIT_EN) - bw |= (SROMC_WAIT_EN << (csn * 4)); - - if (cfg->attr | MEM_BYTE_EN) - bw |= (SROMC_BYTE_EN << (csn * 4)); - - writel(bw, S5P_SROM_BW); - - /* Set SROMC memory access timing for the CSn */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - - writel(bc, bank_sfr); - - /* Verify SROMC settings */ - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - pr_err("[MDM] <%s> New SROMC settings = BW(0x%08X), BC%d(0x%08X)\n", - __func__, bw, csn, bc); -} - -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg) -{ - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - unsigned bc = 0; - - bc = __raw_readl(bank_sfr); - pr_info("[MDM] <%s> Old CS%d setting = 0x%08X\n", __func__, csn, bc); - - /* SROMC memory access timing setting */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - writel(bc, bank_sfr); - - bc = __raw_readl(bank_sfr); - pr_err("[MDM] <%s> New CS%d setting = 0x%08X\n", __func__, csn, bc); -} - -static int __init init_modem(void) -{ - struct sromc_cfg *cfg = NULL; - struct sromc_access_cfg *acc_cfg = NULL; - - msm_edpram_cfg.csn = 0; - msm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * msm_edpram_cfg.csn); - msm_edpram_cfg.end = msm_edpram_cfg.addr + msm_edpram_cfg.size - 1; - - config_dpram_port_gpio(); - config_cdma_modem_gpio(); - - init_sromc(); - cfg = &msm_edpram_cfg; - acc_cfg = &msm_edpram_access_cfg[DPRAM_SPEED_LOW]; - setup_sromc(cfg->csn, cfg, acc_cfg); - - if (!msm_edpram_remap_mem_region(&msm_edpram_cfg)) - return -1; - platform_device_register(&cdma_modem); - - return 0; -} -late_initcall(init_modem); -/*device_initcall(init_modem);*/ - -#ifdef CONFIG_USBHUB_USB3503 -static int (*usbhub_set_mode)(struct usb3503_hubctl *, int); -static struct usb3503_hubctl *usbhub_ctl; - -void set_host_states(struct platform_device *pdev, int type) -{ -} - -static int usb3503_hub_handler(void (*set_mode)(void), void *ctl) -{ - if (!set_mode || !ctl) - return -EINVAL; - - usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode; - usbhub_ctl = (struct usb3503_hubctl *)ctl; - - pr_info("[MDM] <%s> set_mode(%pF)\n", __func__, set_mode); - - return 0; -} - -static int usb3503_hw_config(void) -{ - int err; - - err = gpio_request(GPIO_USB_HUB_CONNECT, "HUB_CONNECT"); - if (err) { - pr_err("fail to request gpio %s\n", "HUB_CONNECT"); - } else { - gpio_direction_output(GPIO_USB_HUB_CONNECT, 0); - s3c_gpio_setpull(GPIO_USB_HUB_CONNECT, S3C_GPIO_PULL_NONE); - } - s5p_gpio_set_drvstr(GPIO_USB_HUB_CONNECT, S5P_GPIO_DRVSTR_LV1); - - err = gpio_request(GPIO_USB_BOOT_EN, "USB_BOOT_EN"); - if (err) { - pr_err("fail to request gpio %s\n", "USB_BOOT_EN"); - } else { - gpio_direction_output(GPIO_USB_BOOT_EN, 1); - s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE); - } - msleep(100); - - err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST"); - if (err) { - pr_err("fail to request gpio %s\n", "HUB_RST"); - } else { - gpio_direction_output(GPIO_USB_HUB_RST, 0); - s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE); - } - s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1); - /* need to check drvstr 1 or 2 */ - - /* for USB3503 26Mhz Reference clock setting */ - err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT"); - if (err) { - pr_err("fail to request gpio %s\n", "HUB_INT"); - } else { - gpio_direction_output(GPIO_USB_HUB_INT, 1); - s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE); - } - - return 0; -} - -static int usb3503_reset_n(int val) -{ - gpio_set_value(GPIO_USB_HUB_RST, 0); - msleep(20); - pr_info("[MDM] <%s> val = %d\n", __func__, - gpio_get_value(GPIO_USB_HUB_RST)); - gpio_set_value(GPIO_USB_HUB_RST, !!val); - - pr_info("[MDM] <%s> val = %d\n", __func__, - gpio_get_value(GPIO_USB_HUB_RST)); - - udelay(5); /* need it ?*/ - return 0; -} - -static struct usb3503_platform_data usb3503_pdata = { - .initial_mode = USB3503_MODE_STANDBY, - .reset_n = usb3503_reset_n, - .register_hub_handler = usb3503_hub_handler, - .port_enable = host_port_enable, -}; - -static struct i2c_board_info i2c_devs20_emul[] __initdata = { - { - I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08), - .platform_data = &usb3503_pdata, - }, -}; - -/* I2C20_EMUL */ -static struct i2c_gpio_platform_data i2c20_platdata = { - .sda_pin = GPIO_USB_HUB_SDA, - .scl_pin = GPIO_USB_HUB_SCL, - /*FIXME: need to timming tunning... */ - .udelay = 20, -}; - -static struct platform_device s3c_device_i2c20 = { - .name = "i2c-gpio", - .id = 20, - .dev.platform_data = &i2c20_platdata, -}; - -static int __init init_usbhub(void) -{ - usb3503_hw_config(); - i2c_register_board_info(20, i2c_devs20_emul, - ARRAY_SIZE(i2c_devs20_emul)); - - platform_device_register(&s3c_device_i2c20); - return 0; -} - -device_initcall(init_usbhub); - -static int host_port_enable(int port, int enable) -{ - int err, retry = 30; - - pr_info("[MDM] <%s> port(%d) control(%d)\n", __func__, port, enable); - - if (enable) { - err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB); - if (err < 0) { - pr_err("[MDM] <%s> hub on fail\n", __func__); - goto exit; - } - err = s5p_ehci_port_control(&s5p_device_ehci, port, 1); - if (err < 0) { - pr_err("[MDM] <%s> port(%d) enable fail\n", __func__, - port); - goto exit; - } -#ifdef CONFIG_LTE_MODEM_CMC221 - msleep(20); - err = gpio_direction_output(umts_modem_data.gpio_slave_wakeup, - 1); - pr_err("[MDM] <%s> slave wakeup err(%d), en(%d), level(%d)\n", - __func__, err, 1, - gpio_get_value(umts_modem_data.gpio_slave_wakeup)); - - while (!gpio_get_value(umts_modem_data.gpio_slave_wakeup) - && retry--) - msleep(20); - pr_err("[MDM] <%s> Host wakeup (%d) retry(%d)\n", __func__, - gpio_get_value(umts_modem_data.gpio_host_wakeup), - retry); - err = gpio_direction_output(umts_modem_data.gpio_slave_wakeup, - 0); - pr_err("[MDM] <%s> slave wakeup err(%d), en(%d), level(%d)\n", - __func__, err, 0, - gpio_get_value(umts_modem_data.gpio_slave_wakeup)); -#endif - } else { - err = s5p_ehci_port_control(&s5p_device_ehci, port, 0); - if (err < 0) { - pr_err("[MDM] <%s> port(%d) enable fail\n", __func__, - port); - goto exit; - } - err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY); - if (err < 0) { - pr_err("[MDM] <%s> hub off fail\n", __func__); - goto exit; - } - } - -#ifdef CONFIG_LTE_MODEM_CMC221 - err = gpio_direction_output(umts_modem_data.gpio_host_active, enable); - pr_info("[MDM] <%s> active state err(%d), en(%d), level(%d)\n", - __func__, err, enable, - gpio_get_value(umts_modem_data.gpio_host_active)); -#endif - -exit: - return err; -} -#else -void set_host_states(struct platform_device *pdev, int type) -{ - if (active_ctl.gpio_initialized) { - pr_err(" [MODEM_IF] Active States =%d, %s\n", type, pdev->name); - gpio_direction_output(modem_link_pm_data.gpio_link_active, - type); - } else - active_ctl.gpio_request_host_active = 1; -} -#endif - diff --git a/arch/arm/mach-exynos/board-c1lgt-modems.c b/arch/arm/mach-exynos/board-c1lgt-modems.c index aa218db..5fff511 100644 --- a/arch/arm/mach-exynos/board-c1lgt-modems.c +++ b/arch/arm/mach-exynos/board-c1lgt-modems.c @@ -24,290 +24,31 @@ #include <linux/clk.h> /* inlcude platform specific file */ +#include <linux/cpufreq_pegasusq.h> #include <linux/platform_data/modem.h> -#include <mach/sec_modem.h> + +#include <plat/gpio-cfg.h> +#include <plat/regs-srom.h> +#include <plat/devs.h> +#include <plat/ehci.h> + +#include <mach/dev.h> #include <mach/gpio.h> #include <mach/gpio-exynos4.h> -#include <plat/gpio-cfg.h> #include <mach/regs-mem.h> -#include <plat/regs-srom.h> +#include <mach/cpufreq.h> +#include <mach/sec_modem.h> +#include <mach/sromc-exynos4.h> #ifdef CONFIG_USBHUB_USB3503 #include <linux/i2c.h> #include <linux/i2c-gpio.h> #include <linux/platform_data/usb3503.h> -#include <mach/cpufreq.h> #include <plat/usb-phy.h> #endif -#include <plat/devs.h> -#include <plat/ehci.h> - -#define SROM_CS0_BASE 0x04000000 -#define SROM_WIDTH 0x01000000 -#define SROM_NUM_ADDR_BITS 14 - -/* For "bus width and wait control (BW)" register */ -enum sromc_attr { - SROMC_DATA_16 = 0x1, /* 16-bit data bus */ - SROMC_BYTE_ADDR = 0x2, /* Byte base address */ - SROMC_WAIT_EN = 0x4, /* Wait enabled */ - SROMC_BYTE_EN = 0x8, /* Byte access enabled */ - SROMC_MASK = 0xF -}; - -/* DPRAM configuration */ -struct sromc_cfg { - enum sromc_attr attr; - unsigned size; - unsigned csn; /* CSn # */ - unsigned addr; /* Start address (physical) */ - unsigned end; /* End address (physical) */ -}; - -/* DPRAM access timing configuration */ -struct sromc_access_cfg { - u32 tacs; /* Address set-up before CSn */ - u32 tcos; /* Chip selection set-up before OEn */ - u32 tacc; /* Access cycle */ - u32 tcoh; /* Chip selection hold on OEn */ - u32 tcah; /* Address holding time after CSn */ - u32 tacp; /* Page mode access cycle at Page mode */ - u32 pmc; /* Page Mode config */ -}; - -/* For CMC221 IDPRAM (Internal DPRAM) */ -#define CMC_IDPRAM_SIZE 0x4000 /* 16 KB */ -/* FOR CMC221 SFR for IDPRAM */ -#define CMC_INT2CP_REG 0x10 /* Interrupt to CP */ -#define CMC_INT2AP_REG 0x50 -#define CMC_CLR_INT_REG 0x28 /* Clear Interrupt to AP */ -#define CMC_RESET_REG 0x3C -#define CMC_PUT_REG 0x40 /* AP->CP reg for hostbooting */ -#define CMC_GET_REG 0x50 /* CP->AP reg for hostbooting */ - -/* For CBP7.2 EDPRAM (External DPRAM) */ -#define CBP_EDPRAM_SIZE 0x4000 /* 16 KB */ - -#define INT_MASK_REQ_ACK_F 0x0020 -#define INT_MASK_REQ_ACK_R 0x0010 -#define INT_MASK_RES_ACK_F 0x0008 -#define INT_MASK_RES_ACK_R 0x0004 -#define INT_MASK_SEND_F 0x0002 -#define INT_MASK_SEND_R 0x0001 - -#define INT_MASK_REQ_ACK_RFS 0x0400 /* Request RES_ACK_RFS */ -#define INT_MASK_RES_ACK_RFS 0x0200 /* Response of REQ_ACK_RFS */ -#define INT_MASK_SEND_RFS 0x0100 /* Indicate sending RFS data */ - - -/* Function prototypes */ -static void config_dpram_port_gpio(void); -static void init_sromc(void); -static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg); -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg); static int __init init_modem(void); -#ifdef CONFIG_USBHUB_USB3503 -static int host_port_enable(int port, int enable); -#else -static int host_port_enable(int port, int enable) -{ - return s5p_ehci_port_control(&s5p_device_ehci, port, enable); -} -#endif - -#ifdef CONFIG_LTE_MODEM_CMC221 -static struct sromc_cfg cmc_idpram_cfg = { - .attr = SROMC_DATA_16, - .size = CMC_IDPRAM_SIZE, -}; - -static struct sromc_access_cfg cmc_idpram_access_cfg[] = { - [DPRAM_SPEED_LOW] = { - /* for 33 MHz clock, 64 cycles */ - .tacs = 0x08 << 28, - .tcos = 0x08 << 24, - .tacc = 0x1F << 16, - .tcoh = 0x08 << 12, - .tcah = 0x08 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, - [DPRAM_SPEED_MID] = { - /* for 66 MHz clock, 32 cycles */ - .tacs = 0x01 << 28, - .tcos = 0x01 << 24, - .tacc = 0x1B << 16, - .tcoh = 0x01 << 12, - .tcah = 0x01 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, - [DPRAM_SPEED_HIGH] = { - /* for 133 MHz clock, 16 cycles */ - .tacs = 0x01 << 28, - .tcos = 0x01 << 24, - .tacc = 0x0B << 16, - .tcoh = 0x01 << 12, - .tcah = 0x01 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, -}; - -/* - magic_code + - access_enable + - fmt_tx_head + fmt_tx_tail + fmt_tx_buff + - raw_tx_head + raw_tx_tail + raw_tx_buff + - fmt_rx_head + fmt_rx_tail + fmt_rx_buff + - raw_rx_head + raw_rx_tail + raw_rx_buff + - mbx_cp2ap + - mbx_ap2cp - = 2 + - 2 + - 2 + 2 + 1336 + - 2 + 2 + 4564 + - 2 + 2 + 1336 + - 2 + 2 + 9124 + - 2 + - 2 - = 16384 -*/ - -#define DP_FMT_TX_BUFF_SZ 1336 -#define DP_RAW_TX_BUFF_SZ 4564 -#define DP_FMT_RX_BUFF_SZ 1336 -#define DP_RAW_RX_BUFF_SZ 9124 - -#define MAX_CMC_IDPRAM_IPC_DEV (IPC_RAW + 1) /* FMT, RAW */ - -struct dpram_ipc_cfg { - u16 magic; - u16 access; - - u16 fmt_tx_head; - u16 fmt_tx_tail; - u8 fmt_tx_buff[DP_FMT_TX_BUFF_SZ]; - - u16 raw_tx_head; - u16 raw_tx_tail; - u8 raw_tx_buff[DP_RAW_TX_BUFF_SZ]; - - u16 fmt_rx_head; - u16 fmt_rx_tail; - u8 fmt_rx_buff[DP_FMT_RX_BUFF_SZ]; - - u16 raw_rx_head; - u16 raw_rx_tail; - u8 raw_rx_buff[DP_RAW_RX_BUFF_SZ]; - - u16 mbx_cp2ap; - u16 mbx_ap2cp; -}; - -struct cmc221_idpram_sfr { - u16 __iomem *int2cp; - u16 __iomem *int2ap; - u16 __iomem *clr_int2ap; - u16 __iomem *reset; - u16 __iomem *msg2cp; - u16 __iomem *msg2ap; -}; - -static struct dpram_ipc_map cmc_ipc_map; -static u8 *cmc_sfr_base; -static struct cmc221_idpram_sfr cmc_sfr; - -/* Function prototypes */ -static void cmc_idpram_reset(void); -static void cmc_idpram_setup_speed(enum dpram_speed); -static int cmc_idpram_wakeup(void); -static void cmc_idpram_sleep(void); -static void cmc_idpram_clr_intr(void); -static u16 cmc_idpram_recv_intr(void); -static void cmc_idpram_send_intr(u16 irq_mask); -static u16 cmc_idpram_recv_msg(void); -static void cmc_idpram_send_msg(u16 msg); - -static u16 cmc_idpram_get_magic(void); -static void cmc_idpram_set_magic(u16 value); -static u16 cmc_idpram_get_access(void); -static void cmc_idpram_set_access(u16 value); - -static u32 cmc_idpram_get_tx_head(int dev_id); -static u32 cmc_idpram_get_tx_tail(int dev_id); -static void cmc_idpram_set_tx_head(int dev_id, u32 head); -static void cmc_idpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id); -static u32 cmc_idpram_get_tx_buff_size(int dev_id); - -static u32 cmc_idpram_get_rx_head(int dev_id); -static u32 cmc_idpram_get_rx_tail(int dev_id); -static void cmc_idpram_set_rx_head(int dev_id, u32 head); -static void cmc_idpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id); -static u32 cmc_idpram_get_rx_buff_size(int dev_id); - -static u16 cmc_idpram_get_mask_req_ack(int dev_id); -static u16 cmc_idpram_get_mask_res_ack(int dev_id); -static u16 cmc_idpram_get_mask_send(int dev_id); - -static struct modemlink_dpram_control cmc_idpram_ctrl = { - .reset = cmc_idpram_reset, - - .setup_speed = cmc_idpram_setup_speed, - - .wakeup = cmc_idpram_wakeup, - .sleep = cmc_idpram_sleep, - - .clear_intr = cmc_idpram_clr_intr, - .recv_intr = cmc_idpram_recv_intr, - .send_intr = cmc_idpram_send_intr, - .recv_msg = cmc_idpram_recv_msg, - .send_msg = cmc_idpram_send_msg, - - .get_magic = cmc_idpram_get_magic, - .set_magic = cmc_idpram_set_magic, - .get_access = cmc_idpram_get_access, - .set_access = cmc_idpram_set_access, - - .get_tx_head = cmc_idpram_get_tx_head, - .get_tx_tail = cmc_idpram_get_tx_tail, - .set_tx_head = cmc_idpram_set_tx_head, - .set_tx_tail = cmc_idpram_set_tx_tail, - .get_tx_buff = cmc_idpram_get_tx_buff, - .get_tx_buff_size = cmc_idpram_get_tx_buff_size, - - .get_rx_head = cmc_idpram_get_rx_head, - .get_rx_tail = cmc_idpram_get_rx_tail, - .set_rx_head = cmc_idpram_set_rx_head, - .set_rx_tail = cmc_idpram_set_rx_tail, - .get_rx_buff = cmc_idpram_get_rx_buff, - .get_rx_buff_size = cmc_idpram_get_rx_buff_size, - - .get_mask_req_ack = cmc_idpram_get_mask_req_ack, - .get_mask_res_ack = cmc_idpram_get_mask_res_ack, - .get_mask_send = cmc_idpram_get_mask_send, - - .dp_base = NULL, - .dp_size = 0, - .dp_type = CP_IDPRAM, - .aligned = 1, - - .dpram_irq = CMC_IDPRAM_INT_IRQ_00, - .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING), - .dpram_irq_name = "CMC221_IDPRAM_IRQ", - .dpram_wlock_name = "CMC221_IDPRAM_WLOCK", - - .max_ipc_dev = MAX_CMC_IDPRAM_IPC_DEV, -}; - -/* -** UMTS target platform data -*/ static struct modem_io_t umts_io_devices[] = { [0] = { .name = "umts_boot0", @@ -331,7 +72,7 @@ static struct modem_io_t umts_io_devices[] = { .links = LINKTYPE(LINKDEV_DPRAM), }, [3] = { - .name = "lte_multipdp", + .name = "multipdp", .id = 0, .format = IPC_MULTI_RAW, .io_type = IODEV_DUMMY, @@ -392,14 +133,15 @@ static struct modem_io_t umts_io_devices[] = { .links = LINKTYPE(LINKDEV_DPRAM), }, [11] = { - .name = "umts_loopback_ap2cp", + .name = "umts_loopback_cp2ap", .id = 30, .format = IPC_RAW, .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), + .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), + .tx_link = LINKDEV_DPRAM, }, [12] = { - .name = "umts_loopback_cp2ap", + .name = "umts_loopback_ap2cp", .id = 31, .format = IPC_RAW, .io_type = IODEV_MISC, @@ -413,6 +155,13 @@ static struct modem_io_t umts_io_devices[] = { .links = LINKTYPE(LINKDEV_DPRAM), }, [14] = { + .name = "umts_log", + .id = 0, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [15] = { .name = "lte_ipc0", .id = 235, .format = IPC_FMT, @@ -421,28 +170,229 @@ static struct modem_io_t umts_io_devices[] = { }, }; -static int exynos_cpu_frequency_lock(void); -static int exynos_cpu_frequency_unlock(void); +static struct modem_io_t cdma_io_devices[] = { + [0] = { + .name = "cdma_boot0", + .id = 0, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [1] = { + .name = "cdma_ipc0", + .id = 235, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [2] = { + .name = "cdma_rfs0", + .id = 245, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [3] = { + .name = "cdma_multipdp", + .id = 0, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [4] = { + .name = "cdma_rmnet0", + .id = 10, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [5] = { + .name = "cdma_rmnet1", + .id = 11, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [6] = { + .name = "cdma_rmnet2", + .id = 12, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [7] = { + .name = "cdma_rmnet3", + .id = 13, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [8] = { + .name = "cdma_rmnet4", + .id = 7, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [9] = { + .name = "cdma_rmnet5", /* DM Port IO device */ + .id = 26, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [10] = { + .name = "cdma_rmnet6", /* AT CMD IO device */ + .id = 17, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [11] = { + .name = "cdma_ramdump0", + .id = 0, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [12] = { + .name = "cdma_cplog", + .id = 29, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, +}; -static struct modemlink_pm_data umts_link_pm_data = { - .name = "umts_link_pm", +/* +** addr_bits: 14 bits (14 bits for CMC221 vs. 13 bits for CBP72) +** :: CMC221 14 bits = 13 bits (8K words) + 1 bit (SFR) +** data_bits: 16 bits +** byte_acc: CMC221 N/A, CBP72 Available +*/ +static struct sromc_bus_cfg c1lgt_sromc_bus_cfg = { + .addr_bits = 14, + .data_bits = 16, + .byte_acc = 1, +}; - .gpio_link_enable = 0, - .gpio_link_active = GPIO_ACTIVE_STATE, - .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, - .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, +/* For CMC221 IDPRAM (Internal DPRAM) */ +#define CMC_IDPRAM_SIZE DPRAM_SIZE_16KB + +/* For CMC221 SFR for IDPRAM */ +#define CMC_INT2CP_REG 0x10 /* Interrupt to CP */ +#define CMC_INT2AP_REG 0x50 +#define CMC_CLR_INT_REG 0x28 /* Clear Interrupt to AP */ +#define CMC_RESET_REG 0x3C +#define CMC_PUT_REG 0x40 /* AP->CP reg for hostbooting */ +#define CMC_GET_REG 0x50 /* CP->AP reg for hostbooting */ + +struct cmc22x_idpram_sfr { + u16 __iomem *int2cp; + u16 __iomem *int2ap; + u16 __iomem *clr_int2ap; + u16 __iomem *reset; + u16 __iomem *msg2cp; + u16 __iomem *msg2ap; +}; - .port_enable = host_port_enable, /* - .link_reconnect = umts_link_reconnect, +** Function prototypes for CMC221 */ - .freqlock = ATOMIC_INIT(0), - .cpufreq_lock = exynos_cpu_frequency_lock, - .cpufreq_unlock = exynos_cpu_frequency_unlock, +static void cmc_idpram_reset(void); +static void cmc_idpram_clr_intr(void); +static u16 cmc_idpram_recv_intr(void); +static void cmc_idpram_send_intr(u16 irq_mask); +static u16 cmc_idpram_recv_msg(void); +static void cmc_idpram_send_msg(u16 msg); - .autosuspend_delay_ms = 2000, +static int cmc_idpram_wakeup(void); +static void cmc_idpram_sleep(void); - .has_usbhub = true, +static void cmc_idpram_setup_speed(enum dpram_speed speed); + +/* +** Static variables for CMC221 +*/ +static struct sromc_bank_cfg cmc_idpram_bank_cfg = { + .csn = 0, + .attr = SROMC_DATA_16, + .size = CMC_IDPRAM_SIZE, + .addr = SROM_CS0_BASE, +}; + +static struct sromc_timing_cfg cmc_idpram_timing_cfg[] = { + [DPRAM_SPEED_LOW] = { + /* CP 33 MHz clk, 315 ns (63 cycles) with 200 MHz INT clk */ + .tacs = 0x0F << 28, + .tcos = 0x0F << 24, + .tacc = 0x1F << 16, + .tcoh = 0x01 << 12, + .tcah = 0x00 << 8, + .tacp = 0x00 << 4, + .pmc = 0x00 << 0, + }, + [DPRAM_SPEED_MID] = { + /* CP 66 MHz clk, 160 ns (32 cycles) with 200 MHz INT clk */ + .tacs = 0x01 << 28, + .tcos = 0x01 << 24, + .tacc = 0x1C << 16, + .tcoh = 0x01 << 12, + .tcah = 0x00 << 8, + .tacp = 0x00 << 4, + .pmc = 0x00 << 0, + }, + [DPRAM_SPEED_HIGH] = { + /* CP 133 MHz clk, 80 ns (16 cycles) with 200 MHz INT clk */ + .tacs = 0x01 << 28, + .tcos = 0x01 << 24, + .tacc = 0x0C << 16, + .tcoh = 0x01 << 12, + .tcah = 0x00 << 8, + .tacp = 0x00 << 4, + .pmc = 0x00 << 0, + }, +}; + +static struct modemlink_dpram_control cmc_idpram_ctrl = { + .reset = cmc_idpram_reset, + .clear_intr = cmc_idpram_clr_intr, + .recv_intr = cmc_idpram_recv_intr, + .send_intr = cmc_idpram_send_intr, + .recv_msg = cmc_idpram_recv_msg, + .send_msg = cmc_idpram_send_msg, + + .wakeup = cmc_idpram_wakeup, + .sleep = cmc_idpram_sleep, + + .setup_speed = cmc_idpram_setup_speed, + + .dp_type = CP_IDPRAM, + + .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING), +}; + +static struct cmc22x_idpram_sfr cmc_idpram_sfr; + +static struct resource umts_modem_res[] = { + [RES_CP_ACTIVE_IRQ_ID] = { + .name = "cp_active_irq", + .start = LTE_ACTIVE_IRQ, + .end = LTE_ACTIVE_IRQ, + .flags = IORESOURCE_IRQ, + }, + [RES_DPRAM_MEM_ID] = { + .name = "dpram_base", + .start = SROM_CS0_BASE, + .end = SROM_CS0_BASE + (CMC_IDPRAM_SIZE - 1), + .flags = IORESOURCE_MEM, + }, + [RES_DPRAM_IRQ_ID] = { + .name = "dpram_irq", + .start = CMC_IDPRAM_INT_IRQ_01, + .end = CMC_IDPRAM_INT_IRQ_01, + .flags = IORESOURCE_IRQ, + }, }; static struct modem_data umts_modem_data = { @@ -451,14 +401,18 @@ static struct modem_data umts_modem_data = { .gpio_cp_on = CP_CMC221_PMIC_PWRON, .gpio_cp_reset = CP_CMC221_CPU_RST, .gpio_phone_active = GPIO_LTE_ACTIVE, +#if 1 + .gpio_pda_active = GPIO_PDA_ACTIVE, +#endif - .gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00, + .gpio_dpram_int = GPIO_CMC_IDPRAM_INT_01, .gpio_dpram_status = GPIO_CMC_IDPRAM_STATUS, .gpio_dpram_wakeup = GPIO_CMC_IDPRAM_WAKEUP, .gpio_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP, .gpio_host_active = GPIO_ACTIVE_STATE, .gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP, + .gpio_dynamic_switching = GPIO_AP2CMC_INT2, .modem_net = UMTS_NETWORK, .modem_type = SEC_CMC221, @@ -469,23 +423,12 @@ static struct modem_data umts_modem_data = { .num_iodevs = ARRAY_SIZE(umts_io_devices), .iodevs = umts_io_devices, - .link_pm_data = &umts_link_pm_data, - .use_handover = true, .ipc_version = SIPC_VER_50, .use_mif_log = true, }; -static struct resource umts_modem_res[] = { - [0] = { - .name = "cp_active_irq", - .start = LTE_ACTIVE_IRQ, - .end = LTE_ACTIVE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - static struct platform_device umts_modem = { .name = "mif_sipc5", .id = 1, @@ -496,33 +439,38 @@ static struct platform_device umts_modem = { }, }; -#define HUB_STATE_OFF 0 -void set_hsic_lpa_states(int states) +/* +** Function definitions +*/ +static void cmc_idpram_reset(void) { - int val = gpio_get_value(umts_modem_data.gpio_cp_reset); + iowrite16(1, cmc_idpram_sfr.reset); +} - mif_trace("\n"); +static void cmc_idpram_clr_intr(void) +{ + iowrite16(0xFFFF, cmc_idpram_sfr.clr_int2ap); + iowrite16(0, cmc_idpram_sfr.int2ap); +} - if (val && states == STATE_HSIC_LPA_ENTER) { - mif_info("usb3503: hub off - lpa\n"); - host_port_enable(2, 0); - *(umts_link_pm_data.p_hub_status) = HUB_STATE_OFF; - } +static u16 cmc_idpram_recv_intr(void) +{ + return ioread16(cmc_idpram_sfr.int2ap); } -int get_cp_active_state(void) +static void cmc_idpram_send_intr(u16 irq_mask) { - return gpio_get_value(umts_modem_data.gpio_phone_active); + iowrite16(irq_mask, cmc_idpram_sfr.int2cp); } -static void cmc_idpram_reset(void) +static u16 cmc_idpram_recv_msg(void) { - iowrite16(1, cmc_sfr.reset); + return ioread16(cmc_idpram_sfr.msg2ap); } -static void cmc_idpram_setup_speed(enum dpram_speed speed) +static void cmc_idpram_send_msg(u16 msg) { - setup_dpram_speed(cmc_idpram_cfg.csn, &cmc_idpram_access_cfg[speed]); + iowrite16(msg, cmc_idpram_sfr.msg2cp); } static int cmc_idpram_wakeup(void) @@ -533,14 +481,18 @@ static int cmc_idpram_wakeup(void) while (!gpio_get_value(umts_modem_data.gpio_dpram_status)) { if (cnt++ > 10) { - mif_err("ERR: gpio_dpram_status == 0\n"); - return -EAGAIN; + if (in_irq()) + mif_err("ERR! gpio_dpram_status == 0 in IRQ\n"); + else + mif_err("ERR! gpio_dpram_status == 0\n"); + return -EACCES; } + mif_info("gpio_dpram_status == 0 (cnt %d)\n", cnt); if (in_interrupt()) - mdelay(1); + udelay(1000); else - msleep_interruptible(1); + usleep_range(1000, 2000); } return 0; @@ -551,205 +503,67 @@ static void cmc_idpram_sleep(void) gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 0); } -static void cmc_idpram_clr_intr(void) -{ - iowrite16(0xFFFF, cmc_sfr.clr_int2ap); - iowrite16(0, cmc_sfr.int2ap); -} - -static u16 cmc_idpram_recv_intr(void) -{ - return ioread16(cmc_sfr.int2ap); -} - -static void cmc_idpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, cmc_sfr.int2cp); -} - -static u16 cmc_idpram_recv_msg(void) -{ - return ioread16(cmc_sfr.msg2ap); -} - -static void cmc_idpram_send_msg(u16 msg) -{ - iowrite16(msg, cmc_sfr.msg2cp); -} - -static u16 cmc_idpram_get_magic(void) -{ - return ioread16(cmc_ipc_map.magic); -} - -static void cmc_idpram_set_magic(u16 value) -{ - iowrite16(value, cmc_ipc_map.magic); -} - -static u16 cmc_idpram_get_access(void) -{ - return ioread16(cmc_ipc_map.access); -} - -static void cmc_idpram_set_access(u16 value) -{ - iowrite16(value, cmc_ipc_map.access); -} - -static u32 cmc_idpram_get_tx_head(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].txq.head); -} - -static u32 cmc_idpram_get_tx_tail(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].txq.tail); -} - -static void cmc_idpram_set_tx_head(int dev_id, u32 head) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head); - - do { - /* Check head value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].txq.head); - if (val == head) - break; - - mif_err("ERR: txq.head(%d) != head(%d)\n", val, head); - - /* Write head value again */ - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head); - } while (cnt--); -} - -static void cmc_idpram_set_tx_tail(int dev_id, u32 tail) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail); - - do { - /* Check tail value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].txq.tail); - if (val == tail) - break; - - mif_err("ERR: txq.tail(%d) != tail(%d)\n", val, tail); - - /* Write tail value again */ - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail); - } while (cnt--); -} - -static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].txq.buff; -} - -static u32 cmc_idpram_get_tx_buff_size(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].txq.size; -} - -static u32 cmc_idpram_get_rx_head(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].rxq.head); -} - -static u32 cmc_idpram_get_rx_tail(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].rxq.tail); -} - -static void cmc_idpram_set_rx_head(int dev_id, u32 head) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head); - - do { - /* Check head value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].rxq.head); - if (val == head) - break; - - mif_err("ERR: rxq.head(%d) != head(%d)\n", val, head); - - /* Write head value again */ - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head); - } while (cnt--); -} - -static void cmc_idpram_set_rx_tail(int dev_id, u32 tail) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail); - - do { - /* Check tail value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].rxq.tail); - if (val == tail) - break; - - mif_err("ERR: rxq.tail(%d) != tail(%d)\n", val, tail); - - /* Write tail value again */ - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail); - } while (cnt--); -} - -static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id) +static void cmc_idpram_setup_speed(enum dpram_speed speed) { - return cmc_ipc_map.dev[dev_id].rxq.buff; + sromc_config_access_timing(cmc_idpram_bank_cfg.csn, + &cmc_idpram_timing_cfg[speed]); } -static u32 cmc_idpram_get_rx_buff_size(int dev_id) +static u8 *cmc_idpram_remap_sfr_region(struct sromc_bank_cfg *cfg) { - return cmc_ipc_map.dev[dev_id].rxq.size; -} + int dp_addr = cfg->addr + cfg->size; + int dp_size = cfg->size; + u8 __iomem *sfr_base; -static u16 cmc_idpram_get_mask_req_ack(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].mask_req_ack; -} + /* Remap DPRAM SFR region */ + sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); + if (!sfr_base) { + mif_err("ERR: ioremap_nocache fail\n"); + return NULL; + } -static u16 cmc_idpram_get_mask_res_ack(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].mask_res_ack; -} + cmc_idpram_sfr.int2cp = (u16 __iomem *)(sfr_base + CMC_INT2CP_REG); + cmc_idpram_sfr.int2ap = (u16 __iomem *)(sfr_base + CMC_INT2AP_REG); + cmc_idpram_sfr.clr_int2ap = (u16 __iomem *)(sfr_base + CMC_CLR_INT_REG); + cmc_idpram_sfr.reset = (u16 __iomem *)(sfr_base + CMC_RESET_REG); + cmc_idpram_sfr.msg2cp = (u16 __iomem *)(sfr_base + CMC_PUT_REG); + cmc_idpram_sfr.msg2ap = (u16 __iomem *)(sfr_base + CMC_GET_REG); -static u16 cmc_idpram_get_mask_send(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].mask_send; + return sfr_base; } /* Set dynamic environment for a modem */ static void setup_umts_modem_env(void) { - /* - ** Config DPRAM control structure - */ - if (system_rev == 1 || system_rev >= 4) - cmc_idpram_cfg.csn = 0; - else - cmc_idpram_cfg.csn = 1; + unsigned int addr; + unsigned int end; - cmc_idpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cmc_idpram_cfg.csn); - cmc_idpram_cfg.end = cmc_idpram_cfg.addr + cmc_idpram_cfg.size - 1; + /* Config DPRAM control structure */ + if (system_rev == 1 || system_rev >= 4) { + cmc_idpram_bank_cfg.csn = 0; + cmc_idpram_bank_cfg.addr = SROM_CS0_BASE; + } else { + cmc_idpram_bank_cfg.csn = 1; + cmc_idpram_bank_cfg.addr = SROM_CS1_BASE; + } + + addr = cmc_idpram_bank_cfg.addr; + end = addr + cmc_idpram_bank_cfg.size - 1; + umts_modem_res[RES_DPRAM_MEM_ID].start = addr; + umts_modem_res[RES_DPRAM_MEM_ID].end = end; if (system_rev == 1 || system_rev >= 4) { - umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_01; - cmc_idpram_ctrl.dpram_irq = CMC_IDPRAM_INT_IRQ_01; + umts_modem_res[RES_DPRAM_IRQ_ID].start = CMC_IDPRAM_INT_IRQ_01; + umts_modem_res[RES_DPRAM_IRQ_ID].end = CMC_IDPRAM_INT_IRQ_01; + } else { + umts_modem_res[RES_DPRAM_IRQ_ID].start = CMC_IDPRAM_INT_IRQ_00; + umts_modem_res[RES_DPRAM_IRQ_ID].end = CMC_IDPRAM_INT_IRQ_00; } + + if (system_rev == 1 || system_rev >= 4) + umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_01; + else + umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00; } static void config_umts_modem_gpio(void) @@ -765,6 +579,8 @@ static void config_umts_modem_gpio(void) unsigned gpio_dpram_int = umts_modem_data.gpio_dpram_int; unsigned gpio_dpram_status = umts_modem_data.gpio_dpram_status; unsigned gpio_dpram_wakeup = umts_modem_data.gpio_dpram_wakeup; + unsigned gpio_dynamic_switching = + umts_modem_data.gpio_dynamic_switching; if (gpio_cp_on) { err = gpio_request(gpio_cp_on, "CMC_ON"); @@ -877,334 +693,233 @@ static void config_umts_modem_gpio(void) s3c_gpio_setpull(gpio_dpram_wakeup, S3C_GPIO_PULL_NONE); } } -} - -static u8 *cmc_idpram_remap_mem_region(struct sromc_cfg *cfg) -{ - int dp_addr = cfg->addr; - int dp_size = cfg->size; - u8 __iomem *dp_base; - struct dpram_ipc_cfg *ipc_map; - struct dpram_ipc_device *dev; - - /* Remap DPRAM memory region */ - dp_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); - if (!dp_base) { - mif_err("ERR: ioremap_nocache for dp_base fail\n"); - return NULL; - } - mif_err("DPRAM VA=0x%08X\n", (int)dp_base); - /* Remap DPRAM SFR region */ - dp_addr += dp_size; - cmc_sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); - if (cmc_sfr_base == NULL) { - iounmap(dp_base); - mif_err("ERR: ioremap_nocache for cmc_sfr_base fail\n"); - return NULL; + if (gpio_dynamic_switching) { + err = gpio_request(gpio_dynamic_switching, "DYNAMIC_SWITCHING"); + if (err) { + mif_err("ERR: fail to request gpio %s\n", + "DYNAMIC_SWITCHING\n"); + } else { + gpio_direction_input(gpio_dynamic_switching); + s3c_gpio_setpull(gpio_dynamic_switching, + S3C_GPIO_PULL_DOWN); + } } - cmc_sfr.int2cp = (u16 __iomem *)(cmc_sfr_base + CMC_INT2CP_REG); - cmc_sfr.int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_INT2AP_REG); - cmc_sfr.clr_int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_CLR_INT_REG); - cmc_sfr.reset = (u16 __iomem *)(cmc_sfr_base + CMC_RESET_REG); - cmc_sfr.msg2cp = (u16 __iomem *)(cmc_sfr_base + CMC_PUT_REG); - cmc_sfr.msg2ap = (u16 __iomem *)(cmc_sfr_base + CMC_GET_REG); + mif_info("done\n"); +} - cmc_idpram_ctrl.dp_base = (u8 __iomem *)dp_base; - cmc_idpram_ctrl.dp_size = dp_size; +static int host_port_enable(int port, int enable); +static int exynos_frequency_lock(struct device *dev); +static int exynos_frequency_unlock(struct device *dev); - /* Map for IPC */ - ipc_map = (struct dpram_ipc_cfg *)dp_base; +static struct modemlink_pm_data umts_link_pm_data = { + .name = "umts_link_pm", - /* Magic code and access enable fields */ - cmc_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; - cmc_ipc_map.access = (u16 __iomem *)&ipc_map->access; + .gpio_link_enable = 0, + .gpio_link_active = GPIO_ACTIVE_STATE, + .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, + .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, - /* FMT */ - dev = &cmc_ipc_map.dev[IPC_FMT]; + .port_enable = host_port_enable, +/* + .link_reconnect = umts_link_reconnect, +*/ + .freqlock = ATOMIC_INIT(0), + .freq_lock = exynos_frequency_lock, + .freq_unlock = exynos_frequency_unlock, - strcpy(dev->name, "FMT"); - dev->id = IPC_FMT; + .autosuspend_delay_ms = 2000, - dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; - dev->txq.size = DP_FMT_TX_BUFF_SZ; + .has_usbhub = true, +}; - dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; - dev->rxq.size = DP_FMT_RX_BUFF_SZ; +static struct modemlink_pm_link_activectl active_ctl; - dev->mask_req_ack = INT_MASK_REQ_ACK_F; - dev->mask_res_ack = INT_MASK_RES_ACK_F; - dev->mask_send = INT_MASK_SEND_F; +#ifdef CONFIG_EXYNOS4_CPUFREQ +static int exynos_frequency_lock(struct device *dev) +{ + unsigned int level, cpufreq = 600; /* 200 ~ 1400 */ + unsigned int busfreq = 400200; /* 100100 ~ 400200 */ + int ret = 0; + struct device *busdev = dev_get("exynos-busfreq"); - /* RAW */ - dev = &cmc_ipc_map.dev[IPC_RAW]; + if (atomic_read(&umts_link_pm_data.freqlock) == 0) { + /* cpu frequency lock */ + ret = exynos_cpufreq_get_level(cpufreq * 1000, &level); + if (ret < 0) { + mif_err("ERR: exynos_cpufreq_get_level fail: %d\n", + ret); + goto exit; + } - strcpy(dev->name, "RAW"); - dev->id = IPC_RAW; + ret = exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level); + if (ret < 0) { + mif_err("ERR: exynos_cpufreq_lock fail: %d\n", ret); + goto exit; + } - dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; - dev->txq.size = DP_RAW_TX_BUFF_SZ; + /* bus frequncy lock */ + if (!busdev) { + mif_err("ERR: busdev is not exist\n"); + ret = -ENODEV; + goto exit; + } - dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; - dev->rxq.size = DP_RAW_RX_BUFF_SZ; + ret = dev_lock(busdev, dev, busfreq); + if (ret < 0) { + mif_err("ERR: dev_lock error: %d\n", ret); + goto exit; + } - dev->mask_req_ack = INT_MASK_REQ_ACK_R; - dev->mask_res_ack = INT_MASK_RES_ACK_R; - dev->mask_send = INT_MASK_SEND_R; + /* lock minimum number of cpu cores */ + cpufreq_pegasusq_min_cpu_lock(2); - return dp_base; + atomic_set(&umts_link_pm_data.freqlock, 1); + mif_debug("level=%d, cpufreq=%d MHz, busfreq=%06d\n", + level, cpufreq, busfreq); + } +exit: + return ret; } -#endif -#ifdef CONFIG_CDMA_MODEM_CBP72 -static struct sromc_cfg cbp_edpram_cfg = { - .attr = SROMC_DATA_16 | SROMC_BYTE_EN, - .size = CBP_EDPRAM_SIZE, -}; +static int exynos_frequency_unlock(struct device *dev) +{ + int ret = 0; + struct device *busdev = dev_get("exynos-busfreq"); -static struct sromc_access_cfg cbp_edpram_access_cfg[] = { - [DPRAM_SPEED_LOW] = { - .tacs = 0x00 << 28, - .tcos = 0x00 << 24, - .tacc = 0x0F << 16, - .tcoh = 0x00 << 12, - .tcah = 0x00 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, -}; + if (atomic_read(&umts_link_pm_data.freqlock) == 1) { + /* cpu frequency unlock */ + exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF); -/* - magic_code + - access_enable + - fmt_tx_head + fmt_tx_tail + fmt_tx_buff + - raw_tx_head + raw_tx_tail + raw_tx_buff + - fmt_rx_head + fmt_rx_tail + fmt_rx_buff + - raw_rx_head + raw_rx_tail + raw_rx_buff + - mbx_cp2ap + - mbx_ap2cp - = 2 + - 2 + - 2 + 2 + 1336 + - 2 + 2 + 4564 + - 2 + 2 + 1336 + - 2 + 2 + 9124 + - 2 + - 2 - = 16384 -*/ + /* bus frequency unlock */ + ret = dev_unlock(busdev, dev); + if (ret < 0) { + mif_err("ERR: dev_unlock error: %d\n", ret); + goto exit; + } -#define CBP_DP_FMT_TX_BUFF_SZ 1336 -#define CBP_DP_RAW_TX_BUFF_SZ 4564 -#define CBP_DP_FMT_RX_BUFF_SZ 1336 -#define CBP_DP_RAW_RX_BUFF_SZ 9124 + /* unlock minimum number of cpu cores */ + cpufreq_pegasusq_min_cpu_unlock(); -#define MAX_CBP_EDPRAM_IPC_DEV (IPC_RAW + 1) /* FMT, RAW */ + atomic_set(&umts_link_pm_data.freqlock, 0); + mif_debug("success\n"); + } +exit: + return ret; +} +#else +static int exynos_frequency_lock(void) +{ + return 0; +} -struct cbp_edpram_ipc_cfg { - u16 magic; - u16 access; +static int exynos_frequency_unlock(void) +{ + return 0; +} +#endif - u16 fmt_tx_head; - u16 fmt_tx_tail; - u8 fmt_tx_buff[CBP_DP_FMT_TX_BUFF_SZ]; +bool modem_using_hub(void) +{ + return umts_link_pm_data.has_usbhub; +} - u16 raw_tx_head; - u16 raw_tx_tail; - u8 raw_tx_buff[CBP_DP_RAW_TX_BUFF_SZ]; +void set_slave_wake(void) +{ + int slavewake = umts_link_pm_data.gpio_link_slavewake; - u16 fmt_rx_head; - u16 fmt_rx_tail; - u8 fmt_rx_buff[CBP_DP_FMT_RX_BUFF_SZ]; + if (gpio_get_value(slavewake)) { + gpio_direction_output(slavewake, 0); + mif_info("> S-WUP 0\n"); + mdelay(10); + } + gpio_direction_output(slavewake, 1); + mif_info("> S-WUP 1\n"); +} - u16 raw_rx_head; - u16 raw_rx_tail; - u8 raw_rx_buff[CBP_DP_RAW_RX_BUFF_SZ]; +void set_hsic_lpa_states(int states) +{ + int val = gpio_get_value(umts_modem_data.gpio_cp_reset); + struct modemlink_pm_data *pm_data = &umts_link_pm_data; + + mif_trace("\n"); + + if (val) { + switch (states) { + case STATE_HSIC_LPA_ENTER: + mif_info("lpa_enter\n"); + /* gpio_link_active == gpio_host_active in C1 */ + gpio_set_value(umts_modem_data.gpio_host_active, 0); + mif_info("> H-ACT %d\n", 0); + if (pm_data->hub_standby && pm_data->hub_pm_data) + pm_data->hub_standby(pm_data->hub_pm_data); + break; + case STATE_HSIC_LPA_WAKE: + mif_info("lpa_wake\n"); + gpio_set_value(umts_modem_data.gpio_host_active, 1); + mif_info("> H-ACT %d\n", 1); + break; + case STATE_HSIC_LPA_PHY_INIT: + mif_info("lpa_phy_init\n"); + if (!modem_using_hub() && active_ctl.gpio_initialized) + set_slave_wake(); + break; + } + } +} - u16 mbx_cp2ap; - u16 mbx_ap2cp; +int get_cp_active_state(void) +{ + return gpio_get_value(umts_modem_data.gpio_phone_active); +} + +/* For CBP7.2 EDPRAM (External DPRAM) */ +#define CBP_EDPRAM_SIZE DPRAM_SIZE_16KB + +/* +** Static variables for CBP72 +*/ +static struct sromc_bank_cfg cbp_edpram_bank_cfg = { + .csn = 1, + .attr = SROMC_DATA_16 | SROMC_BYTE_EN, + .size = CBP_EDPRAM_SIZE, + .addr = SROM_CS1_BASE, }; -static struct dpram_ipc_map cbp_ipc_map; - -static void cbp_edpram_reset(void); -static void cbp_edpram_clr_intr(void); -static u16 cbp_edpram_recv_intr(void); -static void cbp_edpram_send_intr(u16 irq_mask); -static u16 cbp_edpram_recv_msg(void); -static void cbp_edpram_send_msg(u16 msg); - -static u16 cbp_edpram_get_magic(void); -static void cbp_edpram_set_magic(u16 value); -static u16 cbp_edpram_get_access(void); -static void cbp_edpram_set_access(u16 value); - -static u32 cbp_edpram_get_tx_head(int dev_id); -static u32 cbp_edpram_get_tx_tail(int dev_id); -static void cbp_edpram_set_tx_head(int dev_id, u32 head); -static void cbp_edpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id); -static u32 cbp_edpram_get_tx_buff_size(int dev_id); - -static u32 cbp_edpram_get_rx_head(int dev_id); -static u32 cbp_edpram_get_rx_tail(int dev_id); -static void cbp_edpram_set_rx_head(int dev_id, u32 head); -static void cbp_edpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id); -static u32 cbp_edpram_get_rx_buff_size(int dev_id); - -static u16 cbp_edpram_get_mask_req_ack(int dev_id); -static u16 cbp_edpram_get_mask_res_ack(int dev_id); -static u16 cbp_edpram_get_mask_send(int dev_id); +static struct sromc_timing_cfg cbp_edpram_timing_cfg = { + .tacs = 0x00 << 28, + .tcos = 0x00 << 24, + .tacc = 0x0F << 16, + .tcoh = 0x00 << 12, + .tcah = 0x00 << 8, + .tacp = 0x00 << 4, + .pmc = 0x00 << 0, +}; static struct modemlink_dpram_control cbp_edpram_ctrl = { - .reset = cbp_edpram_reset, - - .clear_intr = cbp_edpram_clr_intr, - .recv_intr = cbp_edpram_recv_intr, - .send_intr = cbp_edpram_send_intr, - .recv_msg = cbp_edpram_recv_msg, - .send_msg = cbp_edpram_send_msg, - - .get_magic = cbp_edpram_get_magic, - .set_magic = cbp_edpram_set_magic, - .get_access = cbp_edpram_get_access, - .set_access = cbp_edpram_set_access, - - .get_tx_head = cbp_edpram_get_tx_head, - .get_tx_tail = cbp_edpram_get_tx_tail, - .set_tx_head = cbp_edpram_set_tx_head, - .set_tx_tail = cbp_edpram_set_tx_tail, - .get_tx_buff = cbp_edpram_get_tx_buff, - .get_tx_buff_size = cbp_edpram_get_tx_buff_size, - - .get_rx_head = cbp_edpram_get_rx_head, - .get_rx_tail = cbp_edpram_get_rx_tail, - .set_rx_head = cbp_edpram_set_rx_head, - .set_rx_tail = cbp_edpram_set_rx_tail, - .get_rx_buff = cbp_edpram_get_rx_buff, - .get_rx_buff_size = cbp_edpram_get_rx_buff_size, - - .get_mask_req_ack = cbp_edpram_get_mask_req_ack, - .get_mask_res_ack = cbp_edpram_get_mask_res_ack, - .get_mask_send = cbp_edpram_get_mask_send, - - .dp_base = NULL, - .dp_size = 0, .dp_type = EXT_DPRAM, - .aligned = 1, - - .dpram_irq = CBP_DPRAM_INT_IRQ_00, - .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_FALLING), - .dpram_irq_name = "CBP72_EDPRAM_IRQ", - .dpram_wlock_name = "CBP72_EDPRAM_WLOCK", - - .max_ipc_dev = MAX_CBP_EDPRAM_IPC_DEV, + .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_FALLING), }; -/* -** CDMA target platform data -*/ -static struct modem_io_t cdma_io_devices[] = { - [0] = { - .name = "cdma_boot0", - .id = 0, - .format = IPC_BOOT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [1] = { - .name = "cdma_ipc0", - .id = 235, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [2] = { - .name = "cdma_rfs0", - .id = 245, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [3] = { - .name = "cdma_multipdp", - .id = 0, - .format = IPC_MULTI_RAW, - .io_type = IODEV_DUMMY, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [4] = { - .name = "cdma_rmnet0", - .id = 10, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [5] = { - .name = "cdma_rmnet1", - .id = 11, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [6] = { - .name = "cdma_rmnet2", - .id = 12, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [7] = { - .name = "cdma_rmnet3", - .id = 13, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [8] = { - .name = "cdma_rmnet4", - .id = 7, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [9] = { - .name = "cdma_rmnet5", /* DM Port IO device */ - .id = 26, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [10] = { - .name = "cdma_rmnet6", /* AT CMD IO device */ - .id = 17, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), +static struct resource cdma_modem_res[] = { + [RES_CP_ACTIVE_IRQ_ID] = { + .name = "cp_active_irq", + .start = CBP_PHONE_ACTIVE_IRQ, + .end = CBP_PHONE_ACTIVE_IRQ, + .flags = IORESOURCE_IRQ, }, - [11] = { - .name = "cdma_ramdump0", - .id = 0, - .format = IPC_RAMDUMP, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), + [RES_DPRAM_MEM_ID] = { + .name = "dpram_base", + .start = SROM_CS1_BASE, + .end = SROM_CS1_BASE + (CBP_EDPRAM_SIZE - 1), + .flags = IORESOURCE_MEM, }, - [12] = { - .name = "cdma_cplog", - .id = 29, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), + [RES_DPRAM_IRQ_ID] = { + .name = "dpram_irq", + .start = CBP_DPRAM_INT_IRQ_01, + .end = CBP_DPRAM_INT_IRQ_01, + .flags = IORESOURCE_IRQ, }, }; @@ -1217,7 +932,7 @@ static struct modem_data cdma_modem_data = { .gpio_pda_active = GPIO_PDA_ACTIVE, .gpio_phone_active = GPIO_CBP_PHONE_ACTIVE, - .gpio_dpram_int = GPIO_CBP_DPRAM_INT_00, + .gpio_dpram_int = GPIO_CBP_DPRAM_INT_01, .modem_net = CDMA_NETWORK, .modem_type = VIA_CBP72, @@ -1233,15 +948,6 @@ static struct modem_data cdma_modem_data = { .ipc_version = SIPC_VER_50, }; -static struct resource cdma_modem_res[] = { - [0] = { - .name = "cp_active_irq", - .start = CBP_PHONE_ACTIVE_IRQ, - .end = CBP_PHONE_ACTIVE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - static struct platform_device cdma_modem = { .name = "mif_sipc5", .id = 2, @@ -1252,149 +958,38 @@ static struct platform_device cdma_modem = { }, }; -static void cbp_edpram_reset(void) -{ - return; -} - -static void cbp_edpram_clr_intr(void) -{ - ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static u16 cbp_edpram_recv_intr(void) -{ - return ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static void cbp_edpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, cbp_ipc_map.mbx_ap2cp); -} - -static u16 cbp_edpram_recv_msg(void) -{ - return ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static void cbp_edpram_send_msg(u16 msg) -{ - iowrite16(msg, cbp_ipc_map.mbx_ap2cp); -} - -static u16 cbp_edpram_get_magic(void) -{ - return ioread16(cbp_ipc_map.magic); -} - -static void cbp_edpram_set_magic(u16 value) -{ - iowrite16(value, cbp_ipc_map.magic); -} - -static u16 cbp_edpram_get_access(void) -{ - return ioread16(cbp_ipc_map.access); -} - -static void cbp_edpram_set_access(u16 value) -{ - iowrite16(value, cbp_ipc_map.access); -} - -static u32 cbp_edpram_get_tx_head(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].txq.head); -} - -static u32 cbp_edpram_get_tx_tail(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].txq.tail); -} - -static void cbp_edpram_set_tx_head(int dev_id, u32 head) -{ - iowrite16((u16)head, cbp_ipc_map.dev[dev_id].txq.head); -} - -static void cbp_edpram_set_tx_tail(int dev_id, u32 tail) -{ - iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].txq.tail); -} - -static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].txq.buff; -} - -static u32 cbp_edpram_get_tx_buff_size(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].txq.size; -} - -static u32 cbp_edpram_get_rx_head(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].rxq.head); -} - -static u32 cbp_edpram_get_rx_tail(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].rxq.tail); -} - -static void cbp_edpram_set_rx_head(int dev_id, u32 head) -{ - return iowrite16((u16)head, cbp_ipc_map.dev[dev_id].rxq.head); -} - -static void cbp_edpram_set_rx_tail(int dev_id, u32 tail) -{ - return iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].rxq.tail); -} - -static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].rxq.buff; -} - -static u32 cbp_edpram_get_rx_buff_size(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].rxq.size; -} - -static u16 cbp_edpram_get_mask_req_ack(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_req_ack; -} - -static u16 cbp_edpram_get_mask_res_ack(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_res_ack; -} - -static u16 cbp_edpram_get_mask_send(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_send; -} - /* Set dynamic environment for a modem */ static void setup_cdma_modem_env(void) { - /* - ** Config DPRAM control structure - */ - if (system_rev == 1 || system_rev >= 4) - cbp_edpram_cfg.csn = 1; - else - cbp_edpram_cfg.csn = 0; + unsigned int addr; + unsigned int end; + + /* Config DPRAM control structure */ + if (system_rev == 1 || system_rev >= 4) { + cbp_edpram_bank_cfg.csn = 1; + cbp_edpram_bank_cfg.addr = SROM_CS1_BASE; + } else { + cbp_edpram_bank_cfg.csn = 0; + cbp_edpram_bank_cfg.addr = SROM_CS0_BASE; + } - cbp_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cbp_edpram_cfg.csn); - cbp_edpram_cfg.end = cbp_edpram_cfg.addr + cbp_edpram_cfg.size - 1; + addr = cbp_edpram_bank_cfg.addr; + end = addr + cbp_edpram_bank_cfg.size - 1; + cdma_modem_res[RES_DPRAM_MEM_ID].start = addr; + cdma_modem_res[RES_DPRAM_MEM_ID].end = end; if (system_rev == 1 || system_rev >= 4) { - cdma_modem_data.gpio_dpram_int = GPIO_CBP_DPRAM_INT_01; - cbp_edpram_ctrl.dpram_irq = CBP_DPRAM_INT_IRQ_01; + cdma_modem_res[RES_DPRAM_IRQ_ID].start = CBP_DPRAM_INT_IRQ_01; + cdma_modem_res[RES_DPRAM_IRQ_ID].end = CBP_DPRAM_INT_IRQ_01; + } else { + cdma_modem_res[RES_DPRAM_IRQ_ID].start = CBP_DPRAM_INT_IRQ_00; + cdma_modem_res[RES_DPRAM_IRQ_ID].end = CBP_DPRAM_INT_IRQ_00; } + + if (system_rev == 1 || system_rev >= 4) + cdma_modem_data.gpio_dpram_int = GPIO_CBP_DPRAM_INT_01; + else + cdma_modem_data.gpio_dpram_int = GPIO_CBP_DPRAM_INT_00; } static void config_cdma_modem_gpio(void) @@ -1486,308 +1081,40 @@ static void config_cdma_modem_gpio(void) /* set low unused gpios between AP and CP */ err = gpio_request(GPIO_FLM_RXD, "FLM_RXD"); - if (err) + if (err) { pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD", err); - else { + } else { gpio_direction_input(GPIO_FLM_RXD); s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(2)); } err = gpio_request(GPIO_FLM_TXD, "FLM_TXD"); - if (err) + if (err) { pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD", err); - else { + } else { gpio_direction_input(GPIO_FLM_TXD); s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(2)); } } -static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg) -{ - int dp_addr = 0; - int dp_size = 0; - u8 __iomem *dp_base = NULL; - struct cbp_edpram_ipc_cfg *ipc_map = NULL; - struct dpram_ipc_device *dev = NULL; - - dp_addr = cfg->addr; - dp_size = cfg->size; - dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size); - if (!dp_base) { - pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__); - return NULL; - } - pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base); - - cbp_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; - cbp_edpram_ctrl.dp_size = dp_size; - - /* Map for IPC */ - ipc_map = (struct cbp_edpram_ipc_cfg *)dp_base; - - /* Magic code and access enable fields */ - cbp_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; - cbp_ipc_map.access = (u16 __iomem *)&ipc_map->access; - - /* FMT */ - dev = &cbp_ipc_map.dev[IPC_FMT]; - - strcpy(dev->name, "FMT"); - dev->id = IPC_FMT; - - dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; - dev->txq.size = CBP_DP_FMT_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; - dev->rxq.size = CBP_DP_FMT_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_F; - dev->mask_res_ack = INT_MASK_RES_ACK_F; - dev->mask_send = INT_MASK_SEND_F; - - /* RAW */ - dev = &cbp_ipc_map.dev[IPC_RAW]; - - strcpy(dev->name, "RAW"); - dev->id = IPC_RAW; - - dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; - dev->txq.size = CBP_DP_RAW_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; - dev->rxq.size = CBP_DP_RAW_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_R; - dev->mask_res_ack = INT_MASK_RES_ACK_R; - dev->mask_send = INT_MASK_SEND_R; - - /* Mailboxes */ - cbp_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; - cbp_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; - - return dp_base; -} -#endif - -/** - * DPRAM GPIO settings - * - * SROM_NUM_ADDR_BITS value indicate the address line number or - * the mux/demux dpram type. if you want to set mux mode, define the - * SROM_NUM_ADDR_BITS to zero. - * - * for CMC22x - * CMC22x has 16KB + a SFR register address. - * It used 14 bits (13bits for 16KB word address and 1 bit for SFR - * register) - */ -static void config_dpram_port_gpio(void) -{ - int addr_bits = SROM_NUM_ADDR_BITS; - - mif_info("address line = %d bits\n", addr_bits); - - /* - ** Config DPRAM address/data GPIO pins - */ - - /* Set GPIO for address bus (13 ~ 14 bits) */ - switch (addr_bits) { - case 0: - break; - - case 13 ... 14: - s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_LOW, - EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_HIGH, - (addr_bits - EXYNOS4_GPIO_Y3_NR), S3C_GPIO_SFN(2)); - break; - - default: - mif_err("ERR: invalid addr_bits!!!\n"); - return; - } - - /* Set GPIO for data bus (16 bits) */ - s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_LOW, 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_HIGH, 8, S3C_GPIO_SFN(2)); - - /* Setup SROMC CSn pins */ - s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin((GPIO_DPRAM_CSN0 + 1), S3C_GPIO_SFN(2)); - - /* Config OEn, WEn */ - s3c_gpio_cfgpin(GPIO_DPRAM_REN, S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(GPIO_DPRAM_WEN, S3C_GPIO_SFN(2)); - - /* Config LBn, UBn */ - s3c_gpio_cfgpin(GPIO_DPRAM_LBN, S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(GPIO_DPRAM_UBN, S3C_GPIO_SFN(2)); -} - -static void init_sromc(void) -{ - struct clk *clk = NULL; - - /* SROMC clk enable */ - clk = clk_get(NULL, "sromc"); - if (!clk) { - mif_err("ERR: SROMC clock gate fail\n"); - return; - } - clk_enable(clk); -} - -static void setup_sromc -( - unsigned csn, - struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg -) -{ - unsigned bw = 0; /* Bus width and wait control */ - unsigned bc = 0; /* Vank control */ - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - - mif_err("SROMC settings for CS%d...\n", csn); - - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - mif_err("Old SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc); - - /* Set the BW control field for the CSn */ - bw &= ~(SROMC_MASK << (csn << 2)); - bw |= (cfg->attr << (csn << 2)); - writel(bw, S5P_SROM_BW); - - /* Set SROMC memory access timing for the CSn */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - - writel(bc, bank_sfr); - - /* Verify SROMC settings */ - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - mif_err("New SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc); -} - -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg) -{ - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - unsigned bc = 0; - - bc = __raw_readl(bank_sfr); - mif_info("Old CS%d setting = 0x%08X\n", csn, bc); - - /* SROMC memory access timing setting */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - writel(bc, bank_sfr); - - bc = __raw_readl(bank_sfr); - mif_info("New CS%d setting = 0x%08X\n", csn, bc); -} - -static int __init init_modem(void) -{ - struct sromc_cfg *cfg = NULL; - struct sromc_access_cfg *acc_cfg = NULL; - - mif_err("System Revision = %d\n", system_rev); - - setup_umts_modem_env(); - setup_cdma_modem_env(); - - config_dpram_port_gpio(); - - config_umts_modem_gpio(); - config_cdma_modem_gpio(); - - init_sromc(); - - cfg = &cmc_idpram_cfg; - acc_cfg = &cmc_idpram_access_cfg[DPRAM_SPEED_LOW]; - setup_sromc(cfg->csn, cfg, acc_cfg); - - cfg = &cbp_edpram_cfg; - acc_cfg = &cbp_edpram_access_cfg[DPRAM_SPEED_LOW]; - setup_sromc(cfg->csn, cfg, acc_cfg); - - if (!cmc_idpram_remap_mem_region(&cmc_idpram_cfg)) - return -1; - platform_device_register(&umts_modem); - - if (!cbp_edpram_remap_mem_region(&cbp_edpram_cfg)) - return -1; - platform_device_register(&cdma_modem); - - return 0; -} -late_initcall(init_modem); -/*device_initcall(init_modem);*/ - -#ifdef CONFIG_USBHUB_USB3503 static int (*usbhub_set_mode)(struct usb3503_hubctl *, int); static struct usb3503_hubctl *usbhub_ctl; -#ifdef CONFIG_EXYNOS4_CPUFREQ -static int exynos_cpu_frequency_lock(void) +void set_host_states(struct platform_device *pdev, int type) { - unsigned int level, freq = 700; - - if (atomic_read(&umts_link_pm_data.freqlock) == 0) { - if (exynos_cpufreq_get_level(freq * 1000, &level)) { - mif_err("ERR: exynos_cpufreq_get_level fail\n"); - return -EINVAL; - } - - if (exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level)) { - mif_err("ERR: exynos_cpufreq_lock fail\n"); - return -EINVAL; - } - - atomic_set(&umts_link_pm_data.freqlock, 1); - mif_debug("<%d> %d MHz\n", level, freq); - } - return 0; -} + if (modem_using_hub()) + return; -static int exynos_cpu_frequency_unlock(void) -{ - if (atomic_read(&umts_link_pm_data.freqlock) == 1) { - exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF); - atomic_set(&umts_link_pm_data.freqlock, 0); - mif_debug("\n"); + if (active_ctl.gpio_initialized) { + mif_err("%s: > H-ACT %d\n", pdev->name, type); + gpio_direction_output(umts_link_pm_data.gpio_link_active, type); + } else { + active_ctl.gpio_request_host_active = 1; } - return 0; -} -#else -static int exynos_cpu_frequency_lock(void) -{ - return 0; -} - -static int exynos_cpu_frequency_unlock(void) -{ - return 0; -} -#endif - -void set_host_states(struct platform_device *pdev, int type) -{ } static int usb3503_hub_handler(void (*set_mode)(void), void *ctl) @@ -1874,24 +1201,15 @@ static struct platform_device s3c_device_i2c20 = { .dev.platform_data = &i2c20_platdata, }; -static int __init init_usbhub(void) -{ - usb3503_hw_config(); - i2c_register_board_info(20, i2c_devs20_emul, - ARRAY_SIZE(i2c_devs20_emul)); - - platform_device_register(&s3c_device_i2c20); - return 0; -} - -device_initcall(init_usbhub); - static int host_port_enable(int port, int enable) { int err; mif_info("port(%d) control(%d)\n", port, enable); + if (!modem_using_hub()) + return 0; + if (enable) { err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB); if (err < 0) { @@ -1904,14 +1222,14 @@ static int host_port_enable(int port, int enable) goto exit; } } else { - err = s5p_ehci_port_control(&s5p_device_ehci, port, 0); + err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY); if (err < 0) { - mif_err("ERR: port(%d) enable fail\n", port); + mif_err("ERR: hub off fail\n"); goto exit; } - err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY); + err = s5p_ehci_port_control(&s5p_device_ehci, port, 0); if (err < 0) { - mif_err("ERR: hub off fail\n"); + mif_err("ERR: port(%d) enable fail\n", port); goto exit; } } @@ -1923,15 +1241,79 @@ static int host_port_enable(int port, int enable) exit: return err; } -#else -void set_host_states(struct platform_device *pdev, int type) + +static int __init init_usbhub(void) { - if (active_ctl.gpio_initialized) { - mif_err("<%s> Active States =%d, %s\n", pdev->name, type); - gpio_direction_output(umts_link_pm_data.gpio_link_active, type); - } else { - active_ctl.gpio_request_host_active = 1; - } + usb3503_hw_config(); + i2c_register_board_info(20, i2c_devs20_emul, + ARRAY_SIZE(i2c_devs20_emul)); + + platform_device_register(&s3c_device_i2c20); + return 0; } -#endif +device_initcall(init_usbhub); + +static int __init init_modem(void) +{ + struct sromc_bus_cfg *bus_cfg; + struct sromc_bank_cfg *bnk_cfg; + struct sromc_timing_cfg *tm_cfg; + + mif_err("System Revision = %d\n", system_rev); + + /* + ** Complete modem_data configuration including link_pm_data + */ + umts_modem_data.link_pm_data = &umts_link_pm_data, + setup_umts_modem_env(); + setup_cdma_modem_env(); + + /* + ** Configure GPIO pins for the modem + */ + config_umts_modem_gpio(); + config_cdma_modem_gpio(); + active_ctl.gpio_initialized = 1; + + /* + ** Configure SROM controller + */ + if (sromc_enable() < 0) + return -1; + + bus_cfg = &c1lgt_sromc_bus_cfg; + if (sromc_config_demux_gpio(bus_cfg) < 0) + return -1; + + bnk_cfg = &cmc_idpram_bank_cfg; + if (sromc_config_csn_gpio(bnk_cfg->csn) < 0) + return -1; + sromc_config_access_attr(bnk_cfg->csn, bnk_cfg->attr); + + tm_cfg = &cmc_idpram_timing_cfg[DPRAM_SPEED_LOW]; + sromc_config_access_timing(bnk_cfg->csn, tm_cfg); + + bnk_cfg = &cbp_edpram_bank_cfg; + if (sromc_config_csn_gpio(bnk_cfg->csn) < 0) + return -1; + sromc_config_access_attr(bnk_cfg->csn, bnk_cfg->attr); + + tm_cfg = &cbp_edpram_timing_cfg; + sromc_config_access_timing(bnk_cfg->csn, tm_cfg); + + /* + ** Remap SFR region for CMC22x IDPRAM + */ + if (!cmc_idpram_remap_sfr_region(&cmc_idpram_bank_cfg)) + return -1; + + /* + ** Register the modem devices + */ + platform_device_register(&umts_modem); + platform_device_register(&cdma_modem); + + return 0; +} +late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/board-c1vzw-modems.c b/arch/arm/mach-exynos/board-c1vzw-modems.c deleted file mode 100644 index 6eb0509..0000000 --- a/arch/arm/mach-exynos/board-c1vzw-modems.c +++ /dev/null @@ -1,1930 +0,0 @@ -/* linux/arch/arm/mach-xxxx/board-c1vzw-modems.c - * Copyright (C) 2010 Samsung Electronics. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/interrupt.h> -#include <linux/regulator/consumer.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/clk.h> - -/* inlcude platform specific file */ -#include <linux/platform_data/modem.h> -#include <mach/sec_modem.h> -#include <mach/gpio.h> -#include <mach/gpio-exynos4.h> -#include <plat/gpio-cfg.h> -#include <mach/regs-mem.h> -#include <plat/regs-srom.h> - -#ifdef CONFIG_USBHUB_USB3503 -#include <linux/i2c.h> -#include <linux/i2c-gpio.h> -#include <linux/platform_data/usb3503.h> -#include <mach/cpufreq.h> -#include <plat/usb-phy.h> -#endif -#include <plat/devs.h> -#include <plat/ehci.h> - -#define SROM_CS0_BASE 0x04000000 -#define SROM_WIDTH 0x01000000 -#define SROM_NUM_ADDR_BITS 14 - -/* For "bus width and wait control (BW)" register */ -enum sromc_attr { - SROMC_DATA_16 = 0x1, /* 16-bit data bus */ - SROMC_BYTE_ADDR = 0x2, /* Byte base address */ - SROMC_WAIT_EN = 0x4, /* Wait enabled */ - SROMC_BYTE_EN = 0x8, /* Byte access enabled */ - SROMC_MASK = 0xF -}; - -/* DPRAM configuration */ -struct sromc_cfg { - enum sromc_attr attr; - unsigned size; - unsigned csn; /* CSn # */ - unsigned addr; /* Start address (physical) */ - unsigned end; /* End address (physical) */ -}; - -/* DPRAM access timing configuration */ -struct sromc_access_cfg { - u32 tacs; /* Address set-up before CSn */ - u32 tcos; /* Chip selection set-up before OEn */ - u32 tacc; /* Access cycle */ - u32 tcoh; /* Chip selection hold on OEn */ - u32 tcah; /* Address holding time after CSn */ - u32 tacp; /* Page mode access cycle at Page mode */ - u32 pmc; /* Page Mode config */ -}; - -/* For CMC221 IDPRAM (Internal DPRAM) */ -#define CMC_IDPRAM_SIZE 0x4000 /* 16 KB */ - -/* FOR CMC221 SFR for IDPRAM */ -#define CMC_INT2CP_REG 0x10 /* Interrupt to CP */ -#define CMC_INT2AP_REG 0x50 -#define CMC_CLR_INT_REG 0x28 /* Clear Interrupt to AP */ -#define CMC_RESET_REG 0x3C -#define CMC_PUT_REG 0x40 /* AP->CP reg for hostbooting */ -#define CMC_GET_REG 0x50 /* CP->AP reg for hostbooting */ - -/* For CBP7.2 EDPRAM (External DPRAM) */ -#define CBP_EDPRAM_SIZE 0x4000 /* 16 KB */ - -#define INT_MASK_REQ_ACK_F 0x0020 -#define INT_MASK_REQ_ACK_R 0x0010 -#define INT_MASK_RES_ACK_F 0x0008 -#define INT_MASK_RES_ACK_R 0x0004 -#define INT_MASK_SEND_F 0x0002 -#define INT_MASK_SEND_R 0x0001 - -#define INT_MASK_REQ_ACK_RFS 0x0400 /* Request RES_ACK_RFS */ -#define INT_MASK_RES_ACK_RFS 0x0200 /* Response of REQ_ACK_RFS */ -#define INT_MASK_SEND_RFS 0x0100 /* Indicate sending RFS data */ - - -/* Function prototypes */ -static void config_dpram_port_gpio(void); -static void init_sromc(void); -static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg); -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg); -static int __init init_modem(void); - -#ifdef CONFIG_USBHUB_USB3503 -static int host_port_enable(int port, int enable); -#else -static int host_port_enable(int port, int enable) -{ - return s5p_ehci_port_control(&s5p_device_ehci, port, enable); -} -#endif - -#ifdef CONFIG_LTE_MODEM_CMC221 -static struct sromc_cfg cmc_idpram_cfg = { - .attr = SROMC_DATA_16, - .size = CMC_IDPRAM_SIZE, -}; - -static struct sromc_access_cfg cmc_idpram_access_cfg[] = { - [DPRAM_SPEED_LOW] = { - /* for 33 MHz clock, 64 cycles */ - .tacs = 0x08 << 28, - .tcos = 0x08 << 24, - .tacc = 0x1F << 16, - .tcoh = 0x08 << 12, - .tcah = 0x08 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, - [DPRAM_SPEED_MID] = { - /* for 66 MHz clock, 32 cycles */ - .tacs = 0x01 << 28, - .tcos = 0x01 << 24, - .tacc = 0x1B << 16, - .tcoh = 0x01 << 12, - .tcah = 0x01 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, - [DPRAM_SPEED_HIGH] = { - /* for 133 MHz clock, 16 cycles */ - .tacs = 0x01 << 28, - .tcos = 0x01 << 24, - .tacc = 0x0B << 16, - .tcoh = 0x01 << 12, - .tcah = 0x01 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, -}; - -/* - magic_code + - access_enable + - fmt_tx_head + fmt_tx_tail + fmt_tx_buff + - raw_tx_head + raw_tx_tail + raw_tx_buff + - fmt_rx_head + fmt_rx_tail + fmt_rx_buff + - raw_rx_head + raw_rx_tail + raw_rx_buff + - mbx_cp2ap + - mbx_ap2cp - = 2 + - 2 + - 2 + 2 + 1336 + - 2 + 2 + 4564 + - 2 + 2 + 1336 + - 2 + 2 + 9124 + - 2 + - 2 - = 16384 -*/ - -#define DP_FMT_TX_BUFF_SZ 1336 -#define DP_RAW_TX_BUFF_SZ 4564 -#define DP_FMT_RX_BUFF_SZ 1336 -#define DP_RAW_RX_BUFF_SZ 9124 - -#define MAX_CMC_IDPRAM_IPC_DEV (IPC_RAW + 1) /* FMT, RAW */ - -struct dpram_ipc_cfg { - u16 magic; - u16 access; - - u16 fmt_tx_head; - u16 fmt_tx_tail; - u8 fmt_tx_buff[DP_FMT_TX_BUFF_SZ]; - - u16 raw_tx_head; - u16 raw_tx_tail; - u8 raw_tx_buff[DP_RAW_TX_BUFF_SZ]; - - u16 fmt_rx_head; - u16 fmt_rx_tail; - u8 fmt_rx_buff[DP_FMT_RX_BUFF_SZ]; - - u16 raw_rx_head; - u16 raw_rx_tail; - u8 raw_rx_buff[DP_RAW_RX_BUFF_SZ]; - - u16 mbx_cp2ap; - u16 mbx_ap2cp; -}; - -struct cmc221_idpram_sfr { - u16 __iomem *int2cp; - u16 __iomem *int2ap; - u16 __iomem *clr_int2ap; - u16 __iomem *reset; - u16 __iomem *msg2cp; - u16 __iomem *msg2ap; -}; - -static struct dpram_ipc_map cmc_ipc_map; -static u8 *cmc_sfr_base; -static struct cmc221_idpram_sfr cmc_sfr; - -/* Function prototypes */ -static void cmc_idpram_reset(void); -static void cmc_idpram_setup_speed(enum dpram_speed); -static int cmc_idpram_wakeup(void); -static void cmc_idpram_sleep(void); -static void cmc_idpram_clr_intr(void); -static u16 cmc_idpram_recv_intr(void); -static void cmc_idpram_send_intr(u16 irq_mask); -static u16 cmc_idpram_recv_msg(void); -static void cmc_idpram_send_msg(u16 msg); - -static u16 cmc_idpram_get_magic(void); -static void cmc_idpram_set_magic(u16 value); -static u16 cmc_idpram_get_access(void); -static void cmc_idpram_set_access(u16 value); - -static u32 cmc_idpram_get_tx_head(int dev_id); -static u32 cmc_idpram_get_tx_tail(int dev_id); -static void cmc_idpram_set_tx_head(int dev_id, u32 head); -static void cmc_idpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id); -static u32 cmc_idpram_get_tx_buff_size(int dev_id); - -static u32 cmc_idpram_get_rx_head(int dev_id); -static u32 cmc_idpram_get_rx_tail(int dev_id); -static void cmc_idpram_set_rx_head(int dev_id, u32 head); -static void cmc_idpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id); -static u32 cmc_idpram_get_rx_buff_size(int dev_id); - -static u16 cmc_idpram_get_mask_req_ack(int dev_id); -static u16 cmc_idpram_get_mask_res_ack(int dev_id); -static u16 cmc_idpram_get_mask_send(int dev_id); - -static struct modemlink_dpram_control cmc_idpram_ctrl = { - .reset = cmc_idpram_reset, - - .setup_speed = cmc_idpram_setup_speed, - - .wakeup = cmc_idpram_wakeup, - .sleep = cmc_idpram_sleep, - - .clear_intr = cmc_idpram_clr_intr, - .recv_intr = cmc_idpram_recv_intr, - .send_intr = cmc_idpram_send_intr, - .recv_msg = cmc_idpram_recv_msg, - .send_msg = cmc_idpram_send_msg, - - .get_magic = cmc_idpram_get_magic, - .set_magic = cmc_idpram_set_magic, - .get_access = cmc_idpram_get_access, - .set_access = cmc_idpram_set_access, - - .get_tx_head = cmc_idpram_get_tx_head, - .get_tx_tail = cmc_idpram_get_tx_tail, - .set_tx_head = cmc_idpram_set_tx_head, - .set_tx_tail = cmc_idpram_set_tx_tail, - .get_tx_buff = cmc_idpram_get_tx_buff, - .get_tx_buff_size = cmc_idpram_get_tx_buff_size, - - .get_rx_head = cmc_idpram_get_rx_head, - .get_rx_tail = cmc_idpram_get_rx_tail, - .set_rx_head = cmc_idpram_set_rx_head, - .set_rx_tail = cmc_idpram_set_rx_tail, - .get_rx_buff = cmc_idpram_get_rx_buff, - .get_rx_buff_size = cmc_idpram_get_rx_buff_size, - - .get_mask_req_ack = cmc_idpram_get_mask_req_ack, - .get_mask_res_ack = cmc_idpram_get_mask_res_ack, - .get_mask_send = cmc_idpram_get_mask_send, - - .dp_base = NULL, - .dp_size = 0, - .dp_type = CP_IDPRAM, - .aligned = 1, - - .dpram_irq = CMC_IDPRAM_INT_IRQ_00, - .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_RISING), - .dpram_irq_name = "CMC221_IDPRAM_IRQ", - .dpram_wlock_name = "CMC221_IDPRAM_WLOCK", - - .max_ipc_dev = MAX_CMC_IDPRAM_IPC_DEV, -}; - -/* -** UMTS target platform data -*/ -static struct modem_io_t umts_io_devices[] = { - [0] = { - .name = "umts_boot0", - .id = 0, - .format = IPC_BOOT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [1] = { - .name = "umts_ipc0", - .id = 235, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [2] = { - .name = "umts_rfs0", - .id = 245, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [3] = { - .name = "lte_multipdp", - .id = 0, - .format = IPC_MULTI_RAW, - .io_type = IODEV_DUMMY, - .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), - .tx_link = LINKDEV_DPRAM, - }, - [4] = { - .name = "lte_rmnet0", - .id = 10, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), - .tx_link = LINKDEV_DPRAM, - }, - [5] = { - .name = "lte_rmnet1", - .id = 11, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), - .tx_link = LINKDEV_DPRAM, - }, - [6] = { - .name = "lte_rmnet2", - .id = 12, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), - .tx_link = LINKDEV_DPRAM, - }, - [7] = { - .name = "lte_rmnet3", - .id = 13, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), - .tx_link = LINKDEV_DPRAM, - }, - [8] = { - .name = "umts_csd", /* CS Video Telephony */ - .id = 1, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [9] = { - .name = "umts_router", /* AT Iface & Dial-up */ - .id = 25, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [10] = { - .name = "umts_dm0", /* DM Port */ - .id = 28, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [11] = { - .name = "umts_loopback_ap2cp", - .id = 30, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [12] = { - .name = "umts_loopback_cp2ap", - .id = 31, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [13] = { - .name = "umts_ramdump0", - .id = 0, - .format = IPC_RAMDUMP, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [14] = { - .name = "lte_ipc0", - .id = 235, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_USB), - }, -}; - -static int exynos_cpu_frequency_lock(void); -static int exynos_cpu_frequency_unlock(void); - -static struct modemlink_pm_data umts_link_pm_data = { - .name = "umts_link_pm", - - .gpio_link_enable = 0, - .gpio_link_active = GPIO_ACTIVE_STATE, - .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, - .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, - - .port_enable = host_port_enable, -/* - .link_reconnect = umts_link_reconnect, -*/ - .freqlock = ATOMIC_INIT(0), - .cpufreq_lock = exynos_cpu_frequency_lock, - .cpufreq_unlock = exynos_cpu_frequency_unlock, - - .autosuspend_delay_ms = 2000, - - .has_usbhub = true, -}; - -static struct modem_data umts_modem_data = { - .name = "cmc221", - - .gpio_cp_on = CP_CMC221_PMIC_PWRON, - .gpio_cp_reset = CP_CMC221_CPU_RST, - .gpio_phone_active = GPIO_LTE_ACTIVE, - - .gpio_dpram_int = GPIO_CMC_IDPRAM_INT_00, - .gpio_dpram_status = GPIO_CMC_IDPRAM_STATUS, - .gpio_dpram_wakeup = GPIO_CMC_IDPRAM_WAKEUP, - - .gpio_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP, - .gpio_host_active = GPIO_ACTIVE_STATE, - .gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP, - - .modem_net = UMTS_NETWORK, - .modem_type = SEC_CMC221, - .link_types = LINKTYPE(LINKDEV_DPRAM) | LINKTYPE(LINKDEV_USB), - .link_name = "cmc221_idpram", - .dpram_ctl = &cmc_idpram_ctrl, - - .num_iodevs = ARRAY_SIZE(umts_io_devices), - .iodevs = umts_io_devices, - - .link_pm_data = &umts_link_pm_data, - - .use_handover = true, - - .ipc_version = SIPC_VER_50, - .use_mif_log = true, -}; - -static struct resource umts_modem_res[] = { - [0] = { - .name = "cp_active_irq", - .start = LTE_ACTIVE_IRQ, - .end = LTE_ACTIVE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device umts_modem = { - .name = "mif_sipc5", - .id = 1, - .num_resources = ARRAY_SIZE(umts_modem_res), - .resource = umts_modem_res, - .dev = { - .platform_data = &umts_modem_data, - }, -}; - -#define HUB_STATE_OFF 0 -void set_hsic_lpa_states(int states) -{ - int val = gpio_get_value(umts_modem_data.gpio_cp_reset); - - mif_trace("\n"); - - if (val && states == STATE_HSIC_LPA_ENTER) { - mif_info("usb3503: hub off - lpa\n"); - host_port_enable(2, 0); - *(umts_link_pm_data.p_hub_status) = HUB_STATE_OFF; - } -} - -int get_cp_active_state(void) -{ - return gpio_get_value(umts_modem_data.gpio_phone_active); -} - -static void cmc_idpram_reset(void) -{ - iowrite16(1, cmc_sfr.reset); -} - -static void cmc_idpram_setup_speed(enum dpram_speed speed) -{ - setup_dpram_speed(cmc_idpram_cfg.csn, &cmc_idpram_access_cfg[speed]); -} - -static int cmc_idpram_wakeup(void) -{ - int cnt = 0; - - gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 1); - - while (!gpio_get_value(umts_modem_data.gpio_dpram_status)) { - if (cnt++ > 10) { - mif_err("ERR: gpio_dpram_status == 0\n"); - return -EAGAIN; - } - - if (in_interrupt()) - mdelay(1); - else - msleep_interruptible(1); - } - - return 0; -} - -static void cmc_idpram_sleep(void) -{ - gpio_set_value(umts_modem_data.gpio_dpram_wakeup, 0); -} - -static void cmc_idpram_clr_intr(void) -{ - iowrite16(0xFFFF, cmc_sfr.clr_int2ap); - iowrite16(0, cmc_sfr.int2ap); -} - -static u16 cmc_idpram_recv_intr(void) -{ - return ioread16(cmc_sfr.int2ap); -} - -static void cmc_idpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, cmc_sfr.int2cp); -} - -static u16 cmc_idpram_recv_msg(void) -{ - return ioread16(cmc_sfr.msg2ap); -} - -static void cmc_idpram_send_msg(u16 msg) -{ - iowrite16(msg, cmc_sfr.msg2cp); -} - -static u16 cmc_idpram_get_magic(void) -{ - return ioread16(cmc_ipc_map.magic); -} - -static void cmc_idpram_set_magic(u16 value) -{ - iowrite16(value, cmc_ipc_map.magic); -} - -static u16 cmc_idpram_get_access(void) -{ - return ioread16(cmc_ipc_map.access); -} - -static void cmc_idpram_set_access(u16 value) -{ - iowrite16(value, cmc_ipc_map.access); -} - -static u32 cmc_idpram_get_tx_head(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].txq.head); -} - -static u32 cmc_idpram_get_tx_tail(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].txq.tail); -} - -static void cmc_idpram_set_tx_head(int dev_id, u32 head) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head); - - do { - /* Check head value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].txq.head); - if (val == head) - break; - - mif_err("ERR: txq.head(%d) != head(%d)\n", val, head); - - /* Write head value again */ - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].txq.head); - } while (cnt--); -} - -static void cmc_idpram_set_tx_tail(int dev_id, u32 tail) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail); - - do { - /* Check tail value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].txq.tail); - if (val == tail) - break; - - mif_err("ERR: txq.tail(%d) != tail(%d)\n", val, tail); - - /* Write tail value again */ - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].txq.tail); - } while (cnt--); -} - -static u8 __iomem *cmc_idpram_get_tx_buff(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].txq.buff; -} - -static u32 cmc_idpram_get_tx_buff_size(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].txq.size; -} - -static u32 cmc_idpram_get_rx_head(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].rxq.head); -} - -static u32 cmc_idpram_get_rx_tail(int dev_id) -{ - return ioread16(cmc_ipc_map.dev[dev_id].rxq.tail); -} - -static void cmc_idpram_set_rx_head(int dev_id, u32 head) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head); - - do { - /* Check head value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].rxq.head); - if (val == head) - break; - - mif_err("ERR: rxq.head(%d) != head(%d)\n", val, head); - - /* Write head value again */ - iowrite16((u16)head, cmc_ipc_map.dev[dev_id].rxq.head); - } while (cnt--); -} - -static void cmc_idpram_set_rx_tail(int dev_id, u32 tail) -{ - int cnt = 100; - u32 val = 0; - - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail); - - do { - /* Check tail value written */ - val = ioread16(cmc_ipc_map.dev[dev_id].rxq.tail); - if (val == tail) - break; - - mif_err("ERR: rxq.tail(%d) != tail(%d)\n", val, tail); - - /* Write tail value again */ - iowrite16((u16)tail, cmc_ipc_map.dev[dev_id].rxq.tail); - } while (cnt--); -} - -static u8 __iomem *cmc_idpram_get_rx_buff(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].rxq.buff; -} - -static u32 cmc_idpram_get_rx_buff_size(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].rxq.size; -} - -static u16 cmc_idpram_get_mask_req_ack(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].mask_req_ack; -} - -static u16 cmc_idpram_get_mask_res_ack(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].mask_res_ack; -} - -static u16 cmc_idpram_get_mask_send(int dev_id) -{ - return cmc_ipc_map.dev[dev_id].mask_send; -} - -/* Set dynamic environment for a modem */ -static void setup_umts_modem_env(void) -{ - /* - ** Config DPRAM control structure - */ - if (system_rev == 1 || system_rev >= 4) - cmc_idpram_cfg.csn = 0; - else - cmc_idpram_cfg.csn = 1; - - cmc_idpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cmc_idpram_cfg.csn); - cmc_idpram_cfg.end = cmc_idpram_cfg.addr + cmc_idpram_cfg.size - 1; - - if (system_rev == 1 || system_rev >= 4) { - umts_modem_data.gpio_dpram_int = GPIO_CMC_IDPRAM_INT_01; - cmc_idpram_ctrl.dpram_irq = CMC_IDPRAM_INT_IRQ_01; - } -} - -static void config_umts_modem_gpio(void) -{ - int err; - unsigned gpio_cp_on = umts_modem_data.gpio_cp_on; - unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset; - unsigned gpio_pda_active = umts_modem_data.gpio_pda_active; - unsigned gpio_phone_active = umts_modem_data.gpio_phone_active; - unsigned gpio_active_state = umts_modem_data.gpio_host_active; - unsigned gpio_host_wakeup = umts_modem_data.gpio_host_wakeup; - unsigned gpio_slave_wakeup = umts_modem_data.gpio_slave_wakeup; - unsigned gpio_dpram_int = umts_modem_data.gpio_dpram_int; - unsigned gpio_dpram_status = umts_modem_data.gpio_dpram_status; - unsigned gpio_dpram_wakeup = umts_modem_data.gpio_dpram_wakeup; - - if (gpio_cp_on) { - err = gpio_request(gpio_cp_on, "CMC_ON"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", "CMC_ON"); - } else { - gpio_direction_output(gpio_cp_on, 0); - s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_cp_rst) { - err = gpio_request(gpio_cp_rst, "CMC_RST"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", "CMC_RST"); - } else { - gpio_direction_output(gpio_cp_rst, 0); - s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_pda_active) { - err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", "PDA_ACTIVE"); - } else { - gpio_direction_output(gpio_pda_active, 0); - s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_phone_active) { - err = gpio_request(gpio_phone_active, "CMC_ACTIVE"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", "CMC_ACTIVE"); - } else { - /* Configure as a wake-up source */ - gpio_direction_input(gpio_phone_active); - s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_DOWN); - s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); - } - } - - if (gpio_active_state) { - err = gpio_request(gpio_active_state, "CMC_ACTIVE_STATE"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", - "CMC_ACTIVE_STATE"); - } else { - gpio_direction_output(gpio_active_state, 0); - s3c_gpio_setpull(gpio_active_state, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_slave_wakeup) { - err = gpio_request(gpio_slave_wakeup, "CMC_SLAVE_WAKEUP"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", - "CMC_SLAVE_WAKEUP"); - } else { - gpio_direction_output(gpio_slave_wakeup, 0); - s3c_gpio_setpull(gpio_slave_wakeup, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_host_wakeup) { - err = gpio_request(gpio_host_wakeup, "CMC_HOST_WAKEUP"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", - "CMC_HOST_WAKEUP"); - } else { - /* Configure as a wake-up source */ - gpio_direction_input(gpio_host_wakeup); - s3c_gpio_setpull(gpio_host_wakeup, S3C_GPIO_PULL_DOWN); - s3c_gpio_cfgpin(gpio_host_wakeup, S3C_GPIO_SFN(0xF)); - } - } - - if (gpio_dpram_int) { - err = gpio_request(gpio_dpram_int, "CMC_DPRAM_INT"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", - "CMC_DPRAM_INT"); - } else { - /* Configure as a wake-up source */ - gpio_direction_input(gpio_dpram_int); - s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF)); - } - } - - if (gpio_dpram_status) { - err = gpio_request(gpio_dpram_status, "CMC_DPRAM_STATUS"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", - "CMC_DPRAM_STATUS"); - } else { - gpio_direction_input(gpio_dpram_status); - s3c_gpio_setpull(gpio_dpram_status, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_dpram_wakeup) { - err = gpio_request(gpio_dpram_wakeup, "CMC_DPRAM_WAKEUP"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", - "CMC_DPRAM_WAKEUP"); - } else { - gpio_direction_output(gpio_dpram_wakeup, 1); - s3c_gpio_setpull(gpio_dpram_wakeup, S3C_GPIO_PULL_NONE); - } - } -} - -static u8 *cmc_idpram_remap_mem_region(struct sromc_cfg *cfg) -{ - int dp_addr = cfg->addr; - int dp_size = cfg->size; - u8 __iomem *dp_base; - struct dpram_ipc_cfg *ipc_map; - struct dpram_ipc_device *dev; - - /* Remap DPRAM memory region */ - dp_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); - if (!dp_base) { - mif_err("ERR: ioremap_nocache for dp_base fail\n"); - return NULL; - } - mif_err("DPRAM VA=0x%08X\n", (int)dp_base); - - /* Remap DPRAM SFR region */ - dp_addr += dp_size; - cmc_sfr_base = (u8 __iomem *)ioremap_nocache(dp_addr, dp_size); - if (cmc_sfr_base == NULL) { - iounmap(dp_base); - mif_err("ERR: ioremap_nocache for cmc_sfr_base fail\n"); - return NULL; - } - - cmc_sfr.int2cp = (u16 __iomem *)(cmc_sfr_base + CMC_INT2CP_REG); - cmc_sfr.int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_INT2AP_REG); - cmc_sfr.clr_int2ap = (u16 __iomem *)(cmc_sfr_base + CMC_CLR_INT_REG); - cmc_sfr.reset = (u16 __iomem *)(cmc_sfr_base + CMC_RESET_REG); - cmc_sfr.msg2cp = (u16 __iomem *)(cmc_sfr_base + CMC_PUT_REG); - cmc_sfr.msg2ap = (u16 __iomem *)(cmc_sfr_base + CMC_GET_REG); - - cmc_idpram_ctrl.dp_base = (u8 __iomem *)dp_base; - cmc_idpram_ctrl.dp_size = dp_size; - - /* Map for IPC */ - ipc_map = (struct dpram_ipc_cfg *)dp_base; - - /* Magic code and access enable fields */ - cmc_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; - cmc_ipc_map.access = (u16 __iomem *)&ipc_map->access; - - /* FMT */ - dev = &cmc_ipc_map.dev[IPC_FMT]; - - strcpy(dev->name, "FMT"); - dev->id = IPC_FMT; - - dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; - dev->txq.size = DP_FMT_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; - dev->rxq.size = DP_FMT_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_F; - dev->mask_res_ack = INT_MASK_RES_ACK_F; - dev->mask_send = INT_MASK_SEND_F; - - /* RAW */ - dev = &cmc_ipc_map.dev[IPC_RAW]; - - strcpy(dev->name, "RAW"); - dev->id = IPC_RAW; - - dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; - dev->txq.size = DP_RAW_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; - dev->rxq.size = DP_RAW_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_R; - dev->mask_res_ack = INT_MASK_RES_ACK_R; - dev->mask_send = INT_MASK_SEND_R; - - return dp_base; -} -#endif - -#ifdef CONFIG_CDMA_MODEM_CBP72 -static struct sromc_cfg cbp_edpram_cfg = { - .attr = SROMC_DATA_16 | SROMC_BYTE_EN, - .size = CBP_EDPRAM_SIZE, -}; - -static struct sromc_access_cfg cbp_edpram_access_cfg[] = { - [DPRAM_SPEED_LOW] = { - .tacs = 0x00 << 28, - .tcos = 0x00 << 24, - .tacc = 0x0F << 16, - .tcoh = 0x00 << 12, - .tcah = 0x00 << 8, - .tacp = 0x00 << 4, - .pmc = 0x00 << 0, - }, -}; - -/* - magic_code + - access_enable + - fmt_tx_head + fmt_tx_tail + fmt_tx_buff + - raw_tx_head + raw_tx_tail + raw_tx_buff + - fmt_rx_head + fmt_rx_tail + fmt_rx_buff + - raw_rx_head + raw_rx_tail + raw_rx_buff + - mbx_cp2ap + - mbx_ap2cp - = 2 + - 2 + - 2 + 2 + 1336 + - 2 + 2 + 4564 + - 2 + 2 + 1336 + - 2 + 2 + 9124 + - 2 + - 2 - = 16384 -*/ - -#define CBP_DP_FMT_TX_BUFF_SZ 1336 -#define CBP_DP_RAW_TX_BUFF_SZ 4564 -#define CBP_DP_FMT_RX_BUFF_SZ 1336 -#define CBP_DP_RAW_RX_BUFF_SZ 9124 - -#define MAX_CBP_EDPRAM_IPC_DEV (IPC_RAW + 1) /* FMT, RAW */ - -struct cbp_edpram_ipc_cfg { - u16 magic; - u16 access; - - u16 fmt_tx_head; - u16 fmt_tx_tail; - u8 fmt_tx_buff[CBP_DP_FMT_TX_BUFF_SZ]; - - u16 raw_tx_head; - u16 raw_tx_tail; - u8 raw_tx_buff[CBP_DP_RAW_TX_BUFF_SZ]; - - u16 fmt_rx_head; - u16 fmt_rx_tail; - u8 fmt_rx_buff[CBP_DP_FMT_RX_BUFF_SZ]; - - u16 raw_rx_head; - u16 raw_rx_tail; - u8 raw_rx_buff[CBP_DP_RAW_RX_BUFF_SZ]; - - u16 mbx_cp2ap; - u16 mbx_ap2cp; -}; - -static struct dpram_ipc_map cbp_ipc_map; - -static void cbp_edpram_reset(void); -static void cbp_edpram_clr_intr(void); -static u16 cbp_edpram_recv_intr(void); -static void cbp_edpram_send_intr(u16 irq_mask); -static u16 cbp_edpram_recv_msg(void); -static void cbp_edpram_send_msg(u16 msg); - -static u16 cbp_edpram_get_magic(void); -static void cbp_edpram_set_magic(u16 value); -static u16 cbp_edpram_get_access(void); -static void cbp_edpram_set_access(u16 value); - -static u32 cbp_edpram_get_tx_head(int dev_id); -static u32 cbp_edpram_get_tx_tail(int dev_id); -static void cbp_edpram_set_tx_head(int dev_id, u32 head); -static void cbp_edpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id); -static u32 cbp_edpram_get_tx_buff_size(int dev_id); - -static u32 cbp_edpram_get_rx_head(int dev_id); -static u32 cbp_edpram_get_rx_tail(int dev_id); -static void cbp_edpram_set_rx_head(int dev_id, u32 head); -static void cbp_edpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id); -static u32 cbp_edpram_get_rx_buff_size(int dev_id); - -static u16 cbp_edpram_get_mask_req_ack(int dev_id); -static u16 cbp_edpram_get_mask_res_ack(int dev_id); -static u16 cbp_edpram_get_mask_send(int dev_id); - -static struct modemlink_dpram_control cbp_edpram_ctrl = { - .reset = cbp_edpram_reset, - - .clear_intr = cbp_edpram_clr_intr, - .recv_intr = cbp_edpram_recv_intr, - .send_intr = cbp_edpram_send_intr, - .recv_msg = cbp_edpram_recv_msg, - .send_msg = cbp_edpram_send_msg, - - .get_magic = cbp_edpram_get_magic, - .set_magic = cbp_edpram_set_magic, - .get_access = cbp_edpram_get_access, - .set_access = cbp_edpram_set_access, - - .get_tx_head = cbp_edpram_get_tx_head, - .get_tx_tail = cbp_edpram_get_tx_tail, - .set_tx_head = cbp_edpram_set_tx_head, - .set_tx_tail = cbp_edpram_set_tx_tail, - .get_tx_buff = cbp_edpram_get_tx_buff, - .get_tx_buff_size = cbp_edpram_get_tx_buff_size, - - .get_rx_head = cbp_edpram_get_rx_head, - .get_rx_tail = cbp_edpram_get_rx_tail, - .set_rx_head = cbp_edpram_set_rx_head, - .set_rx_tail = cbp_edpram_set_rx_tail, - .get_rx_buff = cbp_edpram_get_rx_buff, - .get_rx_buff_size = cbp_edpram_get_rx_buff_size, - - .get_mask_req_ack = cbp_edpram_get_mask_req_ack, - .get_mask_res_ack = cbp_edpram_get_mask_res_ack, - .get_mask_send = cbp_edpram_get_mask_send, - - .dp_base = NULL, - .dp_size = 0, - .dp_type = EXT_DPRAM, - .aligned = 1, - - .dpram_irq = CBP_DPRAM_INT_IRQ_00, - .dpram_irq_flags = (IRQF_NO_SUSPEND | IRQF_TRIGGER_FALLING), - .dpram_irq_name = "CBP72_EDPRAM_IRQ", - .dpram_wlock_name = "CBP72_EDPRAM_WLOCK", - - .max_ipc_dev = MAX_CBP_EDPRAM_IPC_DEV, -}; - -/* -** CDMA target platform data -*/ -static struct modem_io_t cdma_io_devices[] = { - [0] = { - .name = "cdma_boot0", - .id = 0, - .format = IPC_BOOT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [1] = { - .name = "cdma_ipc0", - .id = 235, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [2] = { - .name = "cdma_rfs0", - .id = 245, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [3] = { - .name = "cdma_multipdp", - .id = 0, - .format = IPC_MULTI_RAW, - .io_type = IODEV_DUMMY, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [4] = { - .name = "cdma_rmnet0", - .id = 10, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [5] = { - .name = "cdma_rmnet1", - .id = 11, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [6] = { - .name = "cdma_rmnet2", - .id = 12, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [7] = { - .name = "cdma_rmnet3", - .id = 13, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [8] = { - .name = "cdma_rmnet4", - .id = 7, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [9] = { - .name = "cdma_rmnet5", /* DM Port IO device */ - .id = 26, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [10] = { - .name = "cdma_rmnet6", /* AT CMD IO device */ - .id = 17, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, - [11] = { - .name = "cdma_ramdump0", - .id = 0, - .format = IPC_RAMDUMP, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, -}; - -static struct modem_data cdma_modem_data = { - .name = "cbp7.2", - - .gpio_cp_on = GPIO_CBP_PMIC_PWRON, - .gpio_cp_off = GPIO_CBP_PS_HOLD_OFF, - .gpio_cp_reset = GPIO_CBP_CP_RST, - .gpio_pda_active = GPIO_PDA_ACTIVE, - .gpio_phone_active = GPIO_CBP_PHONE_ACTIVE, - - .gpio_dpram_int = GPIO_CBP_DPRAM_INT_00, - - .modem_net = CDMA_NETWORK, - .modem_type = VIA_CBP72, - .link_types = LINKTYPE(LINKDEV_DPRAM), - .link_name = "cbp72_edpram", - .dpram_ctl = &cbp_edpram_ctrl, - - .num_iodevs = ARRAY_SIZE(cdma_io_devices), - .iodevs = cdma_io_devices, - - .use_handover = true, - - .ipc_version = SIPC_VER_50, -}; - -static struct resource cdma_modem_res[] = { - [0] = { - .name = "cp_active_irq", - .start = CBP_PHONE_ACTIVE_IRQ, - .end = CBP_PHONE_ACTIVE_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cdma_modem = { - .name = "mif_sipc5", - .id = 2, - .num_resources = ARRAY_SIZE(cdma_modem_res), - .resource = cdma_modem_res, - .dev = { - .platform_data = &cdma_modem_data, - }, -}; - -static void cbp_edpram_reset(void) -{ - return; -} - -static void cbp_edpram_clr_intr(void) -{ - ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static u16 cbp_edpram_recv_intr(void) -{ - return ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static void cbp_edpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, cbp_ipc_map.mbx_ap2cp); -} - -static u16 cbp_edpram_recv_msg(void) -{ - return ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static void cbp_edpram_send_msg(u16 msg) -{ - iowrite16(msg, cbp_ipc_map.mbx_ap2cp); -} - -static u16 cbp_edpram_get_magic(void) -{ - return ioread16(cbp_ipc_map.magic); -} - -static void cbp_edpram_set_magic(u16 value) -{ - iowrite16(value, cbp_ipc_map.magic); -} - -static u16 cbp_edpram_get_access(void) -{ - return ioread16(cbp_ipc_map.access); -} - -static void cbp_edpram_set_access(u16 value) -{ - iowrite16(value, cbp_ipc_map.access); -} - -static u32 cbp_edpram_get_tx_head(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].txq.head); -} - -static u32 cbp_edpram_get_tx_tail(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].txq.tail); -} - -static void cbp_edpram_set_tx_head(int dev_id, u32 head) -{ - iowrite16((u16)head, cbp_ipc_map.dev[dev_id].txq.head); -} - -static void cbp_edpram_set_tx_tail(int dev_id, u32 tail) -{ - iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].txq.tail); -} - -static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].txq.buff; -} - -static u32 cbp_edpram_get_tx_buff_size(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].txq.size; -} - -static u32 cbp_edpram_get_rx_head(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].rxq.head); -} - -static u32 cbp_edpram_get_rx_tail(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].rxq.tail); -} - -static void cbp_edpram_set_rx_head(int dev_id, u32 head) -{ - return iowrite16((u16)head, cbp_ipc_map.dev[dev_id].rxq.head); -} - -static void cbp_edpram_set_rx_tail(int dev_id, u32 tail) -{ - return iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].rxq.tail); -} - -static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].rxq.buff; -} - -static u32 cbp_edpram_get_rx_buff_size(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].rxq.size; -} - -static u16 cbp_edpram_get_mask_req_ack(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_req_ack; -} - -static u16 cbp_edpram_get_mask_res_ack(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_res_ack; -} - -static u16 cbp_edpram_get_mask_send(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_send; -} - -/* Set dynamic environment for a modem */ -static void setup_cdma_modem_env(void) -{ - /* - ** Config DPRAM control structure - */ - if (system_rev == 1 || system_rev >= 4) - cbp_edpram_cfg.csn = 1; - else - cbp_edpram_cfg.csn = 0; - - cbp_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cbp_edpram_cfg.csn); - cbp_edpram_cfg.end = cbp_edpram_cfg.addr + cbp_edpram_cfg.size - 1; - - if (system_rev == 1 || system_rev >= 4) { - cdma_modem_data.gpio_dpram_int = GPIO_CBP_DPRAM_INT_01; - cbp_edpram_ctrl.dpram_irq = CBP_DPRAM_INT_IRQ_01; - } -} - -static void config_cdma_modem_gpio(void) -{ - int err; - unsigned gpio_boot_sel = GPIO_CBP_BOOT_SEL; - unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on; - unsigned gpio_cp_off = cdma_modem_data.gpio_cp_off; - unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset; - unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active; - unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active; - unsigned gpio_dpram_int = cdma_modem_data.gpio_dpram_int; - - pr_info("[MDM] <%s>\n", __func__); - - if (gpio_boot_sel) { - err = gpio_request(gpio_boot_sel, "CBP_BOOT_SEL"); - if (err) { - pr_err("fail to request gpio %s\n", "CBP_BOOT_SEL"); - } else { - gpio_direction_output(gpio_boot_sel, 0); - s3c_gpio_setpull(gpio_boot_sel, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_cp_on) { - err = gpio_request(gpio_cp_on, "CBP_ON"); - if (err) { - pr_err("fail to request gpio %s\n", "CBP_ON"); - } else { - gpio_direction_output(gpio_cp_on, 0); - s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_cp_off) { - err = gpio_request(gpio_cp_off, "CBP_OFF"); - if (err) { - pr_err("fail to request gpio %s\n", "CBP_OFF"); - } else { - gpio_direction_output(gpio_cp_off, 1); - s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_cp_rst) { - err = gpio_request(gpio_cp_rst, "CBP_RST"); - if (err) { - pr_err("fail to request gpio %s\n", "CBP_RST"); - } else { - gpio_direction_output(gpio_cp_rst, 0); - s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_pda_active) { - err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); - if (err) { - pr_err("fail to request gpio %s\n", "PDA_ACTIVE"); - } else { - gpio_direction_output(gpio_pda_active, 0); - s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); - } - } - - if (gpio_phone_active) { - err = gpio_request(gpio_phone_active, "CBP_ACTIVE"); - if (err) { - pr_err("fail to request gpio %s\n", "CBP_ACTIVE"); - } else { - /* Configure as a wake-up source */ - gpio_direction_input(gpio_phone_active); - s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); - } - } - - if (gpio_dpram_int) { - err = gpio_request(gpio_dpram_int, "CBP_DPRAM_INT"); - if (err) { - pr_err("fail to request gpio %s\n", "CBP_DPRAM_INT"); - } else { - /* Configure as a wake-up source */ - gpio_direction_input(gpio_dpram_int); - s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF)); - } - } - - /* set low unused gpios between AP and CP */ - err = gpio_request(GPIO_FLM_RXD, "FLM_RXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD", - err); - else { - gpio_direction_input(GPIO_FLM_RXD); - s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(2)); - } - - err = gpio_request(GPIO_FLM_TXD, "FLM_TXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD", - err); - else { - gpio_direction_input(GPIO_FLM_TXD); - s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(2)); - } -} - -static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg) -{ - int dp_addr = 0; - int dp_size = 0; - u8 __iomem *dp_base = NULL; - struct cbp_edpram_ipc_cfg *ipc_map = NULL; - struct dpram_ipc_device *dev = NULL; - - dp_addr = cfg->addr; - dp_size = cfg->size; - dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size); - if (!dp_base) { - pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__); - return NULL; - } - pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base); - - cbp_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; - cbp_edpram_ctrl.dp_size = dp_size; - - /* Map for IPC */ - ipc_map = (struct cbp_edpram_ipc_cfg *)dp_base; - - /* Magic code and access enable fields */ - cbp_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; - cbp_ipc_map.access = (u16 __iomem *)&ipc_map->access; - - /* FMT */ - dev = &cbp_ipc_map.dev[IPC_FMT]; - - strcpy(dev->name, "FMT"); - dev->id = IPC_FMT; - - dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; - dev->txq.size = CBP_DP_FMT_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; - dev->rxq.size = CBP_DP_FMT_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_F; - dev->mask_res_ack = INT_MASK_RES_ACK_F; - dev->mask_send = INT_MASK_SEND_F; - - /* RAW */ - dev = &cbp_ipc_map.dev[IPC_RAW]; - - strcpy(dev->name, "RAW"); - dev->id = IPC_RAW; - - dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; - dev->txq.size = CBP_DP_RAW_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; - dev->rxq.size = CBP_DP_RAW_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_R; - dev->mask_res_ack = INT_MASK_RES_ACK_R; - dev->mask_send = INT_MASK_SEND_R; - - /* Mailboxes */ - cbp_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; - cbp_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; - - return dp_base; -} -#endif - -/** - * DPRAM GPIO settings - * - * SROM_NUM_ADDR_BITS value indicate the address line number or - * the mux/demux dpram type. if you want to set mux mode, define the - * SROM_NUM_ADDR_BITS to zero. - * - * for CMC22x - * CMC22x has 16KB + a SFR register address. - * It used 14 bits (13bits for 16KB word address and 1 bit for SFR - * register) - */ -static void config_dpram_port_gpio(void) -{ - int addr_bits = SROM_NUM_ADDR_BITS; - - mif_info("address line = %d bits\n", addr_bits); - - /* - ** Config DPRAM address/data GPIO pins - */ - - /* Set GPIO for address bus (13 ~ 14 bits) */ - switch (addr_bits) { - case 0: - break; - - case 13 ... 14: - s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_LOW, - EXYNOS4_GPIO_Y3_NR, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(GPIO_SROM_ADDR_BUS_HIGH, - (addr_bits - EXYNOS4_GPIO_Y3_NR), S3C_GPIO_SFN(2)); - break; - - default: - mif_err("ERR: invalid addr_bits!!!\n"); - return; - } - - /* Set GPIO for data bus (16 bits) */ - s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_LOW, 8, S3C_GPIO_SFN(2)); - s3c_gpio_cfgrange_nopull(GPIO_SROM_DATA_BUS_HIGH, 8, S3C_GPIO_SFN(2)); - - /* Setup SROMC CSn pins */ - s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin((GPIO_DPRAM_CSN0 + 1), S3C_GPIO_SFN(2)); - - /* Config OEn, WEn */ - s3c_gpio_cfgpin(GPIO_DPRAM_REN, S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(GPIO_DPRAM_WEN, S3C_GPIO_SFN(2)); - - /* Config LBn, UBn */ - s3c_gpio_cfgpin(GPIO_DPRAM_LBN, S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(GPIO_DPRAM_UBN, S3C_GPIO_SFN(2)); -} - -static void init_sromc(void) -{ - struct clk *clk = NULL; - - /* SROMC clk enable */ - clk = clk_get(NULL, "sromc"); - if (!clk) { - mif_err("ERR: SROMC clock gate fail\n"); - return; - } - clk_enable(clk); -} - -static void setup_sromc -( - unsigned csn, - struct sromc_cfg *cfg, - struct sromc_access_cfg *acc_cfg -) -{ - unsigned bw = 0; /* Bus width and wait control */ - unsigned bc = 0; /* Vank control */ - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - - mif_err("SROMC settings for CS%d...\n", csn); - - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - mif_err("Old SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc); - - /* Set the BW control field for the CSn */ - bw &= ~(SROMC_MASK << (csn << 2)); - bw |= (cfg->attr << (csn << 2)); - writel(bw, S5P_SROM_BW); - - /* Set SROMC memory access timing for the CSn */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - - writel(bc, bank_sfr); - - /* Verify SROMC settings */ - bw = __raw_readl(S5P_SROM_BW); - bc = __raw_readl(bank_sfr); - mif_err("New SROMC settings = BW(0x%08X) BC%d(0x%08X)\n", bw, csn, bc); -} - -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg) -{ - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - unsigned bc = 0; - - bc = __raw_readl(bank_sfr); - mif_info("Old CS%d setting = 0x%08X\n", csn, bc); - - /* SROMC memory access timing setting */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - writel(bc, bank_sfr); - - bc = __raw_readl(bank_sfr); - mif_info("New CS%d setting = 0x%08X\n", csn, bc); -} - -static int __init init_modem(void) -{ - struct sromc_cfg *cfg = NULL; - struct sromc_access_cfg *acc_cfg = NULL; - - mif_err("System Revision = %d\n", system_rev); - - setup_umts_modem_env(); - setup_cdma_modem_env(); - - config_dpram_port_gpio(); - - config_umts_modem_gpio(); - config_cdma_modem_gpio(); - - init_sromc(); - - cfg = &cmc_idpram_cfg; - acc_cfg = &cmc_idpram_access_cfg[DPRAM_SPEED_LOW]; - setup_sromc(cfg->csn, cfg, acc_cfg); - - cfg = &cbp_edpram_cfg; - acc_cfg = &cbp_edpram_access_cfg[DPRAM_SPEED_LOW]; - setup_sromc(cfg->csn, cfg, acc_cfg); - - if (!cmc_idpram_remap_mem_region(&cmc_idpram_cfg)) - return -1; - platform_device_register(&umts_modem); - - if (!cbp_edpram_remap_mem_region(&cbp_edpram_cfg)) - return -1; - platform_device_register(&cdma_modem); - - return 0; -} -late_initcall(init_modem); -/*device_initcall(init_modem);*/ - -#ifdef CONFIG_USBHUB_USB3503 -static int (*usbhub_set_mode)(struct usb3503_hubctl *, int); -static struct usb3503_hubctl *usbhub_ctl; - -#ifdef CONFIG_EXYNOS4_CPUFREQ -static int exynos_cpu_frequency_lock(void) -{ - unsigned int level, freq = 700; - - if (atomic_read(&umts_link_pm_data.freqlock) == 0) { - if (exynos_cpufreq_get_level(freq * 1000, &level)) { - mif_err("ERR: exynos_cpufreq_get_level fail\n"); - return -EINVAL; - } - - if (exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level)) { - mif_err("ERR: exynos_cpufreq_lock fail\n"); - return -EINVAL; - } - - atomic_set(&umts_link_pm_data.freqlock, 1); - mif_debug("<%d> %d MHz\n", level, freq); - } - return 0; -} - -static int exynos_cpu_frequency_unlock(void) -{ - if (atomic_read(&umts_link_pm_data.freqlock) == 1) { - exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF); - atomic_set(&umts_link_pm_data.freqlock, 0); - mif_debug("\n"); - } - return 0; -} -#else -static int exynos_cpu_frequency_lock(void) -{ - return 0; -} - -static int exynos_cpu_frequency_unlock(void) -{ - return 0; -} -#endif - -void set_host_states(struct platform_device *pdev, int type) -{ -} - -static int usb3503_hub_handler(void (*set_mode)(void), void *ctl) -{ - if (!set_mode || !ctl) - return -EINVAL; - - usbhub_set_mode = (int (*)(struct usb3503_hubctl *, int))set_mode; - usbhub_ctl = (struct usb3503_hubctl *)ctl; - - mif_info("set_mode(%pF)\n", set_mode); - - return 0; -} - -static int usb3503_hw_config(void) -{ - int err; - - err = gpio_request(GPIO_USB_HUB_RST, "HUB_RST"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", "HUB_RST"); - } else { - gpio_direction_output(GPIO_USB_HUB_RST, 0); - s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE); - } - s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, S5P_GPIO_DRVSTR_LV1); - /* need to check drvstr 1 or 2 */ - - /* for USB3503 26Mhz Reference clock setting */ - err = gpio_request(GPIO_USB_HUB_INT, "HUB_INT"); - if (err) { - mif_err("ERR: fail to request gpio %s\n", "HUB_INT"); - } else { - gpio_direction_output(GPIO_USB_HUB_INT, 1); - s3c_gpio_setpull(GPIO_USB_HUB_INT, S3C_GPIO_PULL_NONE); - } - - return 0; -} - -static int usb3503_reset_n(int val) -{ - gpio_set_value(GPIO_USB_HUB_RST, 0); - - /* hub off from cpuidle(LPA), skip the msleep schedule*/ - if (val) { - msleep(20); - mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST)); - - gpio_set_value(GPIO_USB_HUB_RST, !!val); - - mif_info("val = %d\n", gpio_get_value(GPIO_USB_HUB_RST)); - udelay(5); /* need it ?*/ - } - return 0; -} - -static struct usb3503_platform_data usb3503_pdata = { - .initial_mode = USB3503_MODE_STANDBY, - .reset_n = usb3503_reset_n, - .register_hub_handler = usb3503_hub_handler, - .port_enable = host_port_enable, -}; - -static struct i2c_board_info i2c_devs20_emul[] __initdata = { - { - I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08), - .platform_data = &usb3503_pdata, - }, -}; - -/* I2C20_EMUL */ -static struct i2c_gpio_platform_data i2c20_platdata = { - .sda_pin = GPIO_USB_HUB_SDA, - .scl_pin = GPIO_USB_HUB_SCL, - /*FIXME: need to timming tunning... */ - .udelay = 20, -}; - -static struct platform_device s3c_device_i2c20 = { - .name = "i2c-gpio", - .id = 20, - .dev.platform_data = &i2c20_platdata, -}; - -static int __init init_usbhub(void) -{ - usb3503_hw_config(); - i2c_register_board_info(20, i2c_devs20_emul, - ARRAY_SIZE(i2c_devs20_emul)); - - platform_device_register(&s3c_device_i2c20); - return 0; -} - -device_initcall(init_usbhub); - -static int host_port_enable(int port, int enable) -{ - int err; - - mif_info("port(%d) control(%d)\n", port, enable); - - if (enable) { - err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_HUB); - if (err < 0) { - mif_err("ERR: hub on fail\n"); - goto exit; - } - err = s5p_ehci_port_control(&s5p_device_ehci, port, 1); - if (err < 0) { - mif_err("ERR: port(%d) enable fail\n", port); - goto exit; - } - } else { - err = s5p_ehci_port_control(&s5p_device_ehci, port, 0); - if (err < 0) { - mif_err("ERR: port(%d) enable fail\n", port); - goto exit; - } - err = usbhub_set_mode(usbhub_ctl, USB3503_MODE_STANDBY); - if (err < 0) { - mif_err("ERR: hub off fail\n"); - goto exit; - } - } - - err = gpio_direction_output(umts_modem_data.gpio_host_active, enable); - mif_info("active state err(%d), en(%d), level(%d)\n", - err, enable, gpio_get_value(umts_modem_data.gpio_host_active)); - -exit: - return err; -} -#else -void set_host_states(struct platform_device *pdev, int type) -{ - if (active_ctl.gpio_initialized) { - mif_err("<%s> Active States =%d, %s\n", pdev->name, type); - gpio_direction_output(umts_link_pm_data.gpio_link_active, type); - } else { - active_ctl.gpio_request_host_active = 1; - } -} -#endif - diff --git a/arch/arm/mach-exynos/board-gps-bcm475x.c b/arch/arm/mach-exynos/board-gps-bcm475x.c index 7b9a1c7..841c1de 100644 --- a/arch/arm/mach-exynos/board-gps-bcm475x.c +++ b/arch/arm/mach-exynos/board-gps-bcm475x.c @@ -6,10 +6,18 @@ #include <plat/gpio-cfg.h> #include <mach/board-gps.h> -#if !defined(CONFIG_MACH_M0_GRANDECTC) +#if !defined(CONFIG_MACH_M0_GRANDECTC) && !defined(CONFIG_MACH_M0_DUOSCTC) static struct device *gps_dev; +static ssize_t hwrev_show(struct device *dev, \ +struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%x\n", system_rev); +} + +static DEVICE_ATTR(hwrev, S_IRUGO, hwrev_show, NULL); + static int __init gps_bcm475x_init(void) { int n_rst_pin = 0; @@ -28,28 +36,32 @@ static int __init gps_bcm475x_init(void) s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_NONE); #ifdef CONFIG_MACH_P2 - n_rst_pin = GPIO_GPS_nRST_28V; - n_rst_nc_pin = GPIO_GPS_nRST; + n_rst_pin = system_rev >= 5 ? + GPIO_GPS_nRST_28V : GPIO_GPS_nRST; #else n_rst_pin = GPIO_GPS_nRST; - n_rst_nc_pin = 0; #endif - if (gpio_request(n_rst_pin, "GPS_nRST")) + if (gpio_request(n_rst_pin, "GPS_nRST")) { WARN(1, "fail to request gpio (GPS_nRST)\n"); + device_destroy(sec_class, gps_dev->devt); + return 1; + } + + if (device_create_file(gps_dev, &dev_attr_hwrev) < 0) { + pr_err("Failed to create device file(%s)!\n", + dev_attr_hwrev.attr.name); + } s3c_gpio_setpull(n_rst_pin, S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(n_rst_pin, S3C_GPIO_OUTPUT); gpio_direction_output(n_rst_pin, 1); - if (gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN")) + if (gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN")) { WARN(1, "fail to request gpio (GPS_PWR_EN)\n"); - -#ifdef CONFIG_MACH_P2 - gpio_set_value(n_rst_nc_pin, 0); - s3c_gpio_cfgpin(n_rst_nc_pin, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(n_rst_nc_pin, S3C_GPIO_PULL_NONE); -#endif + device_destroy(sec_class, gps_dev->devt); + return 1; + } s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT); @@ -61,6 +73,8 @@ static int __init gps_bcm475x_init(void) gpio_export_link(gps_dev, "GPS_nRST", n_rst_pin); gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN); + printk(KERN_DEBUG "%s - system_rev : %x\n", __func__, system_rev); + return 0; } diff --git a/arch/arm/mach-exynos/board-grande-camera.c b/arch/arm/mach-exynos/board-grande-camera.c new file mode 100755 index 0000000..2327b84 --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-camera.c @@ -0,0 +1,3468 @@ +/* + * camera class init + */ + +#include <linux/gpio.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/clk.h> +#include <linux/vmalloc.h> +#include <media/v4l2-device.h> +#include <linux/vmalloc.h> +#include <linux/firmware.h> +#include <linux/regulator/machine.h> +#include <linux/init.h> + +#include <plat/devs.h> +#include <plat/csis.h> +#include <plat/pd.h> +#include <plat/gpio-cfg.h> +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC +#include <plat/fimc-core.h> +#include <media/s5p_fimc.h> +#endif + +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE +#include <media/exynos_flite.h> +#endif + +#if defined(CONFIG_VIDEO_S5C73M3) || defined(CONFIG_VIDEO_SLP_S5C73M3) +#include <media/s5c73m3_platform.h> +#endif + +#if defined(CONFIG_VIDEO_M5MO) +#include <mach/regs-gpio.h> +#include <media/m5mo_platform.h> +#endif + +#if defined(CONFIG_VIDEO_M9MO) +#include <mach/regs-gpio.h> +#include <media/m9mo_platform.h> +#endif + +#if defined(CONFIG_VIDEO_ISX012) +#include <media/isx012_platform.h> +#endif +#if defined(CONFIG_VIDEO_S5K5CCGX_COMMON) +#include <media/s5k5ccgx_platform.h> +#endif + +#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION +#include <mach/secmem.h> +#endif + +#ifdef CONFIG_VIDEO_SR200PC20M +#include <media/sr200pc20m_platform.h> +#endif + +#ifdef CONFIG_VIDEO_SR200PC20 +#include <media/sr200pc20_platform.h> +#endif + +struct class *camera_class; + +static int __init camera_class_init(void) +{ + camera_class = class_create(THIS_MODULE, "camera"); + if (IS_ERR(camera_class)) { + pr_err("Failed to create class(camera)!\n"); + return PTR_ERR(camera_class); + } + + return 0; +} + +subsys_initcall(camera_class_init); + +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x06 +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x09 +#elif defined(CONFIG_MACH_C1_KOR_LGT) +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x04 +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x07 +#elif defined(CONFIG_MACH_C1_USA_ATT) +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x05 +#elif defined(CONFIG_MACH_M3) +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x0A +#else +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x08 +#endif + +#if defined(CONFIG_VIDEO_FIMC) +/* + * External camera reset + * Because the most of cameras take i2c bus signal, so that + * you have to reset at the boot time for other i2c slave devices. + * This function also called at fimc_init_camera() + * Do optimization for cameras on your platform. + */ + +#define CAM_CHECK_ERR_RET(x, msg) \ + if (unlikely((x) < 0)) { \ + printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \ + return x; \ + } +#define CAM_CHECK_ERR(x, msg) \ + if (unlikely((x) < 0)) { \ + printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \ + } +#define CAM_CHECK_ERR_GOTO(x, out, fmt, ...) \ + if (unlikely((x) < 0)) { \ + printk(KERN_ERR fmt, ##__VA_ARGS__); \ + goto out; \ + } + +int s3c_csis_power(int enable) +{ + struct regulator *regulator; + int ret = 0; + + /* mipi_1.1v ,mipi_1.8v are always powered-on. + * If they are off, we then power them on. + */ + if (enable) { + /* VMIPI_1.0V */ + regulator = regulator_get(NULL, "vmipi_1.0v"); + if (IS_ERR(regulator)) + goto error_out; + regulator_enable(regulator); + regulator_put(regulator); + + /* VMIPI_1.8V */ + regulator = regulator_get(NULL, "vmipi_1.8v"); + if (IS_ERR(regulator)) + goto error_out; + regulator_enable(regulator); + regulator_put(regulator); + + printk(KERN_WARNING "%s: vmipi_1.0v and vmipi_1.8v were ON\n", + __func__); + } else { + /* VMIPI_1.8V */ + regulator = regulator_get(NULL, "vmipi_1.8v"); + if (IS_ERR(regulator)) + goto error_out; + if (regulator_is_enabled(regulator)) { + printk(KERN_WARNING "%s: vmipi_1.8v is on. so OFF\n", + __func__); + ret = regulator_disable(regulator); + } + regulator_put(regulator); + + /* VMIPI_1.0V */ + regulator = regulator_get(NULL, "vmipi_1.0v"); + if (IS_ERR(regulator)) + goto error_out; + if (regulator_is_enabled(regulator)) { + printk(KERN_WARNING "%s: vmipi_1.1v is on. so OFF\n", + __func__); + ret = regulator_disable(regulator); + } + regulator_put(regulator); + + printk(KERN_WARNING "%s: vmipi_1.0v and vmipi_1.8v were OFF\n", + __func__); + } + + return 0; + +error_out: + printk(KERN_ERR "%s: ERROR: failed to check mipi-power\n", __func__); + return 0; +} + +#ifdef CONFIG_WRITEBACK_ENABLED +#define WRITEBACK_ENABLED +#endif +#ifdef WRITEBACK_ENABLED +static int get_i2c_busnum_writeback(void) +{ + return 0; +} + +static struct i2c_board_info writeback_i2c_info = { + I2C_BOARD_INFO("WriteBack", 0x0), +}; + +static struct s3c_platform_camera writeback = { + .id = CAMERA_WB, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .get_i2c_busnum = get_i2c_busnum_writeback, + .info = &writeback_i2c_info, + .pixelformat = V4L2_PIX_FMT_YUV444, + .line_length = 1280, + .width = 720, + .height = 1280, + .window = { + .left = 0, + .top = 0, + .width = 720, + .height = 1280, + }, + + .initialized = 0, +}; +#endif + +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS +#ifdef CONFIG_VIDEO_S5K6A3 +#ifdef CONFIG_MACH_P4NOTE +/* For P4Note PegasusQ */ +static int s5k6a3_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + ret = gpio_request(GPIO_VT_CAM_nRST, "GPJ1"); + if (unlikely(ret)) { + printk(KERN_ERR "request GPIO_VT_CAM_nRST\n"); + return ret; + } + + /* VT_CAM_2.8V */ + regulator = regulator_get(NULL, "cam_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "cam_a2.8v"); + udelay(100); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_NONE); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + udelay(1); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_core_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "vt_core_1.8v"); + udelay(1000); + + /* VT_CAM_nRST */ + ret = gpio_direction_output(GPIO_VT_CAM_nRST, 1); + CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST"); + udelay(600); + + ret = gpio_direction_output(GPIO_VT_CAM_nRST, 0); + CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST"); + udelay(600); + + ret = gpio_direction_output(GPIO_VT_CAM_nRST, 1); + CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST"); + + gpio_free(GPIO_VT_CAM_nRST); + + return ret; +} + +static int s5k6a3_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + ret = gpio_request(GPIO_VT_CAM_nRST, "GPJ1"); + if (unlikely(ret)) { + printk(KERN_ERR "request GPIO_VT_CAM_nRST\n"); + return ret; + } + + /* VT_CAM_nRST */ + ret = gpio_direction_output(GPIO_VT_CAM_nRST, 0); + CAM_CHECK_ERR_RET(ret, "GPIO_VT_CAM_nRST"); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_core_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "vt_core_1.8v"); + + + /* VT_CAM_2.8V */ + regulator = regulator_get(NULL, "cam_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "cam_a2.8v"); + udelay(100); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + udelay(1); + + gpio_free(GPIO_VT_CAM_nRST); + + return ret; +} +#else /* !CONFIG_MACH_P4NOTE */ +static int s5k6a3_gpio_request(void) +{ + int ret = 0; + + /* SENSOR_A2.8V */ + ret = gpio_request(GPIO_CAM_IO_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_CAM_IO_EN)\n"); + return ret; + } + + if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) + ret = gpio_request(GPIO_CAM_MCLK, "GPJ1"); + else + ret = gpio_request(GPIO_VTCAM_MCLK, "GPM2"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_VTCAM_MCLK)\n"); + return ret; + } + + ret = gpio_request(GPIO_CAM_VT_nRST, "GPM1"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_CAM_VT_nRST)\n"); + return ret; + } + + return ret; +} + +static int s5k6a3_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + s5k6a3_gpio_request(); + + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_IO_EN"); + /* delay is needed : external LDO control is slower than MCLK control*/ + udelay(100); + + /* MCLK */ + if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) { + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV2); + } else { + ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(GPIO_VTCAM_MCLK, S5P_GPIO_DRVSTR_LV2); + } + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + + /* VT_CORE_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable vt_cam_1.8v"); + udelay(1000); + + /* VT_2.8V */ + regulator = regulator_get(NULL, "vt_cam_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable vt_cam_2.8v"); + udelay(100); + + /* VT_RESET */ + ret = gpio_direction_output(GPIO_CAM_VT_nRST, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST"); + udelay(600); + + ret = gpio_direction_output(GPIO_CAM_VT_nRST, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST"); + udelay(600); + + ret = gpio_direction_output(GPIO_CAM_VT_nRST, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST"); + + gpio_free(GPIO_CAM_IO_EN); + gpio_free(GPIO_CAM_VT_nRST); + if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) + gpio_free(GPIO_CAM_MCLK); + else + gpio_free(GPIO_VTCAM_MCLK); + + return ret; +} + +static int s5k6a3_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + s5k6a3_gpio_request(); + + /* VT_RESET */ + ret = gpio_direction_output(GPIO_CAM_VT_nRST, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_VT_nRST"); + + /* VT_2.8V */ + regulator = regulator_get(NULL, "vt_cam_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable vt_cam_2.8v"); + + /* VT_CORE_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable vt_cam_1.8v"); + + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_IO_EN"); + /* delay is needed : external LDO control is slower than MCLK control*/ + udelay(500); + + /* MCLK */ + if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) { + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + + } else { + ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_DOWN); + } + CAM_CHECK_ERR(ret, "cfg mclk"); + + gpio_free(GPIO_CAM_IO_EN); + gpio_free(GPIO_CAM_VT_nRST); + + if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) + gpio_free(GPIO_CAM_MCLK); + else + gpio_free(GPIO_VTCAM_MCLK); + + return ret; +} +#endif /* CONFIG_MACH_P4NOTE */ + +static int s5k6a3_power(int enable) +{ + int ret = 0; + + if (enable) { + ret = s5k6a3_power_on(); + if (unlikely(ret)) { + printk(KERN_ERR "%s: power-on fail\n", __func__); + goto error_out; + } + } else + ret = s5k6a3_power_down(); + + ret = s3c_csis_power(enable); + +error_out: + return ret; +} + +static const char *s5k6a3_get_clk_name(void) +{ +#ifdef CONFIG_MACH_P4NOTE + return "sclk_cam1"; +#else + if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) + return "sclk_cam0"; + else + return "sclk_cam1"; +#endif +} + +static struct s3c_platform_camera s5k6a3 = { + .id = CAMERA_CSI_D, + .get_clk_name = s5k6a3_get_clk_name, + .cam_power = s5k6a3_power, + .type = CAM_TYPE_MIPI, + .fmt = MIPI_CSI_RAW10, + .order422 = CAM_ORDER422_8BIT_YCBYCR, + .pixelformat = V4L2_PIX_FMT_UYVY, + .line_length = 1920, + .width = 1920, + .height = 1080, + .window = { + .left = 0, + .top = 0, + .width = 1920, + .height = 1080, + }, + .srclk_name = "xusbxti", + .clk_rate = 24000000, + .mipi_lanes = 1, + .mipi_settle = 18, + .mipi_align = 24, + + .initialized = 0, + .flite_id = FLITE_IDX_B, + .use_isp = true, + .sensor_index = 102, +}; + +#ifdef CONFIG_S5K6A3_CSI_D +static struct s3c_platform_camera s5k6a3_fd = { + .id = CAMERA_CSI_D, + .get_clk_name = s5k6a3_get_clk_name, + .cam_power = s5k6a3_power, + .type = CAM_TYPE_MIPI, + .fmt = MIPI_CSI_RAW10, + .order422 = CAM_ORDER422_8BIT_YCBYCR, + .pixelformat = V4L2_PIX_FMT_UYVY, + .line_length = 1920, + .width = 1920, + .height = 1080, + .window = { + .left = 0, + .top = 0, + .width = 1920, + .height = 1080, + }, + .srclk_name = "xusbxti", + .clk_rate = 24000000, + .mipi_lanes = 1, + .mipi_settle = 18, + .mipi_align = 24, + + .initialized = 0, + .flite_id = FLITE_IDX_B, + .use_isp = true, + .sensor_index = 200, +}; +#endif +#endif +#endif + +#if defined(CONFIG_VIDEO_S5C73M3) || defined(CONFIG_VIDEO_SLP_S5C73M3) +static int vddCore = 1150000; +static bool isVddCoreSet; +static void s5c73m3_set_vdd_core(int level) +{ + vddCore = level; + isVddCoreSet = true; + printk(KERN_ERR "%s : %d\n", __func__, vddCore); +} + +static void s5c73m3_check_vdd_core(void) +{ + struct file *fp; + mm_segment_t old_fs; + u8 *buf = NULL; + int err = 0; + int nread = 0; + int voltage = 0; + int count = 0; + + if (!isVddCoreSet) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + + fp = filp_open("/data/ISP_CV", O_RDONLY, 0); + if (IS_ERR(fp)) { + printk(KERN_ERR "failed open file. :: %ld\n", + PTR_ERR(fp)); + set_fs(old_fs); + return; + } + + buf = vmalloc(10); + if (!buf) { + printk(KERN_ERR "failed to allocate memory\n"); + err = -ENOMEM; + goto out; + } + + nread = vfs_read(fp, (char __user *)buf, 10, &fp->f_pos); + if (nread != 10) { + printk(KERN_ERR "failed to read file, %d Bytes\n", + nread); + err = -EIO; + goto out; + } + + while (buf[count] != '\0' && + buf[count] >= '0' && buf[count] <= '9') { + voltage = voltage * 10 + buf[count] - '0'; + ++count; + } + + if (voltage == 1000000 || voltage == 1050000 || + voltage == 1100000 || voltage == 1150000) { + printk(KERN_ERR "@@@@ Voltage = %d", voltage); + vddCore = voltage; + /*isVddCoreSet = true;*/ + } +out: + if (buf != NULL) + vfree(buf); + + if (fp != NULL) + filp_close(fp, current->files); + + set_fs(old_fs); + } +} +static bool s5c73m3_is_vdd_core_set(void) +{ + return isVddCoreSet; +} + +static int s5c73m3_is_isp_reset(void) +{ + int ret = 0; + + ret = gpio_request(GPIO_ISP_RESET, "GPF1"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET"); + udelay(10); /* 200 cycle */ + ret = gpio_direction_output(GPIO_ISP_RESET, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET"); + udelay(10); /* 200 cycle */ + + gpio_free(GPIO_ISP_RESET); + + return ret; +} + +static int s5c73m3_gpio_request(void) +{ + int ret = 0; + + ret = gpio_request(GPIO_ISP_STANDBY, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_STANDBY)\n"); + return ret; + } + + ret = gpio_request(GPIO_ISP_RESET, "GPF1"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + + /* SENSOR_A2.8V */ + ret = gpio_request(GPIO_CAM_IO_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_CAM_IO_EN)\n"); + return ret; + } + + ret = gpio_request(GPIO_CAM_AF_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_AF_EN)\n"); + return ret; + } + + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_ISP_CORE_EN)\n"); + return ret; + } + +#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) + if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) { + ret = gpio_request(GPIO_CAM_SENSOR_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_CAM_SENSOR_CORE_EN)\n"); + return ret; + } + } +#endif + + return ret; +} + +static void s5c73m3_gpio_free(void) +{ + gpio_free(GPIO_ISP_STANDBY); + gpio_free(GPIO_ISP_RESET); + gpio_free(GPIO_CAM_IO_EN); + gpio_free(GPIO_CAM_AF_EN); + gpio_free(GPIO_ISP_CORE_EN); + +#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) + if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) + gpio_free(GPIO_CAM_SENSOR_CORE_EN); +#endif +} + +static int s5c73m3_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + +#ifndef CONFIG_VIDEO_SLP_S5C73M3 + s5c73m3_check_vdd_core(); +#endif + printk(KERN_DEBUG "s5c73m3 vddCore : %d\n", vddCore); + + s5c73m3_gpio_request(); + + /* CAM_ISP_CORE_1.2V */ + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN"); + +#if !defined(CONFIG_MACH_GRANDE) + regulator = regulator_get(NULL, "cam_isp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + regulator_set_voltage(regulator, vddCore, vddCore); + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v"); +#endif + + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 1); + CAM_CHECK_ERR_RET(ret, "output IO_EN"); + + /* CAM_SENSOR_CORE_1.2V */ +#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) + if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) { + ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE_EN, 1); + CAM_CHECK_ERR_RET(ret, "output CAM_SENSOR_CORE_EN"); + mdelay(5); + } else { + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v"); + /* delay is needed : pmu control is slower than gpio control*/ + mdelay(5); + } +#else + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v"); + /* delay is needed : pmu control is slower than gpio control*/ + mdelay(5); +#endif + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV3); + + /* CAM_AF_2.8V */ + ret = gpio_direction_output(GPIO_CAM_AF_EN, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_AF_EN"); + udelay(2000); + + /* CAM_ISP_SENSOR_1.8V */ + regulator = regulator_get(NULL, "cam_isp_sensor_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_sensor_1.8v"); + + /* CAM_ISP_MIPI_1.2V */ + regulator = regulator_get(NULL, "cam_isp_mipi_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_mipi_1.2v"); + /* delay is needed : pmu control is slower than gpio control*/ + mdelay(5); + + /* ISP_STANDBY */ + ret = gpio_direction_output(GPIO_ISP_STANDBY, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_STANDBY"); + udelay(100); /* 2000 cycle */ + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET"); + udelay(10); /* 200 cycle */ + + s5c73m3_gpio_free(); + + return ret; +} + +static int s5c73m3_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + s5c73m3_gpio_request(); + + /* ISP_STANDBY */ + ret = gpio_direction_output(GPIO_ISP_STANDBY, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_STANDBY"); + udelay(2); /* 40 cycle */ + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_RESET"); + + /* CAM_AF_2.8V */ + ret = gpio_direction_output(GPIO_CAM_AF_EN, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_AF_EN"); + + /* CAM_ISP_MIPI_1.2V */ + regulator = regulator_get(NULL, "cam_isp_mipi_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_isp_mipi_1.2v"); + udelay(10); /* 200 cycle */ + + /* CAM_ISP_SENSOR_1.8V */ + regulator = regulator_get(NULL, "cam_isp_sensor_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_isp_sensor_1.8v"); + + /* CAM_SENSOR_CORE_1.2V */ +#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) + if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) { + ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE_EN, 0); + CAM_CHECK_ERR_RET(ret, "output CAM_SENSOR_CORE_EN"); + udelay(500); + } else { + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v"); + /* delay is needed : hw request*/ + udelay(500); + } +#else + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v"); + /* delay is needed : hw request*/ + udelay(500); +#endif + + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_IO_EN"); + +#if !defined(CONFIG_MACH_GRANDE) + /* CAM_ISP_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_isp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_isp_core_1.2v"); +#endif + + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0); + CAM_CHECK_ERR_RET(ret, "output GPIO_CAM_ISP_CORE_EN"); + /* delay is needed : hw request*/ + mdelay(30); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + + s5c73m3_gpio_free(); + + return ret; +} + +static int s5c73m3_power(int enable) +{ + int ret = 0; + + if (enable) { + ret = s5c73m3_power_on(); + + if (unlikely(ret)) + goto error_out; + } else + ret = s5c73m3_power_down(); + + ret = s3c_csis_power(enable); + +error_out: + return ret; +} + +static int s5c73m3_get_i2c_busnum(void) +{ + return 0; +} + +static const char *s5c73m3_get_clk_name(void) +{ + return "sclk_cam0"; +} + +static struct s5c73m3_platform_data s5c73m3_plat = { + .default_width = 640, /* 1920 */ + .default_height = 480, /* 1080 */ + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, + .set_vdd_core = s5c73m3_set_vdd_core, + .is_vdd_core_set = s5c73m3_is_vdd_core_set, + .is_isp_reset = s5c73m3_is_isp_reset, + .power_on_off = s5c73m3_power, +}; + +static struct i2c_board_info s5c73m3_i2c_info = { + I2C_BOARD_INFO("S5C73M3", 0x78 >> 1), + .platform_data = &s5c73m3_plat, +}; + +static struct s3c_platform_camera s5c73m3 = { + .id = CAMERA_CSI_C, + .get_clk_name = s5c73m3_get_clk_name, + .get_i2c_busnum = s5c73m3_get_i2c_busnum, + .cam_power = s5c73m3_power, + .type = CAM_TYPE_MIPI, + .fmt = MIPI_CSI_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR, + .info = &s5c73m3_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", /* "mout_mpll" */ + .clk_rate = 24000000, /* 48000000 */ + .line_length = 1920, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + .mipi_lanes = 4, + .mipi_settle = 12, + .mipi_align = 32, + + /* Polarity */ + .inv_pclk = 1, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, +}; +#endif + +#ifdef CONFIG_VIDEO_M5MO +static int m5mo_get_i2c_busnum(void) +{ +#ifdef CONFIG_VIDEO_M5MO_USE_SWI2C + return 25; +#else + return 0; +#endif +} + +static int m5mo_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_RESET, "GPY3"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + /* CAM_VT_nSTBY low */ + ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "output VT_nSTBY"); + + /* CAM_VT_nRST low */ + gpio_direction_output(GPIO_CAM_VT_nRST, 0); + CAM_CHECK_ERR_RET(ret, "output VT_nRST"); + udelay(10); + + /* CAM_ISP_CORE_1.2V */ + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN"); + + regulator = regulator_get(NULL, "cam_isp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v"); + udelay(10); + /* CAM_SENSOR_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v"); + udelay(10); + + /* CAM_SENSOR_A2.8V */ + regulator = regulator_get(NULL, "cam_sensor_a2.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_a2.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_a2.8v"); + /* it takes about 100us at least during level transition.*/ + udelay(160); /* 130us -> 160us */ + /* VT_CAM_DVDD_1.8V */ + regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable vt_cam_dvdd_1.8v"); + udelay(10); + + /* CAM_AF_2.8V */ + regulator = regulator_get(NULL, "cam_af_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "output cam_af_2.8v"); + mdelay(7); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err vt_cam_1.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable vt_cam_1.8v"); + udelay(20); + + /* CAM_ISP_1.8V */ + regulator = regulator_get(NULL, "cam_isp_1.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_isp_1.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_1.8v"); + udelay(120); /* at least */ + + /* CAM_ISP_SEN_IO_1.8V */ + regulator = regulator_get(NULL, "cam_isp_sensor_1.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_isp_sensor_1.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_sensor_1.8v"); + udelay(30); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + udelay(70); + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 1); + CAM_CHECK_ERR_RET(ret, "output reset"); + mdelay(4); + + gpio_free(GPIO_CAM_VT_nSTBY); + gpio_free(GPIO_CAM_VT_nRST); + gpio_free(GPIO_ISP_CORE_EN); + gpio_free(GPIO_ISP_RESET); + + return ret; +} + +static int m5mo_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_RESET, "GPY3"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + + /* s3c_i2c0_force_stop(); */ + + mdelay(3); + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 0); + CAM_CHECK_ERR(ret, "output reset"); + mdelay(2); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + udelay(20); + + /* CAM_AF_2.8V */ + regulator = regulator_get(NULL, "cam_af_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_af_2.8v"); + + /* CAM_ISP_SEN_IO_1.8V */ + regulator = regulator_get(NULL, "cam_isp_sensor_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable, cam_isp_sensor_1.8v"); + udelay(10); + + /* CAM_ISP_1.8V */ + regulator = regulator_get(NULL, "cam_isp_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_isp_1.8v"); + udelay(500); /* 100us -> 500us */ + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable vt_cam_1.8v"); + udelay(250); /* 10us -> 250us */ + + /* VT_CAM_DVDD_1.8V */ + regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable vt_cam_dvdd_1.8v"); + udelay(300); /*10 -> 300 us */ + + /* CAM_SENSOR_A2.8V */ + regulator = regulator_get(NULL, "cam_sensor_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_a2.8v"); + udelay(800); + + /* CAM_SENSOR_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v"); + udelay(5); + + /* CAM_ISP_CORE_1.2V */ + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0); + CAM_CHECK_ERR(ret, "output ISP_CORE"); + + regulator = regulator_get(NULL, "cam_isp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "disable cam_isp_core_1.2v"); + + gpio_free(GPIO_CAM_VT_nSTBY); + gpio_free(GPIO_CAM_VT_nRST); + gpio_free(GPIO_ISP_CORE_EN); + gpio_free(GPIO_ISP_RESET); + + return ret; +} + +static int m5mo_flash_power(int enable) +{ +/* TODO */ + return 0; +} + +static int m5mo_power(int enable) +{ + int ret = 0; + + printk(KERN_ERR "%s %s\n", __func__, enable ? "on" : "down"); + if (enable) { + ret = m5mo_power_on(); + if (unlikely(ret)) + goto error_out; + } else + ret = m5mo_power_down(); + + ret = s3c_csis_power(enable); + m5mo_flash_power(enable); + +error_out: + return ret; +} + +static int m5mo_config_isp_irq(void) +{ + s3c_gpio_cfgpin(GPIO_ISP_INT, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(GPIO_ISP_INT, S3C_GPIO_PULL_NONE); + return 0; +} + +static const char *m5mo_get_clk_name(void) +{ + return "sclk_cam0"; +} + +static struct m5mo_platform_data m5mo_plat = { + .default_width = 640, /* 1920 */ + .default_height = 480, /* 1080 */ + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, + .config_isp_irq = m5mo_config_isp_irq, + .irq = IRQ_EINT(24), +}; + +static struct i2c_board_info m5mo_i2c_info = { + I2C_BOARD_INFO("M5MO", 0x1F), + .platform_data = &m5mo_plat, +}; + +static struct s3c_platform_camera m5mo = { + .id = CAMERA_CSI_C, + .get_clk_name = m5mo_get_clk_name, + .get_i2c_busnum = m5mo_get_i2c_busnum, + .cam_power = m5mo_power, /*smdkv310_mipi_cam0_reset,*/ + .type = CAM_TYPE_MIPI, + .fmt = ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/ + .order422 = CAM_ORDER422_8BIT_CBYCRY, + + .info = &m5mo_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", /* "mout_mpll" */ + .clk_rate = 24000000, /* 48000000 */ + .line_length = 1920, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + .mipi_lanes = 2, + .mipi_settle = 12, + .mipi_align = 32, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, +}; +#endif /* #ifdef CONFIG_VIDEO_M5MO */ + +#ifdef CONFIG_VIDEO_M9MO +static int m9mo_get_i2c_busnum(void) +{ + return 0; +} + +static int m9mo_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n"); + return ret; + } + + ret = gpio_request(GPIO_ISP_RESET, "GPF1"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + /* CAM_ISP_CORE_EN */ + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN"); + + /* CAM_ISP_1.2V (ISP 1.2V) => BUCK 9*/ + regulator = regulator_get(NULL, "cam_isp_1.2v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_isp_1.2v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_1.2v"); + + /* CAM_SENSOR_CORE_1.2V (CIS 1.2V) => LDO17*/ + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v"); + + /* CAM_ISP_1.8V (ISP 1.8V) => LDO23*/ + regulator = regulator_get(NULL, "cam_isp_1.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_isp_1.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_1.8v"); + + /* CAM_SENSOR_1.8V (CIS 1.8V) => LDO19*/ + regulator = regulator_get(NULL, "cam_sensor_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_1.8v"); + + /* CAM_SENSOR_2.8V (CIS 2.8V) => LDO25*/ + regulator = regulator_get(NULL, "cam_sensor_2.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_2.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_2.8v"); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + udelay(70); + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 1); + CAM_CHECK_ERR_RET(ret, "output reset"); + mdelay(4); + + gpio_free(GPIO_ISP_CORE_EN); + gpio_free(GPIO_ISP_RESET); + + return ret; +} + +static int m9mo_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s: in\n", __func__); + + if (system_rev > 0) { + ret = gpio_request(GPIO_MOT_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_MOT_EN)\n"); + return ret; + } + ret = gpio_request(GPIO_SAMBAZ_RESET, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_SAMBAZ_RESET)\n"); + return ret; + } + } + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n"); + return ret; + } + + ret = gpio_request(GPIO_ISP_RESET, "GPF1"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + /* s3c_i2c0_force_stop(); */ + + mdelay(3); + + /*MOT_3.3*/ + regulator = regulator_get(NULL, "mot_3.3v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "mot_3.3v"); + + /*OIS_1.5*/ + regulator = regulator_get(NULL, "ois_1.5v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable ois_1.5v"); + msleep(10); + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 0); + CAM_CHECK_ERR(ret, "output reset"); + mdelay(2); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + udelay(20); + + /* CAM_SENSOR_2.8V (CIS 2.8V) => LDO25*/ + regulator = regulator_get(NULL, "cam_sensor_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_2.8v"); + + /* CAM_SENSOR_1.8V (CIS 1.8V) => LDO19*/ + regulator = regulator_get(NULL, "cam_sensor_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_1.8v"); + + /* CAM_ISP_1.8V (ISP 1.8V) => LDO23*/ + regulator = regulator_get(NULL, "cam_isp_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_isp_1.8v"); + + /* CAM_SENSOR_CORE_1.2V (CIS 1.2V) => LDO17*/ + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v"); + + /* CAM_ISP_1.2V (ISP 1.2V) => BUCK 9*/ + regulator = regulator_get(NULL, "cam_isp_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable, cam_isp_1.2v"); + + /* CAM_ISP_CORE_1.2V */ + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0); + CAM_CHECK_ERR(ret, "output ISP_CORE"); + + if (system_rev > 0) { + ret = gpio_direction_output(GPIO_SAMBAZ_RESET, 0); + CAM_CHECK_ERR(ret, "output GPIO_SAMBAZ_RESET"); + mdelay(100); + + ret = gpio_direction_output(GPIO_MOT_EN, 0); + CAM_CHECK_ERR(ret, "output GPIO_MOT_EN"); + mdelay(2); + + gpio_free(GPIO_MOT_EN); + gpio_free(GPIO_SAMBAZ_RESET); + } + gpio_free(GPIO_ISP_CORE_EN); + gpio_free(GPIO_ISP_RESET); + + return ret; +} + +static int m9mo_flash_power(int enable) +{ +/* TODO */ + return 0; +} + +static int m9mo_power(int enable) +{ + int ret = 0; + + printk(KERN_ERR "%s %s\n", __func__, enable ? "on" : "down"); + if (enable) { + ret = m9mo_power_on(); + if (unlikely(ret)) + goto error_out; + } else + ret = m9mo_power_down(); + + ret = s3c_csis_power(enable); + m9mo_flash_power(enable); + +error_out: + return ret; +} + +static int m9mo_config_isp_irq(void) +{ +printk(KERN_ERR "m9mo_config_isp_irq~~~~~~~~~~\n"); + s3c_gpio_cfgpin(GPIO_ISP_INT, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(GPIO_ISP_INT, S3C_GPIO_PULL_NONE); + return 0; +} + +static int m9mo_config_sambaz(int enable) +{ + struct regulator *regulator; + int ret = 0; + + if (enable) { + if (system_rev > 0) { + ret = gpio_request(GPIO_MOT_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n"); + return ret; + } + ret = gpio_request(GPIO_SAMBAZ_RESET, "GPM0"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + ret = gpio_direction_output(GPIO_MOT_EN, 1); + CAM_CHECK_ERR(ret, "output reset"); + msleep(100); + } + + regulator = regulator_get(NULL, "mot_3.3v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "mot_3.3v"); + mdelay(100); + + regulator = regulator_get(NULL, "ois_1.5v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "ois_1.5v"); + mdelay(10); + + if (system_rev > 0) { + ret = gpio_direction_output(GPIO_SAMBAZ_RESET, 1); + CAM_CHECK_ERR(ret, "output reset"); + msleep(100); + + gpio_free(GPIO_MOT_EN); + gpio_free(GPIO_SAMBAZ_RESET); + } + + } else { + regulator = regulator_get(NULL, "mot_3.3v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "mot_3.3v"); + + regulator = regulator_get(NULL, "ois_1.5v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable ois_1.5v"); + } + return ret; +} + +static const char *m9mo_get_clk_name(void) +{ + return "sclk_cam0"; +} + +static struct m9mo_platform_data m9mo_plat = { + .default_width = 640, /* 1920 */ + .default_height = 480, /* 1080 */ + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, + .config_isp_irq = m9mo_config_isp_irq, + .config_sambaz = m9mo_config_sambaz, + .irq = IRQ_EINT(2), +}; + +static struct i2c_board_info m9mo_i2c_info = { + I2C_BOARD_INFO("M9MO", 0x1F), + .platform_data = &m9mo_plat, +}; + +static struct s3c_platform_camera m9mo = { + .id = CAMERA_CSI_C, + .get_clk_name = m9mo_get_clk_name, + .get_i2c_busnum = m9mo_get_i2c_busnum, + .cam_power = m9mo_power, /*smdkv310_mipi_cam0_reset,*/ + .type = CAM_TYPE_MIPI, + .fmt = ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/ + .order422 = CAM_ORDER422_8BIT_CBYCRY, + + .info = &m9mo_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", /* "mout_mpll" */ + .clk_rate = 24000000, /* 48000000 */ + .line_length = 1920, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + .mipi_lanes = 4, + .mipi_settle = 12, + .mipi_align = 32, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, +}; +#endif /* #ifdef CONFIG_VIDEO_M9MO */ + +#ifdef CONFIG_VIDEO_ISX012 +static int isx012_get_i2c_busnum(void) +{ + return 0; +} + +static void isx012_flashtimer_handler(unsigned long data) +{ + int ret = -ENODEV; + atomic_t *flash_status = (atomic_t *)data; + + pr_info("********** flashtimer_handler **********\n"); + + ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 0); + atomic_set(flash_status, ISX012_FLASH_OFF); + if (unlikely(ret)) + pr_err("flash_timer: ERROR, failed to oneshot flash off\n"); + +} + +static atomic_t flash_status = ATOMIC_INIT(ISX012_FLASH_OFF); +static int isx012_flash_en(u32 mode, u32 onoff) +{ + static int flash_mode = ISX012_FLASH_MODE_NORMAL; + static DEFINE_MUTEX(flash_lock); + static DEFINE_TIMER(flash_timer, isx012_flashtimer_handler, + 0, (unsigned long)&flash_status); + int ret = 0; + + printk(KERN_DEBUG "flash_en: mode=%d, on=%d\n", mode, onoff); + + if (unlikely((u32)mode >= ISX012_FLASH_MODE_MAX)) { + pr_err("flash_en: ERROR, invalid flash mode(%d)\n", mode); + return -EINVAL; + } + + /* We could not use spin lock because of gpio kernel API.*/ + mutex_lock(&flash_lock); + if (atomic_read(&flash_status) == onoff) { + mutex_unlock(&flash_lock); + pr_warn("flash_en: WARNING, already flash %s\n", + onoff ? "On" : "Off"); + return 0; + } + + switch (onoff) { + case ISX012_FLASH_ON: + if (mode == ISX012_FLASH_MODE_MOVIE) + ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 1); + else { + ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 1); + flash_timer.expires = get_jiffies_64() + HZ / 2; + add_timer(&flash_timer); + } + CAM_CHECK_ERR_GOTO(ret, out, + "flash_en: ERROR, fail to turn flash on (mode:%d)\n", + mode); + flash_mode = mode; + break; + + case ISX012_FLASH_OFF: + if (unlikely(flash_mode != mode)) { + pr_err("flash_en: ERROR, unmatched flash mode(%d, %d)\n", + flash_mode, mode); + WARN_ON(1); + goto out; + } + + if (mode == ISX012_FLASH_MODE_MOVIE) + ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 0); + else { + if (del_timer_sync(&flash_timer)) { + pr_info("flash_en: terminate flash timer...\n"); + ret = gpio_direction_output(GPIO_CAM_FLASH_EN, + 0); + } + } + CAM_CHECK_ERR_GOTO(ret, out, + "flash_en: ERROR, flash off (mode:%d)\n", mode); + break; + + default: + pr_err("flash_en: ERROR, invalid flash cmd(%d)\n", onoff); + goto out; + break; + } + + atomic_set(&flash_status, onoff); + +out: + mutex_unlock(&flash_lock); + return 0; +} + +static int isx012_is_flash_on(void) +{ + return atomic_read(&flash_status); +} + +/* Power up/down func for P4C, P2. */ +static int isx012_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "[ISX012] power on\n"); + +#ifndef USE_CAM_GPIO_CFG + ret = gpio_request(GPIO_5M_nSTBY, "GPJ0"); + if (unlikely(ret)) { + printk(KERN_ERR "error: request 5M_nSTBY\n"); + return ret; + } + ret = gpio_request(GPIO_5M_nRST, "GPL1"); + if (unlikely(ret)) { + printk(KERN_ERR "error: request 5M_nRST\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_EN2, "GPJ0"); + if (unlikely(ret)) { + printk(KERN_ERR "error: request CAM_EN2\n"); + return ret; + } +#endif + + /* 5MP_CORE_1.2V */ + regulator = regulator_get(NULL, "3mp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "3mp_core_1.2v"); + udelay(10); + + /* CAM_IO_1.8V */ + regulator = regulator_get(NULL, "cam_io_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "cam_io_1.8v"); + udelay(10); + + /* CAM_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_EN2, 1); + CAM_CHECK_ERR_RET(ret, "CAM_A2.8V"); + udelay(200); + + /* CAM_MCLK */ + /*s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV2);*/ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + udelay(10); + + /* 3M_nRST */ + ret = gpio_direction_output(GPIO_5M_nRST, 1); + CAM_CHECK_ERR_RET(ret, "3M_nRST"); + udelay(10); + + /* 5MP_AF_2.8V */ + regulator = regulator_get(NULL, "3mp_af_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "3mp_af_2.8v"); + usleep_range(6000, 6500); + +#ifndef USE_CAM_GPIO_CFG + gpio_free(GPIO_5M_nSTBY); + gpio_free(GPIO_5M_nRST); + gpio_free(GPIO_CAM_EN2); +#endif + + return ret; +} + +static int isx012_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "[ISX012] power down\n"); + + ret = gpio_request(GPIO_5M_nSTBY, "GPJ0"); + if (unlikely(ret)) { + printk(KERN_ERR "error: request 3M_nSTBY\n"); + return ret; + } + ret = gpio_request(GPIO_5M_nRST, "GPL1"); + if (unlikely(ret)) { + printk(KERN_ERR "error: request 3M_nRST\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_EN2, "GPJ0"); + if (unlikely(ret)) { + printk(KERN_ERR "error: request CAM_EN2\n"); + return ret; + } + + /* 5MP_AF_2.8V */ + regulator = regulator_get(NULL, "3mp_af_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + CAM_CHECK_ERR_RET(ret, "3mp_af_2.8v"); + udelay(10); + + /* 5M_nSTBY */ + ret = gpio_direction_output(GPIO_5M_nSTBY, 0); + CAM_CHECK_ERR(ret, "5M_nSTBY"); + udelay(10); + + /* 5M_nRST */ + ret = gpio_direction_output(GPIO_5M_nRST, 0); + CAM_CHECK_ERR(ret, "5M_nRST"); + udelay(50); + + /* CAM_MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + udelay(10); + + /* CAM_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_EN2, 0); + CAM_CHECK_ERR_RET(ret, "CAM_A2.8V"); + udelay(10); + + /* CAM_IO_1.8V */ + regulator = regulator_get(NULL, "cam_io_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "cam_io_1.8v"); + udelay(10); + + /* 5MP_CORE_1.2V */ + regulator = regulator_get(NULL, "3mp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "3mp_core_1.2v"); + + gpio_free(GPIO_5M_nSTBY); + gpio_free(GPIO_5M_nRST); + gpio_free(GPIO_CAM_EN2); + + return ret; +} + +static int isx012_power(int enable) +{ + int ret = 0; + + if (enable) { + ret = isx012_power_on(); + } else + ret = isx012_power_down(); + + if (unlikely(ret)) { + pr_err("%s: power-on/down failed\n", __func__); + return ret; + } + + ret = s3c_csis_power(enable); + if (unlikely(ret)) { + pr_err("%s: csis power-on failed\n", __func__); + return ret; + } + + return ret; +} + +static int isx012_enable_standby(bool enable) +{ + int err; + + pr_info("%s: %s\n", __func__, enable ? "on" : "off"); + + err = gpio_request(GPIO_5M_nSTBY, "GPJ0"); + if (unlikely(err)) { + printk(KERN_ERR "error: request 5M_nSTBY\n"); + return err; + } + + /* GPIO_5M_nSTBY */ + err = gpio_direction_output(GPIO_5M_nSTBY, enable ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH); + CAM_CHECK_ERR_RET(err, "GPIO_5M_nSTBY"); + + gpio_free(GPIO_5M_nSTBY); + return 0; +} + +static int px_cam_cfg_init(void) +{ + int ret = -ENODEV; + + pr_info("cam_cfg_init\n"); + + ret = gpio_request(GPIO_CAM_MOVIE_EN, "GPM3"); + if (unlikely(ret)) { + pr_err("cam_cfg_init: fail to get gpio(MOVIE_EN), " + "err=%d\n", ret); + goto out; + } + + ret = gpio_request(GPIO_CAM_FLASH_EN, "GPM3"); + if (unlikely(ret)) { + pr_err("cam_cfg_init: fail to get gpio(FLASH_EN), " + "err=%d\n", ret); + goto out_free; + } + + return 0; + +out_free: + gpio_free(GPIO_CAM_MOVIE_EN); +out: + return ret; +} + +static const char *isx012_get_clk_name(void) +{ + return "sclk_cam0"; +} + +static struct isx012_platform_data isx012_plat = { + .default_width = 1024, + .default_height = 768, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, + .streamoff_delay = ISX012_STREAMOFF_DELAY, + .flash_en = isx012_flash_en, + .is_flash_on = isx012_is_flash_on, + .stby_on = isx012_enable_standby, + .dbg_level = CAMDBG_LEVEL_DEFAULT, +}; +#define REAR_CAM_PLAT (isx012_plat) + +static struct i2c_board_info isx012_i2c_info = { + I2C_BOARD_INFO("ISX012", 0x7A>>1), + .platform_data = &isx012_plat, +}; + +static struct s3c_platform_camera isx012 = { + .id = CAMERA_CSI_C, + .get_clk_name = isx012_get_clk_name, + .get_i2c_busnum = isx012_get_i2c_busnum, + .cam_power = isx012_power, /*smdkv310_mipi_cam0_reset,*/ + .type = CAM_TYPE_MIPI, + .fmt = ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/ + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .info = &isx012_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", /* "mout_mpll" */ + .clk_rate = 24000000, /* 48000000 */ + .line_length = 640, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + .mipi_lanes = 2, + .mipi_settle = 12, + .mipi_align = 32, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, +}; + +static ssize_t isx012_camtype_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const char cam_type[] = "SONY_ISX012"; + pr_info("%s\n", __func__); + return sprintf(buf, "%s\n", cam_type); +} +static DEVICE_ATTR(rear_camtype, S_IRUGO, isx012_camtype_show, NULL); + +static ssize_t isx012_camfw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char type[] = "ISX012"; + return sprintf(buf, "%s %s\n", type, type); + +} +static DEVICE_ATTR(rear_camfw, S_IRUGO, isx012_camfw_show, NULL); + +static ssize_t flash_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%s\n", isx012_is_flash_on() ? "on" : "off"); +} + +static ssize_t flash_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + + isx012_flash_en(ISX012_FLASH_MODE_MOVIE, (*buf == '0') ? + ISX012_FLASH_OFF : ISX012_FLASH_ON); + + return count; +} +static DEVICE_ATTR(rear_flash, 0664, flash_show, flash_store); + +int isx012_create_file(struct class *cls) +{ + struct device *dev_rear = NULL; + int ret = -ENODEV; + + dev_rear = device_create(cls, NULL, 0, NULL, "rear"); + if (IS_ERR(dev_rear)) { + pr_err("cam_init: failed to create device(rearcam_dev)\n"); + return -ENODEV; + } + + ret = device_create_file(dev_rear, &dev_attr_rear_camtype); + if (unlikely(ret < 0)) + pr_err("cam_init: failed to create device file, %s\n", + dev_attr_rear_camtype.attr.name); + + ret = device_create_file(dev_rear, &dev_attr_rear_camfw); + if (unlikely(ret < 0)) + pr_err("cam_init: failed to create device file, %s\n", + dev_attr_rear_camtype.attr.name); + + ret = device_create_file(dev_rear, &dev_attr_rear_flash); + if (unlikely(ret < 0)) + pr_err("cam_init: failed to create device file, %s\n", + dev_attr_rear_flash.attr.name); + + return 0; +} +#endif /* CONFIG_VIDEO_ISX012*/ + +#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON +static int s5k5ccgx_get_i2c_busnum(void) +{ + return 0; +} + +/* Power up/down func for P4C, P2. */ +static int s5k5ccgx_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s in P4C,P2\n", __func__); + +#ifndef USE_CAM_GPIO_CFG + ret = gpio_request(GPIO_2M_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_2M_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_3M_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_3M_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n"); + return ret; + } +#endif + + /* 2M_nSTBY low */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + + /* 2M_nRST low */ + ret = gpio_direction_output(GPIO_2M_nRST, 0); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + + /* 3MP_CORE_1.2V */ + regulator = regulator_get(NULL, "3mp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "3mp_core_1.2v"); + + /* CAM_IO_1.8V */ + regulator = regulator_get(NULL, "cam_io_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "cam_io_1.8v"); + + /* CAM_A2.8V, LDO13 */ + regulator = regulator_get(NULL, "cam_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "cam_a2.8v"); + + /* VT_CORE_1.8V */ + regulator = regulator_get(NULL, "vt_core_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "vt_core_1.8v"); + udelay(20); + + /* 2M_nSTBY High */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + udelay(3); + + /* CAM_MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + msleep(5); /* >=5ms */ + + /* 2M_nSTBY Low */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + msleep(10); /* >=10ms */ + + /* 2M_nRST High */ + ret = gpio_direction_output(GPIO_2M_nRST, 1); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + msleep(5); + + /* 2M_nSTBY High */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + udelay(2); + + /* 3M_nSTBY */ + ret = gpio_direction_output(GPIO_3M_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "3M_nSTBY"); + udelay(16); + + /* 3M_nRST */ + ret = gpio_direction_output(GPIO_3M_nRST, 1); + CAM_CHECK_ERR_RET(ret, "3M_nRST"); + /* udelay(10); */ + + /* 3MP_AF_2.8V */ + regulator = regulator_get(NULL, "3mp_af_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "3mp_af_2.8v"); + msleep(10); + +#ifndef USE_CAM_GPIO_CFG + gpio_free(GPIO_2M_nSTBY); + gpio_free(GPIO_2M_nRST); + gpio_free(GPIO_3M_nSTBY); + gpio_free(GPIO_3M_nRST); +#endif + + return ret; +} + +static int s5k5ccgx_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s in P4C,P2\n", __func__); + +#ifndef USE_CAM_GPIO_CFG + ret = gpio_request(GPIO_2M_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_2M_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_3M_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_3M_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n"); + return ret; + } +#endif + /* 3MP_AF_2.8V */ + regulator = regulator_get(NULL, "3mp_af_2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "3mp_af_2.8v"); + + /* 3M_nRST Low*/ + ret = gpio_direction_output(GPIO_3M_nRST, 0); + CAM_CHECK_ERR(ret, "3M_nSTBY"); + udelay(50); + + /* CAM_MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + udelay(5); + + /* 3M_nSTBY */ + ret = gpio_direction_output(GPIO_3M_nSTBY, 0); + CAM_CHECK_ERR(ret, "3M_nSTBY"); + udelay(1); + + /* 2M_nRST Low */ + ret = gpio_direction_output(GPIO_2M_nRST, 0); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + + /* 2M_nSTBY Low */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + + /* VT_CORE_1.8V */ + regulator = regulator_get(NULL, "vt_core_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "vt_core_1.8v"); + + /* CAM_A2.8V */ + regulator = regulator_get(NULL, "cam_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "cam_a2.8v"); + /* udelay(50); */ + + /* CAM_IO_1.8V */ + regulator = regulator_get(NULL, "cam_io_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "cam_io_1.8v"); + /*udelay(50); */ + + /* 3MP_CORE_1.2V */ + regulator = regulator_get(NULL, "3mp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "3mp_core_1.2v"); + +#ifndef USE_CAM_GPIO_CFG + gpio_free(GPIO_2M_nSTBY); + gpio_free(GPIO_2M_nRST); + gpio_free(GPIO_3M_nSTBY); + gpio_free(GPIO_3M_nRST); +#endif + return ret; +} + +static int s5k5ccgx_power(int enable) +{ + int ret = 0; + + printk(KERN_DEBUG "%s %s\n", __func__, enable ? "on" : "down"); + if (enable) { +#ifdef USE_CAM_GPIO_CFG + if (cfg_gpio_err) { + printk(KERN_ERR "%s: ERROR: gpio configuration", + __func__); + return cfg_gpio_err; + } +#endif + ret = s5k5ccgx_power_on(); + } else + ret = s5k5ccgx_power_down(); + + s3c_csis_power(enable); + + return ret; +} + +static void s5k5ccgx_flashtimer_handler(unsigned long data) +{ +#if 0 /* dslim */ + int ret = -ENODEV; + atomic_t *flash_status = (atomic_t *)data; + + pr_info("********** flashtimer_handler **********\n"); + + ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 0); + atomic_set(flash_status, S5K5CCGX_FLASH_OFF); + if (unlikely(ret)) + pr_err("flash_timer: ERROR, failed to oneshot flash off\n"); +#endif +} + +static atomic_t flash_status = ATOMIC_INIT(S5K5CCGX_FLASH_OFF); +static int s5k5ccgx_flash_en(u32 mode, u32 onoff) +{ +#if 0 /* dslim */ + + static int flash_mode = S5K5CCGX_FLASH_MODE_NORMAL; + static DEFINE_MUTEX(flash_lock); + static DEFINE_TIMER(flash_timer, s5k5ccgx_flashtimer_handler, + 0, (unsigned long)&flash_status); + int ret = 0; + + printk(KERN_DEBUG "flash_en: mode=%d, on=%d\n", mode, onoff); + + if (unlikely((u32)mode >= S5K5CCGX_FLASH_MODE_MAX)) { + pr_err("flash_en: ERROR, invalid flash mode(%d)\n", mode); + return -EINVAL; + } + + /* We could not use spin lock because of gpio kernel API.*/ + mutex_lock(&flash_lock); + if (atomic_read(&flash_status) == onoff) { + mutex_unlock(&flash_lock); + pr_warn("flash_en: WARNING, already flash %s\n", + onoff ? "On" : "Off"); + return 0; + } + + switch (onoff) { + case S5K5CCGX_FLASH_ON: + if (mode == S5K5CCGX_FLASH_MODE_MOVIE) + ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 1); + else { + ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 1); + flash_timer.expires = get_jiffies_64() + HZ / 2; + add_timer(&flash_timer); + } + CAM_CHECK_ERR_GOTO(ret, out, + "flash_en: ERROR, fail to turn flash on (mode:%d)\n", + mode); + flash_mode = mode; + break; + + case S5K5CCGX_FLASH_OFF: + if (unlikely(flash_mode != mode)) { + pr_err("flash_en: ERROR, unmatched flash mode(%d, %d)\n", + flash_mode, mode); + WARN_ON(1); + goto out; + } + + if (mode == S5K5CCGX_FLASH_MODE_MOVIE) + ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 0); + else { + if (del_timer_sync(&flash_timer)) { + pr_info("flash_en: terminate flash timer...\n"); + ret = gpio_direction_output(GPIO_CAM_FLASH_EN, + 0); + } + } + CAM_CHECK_ERR_GOTO(ret, out, + "flash_en: ERROR, flash off (mode:%d)\n", mode); + break; + + default: + pr_err("flash_en: ERROR, invalid flash cmd(%d)\n", onoff); + goto out; + break; + } + + atomic_set(&flash_status, onoff); + +out: + mutex_unlock(&flash_lock); +#endif + return 0; +} + +static int s5k5ccgx_is_flash_on(void) +{ + return atomic_read(&flash_status); +} + +static int px_cam_cfg_init(void) +{ + int ret = -ENODEV; + + /* pr_info("%s\n", __func__); */ +#if 0 /* dslim */ + ret = gpio_request(GPIO_CAM_MOVIE_EN, "GPL0"); + if (unlikely(ret)) { + pr_err("cam_cfg_init: fail to get gpio(MOVIE_EN), " + "err=%d\n", ret); + goto out; + } + + ret = gpio_request(GPIO_CAM_FLASH_EN, "GPL0"); + if (unlikely(ret)) { + pr_err("cam_cfg_init: fail to get gpio(FLASH_EN), " + "err=%d\n", ret); + goto out_free; + } + + return 0; + +out_free: + gpio_free(GPIO_CAM_MOVIE_EN); +out: + return ret; +#else + return 0; +#endif +} + +static const char *s5k5ccgx_get_clk_name(void) +{ + return "sclk_cam0"; +} + +static struct s5k5ccgx_platform_data s5k5ccgx_plat = { + .default_width = 1024, + .default_height = 768, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, + .streamoff_delay = S5K5CCGX_STREAMOFF_DELAY, + .flash_en = s5k5ccgx_flash_en, + .is_flash_on = s5k5ccgx_is_flash_on, + .dbg_level = CAMDBG_LEVEL_DEFAULT, +}; +#define REAR_CAM_PLAT (s5k5ccgx_plat) + +static struct i2c_board_info s5k5ccgx_i2c_info = { + I2C_BOARD_INFO("S5K5CCGX", 0x78>>1), + .platform_data = &s5k5ccgx_plat, +}; + +static struct s3c_platform_camera s5k5ccgx = { + .id = CAMERA_CSI_C, + .get_clk_name = s5k5ccgx_get_clk_name, + .get_i2c_busnum = s5k5ccgx_get_i2c_busnum, + .cam_power = s5k5ccgx_power, /*smdkv310_mipi_cam0_reset,*/ + .type = CAM_TYPE_MIPI, + .fmt = ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT*/ + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .info = &s5k5ccgx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", /* "mout_mpll" */ + .clk_rate = 24000000, /* 48000000 */ + .line_length = 640, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + .mipi_lanes = 1, + .mipi_settle = 6, + .mipi_align = 32, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, +}; +#endif /* #ifdef CONFIG_VIDEO_S5K5CCGX_COMMON */ + + +#ifdef CONFIG_VIDEO_SR200PC20M +static int sr200pc20m_get_i2c_busnum(void) +{ + return 13; +} + +static int sr200pc20m_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_RESET, "GPY3"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + + /* CAM_VT_nSTBY low */ + ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "output VT_nSTBY"); + + /* CAM_VT_nRST low */ + gpio_direction_output(GPIO_CAM_VT_nRST, 0); + CAM_CHECK_ERR_RET(ret, "output VT_nRST"); + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 0); + CAM_CHECK_ERR(ret, "output reset"); + + /* CAM_ISP_CORE_1.2V */ + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 1); + CAM_CHECK_ERR_RET(ret, "output GPIO_ISP_CORE_EN"); + + regulator = regulator_get(NULL, "cam_isp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_core_1.2v"); + /* No delay */ + + /* CAM_SENSOR_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v"); + udelay(10); + + /* CAM_SENSOR_A2.8V */ + regulator = regulator_get(NULL, "cam_sensor_a2.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_a2.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_a2.8v"); + /* it takes about 100us at least during level transition.*/ + udelay(160); /* 130us -> 160us */ + + /* VT_CAM_DVDD_1.8V */ + regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable vt_cam_dvdd_1.8v"); + udelay(10); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err vt_cam_1.8v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable vt_cam_1.8v"); + udelay(20); + + /* CAM_VT_nSTBY high */ + ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "output VT_nSTBY"); + mdelay(2); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + mdelay(30); + + /* CAM_VT_nRST high */ + gpio_direction_output(GPIO_CAM_VT_nRST, 1); + CAM_CHECK_ERR_RET(ret, "output VT_nRST"); + + gpio_free(GPIO_CAM_VT_nSTBY); + gpio_free(GPIO_CAM_VT_nRST); + gpio_free(GPIO_ISP_CORE_EN); + gpio_free(GPIO_ISP_RESET); + + return ret; +} + +static int sr200pc20m_power_off(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s in\n", __func__); + + ret = gpio_request(GPIO_CAM_VT_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VT_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); + if (ret) { + printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); + return ret; + } + ret = gpio_request(GPIO_ISP_RESET, "GPY3"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_ISP_RESET)\n"); + return ret; + } + + /* ISP_RESET */ + ret = gpio_direction_output(GPIO_ISP_RESET, 0); + CAM_CHECK_ERR(ret, "output reset"); + + /* CAM_VT_nRST low */ + gpio_direction_output(GPIO_CAM_VT_nRST, 0); + CAM_CHECK_ERR_RET(ret, "output VT_nRST"); + + /* MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + udelay(20); + + /* CAM_VT_nSTBY low */ + ret = gpio_direction_output(GPIO_CAM_VT_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "output VT_nSTBY"); + mdelay(2); + + /* CAM_SENSOR_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_core_1.2v"); + udelay(5); + + /* CAM_ISP_CORE_1.2V */ + ret = gpio_direction_output(GPIO_ISP_CORE_EN, 0); + CAM_CHECK_ERR(ret, "output ISP_CORE"); + + regulator = regulator_get(NULL, "cam_isp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "disable cam_isp_core_1.2v"); + + /* CAM_SENSOR_A2.8V */ + regulator = regulator_get(NULL, "cam_sensor_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_sensor_a2.8v"); + udelay(800); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable vt_cam_1.8v"); + udelay(250); /* 10us -> 250us */ + + /* VT_CAM_DVDD_1.8V */ + regulator = regulator_get(NULL, "vt_cam_dvdd_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable vt_cam_dvdd_1.8v"); + udelay(300); /*10 -> 300 us */ + + gpio_free(GPIO_CAM_VT_nSTBY); + gpio_free(GPIO_CAM_VT_nRST); + gpio_free(GPIO_ISP_CORE_EN); + gpio_free(GPIO_ISP_RESET); + + return ret; +} + +static int sr200pc20m_power(int onoff) +{ + int ret = 0; + + printk(KERN_DEBUG "%s(): %s\n", __func__, onoff ? "on" : "down"); + + if (onoff) { + ret = sr200pc20m_power_on(); + if (unlikely(ret)) + goto error_out; + } else { + ret = sr200pc20m_power_off(); + } + + ret = s3c_csis_power(onoff); + +error_out: + return ret; +} + +static const char *sr200pc20m_get_clk_name(void) +{ + return "sclk_cam0"; +} + +static struct sr200pc20m_platform_data sr200pc20m_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 1, + .streamoff_delay = 0, + .dbg_level = CAMDBG_LEVEL_DEFAULT, +}; + +static struct i2c_board_info sr200pc20m_i2c_info = { + I2C_BOARD_INFO("SR200PC20M", 0x40 >> 1), + .platform_data = &sr200pc20m_plat, +}; + +static struct s3c_platform_camera sr200pc20m = { + .id = CAMERA_CSI_D, + .get_clk_name = sr200pc20m_get_clk_name, + .type = CAM_TYPE_MIPI, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR, + .get_i2c_busnum = sr200pc20m_get_i2c_busnum, + .info = &sr200pc20m_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_rate = 24000000, + .line_length = 640, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + .mipi_lanes = 1, + .mipi_settle = 6, + .mipi_align = 32, + + .inv_pclk = 0, + .inv_vsync = 0, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, + .cam_power = sr200pc20m_power, +}; +#endif /* CONFIG_VIDEO_SR200PC20M */ + +#ifdef CONFIG_VIDEO_SR200PC20 +static int sr200pc20_get_i2c_busnum(void) +{ +#ifdef CONFIG_MACH_P4 + pr_info("%s: system_rev=%d\n", __func__); + if (system_rev >= 2) + return 0; + else +#endif + return 13; +} + +static int sr200pc20_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + +#ifndef USE_CAM_GPIO_CFG + ret = gpio_request(GPIO_2M_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_2M_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_3M_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(3M_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_3M_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(3M_nRST)\n"); + return ret; + } +#endif + + /* 3M_nSTBY low */ + ret = gpio_direction_output(GPIO_3M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "3M_nSTBY"); + + /* 3M_nRST low */ + ret = gpio_direction_output(GPIO_3M_nRST, 0); + CAM_CHECK_ERR_RET(ret, "3M_nRST"); + + /* 2M_nSTBY low */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + + /* 2M_nRST low */ + ret = gpio_direction_output(GPIO_2M_nRST, 0); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + + /* 3MP_CORE_1.2V */ + regulator = regulator_get(NULL, "3mp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "3mp_core_1.2v"); + /* udelay(5); */ + + /* CAM_IO_1.8V */ + regulator = regulator_get(NULL, "cam_io_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "cam_io_1.8v"); + /*udelay(5); */ + + /* CAM_A2.8V */ + regulator = regulator_get(NULL, "cam_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "cam_a2.8v"); + /* udelay(5); */ + + /* VT_CORE_1.8V */ + regulator = regulator_get(NULL, "vt_core_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "vt_core_1.8v"); + udelay(20); + + /* ENB High */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + udelay(3); /* 30 -> 3 */ + + /* CAM_MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + msleep(5); /* >= 5ms */ + + /* ENB Low */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + msleep(10); /* >= 10ms */ + + /* 2M_nRST High*/ + ret = gpio_direction_output(GPIO_2M_nRST, 1); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + /*msleep(7);*/ /* >= 7ms */ + +#if 0 + /* ENB High */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + msleep(12); /* >= 10ms */ + + /* ENB Low */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + msleep(12); /* >= 10ms */ + + /* 2M_nRST Low*/ + ret = gpio_direction_output(GPIO_2M_nRST, 0); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + udelay(10); /* >= 16 cycle */ + + /* 2M_nRST High */ + ret = gpio_direction_output(GPIO_2M_nRST, 1); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); +#endif + udelay(10); /* >= 16 cycle */ + +#ifndef USE_CAM_GPIO_CFG + gpio_free(GPIO_2M_nSTBY); + gpio_free(GPIO_2M_nRST); + gpio_free(GPIO_3M_nSTBY); + gpio_free(GPIO_3M_nRST); +#endif + return 0; +} + +static int sr200pc20_power_off(void) +{ + struct regulator *regulator; + int ret = 0; + + printk(KERN_DEBUG "%s in\n", __func__); + +#ifndef USE_CAM_GPIO_CFG + ret = gpio_request(GPIO_2M_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_2M_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "Error: fail to request gpio(2M_nRST)\n"); + return ret; + } +#endif + +#if 0 + /* 2M_nRST */ + ret = gpio_direction_output(GPIO_2M_nRST, 0); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + udelay(100); + + /* 2M_nSTBY */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + udelay(100); +#endif + /* Sleep command */ + mdelay(1); + + /* 2M_nRST Low*/ + ret = gpio_direction_output(GPIO_2M_nRST, 0); + CAM_CHECK_ERR_RET(ret, "2M_nRST"); + udelay(3); + + /* CAM_MCLK */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + udelay(10); + + /* ENB High*/ + ret = gpio_direction_output(GPIO_2M_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "2M_nSTBY"); + mdelay(5); + + /* ENB Low */ + ret = gpio_direction_output(GPIO_2M_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "2M_spnSTBY"); + /* udelay(1); */ + + /* VT_CORE_1.8V */ + regulator = regulator_get(NULL, "vt_core_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "vt_core_1.8v"); + /* udelay(10); */ + + /* CAM_A2.8V */ + regulator = regulator_get(NULL, "cam_a2.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "cam_a2.8v"); + /* udelay(10); */ + + /* CAM_IO_1.8V */ + regulator = regulator_get(NULL, "cam_io_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "cam_io_1.8v"); + /*udelay(10); */ + + /* 3MP_CORE_1.2V */ + regulator = regulator_get(NULL, "3mp_core_1.2v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + +#ifndef USE_CAM_GPIO_CFG + gpio_free(GPIO_2M_nSTBY); + gpio_free(GPIO_2M_nRST); +#endif + return 0; +} + +static int sr200pc20_power(int onoff) +{ + int ret = 0; + + printk(KERN_DEBUG "%s(): %s\n", __func__, onoff ? "on" : "down"); + + if (onoff) { +#ifdef USE_CAM_GPIO_CFG + if (cfg_gpio_err) { + printk(KERN_ERR "%s: ERROR: gpio configuration", + __func__); + return cfg_gpio_err; + } +#endif + ret = sr200pc20_power_on(); + } else { + ret = sr200pc20_power_off(); + /* s3c_i2c0_force_stop();*/ /* DSLIM. Should be implemented */ + } + + return ret; +} + +static const char *sr200pc20_get_clk_name(void) +{ + return "sclk_cam0"; +} + +static struct sr200pc20_platform_data sr200pc20_plat = { + .default_width = 800, + .default_height = 600, + .pixelformat = V4L2_PIX_FMT_UYVY, + .is_mipi = 0, + .streamoff_delay = 0, + .dbg_level = CAMDBG_LEVEL_DEFAULT, +}; +#define FRONT_CAM_PLAT (sr200pc20_plat) + +static struct i2c_board_info sr200pc20_i2c_info = { + I2C_BOARD_INFO("SR200PC20", 0x40 >> 1), + .platform_data = &sr200pc20_plat, +}; + +static struct s3c_platform_camera sr200pc20 = { + .id = CAMERA_PAR_A, + .get_clk_name = sr200pc20_get_clk_name, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR, + .get_i2c_busnum = sr200pc20_get_i2c_busnum, + .info = &sr200pc20_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_rate = 24000000, + .line_length = 800, + .width = 800, + .height = 600, + .window = { + .left = 0, + .top = 0, + .width = 800, + .height = 600, + }, + + /* Polarity */ +#if 1 /*def CONFIG_VIDEO_SR200PC20_P4W */ + .inv_pclk = 0, + .inv_vsync = 1, +#else + .inv_pclk = 1, + .inv_vsync = 0, +#endif + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, + .cam_power = sr200pc20_power, +}; +#endif /* CONFIG_VIDEO_SR200PC20 */ + + +/* Interface setting */ +static struct s3c_platform_fimc fimc_plat = { + .default_cam = CAMERA_CSI_D, + .camera = { +#if defined(CONFIG_VIDEO_S5C73M3) || defined(CONFIG_VIDEO_SLP_S5C73M3) + &s5c73m3, +#endif +#ifdef CONFIG_VIDEO_ISX012 + &isx012, +#endif +#ifdef CONFIG_VIDEO_S5K6A3 + &s5k6a3, +#endif +#if defined(CONFIG_VIDEO_S5K6A3) && defined(CONFIG_S5K6A3_CSI_D) + &s5k6a3_fd, +#endif +#if defined(CONFIG_VIDEO_M5MO) + &m5mo, +#endif +#if defined(CONFIG_VIDEO_M9MO) + &m9mo, +#endif +#if defined(CONFIG_VIDEO_SR200PC20M) + &sr200pc20m, +#endif +#ifdef CONFIG_VIDEO_S5K5CCGX_COMMON + &s5k5ccgx, +#endif +#ifdef CONFIG_VIDEO_SR200PC20 + &sr200pc20, +#endif +#ifdef WRITEBACK_ENABLED + &writeback, +#endif + }, + .hw_ver = 0x51, +}; + +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE +static void __set_flite_camera_config(struct exynos_platform_flite *data, + u32 active_index, u32 max_cam) +{ + data->active_cam_index = active_index; + data->num_clients = max_cam; +} + +static void __init smdk4x12_set_camera_flite_platdata(void) +{ + int flite0_cam_index = 0; + int flite1_cam_index = 0; +#ifdef CONFIG_VIDEO_S5K6A3 + exynos_flite1_default_data.cam[flite1_cam_index++] = &s5k6a3; +#endif +#ifdef CONFIG_VIDEO_SR200PC20M + exynos_flite1_default_data.cam[flite1_cam_index++] = &sr200pc20m; +#endif + __set_flite_camera_config(&exynos_flite0_default_data, 0, flite0_cam_index); + __set_flite_camera_config(&exynos_flite1_default_data, 0, flite1_cam_index); +} +#endif /* CONFIG_VIDEO_EXYNOS_FIMC_LITE */ +#endif /* CONFIG_VIDEO_FIMC */ + +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC +static struct i2c_board_info __initdata test_info = { + I2C_BOARD_INFO("testinfo", 0x0), +}; + +static struct s5p_fimc_isp_info isp_info[] = { + { + .board_info = &test_info, + .bus_type = FIMC_LCD_WB, + .i2c_bus_num = 0, + .mux_id = 0, /* A-Port : 0, B-Port : 1 */ + .flags = FIMC_CLK_INV_VSYNC, + }, +}; + +static void __init midas_subdev_config(void) +{ + s3c_fimc0_default_data.isp_info[0] = &isp_info[0]; + s3c_fimc0_default_data.isp_info[0]->use_cam = true; + s3c_fimc0_default_data.isp_info[1] = &isp_info[1]; + s3c_fimc0_default_data.isp_info[1]->use_cam = false; + s3c_fimc0_default_data.isp_info[2] = &isp_info[1]; + s3c_fimc0_default_data.isp_info[2]->use_cam = false; + s3c_fimc0_default_data.isp_info[3] = &isp_info[1]; + s3c_fimc0_default_data.isp_info[3]->use_cam = false; +} +#endif /* CONFIG_VIDEO_SAMSUNG_S5P_FIMC */ + +void __init midas_camera_init(void) +{ +#ifdef CONFIG_VIDEO_FIMC + s3c_fimc0_set_platdata(&fimc_plat); + s3c_fimc1_set_platdata(&fimc_plat); + s3c_fimc2_set_platdata(NULL); +#ifdef CONFIG_DRM_EXYNOS_FIMD_WB + s3c_fimc3_set_platdata(&fimc_plat); +#else + s3c_fimc3_set_platdata(NULL); +#endif +#ifdef CONFIG_EXYNOS_DEV_PD + s3c_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION + secmem.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#endif +#ifdef CONFIG_VIDEO_FIMC_MIPI + s3c_csis0_set_platdata(NULL); + s3c_csis1_set_platdata(NULL); +#ifdef CONFIG_EXYNOS_DEV_PD + s3c_device_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s3c_device_csis1.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#endif +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE + smdk4x12_set_camera_flite_platdata(); + s3c_set_platdata(&exynos_flite0_default_data, + sizeof(exynos_flite0_default_data), &exynos_device_flite0); + s3c_set_platdata(&exynos_flite1_default_data, + sizeof(exynos_flite1_default_data), &exynos_device_flite1); +#endif +#endif /* CONFIG_VIDEO_FIMC */ + +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_FIMC + midas_subdev_config(); + + dev_set_name(&s5p_device_fimc0.dev, "s3c-fimc.0"); + dev_set_name(&s5p_device_fimc1.dev, "s3c-fimc.1"); + dev_set_name(&s5p_device_fimc2.dev, "s3c-fimc.2"); + dev_set_name(&s5p_device_fimc3.dev, "s3c-fimc.3"); + + clk_add_alias("fimc", "exynos4210-fimc.0", "fimc", + &s5p_device_fimc0.dev); + clk_add_alias("fimc", "exynos4210-fimc.1", "fimc", + &s5p_device_fimc1.dev); + clk_add_alias("fimc", "exynos4210-fimc.2", "fimc", + &s5p_device_fimc2.dev); + clk_add_alias("fimc", "exynos4210-fimc.3", "fimc", + &s5p_device_fimc3.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.0", "sclk_fimc", + &s5p_device_fimc0.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.1", "sclk_fimc", + &s5p_device_fimc1.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.2", "sclk_fimc", + &s5p_device_fimc2.dev); + clk_add_alias("sclk_fimc", "exynos4210-fimc.3", "sclk_fimc", + &s5p_device_fimc3.dev); + + s3c_fimc_setname(0, "exynos4210-fimc"); + s3c_fimc_setname(1, "exynos4210-fimc"); + s3c_fimc_setname(2, "exynos4210-fimc"); + s3c_fimc_setname(3, "exynos4210-fimc"); + + s3c_set_platdata(&s3c_fimc0_default_data, + sizeof(s3c_fimc0_default_data), &s5p_device_fimc0); + s3c_set_platdata(&s3c_fimc1_default_data, + sizeof(s3c_fimc1_default_data), &s5p_device_fimc1); + s3c_set_platdata(&s3c_fimc2_default_data, + sizeof(s3c_fimc2_default_data), &s5p_device_fimc2); + s3c_set_platdata(&s3c_fimc3_default_data, + sizeof(s3c_fimc3_default_data), &s5p_device_fimc3); +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev; +#endif +#endif /* CONFIG_VIDEO_S5P_FIMC */ + +#if defined(CONFIG_MACH_P4NOTE) && defined(CONFIG_VIDEO_ISX012) + px_cam_cfg_init(); +#endif +} diff --git a/arch/arm/mach-exynos/board-grande-gpio.c b/arch/arm/mach-exynos/board-grande-gpio.c new file mode 100755 index 0000000..6820a40 --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-gpio.c @@ -0,0 +1,495 @@ +/* + * linux/arch/arm/mach-exynos/board-grande-gpio.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - GPIO setting in set board + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/serial_core.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-serial.h> +#include <mach/gpio-midas.h> +#include <plat/cpu.h> +#include <mach/pmu.h> + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + +/* + * M0 GPIO Init Table + */ +static struct gpio_init_data m0_init_gpios[] = { + {EXYNOS4_GPA0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPC0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPC1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* TSK_LDE_EN */ + {EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */ + {EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */ + {EXYNOS4_GPL0(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TSP_LDO_EN */ + {EXYNOS4_GPL2(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV1}, /* TSP_LDO_EN */ + {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */ + {EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 3G_DET */ + {EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */ + {EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */ + {EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* V_BUS_INT */ + {EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */ + {EXYNOS4_GPX2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_HOST_WAKEUP */ + {EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */ + {EXYNOS4_GPX2(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* nPower */ + {EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */ + {EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */ + {EXYNOS4_GPX3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CP_PMU_RST */ + {EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */ + {EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */ + {EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */ + {EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */ + {EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */ + {EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */ + {EXYNOS4212_GPM3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PMIC_DVS1 */ + {EXYNOS4212_GPM4(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV3}, /* MSENSE_RST_N */ + {EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4212_GPJ0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV3}, /* GPIO_3_TOUCH_INT */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV3}, /* GPIO_MSENSOR_INT */ + {EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* CAM_MCLK */ + {EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* VTCAM_MCLK */ +}; + +/* + * GRANDE GPIO Sleep Table + */ +static unsigned int grande_sleep_gpio_table[][3] = { + {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + /* FOLDER_PMIC_SDA */ + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + /* FOLDER_PMIC_SCL */ + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + /* SUB_PMIC_SDA */ + {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + + /* SUB_PMIC_SCL */ + {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PCM_SEL */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SCL*/ + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*TSP_SEL*/ + + {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK2_SEL*/ + {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK3_SEL*/ + {EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK4_SEL*/ + {EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CLK*/ + {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CMD*/ + {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*eMMC_EN*/ + {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(0)*/ + {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(1)*/ + {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(2)*/ + {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(3)*/ + + {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(4)*/ + {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(5)*/ + {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(6)*/ + {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(7)*/ + + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */ +/* {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ + {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +/* {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ + + {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +/* {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, */ + + {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPX0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},/* PS_ALS_INT */ + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ + {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY4(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY5(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY6(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + /* Exynos4212 specific gpio */ + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS1*/ + {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS2*/ + {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS3*/ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SCL*/ + {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SDA*/ + {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +}; /* grande_sleep_gpio_table */ + +static void config_sleep_gpio_table(int array_size, + unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +/* To save power consumption, gpio pin set before enterling sleep */ +void midas_config_sleep_gpio_table(void) +{ +#if defined(CONFIG_MACH_GRANDE) + config_sleep_gpio_table(ARRAY_SIZE(grande_sleep_gpio_table), + grande_sleep_gpio_table); +#endif +} + +/* Intialize gpio set in midas board */ +void midas_config_gpio_table(void) +{ + u32 i, gpio; + + printk(KERN_DEBUG "%s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(m0_init_gpios); i++) { + gpio = m0_init_gpios[i].num; + if (gpio <= EXYNOS4212_GPV4(1)) { + s3c_gpio_cfgpin(gpio, m0_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, m0_init_gpios[i].pud); + + if (m0_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, m0_init_gpios[i].val); + + s5p_gpio_set_drvstr(gpio, m0_init_gpios[i].drv); + } + } +} diff --git a/arch/arm/mach-exynos/board-grande-lcd.c b/arch/arm/mach-exynos/board-grande-lcd.c new file mode 100755 index 0000000..27a54dc --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-lcd.c @@ -0,0 +1,868 @@ +/* + * midas-lcd.c - lcd driver of MIDAS Project + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/regulator/consumer.h> +#include <linux/lcd.h> + +#include <plat/devs.h> +#include <plat/fb-s5p.h> +#include <plat/gpio-cfg.h> +#include <plat/pd.h> +#include <plat/map-base.h> +#include <plat/map-s5p.h> + +#ifdef CONFIG_FB_S5P_LD9040 +#include <linux/ld9040.h> +#endif + +#ifdef CONFIG_FB_S5P_MIPI_DSIM +#include <mach/mipi_ddi.h> +#include <mach/dsim.h> +#endif +#if defined(CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD) +#include <../../../drivers/video/samsung_duallcd/s3cfb.h> +#else +#include <../../../drivers/video/samsung/s3cfb.h> +#endif + +#ifdef CONFIG_FB_S5P_MDNIE +#include <linux/mdnie.h> +#endif + +struct s3c_platform_fb fb_platform_data; +unsigned int lcdtype; +static int __init lcdtype_setup(char *str) +{ + get_option(&str, &lcdtype); + return 1; +} +__setup("lcdtype=", lcdtype_setup); + + +#ifdef CONFIG_FB_S5P +#ifdef CONFIG_FB_S5P_LD9040 +static int lcd_cfg_gpio(void) +{ + int i, f3_end = 4; + + for (i = 0; i < 8; i++) { + /* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */ + s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE); + } + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < f3_end; i++) { + s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE); + } + + /* MLCD_RST */ + s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE); + + /* LCD_nCS */ + s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE); + + /* LCD_SCLK */ + s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE); + + /* LCD_SDI */ + s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE); + + return 0; +} + +static int lcd_power_on(struct lcd_device *ld, int enable) +{ + struct regulator *regulator; + + if (ld == NULL) { + printk(KERN_ERR "lcd device object is NULL.\n"); + return 0; + } + + if (enable) { + regulator = regulator_get(NULL, "vlcd_3.0v"); + if (IS_ERR(regulator)) + return 0; + + regulator_enable(regulator); + regulator_put(regulator); + } else { + regulator = regulator_get(NULL, "vlcd_3.0v"); + + if (IS_ERR(regulator)) + return 0; + + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + + regulator_put(regulator); + } + + return 1; +} + +static int reset_lcd(struct lcd_device *ld) +{ + int reset_gpio = -1; + int err; + + reset_gpio = EXYNOS4_GPY4(5); + + err = gpio_request(reset_gpio, "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request MLCD_RST for " + "lcd reset control\n"); + return err; + } + + gpio_request(reset_gpio, "MLCD_RST"); + + mdelay(10); + gpio_direction_output(reset_gpio, 0); + mdelay(10); + gpio_direction_output(reset_gpio, 1); + + gpio_free(reset_gpio); + + return 1; +} + +static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld) +{ + int reset_gpio = -1; + int err; + + reset_gpio = EXYNOS4_GPY4(5); + + err = gpio_request(reset_gpio, "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request MLCD_RST for " + "lcd reset control\n"); + return err; + } + + mdelay(10); + gpio_direction_output(reset_gpio, 0); + + gpio_free(reset_gpio); + + return 0; +} + +static int lcd_gpio_cfg_lateresume(struct lcd_device *ld) +{ + /* MLCD_RST */ + s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE); + + /* LCD_nCS */ + s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE); + + /* LCD_SCLK */ + s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE); + + /* LCD_SDI */ + s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE); + + return 0; +} + +static struct s3cfb_lcd ld9040_info = { + .width = 480, + .height = 800, + .p_width = 56, + .p_height = 93, + .bpp = 24, + + .freq = 60, + .timing = { + .h_fp = 16, + .h_bp = 14, + .h_sw = 2, + .v_fp = 10, + .v_fpe = 1, + .v_bp = 4, + .v_bpe = 1, + .v_sw = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 1, + }, +}; + +struct ld9040_panel_data s2plus_panel_data; +static struct lcd_platform_data ld9040_platform_data = { + .reset = reset_lcd, + .power_on = lcd_power_on, + .gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend, + .gpio_cfg_lateresume = lcd_gpio_cfg_lateresume, + /* it indicates whether lcd panel is enabled from u-boot. */ + .lcd_enabled = 0, + .reset_delay = 20, /* 20ms */ + .power_on_delay = 20, /* 20ms */ + .power_off_delay = 200, /* 200ms */ + .sleep_in_delay = 160, + .pdata = &s2plus_panel_data, +}; + +#define LCD_BUS_NUM 3 +#define DISPLAY_CS EXYNOS4_GPY4(3) +static struct spi_board_info spi_board_info[] __initdata = { + { + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + }, +}; + +#define DISPLAY_CLK EXYNOS4_GPY3(1) +#define DISPLAY_SI EXYNOS4_GPY3(3) +static struct spi_gpio_platform_data lcd_spi_gpio_data = { + .sck = DISPLAY_CLK, + .mosi = DISPLAY_SI, + .miso = SPI_GPIO_NO_MISO, + .num_chipselect = 1, +}; + +static struct platform_device ld9040_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s3c_device_fb.dev, + .platform_data = &lcd_spi_gpio_data, + }, +}; + +/* reading with 3-WIRE SPI with GPIO */ +static inline void setcs(u8 is_on) +{ + gpio_set_value(DISPLAY_CS, is_on); +} + +static inline void setsck(u8 is_on) +{ + gpio_set_value(DISPLAY_CLK, is_on); +} + +static inline void setmosi(u8 is_on) +{ + gpio_set_value(DISPLAY_SI, is_on); +} + +static inline unsigned int getmiso(void) +{ + return !!gpio_get_value(DISPLAY_SI); +} + +static inline void setmosi2miso(u8 is_on) +{ + if (is_on) + s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_INPUT); + else + s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_OUTPUT); +} + +struct spi_ops ops = { + .setcs = setcs, + .setsck = setsck, + .setmosi = setmosi, + .setmosi2miso = setmosi2miso, + .getmiso = getmiso, +}; + +void __init ld9040_fb_init(void) +{ + struct ld9040_panel_data *pdata; + + strcpy(spi_board_info[0].modalias, "ld9040"); + spi_board_info[0].platform_data = (void *)&ld9040_platform_data; + + pdata = ld9040_platform_data.pdata; + pdata->ops = &ops; + + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + + if (!ld9040_platform_data.lcd_enabled) + lcd_cfg_gpio(); + /*s3cfb_set_platdata(&fb_platform_data);*/ +} +#endif + +#if defined(CONFIG_FB_S5P_S6C1372) +int s6c1372_panel_gpio_init(void) +{ + int i, f3_end = 4; + + for (i = 0; i < 8; i++) { + /* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */ + s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < f3_end; i++) { + s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE); + } + + return 0; +} + +static struct s3cfb_lcd s6c1372 = { + .width = 1280, + .height = 800, + .p_width = 217, + .p_height = 135, + .bpp = 24, + + .freq = 60, + .timing = { + .h_fp = 18, + .h_bp = 36, + .h_sw = 16, + .v_fp = 4, + .v_fpe = 1, + .v_bp = 16, + .v_bpe = 1, + .v_sw = 3, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 0, + }, +}; + +static int lcd_power_on(struct lcd_device *ld, int enable) +{ + if (enable) { + /* LVDS_N_SHDN to high*/ + mdelay(1); + gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_HIGH); + msleep(300); + + gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_HIGH); + mdelay(2); + } else { + gpio_set_value(GPIO_LED_BACKLIGHT_RESET, GPIO_LEVEL_LOW); + msleep(200); + + /* LVDS_nSHDN low*/ + gpio_set_value(GPIO_LVDS_NSHDN, GPIO_LEVEL_LOW); + msleep(40); +} + + return 0; +} + +static struct lcd_platform_data s6c1372_platform_data = { + .power_on = lcd_power_on, +}; + +struct platform_device lcd_s6c1372 = { + .name = "s6c1372", + .id = -1, + .dev.platform_data = &s6c1372_platform_data, +}; + +#endif + +#ifdef CONFIG_FB_S5P_LMS501KF03 +static struct s3c_platform_fb lms501kf03_data __initdata = { + .hw_ver = 0x70, + .clk_name = "sclk_lcd", + .nr_wins = 5, + .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, +}; + +#define LCD_BUS_NUM 3 +#define DISPLAY_CS EXYNOS4_GPB(5) +#define DISPLAY_CLK EXYNOS4_GPB(4) +#define DISPLAY_SI EXYNOS4_GPB(7) + +static struct spi_board_info spi_board_info[] __initdata = { + { + .modalias = "lms501kf03", + .platform_data = NULL, + .max_speed_hz = 1200000, + .bus_num = LCD_BUS_NUM, + .chip_select = 0, + .mode = SPI_MODE_3, + .controller_data = (void *)DISPLAY_CS, + } +}; + +static struct spi_gpio_platform_data lms501kf03_spi_gpio_data = { + .sck = DISPLAY_CLK, + .mosi = DISPLAY_SI, + .miso = -1, + .num_chipselect = 1, +}; + +static struct platform_device s3c_device_spi_gpio = { + .name = "spi_gpio", + .id = LCD_BUS_NUM, + .dev = { + .parent = &s3c_device_fb.dev, + .platform_data = &lms501kf03_spi_gpio_data, + }, +}; +#endif + +#ifdef CONFIG_FB_S5P_MIPI_DSIM +#ifdef CONFIG_FB_S5P_S6E8AA0 +/* for Geminus based on MIPI-DSI interface */ +static struct s3cfb_lcd s6e8aa0 = { + .name = "s6e8aa0", + .width = 720, + .height = 1280, + .p_width = 60, /* 59.76 mm */ + .p_height = 106, /* 106.24 mm */ + .bpp = 24, + + .freq = 60, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + + .timing = { + .h_fp = 5, + .h_bp = 5, + .h_sw = 5, + .v_fp = 13, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + .cmd_allow_len = 11, /* v_fp=stable_vfp + cmd_allow_len */ + .stable_vfp = 2, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; +#endif + +#ifdef CONFIG_FB_S5P_S6E63M0 +/* for Geminus based on MIPI-DSI interface */ +static struct s3cfb_lcd s6e63m0 = { + .name = "s6e63m0", + .width = 480, +#if 1 /* Only for S6E63M0X03 DDI */ + .height = 802, /* Originally 800 (due to 2 Line in LCD below issue) */ +#else + .height = 800, +#endif + .p_width = 60, /* 59.76 mm */ + .p_height = 106, /* 106.24 mm */ + .bpp = 24, + + .freq = 56, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + + .timing = { + .h_fp = 16, + .h_bp = 14, + .h_sw = 2, + .v_fp = 28, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + .cmd_allow_len = 11, /* v_fp=stable_vfp + cmd_allow_len */ + .stable_vfp = 2, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; +#endif + +#ifdef CONFIG_FB_S5P_S6E39A0 +static struct s3cfb_lcd s6e39a0 = { + .name = "s6e8aa0", + .width = 540, + .height = 960, + .p_width = 58, + .p_height = 103, + .bpp = 24, + + .freq = 60, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + + .timing = { + .h_fp = 0x48, + .h_bp = 12, + .h_sw = 4, + .v_fp = 13, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + .cmd_allow_len = 0x4, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; +#endif + +#ifdef CONFIG_FB_S5P_S6D6AA1 +/* for Geminus based on MIPI-DSI interface */ +static struct s3cfb_lcd s6d6aa1 = { + .name = "s6d6aa1", + .width = 720, + .height = 1280, + .p_width = 63, /* 63.2 mm */ + .p_height = 114, /* 114.19 mm */ + .bpp = 24, + + .freq = 60, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + + .timing = { + .h_fp = 50, + .h_bp = 15, + .h_sw = 3, + .v_fp = 3, + .v_fpe = 1, + .v_bp = 2, + .v_bpe = 1, + .v_sw = 2, + .cmd_allow_len = 11, /* v_fp=stable_vfp + cmd_allow_len */ + .stable_vfp = 2, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; +#endif + +static int reset_lcd(void) +{ + int err; + + err = gpio_request(GPIO_MLCD_RST, "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request GPY4(5) for " + "lcd reset control\n"); + return -EINVAL; + } + + gpio_direction_output(GPIO_MLCD_RST, 1); + usleep_range(5000, 5000); + gpio_set_value(GPIO_MLCD_RST, 0); + usleep_range(5000, 5000); + gpio_set_value(GPIO_MLCD_RST, 1); + usleep_range(5000, 5000); + gpio_free(GPIO_MLCD_RST); + return 0; +} + +static void lcd_cfg_gpio(void) +{ + /* MLCD_RST */ + s3c_gpio_cfgpin(GPIO_MLCD_RST, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_MLCD_RST, S3C_GPIO_PULL_NONE); + + /* LCD_EN */ + s3c_gpio_cfgpin(GPIO_LCD_22V_EN_00, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_LCD_22V_EN_00, S3C_GPIO_PULL_NONE); + + return; +} + +static int lcd_power_on(void *ld, int enable) +{ + struct regulator *regulator; + int err; + + printk(KERN_INFO "%s : enable=%d\n", __func__, enable); + + err = gpio_request(GPIO_MLCD_RST, "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request GPY4[5] for " + "MLCD_RST control\n"); + return -EPERM; + } + + err = gpio_request(GPIO_LCD_22V_EN_00, "LCD_EN"); + if (err) { + printk(KERN_ERR "failed to request GPM4[4] for " + "LCD_2.2V_EN control\n"); + return -EPERM; + } + + if (enable) { + gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_HIGH); + + regulator = regulator_get(NULL, "vlcd_2.8v"); + if (IS_ERR(regulator)) + goto out; + regulator_enable(regulator); + regulator_put(regulator); + } else { + regulator = regulator_get(NULL, "vlcd_2.8v"); + if (IS_ERR(regulator)) + goto out; + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + regulator_put(regulator); + + gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_LOW); + gpio_set_value(GPIO_MLCD_RST, 0); + } + +out: +/* Release GPIO */ + gpio_free(GPIO_MLCD_RST); + gpio_free(GPIO_LCD_22V_EN_00); +return 0; +} + +static void s5p_dsim_mipi_power_control(int enable) +{ + struct regulator *regulator; + int power_en = 0; + + if (power_en == 1) { + printk(KERN_INFO "%s : enable=%d\n", __func__, enable); + + if (enable) { + regulator = regulator_get(NULL, "vmipi_1.0v"); + if (IS_ERR(regulator)) + goto out; + regulator_enable(regulator); + regulator_put(regulator); + + regulator = regulator_get(NULL, "vmipi_1.8v"); + if (IS_ERR(regulator)) + goto out; + regulator_enable(regulator); + regulator_put(regulator); + } else { + regulator = regulator_get(NULL, "vmipi_1.8v"); + if (IS_ERR(regulator)) + goto out; + if (regulator_is_enabled(regulator)) + regulator_disable(regulator); + regulator_put(regulator); + + regulator = regulator_get(NULL, "vmipi_1.0v"); + if (IS_ERR(regulator)) + goto out; + if (regulator_is_enabled(regulator)) + regulator_disable(regulator); + regulator_put(regulator); + } +out: + return ; + } else { + return ; + } +} + +void __init mipi_fb_init(void) +{ + struct s5p_platform_dsim *dsim_pd = NULL; + struct mipi_ddi_platform_data *mipi_ddi_pd = NULL; + struct dsim_lcd_config *dsim_lcd_info = NULL; + + /* set platform data */ + + /* gpio pad configuration for rgb and spi interface. */ + lcd_cfg_gpio(); + + /* + * register lcd panel data. + */ + printk(KERN_INFO "%s :: fb_platform_data.hw_ver = 0x%x\n", + __func__, fb_platform_data.hw_ver); + + dsim_pd = (struct s5p_platform_dsim *) + s5p_device_dsim.dev.platform_data; + + dsim_pd->platform_rev = 1; + dsim_pd->mipi_power = s5p_dsim_mipi_power_control; + + dsim_lcd_info = dsim_pd->dsim_lcd_info; + +#if defined(CONFIG_FB_S5P_S6E8AA0) + dsim_lcd_info->lcd_panel_info = (void *)&s6e8aa0; +#endif +#if defined(CONFIG_FB_S5P_S6D6AA1) + dsim_lcd_info->lcd_panel_info = (void *)&s6d6aa1; +#endif + +#ifdef CONFIG_FB_S5P_S6E63M0 + dsim_lcd_info->lcd_panel_info = (void *)&s6e63m0; + dsim_pd->dsim_info->e_no_data_lane = DSIM_DATA_LANE_2; + /* 320Mbps */ + dsim_pd->dsim_info->p = 3; + dsim_pd->dsim_info->m = 80; + dsim_pd->dsim_info->s = 1; +#else + /* 500Mbps */ + dsim_pd->dsim_info->p = 3; + dsim_pd->dsim_info->m = 125; + dsim_pd->dsim_info->s = 1; +#endif + + mipi_ddi_pd = (struct mipi_ddi_platform_data *) + dsim_lcd_info->mipi_ddi_pd; + mipi_ddi_pd->lcd_reset = reset_lcd; + mipi_ddi_pd->lcd_power_on = lcd_power_on; +#if defined(CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD) + mipi_ddi_pd->lcd_sel_pin = GPIO_LCD_SEL; +#endif /* CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD */ + platform_device_register(&s5p_device_dsim); + + /*s3cfb_set_platdata(&fb_platform_data);*/ +} +#endif +#endif + +struct s3c_platform_fb fb_platform_data __initdata = { + .hw_ver = 0x70, + .clk_name = "fimd", + .nr_wins = 5, +#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW + .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, +#else + .default_win = 0, +#endif + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, +#if defined(CONFIG_FB_S5P_S6E8AA0) + .lcd = &s6e8aa0 +#endif +#if defined(CONFIG_FB_S5P_S6E63M0) + .lcd = &s6e63m0 +#endif +#if defined(CONFIG_FB_S5P_S6E39A0) + .lcd = &s6e39a0 +#endif +#if defined(CONFIG_FB_S5P_LD9040) + .lcd = &ld9040_info +#endif +#if defined(CONFIG_FB_S5P_S6C1372) + .lcd = &s6c1372 +#endif +#if defined(CONFIG_FB_S5P_S6D6AA1) + .lcd = &s6d6aa1 +#endif +}; + +#ifdef CONFIG_FB_S5P_MDNIE +static struct platform_mdnie_data mdnie_data = { + .display_type = -1, +#if defined(CONFIG_FB_S5P_S6C1372) + .lcd_pd = &s6c1372_platform_data, +#endif +}; +#endif + +struct platform_device mdnie_device = { + .name = "mdnie", + .id = -1, + .dev = { + .parent = &exynos4_device_pd[PD_LCD0].dev, +#ifdef CONFIG_FB_S5P_MDNIE + .platform_data = &mdnie_data, +#endif + }, +}; diff --git a/arch/arm/mach-exynos/board-grande-power.c b/arch/arm/mach-exynos/board-grande-power.c new file mode 100755 index 0000000..0fcc019 --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-power.c @@ -0,0 +1,1293 @@ +/* + * midas-power.c - Power Management of MIDAS Project + * + * Copyright (C) 2011 Samsung Electrnoics + * Chiwoong Byun <woong.byun@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/i2c.h> +#include <linux/regulator/machine.h> +#include <plat/gpio-cfg.h> +#include <mach/gpio-midas.h> +#include <mach/irqs.h> + +#include <linux/mfd/max8997.h> +#include <linux/mfd/max77686.h> +#include <linux/mfd/max77693.h> + +#ifdef CONFIG_REGULATOR_LP8720 +#include <linux/regulator/lp8720.h> +#endif + +#if defined(CONFIG_REGULATOR_S5M8767) +#include <linux/mfd/s5m87xx/s5m-pmic.h> +#include <linux/mfd/s5m87xx/s5m-core.h> +#endif + +#ifdef CONFIG_REGULATOR_MAX8997 +/* MOTOR */ +#ifdef CONFIG_VIBETONZ +static void max8997_motor_init(void) +{ + gpio_request(GPIO_VIBTONE_EN, "VIBTONE_EN"); + s3c_gpio_cfgpin(GPIO_VIBTONE_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_VIBTONE_EN, S3C_GPIO_PULL_NONE); +} + +static void max8997_motor_en(bool en) +{ + gpio_direction_output(GPIO_VIBTONE_EN, en); +} + +static struct max8997_motor_data max8997_motor = { + .max_timeout = 10000, + .duty = 44000, + .period = 44642, + .reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128, + .init_hw = max8997_motor_init, + .motor_en = max8997_motor_en, + .pwm_id = 1, +}; +#endif + +/* max8997 */ +static struct regulator_consumer_supply ldo1_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim"), +}; + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo6_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo7_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("votg_3.0v", NULL), +}; + +static struct regulator_consumer_supply ldo11_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim"), +}; + +static struct regulator_consumer_supply ldo13_supply[] = { + REGULATOR_SUPPLY("vlcd_3.3v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo14_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo15_supply[] = { + REGULATOR_SUPPLY("vlcd_2.2v", NULL), + REGULATOR_SUPPLY("VDD3", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo12_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo16_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo17_supply[] = { + REGULATOR_SUPPLY("cam_af_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo18_supply[] = { + REGULATOR_SUPPLY("touch", NULL), +}; + +static struct regulator_consumer_supply max8997_buck1 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max8997_buck2[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynos4412-busfreq"), +}; + +static struct regulator_consumer_supply max8997_buck3 = + REGULATOR_SUPPLY("vdd_g3d", NULL); + +static struct regulator_consumer_supply max8997_buck4 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo1, "VMIPI_1.8V", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo6, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo7, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo8, "VUOTG_3.0V", 3000000, 3000000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo11, "VMIPI_1.0V", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo13, "VCC_3.3V_LCD", 3300000, 3300000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo14, "VCC_1.8V_IO", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo15, "VDD_2.2V_LCD", 2200000, 2200000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo16, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo17, "CAM_AF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo18, "TSP_AVDD_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data max8997_buck1_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 950000, + .max_uV = 1100000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck1, +}; + +static struct regulator_init_data max8997_buck2_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 900000, + .max_uV = 1100000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(max8997_buck2), + .consumer_supplies = max8997_buck2, +}; + +static struct regulator_init_data max8997_buck3_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 950000, + .max_uV = 1150000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck3, +}; + +static struct regulator_init_data max8997_buck4_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max8997_buck4, +}; + +static struct max8997_regulator_data max8997_regulators[] = { + { MAX8997_BUCK1, &max8997_buck1_data, }, + { MAX8997_BUCK2, &max8997_buck2_data, }, + { MAX8997_BUCK3, &max8997_buck3_data, }, + { MAX8997_BUCK4, &max8997_buck4_data, }, + { MAX8997_LDO1, &ldo1_init_data, }, + { MAX8997_LDO6, &ldo6_init_data, }, + { MAX8997_LDO7, &ldo7_init_data, }, + { MAX8997_LDO8, &ldo8_init_data, }, + { MAX8997_LDO11, &ldo11_init_data, }, + { MAX8997_LDO12, &ldo12_init_data, }, + { MAX8997_LDO13, &ldo13_init_data, }, + { MAX8997_LDO14, &ldo14_init_data, }, + { MAX8997_LDO15, &ldo15_init_data, }, + { MAX8997_LDO16, &ldo16_init_data, }, + { MAX8997_LDO17, &ldo17_init_data, }, + { MAX8997_LDO18, &ldo18_init_data, }, +}; + +struct max8997_platform_data exynos4_max8997_info = { + .irq_base = IRQ_BOARD_PMIC_START, + .num_regulators = ARRAY_SIZE(max8997_regulators), + .regulators = max8997_regulators, + .buck1_max_vol = 1100000, + .buck2_max_vol = 1100000, + .buck5_max_vol = 1100000, + .buck_set1 = EXYNOS4212_GPJ1(1), + .buck_set2 = EXYNOS4212_GPJ1(2), + .buck_set3 = EXYNOS4_GPL0(0), +#ifdef CONFIG_VIBETONZ + .motor = &max8997_motor, +#endif +}; +#elif defined(CONFIG_REGULATOR_MAX77686) +/* max77686 */ + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo3_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +}; +#else +static struct regulator_consumer_supply ldo3_supply[] = {}; +#endif + +static struct regulator_consumer_supply ldo5_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v", NULL), + REGULATOR_SUPPLY("TOUCH_PULL_UP", NULL), +}; + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), + REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), +}; + +#if !defined(CONFIG_MACH_GRANDE) +static struct regulator_consumer_supply ldo9_supply[] = { + REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo10_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), +}; + +static struct regulator_consumer_supply ldo11_supply[] = { + REGULATOR_SUPPLY("vabb1_1.95v", NULL), +}; + +static struct regulator_consumer_supply ldo12_supply[] = { + REGULATOR_SUPPLY("votg_3.0v", NULL), +}; + +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_GRANDECTC) +static struct regulator_consumer_supply ldo13_supply[] = { + REGULATOR_SUPPLY("vusbhub_osc_1.8v", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo14_supply[] = { + REGULATOR_SUPPLY("vabb2_1.95v", NULL), +}; + +#if !defined(CONFIG_MACH_GRANDE) +static struct regulator_consumer_supply ldo17_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo18_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo21_supply[] = { + REGULATOR_SUPPLY("vtf_2.8v", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo23_supply[] = { + REGULATOR_SUPPLY("VREG_KEY", NULL), +}; + +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) \ + || defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) +static struct regulator_consumer_supply ldo24_supply[] = { + REGULATOR_SUPPLY("touch_1.8v", NULL), +}; +#else +static struct regulator_consumer_supply ldo24_supply[] = { + REGULATOR_SUPPLY("vlcd_2.2v", NULL), + REGULATOR_SUPPLY("VDD3", "s6e8aa0"), +}; +#endif + +static struct regulator_consumer_supply ldo25_supply[] = { + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo26_supply[] = { + REGULATOR_SUPPLY("vmotor", NULL), +}; + +static struct regulator_consumer_supply max77686_buck1[] = { + REGULATOR_SUPPLY("vdd_mif", NULL), + REGULATOR_SUPPLY("vdd_mif", "exynos4412-busfreq"), +}; + +static struct regulator_consumer_supply max77686_buck2 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max77686_buck3[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"), +}; + +static struct regulator_consumer_supply max77686_buck4[] = { + REGULATOR_SUPPLY("vdd_g3d", NULL), + REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"), +}; + +#if !defined(CONFIG_MACH_GRANDE) +static struct regulator_consumer_supply max77686_buck9 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); +#endif + +static struct regulator_consumer_supply max77686_enp32khz[] = { + REGULATOR_SUPPLY("lpo_in", "bcm47511"), + REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"), +}; + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo5, "TOUCH_PULL_UP", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 0); +#if !defined(CONFIG_MACH_GRANDE) +REGULATOR_INIT(ldo9, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +#endif +REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo11, "VABB1_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1, + REGULATOR_CHANGE_STATUS, 0); +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_GRANDECTC) +REGULATOR_INIT(ldo13, "VUSBHUB_OSC_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +#endif +REGULATOR_INIT(ldo14, "VABB2_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +#if !defined(CONFIG_MACH_GRANDE) +REGULATOR_INIT(ldo17, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo18, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +#endif +REGULATOR_INIT(ldo23, "VREG_KEY_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) +REGULATOR_INIT(ldo24, "VDD_1.8V_TSP", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +#else +REGULATOR_INIT(ldo24, "VDD_2.2V_LCD", 2200000, 2200000, 0, + REGULATOR_CHANGE_STATUS, 1); +#endif +REGULATOR_INIT(ldo26, "VCC_MOTOR_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); + +#if defined(CONFIG_MACH_SLP_PQ) +static struct regulator_init_data ldo24_pq11_init_data = { + .constraints = { + .name = "VDD_1.8V_TSP", + .min_uV = 1800000, + .max_uV = 1800000, + .always_on = 0, + .boot_on = 0, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 0, + .disabled = 1, + } + }, + .num_consumer_supplies = 1, + .consumer_supplies = ldo24_supply, +}; +#endif + +static struct regulator_init_data max77686_buck1_data = { + .constraints = { + .name = "vdd_mif range", + .min_uV = 850000, +#ifdef CONFIG_SLP + .max_uV = 1100000, +#else + .max_uV = 1050000, +#endif + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck1), + .consumer_supplies = max77686_buck1, +}; + +static struct regulator_init_data max77686_buck2_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 850000, + .max_uV = 1500000, + .apply_uV = 1, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max77686_buck2, +}; + +static struct regulator_init_data max77686_buck3_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 850000, +#ifdef CONFIG_SLP + .max_uV = 1150000, +#else + .max_uV = 1100000, +#endif + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck3), + .consumer_supplies = max77686_buck3, +}; + +static struct regulator_init_data max77686_buck4_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 850000, +#ifdef CONFIG_SLP + .max_uV = 1100000, +#else + .max_uV = 1075000, +#endif + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck4), + .consumer_supplies = max77686_buck4, +}; + +#if !defined(CONFIG_MACH_GRANDE) +static struct regulator_init_data max77686_buck9_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1000000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max77686_buck9, +}; +#endif + +static struct regulator_init_data max77686_enp32khz_data = { + .constraints = { + .name = "32KHZ_PMIC", + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz), + .consumer_supplies = max77686_enp32khz, +}; + +static struct max77686_regulator_data max77686_regulators[] = { + {MAX77686_BUCK1, &max77686_buck1_data,}, + {MAX77686_BUCK2, &max77686_buck2_data,}, + {MAX77686_BUCK3, &max77686_buck3_data,}, + {MAX77686_BUCK4, &max77686_buck4_data,}, +#if !defined(CONFIG_MACH_GRANDE) + /* CAM_ISP_CORE_1.2V */ + {MAX77686_BUCK9, &max77686_buck9_data,}, +#endif + {MAX77686_LDO3, &ldo3_init_data,}, + {MAX77686_LDO5, &ldo5_init_data,}, + {MAX77686_LDO8, &ldo8_init_data,}, +#if !defined(CONFIG_MACH_GRANDE) + {MAX77686_LDO9, &ldo9_init_data,}, +#endif + {MAX77686_LDO10, &ldo10_init_data,}, + {MAX77686_LDO11, &ldo11_init_data,}, + {MAX77686_LDO12, &ldo12_init_data,}, +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_GRANDECTC) + {MAX77686_LDO13, &ldo13_init_data,}, +#endif + {MAX77686_LDO14, &ldo14_init_data,}, +#if !defined(CONFIG_MACH_GRANDE) + {MAX77686_LDO17, &ldo17_init_data,}, + {MAX77686_LDO18, &ldo18_init_data,}, + {MAX77686_LDO21, &ldo21_init_data,}, +#endif + {MAX77686_LDO23, &ldo23_init_data,}, + {MAX77686_LDO24, &ldo24_init_data,}, + {MAX77686_LDO26, &ldo26_init_data,}, + {MAX77686_P32KH, &max77686_enp32khz_data,}, +}; + +struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = { + [MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL}, + [MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY}, +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_GRANDECTC) + [MAX77686_LDO13] = {MAX77686_LDO13, MAX77686_OPMODE_NORMAL}, +#endif + [MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY}, +}; + +struct max77686_platform_data exynos4_max77686_info = { + .num_regulators = ARRAY_SIZE(max77686_regulators), + .regulators = max77686_regulators, + .irq_gpio = GPIO_PMIC_IRQ, + .irq_base = IRQ_BOARD_PMIC_START, + .wakeup = 1, + + .opmode_data = max77686_opmode_data, + .ramp_rate = MAX77686_RAMP_RATE_27MV, + .wtsr_smpl = MAX77686_WTSR_ENABLE | MAX77686_SMPL_ENABLE, + + .buck234_gpio_dvs = { + /* Use DVS2 register of each bucks to supply stable power + * after sudden reset */ + {GPIO_PMIC_DVS1, 1}, + {GPIO_PMIC_DVS2, 0}, + {GPIO_PMIC_DVS3, 0}, + }, + .buck234_gpio_selb = { + GPIO_BUCK2_SEL, + GPIO_BUCK3_SEL, + GPIO_BUCK4_SEL, + }, + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1100000, /* 1.1V */ + .buck2_voltage[2] = 1100000, /* 1.1V */ + .buck2_voltage[3] = 1100000, /* 1.1V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1100000, /* 1.1V */ + .buck2_voltage[6] = 1100000, /* 1.1V */ + .buck2_voltage[7] = 1100000, /* 1.1V */ + + .buck3_voltage[0] = 1100000, /* 1.1V */ + .buck3_voltage[1] = 1000000, /* 1.0V */ + .buck3_voltage[2] = 1100000, /* 1.1V */ + .buck3_voltage[3] = 1100000, /* 1.1V */ + .buck3_voltage[4] = 1100000, /* 1.1V */ + .buck3_voltage[5] = 1100000, /* 1.1V */ + .buck3_voltage[6] = 1100000, /* 1.1V */ + .buck3_voltage[7] = 1100000, /* 1.1V */ + + .buck4_voltage[0] = 1100000, /* 1.1V */ + .buck4_voltage[1] = 1000000, /* 1.0V */ + .buck4_voltage[2] = 1100000, /* 1.1V */ + .buck4_voltage[3] = 1100000, /* 1.1V */ + .buck4_voltage[4] = 1100000, /* 1.1V */ + .buck4_voltage[5] = 1100000, /* 1.1V */ + .buck4_voltage[6] = 1100000, /* 1.1V */ + .buck4_voltage[7] = 1100000, /* 1.1V */ +}; + +#ifdef CONFIG_REGULATOR_LP8720 +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +#ifdef GPIO_FOLDER_PMIC_EN +static struct regulator_consumer_supply folder_pmic_ldo1_supply[] = { + REGULATOR_SUPPLY("proximity_sensor_2.8v", NULL), +}; + +static struct regulator_consumer_supply folder_pmic_ldo2_supply[] = { + REGULATOR_SUPPLY("proximity_led_3.0v", NULL), +}; + +static struct regulator_consumer_supply folder_pmic_ldo3_supply[] = { + REGULATOR_SUPPLY("vt_cam_2.8v", NULL), +}; + +static struct regulator_consumer_supply folder_pmic_ldo4_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply folder_pmic_ldo5_supply[] = { + REGULATOR_SUPPLY("vlcd_2.8v", NULL), +}; + +static struct regulator_consumer_supply folder_pmic_buck_supply[] = { + REGULATOR_SUPPLY("vlcd_1.8v", NULL), +}; + + +REGULATOR_INIT(folder_pmic_ldo1, "V_SENS_2.8V", 2800000, 2800000, 1, + REGULATOR_CHANGE_STATUS, 1); + +REGULATOR_INIT(folder_pmic_ldo2, "LED_A_3.0V", 3000000, 3000000, 1, + REGULATOR_CHANGE_STATUS, 1); + +REGULATOR_INIT(folder_pmic_ldo3, "V_CAM_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +REGULATOR_INIT(folder_pmic_ldo4, "V_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +REGULATOR_INIT(folder_pmic_ldo5, "V_LCD_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data folder_pmic_buck_init_data = { + .constraints = { + .name = "V_LCD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .always_on = 0, + .boot_on = 0, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = folder_pmic_buck_supply, +}; + +static struct lp8720_regulator_subdev lp8720_folder_regulators[] = { + { LP8720_LDO1, &folder_pmic_ldo1_init_data, }, + { LP8720_LDO2, &folder_pmic_ldo2_init_data, }, + { LP8720_LDO3, &folder_pmic_ldo3_init_data, }, + { LP8720_LDO4, &folder_pmic_ldo4_init_data, }, + { LP8720_LDO5, &folder_pmic_ldo5_init_data, }, + { LP8720_BUCK_V2, &folder_pmic_buck_init_data, }, +}; + +struct lp8720_platform_data folder_pmic_info = { + .name = "lp8720_folder_pmic", + .en_pin = GPIO_FOLDER_PMIC_EN, + .num_regulators = ARRAY_SIZE(lp8720_folder_regulators), + .regulators = lp8720_folder_regulators, +}; +#endif /* GPIO_FOLDER_PMIC_EN */ + +#ifdef GPIO_SUB_PMIC_EN +static struct regulator_consumer_supply sub_pmic_ldo1_supply[] = { + REGULATOR_SUPPLY("vtf_2.8v", NULL), +}; + +static struct regulator_consumer_supply sub_pmic_ldo3_supply[] = { + REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL), +}; + +static struct regulator_consumer_supply sub_pmic_ldo4_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply sub_pmic_buck_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +REGULATOR_INIT(sub_pmic_ldo1, "VTF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +REGULATOR_INIT(sub_pmic_ldo3, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); + +REGULATOR_INIT(sub_pmic_ldo4, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data sub_pmic_buck_init_data = { + .constraints = { + .name = "CAM_SENSOR_CORE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .always_on = 0, + .boot_on = 0, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = sub_pmic_buck_supply, +}; + +static struct lp8720_regulator_subdev lp8720_sub_regulators[] = { + { LP8720_LDO1, &sub_pmic_ldo1_init_data, }, + { LP8720_LDO3, &sub_pmic_ldo3_init_data, }, + { LP8720_LDO4, &sub_pmic_ldo4_init_data, }, + { LP8720_BUCK_V2, &sub_pmic_buck_init_data, }, +}; + +struct lp8720_platform_data sub_pmic_info = { + .name = "lp8720_sub_pmic", + .en_pin = GPIO_SUB_PMIC_EN, + .num_regulators = ARRAY_SIZE(lp8720_sub_regulators), + .regulators = lp8720_sub_regulators, +}; +#endif /* GPIO_SUB_PMIC_EN */ +#endif /* CONFIG_REGULATOR_LP8720 */ + +void midas_power_init(void) +{ + printk(KERN_INFO "%s\n", __func__); +} +#endif /* CONFIG_REGULATOR_MAX77686 */ + +void midas_power_set_muic_pdata(void *pdata, int gpio) +{ + gpio_request(gpio, "AP_PMIC_IRQ"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + +#ifdef CONFIG_REGULATOR_MAX8997 + exynos4_max8997_info.muic = pdata; +#endif +} + +void midas_power_gpio_init(void) +{ +#ifdef CONFIG_REGULATOR_MAX8997 + int gpio; + + gpio = EXYNOS4212_GPJ1(1); + gpio_request(gpio, "BUCK_SET1"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + gpio = EXYNOS4212_GPJ1(2); + gpio_request(gpio, "BUCK_SET2"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + gpio = EXYNOS4_GPL0(0); + gpio_request(gpio, "BUCK_SET3"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); +#endif +} + +#ifdef CONFIG_MFD_MAX77693 +static struct regulator_consumer_supply safeout1_supply[] = { + REGULATOR_SUPPLY("safeout1", NULL), +}; + +static struct regulator_consumer_supply safeout2_supply[] = { + REGULATOR_SUPPLY("safeout2", NULL), +}; + +static struct regulator_consumer_supply charger_supply[] = { + REGULATOR_SUPPLY("vinchg1", "charger-manager.0"), + REGULATOR_SUPPLY("vinchg1", NULL), +}; + +static struct regulator_init_data safeout1_init_data = { + .constraints = { + .name = "safeout1 range", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 1, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout1_supply), + .consumer_supplies = safeout1_supply, +}; + +static struct regulator_init_data safeout2_init_data = { + .constraints = { + .name = "safeout2 range", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 0, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout2_supply), + .consumer_supplies = safeout2_supply, +}; + +static struct regulator_init_data charger_init_data = { + .constraints = { + .name = "CHARGER", + .valid_ops_mask = REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_CURRENT, + .boot_on = 1, + .min_uA = 60000, + .max_uA = 2580000, + }, + .num_consumer_supplies = ARRAY_SIZE(charger_supply), + .consumer_supplies = charger_supply, +}; + +struct max77693_regulator_data max77693_regulators[] = { + {MAX77693_ESAFEOUT1, &safeout1_init_data,}, + {MAX77693_ESAFEOUT2, &safeout2_init_data,}, + {MAX77693_CHARGER, &charger_init_data,}, +}; + +#if defined(CONFIG_MACH_SLP_PQ) +/* this initcall replace ldo24 from VDD 2.2 to VDD 1.8 for evt1.1 board. */ +static int __init regulator_init_with_rev(void) +{ + /* SLP PQ Promixa evt1.1 */ + if (system_rev != 3) { + ldo24_supply[0].supply = "touch_1.8v"; + ldo24_supply[0].dev_name = NULL; + + memcpy(&ldo24_init_data, &ldo24_pq11_init_data, + sizeof(struct regulator_init_data)); + } + return 0; +} + +postcore_initcall(regulator_init_with_rev); +#endif /* CONFIG_MACH_SLP_PQ */ +#endif /* CONFIG_MFD_MAX77693 */ + +#if defined(CONFIG_REGULATOR_S5M8767) +/* S5M8767 Regulator */ + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo3_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +}; +#endif + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"), +}; + +static struct regulator_consumer_supply ldo9_supply[] = { + REGULATOR_SUPPLY("cam_isp_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo10_supply[] = { + REGULATOR_SUPPLY("vt_cam_dvdd_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo13_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"), +}; + +static struct regulator_consumer_supply ldo19_supply[] = { + REGULATOR_SUPPLY("cam_af_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo20_supply[] = { + REGULATOR_SUPPLY("vlcd_3.0v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo21_supply[] = { + REGULATOR_SUPPLY("vmotor", NULL), +}; + +static struct regulator_consumer_supply ldo22_supply[] = { + REGULATOR_SUPPLY("cam_sensor_a2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo23_supply[] = { + REGULATOR_SUPPLY("vtf_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo24_supply[] = { + REGULATOR_SUPPLY("touch", NULL), +}; + +static struct regulator_consumer_supply ldo25_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo26_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo27_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo28_supply[] = { + REGULATOR_SUPPLY("3_touch_1.8v", NULL), +}; + +static struct regulator_consumer_supply s5m8767_buck1[] = { + REGULATOR_SUPPLY("vdd_mif", NULL), + REGULATOR_SUPPLY("vdd_mif", "exynos4212-busfreq"), +}; + +static struct regulator_consumer_supply s5m8767_buck2 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply s5m8767_buck3[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynos4212-busfreq"), +}; + +static struct regulator_consumer_supply s5m8767_buck4[] = { + REGULATOR_SUPPLY("vdd_g3d", NULL), + REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"), +}; + +static struct regulator_consumer_supply s5m8767_buck6 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); + +static struct regulator_consumer_supply s5m8767_enp32khz[] = { + REGULATOR_SUPPLY("lpo_in", "bcm47511"), + REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"), +}; + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo9, "CAM_ISP_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo10, "VT_CAM_DVDD_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo13, "VMIPI_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo19, "CAM_AF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo20, "VCC_3.0V_LCD", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo21, "VCC_MOTOR_3.0V", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo22, "CAM_SENSOR_A2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo23, "VTF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo24, "TSP_AVDD_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo26, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo27, "VT_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo28, "3_TOUCH_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data s5m8767_buck1_data = { + .constraints = { + .name = "vdd_mif range", + .min_uV = 850000, + .max_uV = 1100000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck1), + .consumer_supplies = s5m8767_buck1, +}; + +static struct regulator_init_data s5m8767_buck2_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 850000, + .max_uV = 1500000, + .apply_uV = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck2, +}; + +static struct regulator_init_data s5m8767_buck3_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 850000, + .max_uV = 1300000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck3), + .consumer_supplies = s5m8767_buck3, +}; + +static struct regulator_init_data s5m8767_buck4_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 850000, + .max_uV = 1150000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck4), + .consumer_supplies = s5m8767_buck4, +}; + +static struct regulator_init_data s5m8767_buck6_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1000000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck6, +}; + +static struct regulator_init_data s5m8767_enp32khz_data = { + .constraints = { + .name = "32KHZ_PMIC", + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_enp32khz), + .consumer_supplies = s5m8767_enp32khz, +}; + +static struct s5m_regulator_data s5m8767_regulators[] = { + {S5M8767_BUCK1, &s5m8767_buck1_data,}, + {S5M8767_BUCK2, &s5m8767_buck2_data,}, + {S5M8767_BUCK3, &s5m8767_buck3_data,}, + {S5M8767_BUCK4, &s5m8767_buck4_data,}, + {S5M8767_BUCK6, &s5m8767_buck6_data,}, + {S5M8767_LDO3, &ldo3_init_data,}, + {S5M8767_LDO8, &ldo8_init_data,}, + {S5M8767_LDO9, &ldo9_init_data,}, + {S5M8767_LDO10, &ldo10_init_data,}, + {S5M8767_LDO13, &ldo13_init_data,}, + {S5M8767_LDO19, &ldo19_init_data,}, + {S5M8767_LDO20, &ldo20_init_data,}, + {S5M8767_LDO21, &ldo21_init_data,}, + {S5M8767_LDO22, &ldo22_init_data,}, + {S5M8767_LDO23, &ldo23_init_data,}, + {S5M8767_LDO24, &ldo24_init_data,}, + {S5M8767_LDO25, &ldo25_init_data,}, + {S5M8767_LDO26, &ldo26_init_data,}, + {S5M8767_LDO27, &ldo27_init_data,}, + {S5M8767_LDO28, &ldo28_init_data,}, +}; + +struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = { + [S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK6] = {S5M8767_BUCK6, S5M_OPMODE_STANDBY}, + [S5M8767_LDO3] = {S5M8767_LDO3, S5M_OPMODE_NORMAL}, + [S5M8767_LDO8] = {S5M8767_LDO8, S5M_OPMODE_NORMAL}, + [S5M8767_LDO9] = {S5M8767_LDO9, S5M_OPMODE_NORMAL}, + [S5M8767_LDO10] = {S5M8767_LDO10, S5M_OPMODE_NORMAL}, + [S5M8767_LDO19] = {S5M8767_LDO19, S5M_OPMODE_NORMAL}, + [S5M8767_LDO20] = {S5M8767_LDO20, S5M_OPMODE_NORMAL}, + [S5M8767_LDO21] = {S5M8767_LDO21, S5M_OPMODE_NORMAL}, + [S5M8767_LDO22] = {S5M8767_LDO22, S5M_OPMODE_NORMAL}, + [S5M8767_LDO23] = {S5M8767_LDO23, S5M_OPMODE_STANDBY}, + [S5M8767_LDO24] = {S5M8767_LDO24, S5M_OPMODE_NORMAL}, + [S5M8767_LDO25] = {S5M8767_LDO25, S5M_OPMODE_NORMAL}, + [S5M8767_LDO26] = {S5M8767_LDO26, S5M_OPMODE_NORMAL}, + [S5M8767_LDO27] = {S5M8767_LDO27, S5M_OPMODE_NORMAL}, + [S5M8767_LDO28] = {S5M8767_LDO28, S5M_OPMODE_NORMAL}, +}; + +struct s5m_platform_data exynos4_s5m8767_info = { + .device_type = S5M8767X, + .num_regulators = ARRAY_SIZE(s5m8767_regulators), + .regulators = s5m8767_regulators, + .buck2_ramp_enable = true, + .buck3_ramp_enable = true, + .buck4_ramp_enable = true, + .irq_gpio = GPIO_PMIC_IRQ, + .irq_base = IRQ_BOARD_PMIC_START, + .wakeup = 1, + + .opmode_data = s5m8767_opmode_data, + .wtsr_smpl = 1, + + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1100000, /* 1.1V */ + .buck2_voltage[2] = 1100000, /* 1.1V */ + .buck2_voltage[3] = 1100000, /* 1.1V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1100000, /* 1.1V */ + .buck2_voltage[6] = 1100000, /* 1.1V */ + .buck2_voltage[7] = 1100000, /* 1.1V */ + + .buck3_voltage[0] = 1100000, /* 1.1V */ + .buck3_voltage[1] = 1100000, /* 1.1V */ + .buck3_voltage[2] = 1100000, /* 1.1V */ + .buck3_voltage[3] = 1100000, /* 1.1V */ + .buck3_voltage[4] = 1100000, /* 1.1V */ + .buck3_voltage[5] = 1100000, /* 1.1V */ + .buck3_voltage[6] = 1100000, /* 1.1V */ + .buck3_voltage[7] = 1100000, /* 1.1V */ + + .buck4_voltage[0] = 1100000, /* 1.1V */ + .buck4_voltage[1] = 1100000, /* 1.1V */ + .buck4_voltage[2] = 1100000, /* 1.1V */ + .buck4_voltage[3] = 1100000, /* 1.1V */ + .buck4_voltage[4] = 1100000, /* 1.1V */ + .buck4_voltage[5] = 1100000, /* 1.1V */ + .buck4_voltage[6] = 1100000, /* 1.1V */ + .buck4_voltage[7] = 1100000, /* 1.1V */ + + .buck_ramp_delay = 10, + .buck_default_idx = 3, + + .buck_gpios[0] = GPIO_BUCK2_SEL, + .buck_gpios[1] = GPIO_BUCK3_SEL, + .buck_gpios[2] = GPIO_BUCK4_SEL, +}; + +void midas_power_init(void) +{ + ldo8_init_data.constraints.always_on = 1; + ldo10_init_data.constraints.always_on = 1; +} + +/* End of S5M8767 */ +#endif diff --git a/arch/arm/mach-exynos/board-grande-sensor.c b/arch/arm/mach-exynos/board-grande-sensor.c new file mode 100755 index 0000000..720ec31 --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-sensor.c @@ -0,0 +1,499 @@ +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/sensor/sensors_core.h> +#ifdef CONFIG_SENSORS_AK8975C +#include <linux/sensor/ak8975.h> +#endif +#ifdef CONFIG_SENSORS_AK8963C +#include <linux/sensor/ak8963.h> +#endif +#include <linux/sensor/k3dh.h> +#include <linux/sensor/gp2a.h> +#include <linux/sensor/lsm330dlc_accel.h> +#include <linux/sensor/lsm330dlc_gyro.h> +#include <linux/sensor/lps331ap.h> +#include <linux/sensor/cm36651.h> +#include <linux/sensor/cm3663.h> +#include <linux/sensor/bh1721.h> + +#include <plat/gpio-cfg.h> +#include <mach/regs-gpio.h> +#include <mach/gpio.h> +#include "midas.h" + +#if defined(CONFIG_SENSORS_LSM330DLC) ||\ + defined(CONFIG_SENSORS_K3DH) +static int stm_get_position(void); + +static struct accel_platform_data accel_pdata = { + .accel_get_position = stm_get_position, + .axis_adjust = true, +}; +#endif + +#ifdef CONFIG_SENSORS_LSM330DLC +static struct gyro_platform_data gyro_pdata = { + .gyro_get_position = stm_get_position, + .axis_adjust = true, +}; +#endif + + +static struct i2c_board_info i2c_devs1[] __initdata = { +#ifdef CONFIG_SENSORS_LSM330DLC + { + I2C_BOARD_INFO("lsm330dlc_accel", (0x32 >> 1)), + .platform_data = &accel_pdata, + }, + { + I2C_BOARD_INFO("lsm330dlc_gyro", (0xD6 >> 1)), + .platform_data = &gyro_pdata, + }, +#elif defined(CONFIG_SENSORS_K3DH) + { + I2C_BOARD_INFO("k3dh", 0x19), + .platform_data = &accel_pdata, + }, +#endif +}; + +static int stm_get_position(void) +{ + int position = 0; + +#if defined(CONFIG_MACH_M3) + if (system_rev == 1) + position = 3; /* top/lower-left */ + else + position = 2; /* top/lower-right */ +#elif defined(CONFIG_MACH_M0_CMCC) + if (system_rev == 2) + position = 0; /* top/upper-left */ + else + position = 2; /* top/lower-right */ +#elif defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) + if (system_rev >= 6) + position = 6; /* bottom/lower-right */ + else + position = 3; /* top/lower-left */ +#elif defined(CONFIG_MACH_C1_KOR_LGT) + if (system_rev >= 6) + position = 2; /* top/lower-right */ + else if (system_rev == 5) + position = 4; /* bottom/upper-left */ + else + position = 3; /* top/lower-left */ +#elif defined(CONFIG_MACH_P4NOTE) + position = 4; /* bottom/upper-left */ +#elif defined(CONFIG_MACH_M0_GRANDECTC) + if (system_rev == 13) + position = 0; /* top/upper-left */ + else + position = 4; +#elif defined(CONFIG_MACH_IRON) + position = 7; /* bottom/lower-left */ +#elif defined(CONFIG_MACH_M0) + if (system_rev == 3 || system_rev == 0) + position = 6; /* bottom/lower-right */ + else if (system_rev == 1 || system_rev == 2\ + || system_rev == 4 || system_rev == 5) + position = 0; /* top/upper-left */ + else + position = 2; /* top/lower-right */ +#elif defined(CONFIG_MACH_C1) + if (system_rev == 3 || system_rev == 0) + position = 7; /* bottom/lower-left */ + else if (system_rev == 2) + position = 3; /* top/lower-left */ + else + position = 2; /* top/lower-right */ +#elif defined(CONFIG_MACH_GC1) + position = 1; +#else /* Common */ + position = 2; /* top/lower-right */ +#endif + return position; +} + +#if defined(CONFIG_SENSORS_LSM330DLC) || \ + defined(CONFIG_SENSORS_K3DH) +static int accel_gpio_init(void) +{ + int ret = gpio_request(GPIO_ACC_INT, "accelerometer_irq"); + + pr_info("%s\n", __func__); + + if (ret) { + pr_err("%s, Failed to request gpio accelerometer_irq(%d)\n", + __func__, ret); + return ret; + } + + /* Accelerometer sensor interrupt pin initialization */ + s3c_gpio_cfgpin(GPIO_ACC_INT, S3C_GPIO_INPUT); + gpio_set_value(GPIO_ACC_INT, 2); + s3c_gpio_setpull(GPIO_ACC_INT, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(GPIO_ACC_INT, S5P_GPIO_DRVSTR_LV1); + i2c_devs1[0].irq = gpio_to_irq(GPIO_ACC_INT); + + return ret; +} +#endif + +#ifdef CONFIG_SENSORS_LSM330DLC +static int gyro_gpio_init(void) +{ + int ret = gpio_request(GPIO_GYRO_INT, "lsm330dlc_gyro_irq"); + + pr_info("%s\n", __func__); + + if (ret) { + pr_err("%s, Failed to request gpio lsm330dlc_gyro_irq(%d)\n", + __func__, ret); + return ret; + } + + ret = gpio_request(GPIO_GYRO_DE, "lsm330dlc_gyro_data_enable"); + + if (ret) { + pr_err("%s, Failed to request gpio lsm330dlc_gyro_data_enable(%d)\n", + __func__, ret); + return ret; + } + + /* Gyro sensor interrupt pin initialization */ +#if 0 + s5p_register_gpio_interrupt(GPIO_GYRO_INT); + s3c_gpio_cfgpin(GPIO_GYRO_INT, S3C_GPIO_SFN(0xF)); +#else + s3c_gpio_cfgpin(GPIO_GYRO_INT, S3C_GPIO_INPUT); +#endif + gpio_set_value(GPIO_GYRO_INT, 2); + s3c_gpio_setpull(GPIO_GYRO_INT, S3C_GPIO_PULL_DOWN); + s5p_gpio_set_drvstr(GPIO_GYRO_INT, S5P_GPIO_DRVSTR_LV1); +#if 0 + i2c_devs1[1].irq = gpio_to_irq(GPIO_GYRO_INT); /* interrupt */ +#else + i2c_devs1[1].irq = -1; /* polling */ +#endif + + /* Gyro sensor data enable pin initialization */ + s3c_gpio_cfgpin(GPIO_GYRO_DE, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_GYRO_DE, 0); + s3c_gpio_setpull(GPIO_GYRO_DE, S3C_GPIO_PULL_DOWN); + s5p_gpio_set_drvstr(GPIO_GYRO_DE, S5P_GPIO_DRVSTR_LV1); + + return ret; +} +#endif + +#if defined(CONFIG_SENSORS_GP2A) || defined(CONFIG_SENSORS_CM36651) || \ + defined(CONFIG_SENSORS_CM3663) +static int proximity_leda_on(bool onoff) +{ + pr_info("%s, onoff = %d\n", __func__, onoff); + + gpio_set_value(GPIO_PS_ALS_EN, onoff); + + return 0; +} + +static int optical_gpio_init(void) +{ + int ret = gpio_request(GPIO_PS_ALS_EN, "optical_power_supply_on"); + + pr_info("%s\n", __func__); + + if (ret) { + pr_err("%s, Failed to request gpio optical power supply(%d)\n", + __func__, ret); + return ret; + } + + /* configuring for gp2a gpio for LEDA power */ + s3c_gpio_cfgpin(GPIO_PS_ALS_EN, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_PS_ALS_EN, 0); + s3c_gpio_setpull(GPIO_PS_ALS_EN, S3C_GPIO_PULL_NONE); + return ret; +} +#endif + +#if defined(CONFIG_SENSORS_CM36651) +/* Depends window, threshold is needed to be set */ +static u8 cm36651_get_threshold(void) +{ + u8 threshold = 17; + + /* Add model config and threshold here. */ +#if defined(CONFIG_MACH_M0) + if (system_rev >= 12) + threshold = 13; +#elif defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) ||\ + defined(CONFIG_MACH_C1_KOR_LGT) + if (system_rev >= 6) + threshold = 13; +#elif defined(CONFIG_MACH_M3) + if (system_rev >= 11) + threshold = 13; +#elif defined(CONFIG_MACH_C1) + if (system_rev >= 7) + threshold = 13; +#endif + + return threshold; +} + +static struct cm36651_platform_data cm36651_pdata = { + .cm36651_led_on = proximity_leda_on, + .cm36651_get_threshold = cm36651_get_threshold, + .irq = GPIO_PS_ALS_INT, +}; +#endif + +#if defined(CONFIG_SENSORS_CM3663) +static struct cm3663_platform_data cm3663_pdata = { + .proximity_power = proximity_leda_on, +}; +#endif + +#if defined(CONFIG_SENSORS_GP2A) +static struct gp2a_platform_data gp2a_pdata = { + .gp2a_led_on = proximity_leda_on, + .p_out = GPIO_PS_ALS_INT, +}; + +static struct platform_device opt_gp2a = { + .name = "gp2a-opt", + .id = -1, + .dev = { + .platform_data = &gp2a_pdata, + }, +}; +#endif + +static struct i2c_board_info i2c_devs9_emul[] __initdata = { +#if defined(CONFIG_SENSORS_GP2A) + { + I2C_BOARD_INFO("gp2a", (0x72 >> 1)), + }, +#elif defined(CONFIG_SENSORS_CM36651) + { + I2C_BOARD_INFO("cm36651", (0x30 >> 1)), + .platform_data = &cm36651_pdata, + }, +#elif defined(CONFIG_SENSORS_CM3663) + { + I2C_BOARD_INFO("cm3663", (0x20)), + .irq = GPIO_PS_ALS_INT, + .platform_data = &cm3663_pdata, + }, +#elif defined(CONFIG_SENSORS_BH1721) + { + I2C_BOARD_INFO("bh1721fvc", 0x23), + }, +#endif +}; + +#ifdef CONFIG_SENSORS_AK8975C +static struct akm8975_platform_data akm8975_pdata = { + .gpio_data_ready_int = GPIO_MSENSOR_INT, +}; + +static struct i2c_board_info i2c_devs10_emul[] __initdata = { + { + I2C_BOARD_INFO("ak8975", 0x0C), + .platform_data = &akm8975_pdata, + }, +}; + +static int ak8975c_gpio_init(void) +{ + int ret = gpio_request(GPIO_MSENSOR_INT, "gpio_akm_int"); + + pr_info("%s\n", __func__); + + if (ret) { + pr_err("%s, Failed to request gpio akm_int.(%d)\n", + __func__, ret); + return ret; + } + + s5p_register_gpio_interrupt(GPIO_MSENSOR_INT); + s3c_gpio_setpull(GPIO_MSENSOR_INT, S3C_GPIO_PULL_DOWN); + s3c_gpio_cfgpin(GPIO_MSENSOR_INT, S3C_GPIO_SFN(0xF)); + i2c_devs10_emul[0].irq = gpio_to_irq(GPIO_MSENSOR_INT); + return ret; +} +#endif + +#ifdef CONFIG_SENSORS_AK8963C +static struct akm8963_platform_data akm8963_pdata = { + .gpio_data_ready_int = GPIO_MSENSOR_INT, + .layout = 1, + .outbit = 1, +}; + +static struct i2c_board_info i2c_devs10_emul[] __initdata = { + { + I2C_BOARD_INFO("ak8963", 0x0C), + .platform_data = &akm8963_pdata, + }, +}; + +static int ak8963c_gpio_init(void) +{ + int ret = gpio_request(GPIO_MSENSOR_INT, "gpio_akm_int"); + + pr_info("%s\n", __func__); + + if (ret) { + pr_err("%s, Failed to request gpio akm_int.(%d)\n", + __func__, ret); + return ret; + } + + gpio_set_value(GPIO_MSENSE_RST_N, 1); + + s5p_register_gpio_interrupt(GPIO_MSENSOR_INT); + s3c_gpio_setpull(GPIO_MSENSOR_INT, S3C_GPIO_PULL_DOWN); + s3c_gpio_cfgpin(GPIO_MSENSOR_INT, S3C_GPIO_SFN(0xF)); + i2c_devs10_emul[0].irq = gpio_to_irq(GPIO_MSENSOR_INT); + return ret; +} +#endif + +#ifdef CONFIG_SENSORS_LPS331 +static int lps331_gpio_init(void) +{ + int ret = gpio_request(GPIO_BARO_INT, "lps331_irq"); + + pr_info("%s\n", __func__); + + if (ret) { + pr_err("%s, Failed to request gpio lps331_irq(%d)\n", + __func__, ret); + return ret; + } + + s3c_gpio_cfgpin(GPIO_BARO_INT, S3C_GPIO_INPUT); + gpio_set_value(GPIO_BARO_INT, 2); + s3c_gpio_setpull(GPIO_BARO_INT, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(GPIO_BARO_INT, S5P_GPIO_DRVSTR_LV1); + return ret; +} + +static struct lps331ap_platform_data lps331ap_pdata = { + .irq = GPIO_BARO_INT, +}; + +static struct i2c_board_info i2c_devs11_emul[] __initdata = { + { + I2C_BOARD_INFO("lps331ap", 0x5D), + .platform_data = &lps331ap_pdata, + }, +}; +#endif + +static int __init midas_sensor_init(void) +{ + int ret = 0; + + /* Gyro & Accelerometer Sensor */ +#if defined(CONFIG_SENSORS_LSM330DLC) + ret = accel_gpio_init(); + if (ret < 0) { + pr_err("%s, accel_gpio_init fail(err=%d)\n", __func__, ret); + return ret; + } + ret = gyro_gpio_init(); + if (ret < 0) { + pr_err("%s, gyro_gpio_init(err=%d)\n", __func__, ret); + return ret; + } +#elif defined(CONFIG_SENSORS_K3DH) + ret = accel_gpio_init(); + if (ret < 0) { + pr_err("%s, accel_gpio_init fail(err=%d)\n", __func__, ret); + return ret; + } +#endif + ret = i2c_add_devices(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + if (ret < 0) { + pr_err("%s, i2c1 adding i2c fail(err=%d)\n", __func__, ret); + return ret; + } + + /* Optical Sensor */ +#if defined(CONFIG_SENSORS_GP2A) || defined(CONFIG_SENSORS_CM36651) || \ + defined(CONFIG_SENSORS_CM3663) + ret = optical_gpio_init(); + if (ret) { + pr_err("%s, optical_gpio_init(err=%d)\n", __func__, ret); + return ret; + } + ret = i2c_add_devices(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul)); + if (ret < 0) { + pr_err("%s, i2c9 adding i2c fail(err=%d)\n", __func__, ret); + return ret; + } +#elif defined(CONFIG_SENSORS_BH1721) + ret = i2c_add_devices(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul)); + if (ret < 0) { + pr_err("%s, i2c9 adding i2c fail(err=%d)\n", __func__, ret); + return ret; + } +#endif + +#if defined(CONFIG_SENSORS_GP2A) + ret = platform_device_register(&opt_gp2a); + if (ret < 0) { + pr_err("%s, failed to register opt_gp2a(err=%d)\n", + __func__, ret); + return ret; + } +#endif + + /* Magnetic Sensor */ +#ifdef CONFIG_SENSORS_AK8975C + ret = ak8975c_gpio_init(); + if (ret < 0) { + pr_err("%s, ak8975c_gpio_init fail(err=%d)\n", __func__, ret); + return ret; + } + ret = i2c_add_devices(10, i2c_devs10_emul, ARRAY_SIZE(i2c_devs10_emul)); + if (ret < 0) { + pr_err("%s, i2c10 adding i2c fail(err=%d)\n", __func__, ret); + return ret; + } +#endif + /* Magnetic Sensor */ +#ifdef CONFIG_SENSORS_AK8963C + ret = ak8963c_gpio_init(); + if (ret < 0) { + pr_err("%s, ak8975c_gpio_init fail(err=%d)\n", __func__, ret); + return ret; + } + ret = i2c_add_devices(10, i2c_devs10_emul, ARRAY_SIZE(i2c_devs10_emul)); + if (ret < 0) { + pr_err("%s, i2c10 adding i2c fail(err=%d)\n", __func__, ret); + return ret; + } +#endif + + /* Pressure Sensor */ +#ifdef CONFIG_SENSORS_LPS331 + ret = lps331_gpio_init(); + if (ret < 0) { + pr_err("%s, ak8975c_gpio_init fail(err=%d)\n", __func__, ret); + return ret; + } + ret = i2c_add_devices(11, i2c_devs11_emul, ARRAY_SIZE(i2c_devs11_emul)); + if (ret < 0) { + pr_err("%s, i2c1 adding i2c fail(err=%d)\n", __func__, ret); + return ret; + } +#endif + return ret; +} +module_init(midas_sensor_init); diff --git a/arch/arm/mach-exynos/board-grande-sound.c b/arch/arm/mach-exynos/board-grande-sound.c new file mode 100644 index 0000000..e07444a --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-sound.c @@ -0,0 +1,371 @@ +/* + * midas-sound.c - Sound Management of MIDAS Project + * + * Copyright (C) 2012 Samsung Electrnoics + * JS Park <aitdark.park@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/i2c.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/i2c-gpio.h> +#include <mach/irqs.h> +#include <mach/pmu.h> +#include <plat/iic.h> + +#include <plat/gpio-cfg.h> +#ifdef CONFIG_ARCH_EXYNOS5 +#include <mach/gpio-p10.h> +#else +#include <mach/gpio-midas.h> +#endif + +#ifdef CONFIG_SND_SOC_WM8994 +#include <linux/mfd/wm8994/pdata.h> +#include <linux/mfd/wm8994/gpio.h> +#endif + +#ifdef CONFIG_FM34_WE395 +#include <linux/i2c/fm34_we395.h> +#endif + +#ifdef CONFIG_AUDIENCE_ES305 +#include <linux/i2c/es305.h> +#endif + +static bool midas_snd_mclk_enabled; + +#ifdef CONFIG_ARCH_EXYNOS5 +#define I2C_NUM_2MIC 4 +#define I2C_NUM_CODEC 7 +#define SET_PLATDATA_2MIC(i2c_pd) s3c_i2c4_set_platdata(i2c_pd) +#define SET_PLATDATA_CODEC(i2c_pd) s3c_i2c7_set_platdata(i2c_pd) +#else /* for CONFIG_ARCH_EXYNOS4 */ +#define I2C_NUM_2MIC 6 +#define I2C_NUM_CODEC 4 +#define SET_PLATDATA_2MIC(i2c_pd) s3c_i2c6_set_platdata(i2c_pd) +#define SET_PLATDATA_CODEC(i2c_pd) s3c_i2c4_set_platdata(i2c_pd) +#endif + +static DEFINE_SPINLOCK(midas_snd_spinlock); + +void midas_snd_set_mclk(bool on, bool forced) +{ + static int use_cnt; + + spin_lock(&midas_snd_spinlock); + + midas_snd_mclk_enabled = on; + + if (midas_snd_mclk_enabled) { + if (use_cnt++ == 0 || forced) { + printk(KERN_INFO "Sound: enabled mclk\n"); +#ifdef CONFIG_ARCH_EXYNOS5 + exynos5_pmu_xclkout_set(midas_snd_mclk_enabled, + XCLKOUT_XXTI); +#else /* for CONFIG_ARCH_EXYNOS4 */ + exynos4_pmu_xclkout_set(midas_snd_mclk_enabled, + XCLKOUT_XUSBXTI); +#endif + mdelay(10); + } + } else { + if ((--use_cnt <= 0) || forced) { + printk(KERN_INFO "Sound: disabled mclk\n"); +#ifdef CONFIG_ARCH_EXYNOS5 + exynos5_pmu_xclkout_set(midas_snd_mclk_enabled, + XCLKOUT_XXTI); +#else /* for CONFIG_ARCH_EXYNOS4 */ + exynos4_pmu_xclkout_set(midas_snd_mclk_enabled, + XCLKOUT_XUSBXTI); +#endif + use_cnt = 0; + } + } + + spin_unlock(&midas_snd_spinlock); + + printk(KERN_INFO "Sound: state: %d, use_cnt: %d\n", + midas_snd_mclk_enabled, use_cnt); +} + +bool midas_snd_get_mclk(void) +{ + return midas_snd_mclk_enabled; +} + +#ifdef CONFIG_SND_SOC_WM8994 +/* vbatt_devices */ +static struct regulator_consumer_supply vbatt_supplies[] = { + REGULATOR_SUPPLY("LDO1VDD", NULL), + REGULATOR_SUPPLY("SPKVDD1", NULL), + REGULATOR_SUPPLY("SPKVDD2", NULL), +}; + +static struct regulator_init_data vbatt_initdata = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vbatt_supplies), + .consumer_supplies = vbatt_supplies, +}; + +static struct fixed_voltage_config vbatt_config = { + .init_data = &vbatt_initdata, + .microvolts = 5000000, + .supply_name = "VBATT", + .gpio = -EINVAL, +}; + +struct platform_device vbatt_device = { + .name = "reg-fixed-voltage", + .id = -1, + .dev = { + .platform_data = &vbatt_config, + }, +}; + +/* wm1811 ldo1 */ +static struct regulator_consumer_supply wm1811_ldo1_supplies[] = { + REGULATOR_SUPPLY("AVDD1", NULL), +}; + +static struct regulator_init_data wm1811_ldo1_initdata = { + .constraints = { + .name = "WM1811 LDO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(wm1811_ldo1_supplies), + .consumer_supplies = wm1811_ldo1_supplies, +}; + +/* wm1811 ldo2 */ +static struct regulator_consumer_supply wm1811_ldo2_supplies[] = { + REGULATOR_SUPPLY("DCVDD", NULL), +}; + +static struct regulator_init_data wm1811_ldo2_initdata = { + .constraints = { + .name = "WM1811 LDO2", + .always_on = true, /* Actually status changed by LDO1 */ + }, + .num_consumer_supplies = ARRAY_SIZE(wm1811_ldo2_supplies), + .consumer_supplies = wm1811_ldo2_supplies, +}; + +static struct wm8994_drc_cfg drc_value[] = { + { + .name = "voice call DRC", + .regs[0] = 0x009B, + .regs[1] = 0x0844, + .regs[2] = 0x00E8, + .regs[3] = 0x0210, + .regs[4] = 0x0000, + }, +#if defined(CONFIG_MACH_C1_KOR_LGT) + { + .name = "voice call DRC", + .regs[0] = 0x008c, + .regs[1] = 0x0253, + .regs[2] = 0x0028, + .regs[3] = 0x028c, + .regs[4] = 0x0000, + }, +#endif +#if defined(CONFIG_MACH_P4NOTE) +{ + .name = "cam rec DRC", + .regs[0] = 0x019B, + .regs[1] = 0x0844, + .regs[2] = 0x0408, + .regs[3] = 0x0108, + .regs[4] = 0x0120, + }, +#endif +}; + +static struct wm8994_pdata wm1811_pdata = { + .gpio_defaults = { + [0] = WM8994_GP_FN_IRQ, /* GPIO1 IRQ output, CMOS mode */ + [7] = WM8994_GPN_DIR | WM8994_GP_FN_PIN_SPECIFIC, /* DACDAT3 */ + [8] = WM8994_CONFIGURE_GPIO | + WM8994_GP_FN_PIN_SPECIFIC, /* ADCDAT3 */ + [9] = WM8994_CONFIGURE_GPIO |\ + WM8994_GP_FN_PIN_SPECIFIC, /* LRCLK3 */ + [10] = WM8994_CONFIGURE_GPIO |\ + WM8994_GP_FN_PIN_SPECIFIC, /* BCLK3 */ + }, + + .irq_base = IRQ_BOARD_CODEC_START, + + /* The enable is shared but assign it to LDO1 for software */ + .ldo = { + { + .enable = GPIO_WM8994_LDO, + .init_data = &wm1811_ldo1_initdata, + }, + { + .init_data = &wm1811_ldo2_initdata, + }, + }, + /* Apply DRC Value */ + .drc_cfgs = drc_value, + .num_drc_cfgs = ARRAY_SIZE(drc_value), + + /* Support external capacitors*/ + .jd_ext_cap = 1, + + /* Regulated mode at highest output voltage */ +#ifdef CONFIG_TARGET_LOCALE_KOR + .micbias = {0x22, 0x22}, +#else + .micbias = {0x2f, 0x2f}, +#endif + + .micd_lvl_sel = 0xFF, + + .ldo_ena_always_driven = true, + .ldo_ena_delay = 30000, +#ifdef CONFIG_TARGET_LOCALE_KOR + .lineout2_diff = 0, +#endif +#ifdef CONFIG_MACH_C1 + .lineout1fb = 0, +#else + .lineout1fb = 1, +#endif +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1_KOR_SKT) || \ + defined(CONFIG_MACH_C1_KOR_KT) || defined(CONFIG_MACH_C1_KOR_LGT) || \ + defined(CONFIG_MACH_P4NOTE) || defined(CONFIG_MACH_GC1) \ + || defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) + .lineout2fb = 0, +#else + .lineout2fb = 1, +#endif +}; + +static struct i2c_board_info i2c_wm1811[] __initdata = { + { + I2C_BOARD_INFO("wm1811", (0x34 >> 1)), /* Audio CODEC */ + .platform_data = &wm1811_pdata, + .irq = IRQ_EINT(30), + }, +}; + +#endif + +#ifdef CONFIG_FM34_WE395 +static struct fm34_platform_data fm34_we395_pdata = { + .gpio_pwdn = GPIO_FM34_PWDN, + .gpio_rst = GPIO_FM34_RESET, + .gpio_bp = GPIO_FM34_BYPASS, + .set_mclk = midas_snd_set_mclk, +}; +#ifdef CONFIG_MACH_C1_KOR_LGT +static struct fm34_platform_data fm34_we395_pdata_rev05 = { + .gpio_pwdn = GPIO_FM34_PWDN, + .gpio_rst = GPIO_FM34_RESET_05, + .gpio_bp = GPIO_FM34_BYPASS_05, + .set_mclk = midas_snd_set_mclk, +}; +#endif +static struct i2c_board_info i2c_2mic[] __initdata = { + { + I2C_BOARD_INFO("fm34_we395", (0xC0 >> 1)), /* 2MIC */ + .platform_data = &fm34_we395_pdata, + }, +}; + +#if defined(CONFIG_MACH_C1_KOR_LGT) +static struct i2c_gpio_platform_data gpio_i2c_fm34 = { + .sda_pin = GPIO_FM34_SDA, + .scl_pin = GPIO_FM34_SCL, +}; + +struct platform_device s3c_device_fm34 = { + .name = "i2c-gpio", + .id = I2C_NUM_2MIC, + .dev.platform_data = &gpio_i2c_fm34, +}; +#endif +#endif + +#ifdef CONFIG_AUDIENCE_ES305 +static struct es305_platform_data es305_pdata = { + .gpio_wakeup = GPIO_ES305_WAKEUP, + .gpio_reset = GPIO_ES305_RESET, + .set_mclk = midas_snd_set_mclk, +}; + +static struct i2c_board_info i2c_2mic[] __initdata = { + { + I2C_BOARD_INFO("audience_es305", 0x3E), /* 2MIC */ + .platform_data = &es305_pdata, + }, +}; +#endif + +static struct platform_device *midas_sound_devices[] __initdata = { +#if defined(CONFIG_MACH_C1_KOR_LGT) +#ifdef CONFIG_FM34_WE395 + &s3c_device_fm34, +#endif +#endif +}; + +void __init midas_sound_init(void) +{ + printk(KERN_INFO "Sound: start %s\n", __func__); + + platform_add_devices(midas_sound_devices, + ARRAY_SIZE(midas_sound_devices)); + +#ifdef CONFIG_ARCH_EXYNOS5 +#ifndef CONFIG_MACH_P10_LTE_00_BD + i2c_wm1811[0].irq = IRQ_EINT(29); +#endif + SET_PLATDATA_CODEC(NULL); + i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811, + ARRAY_SIZE(i2c_wm1811)); +#else /* for CONFIG_ARCH_EXYNOS4 */ + i2c_wm1811[0].irq = 0; + SET_PLATDATA_CODEC(NULL); + i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811, + ARRAY_SIZE(i2c_wm1811)); +#endif/* CONFIG_ARCH_EXYNOS5 */ + +#ifdef CONFIG_FM34_WE395 + midas_snd_set_mclk(true, false); + SET_PLATDATA_2MIC(NULL); + +#if defined(CONFIG_MACH_C1_KOR_LGT) + if (system_rev > 5) + i2c_2mic[0].platform_data = &fm34_we395_pdata_rev05; +#endif + + i2c_register_board_info(I2C_NUM_2MIC, i2c_2mic, ARRAY_SIZE(i2c_2mic)); +#endif + + +#ifdef CONFIG_AUDIENCE_ES305 + midas_snd_set_mclk(true, false); + SET_PLATDATA_2MIC(NULL); + i2c_register_board_info(I2C_NUM_2MIC, i2c_2mic, ARRAY_SIZE(i2c_2mic)); +#endif +} diff --git a/arch/arm/mach-exynos/board-grande-thermistor.c b/arch/arm/mach-exynos/board-grande-thermistor.c new file mode 100755 index 0000000..6615a14 --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-thermistor.c @@ -0,0 +1,585 @@ +/* + * midas-thermistor.c - thermistor of MIDAS Project + * + * Copyright (C) 2011 Samsung Electrnoics + * SangYoung Son <hello.son@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <mach/midas-thermistor.h> +#ifdef CONFIG_SEC_THERMISTOR +#include <mach/sec_thermistor.h> +#endif + +#ifdef CONFIG_S3C_ADC +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_P4NOTE) \ + || defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 204, 800 }, + { 210, 790 }, + { 216, 780 }, + { 223, 770 }, + { 230, 760 }, + { 237, 750 }, + { 244, 740 }, + { 252, 730 }, + { 260, 720 }, + { 268, 710 }, + { 276, 700 }, + { 285, 690 }, + { 294, 680 }, + { 303, 670 }, + { 312, 660 }, + { 322, 650 }, + { 332, 640 }, + { 342, 630 }, + { 353, 620 }, + { 364, 610 }, + { 375, 600 }, + { 387, 590 }, + { 399, 580 }, + { 411, 570 }, + { 423, 560 }, + { 436, 550 }, + { 450, 540 }, + { 463, 530 }, + { 477, 520 }, + { 492, 510 }, + { 507, 500 }, + { 522, 490 }, + { 537, 480 }, + { 553, 470 }, + { 569, 460 }, + { 586, 450 }, + { 603, 440 }, + { 621, 430 }, + { 638, 420 }, + { 657, 410 }, + { 675, 400 }, + { 694, 390 }, + { 713, 380 }, + { 733, 370 }, + { 753, 360 }, + { 773, 350 }, + { 794, 340 }, + { 815, 330 }, + { 836, 320 }, + { 858, 310 }, + { 880, 300 }, + { 902, 290 }, + { 924, 280 }, + { 947, 270 }, + { 969, 260 }, + { 992, 250 }, + { 1015, 240 }, + { 1039, 230 }, + { 1062, 220 }, + { 1086, 210 }, + { 1109, 200 }, + { 1133, 190 }, + { 1156, 180 }, + { 1180, 170 }, + { 1204, 160 }, + { 1227, 150 }, + { 1250, 140 }, + { 1274, 130 }, + { 1297, 120 }, + { 1320, 110 }, + { 1343, 100 }, + { 1366, 90 }, + { 1388, 80 }, + { 1410, 70 }, + { 1432, 60 }, + { 1454, 50 }, + { 1475, 40 }, + { 1496, 30 }, + { 1516, 20 }, + { 1536, 10 }, + { 1556, 0 }, + { 1576, -10 }, + { 1595, -20 }, + { 1613, -30 }, + { 1631, -40 }, + { 1649, -50 }, + { 1666, -60 }, + { 1683, -70 }, + { 1699, -80 }, + { 1714, -90 }, + { 1730, -100 }, + { 1744, -110 }, + { 1759, -120 }, + { 1773, -130 }, + { 1786, -140 }, + { 1799, -150 }, + { 1811, -160 }, + { 1823, -170 }, + { 1835, -180 }, + { 1846, -190 }, + { 1856, -200 }, +}; +#elif defined(CONFIG_MACH_C1) +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 178, 800 }, + { 186, 790 }, + { 193, 780 }, + { 198, 770 }, + { 204, 760 }, + { 210, 750 }, + { 220, 740 }, + { 226, 730 }, + { 232, 720 }, + { 247, 710 }, + { 254, 700 }, + { 261, 690 }, + { 270, 680 }, + { 278, 670 }, + { 285, 660 }, + { 292, 650 }, + { 304, 640 }, + { 319, 630 }, + { 325, 620 }, + { 331, 610 }, + { 343, 600 }, + { 354, 590 }, + { 373, 580 }, + { 387, 570 }, + { 392, 560 }, + { 408, 550 }, + { 422, 540 }, + { 433, 530 }, + { 452, 520 }, + { 466, 510 }, + { 479, 500 }, + { 497, 490 }, + { 510, 480 }, + { 529, 470 }, + { 545, 460 }, + { 562, 450 }, + { 578, 440 }, + { 594, 430 }, + { 620, 420 }, + { 632, 410 }, + { 651, 400 }, + { 663, 390 }, + { 681, 380 }, + { 705, 370 }, + { 727, 360 }, + { 736, 350 }, + { 778, 340 }, + { 793, 330 }, + { 820, 320 }, + { 834, 310 }, + { 859, 300 }, + { 872, 290 }, + { 891, 280 }, + { 914, 270 }, + { 939, 260 }, + { 951, 250 }, + { 967, 240 }, + { 999, 230 }, + { 1031, 220 }, + { 1049, 210 }, + { 1073, 200 }, + { 1097, 190 }, + { 1128, 180 }, + { 1140, 170 }, + { 1171, 160 }, + { 1188, 150 }, + { 1198, 140 }, + { 1223, 130 }, + { 1236, 120 }, + { 1274, 110 }, + { 1290, 100 }, + { 1312, 90 }, + { 1321, 80 }, + { 1353, 70 }, + { 1363, 60 }, + { 1404, 50 }, + { 1413, 40 }, + { 1444, 30 }, + { 1461, 20 }, + { 1470, 10 }, + { 1516, 0 }, + { 1522, -10 }, + { 1533, -20 }, + { 1540, -30 }, + { 1558, -40 }, + { 1581, -50 }, + { 1595, -60 }, + { 1607, -70 }, + { 1614, -80 }, + { 1627, -90 }, + { 1655, -100 }, + { 1664, -110 }, + { 1670, -120 }, + { 1676, -130 }, + { 1692, -140 }, + { 1713, -150 }, + { 1734, -160 }, + { 1746, -170 }, + { 1789, -180 }, + { 1805, -190 }, + { 1824, -200 }, +}; +#else /* sample */ +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 305, 650 }, + { 566, 430 }, + { 1494, 0 }, + { 1571, -50 }, +}; +#endif + +int convert_adc(int adc_data, int channel) +{ + int adc_value; + int low, mid, high; + struct adc_table_data *temper_table = NULL; + pr_debug("%s\n", __func__); + + low = mid = high = 0; + switch (channel) { + case 1: + temper_table = ap_adc_temper_table_battery; + high = ARRAY_SIZE(ap_adc_temper_table_battery) - 1; + break; + case 2: + temper_table = ap_adc_temper_table_battery; + high = ARRAY_SIZE(ap_adc_temper_table_battery) - 1; + break; + default: + pr_info("%s: not exist temper table for ch(%d)\n", __func__, + channel); + return -EINVAL; + break; + } + + /* Out of table range */ + if (adc_data <= temper_table[low].adc) { + adc_value = temper_table[low].value; + return adc_value; + } else if (adc_data >= temper_table[high].adc) { + adc_value = temper_table[high].value; + return adc_value; + } + + while (low <= high) { + mid = (low + high) / 2; + if (temper_table[mid].adc > adc_data) + high = mid - 1; + else if (temper_table[mid].adc < adc_data) + low = mid + 1; + else + break; + } + adc_value = temper_table[mid].value; + + /* high resolution */ + if (adc_data < temper_table[mid].adc) + adc_value = temper_table[mid].value + + ((temper_table[mid-1].value - temper_table[mid].value) * + (temper_table[mid].adc - adc_data) / + (temper_table[mid].adc - temper_table[mid-1].adc)); + else + adc_value = temper_table[mid].value - + ((temper_table[mid].value - temper_table[mid+1].value) * + (adc_data - temper_table[mid].adc) / + (temper_table[mid+1].adc - temper_table[mid].adc)); + + pr_debug("%s: adc data(%d), adc value(%d)\n", __func__, + adc_data, adc_value); + return adc_value; + +} +#endif + +#ifdef CONFIG_SEC_THERMISTOR +static struct sec_therm_adc_table temper_table_ap[] = { + {196, 700}, + {211, 690}, + {242, 685}, + {249, 680}, + {262, 670}, + {275, 660}, + {288, 650}, + {301, 640}, + {314, 630}, + {328, 620}, + {341, 610}, + {354, 600}, + {366, 590}, + {377, 580}, + {389, 570}, + {404, 560}, + {419, 550}, + {434, 540}, + {452, 530}, + {469, 520}, + {487, 510}, + {498, 500}, + {509, 490}, + {520, 480}, + {529, 460}, + {538, 470}, + {547, 450}, + {556, 440}, + {564, 430}, + {573, 420}, + {581, 410}, + {590, 400}, + {615, 390}, + {640, 380}, + {665, 370}, + {690, 360}, + {715, 350}, + {736, 340}, + {758, 330}, + {779, 320}, + {801, 310}, + {822, 300}, +}; + +/* when the next level is same as prev, returns -1 */ +static int get_midas_siop_level(int temp) +{ + static int prev_temp = 400; + static int prev_level = 0; + int level = -1; + +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) + if (temp > prev_temp) { + if (temp >= 490) + level = 4; + else if (temp >= 480) + level = 3; + else if (temp >= 450) + level = 2; + else if (temp >= 420) + level = 1; + else + level = 0; + } else { + if (temp < 400) + level = 0; + else if (temp < 420) + level = 1; + else if (temp < 450) + level = 2; + else if (temp < 480) + level = 3; + else + level = 4; + + if (level > prev_level) + level = prev_level; + } +#elif defined(CONFIG_MACH_P4NOTE) + if (temp > prev_temp) { + if (temp >= 620) + level = 4; + else if (temp >= 610) + level = 3; + else if (temp >= 580) + level = 2; + else if (temp >= 550) + level = 1; + else + level = 0; + } else { + if (temp < 520) + level = 0; + else if (temp < 550) + level = 1; + else if (temp < 580) + level = 2; + else if (temp < 610) + level = 3; + else + level = 4; + + if (level > prev_level) + level = prev_level; + } +#else + if (temp > prev_temp) { + if (temp >= 540) + level = 4; + else if (temp >= 530) + level = 3; + else if (temp >= 480) + level = 2; + else if (temp >= 440) + level = 1; + else + level = 0; + } else { + if (temp < 410) + level = 0; + else if (temp < 440) + level = 1; + else if (temp < 480) + level = 2; + else if (temp < 530) + level = 3; + else + level = 4; + + if (level > prev_level) + level = prev_level; + } +#endif + + prev_temp = temp; + if (prev_level == level) + return -1; + + prev_level = level; + + return level; +} + +static struct sec_therm_platform_data sec_therm_pdata = { + .adc_channel = 1, + .adc_arr_size = ARRAY_SIZE(temper_table_ap), + .adc_table = temper_table_ap, + .polling_interval = 30 * 1000, /* msecs */ + .get_siop_level = get_midas_siop_level, +}; + +struct platform_device sec_device_thermistor = { + .name = "sec-thermistor", + .id = -1, + .dev.platform_data = &sec_therm_pdata, +}; +#endif + +#ifdef CONFIG_STMPE811_ADC +/* temperature table for ADC ch7 */ +static struct adc_table_data temper_table_battery[] = { + { 1856, -20 }, + { 1846, -19 }, + { 1835, -18 }, + { 1823, -17 }, + { 1811, -16 }, + { 1799, -15 }, + { 1786, -14 }, + { 1773, -13 }, + { 1759, -12 }, + { 1744, -11 }, + { 1730, -10 }, + { 1714, -9 }, + { 1699, -8 }, + { 1683, -7 }, + { 1666, -6 }, + { 1649, -5 }, + { 1631, -4 }, + { 1613, -3 }, + { 1595, -2 }, + { 1576, -1 }, + { 1556, 0 }, + { 1536, 1 }, + { 1516, 2 }, + { 1496, 3 }, + { 1475, 4 }, + { 1454, 5 }, + { 1432, 6 }, + { 1410, 7 }, + { 1388, 8 }, + { 1366, 9 }, + { 1343, 10 }, + { 1320, 11 }, + { 1297, 12 }, + { 1274, 13 }, + { 1250, 14 }, + { 1227, 15 }, + { 1204, 16 }, + { 1180, 17 }, + { 1156, 18 }, + { 1133, 19 }, + { 1109, 20 }, + { 1086, 21 }, + { 1062, 22 }, + { 1039, 23 }, + { 1015, 24 }, + { 992, 25 }, + { 969, 26 }, + { 947, 27 }, + { 924, 28 }, + { 902, 29 }, + { 880, 30 }, + { 858, 31 }, + { 836, 32 }, + { 815, 33 }, + { 794, 34 }, + { 773, 35 }, + { 753, 36 }, + { 733, 37 }, + { 713, 38 }, + { 694, 39 }, + { 675, 40 }, + { 657, 41 }, + { 638, 42 }, + { 621, 43 }, + { 603, 44 }, + { 586, 45 }, + { 569, 46 }, + { 553, 47 }, + { 537, 48 }, + { 522, 49 }, + { 507, 50 }, + { 492, 51 }, + { 477, 52 }, + { 463, 53 }, + { 450, 54 }, + { 436, 55 }, + { 423, 56 }, + { 411, 57 }, + { 399, 58 }, + { 387, 59 }, + { 375, 60 }, + { 364, 61 }, + { 353, 62 }, + { 342, 63 }, + { 332, 64 }, + { 322, 65 }, + { 312, 66 }, + { 303, 67 }, + { 294, 68 }, + { 285, 69 }, + { 276, 70 }, + { 268, 71 }, + { 260, 72 }, + { 252, 73 }, + { 244, 74 }, + { 237, 75 }, + { 230, 76 }, + { 223, 77 }, + { 216, 78 }, + { 210, 79 }, + { 204, 80 }, +}; + +struct stmpe811_platform_data stmpe811_pdata = { + .adc_table_ch4 = temper_table_battery, + .table_size_ch4 = ARRAY_SIZE(temper_table_battery), + .adc_table_ch7 = temper_table_battery, + .table_size_ch7 = ARRAY_SIZE(temper_table_battery), + + .irq_gpio = GPIO_ADC_INT, +}; +#endif + diff --git a/arch/arm/mach-exynos/board-grande-tsp.c b/arch/arm/mach-exynos/board-grande-tsp.c new file mode 100755 index 0000000..c6f9603 --- /dev/null +++ b/arch/arm/mach-exynos/board-grande-tsp.c @@ -0,0 +1,306 @@ +/* + * linux/arch/arm/mach-exynos/midas-tsp.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/i2c.h> +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/i2c/mxt224s_grande.h> +#include <linux/regulator/consumer.h> +#include <plat/gpio-cfg.h> + +extern bool is_cable_attached; + +static struct charging_status_callbacks { + void (*tsp_set_charging_cable) (int type); +} charging_cbs; + +void tsp_register_callback(void *function) +{ + charging_cbs.tsp_set_charging_cable = function; +} + +void tsp_read_ta_status(void *ta_status) +{ + *(bool *) ta_status = is_cable_attached; +} + +void tsp_charger_infom(bool en) +{ + if (charging_cbs.tsp_set_charging_cable) + charging_cbs.tsp_set_charging_cable(en); +} + +static void mxt224s_power_on(void) +{ + gpio_set_value(GPIO_TSP_EN, 1); + mdelay(30); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); + printk(KERN_INFO "mxt224s_power_on is finished\n"); +} + +EXPORT_SYMBOL(mxt224s_power_on); + +static void mxt224s_power_off(void) +{ + gpio_set_value(GPIO_TSP_EN, 0); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN); + printk(KERN_INFO "mxt224s_power_off is finished\n"); +} + +EXPORT_SYMBOL(mxt224s_power_off); + +/* + Configuration for MXT224-S +*/ +#define MXT224S_MAX_MT_FINGERS 5 +#define MXT224S_CHRGTIME_BATT 25 +#define MXT224S_CHRGTIME_CHRG 60 +#define MXT224S_THRESHOLD_BATT 60 +#define MXT224S_THRESHOLD_CHRG 70 +#define MXT224S_CALCFG_BATT 210 +#define MXT224S_CALCFG_CHRG 210 + + +static u8 t7_config_s[] = { GEN_POWERCONFIG_T7, +0x20, 0xFF, 0x32, 0x03 +}; + +static u8 t8_config_s[] = { GEN_ACQUISITIONCONFIG_T8, +0x01, 0x00, 0x05, 0x01, 0x00, 0x00, 0x0A, 0x1E, 0x00, 0x00 +}; + +static u8 t9_config_s[] = { TOUCH_MULTITOUCHSCREEN_T9, + 0x83, 0x00, 0x00, 0x13, 0x0B, 0x00, 0x60, 0x37, 0x02, 0x07, + 0x0A, 0x0A, 0x01, 0x3F, 0x0A, 0x0F, 0x1E, 0x0A, 0x1F, 0x03, +0xDF, 0x01, 0x0F, 0x0F, 0x19, 0x19, 0x80, 0x00, 0xC0, 0x00, +0x14, 0x0F, 0x00, 0x00, 0x00, 0x00 +}; + + static u8 t9_config_s_ta[] = { TOUCH_MULTITOUCHSCREEN_T9, + 0x83, 0x00, 0x00, 0x13, 0x0B, 0x00, 80, 40, 0x02, 0x07, + 0x0A, 0x0A, 0x01, 65, 0x0A, 0x0F, 0x1E, 0x0A, 0x1F, 0x03, + 0xDF, 0x01, 15, 15, 25, 25, 0x80, 0x00, 0xC0, 0x00, + 0x14, 0x0F, 0x00, 0x00, 0x00, 0x00 + }; + +static u8 t15_config_s[] = { TOUCH_KEYARRAY_T15, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 +}; + +static u8 t18_config_s[] = { SPT_COMCONFIG_T18, + 0, 0 +}; + +static u8 t19_config_s[] = { SPT_GPIOPWM_T19, + 0, 0, 0, 0, 0, 0 +}; + +static u8 t23_config_s[] = { TOUCH_PROXIMITY_T23, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0 +}; + +static u8 t25_config_s[] = { SPT_SELFTEST_T25, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0 +}; + +static u8 t40_config_s[] = { PROCI_GRIPSUPPRESSION_T40, + 0, 0, 0, 0, 0 +}; + +static u8 t42_config_s[] = { PROCI_TOUCHSUPPRESSION_T42, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t46_config_s[] = { SPT_CTECONFIG_T46, +0x04, 0x00, 0x10, 0x20, 0x00, 0x01, 0x03, 0x00, 0x00, 0x01 +}; + +static u8 t47_config_s[] = { PROCI_STYLUS_T47, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00 +}; + +static u8 t55_config_s[] = { PROCI_ADAPTIVETHRESHOLD_T55, + 0, 0, 0, 0, 0, 0 +}; + +static u8 t56_config_s[] = { PROCI_SHIELDLESS_T56, + 0x03, 0x00, 0x01, 0x26, 0x0A, 0x0A, 0x0A, 0x0C, 0x0C, 0x0C, + 0x0C, 0x0D, 0x0E, 0x0E, 0x0E, 0x0E, 0x10, 0x10, 0x12, 0x12, + 0x12, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 +}; + +static u8 t56_config_s_ta[] = { PROCI_SHIELDLESS_T56, + 0x03, 0x00, 0x01, 0x1E, 0x0A, 0x0A, 0x0A, 0x0C, 0x0C, 0x0C, + 0x0C, 0x0D, 0x0E, 0x0E, 0x0E, 0x0E, 0x10, 0x10, 0x12, 0x12, + 0x12, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00 + }; + +static u8 t57_config_s[] = { PROCI_EXTRATOUCHSCREENDATA_T57, + 0xE3, 0x0F, 0x00 +}; + +static u8 t61_config_s[] = {SPT_TIMER_T61, + 0x03, 0x00, 0x00, 0x00, 0x00 +}; + +static u8 t62_config_s[] = { PROCG_NOISESUPPRESSION_T62, +0x4F, 0x02, 0x00, 0x16, 0x08, 0x00, 0x00, 0x00, 0x01, 0x00, +0x00, 0x00, 0x00, 0x01, 0x05, 0x00, 0x0A, 0x05, 0x05, 0x80, +0x0F, 0x0F, 0x20, 0x0F, 0x40, 0x10, 0x10, 0x04, 0x64, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x60, 0x28, 0x02, 0x05, 0x01, 0x30, + 0x0A, 0x0F, 0x0F, 0x1E, 0x1E, 0xF6, 0xF6, 0xF2, 0x3E, 0x00, + 0x00, 0x12, 0x0A, 0x00 +}; + +static u8 t62_config_s_ta[] = { PROCG_NOISESUPPRESSION_T62, +0x4F, 0x00, 0x00, 0x16, 0x03, 0x00, 0x00, 0x00, 0x14, 0x00, +0x00, 0x00, 0x00, 0x01, 0x05, 0x00, 0x0A, 0x05, 0x05, 0x80, +0x0F, 0x0F, 0x20, 0x0F, 0x3F, 0x10, 0x10, 0x04, 0x64, 0x00, +0x00, 0x00, 0x00, 0x00, 0x60, 0x28, 0x02, 0x05, 0x01, 0x30, +0x0A, 0x0F, 0x0F, 0x1E, 0x1E, 0xF6, 0xF6, 0xF2, 0x3E, 0x00, +0x00, 0x12, 0x0A, 0x00 +}; + +static u8 end_config_s[] = { RESERVED_T255 }; + +static const u8 *mxt224s_config[] = { + t7_config_s, + t8_config_s, + t9_config_s, + t15_config_s, + t18_config_s, + t19_config_s, + t23_config_s, + t25_config_s, + t40_config_s, + t42_config_s, + t46_config_s, + t47_config_s, + t55_config_s, + t56_config_s, + t57_config_s, + t61_config_s, + t62_config_s, + end_config_s +}; + +static struct mxt224s_platform_data mxt224s_data = { + .max_finger_touches = MXT224S_MAX_MT_FINGERS, + .gpio_read_done = GPIO_TSP_INT, + .min_x = 0, + .max_x = 479, + .min_y = 0, + .max_y = 799, + .min_z = 0, + .max_z = 255, + .min_w = 0, + .max_w = 30, + .config = mxt224s_config, + .config_e = mxt224s_config, + .chrgtime_batt = 0, + .chrgtime_charging = 0, + .atchcalst = 0, + .atchcalsthr = 0, + .tchthr_batt = 0, + .tchthr_charging = 0, + .tchthr_batt_e = 0, + .tchthr_charging_e = 0, + .calcfg_batt_e = 0, + .calcfg_charging_e = 0, + .atchcalsthr_e = 0, + .atchfrccalthr_e = 0, + .atchfrccalratio_e = 0, + .idlesyncsperx_batt = 0, + .idlesyncsperx_charging = 0, + .actvsyncsperx_batt = 0, + .actvsyncsperx_charging = 0, + .idleacqint_batt = 0, + .idleacqint_charging = 0, + .actacqint_batt = 0, + .actacqint_charging = 0, + .xloclip_batt = 0, + .xloclip_charging = 0, + .xhiclip_batt = 0, + .xhiclip_charging = 0, + .yloclip_batt = 0, + .yloclip_charging = 0, + .yhiclip_batt = 0, + .yhiclip_charging = 0, + .xedgectrl_batt = 0, + .xedgectrl_charging = 0, + .xedgedist_batt = 0, + .xedgedist_charging = 0, + .yedgectrl_batt = 0, + .yedgectrl_charging = 0, + .yedgedist_batt = 0, + .yedgedist_charging = 0, + .tchhyst_batt = 0, + .tchhyst_charging = 0, + .t9_config_batt = t9_config_s, + .t9_config_chrg = t9_config_s_ta, + .t56_config_batt = t56_config_s, + .t56_config_chrg = t56_config_s_ta, + .t62_config_batt = t62_config_s, + .t62_config_chrg = t62_config_s_ta, + .power_on = mxt224s_power_on, + .power_off = mxt224s_power_off, + .register_cb = tsp_register_callback, + .read_ta_status = tsp_read_ta_status, + .config_fw_version = "W899_At_0720", +}; + +/* I2C3 */ +static struct i2c_board_info i2c_devs3[] __initdata = { + { + I2C_BOARD_INFO(MXT_DEV_NAME, 0x4b), + .platform_data = &mxt224s_data}, +}; + + +void __init midas_tsp_init(void) +{ +#ifndef CONFIG_MACH_NEWTON_BD + int gpio; + int ret; + printk(KERN_INFO "[TSP] midas_tsp_init() is called\n"); + + /* TSP_INT: XEINT_4 */ + gpio = GPIO_TSP_INT; + ret = gpio_request(gpio, "TSP_INT"); + if (ret) + pr_err("failed to request gpio(TSP_INT)\n"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + /* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */ + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + s5p_register_gpio_interrupt(gpio); + i2c_devs3[0].irq = gpio_to_irq(gpio); + + printk(KERN_INFO "%s touch : %d\n", __func__, i2c_devs3[0].irq); +#endif + + s3c_gpio_cfgpin(GPIO_TSP_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_EN, S3C_GPIO_PULL_NONE); + + i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); +} + + diff --git a/arch/arm/mach-exynos/board-grande.c b/arch/arm/mach-exynos/board-grande.c new file mode 100755 index 0000000..79c0fa8 --- /dev/null +++ b/arch/arm/mach-exynos/board-grande.c @@ -0,0 +1,2095 @@ +/* linux/arch/arm/mach-exynos/mach-smdk4212.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> +#include <linux/serial_core.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/clk.h> +#include <linux/gpio.h> +#include <linux/gpio_keys.h> +#include <linux/gpio_event.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/pwm_backlight.h> +#include <linux/input.h> +#include <linux/mmc/host.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/max8649.h> +#include <linux/regulator/fixed.h> +#ifdef CONFIG_MFD_MAX77693 +#include <linux/mfd/max77693.h> +#include <linux/mfd/max77693-private.h> +#include <linux/leds-max77693.h> +#endif + +#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE +#include <linux/battery/max17047_fuelgauge.h> +#endif +#if defined(CONFIG_BATTERY_SAMSUNG) +#include <linux/power_supply.h> +#include <linux/battery/samsung_battery.h> +#endif + +#ifdef CONFIG_STMPE811_ADC +#include <linux/stmpe811-adc.h> +#endif +#include <linux/v4l2-mediabus.h> +#include <linux/memblock.h> +#include <linux/delay.h> +#include <linux/bootmem.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <plat/regs-serial.h> +#include <plat/exynos4.h> +#include <plat/cpu.h> +#include <plat/clock.h> +#include <plat/keypad.h> +#include <plat/devs.h> +#include <plat/fb-s5p.h> +#include <plat/fb-core.h> +#include <plat/regs-fb-v4.h> +#include <plat/backlight.h> +#include <plat/gpio-cfg.h> +#include <plat/iic.h> +#include <plat/pd.h> +#include <plat/sdhci.h> +#include <plat/mshci.h> +#include <plat/ehci.h> +#include <plat/usbgadget.h> +#include <plat/s3c64xx-spi.h> +#include <plat/tvout.h> +#include <plat/csis.h> +#include <plat/media.h> +#include <plat/adc.h> +#include <media/exynos_fimc_is.h> +#include <mach/exynos-ion.h> + +#include <mach/map.h> +#include <mach/spi-clocks.h> + +#include <mach/dev.h> +#include <mach/ppmu.h> + +#ifdef CONFIG_EXYNOS4_SETUP_THERMAL +#include <plat/s5p-tmu.h> +#include <mach/regs-tmu.h> +#endif + +#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X) +#include <plat/s5p-mfc.h> +#endif + +#include <plat/fb-s5p.h> + +#ifdef CONFIG_FB_S5P_EXTDSP +struct s3cfb_extdsp_lcd { + int width; + int height; + int bpp; +}; +#endif +#include <mach/dev-sysmmu.h> + +#ifdef CONFIG_VIDEO_JPEG_V2X +#include <plat/jpeg.h> +#endif + +#include <plat/fimg2d.h> +#include <plat/s5p-sysmmu.h> + +#include <mach/sec_debug.h> + +#include <mach/gpio-midas.h> + +#include <mach/grande-power.h> + +#ifdef CONFIG_SEC_THERMISTOR +#include <mach/sec_thermistor.h> +#endif +#include <mach/midas-thermistor.h> +#include <mach/midas-tsp.h> +#include <mach/regs-clock.h> + +#include <mach/midas-lcd.h> +#include <mach/midas-sound.h> +#if defined(CONFIG_SEC_DEV_JACK) +#include <mach/grande-jack.h> +#endif + +#ifdef CONFIG_USB_HOST_NOTIFY +#include <linux/host_notify.h> +#endif + +#if defined(CONFIG_PHONE_IPC_SPI) +#include <linux/phone_svn/ipc_spi.h> +#include <linux/irq.h> +#endif +#include <linux/irq.h> +#include "board-mobile.h" + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +#define SMDK4212_UFCON_GPS (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG8 | \ + S5PV210_UFCON_RXTRIG32) + +static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_GPS, + .set_runstate = set_gps_uart_op, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = SMDK4212_UCON_DEFAULT, + .ulcon = SMDK4212_ULCON_DEFAULT, + .ufcon = SMDK4212_UFCON_DEFAULT, + }, +}; + +#if defined(CONFIG_S3C64XX_DEV_SPI) +#if defined(CONFIG_VIDEO_S5C73M3_SPI) + +static struct s3c64xx_spi_csinfo spi1_csi[] = { + [0] = { + .line = EXYNOS4_GPB(5), + .set_level = gpio_set_value, + .fb_delay = 0x00, + }, +}; + +static struct spi_board_info spi1_board_info[] __initdata = { + { + .modalias = "s5c73m3_spi", + .platform_data = NULL, + .max_speed_hz = 50000000, + .bus_num = 1, + .chip_select = 0, + .mode = SPI_MODE_0, + .controller_data = &spi1_csi[0], + } +}; +#endif +#endif + +static struct i2c_board_info i2c_devs8_emul[]; + +#if defined(CONFIG_KEYPAD_MELFAS_TOUCH) +static void touchkey_init_hw(void) +{ + gpio_request(GPIO_3_TOUCH_INT, "3_TOUCH_INT"); + s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE); + s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT); + gpio_direction_input(GPIO_3_TOUCH_INT); + + i2c_devs8_emul[0].irq = gpio_to_irq(GPIO_3_TOUCH_INT); + irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), IRQF_TRIGGER_FALLING); + s3c_gpio_cfgpin(GPIO_3_TOUCH_INT, S3C_GPIO_SFN(0xf)); + + s3c_gpio_setpull(GPIO_3_TOUCH_SCL, S3C_GPIO_PULL_DOWN); + s3c_gpio_setpull(GPIO_3_TOUCH_SDA, S3C_GPIO_PULL_DOWN); + +} +#endif /*CONFIG_KEYPAD_MELFAS_TOUCH*/ + +#if defined(CONFIG_INPUT_FLIP) +static void flip_init_hw(void) +{ + int ret; + + s3c_gpio_cfgpin(GPIO_LCD_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_LCD_SEL, S3C_GPIO_PULL_NONE); + + ret = gpio_request(GPIO_HALL_SW, "HALL_SW"); + if (ret) + pr_err("failed to request gpio(HALL_SW)\n"); + s3c_gpio_cfgpin(GPIO_HALL_SW, S3C_GPIO_SFN(0xf)); + /* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */ + s3c_gpio_setpull(GPIO_HALL_SW, S3C_GPIO_PULL_NONE); + s5p_register_gpio_interrupt(GPIO_HALL_SW); + + s3c_gpio_cfgpin(GPIO_LCD_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_LCD_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_TSP_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SEL, S3C_GPIO_PULL_NONE); + +} +#endif + + +static DEFINE_MUTEX(notify_lock); + +#define DEFINE_MMC_CARD_NOTIFIER(num) \ +static void (*hsmmc##num##_notify_func)(struct platform_device *, int state); \ +static int ext_cd_init_hsmmc##num(void (*notify_func)( \ + struct platform_device *, int state)) \ +{ \ + mutex_lock(¬ify_lock); \ + WARN_ON(hsmmc##num##_notify_func); \ + hsmmc##num##_notify_func = notify_func; \ + mutex_unlock(¬ify_lock); \ + return 0; \ +} \ +static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \ + struct platform_device *, int state)) \ +{ \ + mutex_lock(¬ify_lock); \ + WARN_ON(hsmmc##num##_notify_func != notify_func); \ + hsmmc##num##_notify_func = NULL; \ + mutex_unlock(¬ify_lock); \ + return 0; \ +} + +#ifdef CONFIG_S3C_DEV_HSMMC3 + DEFINE_MMC_CARD_NOTIFIER(3) +#endif + +/* + * call this when you need sd stack to recognize insertion or removal of card + * that can't be told by SDHCI regs + */ +void mmc_force_presence_change(struct platform_device *pdev) +{ + void (*notify_func)(struct platform_device *, int state) = NULL; + mutex_lock(¬ify_lock); +#ifdef CONFIG_S3C_DEV_HSMMC3 + if (pdev == &s3c_device_hsmmc3) + notify_func = hsmmc3_notify_func; +#endif + + if (notify_func) + notify_func(pdev, 1); + else + pr_warn("%s: called for device with no notifier\n", __func__); + mutex_unlock(¬ify_lock); +} +EXPORT_SYMBOL_GPL(mmc_force_presence_change); + +#ifdef CONFIG_S3C_DEV_HSMMC +static struct s3c_sdhci_platdata smdk4212_hsmmc0_pdata __initdata = { + .cd_type = S3C_MSHCI_CD_PERMANENT, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC1 +static struct s3c_sdhci_platdata smdk4212_hsmmc1_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC2 +static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_GPIO, +#if defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) + .ext_cd_gpio = EXYNOS4_GPX0(4), +#else + .ext_cd_gpio = EXYNOS4_GPX3(4), +#endif + .ext_cd_gpio_invert = true, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, + .vmmc_name = "vtf_2.8v" +#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA, +#endif +}; +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC3 +static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = { +/* new code for brm4334 */ + .cd_type = S3C_SDHCI_CD_EXTERNAL, + + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, + .pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME, + .ext_cd_init = ext_cd_init_hsmmc3, + .ext_cd_cleanup = ext_cd_cleanup_hsmmc3, +}; +#endif + +#ifdef CONFIG_EXYNOS4_DEV_MSHC +static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = { + .cd_type = S3C_MSHCI_CD_PERMANENT, + .fifo_depth = 0x80, +#if defined(CONFIG_EXYNOS4_MSHC_8BIT) && \ + defined(CONFIG_EXYNOS4_MSHC_DDR) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR | + MMC_CAP_UHS_DDR50 | MMC_CAP_CMD23, + .host_caps2 = MMC_CAP2_PACKED_CMD, +#elif defined(CONFIG_EXYNOS4_MSHC_8BIT) + .max_width = 8, + .host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, +#elif defined(CONFIG_EXYNOS4_MSHC_DDR) + .host_caps = MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50 | + MMC_CAP_CMD23, +#endif + .int_power_gpio = GPIO_eMMC_EN, +}; +#endif + +#ifdef CONFIG_USB_EHCI_S5P +static struct s5p_ehci_platdata smdk4212_ehci_pdata; + +static void __init smdk4212_ehci_init(void) +{ + struct s5p_ehci_platdata *pdata = &smdk4212_ehci_pdata; + + s5p_ehci_set_platdata(pdata); +} +#endif + +#ifdef CONFIG_USB_OHCI_S5P +static struct s5p_ohci_platdata smdk4212_ohci_pdata; + +static void __init smdk4212_ohci_init(void) +{ + struct s5p_ohci_platdata *pdata = &smdk4212_ohci_pdata; + + s5p_ohci_set_platdata(pdata); +} +#endif + +/* USB GADGET */ +#ifdef CONFIG_USB_GADGET +static struct s5p_usbgadget_platdata smdk4212_usbgadget_pdata; + +#include <linux/usb/android_composite.h> +static void __init smdk4212_usbgadget_init(void) +{ + struct s5p_usbgadget_platdata *pdata = &smdk4212_usbgadget_pdata; + struct android_usb_platform_data *android_pdata = + s3c_device_android_usb.dev.platform_data; + if (android_pdata) { +#if defined(CONFIG_USB_CDFS_SUPPORT) + unsigned int newluns = 1; +#else + unsigned int newluns = 2; +#endif + printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n", + __func__, android_pdata->nluns, newluns); + android_pdata->nluns = newluns; + } else { + printk(KERN_DEBUG "usb: %s android_pdata is not available\n", + __func__); + } + + s5p_usbgadget_set_platdata(pdata); +} +#endif + +#ifdef CONFIG_MFD_MAX77693 +#ifdef CONFIG_VIBETONZ +static struct max77693_haptic_platform_data max77693_haptic_pdata = { + .max_timeout = 10000, + .duty = 37050, + .period = 38054, + .reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128, + .init_hw = NULL, + .motor_en = NULL, + .pwm_id = 0, + .regulator_name = "vmotor", +}; +#endif + +#ifdef CONFIG_LEDS_MAX77693 +static struct max77693_led_platform_data max77693_led_pdata = { + .num_leds = 4, + + .leds[0].name = "leds-sec1", + .leds[0].id = MAX77693_FLASH_LED_1, + .leds[0].timer = MAX77693_FLASH_TIME_500MS, + .leds[0].timer_mode = MAX77693_TIMER_MODE_MAX_TIMER, + .leds[0].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB, + .leds[0].brightness = 0x1F, + + .leds[1].name = "leds-sec2", + .leds[1].id = MAX77693_FLASH_LED_2, + .leds[1].timer = MAX77693_FLASH_TIME_500MS, + .leds[1].timer_mode = MAX77693_TIMER_MODE_MAX_TIMER, + .leds[1].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB, + .leds[1].brightness = 0x1F, + + .leds[2].name = "torch-sec1", + .leds[2].id = MAX77693_TORCH_LED_1, + .leds[2].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB, + .leds[2].brightness = 0x0F, + + .leds[3].name = "torch-sec2", + .leds[3].id = MAX77693_TORCH_LED_2, + .leds[3].cntrl_mode = MAX77693_LED_CTRL_BY_I2C, + .leds[3].brightness = 0x0F, +}; + +#endif + +#ifdef CONFIG_BATTERY_MAX77693_CHARGER +static struct max77693_charger_platform_data max77693_charger_pdata = { +#ifdef CONFIG_BATTERY_WPC_CHARGER + .wpc_irq_gpio = GPIO_WPC_INT, +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_GRANDE) \ + || defined(CONFIG_MACH_IRON) + .vbus_irq_gpio = GPIO_V_BUS_INT, +#endif + .wc_pwr_det = false, +#endif +}; +#endif + +extern struct max77693_muic_data max77693_muic; +extern struct max77693_regulator_data max77693_regulators; + +static bool is_muic_default_uart_path_cp(void) +{ + return false; +} + +struct max77693_platform_data exynos4_max77693_info = { + .irq_base = IRQ_BOARD_IFIC_START, + .irq_gpio = GPIO_IF_PMIC_IRQ, + .wakeup = 1, + .muic = &max77693_muic, + .is_default_uart_path_cp = is_muic_default_uart_path_cp, + .regulators = &max77693_regulators, + .num_regulators = MAX77693_REG_MAX, +#ifdef CONFIG_VIBETONZ + .haptic_data = &max77693_haptic_pdata, +#endif +#ifdef CONFIG_LEDS_MAX77693 + .led_data = &max77693_led_pdata, +#endif +#ifdef CONFIG_BATTERY_MAX77693_CHARGER + .charger_data = &max77693_charger_pdata, +#endif +}; +#endif + +/* I2C0 */ +static struct i2c_board_info i2c_devs0[] __initdata = { +}; + +/* I2C1 */ +static struct i2c_board_info i2c_devs1[] __initdata = { +}; + +#ifdef CONFIG_S3C_DEV_I2C4 +#ifdef CONFIG_MFD_MAX77693 +static struct i2c_board_info i2c_devs4_max77693[] __initdata = { + { + I2C_BOARD_INFO("max77693", (0xCC >> 1)), + .platform_data = &exynos4_max77693_info, + } +}; +#endif +#endif + +#ifdef CONFIG_S3C_DEV_I2C5 +static struct i2c_board_info i2c_devs5[] __initdata = { +#if defined(CONFIG_REGULATOR_MAX77686) + /* max77686 on i2c5 other than M1 board */ + { + I2C_BOARD_INFO("max77686", (0x12 >> 1)), + .platform_data = &exynos4_max77686_info, + }, +#endif +}; + +struct s3c2410_platform_i2c default_i2c5_data __initdata = { + .bus_num = 5, + .flags = 0, + .slave_addr = 0x10, + .frequency = 100*1000, + .sda_delay = 100, +}; + +#endif + +static struct i2c_board_info i2c_devs7[] __initdata = { +#if defined(CONFIG_REGULATOR_MAX77686) /* max77686 on i2c7 with M1 board */ + { + I2C_BOARD_INFO("max77686", (0x12 >> 1)), + .platform_data = &exynos4_max77686_info, + }, +#endif +}; + +/* Bluetooth */ +#ifdef CONFIG_BT_BCM4334 +static struct platform_device bcm4334_bluetooth_device = { + .name = "bcm4334_bluetooth", + .id = -1, +}; +#endif + + +static struct i2c_gpio_platform_data gpio_i2c_data8 = { + .sda_pin = GPIO_3_TOUCH_SDA, + .scl_pin = GPIO_3_TOUCH_SCL, +}; + +struct platform_device s3c_device_i2c8 = { + .name = "i2c-gpio", + .id = 8, + .dev.platform_data = &gpio_i2c_data8, +}; + + +/* I2C8 */ +static struct i2c_board_info i2c_devs8_emul[] = { +#ifdef CONFIG_KEYPAD_MELFAS_TOUCH + { + I2C_BOARD_INFO("melfas-touchkey", 0x20), + }, +#endif +}; + +/* I2C9 */ +static struct i2c_board_info i2c_devs9_emul[] __initdata = { +}; + +/* I2C10 */ +static struct i2c_board_info i2c_devs10_emul[] __initdata = { +}; + +/* I2C11 */ +static struct i2c_board_info i2c_devs11_emul[] __initdata = { +}; + +/* I2C12 */ +#if defined(CONFIG_PN65N_NFC) +static struct i2c_board_info i2c_devs12_emul[] __initdata = { +}; +#endif + +#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE +static struct i2c_gpio_platform_data gpio_i2c_data14 = { + .sda_pin = GPIO_FUEL_SDA, + .scl_pin = GPIO_FUEL_SCL, +}; + +struct platform_device s3c_device_i2c14 = { + .name = "i2c-gpio", + .id = 14, + .dev.platform_data = &gpio_i2c_data14, +}; + +static struct max17047_platform_data max17047_pdata = { + .irq_gpio = GPIO_FUEL_ALERT, +}; + +/* I2C14 */ +static struct i2c_board_info i2c_devs14_emul[] __initdata = { + { + I2C_BOARD_INFO("max17047-fuelgauge", 0x36), + .platform_data = &max17047_pdata, + }, +}; +#endif + +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_GRANDE) \ + || defined(CONFIG_MACH_IRON) +static struct i2c_gpio_platform_data gpio_i2c_data17 = { + .sda_pin = GPIO_IF_PMIC_SDA, + .scl_pin = GPIO_IF_PMIC_SCL, +}; + +struct platform_device s3c_device_i2c17 = { + .name = "i2c-gpio", + .id = 17, + .dev.platform_data = &gpio_i2c_data17, +}; + +/* I2C17 */ +static struct i2c_board_info i2c_devs17_emul[] __initdata = { +#ifdef CONFIG_MFD_MAX77693 + { + I2C_BOARD_INFO("max77693", (0xCC >> 1)), + .platform_data = &exynos4_max77693_info, + } +#endif +}; +#endif + +#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \ + || defined(CONFIG_FM_SI4705_MODULE) +static struct i2c_gpio_platform_data gpio_i2c_data19 = { + .sda_pin = GPIO_ADC_SDA, + .scl_pin = GPIO_ADC_SCL, +}; + +struct platform_device s3c_device_i2c19 = { + .name = "i2c-gpio", + .id = 19, + .dev.platform_data = &gpio_i2c_data19, +}; + + +/* I2C19 */ +static struct i2c_board_info i2c_devs19_emul[] __initdata = { +#if defined(CONFIG_STMPE811_ADC) + { + I2C_BOARD_INFO("stmpe811-adc", (0x82 >> 1)), + .platform_data = &stmpe811_pdata, + }, +#endif +#ifdef CONFIG_FM_SI4705_MODULE + { + I2C_BOARD_INFO("Si4709", (0x22 >> 1)), + }, +#endif +#ifdef CONFIG_FM_SI4709_MODULE + { + I2C_BOARD_INFO("Si4709", (0x20 >> 1)), + }, +#endif + +}; +#endif + +#ifdef CONFIG_REGULATOR_LP8720 +#ifdef GPIO_FOLDER_PMIC_EN +static struct i2c_gpio_platform_data gpio_i2c_data22 = { + .scl_pin = GPIO_FOLDER_PMIC_SCL, + .sda_pin = GPIO_FOLDER_PMIC_SDA, +}; + +struct platform_device s3c_device_i2c22 = { + .name = "i2c-gpio", + .id = 22, + .dev.platform_data = &gpio_i2c_data22, +}; + +static struct i2c_board_info i2c_devs22_emul[] __initdata = { + { + I2C_BOARD_INFO("lp8720", 0xFA>>1), + .platform_data = &folder_pmic_info, + }, +}; +#endif /* GPIO_FOLDER_PMIC_EN */ + +#ifdef GPIO_SUB_PMIC_EN +static struct i2c_gpio_platform_data gpio_i2c_data23 = { + .scl_pin = GPIO_SUB_PMIC_SCL, + .sda_pin = GPIO_SUB_PMIC_SDA, +}; + +struct platform_device s3c_device_i2c23 = { + .name = "i2c-gpio", + .id = 23, + .dev.platform_data = &gpio_i2c_data23, +}; + +static struct i2c_board_info i2c_devs23_emul[] __initdata = { + { + I2C_BOARD_INFO("lp8720", 0xFA>>1), + .platform_data = &sub_pmic_info, + }, +#if defined(CONFIG_REGULATOR_MAX8952_GRANDE) + { + /* MAX8952(MODE3) for Grande */ + I2C_BOARD_INFO("max8952_grande", 0xC0>>1), + }, +#endif +}; +#endif /* GPIO_SUB_PMIC_EN */ +#endif /* CONFIG_REGULATOR_LP8720 */ + +#ifdef CONFIG_ANDROID_RAM_CONSOLE +static struct resource ram_console_resource[] = { + { + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ram_console_device = { + .name = "ram_console", + .id = -1, + .num_resources = ARRAY_SIZE(ram_console_resource), + .resource = ram_console_resource, +}; + +static int __init setup_ram_console_mem(char *str) +{ + unsigned size = memparse(str, &str); + + if (size && (*str == '@')) { + unsigned long long base = 0; + + base = simple_strtoul(++str, &str, 0); + if (reserve_bootmem(base, size, BOOTMEM_EXCLUSIVE)) { + pr_err("%s: failed reserving size %d " + "at base 0x%llx\n", __func__, size, base); + return -1; + } + + ram_console_resource[0].start = base; + ram_console_resource[0].end = base + size - 1; + pr_err("%s: %x at %llx\n", __func__, size, base); + } + return 0; +} + +__setup("ram_console=", setup_ram_console_mem); +#endif + +#if defined(CONFIG_BATTERY_SAMSUNG) +static struct samsung_battery_platform_data samsung_battery_pdata = { + .charger_name = "max77693-charger", + .fuelgauge_name = "max17047-fuelgauge", + + .voltage_max = 4350000, + .voltage_min = 3400000, + .in_curr_limit = 1000, + + .chg_curr_ta = 1000, + .chg_curr_usb = 475, + .chg_curr_cdp = 1000, + .chg_curr_wpc = 475, + .chg_curr_dock = 1000, + .chg_curr_etc = 475, + + .chng_interval = 30, + .chng_susp_interval = 60, + .norm_interval = 120, + .norm_susp_interval = 7200, + .emer_lv1_interval = 30, + .emer_lv2_interval = 10, + + .recharge_voltage = 4300000, /* it will be cacaluated in probe */ + + .abstimer_charge_duration = 6 * 60 * 60, + .abstimer_recharge_duration = 2 * 60 * 60, + + .cb_det_src = CABLE_DET_CHARGER, + +#if defined(CONFIG_MACH_M0_CTC) + .overheat_stop_temp = 640, + .overheat_recovery_temp = 430, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 30, +#else + .overheat_stop_temp = 600, + .overheat_recovery_temp = 400, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#endif + + .temper_src = TEMPER_AP_ADC, + .temper_ch = 2, +#ifdef CONFIG_S3C_ADC + /* s3c adc driver does not convert raw adc data. + * so, register convert function. + */ + .covert_adc = convert_adc, +#endif + + .vf_det_src = VF_DET_CHARGER, + .vf_det_ch = 0, /* if src == VF_DET_ADC */ + .vf_det_th_l = 500, + .vf_det_th_h = 1500, + + .suspend_chging = true, + + .led_indicator = false, + + .battery_standever = false, +}; + +static struct platform_device samsung_device_battery = { + .name = "samsung-battery", + .id = -1, + .dev.platform_data = &samsung_battery_pdata, +}; +#endif + +#define GPIO_KEYS(_code, _gpio, _active_low, _iswake, _hook) \ + { \ + .code = _code, \ + .gpio = _gpio, \ + .active_low = _active_low, \ + .type = EV_KEY, \ + .wakeup = _iswake, \ + .debounce_interval = 10, \ + .isr_hook = _hook, \ + .value = 1 \ + } + +struct gpio_keys_button midas_buttons[] = { + GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP, + 1, 0, sec_debug_check_crash_key), + GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN, + 1, 0, sec_debug_check_crash_key), + GPIO_KEYS(KEY_END, GPIO_nPOWER, + 1, 1, sec_debug_check_crash_key), + GPIO_KEYS(KEY_POWER, GPIO_HOLD, + 1, 1, sec_debug_check_crash_key), +#if !defined(CONFIG_MACH_IRON) + GPIO_KEYS(KEY_3G, GPIO_3G_DET, + 1, 1, sec_debug_check_crash_key), +#endif +}; + +struct gpio_keys_platform_data midas_gpiokeys_platform_data = { + midas_buttons, + ARRAY_SIZE(midas_buttons), +}; + +static struct platform_device midas_keypad = { + .name = "gpio-keys", + .dev = { + .platform_data = &midas_gpiokeys_platform_data, + }, +}; + +#if defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) +static uint32_t smdk4x12_keymap[] __initdata = { +/* KEY(row, col, keycode) */ + KEY(2, 3, KEY_SEND), KEY(8, 3, KEY_BACKSPACE), KEY(12, 3, KEY_HOME), KEY(4, 3, KEY_NETWORK), KEY(11, 3, KEY_ENTER), + KEY(2, 4, KEY_1), KEY(8, 4, KEY_2), KEY(12, 4, KEY_3), KEY(11, 4, KEY_DOWN), + KEY(2, 5, KEY_4), KEY(8, 5, KEY_5), KEY(12, 5, KEY_6), KEY(4, 5, KEY_BACK), + KEY(2, 6, KEY_7), KEY(8, 6, KEY_8), KEY(12, 6, KEY_9), KEY(4, 6, KEY_UP), + KEY(2, 7, KEY_STAR), KEY(8, 7, KEY_0), KEY(12, 7, KEY_POUND), KEY(4, 7, KEY_MENU), + #if defined(CONFIG_MACH_IRON) + KEY(4, 4, KEY_LEFT), KEY(11, 5, KEY_RIGHT), + #else + KEY(4, 4, KEY_RIGHT), KEY(11, 5, KEY_LEFT), + #endif +}; + +static struct matrix_keymap_data smdk4x12_keymap_data __initdata = { + .keymap = smdk4x12_keymap, + .keymap_size = ARRAY_SIZE(smdk4x12_keymap), +}; + +static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = { + .keymap_data = &smdk4x12_keymap_data, + .rows = 14, + .cols = 8, +}; +#endif + +#if defined(CONFIG_INPUT_FLIP) +struct sec_flip_pdata { + int wakeup; +}; + +static struct sec_flip_pdata sec_flip_dev_data = { + .wakeup = 1, +}; + +static struct platform_device sec_flip_device = { + .name = "sec_flip", + .id = -1, + .dev = { + .platform_data = &sec_flip_dev_data, + } +}; +#endif + + +#ifdef CONFIG_VIDEO_FIMG2D +static struct fimg2d_platdata fimg2d_data __initdata = { + .hw_ver = 0x41, + .parent_clkname = "mout_g2d0", + .clkname = "sclk_fimg2d", + .gate_clkname = "fimg2d", + .clkrate = 199 * 1000000, /* 160 Mhz */ +}; +#endif + +/* BUSFREQ to control memory/bus */ +static struct device_domain busfreq; + +static struct platform_device exynos4_busfreq = { + .id = -1, + .name = "exynos-busfreq", +}; + +static struct i2c_gpio_platform_data i2c9_platdata = { +#if defined(CONFIG_SENSORS_CM3663) + .sda_pin = GPIO_PS_ALS_SDA_18V, + .scl_pin = GPIO_PS_ALS_SCL_18V, +#elif defined(CONFIG_SENSORS_BH1721) + .sda_pin = GPIO_PS_ALS_SDA_28V, + .scl_pin = GPIO_PS_ALS_SCL_28V, +#elif defined(CONFIG_SENSORS_CM36651) + .sda_pin = GPIO_RGB_SDA_1_8V, + .scl_pin = GPIO_RGB_SCL_1_8V, +#elif defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) + .sda_pin = GPIO_PS_ALS_SDA_28V, + .scl_pin = GPIO_PS_ALS_SCL_28V, +#endif + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c9 = { + .name = "i2c-gpio", + .id = 9, + .dev.platform_data = &i2c9_platdata, +}; + +#ifdef CONFIG_SENSORS_AK8975C +static struct i2c_gpio_platform_data i2c10_platdata = { + .sda_pin = GPIO_MSENSOR_SDA_18V, + .scl_pin = GPIO_MSENSOR_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c10 = { + .name = "i2c-gpio", + .id = 10, + .dev.platform_data = &i2c10_platdata, +}; +#endif + +#ifdef CONFIG_SENSORS_AK8963C +static struct i2c_gpio_platform_data i2c10_platdata = { + .sda_pin = GPIO_MSENSOR_SDA_18V, + .scl_pin = GPIO_MSENSOR_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c10 = { + .name = "i2c-gpio", + .id = 10, + .dev.platform_data = &i2c10_platdata, +}; +#endif + +#ifdef CONFIG_SENSORS_LPS331 +static struct i2c_gpio_platform_data i2c11_platdata = { + .sda_pin = GPIO_BSENSE_SDA_18V, + .scl_pin = GPIO_BENSE_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c11 = { + .name = "i2c-gpio", + .id = 11, + .dev.platform_data = &i2c11_platdata, +}; +#endif + +#if defined(CONFIG_PN65N_NFC) +static struct i2c_gpio_platform_data i2c12_platdata = { + .sda_pin = GPIO_NFC_SDA_18V, + .scl_pin = GPIO_NFC_SCL_18V, + .udelay = 2, /* 250 kHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c12 = { + .name = "i2c-gpio", + .id = 12, + .dev.platform_data = &i2c12_platdata, +}; +#endif + +#ifdef CONFIG_USB_HOST_NOTIFY +static void otg_accessory_power(int enable) +{ + u8 on = (u8)!!enable; + + /* max77693 otg power control */ + otg_control(enable); + + gpio_request(GPIO_OTG_EN, "USB_OTG_EN"); + gpio_direction_output(GPIO_OTG_EN, on); + gpio_free(GPIO_OTG_EN); + pr_info("%s: otg accessory power = %d\n", __func__, on); +} + +static void otg_accessory_powered_booster(int enable) +{ + u8 on = (u8)!!enable; + + /* max77693 powered otg power control */ + powered_otg_control(enable); + pr_info("%s: otg accessory power = %d\n", __func__, on); +} + +static struct host_notifier_platform_data host_notifier_pdata = { + .ndev.name = "usb_otg", + .booster = otg_accessory_power, + .powered_booster = otg_accessory_powered_booster, + .thread_enable = 0, +}; + +struct platform_device host_notifier_device = { + .name = "host_notifier", + .dev.platform_data = &host_notifier_pdata, +}; +#endif + +#ifdef CONFIG_SEC_WATCHDOG_RESET +static struct platform_device watchdog_reset_device = { + .name = "watchdog-reset", + .id = -1, +}; +#endif + +static struct platform_device *midas_devices[] __initdata = { +#ifdef CONFIG_SEC_WATCHDOG_RESET + &watchdog_reset_device, +#endif +#ifdef CONFIG_ANDROID_RAM_CONSOLE + &ram_console_device, +#endif + /* Samsung Power Domain */ + &exynos4_device_pd[PD_MFC], + &exynos4_device_pd[PD_G3D], + &exynos4_device_pd[PD_LCD0], + &exynos4_device_pd[PD_CAM], + &exynos4_device_pd[PD_TV], + &exynos4_device_pd[PD_GPS], +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS + &exynos4_device_pd[PD_ISP], +#endif + &exynos4_device_pd[PD_GPS_ALIVE], + /* legacy fimd */ +#ifdef CONFIG_FB_S5P + &s3c_device_fb, +#ifdef CONFIG_FB_S5P_LMS501KF03 + &s3c_device_spi_gpio, +#endif +#endif + +#ifdef CONFIG_FB_S5P_MDNIE + &mdnie_device, +#endif + +#ifdef CONFIG_HAVE_PWM + &s3c_device_timer[0], + &s3c_device_timer[1], + &s3c_device_timer[2], + &s3c_device_timer[3], +#endif + +#ifdef CONFIG_SND_SOC_WM8994 + &vbatt_device, +#endif + + &s3c_device_wdt, + &s3c_device_rtc, + + &s3c_device_i2c0, + &s3c_device_i2c1, + &s3c_device_i2c3, +#ifdef CONFIG_S3C_DEV_I2C4 + &s3c_device_i2c4, +#endif + /* &s3c_device_i2c5, */ + +#ifdef CONFIG_AUDIENCE_ES305 + &s3c_device_i2c6, +#endif + &s3c_device_i2c7, +#if defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) + &s3c_device_i2c8, +#endif + &s3c_device_i2c9, +#ifdef CONFIG_SENSORS_AK8975C + &s3c_device_i2c10, +#endif +#ifdef CONFIG_SENSORS_AK8963C + &s3c_device_i2c10, +#endif + +#ifdef CONFIG_SENSORS_LPS331 + &s3c_device_i2c11, +#endif + /* &s3c_device_i2c12, */ +#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE + &s3c_device_i2c14, /* max17047-fuelgauge */ +#endif + +#ifdef CONFIG_SAMSUNG_MHL + &s3c_device_i2c15, + &s3c_device_i2c16, +#endif +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_GRANDE) \ + || defined(CONFIG_MACH_IRON) + &s3c_device_i2c17, +#if 0 + &s3c_device_i2c18, +#endif +#endif +#ifdef CONFIG_LEDS_AN30259A + &s3c_device_i2c21, +#endif +#ifdef CONFIG_REGULATOR_LP8720 +#ifdef GPIO_FOLDER_PMIC_EN + &s3c_device_i2c22, +#endif /* GPIO_FOLDER_PMIC_EN */ +#ifdef GPIO_SUB_PMIC_EN + &s3c_device_i2c23, +#endif /* GPIO_SUB_PMIC_EN */ +#endif +#if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC + &s5p_device_ehci, +#endif +#if defined CONFIG_USB_OHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC + &s5p_device_ohci, +#endif +#ifdef CONFIG_USB_GADGET + &s3c_device_usbgadget, +#endif +#ifdef CONFIG_USB_ANDROID_RNDIS + &s3c_device_rndis, +#endif +#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID) + &s3c_device_android_usb, + &s3c_device_usb_mass_storage, +#endif +#ifdef CONFIG_EXYNOS4_DEV_MSHC + &s3c_device_mshci, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC + &s3c_device_hsmmc0, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + &s3c_device_hsmmc1, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + &s3c_device_hsmmc2, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + &s3c_device_hsmmc3, +#endif + +#ifdef CONFIG_SND_SAMSUNG_AC97 + &exynos_device_ac97, +#endif +#ifdef CONFIG_SND_SAMSUNG_I2S + &exynos_device_i2s0, +#endif +#ifdef CONFIG_SND_SAMSUNG_PCM + &exynos_device_pcm0, +#endif +#ifdef CONFIG_SND_SAMSUNG_SPDIF + &exynos_device_spdif, +#endif +#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP) + &exynos_device_srp, +#endif +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS + &exynos4_device_fimc_is, +#endif +#ifdef CONFIG_FB_S5P_LD9040 + &ld9040_spi_gpio, +#endif +#ifdef CONFIG_VIDEO_TVOUT + &s5p_device_tvout, + &s5p_device_cec, + &s5p_device_hpd, +#endif +#ifdef CONFIG_FB_S5P_EXTDSP + &s3c_device_extdsp, +#endif +#ifdef CONFIG_VIDEO_FIMC + &s3c_device_fimc0, + &s3c_device_fimc1, + &s3c_device_fimc2, + &s3c_device_fimc3, +/* CONFIG_VIDEO_SAMSUNG_S5P_FIMC is the feature for mainline */ +#elif defined(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc3, +#endif +#if defined(CONFIG_VIDEO_FIMC_MIPI) + &s3c_device_csis0, + &s3c_device_csis1, +#endif +#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) + &s5p_device_mfc, +#endif +#ifdef CONFIG_S5P_SYSTEM_MMU + &SYSMMU_PLATDEV(g2d_acp), + &SYSMMU_PLATDEV(fimc0), + &SYSMMU_PLATDEV(fimc1), + &SYSMMU_PLATDEV(fimc2), + &SYSMMU_PLATDEV(fimc3), + &SYSMMU_PLATDEV(jpeg), + &SYSMMU_PLATDEV(mfc_l), + &SYSMMU_PLATDEV(mfc_r), + &SYSMMU_PLATDEV(tv), +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS + &SYSMMU_PLATDEV(is_isp), + &SYSMMU_PLATDEV(is_drc), + &SYSMMU_PLATDEV(is_fd), + &SYSMMU_PLATDEV(is_cpu), +#endif +#endif +#ifdef CONFIG_ION_EXYNOS + &exynos_device_ion, +#endif +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE + &exynos_device_flite0, + &exynos_device_flite1, +#endif +#ifdef CONFIG_VIDEO_FIMG2D + &s5p_device_fimg2d, +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2X + &s5p_device_jpeg, +#endif + &samsung_asoc_dma, +#ifndef CONFIG_SND_SOC_SAMSUNG_USE_DMA_WRAPPER + &samsung_asoc_idma, +#endif +#if defined(CONFIG_CHARGER_MAX8922_U1) + &max8922_device_charger, +#endif +#ifdef CONFIG_EXYNOS_C2C + &exynos_device_c2c, +#endif +#if defined(CONFIG_S3C64XX_DEV_SPI) +#if defined(CONFIG_VIDEO_S5C73M3_SPI) + &exynos_device_spi1, +#endif +#if defined(CONFIG_PHONE_IPC_SPI) + &exynos_device_spi2, + &ipc_spi_device, +#elif defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + &exynos_device_spi2, +#endif +#endif +#if defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) + &samsung_device_keypad, +#endif +#ifdef CONFIG_BT_BCM4334 + &bcm4334_bluetooth_device, +#endif +#ifdef CONFIG_S5P_DEV_ACE + &s5p_device_ace, +#endif + &exynos4_busfreq, +#ifdef CONFIG_USB_HOST_NOTIFY + &host_notifier_device, +#endif +#ifdef CONFIG_EXYNOS4_SETUP_THERMAL + &s5p_device_tmu, +#endif +}; + +#ifdef CONFIG_EXYNOS4_SETUP_THERMAL +/* below temperature base on the celcius degree */ +struct s5p_platform_tmu midas_tmu_data __initdata = { + .ts = { + .stop_1st_throttle = 78, + .start_1st_throttle = 80, + .stop_2nd_throttle = 87, + .start_2nd_throttle = 103, + .start_tripping = 110, /* temp to do tripping */ + .start_emergency = 120, /* To protect chip,forcely kernel panic */ + .stop_mem_throttle = 80, + .start_mem_throttle = 85, + .stop_tc = 13, + .start_tc = 10, + }, + .cpufreq = { + .limit_1st_throttle = 800000, /* 800MHz in KHz order */ + .limit_2nd_throttle = 200000, /* 200MHz in KHz order */ + }, + .temp_compensate = { + .arm_volt = 925000, /* vdd_arm in uV for temperature compensation */ + .bus_volt = 900000, /* vdd_bus in uV for temperature compensation */ + .g3d_volt = 900000, /* vdd_g3d in uV for temperature compensation */ + }, +}; +#endif + +#if defined(CONFIG_USB_OHCI_S5P) && defined(CONFIG_LINK_DEVICE_HSIC) +static int __init s5p_ohci_device_initcall(void) +{ + return platform_device_register(&s5p_device_ohci); +} +late_initcall(s5p_ohci_device_initcall); +#endif +#if defined(CONFIG_USB_EHCI_S5P) && defined(CONFIG_LINK_DEVICE_HSIC) +static int __init s5p_ehci_device_initcall(void) +{ + return platform_device_register(&s5p_device_ehci); +} +late_initcall(s5p_ehci_device_initcall); +#endif + +#if defined(CONFIG_VIDEO_TVOUT) +static struct s5p_platform_hpd hdmi_hpd_data __initdata = { +#if defined(CONFIG_MACH_GC1) && defined(CONFIG_HDMI_CONTROLLED_BY_EXT_IC) + .ext_ic_control = hdmi_ext_ic_control_gc1, +#endif + +}; +static struct s5p_platform_cec hdmi_cec_data __initdata = { + +}; +#endif + +#if defined(CONFIG_CMA) +static unsigned long fbmem_start; +static unsigned long fbmem_size; +static int __init early_fbmem(char *p) +{ + char *endp; + + if (!p) + return -EINVAL; + + fbmem_size = memparse(p, &endp); + if (*endp == '@') + fbmem_start = memparse(endp + 1, &endp); + + return endp > p ? 0 : -EINVAL; +} +early_param("fbmem", early_fbmem); + +static void __init exynos4_reserve_mem(void) +{ + static struct cma_region regions[] = { +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS + { + .name = "fimc_is", + .size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS * SZ_1K, + { + .alignment = 1 << 26, + }, + .start = 0 + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD + { + .name = "fimd", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K, + { + .alignment = 1 << 20, + }, + .start = 0 + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 + { + .name = "fimc0", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 * SZ_1K, + .start = 0 + }, +#endif +#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \ + defined(CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0) + { + .name = "mfc0", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC0 * SZ_1K, + { + .alignment = 1 << 17, + }, + .start = 0, + }, +#endif +#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \ + defined(CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE) + { + .name = "ion", + .size = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC + { + .name = "mfc", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K, + { + .alignment = 1 << 17, + }, + .start = 0 + }, +#endif +#if !defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) && \ + defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) + { + .name = "b2", + .size = 32 << 20, + { .alignment = 128 << 10 }, + }, + { + .name = "b1", + .size = 32 << 20, + { .alignment = 128 << 10 }, + }, + { + .name = "fw", + .size = 1 << 20, + { .alignment = 128 << 10 }, + }, +#endif +#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP + { + .name = "srp", + .size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K, + .start = 0, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D + { + .name = "fimg2d", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K, + .start = 0 + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 + { + .name = "fimc1", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K, + .start = 0x65c00000, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 + { + .name = "mfc1", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 * SZ_1K, + { + .alignment = 1 << 26, + }, + .start = 0x64000000, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL + { + .name = "mfc-normal", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL * SZ_1K, + .start = 0x64000000, + }, +#endif + { + .size = 0 + }, + }; +#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION + static struct cma_region regions_secure[] = { +#ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE + { + .name = "ion", + .size = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE + { + .name = "mfc-secure", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K, + }, +#endif + { + .name = "sectbl", + .size = SZ_1M, + }, + { + .size = 0 + }, + }; +#else /* !CONFIG_EXYNOS_CONTENT_PATH_PROTECTION */ + struct cma_region *regions_secure = NULL; +#endif + + static const char map[] __initconst = + "s3cfb.0=fimd;exynos4-fb.0=fimd;" + "s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;" + "exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc.3=fimc3;" +#ifdef CONFIG_ION_EXYNOS + "ion-exynos=ion;" +#endif +#ifdef CONFIG_VIDEO_MFC5X + "s3c-mfc/A=mfc0,mfc-secure;" + "s3c-mfc/B=mfc1,mfc-normal;" + "s3c-mfc/AB=mfc;" +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC + "s5p-mfc/f=fw;" + "s5p-mfc/a=b1;" + "s5p-mfc/b=b2;" +#endif + "samsung-rp=srp;" +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS + "exynos4-fimc-is=fimc_is;" +#endif + "s5p-fimg2d=fimg2d;" +#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION + "s5p-smem/sectbl=sectbl;" +#endif + "s5p-smem/mfc=mfc-secure;" + "s5p-smem/fimc=ion;" + "s5p-smem/mfc-shm=mfc-normal;" + "s5p-smem/fimd=fimd;"; + + int i; + + s5p_cma_region_reserve(regions, regions_secure, 0, map); + + if (!(fbmem_start && fbmem_size)) + return; + + for (i = 0; i < ARRAY_SIZE(regions); i++) { + if (regions[i].name && !strcmp(regions[i].name, "fimd")) { + memcpy(phys_to_virt(regions[i].start), phys_to_virt(fbmem_start), fbmem_size * SZ_1K); + printk(KERN_INFO "Bootloader sent 'fbmem' : %08X\n", (u32)fbmem_start); + break; + } + } +} +#else +static inline void exynos4_reserve_mem(void) +{ +} +#endif + +#ifdef CONFIG_BACKLIGHT_PWM +/* LCD Backlight data */ +static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = { + .no = EXYNOS4_GPD0(1), + .func = S3C_GPIO_SFN(2), +}; + +static struct platform_pwm_backlight_data smdk4212_bl_data = { + .pwm_id = 1, +#ifdef CONFIG_FB_S5P_LMS501KF03 + .pwm_period_ns = 1000, +#endif +}; +#endif + +static void __init midas_map_io(void) +{ + clk_xusbxti.rate = 24000000; + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs)); + +#if defined(CONFIG_S5P_MEM_CMA) + exynos4_reserve_mem(); +#endif + + /* as soon as INFORM6 is visible, sec_debug is ready to run */ + sec_debug_init(); +} + +static void __init exynos_sysmmu_init(void) +{ + ASSIGN_SYSMMU_POWERDOMAIN(fimc0, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(fimc1, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(fimc2, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev); + ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev); + +#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X) + ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev); + ASSIGN_SYSMMU_POWERDOMAIN(mfc_r, &exynos4_device_pd[PD_MFC].dev); +#endif + ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev); +#ifdef CONFIG_VIDEO_FIMG2D + sysmmu_set_owner(&SYSMMU_PLATDEV(g2d_acp).dev, &s5p_device_fimg2d.dev); +#endif +#ifdef CONFIG_VIDEO_MFC5X + sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_r).dev, &s5p_device_mfc.dev); +#endif +#ifdef CONFIG_VIDEO_FIMC + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc0).dev, &s3c_device_fimc0.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc1).dev, &s3c_device_fimc1.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc2).dev, &s3c_device_fimc2.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(fimc3).dev, &s3c_device_fimc3.dev); +#endif +#ifdef CONFIG_VIDEO_TVOUT + sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev); +#endif +#ifdef CONFIG_VIDEO_JPEG_V2X + sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev); +#endif +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS + ASSIGN_SYSMMU_POWERDOMAIN(is_isp, &exynos4_device_pd[PD_ISP].dev); + ASSIGN_SYSMMU_POWERDOMAIN(is_drc, &exynos4_device_pd[PD_ISP].dev); + ASSIGN_SYSMMU_POWERDOMAIN(is_fd, &exynos4_device_pd[PD_ISP].dev); + ASSIGN_SYSMMU_POWERDOMAIN(is_cpu, &exynos4_device_pd[PD_ISP].dev); + + sysmmu_set_owner(&SYSMMU_PLATDEV(is_isp).dev, + &exynos4_device_fimc_is.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(is_drc).dev, + &exynos4_device_fimc_is.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(is_fd).dev, + &exynos4_device_fimc_is.dev); + sysmmu_set_owner(&SYSMMU_PLATDEV(is_cpu).dev, + &exynos4_device_fimc_is.dev); +#endif +} + +#ifdef CONFIG_FB_S5P_EXTDSP +struct platform_device s3c_device_extdsp = { + .name = "s3cfb_extdsp", + .id = 0, +}; + +static struct s3cfb_extdsp_lcd dummy_buffer = { + .width = 1920, + .height = 1080, + .bpp = 16, +}; + +static struct s3c_platform_fb default_extdsp_data __initdata = { + .hw_ver = 0x70, + .nr_wins = 1, + .default_win = 0, + .swap = FB_SWAP_WORD | FB_SWAP_HWORD, + .lcd = &dummy_buffer +}; + +void __init s3cfb_extdsp_set_platdata(struct s3c_platform_fb *pd) +{ + struct s3c_platform_fb *npd; + int i; + + if (!pd) + pd = &default_extdsp_data; + + npd = kmemdup(pd, sizeof(struct s3c_platform_fb), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + else { + for (i = 0; i < npd->nr_wins; i++) + npd->nr_buffers[i] = 1; + s3c_device_extdsp.dev.platform_data = npd; + } +} +#endif + +static inline int need_i2c5(void) +{ +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_GRANDE) \ + || defined(CONFIG_MACH_IRON) + return system_rev != 3; +#endif +} + +static void __init midas_machine_init(void) +{ + struct clk *ppmu_clk = NULL; + +#if defined(CONFIG_S3C64XX_DEV_SPI) +#if defined(CONFIG_VIDEO_S5C73M3_SPI) + unsigned int gpio; + struct clk *sclk = NULL; + struct clk *prnt = NULL; + struct device *spi1_dev = &exynos_device_spi1.dev; +#endif +#endif + /* + * prevent 4x12 ISP power off problem + * ISP_SYS Register has to be 0 before ISP block power off. + */ + __raw_writel(0x0, S5P_CMU_RESET_ISP_SYS); + + /* initialise the gpios */ + midas_config_gpio_table(); + exynos4_sleep_gpio_table_set = midas_config_sleep_gpio_table; + + midas_power_init(); + + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); + + s3c_i2c1_set_platdata(NULL); + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + + s3c_i2c3_set_platdata(NULL); + midas_tsp_init(); +#ifdef CONFIG_INPUT_FLIP + flip_init_hw(); +#endif + +#ifdef CONFIG_S3C_DEV_I2C4 + s3c_i2c4_set_platdata(NULL); + if (!(system_rev != 3 && system_rev >= 0)) { + i2c_register_board_info(4, i2c_devs4_max77693, + ARRAY_SIZE(i2c_devs4_max77693)); + } +#endif + midas_sound_init(); + +#ifdef CONFIG_S3C_DEV_I2C5 + if (need_i2c5()) { + s3c_i2c5_set_platdata(&default_i2c5_data); + i2c_register_board_info(5, i2c_devs5, + ARRAY_SIZE(i2c_devs5)); + } +#endif + + s3c_i2c7_set_platdata(NULL); + i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7)); +#if defined(CONFIG_KEYPAD_MELFAS_TOUCH) + touchkey_init_hw(); +#endif + i2c_register_board_info(8, i2c_devs8_emul, ARRAY_SIZE(i2c_devs8_emul)); + +#ifndef CONFIG_LEDS_AAT1290A + gpio_request(GPIO_3_TOUCH_INT, "3_TOUCH_INT"); + s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT); +#endif + + i2c_register_board_info(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul)); + + i2c_register_board_info(10, i2c_devs10_emul, + ARRAY_SIZE(i2c_devs10_emul)); + + i2c_register_board_info(11, i2c_devs11_emul, + ARRAY_SIZE(i2c_devs11_emul)); + +#if defined(CONFIG_PN65N_NFC) + i2c_register_board_info(12, i2c_devs12_emul, + ARRAY_SIZE(i2c_devs12_emul)); +#endif + +#ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE + /* max17047 fuel gauge */ + i2c_register_board_info(14, i2c_devs14_emul, + ARRAY_SIZE(i2c_devs14_emul)); +#endif +#ifdef CONFIG_SAMSUNG_MHL + printk(KERN_INFO "%s() register sii9234 driver\n", __func__); + + i2c_register_board_info(15, i2c_devs15_emul, + ARRAY_SIZE(i2c_devs15_emul)); + i2c_register_board_info(16, i2c_devs16_emul, + ARRAY_SIZE(i2c_devs16_emul)); +#endif +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_GRANDE) \ + || defined(CONFIG_MACH_IRON) + i2c_register_board_info(17, i2c_devs17_emul, + ARRAY_SIZE(i2c_devs17_emul)); +#endif +#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \ + || defined(CONFIG_FM_SI4705_MODULE) + i2c_register_board_info(19, i2c_devs19_emul, + ARRAY_SIZE(i2c_devs19_emul)); +#endif + +#ifdef CONFIG_REGULATOR_LP8720 +#ifdef GPIO_FOLDER_PMIC_EN + i2c_register_board_info(22, i2c_devs22_emul, + ARRAY_SIZE(i2c_devs22_emul)); +#endif /* GPIO_FOLDER_PMIC_EN */ +#ifdef GPIO_SUB_PMIC_EN + i2c_register_board_info(23, i2c_devs23_emul, + ARRAY_SIZE(i2c_devs23_emul)); +#endif /* GPIO_SUB_PMIC_EN */ +#endif + +#if defined(GPIO_OLED_DET) + gpio_request(GPIO_OLED_DET, "OLED_DET"); + s5p_register_gpio_interrupt(GPIO_OLED_DET); + gpio_free(GPIO_OLED_DET); +#endif + +#ifdef CONFIG_FB_S5P +#ifdef CONFIG_FB_S5P_LMS501KF03 + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + s3cfb_set_platdata(&lms501kf03_data); +#endif +#if defined(CONFIG_FB_S5P_MIPI_DSIM) + mipi_fb_init(); +#elif defined(CONFIG_FB_S5P_LD9040) + ld9040_fb_init(); +#elif defined(CONFIG_BACKLIGHT_PWM) + samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data); +#endif + s3cfb_set_platdata(&fb_platform_data); + +#ifdef CONFIG_EXYNOS_DEV_PD + s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#endif +#endif +#ifdef CONFIG_USB_EHCI_S5P + smdk4212_ehci_init(); +#endif +#ifdef CONFIG_USB_OHCI_S5P + smdk4212_ohci_init(); +#endif +#ifdef CONFIG_USB_GADGET + smdk4212_usbgadget_init(); +#endif + +#ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS + exynos4_fimc_is_set_platdata(NULL); +#ifdef CONFIG_EXYNOS_DEV_PD + exynos4_device_fimc_is.dev.parent = &exynos4_device_pd[PD_ISP].dev; +#endif +#endif +#ifdef CONFIG_EXYNOS4_DEV_MSHC + s3c_mshci_set_platdata(&exynos4_mshc_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC + s3c_sdhci0_set_platdata(&smdk4212_hsmmc0_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + s3c_sdhci1_set_platdata(&smdk4212_hsmmc1_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata); +#endif + + midas_camera_init(); + +#ifdef CONFIG_FB_S5P_EXTDSP + s3cfb_extdsp_set_platdata(&default_extdsp_data); +#endif + +#if defined(CONFIG_VIDEO_TVOUT) + s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data); + s5p_hdmi_cec_set_platdata(&hdmi_cec_data); +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev; + exynos4_device_pd[PD_TV].dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#endif +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2X +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev; + exynos4_jpeg_setup_clock(&s5p_device_jpeg.dev, 160000000); +#endif +#endif + +#ifdef CONFIG_ION_EXYNOS + exynos_ion_set_platdata(); +#endif + +#if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; +#endif + exynos4_mfc_setup_clock(&s5p_device_mfc.dev, 200 * MHZ); +#endif + +#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) + dev_set_name(&s5p_device_mfc.dev, "s3c-mfc"); + clk_add_alias("mfc", "s5p-mfc", "mfc", &s5p_device_mfc.dev); + s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc"); +#endif +#ifdef CONFIG_VIDEO_FIMG2D + s5p_fimg2d_set_platdata(&fimg2d_data); +#endif +#ifdef CONFIG_EXYNOS_C2C + exynos_c2c_set_platdata(&smdk4212_c2c_pdata); +#endif + + brcm_wlan_init(); + +#ifdef CONFIG_EXYNOS4_SETUP_THERMAL + s5p_tmu_set_platdata(&midas_tmu_data); +#endif + + exynos_sysmmu_init(); + + platform_add_devices(midas_devices, ARRAY_SIZE(midas_devices)); + +#ifdef CONFIG_S3C_ADC + platform_device_register(&s3c_device_adc); +#endif +#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \ + || defined(CONFIG_FM_SI4705_MODULE) + platform_device_register(&s3c_device_i2c19); +#endif +#if defined(CONFIG_BATTERY_SAMSUNG) + platform_device_register(&samsung_device_battery); +#endif +#ifdef CONFIG_SEC_THERMISTOR + platform_device_register(&sec_device_thermistor); +#endif + +#if defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) + midas_gpiokeys_platform_data.buttons = midas_buttons; + midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(midas_buttons); +#endif + /* Above logic is too complex. Let's override whatever the + result is... */ + + platform_device_register(&midas_keypad); + +#if defined(CONFIG_MACH_GRANDE) || defined(CONFIG_MACH_IRON) + samsung_keypad_set_platdata(&smdk4x12_keypad_data); +#endif + +#ifdef CONFIG_INPUT_FLIP + platform_device_register(&sec_flip_device); +#endif + +#if defined(CONFIG_S3C_DEV_I2C5) + if (need_i2c5()) + platform_device_register(&s3c_device_i2c5); +#endif + +#if defined(CONFIG_PN65N_NFC) + platform_device_register(&s3c_device_i2c12); +#endif + +#if defined(CONFIG_SEC_DEV_JACK) + grande_jack_init(); +#endif + +#if defined(CONFIG_S3C64XX_DEV_SPI) +#if defined(CONFIG_VIDEO_S5C73M3_SPI) + sclk = clk_get(spi1_dev, "dout_spi1"); + if (IS_ERR(sclk)) + dev_err(spi1_dev, "failed to get sclk for SPI-1\n"); + prnt = clk_get(spi1_dev, "mout_mpll_user"); + if (IS_ERR(prnt)) + dev_err(spi1_dev, "failed to get prnt\n"); + if (clk_set_parent(sclk, prnt)) + printk(KERN_ERR "Unable to set parent %s of clock %s.\n", + prnt->name, sclk->name); + + clk_set_rate(sclk, 88 * 1000 * 1000); + clk_put(sclk); + clk_put(prnt); + + if (!gpio_request(EXYNOS4_GPB(5), "SPI_CS1")) { + gpio_direction_output(EXYNOS4_GPB(5), 1); + s3c_gpio_cfgpin(EXYNOS4_GPB(5), S3C_GPIO_SFN(1)); + s3c_gpio_setpull(EXYNOS4_GPB(5), S3C_GPIO_PULL_UP); + exynos_spi_set_info(1, EXYNOS_SPI_SRCCLK_SCLK, + ARRAY_SIZE(spi1_csi)); + } + + for (gpio = EXYNOS4_GPB(4); gpio < EXYNOS4_GPB(8); gpio++) + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); + + spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info)); +#endif +#endif + +#ifdef CONFIG_BUSFREQ_OPP + dev_add(&busfreq, &exynos4_busfreq.dev); + + /* PPMUs using for cpufreq get clk from clk_list */ + ppmu_clk = clk_get(NULL, "ppmudmc0"); + if (IS_ERR(ppmu_clk)) + printk(KERN_ERR "failed to get ppmu_dmc0\n"); + clk_enable(ppmu_clk); + clk_put(ppmu_clk); + + ppmu_clk = clk_get(NULL, "ppmudmc1"); + if (IS_ERR(ppmu_clk)) + printk(KERN_ERR "failed to get ppmu_dmc1\n"); + clk_enable(ppmu_clk); + clk_put(ppmu_clk); + + ppmu_clk = clk_get(NULL, "ppmucpu"); + if (IS_ERR(ppmu_clk)) + printk(KERN_ERR "failed to get ppmu_cpu\n"); + clk_enable(ppmu_clk); + clk_put(ppmu_clk); + + ppmu_init(&exynos_ppmu[PPMU_DMC0], &exynos4_busfreq.dev); + ppmu_init(&exynos_ppmu[PPMU_DMC1], &exynos4_busfreq.dev); + ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos4_busfreq.dev); +#endif + + /* 400 kHz for initialization of MMC Card */ + __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0) + | 0x9, EXYNOS4_CLKDIV_FSYS3); +#if (defined(CONFIG_MACH_M0) && defined(CONFIG_TARGET_LOCALE_EUR)) || \ + ((defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M0)) && \ + defined(CONFIG_TARGET_LOCALE_KOR)) + __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0x00f0fff0) + | 0x10008, EXYNOS4_CLKDIV_FSYS2); +#else + __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0) + | 0x80008, EXYNOS4_CLKDIV_FSYS2); +#endif + __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0) + | 0x80008, EXYNOS4_CLKDIV_FSYS1); +} + +static void __init exynos_init_reserve(void) +{ + sec_debug_magic_init(); +} + +MACHINE_START(SMDK4412, "SMDK4x12") + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = exynos4_init_irq, + .map_io = midas_map_io, + .init_machine = midas_machine_init, + .timer = &exynos4_timer, + .init_early = &exynos_init_reserve, +MACHINE_END + +MACHINE_START(SMDK4212, "SMDK4x12") + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = exynos4_init_irq, + .map_io = midas_map_io, + .init_machine = midas_machine_init, + .timer = &exynos4_timer, + .init_early = &exynos_init_reserve, +MACHINE_END diff --git a/arch/arm/mach-exynos/board-iron-gpio.c b/arch/arm/mach-exynos/board-iron-gpio.c new file mode 100644 index 0000000..5374b4a --- /dev/null +++ b/arch/arm/mach-exynos/board-iron-gpio.c @@ -0,0 +1,474 @@ +/* + * linux/arch/arm/mach-exynos/board-iron-gpio.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - GPIO setting in set board + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/serial_core.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-serial.h> +#include <mach/gpio-midas.h> +#include <plat/cpu.h> +#include <mach/pmu.h> + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + +/* + * M0 GPIO Init Table + */ +static struct gpio_init_data m0_init_gpios[] = { + {EXYNOS4_GPA1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPC1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* TSK_LDO_EN */ + {EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */ + {EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */ + {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */ + {EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */ + {EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */ + {EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* V_BUS_INT */ + {EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */ + {EXYNOS4_GPX2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_HOST_WAKEUP */ + {EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */ + {EXYNOS4_GPX2(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* nPower */ + {EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */ + {EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */ + {EXYNOS4_GPX3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CP_PMU_RST */ + {EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */ + {EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */ + {EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */ + {EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */ + {EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */ + {EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */ + {EXYNOS4212_GPM3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PMIC_DVS1 */ + {EXYNOS4212_GPM4(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV3}, /* MSENSE_RST_N */ + {EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4212_GPJ0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV3}, /* GPIO_3_TOUCH_INT */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV3}, /* GPIO_MSENSOR_INT */ + {EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* CAM_MCLK */ + {EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* VTCAM_MCLK */ +}; + +/* + * IRON GPIO Sleep Table + */ +static unsigned int iron_sleep_gpio_table[][3] = { + {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + + {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */ + {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PCM_SEL */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SCL*/ + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SDA*/ + + {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK2_SEL*/ + {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK3_SEL*/ + {EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK4_SEL*/ + {EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CLK*/ + {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CMD*/ + {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*eMMC_EN*/ + {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(0)*/ + {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(1)*/ + {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(2)*/ + {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(3)*/ + + {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(4)*/ + {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(5)*/ + {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(6)*/ + {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(7)*/ + + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */ +/* {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ + {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +/* {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ + + {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +/* {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, */ + + {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPX0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP},/* PS_ALS_INT */ + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ + {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY4(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY5(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY6(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + /* Exynos4212 specific gpio */ + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*TCH_EN*/ + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*TCH_SET*/ + {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS1*/ + {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS2*/ + {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS3*/ + /* GPM3(3) M0, CP_RESET_REQ hold high */ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SCL*/ + {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SDA*/ + {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +}; /* iron_sleep_gpio_table */ + +static void config_sleep_gpio_table(int array_size, + unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +/* To save power consumption, gpio pin set before enterling sleep */ +void midas_config_sleep_gpio_table(void) +{ + config_sleep_gpio_table(ARRAY_SIZE(iron_sleep_gpio_table), + iron_sleep_gpio_table); +} + +/* Intialize gpio set in midas board */ +void midas_config_gpio_table(void) +{ + u32 i, gpio; + + printk(KERN_DEBUG "%s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(m0_init_gpios); i++) { + gpio = m0_init_gpios[i].num; + if (gpio <= EXYNOS4212_GPV4(1)) { + s3c_gpio_cfgpin(gpio, m0_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, m0_init_gpios[i].pud); + + if (m0_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, m0_init_gpios[i].val); + + s5p_gpio_set_drvstr(gpio, m0_init_gpios[i].drv); + } + } +} diff --git a/arch/arm/mach-exynos/board-iron-modems.c b/arch/arm/mach-exynos/board-iron-modems.c new file mode 100644 index 0000000..9a942c9 --- /dev/null +++ b/arch/arm/mach-exynos/board-iron-modems.c @@ -0,0 +1,1174 @@ +/* linux/arch/arm/mach-xxxx/board-iron-modems.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Modem configuraiton for Iron (P-Q + XMM6262)*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <mach/gpio-exynos4.h> +#include <plat/gpio-cfg.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/delay.h> + +#include <linux/platform_data/modem.h> +#include <mach/sec_modem.h> + +#if defined(CONFIG_GSM_MODEM_ESC6270) +#include <linux/interrupt.h> +#include <linux/io.h> +#include <mach/gpio.h> +#include <mach/gpio-exynos4.h> +#include <plat/gpio-cfg.h> +#include <mach/regs-mem.h> +#include <plat/regs-srom.h> + + +#define SROM_CS0_BASE 0x04000000 +#define SROM_WIDTH 0x01000000 +#define SROM_NUM_ADDR_BITS 14 + +/* + * For SROMC Configuration: + * SROMC_ADDR_BYTE enable for byte access + */ +#define SROMC_DATA_16 0x1 +#define SROMC_ADDR_BYTE 0x2 +#define SROMC_WAIT_EN 0x4 +#define SROMC_BYTE_EN 0x8 +#define SROMC_MASK 0xF + +/* Memory attributes */ +enum sromc_attr { + MEM_DATA_BUS_16BIT = 0x00000001, + MEM_BYTE_ADDRESSABLE = 0x00000002, + MEM_WAIT_EN = 0x00000004, + MEM_BYTE_EN = 0x00000008, + +}; + +/* DPRAM configuration */ +struct sromc_cfg { + enum sromc_attr attr; + unsigned size; + unsigned csn; /* CSn # */ + unsigned addr; /* Start address (physical) */ + unsigned end; /* End address (physical) */ +}; + +/* DPRAM access timing configuration */ +struct sromc_access_cfg { + u32 tacs; /* Address set-up before CSn */ + u32 tcos; /* Chip selection set-up before OEn */ + u32 tacc; /* Access cycle */ + u32 tcoh; /* Chip selection hold on OEn */ + u32 tcah; /* Address holding time after CSn */ + u32 tacp; /* Page mode access cycle at Page mode */ + u32 pmc; /* Page Mode config */ +}; + +/* For MDM6600 EDPRAM (External DPRAM) */ +#define MSM_EDPRAM_SIZE 0x4000 /* 16 KB */ + +#define INT_MASK_REQ_ACK_F 0x0020 +#define INT_MASK_REQ_ACK_R 0x0010 +#define INT_MASK_RES_ACK_F 0x0008 +#define INT_MASK_RES_ACK_R 0x0004 +#define INT_MASK_SEND_F 0x0002 +#define INT_MASK_SEND_R 0x0001 + +#define INT_MASK_REQ_ACK_RFS 0x0400 /* Request RES_ACK_RFS */ +#define INT_MASK_RES_ACK_RFS 0x0200 /* Response of REQ_ACK_RFS */ +#define INT_MASK_SEND_RFS 0x0100 /* Indicate sending RFS data */ + + +#define MSM_DP_FMT_TX_BUFF_SZ 2044 +#define MSM_DP_RAW_TX_BUFF_SZ 6128 +#define MSM_DP_FMT_RX_BUFF_SZ 2044 +#define MSM_DP_RAW_RX_BUFF_SZ 6128 + +#define MAX_MSM_EDPRAM_IPC_DEV 2 /* FMT, RAW */ + + +struct msm_edpram_ipc_cfg { + u16 magic; + u16 access; + + u16 fmt_tx_head; + u16 fmt_tx_tail; + u8 fmt_tx_buff[MSM_DP_FMT_TX_BUFF_SZ]; + + u16 raw_tx_head; + u16 raw_tx_tail; + u8 raw_tx_buff[MSM_DP_RAW_TX_BUFF_SZ]; + + u16 fmt_rx_head; + u16 fmt_rx_tail; + u8 fmt_rx_buff[MSM_DP_FMT_RX_BUFF_SZ]; + + u16 raw_rx_head; + u16 raw_rx_tail; + u8 raw_rx_buff[MSM_DP_RAW_RX_BUFF_SZ]; + + u8 padding[16]; + u16 mbx_ap2cp; + u16 mbx_cp2ap; +}; + + + +#if (MSM_EDPRAM_SIZE == 0x4000) +/* +------------------ +Buffer : 15KByte +------------------ +Reserved: 1014Byte +------------------ +SIZE: 2Byte +------------------ +TAG: 2Byte +------------------ +COUNT: 2Byte +------------------ +AP -> CP Intr : 2Byte +------------------ +CP -> AP Intr : 2Byte +------------------ +*/ +#define DP_BOOT_CLEAR_OFFSET 4 +#define DP_BOOT_RSRVD_OFFSET 0x3C00 +#define DP_BOOT_SIZE_OFFSET 0x3FF6 +#define DP_BOOT_TAG_OFFSET 0x3FF8 +#define DP_BOOT_COUNT_OFFSET 0x3FFA + +#define DP_BOOT_FRAME_SIZE_LIMIT 0x3C00 /* 15KB = 15360byte = 0x3C00 */ +#else +/* +------------------ +Buffer : 31KByte +------------------ +Reserved: 1014Byte +------------------ +SIZE: 2Byte +------------------ +TAG: 2Byte +------------------ +COUNT: 2Byte +------------------ +AP -> CP Intr : 2Byte +------------------ +CP -> AP Intr : 2Byte +------------------ +*/ +#define DP_BOOT_CLEAR_OFFSET 4 +#define DP_BOOT_RSRVD_OFFSET 0x7C00 +#define DP_BOOT_SIZE_OFFSET 0x7FF6 +#define DP_BOOT_TAG_OFFSET 0x7FF8 +#define DP_BOOT_COUNT_OFFSET 0x7FFA + +#define DP_BOOT_FRAME_SIZE_LIMIT 0x7C00 /* 31KB = 31744byte = 0x7C00 */ +#endif + +#endif + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +/* umts target platform data */ +static struct modem_io_t umts_io_devices[] = { + [0] = { + .name = "umts_ipc0", + .id = 0x1, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [1] = { + .name = "umts_rfs0", + .id = 0x41, + .format = IPC_RFS, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [2] = { + .name = "umts_boot0", + .id = 0x0, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [3] = { + .name = "multipdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [4] = { +#ifdef CONFIG_SLP + .name = "pdp0", +#else + .name = "rmnet0", +#endif + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [5] = { +#ifdef CONFIG_SLP + .name = "pdp1", +#else + .name = "rmnet1", +#endif + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [6] = { +#ifdef CONFIG_SLP + .name = "pdp2", +#else + .name = "rmnet2", +#endif + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [7] = { + .name = "umts_router", + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [8] = { + .name = "umts_csd", + .id = 0x21, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [9] = { + .name = "umts_ramdump0", + .id = 0x0, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_HSIC), + }, + [10] = { + .name = "umts_loopback0", + .id = 0x3f, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_HSIC), + }, +}; + +/* To get modem state, register phone active irq using resource */ +static struct resource umts_modem_res[] = { +}; + +static int umts_link_ldo_enble(bool enable) +{ + /* Exynos HSIC V1.2 LDO was controlled by kernel */ + return 0; +} + +static int umts_link_reconnect(void); +static struct modemlink_pm_data modem_link_pm_data = { + .name = "link_pm", + .link_ldo_enable = umts_link_ldo_enble, + .gpio_link_enable = 0, + .gpio_link_active = GPIO_ACTIVE_STATE, + .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, + .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, + .link_reconnect = umts_link_reconnect, +}; + +static struct modemlink_pm_link_activectl active_ctl; + +static void xmm_gpio_revers_bias_clear(void); +static void xmm_gpio_revers_bias_restore(void); + +#ifndef GPIO_AP_DUMP_INT +#define GPIO_AP_DUMP_INT 0 +#endif +static struct modem_data umts_modem_data = { + .name = "xmm6262", + + .gpio_cp_on = GPIO_PHONE_ON, + .gpio_reset_req_n = GPIO_CP_REQ_RESET, + .gpio_cp_reset = GPIO_CP_RST, + .gpio_pda_active = GPIO_PDA_ACTIVE, + .gpio_phone_active = GPIO_PHONE_ACTIVE, + .gpio_cp_dump_int = GPIO_CP_DUMP_INT, + .gpio_ap_dump_int = GPIO_AP_DUMP_INT, + .gpio_flm_uart_sel = 0, + .gpio_cp_warm_reset = 0, + + .modem_type = IMC_XMM6262, + .link_types = LINKTYPE(LINKDEV_HSIC), + .modem_net = UMTS_NETWORK, + .use_handover = false, + + .num_iodevs = ARRAY_SIZE(umts_io_devices), + .iodevs = umts_io_devices, + + .link_pm_data = &modem_link_pm_data, + .gpio_revers_bias_clear = xmm_gpio_revers_bias_clear, + .gpio_revers_bias_restore = xmm_gpio_revers_bias_restore, +}; + +/* HSIC specific function */ +void set_slave_wake(void) +{ + if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) { + pr_info("[MODEM_IF]Slave Wake\n"); + if (gpio_get_value(modem_link_pm_data.gpio_link_slavewake)) { + pr_info("[MODEM_IF]Slave Wake set _-\n"); + gpio_direction_output( + modem_link_pm_data.gpio_link_slavewake, 0); + mdelay(10); + } + gpio_direction_output( + modem_link_pm_data.gpio_link_slavewake, 1); + } +} + +void set_host_states(struct platform_device *pdev, int type) +{ + int val = gpio_get_value(umts_modem_data.gpio_cp_reset); + + if (!val) { + pr_info("CP not ready, Active State low\n"); + return; + } + + if (active_ctl.gpio_initialized) { + pr_err(LOG_TAG "Active States =%d, %s\n", type, pdev->name); + gpio_direction_output(modem_link_pm_data.gpio_link_active, + type); + } +} + +void set_hsic_lpa_states(int states) +{ + int val = gpio_get_value(umts_modem_data.gpio_cp_reset); + + mif_trace("\n"); + + if (val) { + switch (states) { + case STATE_HSIC_LPA_ENTER: + gpio_set_value(modem_link_pm_data.gpio_link_active, 0); + gpio_set_value(umts_modem_data.gpio_pda_active, 0); + pr_info(LOG_TAG "set hsic lpa enter: " + "active state (%d)" ", pda active (%d)\n", + gpio_get_value( + modem_link_pm_data.gpio_link_active), + gpio_get_value(umts_modem_data.gpio_pda_active) + ); + break; + case STATE_HSIC_LPA_WAKE: + gpio_set_value(umts_modem_data.gpio_pda_active, 1); + pr_info(LOG_TAG "set hsic lpa wake: " + "pda active (%d)\n", + gpio_get_value(umts_modem_data.gpio_pda_active) + ); + break; + case STATE_HSIC_LPA_PHY_INIT: + gpio_set_value(umts_modem_data.gpio_pda_active, 1); + set_slave_wake(); + pr_info(LOG_TAG "set hsic lpa phy init: " + "slave wake-up (%d)\n", + gpio_get_value( + modem_link_pm_data.gpio_link_slavewake) + ); + break; + } + } +} + +int get_cp_active_state(void) +{ + return gpio_get_value(umts_modem_data.gpio_phone_active); +} + +static int umts_link_reconnect(void) +{ + if (gpio_get_value(umts_modem_data.gpio_phone_active) && + gpio_get_value(umts_modem_data.gpio_cp_reset)) { + pr_info("[MODEM_IF] trying reconnect link\n"); + gpio_set_value(modem_link_pm_data.gpio_link_active, 0); + mdelay(10); + set_slave_wake(); + gpio_set_value(modem_link_pm_data.gpio_link_active, 1); + } else + return -ENODEV; + + return 0; +} + +/* if use more than one modem device, then set id num */ +static struct platform_device umts_modem = { + .name = "modem_if", + .id = -1, + .num_resources = ARRAY_SIZE(umts_modem_res), + .resource = umts_modem_res, + .dev = { + .platform_data = &umts_modem_data, + }, +}; + +static void umts_modem_cfg_gpio(void) +{ + int err = 0; + + unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n; + unsigned gpio_cp_on = umts_modem_data.gpio_cp_on; + unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset; + unsigned gpio_pda_active = umts_modem_data.gpio_pda_active; + unsigned gpio_phone_active = umts_modem_data.gpio_phone_active; + unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int; + unsigned gpio_ap_dump_int = umts_modem_data.gpio_ap_dump_int; + unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel; + unsigned irq_phone_active = umts_modem_res[0].start; + + if (gpio_reset_req_n) { + err = gpio_request(gpio_reset_req_n, "RESET_REQ_N"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "RESET_REQ_N", err); + } + s3c_gpio_slp_cfgpin(gpio_reset_req_n, S3C_GPIO_SLP_OUT1); + gpio_direction_output(gpio_reset_req_n, 0); + } + + if (gpio_cp_on) { + err = gpio_request(gpio_cp_on, "CP_ON"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "CP_ON", err); + } + gpio_direction_output(gpio_cp_on, 0); + } + + if (gpio_cp_rst) { + err = gpio_request(gpio_cp_rst, "CP_RST"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "CP_RST", err); + } + s3c_gpio_slp_cfgpin(gpio_cp_rst, S3C_GPIO_SLP_OUT1); + gpio_direction_output(gpio_cp_rst, 0); + } + + if (gpio_pda_active) { + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "PDA_ACTIVE", err); + } + gpio_direction_output(gpio_pda_active, 0); + } + + if (gpio_phone_active) { + err = gpio_request(gpio_phone_active, "PHONE_ACTIVE"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "PHONE_ACTIVE", err); + } + gpio_direction_input(gpio_phone_active); + pr_err(LOG_TAG "check phone active = %d\n", irq_phone_active); + } + + if (gpio_cp_dump_int) { + err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "CP_DUMP_INT", err); + } + gpio_direction_input(gpio_cp_dump_int); + } + + if (gpio_ap_dump_int /*&& system_rev >= 11*/) { /* MO rev1.0*/ + err = gpio_request(gpio_ap_dump_int, "AP_DUMP_INT"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "AP_DUMP_INT", err); + } + gpio_direction_output(gpio_ap_dump_int, 0); + } + + if (gpio_flm_uart_sel) { + err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "GPS_UART_SEL", err); + } + gpio_direction_output(gpio_reset_req_n, 0); + } + + if (gpio_phone_active) + irq_set_irq_type(gpio_to_irq(gpio_phone_active), + IRQ_TYPE_LEVEL_HIGH); + +#if !defined(CONFIG_GSM_MODEM_ESC6270) + /* set low unused gpios between AP and CP */ + err = gpio_request(GPIO_FLM_RXD, "FLM_RXD"); + if (err) + pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD", + err); + else { + gpio_direction_output(GPIO_FLM_RXD, 0); + s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); + } + err = gpio_request(GPIO_FLM_TXD, "FLM_TXD"); + if (err) + pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD", + err); + else { + gpio_direction_output(GPIO_FLM_TXD, 0); + s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); + } +#endif + + err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ"); + if (err) + pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ", + err); + else { + gpio_direction_output(GPIO_SUSPEND_REQUEST, 0); + s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE); + } + err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL"); + if (err) + pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL", + err); + else { + gpio_direction_output(GPIO_GPS_CNTL, 0); + s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE); + } + + pr_info(LOG_TAG "umts_modem_cfg_gpio done\n"); +} + +static void xmm_gpio_revers_bias_clear(void) +{ + gpio_direction_output(umts_modem_data.gpio_pda_active, 0); + gpio_direction_output(umts_modem_data.gpio_phone_active, 0); + gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0); + gpio_direction_output(modem_link_pm_data.gpio_link_active, 0); + gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0); + gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0); + + msleep(20); +} + +static void xmm_gpio_revers_bias_restore(void) +{ + s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF)); + s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake, + S3C_GPIO_SFN(0xF)); + gpio_direction_input(umts_modem_data.gpio_cp_dump_int); +} + +static void modem_link_pm_config_gpio(void) +{ + int err = 0; + + unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable; + unsigned gpio_link_active = modem_link_pm_data.gpio_link_active; + unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake; + unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake; + /* unsigned irq_link_hostwake = umts_modem_res[1].start; */ + + if (gpio_link_enable) { + err = gpio_request(gpio_link_enable, "LINK_EN"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "LINK_EN", err); + } + gpio_direction_output(gpio_link_enable, 0); + } + + if (gpio_link_active) { + err = gpio_request(gpio_link_active, "LINK_ACTIVE"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "LINK_ACTIVE", err); + } + gpio_direction_output(gpio_link_active, 0); + } + + if (gpio_link_hostwake) { + err = gpio_request(gpio_link_hostwake, "HOSTWAKE"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "HOSTWAKE", err); + } + gpio_direction_input(gpio_link_hostwake); + } + + if (gpio_link_slavewake) { + err = gpio_request(gpio_link_slavewake, "SLAVEWAKE"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "SLAVEWAKE", err); + } + gpio_direction_output(gpio_link_slavewake, 0); + } + + if (gpio_link_hostwake) + irq_set_irq_type(gpio_to_irq(gpio_link_hostwake), + IRQ_TYPE_EDGE_BOTH); + + active_ctl.gpio_initialized = 1; + + pr_info(LOG_TAG "modem_link_pm_config_gpio done\n"); +} + +/* For ESC6270 modem */ +#if defined(CONFIG_GSM_MODEM_ESC6270) +static struct dpram_ipc_map gsm_ipc_map; + +static struct sromc_cfg gsm_edpram_cfg = { + .attr = (MEM_DATA_BUS_16BIT | MEM_WAIT_EN | MEM_BYTE_EN), + .size = MSM_EDPRAM_SIZE, +}; + +static struct sromc_access_cfg gsm_edpram_access_cfg[] = { + [DPRAM_SPEED_LOW] = { + .tacs = 0x2 << 28, + .tcos = 0x2 << 24, + .tacc = 0x3 << 16, + .tcoh = 0x2 << 12, + .tcah = 0x2 << 8, + .tacp = 0x2 << 4, + .pmc = 0x0 << 0, + }, +}; + +static struct modemlink_dpram_control gsm_edpram_ctrl = { + .dp_type = EXT_DPRAM, + + .dpram_irq = ESC_DPRAM_INT_IRQ, + .dpram_irq_flags = IRQF_TRIGGER_FALLING, + + .max_ipc_dev = IPC_RFS, + .ipc_map = &gsm_ipc_map, + + .boot_size_offset = DP_BOOT_SIZE_OFFSET, + .boot_tag_offset = DP_BOOT_TAG_OFFSET, + .boot_count_offset = DP_BOOT_COUNT_OFFSET, + .max_boot_frame_size = DP_BOOT_FRAME_SIZE_LIMIT, +}; + +/* +** GSM target platform data +*/ +static struct modem_io_t gsm_io_devices[] = { + [0] = { + .name = "gsm_ipc0", + .id = 0x01, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [1] = { + .name = "gsm_rfs0", + .id = 0x28, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [2] = { + .name = "gsm_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [3] = { + .name = "gsm_multi_pdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [4] = { + .name = "gsm_rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [5] = { + .name = "gsm_rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [6] = { + .name = "gsm_rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [7] = { + .name = "gsm_router", + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [8] = { + .name = "gsm_csd", + .id = 0x21, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [9] = { + .name = "gsm_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [10] = { + .name = "gsm_loopback0", + .id = 0x3F, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, +}; + +static struct modem_data gsm_modem_data = { + .name = "esc6270", + + .gpio_cp_on = GPIO_CP2_MSM_PWRON, + .gpio_cp_off = 0, + .gpio_reset_req_n = 0, /* GPIO_CP_MSM_PMU_RST, */ + .gpio_cp_reset = GPIO_CP2_MSM_RST, + .gpio_pda_active = 0, + .gpio_phone_active = GPIO_ESC_PHONE_ACTIVE, + .gpio_flm_uart_sel = GPIO_BOOT_SW_SEL_CP2, + + .gpio_dpram_int = GPIO_ESC_DPRAM_INT, + + .gpio_cp_dump_int = 0, + .gpio_cp_warm_reset = 0, + + .use_handover = false, + + .modem_net = CDMA_NETWORK, + .modem_type = QC_ESC6270, + .link_types = LINKTYPE(LINKDEV_DPRAM), + .link_name = "esc6270_edpram", + .dpram_ctl = &gsm_edpram_ctrl, + + .ipc_version = SIPC_VER_41, + + .num_iodevs = ARRAY_SIZE(gsm_io_devices), + .iodevs = gsm_io_devices, +}; + +static struct resource gsm_modem_res[] = { + [0] = { + .name = "cp_active_irq", + .start = ESC_PHONE_ACTIVE_IRQ, + .end = ESC_PHONE_ACTIVE_IRQ, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "dpram_irq", + .start = ESC_DPRAM_INT_IRQ, + .end = ESC_DPRAM_INT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device gsm_modem = { + .name = "modem_if", + .id = 1, + .num_resources = ARRAY_SIZE(gsm_modem_res), + .resource = gsm_modem_res, + .dev = { + .platform_data = &gsm_modem_data, + }, +}; + +static void config_dpram_port_gpio(void) +{ + int addr_bits = SROM_NUM_ADDR_BITS; + + pr_info("[MDM] <%s> address line = %d bits\n", __func__, addr_bits); + + /* + ** Config DPRAM address/data GPIO pins + */ + + /* Set GPIO for dpram address */ + switch (addr_bits) { + case 0: + break; + + case 13 ... 14: + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR, + S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0), + addr_bits - EXYNOS4_GPIO_Y3_NR, + S3C_GPIO_SFN(2)); + pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n", + __func__, addr_bits - EXYNOS4_GPIO_Y3_NR); + break; + + default: + pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__); + return; + } + + /* Set GPIO for dpram data - 16bit */ + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY6(0), 8, S3C_GPIO_SFN(2)); + +#if 0 + /* Setup SROMC CSn pins */ + s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2)); +#endif + +#if defined(CONFIG_GSM_MODEM_ESC6270) + s3c_gpio_cfgpin(GPIO_DPRAM_CSN1, S3C_GPIO_SFN(2)); +#endif + + /* Config OEn, WEn */ + s3c_gpio_cfgrange_nopull(GPIO_DPRAM_REN, 2, S3C_GPIO_SFN(2)); + + /* Config LBn, UBn */ + s3c_gpio_cfgrange_nopull(GPIO_DPRAM_LBN, 2, S3C_GPIO_SFN(2)); + + /* Config BUSY */ + s3c_gpio_cfgpin(GPIO_DPRAM_BUSY, S3C_GPIO_SFN(2)); +} + + +static void init_sromc(void) +{ + struct clk *clk = NULL; + + /* SROMC clk enable */ + clk = clk_get(NULL, "sromc"); + if (!clk) { + pr_err("[MDM/E] <%s> SROMC clock gate fail\n", __func__); + return; + } + clk_enable(clk); +} + +static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, + struct sromc_access_cfg *acc_cfg) +{ + unsigned bw = 0; + unsigned bc = 0; + void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); + + pr_err("[MDM] <%s> SROMC settings for CS%d...\n", __func__, csn); + + bw = __raw_readl(S5P_SROM_BW); + bc = __raw_readl(bank_sfr); + pr_err("[MDM] <%s> Old SROMC settings = BW(0x%08X), BC%d(0x%08X)\n", + __func__, bw, csn, bc); + + /* Set the BW control field for the CSn */ + bw &= ~(SROMC_MASK << (csn * 4)); + + if (cfg->attr | MEM_DATA_BUS_16BIT) + bw |= (SROMC_DATA_16 << (csn * 4)); + + if (cfg->attr | MEM_WAIT_EN) + bw |= (SROMC_WAIT_EN << (csn * 4)); + + if (cfg->attr | MEM_BYTE_EN) + bw |= (SROMC_BYTE_EN << (csn * 4)); + + writel(bw, S5P_SROM_BW); + + /* Set SROMC memory access timing for the CSn */ + bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | + acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; + + writel(bc, bank_sfr); + + /* Verify SROMC settings */ + bw = __raw_readl(S5P_SROM_BW); + bc = __raw_readl(bank_sfr); + pr_err("[MDM] <%s> New SROMC settings = BW(0x%08X), BC%d(0x%08X)\n", + __func__, bw, csn, bc); +} + + +void config_gsm_modem_gpio(void) +{ + int err = 0; + unsigned gpio_cp_on = gsm_modem_data.gpio_cp_on; + unsigned gpio_cp_off = gsm_modem_data.gpio_cp_off; + unsigned gpio_rst_req_n = gsm_modem_data.gpio_reset_req_n; + unsigned gpio_cp_rst = gsm_modem_data.gpio_cp_reset; + unsigned gpio_pda_active = gsm_modem_data.gpio_pda_active; + unsigned gpio_phone_active = gsm_modem_data.gpio_phone_active; + unsigned gpio_flm_uart_sel = gsm_modem_data.gpio_flm_uart_sel; + unsigned gpio_dpram_int = gsm_modem_data.gpio_dpram_int; + + pr_err("[MODEMS] <%s>\n", __func__); + + if (gpio_pda_active) { + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "PDA_ACTIVE", gpio_pda_active, err); + } else { + gpio_direction_output(gpio_pda_active, 1); + s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_pda_active, 0); + } + } + + if (gpio_phone_active) { + err = gpio_request(gpio_phone_active, "ESC_ACTIVE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_ACTIVE", gpio_phone_active, err); + } else { + s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH); + } + } + + if (gpio_flm_uart_sel) { + err = gpio_request(gpio_flm_uart_sel, "BOOT_SW_SEL2"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "BOOT_SW_SEL2", gpio_flm_uart_sel, err); + } else { + gpio_direction_output(gpio_flm_uart_sel, 1); + s3c_gpio_setpull(gpio_flm_uart_sel, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_flm_uart_sel, 1); + } + } + + if (gpio_cp_on) { + err = gpio_request(gpio_cp_on, "ESC_ON"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_ON", gpio_cp_on, err); + } else { + gpio_direction_output(gpio_cp_on, 0); + s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio_cp_on, S5P_GPIO_DRVSTR_LV1); + gpio_set_value(gpio_cp_on, 0); + } + } + + if (gpio_cp_off) { + err = gpio_request(gpio_cp_off, "ESC_OFF"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_OFF", (gpio_cp_off), err); + } else { + gpio_direction_output(gpio_cp_off, 1); + s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_cp_off, 1); + } + } + + if (gpio_rst_req_n) { + err = gpio_request(gpio_rst_req_n, "ESC_RST_REQ"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_RST_REQ", gpio_rst_req_n, err); + } else { + gpio_direction_output(gpio_rst_req_n, 1); + s3c_gpio_setpull(gpio_rst_req_n, S3C_GPIO_PULL_NONE); + } + gpio_set_value(gpio_rst_req_n, 0); + } + + if (gpio_cp_rst) { + err = gpio_request(gpio_cp_rst, "ESC_RST"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_RST", gpio_cp_rst, err); + } else { + gpio_direction_output(gpio_cp_rst, 0); + s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio_cp_rst, S5P_GPIO_DRVSTR_LV4); + } + gpio_set_value(gpio_cp_rst, 0); + } + + if (gpio_dpram_int) { + err = gpio_request(gpio_dpram_int, "ESC_DPRAM_INT"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_DPRAM_INT", gpio_dpram_int, err); + } else { + /* Configure as a wake-up source */ + s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE); + } + } + + err = gpio_request(EXYNOS4_GPA1(4), "AP_CP2_UART_RXD"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "AP_CP2_UART_RXD", EXYNOS4_GPA1(4), err); + } else { + s3c_gpio_cfgpin(EXYNOS4_GPA1(4), S3C_GPIO_SFN(0x2)); + s3c_gpio_setpull(EXYNOS4_GPA1(4), S3C_GPIO_PULL_NONE); + } + + err = gpio_request(EXYNOS4_GPA1(5), "AP_CP2_UART_TXD"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "AP_CP2_UART_TXD", EXYNOS4_GPA1(5), err); + } else { + s3c_gpio_cfgpin(EXYNOS4_GPA1(5), S3C_GPIO_SFN(0x2)); + s3c_gpio_setpull(EXYNOS4_GPA1(5), S3C_GPIO_PULL_NONE); + } +} + +static u8 *gsm_edpram_remap_mem_region(struct sromc_cfg *cfg) +{ + int dp_addr = 0; + int dp_size = 0; + u8 __iomem *dp_base = NULL; + struct msm_edpram_ipc_cfg *ipc_map = NULL; + struct dpram_ipc_device *dev = NULL; + + dp_addr = cfg->addr; + dp_size = cfg->size; + dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size); + if (!dp_base) { + pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__); + return NULL; + } + pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base); + + gsm_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; + gsm_edpram_ctrl.dp_size = dp_size; + + /* Map for IPC */ + ipc_map = (struct msm_edpram_ipc_cfg *)dp_base; + + /* Magic code and access enable fields */ + gsm_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; + gsm_ipc_map.access = (u16 __iomem *)&ipc_map->access; + + /* FMT */ + dev = &gsm_ipc_map.dev[IPC_FMT]; + + strcpy(dev->name, "FMT"); + dev->id = IPC_FMT; + + dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; + dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; + dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; + dev->txq.size = MSM_DP_FMT_TX_BUFF_SZ; + + dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; + dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; + dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; + dev->rxq.size = MSM_DP_FMT_RX_BUFF_SZ; + + dev->mask_req_ack = INT_MASK_REQ_ACK_F; + dev->mask_res_ack = INT_MASK_RES_ACK_F; + dev->mask_send = INT_MASK_SEND_F; + + /* RAW */ + dev = &gsm_ipc_map.dev[IPC_RAW]; + + strcpy(dev->name, "RAW"); + dev->id = IPC_RAW; + + dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; + dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; + dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; + dev->txq.size = MSM_DP_RAW_TX_BUFF_SZ; + + dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; + dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; + dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; + dev->rxq.size = MSM_DP_RAW_RX_BUFF_SZ; + + dev->mask_req_ack = INT_MASK_REQ_ACK_R; + dev->mask_res_ack = INT_MASK_RES_ACK_R; + dev->mask_send = INT_MASK_SEND_R; + + /* Mailboxes */ + gsm_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; + gsm_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; + + return dp_base; +} +#endif + + +static int __init init_modem(void) +{ +#if defined(CONFIG_GSM_MODEM_ESC6270) + struct sromc_cfg *cfg = NULL; + struct sromc_access_cfg *acc_cfg = NULL; +#endif + int ret; + pr_info(LOG_TAG "init_modem, system_rev = %d\n", system_rev); + + /* umts gpios configuration */ + umts_modem_cfg_gpio(); + modem_link_pm_config_gpio(); + ret = platform_device_register(&umts_modem); + if (ret < 0) + return ret; + + /* For ESC6270 modem */ +#if defined(CONFIG_GSM_MODEM_ESC6270) + config_dpram_port_gpio(); + init_sromc(); + + gsm_edpram_cfg.csn = 1; + gsm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * gsm_edpram_cfg.csn); + gsm_edpram_cfg.end = gsm_edpram_cfg.addr + gsm_edpram_cfg.size - 1; + + config_gsm_modem_gpio(); + + cfg = &gsm_edpram_cfg; + acc_cfg = &gsm_edpram_access_cfg[DPRAM_SPEED_LOW]; + setup_sromc(cfg->csn, cfg, acc_cfg); + + if (!gsm_edpram_remap_mem_region(&gsm_edpram_cfg)) + return -1; + + platform_device_register(&gsm_modem); +#endif + + return ret; +} +late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/board-jenga-modems.c b/arch/arm/mach-exynos/board-jenga-modems.c deleted file mode 100644 index 8071df1..0000000 --- a/arch/arm/mach-exynos/board-jenga-modems.c +++ /dev/null @@ -1,429 +0,0 @@ -/* linux/arch/arm/mach-xxxx/board-m0-modems.c - * Copyright (C) 2010 Samsung Electronics. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Modem configuraiton for M0 (P-Q + XMM6262)*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <mach/gpio-exynos4.h> -#include <plat/gpio-cfg.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/delay.h> - -#include <linux/platform_data/modem.h> - -/* umts target platform data */ -static struct modem_io_t umts_io_devices[] = { - [0] = { - .name = "umts_ipc0", - .id = 0x1, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [1] = { - .name = "umts_rfs0", - .id = 0x41, - .format = IPC_RFS, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [2] = { - .name = "umts_boot0", - .id = 0x0, - .format = IPC_BOOT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [3] = { - .name = "multipdp", - .id = 0x1, - .format = IPC_MULTI_RAW, - .io_type = IODEV_DUMMY, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [4] = { - .name = "rmnet0", - .id = 0x2A, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [5] = { - .name = "rmnet1", - .id = 0x2B, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [6] = { - .name = "rmnet2", - .id = 0x2C, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [7] = { - .name = "umts_router", - .id = 0x39, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [8] = { - .name = "umts_csd", - .id = 0x21, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [9] = { - .name = "umts_ramdump0", - .id = 0x0, - .format = IPC_RAMDUMP, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [10] = { - .name = "umts_loopback0", - .id = 0x3f, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, -}; - -/* To get modem state, register phone active irq using resource */ -static struct resource umts_modem_res[] = { -}; - -static int umts_link_ldo_enble(bool enable) -{ - /* Exynos HSIC V1.2 LDO was controlled by kernel */ - return 0; -} - -static int umts_link_reconnect(void); -static struct modemlink_pm_data modem_link_pm_data = { - .name = "link_pm", - .link_ldo_enable = umts_link_ldo_enble, - .gpio_link_enable = 0, - .gpio_link_active = GPIO_ACTIVE_STATE, - .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, - .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, - .link_reconnect = umts_link_reconnect, -}; - -static struct modemlink_pm_link_activectl active_ctl; - -static void xmm_gpio_revers_bias_clear(void); -static void xmm_gpio_revers_bias_restore(void); -static struct modem_data umts_modem_data = { - .name = "xmm6262", - - .gpio_cp_on = GPIO_PHONE_ON, - .gpio_reset_req_n = GPIO_CP_REQ_RESET, - .gpio_cp_reset = GPIO_CP_RST, - .gpio_pda_active = GPIO_PDA_ACTIVE, - .gpio_phone_active = GPIO_PHONE_ACTIVE, - .gpio_cp_dump_int = GPIO_CP_DUMP_INT, - .gpio_flm_uart_sel = 0, - .gpio_cp_warm_reset = 0, - - .modem_type = IMC_XMM6262, - .link_types = LINKTYPE(LINKDEV_HSIC), - .modem_net = UMTS_NETWORK, - .use_handover = false, - - .num_iodevs = ARRAY_SIZE(umts_io_devices), - .iodevs = umts_io_devices, - - .link_pm_data = &modem_link_pm_data, - .gpio_revers_bias_clear = xmm_gpio_revers_bias_clear, - .gpio_revers_bias_restore = xmm_gpio_revers_bias_restore, -}; - -/* HSIC specific function */ -void set_slave_wake(void) -{ - int spin = 20; - if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) { - pr_err(LOG_TAG "Send Slave Wake\n"); - gpio_direction_output( - modem_link_pm_data.gpio_link_slavewake, 1); - mdelay(5); - gpio_direction_output( - modem_link_pm_data.gpio_link_slavewake, 0); - while (spin--) { - if (!gpio_get_value( - modem_link_pm_data.gpio_link_hostwake)) - break; - mdelay(5); - } - } -} - -void set_host_states(struct platform_device *pdev, int type) -{ - if (active_ctl.gpio_initialized) { - if (type) - set_slave_wake(); - pr_err(LOG_TAG "Active States =%d, %s\n", type, pdev->name); - gpio_direction_output(modem_link_pm_data.gpio_link_active, - type); - } else - active_ctl.gpio_request_host_active = 1; -} - -static int umts_link_reconnect(void) -{ - if (gpio_get_value(umts_modem_data.gpio_phone_active) && - gpio_get_value(umts_modem_data.gpio_cp_reset)) { - pr_info("[MODEM_IF] trying reconnect link\n"); - gpio_set_value(modem_link_pm_data.gpio_link_active, 0); - mdelay(10); - set_slave_wake(); - gpio_set_value(modem_link_pm_data.gpio_link_active, 1); - } else - return -ENODEV; - - return 0; -} - -/* if use more than one modem device, then set id num */ -static struct platform_device umts_modem = { - .name = "modem_if", - .id = -1, - .num_resources = ARRAY_SIZE(umts_modem_res), - .resource = umts_modem_res, - .dev = { - .platform_data = &umts_modem_data, - }, -}; - -static void umts_modem_cfg_gpio(void) -{ - int err = 0; - - unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n; - unsigned gpio_cp_on = umts_modem_data.gpio_cp_on; - unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset; - unsigned gpio_pda_active = umts_modem_data.gpio_pda_active; - unsigned gpio_phone_active = umts_modem_data.gpio_phone_active; - unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int; - unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel; - unsigned irq_phone_active = umts_modem_res[0].start; - - if (gpio_reset_req_n) { - err = gpio_request(gpio_reset_req_n, "RESET_REQ_N"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "RESET_REQ_N", err); - } - gpio_direction_output(gpio_reset_req_n, 0); - } - - if (gpio_cp_on) { - err = gpio_request(gpio_cp_on, "CP_ON"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "CP_ON", err); - } - gpio_direction_output(gpio_cp_on, 0); - } - - if (gpio_cp_rst) { - err = gpio_request(gpio_cp_rst, "CP_RST"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "CP_RST", err); - } - gpio_direction_output(gpio_cp_rst, 0); - } - - if (gpio_pda_active) { - err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "PDA_ACTIVE", err); - } - gpio_direction_output(gpio_pda_active, 0); - } - - if (gpio_phone_active) { - err = gpio_request(gpio_phone_active, "PHONE_ACTIVE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "PHONE_ACTIVE", err); - } - gpio_direction_input(gpio_phone_active); - pr_err(LOG_TAG "check phone active = %d\n", irq_phone_active); - } - - if (gpio_cp_dump_int) { - err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "CP_DUMP_INT", err); - } - gpio_direction_input(gpio_cp_dump_int); - } - - if (gpio_flm_uart_sel) { - err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "GPS_UART_SEL", err); - } - gpio_direction_output(gpio_reset_req_n, 0); - } - - if (gpio_phone_active) - irq_set_irq_type(gpio_to_irq(gpio_phone_active), - IRQ_TYPE_LEVEL_HIGH); - /* set low unused gpios between AP and CP */ - err = gpio_request(GPIO_FLM_RXD, "FLM_RXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD", - err); - else { - gpio_direction_output(GPIO_FLM_RXD, 0); - s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); - } - err = gpio_request(GPIO_FLM_TXD, "FLM_TXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD", - err); - else { - gpio_direction_output(GPIO_FLM_TXD, 0); - s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); - } - err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ", - err); - else { - gpio_direction_output(GPIO_SUSPEND_REQUEST, 0); - s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE); - } - err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL", - err); - else { - gpio_direction_output(GPIO_GPS_CNTL, 0); - s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE); - } - - pr_info(LOG_TAG "umts_modem_cfg_gpio done\n"); -} - -static void xmm_gpio_revers_bias_clear(void) -{ - gpio_direction_output(umts_modem_data.gpio_pda_active, 0); - gpio_direction_output(umts_modem_data.gpio_phone_active, 0); - gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0); - gpio_direction_output(modem_link_pm_data.gpio_link_active, 0); - gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0); - gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0); - - msleep(20); -} - -static void xmm_gpio_revers_bias_restore(void) -{ - s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF)); - s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake, - S3C_GPIO_SFN(0xF)); - gpio_direction_input(umts_modem_data.gpio_cp_dump_int); -} - -static void modem_link_pm_config_gpio(void) -{ - int err = 0; - - unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable; - unsigned gpio_link_active = modem_link_pm_data.gpio_link_active; - unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake; - unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake; - /* unsigned irq_link_hostwake = umts_modem_res[1].start; */ - - if (gpio_link_enable) { - err = gpio_request(gpio_link_enable, "LINK_EN"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "LINK_EN", err); - } - gpio_direction_output(gpio_link_enable, 0); - } - - if (gpio_link_active) { - err = gpio_request(gpio_link_active, "LINK_ACTIVE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "LINK_ACTIVE", err); - } - gpio_direction_output(gpio_link_active, 0); - } - - if (gpio_link_hostwake) { - err = gpio_request(gpio_link_hostwake, "HOSTWAKE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "HOSTWAKE", err); - } - gpio_direction_input(gpio_link_hostwake); - } - - if (gpio_link_slavewake) { - err = gpio_request(gpio_link_slavewake, "SLAVEWAKE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "SLAVEWAKE", err); - } - gpio_direction_output(gpio_link_slavewake, 0); - } - - if (gpio_link_hostwake) - irq_set_irq_type(gpio_to_irq(gpio_link_hostwake), - IRQ_TYPE_EDGE_BOTH); - - active_ctl.gpio_initialized = 1; - if (active_ctl.gpio_request_host_active) { - pr_err(LOG_TAG "Active States = 1, %s\n", __func__); - gpio_direction_output(modem_link_pm_data.gpio_link_active, 1); - } - - - pr_info(LOG_TAG "modem_link_pm_config_gpio done\n"); -} - -static int __init init_modem(void) -{ - int ret; - pr_info(LOG_TAG "init_modem\n"); - - /* umts gpios configuration */ - umts_modem_cfg_gpio(); - modem_link_pm_config_gpio(); - ret = platform_device_register(&umts_modem); - if (ret < 0) - return ret; - - return ret; -} -late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/board-m0-modems.c b/arch/arm/mach-exynos/board-m0-modems.c index 76e9ab9..4139c79 100644 --- a/arch/arm/mach-exynos/board-m0-modems.c +++ b/arch/arm/mach-exynos/board-m0-modems.c @@ -17,12 +17,16 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/irq.h> +#include <linux/interrupt.h> #include <linux/gpio.h> #include <mach/gpio-exynos4.h> #include <plat/gpio-cfg.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/delay.h> +#include <linux/usb.h> +#include <linux/usb/hcd.h> +#include <linux/usb/ehci_def.h> #include <linux/platform_data/modem.h> #include <mach/sec_modem.h> @@ -131,6 +135,81 @@ static int umts_link_ldo_enble(bool enable) return 0; } +#ifdef EHCI_REG_DUMP +struct dump_ehci_regs { + unsigned caps_hc_capbase; + unsigned caps_hcs_params; + unsigned caps_hcc_params; + unsigned reserved0; + struct ehci_regs regs; + unsigned port_usb; /*0x54*/ + unsigned port_hsic0; + unsigned port_hsic1; + unsigned reserved[12]; + unsigned insnreg00; /*0x90*/ + unsigned insnreg01; + unsigned insnreg02; + unsigned insnreg03; + unsigned insnreg04; + unsigned insnreg05; + unsigned insnreg06; + unsigned insnreg07; +}; + +struct s5p_ehci_hcd_stub { + struct device *dev; + struct usb_hcd *hcd; + struct clk *clk; + int power_on; +}; +/* for EHCI register dump */ +struct dump_ehci_regs sec_debug_ehci_regs; + +#define pr_hcd(s, r) printk(KERN_DEBUG "hcd reg(%s):\t 0x%08x\n", s, r) +static void print_ehci_regs(struct dump_ehci_regs *base) +{ + pr_hcd("HCCPBASE", base->caps_hc_capbase); + pr_hcd("HCSPARAMS", base->caps_hcs_params); + pr_hcd("HCCPARAMS", base->caps_hcc_params); + pr_hcd("USBCMD", base->regs.command); + pr_hcd("USBSTS", base->regs.status); + pr_hcd("USBINTR", base->regs.intr_enable); + pr_hcd("FRINDEX", base->regs.frame_index); + pr_hcd("CTRLDSSEGMENT", base->regs.segment); + pr_hcd("PERIODICLISTBASE", base->regs.frame_list); + pr_hcd("ASYNCLISTADDR", base->regs.async_next); + pr_hcd("CONFIGFLAG", base->regs.configured_flag); + pr_hcd("PORT0 Status/Control", base->port_usb); + pr_hcd("PORT1 Status/Control", base->port_hsic0); + pr_hcd("PORT2 Status/Control", base->port_hsic1); + pr_hcd("INSNREG00", base->insnreg00); + pr_hcd("INSNREG01", base->insnreg01); + pr_hcd("INSNREG02", base->insnreg02); + pr_hcd("INSNREG03", base->insnreg03); + pr_hcd("INSNREG04", base->insnreg04); + pr_hcd("INSNREG05", base->insnreg05); + pr_hcd("INSNREG06", base->insnreg06); + pr_hcd("INSNREG07", base->insnreg07); +} + +static void debug_ehci_reg_dump(struct device *hdev) +{ + struct s5p_ehci_hcd_stub *s5p_ehci = dev_get_drvdata(hdev); + struct usb_hcd *hcd = s5p_ehci->hcd; + char *buf = (char *)&sec_debug_ehci_regs; + + if (s5p_ehci->power_on && hcd) { + memcpy(buf, hcd->regs, 0xB); + memcpy(buf + 0x10, hcd->regs + 0x10, 0x1F); + memcpy(buf + 0x50, hcd->regs + 0x50, 0xF); + memcpy(buf + 0x90, hcd->regs + 0x90, 0x1F); + print_ehci_regs(hcd->regs); + } +} +#else +#define debug_ehci_reg_dump (NULL) +#endif + static int umts_link_reconnect(void); static struct modemlink_pm_data modem_link_pm_data = { .name = "link_pm", @@ -140,6 +219,7 @@ static struct modemlink_pm_data modem_link_pm_data = { .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, .link_reconnect = umts_link_reconnect, + .ehci_reg_dump = debug_ehci_reg_dump, }; static struct modemlink_pm_link_activectl active_ctl; @@ -147,9 +227,6 @@ static struct modemlink_pm_link_activectl active_ctl; static void xmm_gpio_revers_bias_clear(void); static void xmm_gpio_revers_bias_restore(void); -#ifndef GPIO_AP_DUMP_INT -#define GPIO_AP_DUMP_INT 0 -#endif static struct modem_data umts_modem_data = { .name = "xmm6262", @@ -159,10 +236,22 @@ static struct modem_data umts_modem_data = { .gpio_pda_active = GPIO_PDA_ACTIVE, .gpio_phone_active = GPIO_PHONE_ACTIVE, .gpio_cp_dump_int = GPIO_CP_DUMP_INT, +#ifdef GPIO_AP_DUMP_INT .gpio_ap_dump_int = GPIO_AP_DUMP_INT, +#endif .gpio_flm_uart_sel = 0, .gpio_cp_warm_reset = 0, +#ifdef CONFIG_SEC_DUAL_MODEM_MODE + .gpio_sim_io_sel = GPIO_SIM_IO_SEL, + .gpio_cp_ctrl1 = GPIO_CP_CTRL1, + .gpio_cp_ctrl2 = GPIO_CP_CTRL2, +#endif + +#ifdef GPIO_SIM_DETECT + .gpio_sim_detect = GPIO_SIM_DETECT, +#endif + .modem_type = IMC_XMM6262, .link_types = LINKTYPE(LINKDEV_HSIC), .modem_net = UMTS_NETWORK, @@ -266,10 +355,11 @@ static int umts_link_reconnect(void) return 0; } + /* if use more than one modem device, then set id num */ static struct platform_device umts_modem = { .name = "modem_if", - .id = -1, + .id = 1, .num_resources = ARRAY_SIZE(umts_modem_res), .resource = umts_modem_res, .dev = { @@ -289,7 +379,14 @@ static void umts_modem_cfg_gpio(void) unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int; unsigned gpio_ap_dump_int = umts_modem_data.gpio_ap_dump_int; unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel; - /* unsigned irq_phone_active = umts_modem_res[0].start; */ + unsigned gpio_sim_detect = umts_modem_data.gpio_sim_detect; + //unsigned irq_phone_active = umts_modem_res[0].start; + +#ifdef CONFIG_SEC_DUAL_MODEM_MODE + unsigned gpio_sim_io_sel = umts_modem_data.gpio_sim_io_sel; + unsigned gpio_cp_ctrl1 = umts_modem_data.gpio_cp_ctrl1; + unsigned gpio_cp_ctrl2 = umts_modem_data.gpio_cp_ctrl2; +#endif if (gpio_reset_req_n) { err = gpio_request(gpio_reset_req_n, "RESET_REQ_N"); @@ -339,6 +436,19 @@ static void umts_modem_cfg_gpio(void) pr_err(LOG_TAG "check phone active = %d\n", gpio_phone_active); } + if (gpio_sim_detect) { + err = gpio_request(gpio_sim_detect, "SIM_DETECT"); + if (err) + printk(KERN_ERR "fail to request gpio %s: %d\n", + "SIM_DETECT", err); + + /* gpio_direction_input(gpio_sim_detect); */ + s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_to_irq(gpio_sim_detect), + IRQ_TYPE_EDGE_BOTH); + } + if (gpio_cp_dump_int) { err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT"); if (err) { @@ -348,7 +458,7 @@ static void umts_modem_cfg_gpio(void) gpio_direction_input(gpio_cp_dump_int); } - if (gpio_ap_dump_int /*&& system_rev >= 11*/) { /* MO rev1.0*/ + if (gpio_ap_dump_int) { err = gpio_request(gpio_ap_dump_int, "AP_DUMP_INT"); if (err) { pr_err(LOG_TAG "fail to request gpio %s : %d\n", @@ -370,22 +480,6 @@ static void umts_modem_cfg_gpio(void) irq_set_irq_type(gpio_to_irq(gpio_phone_active), IRQ_TYPE_LEVEL_HIGH); /* set low unused gpios between AP and CP */ - err = gpio_request(GPIO_FLM_RXD, "FLM_RXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD", - err); - else { - gpio_direction_output(GPIO_FLM_RXD, 0); - s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); - } - err = gpio_request(GPIO_FLM_TXD, "FLM_TXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD", - err); - else { - gpio_direction_output(GPIO_FLM_TXD, 0); - s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); - } err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ"); if (err) pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ", @@ -394,15 +488,6 @@ static void umts_modem_cfg_gpio(void) gpio_direction_output(GPIO_SUSPEND_REQUEST, 0); s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE); } - err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL", - err); - else { - gpio_direction_output(GPIO_GPS_CNTL, 0); - s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE); - } - pr_info(LOG_TAG "umts_modem_cfg_gpio done\n"); } @@ -415,15 +500,29 @@ static void xmm_gpio_revers_bias_clear(void) gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0); gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0); + if (umts_modem_data.gpio_sim_detect) + gpio_direction_output(umts_modem_data.gpio_sim_detect, 0); + msleep(20); } static void xmm_gpio_revers_bias_restore(void) { + unsigned gpio_sim_detect = umts_modem_data.gpio_sim_detect; + s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF)); s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake, S3C_GPIO_SFN(0xF)); gpio_direction_input(umts_modem_data.gpio_cp_dump_int); + + if (gpio_sim_detect) { + gpio_direction_input(gpio_sim_detect); + s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_to_irq(gpio_sim_detect), + IRQ_TYPE_EDGE_BOTH); + enable_irq_wake(gpio_to_irq(gpio_sim_detect)); + } } static void modem_link_pm_config_gpio(void) @@ -481,6 +580,20 @@ static void modem_link_pm_config_gpio(void) pr_info(LOG_TAG "modem_link_pm_config_gpio done\n"); } +static void board_set_simdetect_polarity(void) +{ + if (umts_modem_data.gpio_sim_detect) { +#if defined(CONFIG_MACH_GC1) + if (system_rev >= 6) /* GD1 3G real B'd*/ + umts_modem_data.sim_polarity = 1; + else + umts_modem_data.sim_polarity = 0; +#else + umts_modem_data.sim_polarity = 0; +#endif + } +} + static int __init init_modem(void) { int ret; @@ -489,9 +602,10 @@ static int __init init_modem(void) /* umts gpios configuration */ umts_modem_cfg_gpio(); modem_link_pm_config_gpio(); + board_set_simdetect_polarity(); ret = platform_device_register(&umts_modem); if (ret < 0) - return ret; + pr_err("(%s) register fail\n", umts_modem.name); return ret; } diff --git a/arch/arm/mach-exynos/board-m0-td-modems.c b/arch/arm/mach-exynos/board-m0-td-modems.c index f98a66b..9ef2d81 100644 --- a/arch/arm/mach-exynos/board-m0-td-modems.c +++ b/arch/arm/mach-exynos/board-m0-td-modems.c @@ -1,292 +1,320 @@ +/* linux/arch/arm/mach-xxxx/board-m0-td-modems.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Modem configuraiton for M0 CMCC (P-Q + SPRD8803)*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> #include <linux/gpio.h> +#include <mach/gpio-exynos4.h> #include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <mach/regs-gpio.h> -#include <mach/gpio.h> -#include <mach/irqs.h> +#include <linux/clk.h> #include <linux/err.h> #include <linux/delay.h> -#include <linux/workqueue.h> -#include <linux/regulator/consumer.h> -#ifdef CONFIG_HAS_WAKELOCK -#include <linux/wakelock.h> + +#include <linux/platform_data/modem.h> +#include <mach/sec_modem.h> + +/* tdscdma target platform data */ +static struct modem_io_t tdscdma_io_devices[] = { + [0] = { + .name = "td_ipc0", + .id = 0x1, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_SPI), + }, + [1] = { + .name = "td_rfs0", + .id = 0x41, + .format = IPC_RFS, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_SPI), + }, + [2] = { + .name = "td_boot0", + .id = 0x0, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_SPI), + }, + [3] = { + .name = "td_multipdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_SPI), + }, + [4] = { +#ifdef CONFIG_SLP + .name = "pdp0", +#else + .name = "td_rmnet0", +#endif + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_SPI), + }, + [5] = { +#ifdef CONFIG_SLP + .name = "pdp1", +#else + .name = "td_rmnet1", +#endif + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_SPI), + }, + [6] = { +#ifdef CONFIG_SLP + .name = "pdp2", +#else + .name = "td_rmnet2", #endif -#include <linux/phone_svn/modemctl.h> + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_SPI), + }, + [7] = { + .name = "td_router", + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_SPI), + }, + [8] = { + .name = "td_csd", + .id = 0x21, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_SPI), + }, + [9] = { + .name = "td_ramdump0", + .id = 0x0, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_SPI), + }, + [10] = { + .name = "td_loopback0", + .id = 0x3f, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_SPI), + }, +}; -#define DEBUG +/* To get modem state, register phone active irq using resource */ +static struct resource tdscdma_modem_res[] = { +}; -static struct modemctl_platform_data mdmctl_data; -void modemctl_cfg_gpio(void) -{ - int err = 0; +static struct modem_data tdscdma_modem_data = { + .name = "sprd8803", + + .gpio_cp_on = GPIO_TD_PHONE_ON, + .gpio_pda_active = GPIO_TD_PDA_ACTIVE, + .gpio_phone_active = GPIO_TD_PHONE_ACTIVE, + .gpio_cp_dump_int = GPIO_TD_DUMP_INT, + .gpio_ap_cp_int1 = GPIO_AP_TD_INT1, + .gpio_ap_cp_int2 = GPIO_AP_TD_INT2, + .gpio_ipc_mrdy = GPIO_IPC_MRDY, + .gpio_ipc_srdy = GPIO_IPC_SRDY, + .gpio_ipc_sub_mrdy = GPIO_IPC_SUB_MRDY, + .gpio_ipc_sub_srdy = GPIO_IPC_SUB_SRDY, +#ifdef CONFIG_SEC_DUAL_MODEM_MODE + .gpio_sim_io_sel = GPIO_SIM_IO_SEL, + .gpio_cp_ctrl1 = GPIO_CP_CTRL1, + .gpio_cp_ctrl2 = GPIO_CP_CTRL2, +#endif + .modem_type = SPRD_SC8803, + .link_types = LINKTYPE(LINKDEV_SPI), + .modem_net = TDSCDMA_NETWORK, - unsigned gpio_phone_on = mdmctl_data.gpio_phone_on; - unsigned gpio_phone_active = mdmctl_data.gpio_phone_active; - unsigned gpio_cp_rst = mdmctl_data.gpio_cp_reset; - unsigned gpio_pda_active = mdmctl_data.gpio_pda_active; - unsigned gpio_cp_req_reset = mdmctl_data.gpio_cp_req_reset; - unsigned gpio_ipc_slave_wakeup = mdmctl_data.gpio_ipc_slave_wakeup; - unsigned gpio_ipc_host_wakeup = mdmctl_data.gpio_ipc_host_wakeup; - unsigned gpio_suspend_request = mdmctl_data.gpio_suspend_request; - unsigned gpio_active_state = mdmctl_data.gpio_active_state; - unsigned gpio_cp_dump_int = mdmctl_data.gpio_cp_dump_int; + .num_iodevs = ARRAY_SIZE(tdscdma_io_devices), + .iodevs = tdscdma_io_devices, +}; - /*TODO: check uart init func AP FLM BOOT RX -- */ - s3c_gpio_setpull(EXYNOS4_GPA1(4), S3C_GPIO_PULL_UP); +/* if use more than one modem device, then set id num */ +static struct platform_device tdscdma_modem = { + .name = "modem_if", + .id = 2, + .num_resources = ARRAY_SIZE(tdscdma_modem_res), + .resource = tdscdma_modem_res, + .dev = { + .platform_data = &tdscdma_modem_data, + }, +}; - err = gpio_request(gpio_phone_on, "PHONE_ON"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "PHONE_ON"); - } else { - gpio_direction_output(gpio_phone_on, 0); - s3c_gpio_setpull(gpio_phone_on, S3C_GPIO_PULL_NONE); - } - err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "PDA_ACTIVE"); - } else { - gpio_direction_output(gpio_pda_active, 0); - s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); - } -#if !defined(CONFIG_CHN_CMCC_SPI_SPRD) - err = gpio_request(gpio_cp_rst, "CP_RST"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "CP_RST"); - } else { - gpio_direction_output(gpio_cp_rst, 0); - s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); - } - err = gpio_request(gpio_cp_req_reset, "CP_REQ_RESET"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "CP_REQ_RESET"); - } else { - gpio_direction_output(gpio_cp_req_reset, 0); - s3c_gpio_setpull(gpio_cp_req_reset, S3C_GPIO_PULL_NONE); +static void tdscdma_modem_cfg_gpio(void) +{ + int err = 0; + + unsigned gpio_cp_on = tdscdma_modem_data.gpio_cp_on; + unsigned gpio_pda_active = tdscdma_modem_data.gpio_pda_active; + unsigned gpio_phone_active = tdscdma_modem_data.gpio_phone_active; + unsigned gpio_cp_dump_int = tdscdma_modem_data.gpio_cp_dump_int; + unsigned gpio_ipc_mrdy = tdscdma_modem_data.gpio_ipc_mrdy; + unsigned gpio_ipc_srdy = tdscdma_modem_data.gpio_ipc_srdy; + unsigned gpio_ipc_sub_mrdy = tdscdma_modem_data.gpio_ipc_sub_mrdy; + unsigned gpio_ipc_sub_srdy = tdscdma_modem_data.gpio_ipc_sub_srdy; +#ifdef CONFIG_SEC_DUAL_MODEM_MODE + unsigned gpio_sim_io_sel = tdscdma_modem_data.gpio_sim_io_sel; + unsigned gpio_cp_ctrl1 = tdscdma_modem_data.gpio_cp_ctrl1; + unsigned gpio_cp_ctrl2 = tdscdma_modem_data.gpio_cp_ctrl2; + + /* these 3 gpios need to set again before cp booting */ + if (gpio_sim_io_sel) { + err = gpio_request(gpio_sim_io_sel, "SIM_IO_SEL"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "SIM_IO_SEL", err); + } + gpio_direction_output(gpio_sim_io_sel, 0); } - err = gpio_request(gpio_ipc_slave_wakeup, "IPC_SLAVE_WAKEUP"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", - "IPC_SLAVE_WAKEUP"); - } else { - gpio_direction_output(gpio_ipc_slave_wakeup, 0); - s3c_gpio_setpull(gpio_ipc_slave_wakeup, S3C_GPIO_PULL_NONE); + if (gpio_cp_ctrl1) { + err = gpio_request(gpio_cp_ctrl1, "CP_CTRL1"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "CP_CTRL1", err); + } + gpio_direction_output(gpio_cp_ctrl1, 0); } - err = gpio_request(gpio_ipc_host_wakeup, "IPC_HOST_WAKEUP"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "IPC_HOST_WAKEUP"); - } else { - gpio_direction_output(gpio_ipc_host_wakeup, 0); - s3c_gpio_cfgpin(gpio_ipc_host_wakeup, S3C_GPIO_SFN(0xF)); - s3c_gpio_setpull(gpio_ipc_host_wakeup, S3C_GPIO_PULL_NONE); + if (gpio_cp_ctrl2) { + err = gpio_request(gpio_cp_ctrl2, "CP_CTRL2"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "CP_CTRL2", err); + } + gpio_direction_output(gpio_cp_ctrl2, 0); } +#endif + /*TODO: check uart init func AP FLM BOOT RX -- */ + s3c_gpio_setpull(EXYNOS4_GPA1(4), S3C_GPIO_PULL_UP); - err = gpio_request(gpio_suspend_request, "SUSPEND_REQUEST"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "SUSPEND_REQUEST"); - } else { - gpio_direction_input(gpio_suspend_request); - s3c_gpio_setpull(gpio_suspend_request, S3C_GPIO_PULL_NONE); + if (gpio_cp_on) { + err = gpio_request(gpio_cp_on, "CP_ON"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "CP_ON", err); + } + gpio_direction_output(gpio_cp_on, 0); } - err = gpio_request(gpio_active_state, "ACTIVE_STATE"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "ACTIVE_STATE"); - } else { - gpio_direction_output(gpio_active_state, 0); - s3c_gpio_setpull(gpio_active_state, S3C_GPIO_PULL_NONE); + if (gpio_pda_active) { + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "PDA_ACTIVE", err); + } + gpio_direction_output(gpio_pda_active, 0); } -#endif - err = gpio_request(gpio_phone_active, "PHONE_ACTIVE"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "PHONE_ACTIVE"); - } else { + + if (gpio_phone_active) { + err = gpio_request(gpio_phone_active, "PHONE_ACTIVE"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "PHONE_ACTIVE", err); + } gpio_direction_input(gpio_phone_active); - s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_DOWN); } - err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT"); - if (err) { - printk(KERN_ERR "fail to request gpio %s\n", "CP_DUMP_INT"); - } else { + if (gpio_cp_dump_int) { + err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT"); + if (err) { + pr_err(LOG_TAG "fail to request gpio %s : %d\n", + "CP_DUMP_INT", err); + } gpio_direction_input(gpio_cp_dump_int); - s3c_gpio_cfgpin(gpio_cp_dump_int, S3C_GPIO_SFN(0xF)); s3c_gpio_setpull(gpio_cp_dump_int, S3C_GPIO_PULL_DOWN); } -} -static void xmm6260_vcc_init(struct modemctl *mc) -{ - int err; - - if (!mc->vcc) { - mc->vcc = regulator_get(NULL, "vhsic"); - if (IS_ERR(mc->vcc)) { - err = PTR_ERR(mc->vcc); - dev_dbg(mc->dev, "No VHSIC_1.2V regualtor: %d\n", err); - mc->vcc = NULL; + if (gpio_phone_active) + irq_set_irq_type(gpio_to_irq(gpio_phone_active), + IRQ_TYPE_EDGE_BOTH); + + if (gpio_ipc_mrdy) { + err = gpio_request(gpio_ipc_mrdy, "IPC_MRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_MRDY", err); + } else { + gpio_direction_output(gpio_ipc_mrdy, 0); } } - if (mc->vcc) - regulator_enable(mc->vcc); -} - -static void xmm6260_vcc_off(struct modemctl *mc) -{ - if (mc->vcc) - regulator_disable(mc->vcc); -} - -static void xmm6260_on(struct modemctl *mc) -{ - dev_dbg(mc->dev, "%s\n", __func__); - if (!mc->gpio_cp_reset || !mc->gpio_phone_on || !mc->gpio_cp_req_reset) - return; -#if defined(CONFIG_CHN_CMCC_SPI_SPRD) - gpio_set_value(mc->gpio_cp_req_reset, 0); - gpio_set_value(mc->gpio_pda_active, 0); - gpio_set_value(mc->gpio_phone_on, 0); - msleep(100); - gpio_set_value(mc->gpio_phone_on, 1); - gpio_set_value(mc->gpio_pda_active, 1); -#else - xmm6260_vcc_init(mc); - - gpio_set_value(mc->gpio_phone_on, 0); - gpio_set_value(mc->gpio_cp_reset, 0); - udelay(160); - - gpio_set_value(mc->gpio_pda_active, 0); - gpio_set_value(mc->gpio_active_state, 0); - msleep(100); - - gpio_set_value(mc->gpio_cp_reset, 1); - udelay(160); - gpio_set_value(mc->gpio_cp_req_reset, 1); - udelay(160); - - gpio_set_value(mc->gpio_phone_on, 1); - - msleep(20); - gpio_set_value(mc->gpio_active_state, 1); - gpio_set_value(mc->gpio_pda_active, 1); -#endif -} + if (gpio_ipc_srdy) { + err = gpio_request(gpio_ipc_srdy, "IPC_SRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_SRDY", err); + } else { + gpio_direction_input(gpio_ipc_srdy); + s3c_gpio_cfgpin(gpio_ipc_srdy, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_ipc_srdy, S3C_GPIO_PULL_DOWN); + + irq_set_irq_type(gpio_to_irq(gpio_ipc_srdy), + IRQ_TYPE_EDGE_RISING); + } + } -static void xmm6260_off(struct modemctl *mc) -{ - dev_dbg(mc->dev, "%s\n", __func__); - if (!mc->gpio_cp_reset || !mc->gpio_phone_on) - return; + if (gpio_ipc_sub_mrdy) { + err = gpio_request(gpio_ipc_sub_mrdy, "IPC_SUB_MRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_SUB_MRDY", err); + } else { + gpio_direction_output(gpio_ipc_sub_mrdy, 0); + } + } - gpio_set_value(mc->gpio_phone_on, 0); - gpio_set_value(mc->gpio_cp_reset, 0); + if (gpio_ipc_sub_srdy) { + err = gpio_request(gpio_ipc_sub_srdy, "IPC_SUB_SRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_SUB_SRDY", err); + } else { + gpio_direction_input(gpio_ipc_sub_srdy); + s3c_gpio_cfgpin(gpio_ipc_sub_srdy, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_ipc_sub_srdy, S3C_GPIO_PULL_DOWN); + + irq_set_irq_type(gpio_to_irq(gpio_ipc_sub_srdy), + IRQ_TYPE_EDGE_RISING); + } + } - xmm6260_vcc_off(mc); + pr_info(LOG_TAG "tdscdma_modem_cfg_gpio done\n"); } -static void xmm6260_reset(struct modemctl *mc) +static int __init init_modem(void) { - dev_dbg(mc->dev, "%s\n", __func__); - if (!mc->gpio_cp_reset || !mc->gpio_cp_req_reset) - return; - -#if defined(CONFIG_CHN_CMCC_SPI_SPRD) - gpio_set_value(mc->gpio_cp_req_reset, 0); - msleep(100); - gpio_set_value(mc->gpio_cp_req_reset, 1); -#else -/* gpio_set_value(mc->gpio_pda_active, 0); - gpio_set_value(mc->gpio_active_state, 0);*/ - gpio_set_value(mc->gpio_cp_reset, 0); - gpio_set_value(mc->gpio_cp_req_reset, 0); + int ret; + pr_info(LOG_TAG "tdscdma init_modem\n"); - msleep(100); + /* tdscdma gpios configuration */ + tdscdma_modem_cfg_gpio(); + ret = platform_device_register(&tdscdma_modem); + if (ret < 0) + return ret; - gpio_set_value(mc->gpio_cp_reset, 1); - udelay(160); - gpio_set_value(mc->gpio_cp_req_reset, 1); -#endif -} - -/* move the PDA_ACTIVE Pin control to sleep_gpio_table */ -static void xmm6260_suspend(struct modemctl *mc) -{ - xmm6260_vcc_off(mc); -} - -static void xmm6260_resume(struct modemctl *mc) -{ - xmm6260_vcc_init(mc); + return ret; } - -#if defined(CONFIG_CHN_CMCC_SPI_SPRD) -static struct modemctl_platform_data mdmctl_data = { - .name = "xmm6260", - - .gpio_phone_on = GPIO_PHONE_ON, - .gpio_phone_active = GPIO_PHONE_ACTIVE, - .gpio_pda_active = GPIO_PDA_ACTIVE, - .gpio_cp_reset = GPIO_CP_RST, - .gpio_cp_req_reset = GPIO_AP_CP_INT2, - .gpio_ipc_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP, - .gpio_ipc_host_wakeup = GPIO_IPC_HOST_WAKEUP, - .gpio_suspend_request = GPIO_SUSPEND_REQUEST, - .gpio_active_state = GPIO_ACTIVE_STATE, - .gpio_cp_dump_int = GPIO_CP_DUMP_INT, - - .ops = { - .modem_on = xmm6260_on, - .modem_off = xmm6260_off, - .modem_reset = xmm6260_reset, - .modem_suspend = xmm6260_suspend, - .modem_resume = xmm6260_resume, - .modem_cfg_gpio = modemctl_cfg_gpio, - } -}; -#else -static struct modemctl_platform_data mdmctl_data = { - .name = "xmm6260", - .gpio_phone_on = GPIO_PHONE_ON, - .gpio_phone_active = GPIO_PHONE_ACTIVE, - .gpio_pda_active = GPIO_PDA_ACTIVE, - .gpio_cp_reset = GPIO_CP_RST, - .gpio_cp_req_reset = GPIO_CP_REQ_RESET, - .gpio_ipc_slave_wakeup = GPIO_IPC_SLAVE_WAKEUP, - .gpio_ipc_host_wakeup = GPIO_IPC_HOST_WAKEUP, - .gpio_suspend_request = GPIO_SUSPEND_REQUEST, - .gpio_active_state = GPIO_ACTIVE_STATE, - .gpio_cp_dump_int = GPIO_CP_DUMP_INT, - .ops = { - .modem_on = xmm6260_on, - .modem_off = xmm6260_off, - .modem_reset = xmm6260_reset, - .modem_suspend = xmm6260_suspend, - .modem_resume = xmm6260_resume, - .modem_cfg_gpio = modemctl_cfg_gpio, - } -}; -#endif - -/* TODO: check the IRQs..... */ -static struct resource mdmctl_res[] = { - [0] = { - .start = IRQ_PHONE_ACTIVE, - .end = IRQ_PHONE_ACTIVE, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device modemctl = { - .name = "modemctl", - .id = -1, - .num_resources = ARRAY_SIZE(mdmctl_res), - .resource = mdmctl_res, - - .dev = { - .platform_data = &mdmctl_data, - }, -}; +late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/board-m0ctc-modems.c b/arch/arm/mach-exynos/board-m0ctc-modems.c index 3f69c69..27dbf6e 100644 --- a/arch/arm/mach-exynos/board-m0ctc-modems.c +++ b/arch/arm/mach-exynos/board-m0ctc-modems.c @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-xxxx/board-c1ctc-modems.c +/* linux/arch/arm/mach-xxxx/board-m0ctc-modems.c * Copyright (C) 2010 Samsung Electronics. All rights reserved. * * This software is licensed under the terms of the GNU General Public @@ -42,9 +42,19 @@ #include <plat/devs.h> #include <plat/ehci.h> +#if defined(CONFIG_LINK_DEVICE_PLD) +#include <linux/spi/spi.h> +#include <mach/pld_pdata.h> +#endif + #define SROM_CS0_BASE 0x04000000 #define SROM_WIDTH 0x01000000 + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define SROM_NUM_ADDR_BITS 15 +#else #define SROM_NUM_ADDR_BITS 14 +#endif /* * For SROMC Configuration: @@ -58,6 +68,7 @@ /* Memory attributes */ enum sromc_attr { + MEM_DATA_BUS_8BIT = 0x00000000, MEM_DATA_BUS_16BIT = 0x00000001, MEM_BYTE_ADDRESSABLE = 0x00000002, MEM_WAIT_EN = 0x00000004, @@ -86,7 +97,11 @@ struct sromc_access_cfg { }; /* For MDM6600 EDPRAM (External DPRAM) */ +#if defined(CONFIG_LINK_DEVICE_PLD) +#define MSM_EDPRAM_SIZE 0x10000 /* 8 KB */ +#else #define MSM_EDPRAM_SIZE 0x4000 /* 16 KB */ +#endif #define INT_MASK_REQ_ACK_F 0x0020 #define INT_MASK_REQ_ACK_R 0x0010 @@ -104,7 +119,6 @@ static void config_dpram_port_gpio(void); static void init_sromc(void); static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, struct sromc_access_cfg *acc_cfg); -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg); static int __init init_modem(void); #ifdef CONFIG_USBHUB_USB3503 @@ -116,23 +130,45 @@ static int host_port_enable(int port, int enable) } #endif +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct sromc_cfg msm_edpram_cfg = { + .attr = (MEM_DATA_BUS_8BIT), + .size = 0x10000, +}; +#else static struct sromc_cfg msm_edpram_cfg = { .attr = (MEM_DATA_BUS_16BIT | MEM_WAIT_EN | MEM_BYTE_EN), .size = MSM_EDPRAM_SIZE, }; +#endif +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct sromc_access_cfg msm_edpram_access_cfg[] = { + [DPRAM_SPEED_LOW] = { + .tacs = 0x2 << 28, + .tcos = 0x2 << 24, + .tacc = 0x3 << 16, + .tcoh = 0x2 << 12, + .tcah = 0x2 << 8, + .tacp = 0x3 << 4, + .pmc = 0x0 << 0, + }, +}; +#else static struct sromc_access_cfg msm_edpram_access_cfg[] = { [DPRAM_SPEED_LOW] = { - .tacs = 0x2 << 28, - .tcos = 0x2 << 24, - .tacc = 0x3 << 16, - .tcoh = 0x2 << 12, - .tcah = 0x2 << 8, - .tacp = 0x2 << 4, - .pmc = 0x0 << 0, - }, + .tacs = 0x2 << 28, + .tcos = 0x2 << 24, + .tacc = 0x3 << 16, + .tcoh = 0x2 << 12, + .tcah = 0x2 << 8, + .tacp = 0x2 << 4, + .pmc = 0x0 << 0, + }, }; +#endif +#if (MSM_EDPRAM_SIZE == 0x4000) /* magic_code + access_enable + @@ -187,23 +223,7 @@ struct msm_edpram_ipc_cfg { u16 mbx_cp2ap; }; -struct msm_edpram_boot_map { - u8 __iomem *buff; - u16 __iomem *frame_size; - u16 __iomem *tag; - u16 __iomem *count; -}; - -static struct dpram_ipc_map msm_ipc_map; - -struct _param_nv { - unsigned char *addr; - unsigned int size; - unsigned int count; - unsigned int tag; -}; -#if (MSM_EDPRAM_SIZE == 0x4000) /* ------------------ Buffer : 15KByte @@ -223,11 +243,85 @@ CP -> AP Intr : 2Byte */ #define DP_BOOT_CLEAR_OFFSET 4 #define DP_BOOT_RSRVD_OFFSET 0x3C00 -#define DP_BOOT_SIZE_OFFSET 0x3FF6 -#define DP_BOOT_TAG_OFFSET 0x3FF8 +#define DP_BOOT_SIZE_OFFSET 0x3FF6 +#define DP_BOOT_TAG_OFFSET 0x3FF8 #define DP_BOOT_COUNT_OFFSET 0x3FFA #define DP_BOOT_FRAME_SIZE_LIMIT 0x3C00 /* 15KB = 15360byte = 0x3C00 */ + +#elif (MSM_EDPRAM_SIZE == 0x10000) + +/* + mbx_ap2cp + 0x0 + magic_code + + access_enable + + padding + + mbx_cp2ap + 0x1000 + magic_code + + access_enable + + padding + + fmt_tx_head + fmt_tx_tail + fmt_tx_buff + 0x2000 + raw_tx_head + raw_tx_tail + raw_tx_buff + + fmt_rx_head + fmt_rx_tail + fmt_rx_buff + 0x3000 + raw_rx_head + raw_rx_tail + raw_rx_buff + + = 2 + + 4094 + + 2 + + 4094 + + 2 + + 2 + + 2 + 2 + 1020 + + 2 + 2 + 3064 + + 2 + 2 + 1020 + + 2 + 2 + 3064 + */ + +#define MSM_DP_FMT_TX_BUFF_SZ 1024 +#define MSM_DP_RAW_TX_BUFF_SZ 3072 +#define MSM_DP_FMT_RX_BUFF_SZ 1024 +#define MSM_DP_RAW_RX_BUFF_SZ 3072 + +#define MAX_MSM_EDPRAM_IPC_DEV 2 /* FMT, RAW */ + +struct msm_edpram_ipc_cfg { + u16 mbx_ap2cp; + u16 magic_ap2cp; + u16 access_ap2cp; + u16 fmt_tx_head; + u16 raw_tx_head; + u16 fmt_rx_tail; + u16 raw_rx_tail; + u16 temp1; + u8 padding1[4080]; + + u16 mbx_cp2ap; + u16 magic_cp2ap; + u16 access_cp2ap; + u16 fmt_tx_tail; + u16 raw_tx_tail; + u16 fmt_rx_head; + u16 raw_rx_head; + u16 temp2; + u8 padding2[4080]; + + u8 fmt_tx_buff[MSM_DP_FMT_TX_BUFF_SZ]; + u8 raw_tx_buff[MSM_DP_RAW_TX_BUFF_SZ]; + u8 fmt_rx_buff[MSM_DP_FMT_RX_BUFF_SZ]; + u8 raw_rx_buff[MSM_DP_RAW_RX_BUFF_SZ]; + + u8 padding3[16384]; + + u16 address_buffer; +}; + +#define DP_BOOT_CLEAR_OFFSET 0 +#define DP_BOOT_RSRVD_OFFSET 0 +#define DP_BOOT_SIZE_OFFSET 0x2 +#define DP_BOOT_TAG_OFFSET 0x4 +#define DP_BOOT_COUNT_OFFSET 0x6 + +#define DP_BOOT_FRAME_SIZE_LIMIT 0x1000 /* 15KB = 15360byte = 0x3C00 */ + #else /* ------------------ @@ -248,286 +342,339 @@ CP -> AP Intr : 2Byte */ #define DP_BOOT_CLEAR_OFFSET 4 #define DP_BOOT_RSRVD_OFFSET 0x7C00 -#define DP_BOOT_SIZE_OFFSET 0x7FF6 -#define DP_BOOT_TAG_OFFSET 0x7FF8 +#define DP_BOOT_SIZE_OFFSET 0x7FF6 +#define DP_BOOT_TAG_OFFSET 0x7FF8 #define DP_BOOT_COUNT_OFFSET 0x7FFA #define DP_BOOT_FRAME_SIZE_LIMIT 0x7C00 /* 31KB = 31744byte = 0x7C00 */ #endif -struct _param_check { - unsigned int total_size; - unsigned int rest_size; - unsigned int send_size; - unsigned int copy_start; - unsigned int copy_complete; - unsigned int boot_complete; -}; - -static struct _param_nv *data_param; -static struct _param_check check_param; - -static unsigned int boot_start_complete; -static struct msm_edpram_boot_map msm_edpram_bt_map; static struct dpram_ipc_map msm_ipc_map; -static unsigned char *img; -static unsigned char *nv_img; - -static void msm_edpram_reset(void); -static void msm_edpram_clr_intr(void); -static u16 msm_edpram_recv_intr(void); -static void msm_edpram_send_intr(u16 irq_mask); -static u16 msm_edpram_recv_msg(void); -static void msm_edpram_send_msg(u16 msg); - -static u16 msm_edpram_get_magic(void); -static void msm_edpram_set_magic(u16 value); -static u16 msm_edpram_get_access(void); -static void msm_edpram_set_access(u16 value); - -static u32 msm_edpram_get_tx_head(int dev_id); -static u32 msm_edpram_get_tx_tail(int dev_id); -static void msm_edpram_set_tx_head(int dev_id, u32 head); -static void msm_edpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *msm_edpram_get_tx_buff(int dev_id); -static u32 msm_edpram_get_tx_buff_size(int dev_id); - -static u32 msm_edpram_get_rx_head(int dev_id); -static u32 msm_edpram_get_rx_tail(int dev_id); -static void msm_edpram_set_rx_head(int dev_id, u32 head); -static void msm_edpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *msm_edpram_get_rx_buff(int dev_id); -static u32 msm_edpram_get_rx_buff_size(int dev_id); - -static u16 msm_edpram_get_mask_req_ack(int dev_id); -static u16 msm_edpram_get_mask_res_ack(int dev_id); -static u16 msm_edpram_get_mask_send(int dev_id); - -static void msm_log_disp(struct modemlink_dpram_control *dpctl); -static int msm_uload_step1(struct modemlink_dpram_control *dpctl); -static int msm_uload_step2(void *arg, struct modemlink_dpram_control *dpctl); -static int msm_dload_prep(struct modemlink_dpram_control *dpctl); -static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl); -static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl); -static int msm_boot_start(struct modemlink_dpram_control *dpctl); -static int msm_boot_start_post_proc(void); -static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl); -static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd); -static void msm_bt_map_init(struct modemlink_dpram_control *dpctl); -static void msm_load_init(struct modemlink_dpram_control *dpctl); -static void msm_terminate_link(struct modemlink_dpram_control *dpctl); - static struct modemlink_dpram_control msm_edpram_ctrl = { - .reset = msm_edpram_reset, - - .clear_intr = msm_edpram_clr_intr, - .recv_intr = msm_edpram_recv_intr, - .send_intr = msm_edpram_send_intr, - .recv_msg = msm_edpram_recv_msg, - .send_msg = msm_edpram_send_msg, - - .get_magic = msm_edpram_get_magic, - .set_magic = msm_edpram_set_magic, - .get_access = msm_edpram_get_access, - .set_access = msm_edpram_set_access, - - .get_tx_head = msm_edpram_get_tx_head, - .get_tx_tail = msm_edpram_get_tx_tail, - .set_tx_head = msm_edpram_set_tx_head, - .set_tx_tail = msm_edpram_set_tx_tail, - .get_tx_buff = msm_edpram_get_tx_buff, - .get_tx_buff_size = msm_edpram_get_tx_buff_size, - - .get_rx_head = msm_edpram_get_rx_head, - .get_rx_tail = msm_edpram_get_rx_tail, - .set_rx_head = msm_edpram_set_rx_head, - .set_rx_tail = msm_edpram_set_rx_tail, - .get_rx_buff = msm_edpram_get_rx_buff, - .get_rx_buff_size = msm_edpram_get_rx_buff_size, - - .get_mask_req_ack = msm_edpram_get_mask_req_ack, - .get_mask_res_ack = msm_edpram_get_mask_res_ack, - .get_mask_send = msm_edpram_get_mask_send, - - .log_disp = msm_log_disp, - .cpupload_step1 = msm_uload_step1, - .cpupload_step2 = msm_uload_step2, - .cpimage_load = msm_dload, - .nvdata_load = msm_nv_load, - .phone_boot_start = msm_boot_start, - .dload_cmd_hdlr = msm_dload_handler, - .bt_map_init = msm_bt_map_init, - .load_init = msm_load_init, - .cpimage_load_prepare = msm_dload_prep, - .phone_boot_start_post_process = msm_boot_start_post_proc, - .phone_boot_start_handler = msm_boot_start_handler, - .terminate_link = msm_terminate_link, - - .dp_base = NULL, - .dp_size = 0, .dp_type = EXT_DPRAM, .dpram_irq = MSM_DPRAM_INT_IRQ, .dpram_irq_flags = IRQF_TRIGGER_FALLING, - .dpram_irq_name = "MDM6600_EDPRAM_IRQ", - .dpram_wlock_name = "MDM6600_EDPRAM_WLOCK", .max_ipc_dev = IPC_RFS, + .ipc_map = &msm_ipc_map, + + .boot_size_offset = DP_BOOT_SIZE_OFFSET, + .boot_tag_offset = DP_BOOT_TAG_OFFSET, + .boot_count_offset = DP_BOOT_COUNT_OFFSET, + .max_boot_frame_size = DP_BOOT_FRAME_SIZE_LIMIT, + +#if defined(CONFIG_LINK_DEVICE_PLD) + .aligned = 1, +#endif }; /* ** CDMA target platform data */ +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct modem_io_t cdma_io_devices[] = { + [0] = { + .name = "cdma_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD) + }, + [1] = { + .name = "cdma_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [2] = { + .name = "umts_ipc0", + .id = 0x01, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [3] = { + .name = "cdma_ipc0", + .id = 0x00, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [4] = { + .name = "multi_pdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_PLD), + }, + [5] = { + .name = "cdma_CSD", + .id = (1 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [6] = { + .name = "cdma_FOTA", + .id = (2 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [7] = { + .name = "cdma_GPS", + .id = (5 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [8] = { + .name = "cdma_XTRA", + .id = (6 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [9] = { + .name = "cdma_CDMA", + .id = (7 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [10] = { + .name = "cdma_EFS", + .id = (8 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [11] = { + .name = "cdma_TRFB", + .id = (9 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [12] = { + .name = "rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [13] = { + .name = "rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [14] = { + .name = "rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [15] = { + .name = "rmnet3", + .id = 0x2D, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [16] = { + .name = "cdma_SMD", + .id = (25 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [17] = { + .name = "cdma_VTVD", + .id = (26 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [18] = { + .name = "cdma_VTAD", + .id = (27 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [19] = { + .name = "cdma_VTCTRL", + .id = (28 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [20] = { + .name = "cdma_VTENT", + .id = (29 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, +}; + +#else static struct modem_io_t cdma_io_devices[] = { [0] = { - .name = "cdma_boot0", - .id = 0x1, - .format = IPC_BOOT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [1] = { - .name = "cdma_ramdump0", - .id = 0x1, - .format = IPC_RAMDUMP, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [2] = { - .name = "umts_ipc0", - .id = 0x01, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "umts_ipc0", + .id = 0x01, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [3] = { - .name = "cdma_ipc0", - .id = 0x00, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_ipc0", + .id = 0x00, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [4] = { - .name = "multi_pdp", - .id = 0x1, - .format = IPC_MULTI_RAW, - .io_type = IODEV_DUMMY, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "multi_pdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [5] = { - .name = "cdma_CSD", - .id = (1 | 0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_CSD", + .id = (1 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [6] = { - .name = "cdma_FOTA", - .id = (2 | 0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_FOTA", + .id = (2 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [7] = { - .name = "cdma_GPS", - .id = (5 | 0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_GPS", + .id = (5 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [8] = { - .name = "cdma_XTRA", - .id = (6 | 0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_XTRA", + .id = (6 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [9] = { - .name = "cdma_CDMA", - .id = (7 | 0x20), - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_DPRAM), - }, + .name = "cdma_CDMA", + .id = (7 | 0x20), + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, [10] = { .name = "cdma_EFS", .id = (8 | 0x20), .format = IPC_RAW, .io_type = IODEV_MISC, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [11] = { .name = "cdma_TRFB", .id = (9 | 0x20), .format = IPC_RAW, .io_type = IODEV_MISC, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [12] = { .name = "rmnet0", .id = 0x2A, .format = IPC_RAW, .io_type = IODEV_NET, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [13] = { .name = "rmnet1", .id = 0x2B, .format = IPC_RAW, .io_type = IODEV_NET, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [14] = { .name = "rmnet2", .id = 0x2C, .format = IPC_RAW, .io_type = IODEV_NET, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [15] = { .name = "rmnet3", .id = 0x2D, .format = IPC_RAW, .io_type = IODEV_NET, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [16] = { .name = "cdma_SMD", .id = (25 | 0x20), .format = IPC_RAW, .io_type = IODEV_MISC, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [17] = { .name = "cdma_VTVD", .id = (26 | 0x20), .format = IPC_RAW, .io_type = IODEV_MISC, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [18] = { .name = "cdma_VTAD", .id = (27 | 0x20), .format = IPC_RAW, .io_type = IODEV_MISC, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [19] = { .name = "cdma_VTCTRL", .id = (28 | 0x20), .format = IPC_RAW, .io_type = IODEV_MISC, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, [20] = { .name = "cdma_VTENT", .id = (29 | 0x20), .format = IPC_RAW, .io_type = IODEV_MISC, .links = LINKTYPE(LINKDEV_DPRAM), - }, + }, }; +#endif static struct modem_data cdma_modem_data = { .name = "mdm6600", @@ -539,21 +686,37 @@ static struct modem_data cdma_modem_data = { .gpio_pda_active = GPIO_PDA_ACTIVE, .gpio_phone_active = GPIO_MSM_PHONE_ACTIVE, .gpio_flm_uart_sel = GPIO_BOOT_SW_SEL, -#if 1 +#if defined(CONFIG_MACH_M0_CTC) .gpio_flm_uart_sel_rev06 = GPIO_BOOT_SW_SEL_REV06, + .gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP, #endif .gpio_dpram_int = GPIO_MSM_DPRAM_INT, - .gpio_host_wakeup = GPIO_IPC_HOST_WAKEUP, - - .gpio_cp_dump_int = 0, + .gpio_cp_dump_int = GPIO_CP_DUMP_INT, .gpio_cp_warm_reset = 0, .use_handover = false, +#if defined(CONFIG_SIM_DETECT) + .gpio_sim_detect = GPIO_CP_SIM_DETECT, +#else + .gpio_sim_detect = 0, +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) + .gpio_fpga2_creset = GPIO_FPGA2_CRESET, + .gpio_fpga2_cdone = GPIO_FPGA2_CDONE, + .gpio_fpga2_rst_n = GPIO_FPGA2_RST_N, + .gpio_fpga2_cs_n = GPIO_FPGA2_CS_N, +#endif + .modem_net = CDMA_NETWORK, .modem_type = QC_MDM6600, +#if defined(CONFIG_LINK_DEVICE_PLD) + .link_types = LINKTYPE(LINKDEV_PLD), +#else .link_types = LINKTYPE(LINKDEV_DPRAM), +#endif .link_name = "mdm6600_edpram", .dpram_ctl = &msm_edpram_ctrl, @@ -565,11 +728,25 @@ static struct modem_data cdma_modem_data = { static struct resource cdma_modem_res[] = { [0] = { - .name = "cp_active_irq", - .start = MSM_PHONE_ACTIVE_IRQ, - .end = MSM_PHONE_ACTIVE_IRQ, - .flags = IORESOURCE_IRQ, - }, + .name = "cp_active_irq", + .start = MSM_PHONE_ACTIVE_IRQ, + .end = MSM_PHONE_ACTIVE_IRQ, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "dpram_irq", + .start = MSM_DPRAM_INT_IRQ, + .end = MSM_DPRAM_INT_IRQ, + .flags = IORESOURCE_IRQ, + }, +#if defined(CONFIG_SIM_DETECT) + [2] = { + .name = "sim_irq", + .start = CP_SIM_DETECT_IRQ, + .end = CP_SIM_DETECT_IRQ, + .flags = IORESOURCE_IRQ, + }, +#endif }; static struct platform_device cdma_modem = { @@ -579,614 +756,9 @@ static struct platform_device cdma_modem = { .resource = cdma_modem_res, .dev = { .platform_data = &cdma_modem_data, - }, + }, }; -static void msm_edpram_reset(void) -{ - return; -} - -static void msm_edpram_clr_intr(void) -{ - ioread16(msm_ipc_map.mbx_cp2ap); -} - -static u16 msm_edpram_recv_intr(void) -{ - return ioread16(msm_ipc_map.mbx_cp2ap); -} - -static void msm_edpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, msm_ipc_map.mbx_ap2cp); -} - -static u16 msm_edpram_recv_msg(void) -{ - return ioread16(msm_ipc_map.mbx_cp2ap); -} - -static void msm_edpram_send_msg(u16 msg) -{ - iowrite16(msg, msm_ipc_map.mbx_ap2cp); -} - -static u16 msm_edpram_get_magic(void) -{ - return ioread16(msm_ipc_map.magic); -} - -static void msm_edpram_set_magic(u16 value) -{ - iowrite16(value, msm_ipc_map.magic); -} - -static u16 msm_edpram_get_access(void) -{ - return ioread16(msm_ipc_map.access); -} - -static void msm_edpram_set_access(u16 value) -{ - iowrite16(value, msm_ipc_map.access); -} - -static u32 msm_edpram_get_tx_head(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].txq.head); -} - -static u32 msm_edpram_get_tx_tail(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].txq.tail); -} - -static void msm_edpram_set_tx_head(int dev_id, u32 head) -{ - iowrite16((u16) head, msm_ipc_map.dev[dev_id].txq.head); -} - -static void msm_edpram_set_tx_tail(int dev_id, u32 tail) -{ - iowrite16((u16) tail, msm_ipc_map.dev[dev_id].txq.tail); -} - -static u8 __iomem *msm_edpram_get_tx_buff(int dev_id) -{ - return msm_ipc_map.dev[dev_id].txq.buff; -} - -static u32 msm_edpram_get_tx_buff_size(int dev_id) -{ - return msm_ipc_map.dev[dev_id].txq.size; -} - -static u32 msm_edpram_get_rx_head(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].rxq.head); -} - -static u32 msm_edpram_get_rx_tail(int dev_id) -{ - return ioread16(msm_ipc_map.dev[dev_id].rxq.tail); -} - -static void msm_edpram_set_rx_head(int dev_id, u32 head) -{ - return iowrite16((u16) head, msm_ipc_map.dev[dev_id].rxq.head); -} - -static void msm_edpram_set_rx_tail(int dev_id, u32 tail) -{ - return iowrite16((u16) tail, msm_ipc_map.dev[dev_id].rxq.tail); -} - -static u8 __iomem *msm_edpram_get_rx_buff(int dev_id) -{ - return msm_ipc_map.dev[dev_id].rxq.buff; -} - -static u32 msm_edpram_get_rx_buff_size(int dev_id) -{ - return msm_ipc_map.dev[dev_id].rxq.size; -} - -static u16 msm_edpram_get_mask_req_ack(int dev_id) -{ - return msm_ipc_map.dev[dev_id].mask_req_ack; -} - -static u16 msm_edpram_get_mask_res_ack(int dev_id) -{ - return msm_ipc_map.dev[dev_id].mask_res_ack; -} - -static u16 msm_edpram_get_mask_send(int dev_id) -{ - return msm_ipc_map.dev[dev_id].mask_send; -} - -static void msm_log_disp(struct modemlink_dpram_control *dpctl) -{ - static unsigned char buf[151]; - u8 __iomem *tmp_buff = NULL; - - tmp_buff = dpctl->get_rx_buff(IPC_FMT); - memcpy(buf, tmp_buff, (sizeof(buf) - 1)); - - pr_info("[LNK] | PHONE ERR MSG\t| CDMA Crash\n"); - pr_info("[LNK] | PHONE ERR MSG\t| %s\n", buf); -} - -static int msm_data_upload(struct _param_nv *param, - struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - u16 in_interrupt = 0; - int count = 0; - - while (1) { - if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) { - in_interrupt = dpctl->recv_msg(); - if (in_interrupt == 0xDBAB) { - break; - } else { - pr_err("[LNK][intr]:0x%08x\n", in_interrupt); - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - msleep_interruptible(1); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - param->size = ioread16(msm_edpram_bt_map.frame_size); - memcpy(param->addr, msm_edpram_bt_map.buff, param->size); - param->tag = ioread16(msm_edpram_bt_map.tag); - param->count = ioread16(msm_edpram_bt_map.count); - - dpctl->clear_intr(); - dpctl->send_msg(0xDB12); - - return retval; - -} - -static int msm_data_load(struct _param_nv *param, - struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - - if (param->size <= DP_BOOT_FRAME_SIZE_LIMIT) { - memcpy(msm_edpram_bt_map.buff, param->addr, param->size); - iowrite16(param->size, msm_edpram_bt_map.frame_size); - iowrite16(param->tag, msm_edpram_bt_map.tag); - iowrite16(param->count, msm_edpram_bt_map.count); - - dpctl->clear_intr(); - dpctl->send_msg(0xDB12); - - } else { - pr_err("[LNK/E]<%s> size:0x%x\n", __func__, param->size); - } - - return retval; -} - -static int msm_uload_step1(struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - u16 in_interrupt = 0, out_interrupt = 0; - - pr_info("[LNK] +---------------------------------------------+\n"); - pr_info("[LNK] | UPLOAD PHONE SDRAM |\n"); - pr_info("[LNK] +---------------------------------------------+\n"); - - while (1) { - if (!gpio_get_value(GPIO_MSM_DPRAM_INT)) { - in_interrupt = dpctl->recv_msg(); - pr_info("[LNK] [in_interrupt] 0x%04x\n", in_interrupt); - if (in_interrupt == 0x1234) { - break; - } else { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - msleep_interruptible(1); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - in_interrupt = dpctl->recv_msg(); - if (in_interrupt == 0x1234) { - pr_info("[LNK] [in_interrupt]: 0x%04x\n", - in_interrupt); - break; - } - return -1; - } - } - out_interrupt = 0xDEAD; - dpctl->send_msg(out_interrupt); - - return retval; -} - -static int msm_uload_step2(void *arg, struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - struct _param_nv param; - - retval = copy_from_user((void *)¶m, (void *)arg, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - retval = msm_data_upload(¶m, dpctl); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - if (!(param.count % 500)) - pr_info("[LNK] [param->count]:%d\n", param.count); - - if (param.tag == 4) { - dpctl->clear_intr(); - enable_irq(msm_edpram_ctrl.dpram_irq); - pr_info("[LNK] [param->tag]:%d\n", param.tag); - } - - retval = copy_to_user((unsigned long *)arg, ¶m, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - return retval; -} - -static int msm_dload_prep(struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - - while (1) { - if (check_param.copy_start) { - check_param.copy_start = 0; - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - return retval; -} - -static int msm_dload(void *arg, struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - struct _param_nv param; - - retval = copy_from_user((void *)¶m, (void *)arg, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - img = vmalloc(param.size); - if (img == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - memset(img, 0, param.size); - memcpy(img, param.addr, param.size); - - data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL); - if (data_param == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(img); - img = NULL; - return -1; - } - - check_param.total_size = param.size; - check_param.rest_size = param.size; - check_param.send_size = 0; - check_param.copy_complete = 0; - - data_param->addr = img; - data_param->size = DP_BOOT_FRAME_SIZE_LIMIT; - data_param->count = param.count; - - data_param->tag = 0x0001; - - if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT) - data_param->size = check_param.rest_size; - - retval = msm_data_load(data_param, dpctl); - - while (1) { - if (check_param.copy_complete) { - check_param.copy_complete = 0; - - vfree(img); - img = NULL; - kfree(data_param); - data_param = NULL; - - break; - } - msleep_interruptible(10); - count++; - if (count > 1000) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(img); - img = NULL; - kfree(data_param); - data_param = NULL; - return -1; - } - } - - return retval; - -} - -static int msm_nv_load(void *arg, struct modemlink_dpram_control *dpctl) -{ - int retval = 0; - int count = 0; - struct _param_nv param; - - retval = copy_from_user((void *)¶m, (void *)arg, sizeof(param)); - if (retval < 0) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - - nv_img = vmalloc(param.size); - if (nv_img == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - memset(nv_img, 0, param.size); - memcpy(nv_img, param.addr, param.size); - - data_param = kzalloc(sizeof(struct _param_nv), GFP_KERNEL); - if (data_param == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(nv_img); - nv_img = NULL; - return -1; - } - - check_param.total_size = param.size; - check_param.rest_size = param.size; - check_param.send_size = 0; - check_param.copy_complete = 0; - - data_param->addr = nv_img; - data_param->size = DP_BOOT_FRAME_SIZE_LIMIT; - data_param->count = 1; - data_param->tag = 0x0002; - - if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT) - data_param->size = check_param.rest_size; - - retval = msm_data_load(data_param, dpctl); - - while (1) { - if (check_param.copy_complete) { - check_param.copy_complete = 0; - - vfree(nv_img); - nv_img = NULL; - kfree(data_param); - data_param = NULL; - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - vfree(nv_img); - nv_img = NULL; - kfree(data_param); - data_param = NULL; - return -1; - } - } - - return retval; - -} - -static int msm_boot_start(struct modemlink_dpram_control *dpctl) -{ - - u16 out_interrupt = 0; - int count = 0; - - /* Send interrupt -> '0x4567' */ - out_interrupt = 0x4567; - dpctl->send_msg(out_interrupt); - - while (1) { - if (check_param.boot_complete) { - check_param.boot_complete = 0; - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - return 0; -} - - -static void msm_terminate_link(struct modemlink_dpram_control *dpctl) -{ - pr_info("[LNK] +--------------msm_terminate_link------------+\n"); - if (img != NULL) { - pr_info("[LNK] +--------------img free----------------+\n"); - vfree(img); - img = NULL; - } - if (nv_img != NULL) { - pr_info("[LNK] +--------------nv_img free----------------+\n"); - vfree(nv_img); - nv_img = NULL; - } - if (data_param != NULL) { - pr_info("[LNK] +--------------data_param free----------------+\n"); - kfree(data_param); - data_param = NULL; - } - -} - -static struct modemlink_dpram_control *tasklet_dpctl; - -static void interruptable_load_tasklet_handler(unsigned long data); - -static DECLARE_TASKLET(interruptable_load_tasklet, - interruptable_load_tasklet_handler, - (unsigned long)&tasklet_dpctl); - -static void interruptable_load_tasklet_handler(unsigned long data) -{ - struct modemlink_dpram_control *dpctl = - (struct modemlink_dpram_control *) - (*((struct modemlink_dpram_control **)data)); - - if (data_param == NULL) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return; - } - - check_param.send_size += data_param->size; - check_param.rest_size -= data_param->size; - data_param->addr += data_param->size; - - if (check_param.send_size < check_param.total_size) { - - if (check_param.rest_size < DP_BOOT_FRAME_SIZE_LIMIT) - data_param->size = check_param.rest_size; - - data_param->count += 1; - - msm_data_load(data_param, dpctl); - } else { - data_param->tag = 0; - check_param.copy_complete = 1; - } - -} - -static int msm_boot_start_post_proc(void) -{ - int count = 0; - - while (1) { - if (boot_start_complete) { - boot_start_complete = 0; - break; - } - msleep_interruptible(10); - count++; - if (count > 200) { - pr_err("[LNK/E]<%s:%d>\n", __func__, __LINE__); - return -1; - } - } - - return 0; -} - -static void msm_boot_start_handler(struct modemlink_dpram_control *dpctl) -{ - boot_start_complete = 1; - - /* Send INIT_END code to CP */ - pr_info("[LNK] <%s> Send 0x11C2 (INIT_END)\n", __func__); - - /* - * INT_MASK_VALID|INT_MASK_CMD|INT_MASK_CP_AIRPLANE_BOOT| - * INT_MASK_CP_AP_ANDROID|INT_MASK_CMD_INIT_END - */ - dpctl->send_intr((0x0080 | 0x0040 | 0x1000 | 0x0100 | 0x0002)); -} - -static void msm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd) -{ - switch (cmd) { - case 0x1234: - check_param.copy_start = 1; - break; - - case 0xDBAB: - tasklet_schedule(&interruptable_load_tasklet); - break; - - case 0xABCD: - check_param.boot_complete = 1; - break; - - default: - pr_err("[LNK/Err] <%s> Unknown command.. %x\n", __func__, cmd); - } -} - -static void msm_bt_map_init(struct modemlink_dpram_control *dpctl) -{ - msm_edpram_bt_map.buff = (u8 *) (dpctl->dp_base); - msm_edpram_bt_map.frame_size = - (u16 *) (dpctl->dp_base + DP_BOOT_SIZE_OFFSET); - msm_edpram_bt_map.tag = (u16 *) (dpctl->dp_base + DP_BOOT_TAG_OFFSET); - msm_edpram_bt_map.count = - (u16 *) (dpctl->dp_base + DP_BOOT_COUNT_OFFSET); -} - -static void msm_load_init(struct modemlink_dpram_control *dpctl) -{ - tasklet_dpctl = dpctl; - if (tasklet_dpctl == NULL) - pr_err("[LNK/Err] failed tasklet_dpctl remap\n"); - - check_param.total_size = 0; - check_param.rest_size = 0; - check_param.send_size = 0; - check_param.copy_start = 0; - check_param.copy_complete = 0; - check_param.boot_complete = 0; - - dpctl->clear_intr(); -} - -static irqreturn_t host_wakeup_isr(int irq, void *dev) -{ - pr_err("[MODEMS] <%s>\n", __func__); - - return IRQ_HANDLED; -} - static void config_cdma_modem_gpio(void) { int err; @@ -1197,13 +769,21 @@ static void config_cdma_modem_gpio(void) unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active; unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active; unsigned gpio_flm_uart_sel = cdma_modem_data.gpio_flm_uart_sel; -#if 1 +#if defined(CONFIG_MACH_M0_CTC) unsigned gpio_flm_uart_sel_rev06 = - cdma_modem_data.gpio_flm_uart_sel_rev06; + cdma_modem_data.gpio_flm_uart_sel_rev06; + unsigned gpio_host_wakeup = cdma_modem_data.gpio_host_wakeup; #endif unsigned gpio_dpram_int = cdma_modem_data.gpio_dpram_int; - unsigned gpio_host_wakeup = cdma_modem_data.gpio_host_wakeup; - + unsigned gpio_cp_dump_int = cdma_modem_data.gpio_cp_dump_int; + unsigned gpio_sim_detect = cdma_modem_data.gpio_sim_detect; + +#if defined(CONFIG_LINK_DEVICE_PLD) + unsigned gpio_fpga2_creset = cdma_modem_data.gpio_fpga2_creset; + unsigned gpio_fpga2_cdone = cdma_modem_data.gpio_fpga2_cdone; + unsigned gpio_fpga2_rst_n = cdma_modem_data.gpio_fpga2_rst_n; + unsigned gpio_fpga2_cs_n = cdma_modem_data.gpio_fpga2_cs_n; +#endif pr_info("[MODEMS] <%s>\n", __func__); if (gpio_pda_active) { @@ -1211,7 +791,7 @@ static void config_cdma_modem_gpio(void) if (err) { pr_err("fail to request gpio %s\n", "PDA_ACTIVE"); } else { - gpio_direction_output(gpio_pda_active, 1); + gpio_direction_output(gpio_pda_active, 0); s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); gpio_set_value(gpio_pda_active, 0); } @@ -1234,10 +814,10 @@ static void config_cdma_modem_gpio(void) if (err) { pr_err("fail request gpio %s\n", "BOOT_SW_SEL"); } else { - gpio_direction_output(gpio_flm_uart_sel, 1); + gpio_direction_output(gpio_flm_uart_sel, 0); s3c_gpio_setpull(gpio_flm_uart_sel, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_flm_uart_sel, 1); + gpio_set_value(gpio_flm_uart_sel, 0); } } } else if (system_rev == 11) { @@ -1246,12 +826,13 @@ static void config_cdma_modem_gpio(void) if (err) { pr_err("fail request gpio %s\n", "BOOT_SW_SEL"); } else { - gpio_direction_output(gpio_flm_uart_sel, 1); + gpio_direction_output(gpio_flm_uart_sel, 0); s3c_gpio_setpull(gpio_flm_uart_sel, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_flm_uart_sel, 1); + gpio_set_value(gpio_flm_uart_sel, 0); } } +#if defined(CONFIG_MACH_M0_CTC) if (gpio_flm_uart_sel_rev06) { err = gpio_request(gpio_flm_uart_sel_rev06, "BOOT_SW_SEL_REV06"); @@ -1260,23 +841,26 @@ static void config_cdma_modem_gpio(void) "BOOT_SW_SEL_REV06"); } else { gpio_direction_output(gpio_flm_uart_sel_rev06, - 1); + 0); s3c_gpio_setpull(gpio_flm_uart_sel_rev06, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_flm_uart_sel_rev06, 1); + gpio_set_value(gpio_flm_uart_sel_rev06, 0); } } +#endif } else { +#if defined(CONFIG_MACH_M0_CTC) err = gpio_request(gpio_flm_uart_sel_rev06, "BOOT_SW_SEL_REV06"); if (err) { pr_err("fail request gpio %s\n", "BOOT_SW_SEL_REV06"); } else { - gpio_direction_output(gpio_flm_uart_sel_rev06, 1); + gpio_direction_output(gpio_flm_uart_sel_rev06, 0); s3c_gpio_setpull(gpio_flm_uart_sel_rev06, S3C_GPIO_PULL_NONE); - gpio_set_value(gpio_flm_uart_sel_rev06, 1); + gpio_set_value(gpio_flm_uart_sel_rev06, 0); } +#endif } if (gpio_cp_on) { @@ -1284,7 +868,7 @@ static void config_cdma_modem_gpio(void) if (err) { pr_err("fail to request gpio %s\n", "MSM_ON"); } else { - gpio_direction_output(gpio_cp_on, 1); + gpio_direction_output(gpio_cp_on, 0); s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); gpio_set_value(gpio_cp_on, 0); } @@ -1306,7 +890,7 @@ static void config_cdma_modem_gpio(void) if (err) { pr_err("fail to request gpio %s\n", "MSM_RST_REQ"); } else { - gpio_direction_output(gpio_rst_req_n, 1); + gpio_direction_output(gpio_rst_req_n, 0); s3c_gpio_setpull(gpio_rst_req_n, S3C_GPIO_PULL_NONE); } gpio_set_value(gpio_rst_req_n, 0); @@ -1317,7 +901,7 @@ static void config_cdma_modem_gpio(void) if (err) { pr_err("fail to request gpio %s\n", "MSM_RST"); } else { - gpio_direction_output(gpio_cp_rst, 1); + gpio_direction_output(gpio_cp_rst, 0); s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); } gpio_set_value(gpio_cp_rst, 0); @@ -1334,6 +918,7 @@ static void config_cdma_modem_gpio(void) } } +#if defined(CONFIG_MACH_M0_CTC) if (gpio_host_wakeup) { err = gpio_request(gpio_host_wakeup, "MSM_HOST_WAKEUP"); if (err) { @@ -1346,6 +931,76 @@ static void config_cdma_modem_gpio(void) IRQ_TYPE_LEVEL_HIGH); } } +#endif + + if (gpio_cp_dump_int) { + err = gpio_request(gpio_cp_dump_int, "MSM_CP_DUMP_INT"); + if (err) { + pr_err("fail to request gpio %s\n", "MSM_CP_DUMP_INT"); + } else { + s3c_gpio_cfgpin(gpio_cp_dump_int, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio_cp_dump_int, S3C_GPIO_PULL_DOWN); + } + } + +#if defined(CONFIG_LINK_DEVICE_PLD) + if (gpio_fpga2_creset) { + err = gpio_request(gpio_fpga2_creset, "FPGA2_CRESET"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA2_CRESET", gpio_fpga2_creset, err); + } else { + gpio_direction_output(gpio_fpga2_creset, 0); + s3c_gpio_setpull(gpio_fpga2_creset, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga2_cdone) { + err = gpio_request(gpio_fpga2_cdone, "FPGA2_CDONE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA2_CDONE", gpio_fpga2_cdone, err); + } else { + s3c_gpio_cfgpin(gpio_fpga2_cdone, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio_fpga2_cdone, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga2_rst_n) { + err = gpio_request(gpio_fpga2_rst_n, "FPGA2_RESET"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA2_RESET", gpio_fpga2_rst_n, err); + } else { + gpio_direction_output(gpio_fpga2_rst_n, 0); + s3c_gpio_setpull(gpio_fpga2_rst_n, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga2_cs_n) { + err = gpio_request(gpio_fpga2_cs_n, "SPI_CS2_1"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "SPI_CS2_1", gpio_fpga2_cs_n, err); + } else { + gpio_direction_output(gpio_fpga2_cs_n, 0); + s3c_gpio_setpull(gpio_fpga2_cs_n, S3C_GPIO_PULL_NONE); + } + } +#endif + + if (gpio_sim_detect) { + err = gpio_request(gpio_sim_detect, "MSM_SIM_DETECT"); + if (err) { + pr_err("fail to request gpio %s: %d\n", + "MSM_SIM_DETECT", err); + } else { + /* gpio_direction_input(gpio_sim_detect); */ + s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_sim_detect, IRQ_TYPE_EDGE_BOTH); + } + } } static u8 *msm_edpram_remap_mem_region(struct sromc_cfg *cfg) @@ -1371,9 +1026,20 @@ static u8 *msm_edpram_remap_mem_region(struct sromc_cfg *cfg) /* Map for IPC */ ipc_map = (struct msm_edpram_ipc_cfg *)dp_base; +#if defined(CONFIG_LINK_DEVICE_PLD) + /* Magic code and access enable fields */ + msm_ipc_map.magic_ap2cp = (u16 __iomem *) &ipc_map->magic_ap2cp; + msm_ipc_map.access_ap2cp = (u16 __iomem *) &ipc_map->access_ap2cp; + + msm_ipc_map.magic_cp2ap = (u16 __iomem *) &ipc_map->magic_cp2ap; + msm_ipc_map.access_cp2ap = (u16 __iomem *) &ipc_map->access_cp2ap; + + msm_ipc_map.address_buffer = (u16 __iomem *) &ipc_map->address_buffer; +#else /* Magic code and access enable fields */ msm_ipc_map.magic = (u16 __iomem *) &ipc_map->magic; msm_ipc_map.access = (u16 __iomem *) &ipc_map->access; +#endif /* FMT */ dev = &msm_ipc_map.dev[IPC_FMT]; @@ -1415,28 +1081,6 @@ static u8 *msm_edpram_remap_mem_region(struct sromc_cfg *cfg) dev->mask_res_ack = INT_MASK_RES_ACK_R; dev->mask_send = INT_MASK_SEND_R; -#if 0 - /* RFS */ - dev = &msm_ipc_map.dev[IPC_RFS]; - - strcpy(dev->name, "RFS"); - dev->id = IPC_RFS; - - dev->txq.head = (u16 __iomem *) &ipc_map->rfs_tx_head; - dev->txq.tail = (u16 __iomem *) &ipc_map->rfs_tx_tail; - dev->txq.buff = (u8 __iomem *) &ipc_map->rfs_tx_buff[0]; - dev->txq.size = MSM_DP_RFS_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *) &ipc_map->rfs_rx_head; - dev->rxq.tail = (u16 __iomem *) &ipc_map->rfs_rx_tail; - dev->rxq.buff = (u8 __iomem *) &ipc_map->rfs_rx_buff[0]; - dev->rxq.size = MSM_DP_RFS_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_RFS; - dev->mask_res_ack = INT_MASK_RES_ACK_RFS; - dev->mask_send = INT_MASK_SEND_RFS; -#endif - /* Mailboxes */ msm_ipc_map.mbx_ap2cp = (u16 __iomem *) &ipc_map->mbx_ap2cp; msm_ipc_map.mbx_cp2ap = (u16 __iomem *) &ipc_map->mbx_cp2ap; @@ -1481,18 +1125,36 @@ static void config_dpram_port_gpio(void) __func__, addr_bits - EXYNOS4_GPIO_Y3_NR); break; + case 15: + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR, + S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0), EXYNOS4_GPIO_Y4_NR, + S3C_GPIO_SFN(2)); + pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n", + __func__, EXYNOS4_GPIO_Y4_NR); + break; + + default: pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__); return; } /* Set GPIO for dpram data - 16bit */ +#if defined(CONFIG_LINK_DEVICE_PLD) + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2)); +#elif defined(CONFIG_LINK_DEVICE_DPRAM) s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2)); s3c_gpio_cfgrange_nopull(EXYNOS4_GPY6(0), 8, S3C_GPIO_SFN(2)); +#endif /* Setup SROMC CSn pins */ s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2)); +#if defined(CONFIG_GSM_MODEM_ESC6270) + s3c_gpio_cfgpin(GPIO_DPRAM_CSN1, S3C_GPIO_SFN(2)); +#endif + /* Config OEn, WEn */ s3c_gpio_cfgrange_nopull(GPIO_DPRAM_REN, 2, S3C_GPIO_SFN(2)); @@ -1500,7 +1162,9 @@ static void config_dpram_port_gpio(void) s3c_gpio_cfgrange_nopull(GPIO_DPRAM_LBN, 2, S3C_GPIO_SFN(2)); /* Config BUSY */ +#if !defined(CONFIG_LINK_DEVICE_PLD) s3c_gpio_cfgpin(GPIO_DPRAM_BUSY, S3C_GPIO_SFN(2)); +#endif } static void init_sromc(void) @@ -1516,8 +1180,9 @@ static void init_sromc(void) clk_enable(clk); } -static void setup_sromc -(unsigned csn, struct sromc_cfg *cfg, struct sromc_access_cfg *acc_cfg) { +static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, + struct sromc_access_cfg *acc_cfg) +{ unsigned bw = 0; unsigned bc = 0; void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); @@ -1532,13 +1197,13 @@ static void setup_sromc /* Set the BW control field for the CSn */ bw &= ~(SROMC_MASK << (csn * 4)); - if (cfg->attr | MEM_DATA_BUS_16BIT) + if (cfg->attr & MEM_DATA_BUS_16BIT) bw |= (SROMC_DATA_16 << (csn * 4)); - if (cfg->attr | MEM_WAIT_EN) + if (cfg->attr & MEM_WAIT_EN) bw |= (SROMC_WAIT_EN << (csn * 4)); - if (cfg->attr | MEM_BYTE_EN) + if (cfg->attr & MEM_BYTE_EN) bw |= (SROMC_BYTE_EN << (csn * 4)); writel(bw, S5P_SROM_BW); @@ -1556,34 +1221,803 @@ static void setup_sromc __func__, bw, csn, bc); } -static void setup_dpram_speed(unsigned csn, struct sromc_access_cfg *acc_cfg) +/* For ESC6270 modem */ +#if defined(CONFIG_GSM_MODEM_ESC6270) +static struct dpram_ipc_map gsm_ipc_map; + +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct sromc_cfg gsm_edpram_cfg = { + .attr = (MEM_DATA_BUS_8BIT), + .size = 0x10000, +}; +#else +static struct sromc_cfg gsm_edpram_cfg = { + .attr = (MEM_DATA_BUS_16BIT | MEM_WAIT_EN | MEM_BYTE_EN), + .size = MSM_EDPRAM_SIZE, +}; +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct sromc_access_cfg gsm_edpram_access_cfg[] = { + [DPRAM_SPEED_LOW] = { + .tacs = 0x2 << 28, + .tcos = 0x2 << 24, + .tacc = 0x3 << 16, + .tcoh = 0x2 << 12, + .tcah = 0x2 << 8, + .tacp = 0x2 << 4, + .pmc = 0x0 << 0, + }, +}; +#else +static struct sromc_access_cfg gsm_edpram_access_cfg[] = { + [DPRAM_SPEED_LOW] = { + .tacs = 0x2 << 28, + .tcos = 0x2 << 24, + .tacc = 0x3 << 16, + .tcoh = 0x2 << 12, + .tcah = 0x2 << 8, + .tacp = 0x2 << 4, + .pmc = 0x0 << 0, + }, +}; +#endif + +static struct modemlink_dpram_control gsm_edpram_ctrl = { + .dp_type = EXT_DPRAM, + + .dpram_irq = ESC_DPRAM_INT_IRQ, + .dpram_irq_flags = IRQF_TRIGGER_FALLING, + + .max_ipc_dev = IPC_RFS, + .ipc_map = &gsm_ipc_map, + + .boot_size_offset = DP_BOOT_SIZE_OFFSET, + .boot_tag_offset = DP_BOOT_TAG_OFFSET, + .boot_count_offset = DP_BOOT_COUNT_OFFSET, + .max_boot_frame_size = DP_BOOT_FRAME_SIZE_LIMIT, + +#if defined(CONFIG_LINK_DEVICE_PLD) + .aligned = 1, +#endif +}; + +/* +** GSM target platform data +*/ +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct modem_io_t gsm_io_devices[] = { + [0] = { + .name = "gsm_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [1] = { + .name = "gsm_ipc0", + .id = 0x01, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [2] = { + .name = "gsm_rfs0", + .id = 0x28, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [3] = { + .name = "gsm_multi_pdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_PLD), + }, + [4] = { + .name = "gsm_rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [5] = { + .name = "gsm_rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [6] = { + .name = "gsm_rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [7] = { + .name = "gsm_router", + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [8] = { + .name = "gsm_csd", + .id = 0x21, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [9] = { + .name = "gsm_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [10] = { + .name = "gsm_loopback0", + .id = 0x3F, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, +}; +#else +static struct modem_io_t gsm_io_devices[] = { + [0] = { + .name = "gsm_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [1] = { + .name = "gsm_ipc0", + .id = 0x01, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [2] = { + .name = "gsm_rfs0", + .id = 0x28, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [3] = { + .name = "gsm_multi_pdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [4] = { + .name = "gsm_rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [5] = { + .name = "gsm_rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [6] = { + .name = "gsm_rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [7] = { + .name = "gsm_router", + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [8] = { + .name = "gsm_csd", + .id = 0x21, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [9] = { + .name = "gsm_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [10] = { + .name = "gsm_loopback0", + .id = 0x3F, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, +}; +#endif + +static struct modem_data gsm_modem_data = { + .name = "esc6270", + + .gpio_cp_on = GPIO_CP2_MSM_PWRON, + .gpio_cp_off = 0, + .gpio_reset_req_n = 0, /* GPIO_CP_MSM_PMU_RST, */ + .gpio_cp_reset = GPIO_CP2_MSM_RST, + .gpio_pda_active = 0, + .gpio_phone_active = GPIO_ESC_PHONE_ACTIVE, + .gpio_flm_uart_sel = GPIO_BOOT_SW_SEL_CP2, + + .gpio_dpram_int = GPIO_ESC_DPRAM_INT, + + .gpio_cp_dump_int = 0, + .gpio_cp_warm_reset = 0, + +#if defined(CONFIG_SIM_DETECT) + .gpio_sim_detect = GPIO_ESC_SIM_DETECT, +#else + .gpio_sim_detect = 0, +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) + .gpio_fpga1_creset = GPIO_FPGA1_CRESET, + .gpio_fpga1_cdone = GPIO_FPGA1_CDONE, + .gpio_fpga1_rst_n = GPIO_FPGA1_RST_N, + .gpio_fpga1_cs_n = GPIO_FPGA1_CS_N, +#endif + + .use_handover = false, + + .modem_net = CDMA_NETWORK, + .modem_type = QC_ESC6270, +#if defined(CONFIG_LINK_DEVICE_PLD) + .link_types = LINKTYPE(LINKDEV_PLD), +#else + .link_types = LINKTYPE(LINKDEV_DPRAM), +#endif + .link_name = "esc6270_edpram", + .dpram_ctl = &gsm_edpram_ctrl, + + .ipc_version = SIPC_VER_41, + + .num_iodevs = ARRAY_SIZE(gsm_io_devices), + .iodevs = gsm_io_devices, +}; + +static struct resource gsm_modem_res[] = { + [0] = { + .name = "cp_active_irq", + .start = ESC_PHONE_ACTIVE_IRQ, + .end = ESC_PHONE_ACTIVE_IRQ, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "dpram_irq", + .start = ESC_DPRAM_INT_IRQ, + .end = ESC_DPRAM_INT_IRQ, + .flags = IORESOURCE_IRQ, + }, +#if defined(CONFIG_SIM_DETECT) + [2] = { + .name = "sim_irq", + .start = ESC_SIM_DETECT_IRQ, + .end = ESC_SIM_DETECT_IRQ, + .flags = IORESOURCE_IRQ, + }, +#endif +}; + +static struct platform_device gsm_modem = { + .name = "modem_if", + .id = 1, + .num_resources = ARRAY_SIZE(gsm_modem_res), + .resource = gsm_modem_res, + .dev = { + .platform_data = &gsm_modem_data, + }, +}; + +void config_gsm_modem_gpio(void) { - void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); - unsigned bc = 0; + int err = 0; + unsigned gpio_cp_on = gsm_modem_data.gpio_cp_on; + unsigned gpio_cp_off = gsm_modem_data.gpio_cp_off; + unsigned gpio_rst_req_n = gsm_modem_data.gpio_reset_req_n; + unsigned gpio_cp_rst = gsm_modem_data.gpio_cp_reset; + unsigned gpio_pda_active = gsm_modem_data.gpio_pda_active; + unsigned gpio_phone_active = gsm_modem_data.gpio_phone_active; + unsigned gpio_flm_uart_sel = gsm_modem_data.gpio_flm_uart_sel; + unsigned gpio_dpram_int = gsm_modem_data.gpio_dpram_int; + unsigned gpio_sim_detect = gsm_modem_data.gpio_sim_detect; + +#if defined(CONFIG_LINK_DEVICE_PLD) + unsigned gpio_fpga1_creset = gsm_modem_data.gpio_fpga1_creset; + unsigned gpio_fpga1_cdone = gsm_modem_data.gpio_fpga1_cdone; + unsigned gpio_fpga1_rst_n = gsm_modem_data.gpio_fpga1_rst_n; + unsigned gpio_fpga1_cs_n = gsm_modem_data.gpio_fpga1_cs_n; +#endif - bc = __raw_readl(bank_sfr); - pr_info("[MDM] <%s> Old CS%d setting = 0x%08X\n", __func__, csn, bc); + pr_err("[MODEMS] <%s>\n", __func__); - /* SROMC memory access timing setting */ - bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | - acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; - writel(bc, bank_sfr); + if (gpio_pda_active) { + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "PDA_ACTIVE", gpio_pda_active, err); + } else { + gpio_direction_output(gpio_pda_active, 1); + s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_pda_active, 0); + } + } - bc = __raw_readl(bank_sfr); - pr_err("[MDM] <%s> New CS%d setting = 0x%08X\n", __func__, csn, bc); + if (gpio_phone_active) { + err = gpio_request(gpio_phone_active, "ESC_ACTIVE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_ACTIVE", gpio_phone_active, err); + } else { + s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH); + } + } + + if (gpio_flm_uart_sel) { + err = gpio_request(gpio_flm_uart_sel, "BOOT_SW_SEL2"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "BOOT_SW_SEL2", gpio_flm_uart_sel, err); + } else { + gpio_direction_output(gpio_flm_uart_sel, 1); + s3c_gpio_setpull(gpio_flm_uart_sel, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_flm_uart_sel, 1); + } + } + + if (gpio_cp_on) { + err = gpio_request(gpio_cp_on, "ESC_ON"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_ON", gpio_cp_on, err); + } else { + gpio_direction_output(gpio_cp_on, 0); + s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio_cp_on, S5P_GPIO_DRVSTR_LV1); + gpio_set_value(gpio_cp_on, 0); + } + } + + if (gpio_cp_off) { + err = gpio_request(gpio_cp_off, "ESC_OFF"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_OFF", (gpio_cp_off), err); + } else { + gpio_direction_output(gpio_cp_off, 1); + s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_cp_off, 1); + } + } + + if (gpio_rst_req_n) { + err = gpio_request(gpio_rst_req_n, "ESC_RST_REQ"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_RST_REQ", gpio_rst_req_n, err); + } else { + gpio_direction_output(gpio_rst_req_n, 1); + s3c_gpio_setpull(gpio_rst_req_n, S3C_GPIO_PULL_NONE); + } + gpio_set_value(gpio_rst_req_n, 0); + } + + if (gpio_cp_rst) { + err = gpio_request(gpio_cp_rst, "ESC_RST"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_RST", gpio_cp_rst, err); + } else { + gpio_direction_output(gpio_cp_rst, 0); + s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio_cp_rst, S5P_GPIO_DRVSTR_LV4); + } + gpio_set_value(gpio_cp_rst, 0); + } + + if (gpio_dpram_int) { + err = gpio_request(gpio_dpram_int, "ESC_DPRAM_INT"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_DPRAM_INT", gpio_dpram_int, err); + } else { + /* Configure as a wake-up source */ + s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE); + } + } + + err = gpio_request(EXYNOS4_GPA1(4), "AP_CP2_UART_RXD"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "AP_CP2_UART_RXD", EXYNOS4_GPA1(4), err); + } else { + s3c_gpio_cfgpin(EXYNOS4_GPA1(4), S3C_GPIO_SFN(0x2)); + s3c_gpio_setpull(EXYNOS4_GPA1(4), S3C_GPIO_PULL_NONE); + } + + err = gpio_request(EXYNOS4_GPA1(5), "AP_CP2_UART_TXD"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "AP_CP2_UART_TXD", EXYNOS4_GPA1(5), err); + } else { + s3c_gpio_cfgpin(EXYNOS4_GPA1(5), S3C_GPIO_SFN(0x2)); + s3c_gpio_setpull(EXYNOS4_GPA1(5), S3C_GPIO_PULL_NONE); + } + + if (gpio_sim_detect) { + err = gpio_request(gpio_sim_detect, "ESC_SIM_DETECT"); + if (err) { + pr_err("fail to request gpio %s: %d\n", + "ESC_SIM_DETECT", err); + } else { + /* gpio_direction_input(gpio_sim_detect); */ + s3c_gpio_cfgpin(gpio_sim_detect, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_sim_detect, S3C_GPIO_PULL_NONE); + /* irq_set_irq_type(gpio_sim_detect, IRQ_TYPE_EDGE_BOTH); */ + } + } + +#if defined(CONFIG_LINK_DEVICE_PLD) + if (gpio_fpga1_creset) { + err = gpio_request(gpio_fpga1_creset, "FPGA1_CRESET"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA1_CRESET", gpio_fpga1_creset, err); + } else { + gpio_direction_output(gpio_fpga1_creset, 0); + s3c_gpio_setpull(gpio_fpga1_creset, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga1_cdone) { + err = gpio_request(gpio_fpga1_cdone, "FPGA1_CDONE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA1_CDONE", gpio_fpga1_cdone, err); + } else { + s3c_gpio_cfgpin(gpio_fpga1_cdone, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio_fpga1_cdone, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga1_rst_n) { + err = gpio_request(gpio_fpga1_rst_n, "FPGA1_RST"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA1_RST", gpio_fpga1_rst_n, err); + } else { + gpio_direction_output(gpio_fpga1_rst_n, 0); + s3c_gpio_setpull(gpio_fpga1_rst_n, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga1_cs_n) { + err = gpio_request(gpio_fpga1_cs_n, "SPI_CS1_1"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "SPI_CS2_1", gpio_fpga1_cs_n, err); + } else { + gpio_direction_output(gpio_fpga1_cs_n, 0); + s3c_gpio_setpull(gpio_fpga1_cs_n, S3C_GPIO_PULL_NONE); + } + } +#endif } +static u8 *gsm_edpram_remap_mem_region(struct sromc_cfg *cfg) +{ + int dp_addr = 0; + int dp_size = 0; + u8 __iomem *dp_base = NULL; + struct msm_edpram_ipc_cfg *ipc_map = NULL; + struct dpram_ipc_device *dev = NULL; + + dp_addr = cfg->addr; + dp_size = cfg->size; + dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size); + if (!dp_base) { + pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__); + return NULL; + } + pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base); + + gsm_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; + gsm_edpram_ctrl.dp_size = dp_size; + + /* Map for IPC */ + ipc_map = (struct msm_edpram_ipc_cfg *)dp_base; + + /* Magic code and access enable fields */ +#if defined(CONFIG_LINK_DEVICE_PLD) + /* Magic code and access enable fields */ + gsm_ipc_map.magic_ap2cp = (u16 __iomem *) &ipc_map->magic_ap2cp; + gsm_ipc_map.access_ap2cp = (u16 __iomem *) &ipc_map->access_ap2cp; + + gsm_ipc_map.magic_cp2ap = (u16 __iomem *) &ipc_map->magic_cp2ap; + gsm_ipc_map.access_cp2ap = (u16 __iomem *) &ipc_map->access_cp2ap; + + gsm_ipc_map.address_buffer = (u16 __iomem *) &ipc_map->address_buffer; +#else + /* Magic code and access enable fields */ + gsm_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; + gsm_ipc_map.access = (u16 __iomem *)&ipc_map->access; +#endif + + /* FMT */ + dev = &gsm_ipc_map.dev[IPC_FMT]; + + strcpy(dev->name, "FMT"); + dev->id = IPC_FMT; + + dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; + dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; + dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; + dev->txq.size = MSM_DP_FMT_TX_BUFF_SZ; + + dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; + dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; + dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; + dev->rxq.size = MSM_DP_FMT_RX_BUFF_SZ; + + dev->mask_req_ack = INT_MASK_REQ_ACK_F; + dev->mask_res_ack = INT_MASK_RES_ACK_F; + dev->mask_send = INT_MASK_SEND_F; + + /* RAW */ + dev = &gsm_ipc_map.dev[IPC_RAW]; + + strcpy(dev->name, "RAW"); + dev->id = IPC_RAW; + + dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; + dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; + dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; + dev->txq.size = MSM_DP_RAW_TX_BUFF_SZ; + + dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; + dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; + dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; + dev->rxq.size = MSM_DP_RAW_RX_BUFF_SZ; + + dev->mask_req_ack = INT_MASK_REQ_ACK_R; + dev->mask_res_ack = INT_MASK_RES_ACK_R; + dev->mask_send = INT_MASK_SEND_R; + + /* Mailboxes */ + gsm_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; + gsm_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; + + return dp_base; +} +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define PLD_BLOCK_SIZE 0x8000 + +static struct spi_device *p_spi; + +static int pld_spi_probe(struct spi_device *spi) +{ + int ret = 0; + + mif_err("pld spi proble.\n"); + + p_spi = spi; + p_spi->mode = SPI_MODE_0; + p_spi->bits_per_word = 32; + + ret = spi_setup(p_spi); + if (ret != 0) { + mif_err("spi_setup ERROR : %d\n", ret); + return ret; + } + + dev_info(&p_spi->dev, "(%d) spi probe Done.\n", __LINE__); + + return ret; +} + +static int pld_spi_remove(struct spi_device *spi) +{ + return 0; +} + +static struct spi_driver pld_spi_driver = { + .probe = pld_spi_probe, + .remove = __devexit_p(pld_spi_remove), + .driver = { + .name = "modem_if_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, +}; + +static int config_spi_dev_init(void) +{ + int ret = 0; + + ret = spi_register_driver(&pld_spi_driver); + if (ret < 0) { + pr_info("spi_register_driver() fail : %d\n", ret); + return ret; + } + + pr_info("[%s] Done\n", __func__); + return 0; +} + +int spi_tx_rx_sync(u8 *tx_d, u8 *rx_d, unsigned len) +{ + struct spi_transfer t; + struct spi_message msg; + + memset(&t, 0, sizeof t); + + t.len = len; + + t.tx_buf = tx_d; + t.rx_buf = rx_d; + + t.cs_change = 0; + + t.bits_per_word = 8; + t.speed_hz = 12000000; + + spi_message_init(&msg); + spi_message_add_tail(&t, &msg); + + return spi_sync(p_spi, &msg); +} + +static int pld_send_fgpa_bin(void) +{ + int retval = 0; + char *tx_b, *rx_b; +#if defined(CONFIG_LINK_DEVICE_PLD) + unsigned gpio_fpga1_creset = gsm_modem_data.gpio_fpga1_creset; + unsigned gpio_fpga1_cdone = gsm_modem_data.gpio_fpga1_cdone; + unsigned gpio_fpga1_rst_n = gsm_modem_data.gpio_fpga1_rst_n; + unsigned gpio_fpga1_cs_n = gsm_modem_data.gpio_fpga1_cs_n; + + unsigned gpio_fpga2_creset = cdma_modem_data.gpio_fpga2_creset; + unsigned gpio_fpga2_cdone = cdma_modem_data.gpio_fpga2_cdone; + unsigned gpio_fpga2_rst_n = cdma_modem_data.gpio_fpga2_rst_n; + unsigned gpio_fpga2_cs_n = cdma_modem_data.gpio_fpga2_cs_n; +#endif + char dummy_data[8] = "abcdefg"; + + mif_info("sizeofpld : 0%d ", sizeof(fpga_bin)); + + if (gpio_fpga1_cs_n) { + s3c_gpio_cfgpin(gpio_fpga1_cs_n, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio_fpga1_cs_n, S3C_GPIO_PULL_NONE); + gpio_direction_output(gpio_fpga1_cs_n, 0); + } + + if (gpio_fpga2_cs_n) { + s3c_gpio_cfgpin(gpio_fpga2_cs_n, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio_fpga2_cs_n, S3C_GPIO_PULL_NONE); + gpio_direction_output(gpio_fpga2_cs_n, 0); + } + + msleep(20); + + if (gpio_fpga1_creset) { + gpio_direction_output(gpio_fpga1_creset, 1); + s3c_gpio_setpull(gpio_fpga1_creset, S3C_GPIO_PULL_NONE); + } + + if (gpio_fpga2_creset) { + gpio_direction_output(gpio_fpga2_creset, 1); + s3c_gpio_setpull(gpio_fpga2_creset, S3C_GPIO_PULL_NONE); + } + + msleep(20); + + tx_b = kmalloc(PLD_BLOCK_SIZE*2, GFP_ATOMIC); + if (!tx_b) { + mif_err("(%d) tx_b kmalloc fail.", + __LINE__); + return -ENOMEM; + } + memset(tx_b, 0, PLD_BLOCK_SIZE*2); + memcpy(tx_b, fpga_bin, sizeof(fpga_bin)); + + rx_b = kmalloc(PLD_BLOCK_SIZE*2, GFP_ATOMIC); + if (!rx_b) { + mif_err("(%d) rx_b kmalloc fail.", + __LINE__); + retval = -ENOMEM; + goto err; + } + memset(rx_b, 0, PLD_BLOCK_SIZE*2); + + retval = spi_tx_rx_sync(tx_b, rx_b, sizeof(fpga_bin)); + if (retval != 0) { + mif_err("(%d) spi sync error : %d\n", + __LINE__, retval); + goto err; + } + + memset(tx_b, 0, PLD_BLOCK_SIZE*2); + memcpy(tx_b, dummy_data, sizeof(dummy_data)); + + retval = spi_tx_rx_sync(tx_b, rx_b, sizeof(dummy_data)); + if (retval != 0) { + mif_err("(%d) spi sync error : %d\n", + __LINE__, retval); + goto err; + } + + msleep(20); + + mif_info("PLD_CDone1[%d], PLD_CDone2[%d]\n", + gpio_get_value(gpio_fpga1_cdone), + gpio_get_value(gpio_fpga2_cdone)); + + if (gpio_fpga1_rst_n) { + gpio_direction_output(gpio_fpga1_rst_n, 1); + s3c_gpio_setpull(gpio_fpga1_rst_n, S3C_GPIO_PULL_NONE); + } + + if (gpio_fpga2_rst_n) { + gpio_direction_output(gpio_fpga2_rst_n, 1); + s3c_gpio_setpull(gpio_fpga2_rst_n, S3C_GPIO_PULL_NONE); + } + +err: + kfree(tx_b); + kfree(rx_b); + + return retval; + +} +#endif + static int __init init_modem(void) { struct sromc_cfg *cfg = NULL; struct sromc_access_cfg *acc_cfg = NULL; +#if defined(CONFIG_MACH_T0_CHN_CTC) + msm_edpram_cfg.csn = 1; +#else msm_edpram_cfg.csn = 0; +#endif msm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * msm_edpram_cfg.csn); msm_edpram_cfg.end = msm_edpram_cfg.addr + msm_edpram_cfg.size - 1; config_dpram_port_gpio(); config_cdma_modem_gpio(); +#if defined(CONFIG_GSM_MODEM_ESC6270) + config_gsm_modem_gpio(); +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) + config_spi_dev_init(); + pld_send_fgpa_bin(); +#endif init_sromc(); cfg = &msm_edpram_cfg; @@ -1594,6 +2028,26 @@ static int __init init_modem(void) return -1; platform_device_register(&cdma_modem); +/* For ESC6270 modem */ +#if defined(CONFIG_GSM_MODEM_ESC6270) + +#if defined(CONFIG_MACH_T0_CHN_CTC) + gsm_edpram_cfg.csn = 0; +#else + gsm_edpram_cfg.csn = 1; +#endif + gsm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * gsm_edpram_cfg.csn); + gsm_edpram_cfg.end = gsm_edpram_cfg.addr + gsm_edpram_cfg.size - 1; + + cfg = &gsm_edpram_cfg; + acc_cfg = &gsm_edpram_access_cfg[DPRAM_SPEED_LOW]; + setup_sromc(cfg->csn, cfg, acc_cfg); + + if (!gsm_edpram_remap_mem_region(&gsm_edpram_cfg)) + return -1; + + platform_device_register(&gsm_modem); +#endif return 0; } @@ -1639,7 +2093,7 @@ static int usb3503_hw_config(void) if (err) { pr_err("fail to request gpio %s\n", "USB_BOOT_EN"); } else { - gpio_direction_output(GPIO_USB_BOOT_EN, 1); + gpio_direction_output(GPIO_USB_BOOT_EN, 0); s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE); } } else if (system_rev == 11) { @@ -1647,7 +2101,7 @@ static int usb3503_hw_config(void) if (err) { pr_err("fail to request gpio %s\n", "USB_BOOT_EN"); } else { - gpio_direction_output(GPIO_USB_BOOT_EN, 1); + gpio_direction_output(GPIO_USB_BOOT_EN, 0); s3c_gpio_setpull(GPIO_USB_BOOT_EN, S3C_GPIO_PULL_NONE); } err = gpio_request(GPIO_USB_BOOT_EN_REV06, "USB_BOOT_EN_REV06"); @@ -1655,7 +2109,7 @@ static int usb3503_hw_config(void) pr_err("fail to request gpio %s\n", "USB_BOOT_EN_REV06"); } else { - gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); + gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 0); s3c_gpio_setpull(GPIO_USB_BOOT_EN_REV06, S3C_GPIO_PULL_NONE); } @@ -1665,7 +2119,7 @@ static int usb3503_hw_config(void) pr_err("fail to request gpio %s\n", "USB_BOOT_EN_REV06"); } else { - gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); + gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 0); s3c_gpio_setpull(GPIO_USB_BOOT_EN_REV06, S3C_GPIO_PULL_NONE); } @@ -1752,7 +2206,7 @@ device_initcall(init_usbhub); static int host_port_enable(int port, int enable) { - int err, retry = 30; + int err; pr_info("[MDM] <%s> port(%d) control(%d)\n", __func__, port, enable); diff --git a/arch/arm/mach-exynos/board-midas-wlan.c b/arch/arm/mach-exynos/board-midas-wlan.c index 5d9a584..5d9a584 100755..100644 --- a/arch/arm/mach-exynos/board-midas-wlan.c +++ b/arch/arm/mach-exynos/board-midas-wlan.c diff --git a/arch/arm/mach-exynos/board-mobile.h b/arch/arm/mach-exynos/board-mobile.h index 54384d0..02cb8fb 100644 --- a/arch/arm/mach-exynos/board-mobile.h +++ b/arch/arm/mach-exynos/board-mobile.h @@ -9,6 +9,7 @@ extern void midas_camera_init(void); /* charger-manager */ extern struct charger_global_desc midas_charger_g_desc; extern struct platform_device midas_charger_manager; +extern void cm_change_fullbatt_uV(void); /* MAX77693 */ extern struct max77693_muic_data max77693_muic; diff --git a/arch/arm/mach-exynos/board-p10-wlan.c b/arch/arm/mach-exynos/board-p10-wlan.c deleted file mode 100644 index de4b352..0000000 --- a/arch/arm/mach-exynos/board-p10-wlan.c +++ /dev/null @@ -1,333 +0,0 @@ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/skbuff.h> -#include <linux/wlan_plat.h> - -#include <plat/devs.h> -#include <plat/sdhci.h> -#include <plat/gpio-cfg.h> -#include <mach/regs-gpio.h> -#include <mach/gpio.h> - -#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM - -#define WLAN_STATIC_SCAN_BUF0 5 -#define WLAN_STATIC_SCAN_BUF1 6 -#define WLAN_SCAN_BUF_SIZE (64 * 1024) -#define PREALLOC_WLAN_SEC_NUM 4 -#define PREALLOC_WLAN_BUF_NUM 160 -#define PREALLOC_WLAN_SECTION_HEADER 24 - -#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128) -#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128) -#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512) -#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024) - -#define DHD_SKB_HDRSIZE 336 -#define DHD_SKB_1PAGE_BUFSIZE ((PAGE_SIZE*1)-DHD_SKB_HDRSIZE) -#define DHD_SKB_2PAGE_BUFSIZE ((PAGE_SIZE*2)-DHD_SKB_HDRSIZE) -#define DHD_SKB_4PAGE_BUFSIZE ((PAGE_SIZE*4)-DHD_SKB_HDRSIZE) - -#define WLAN_SKB_BUF_NUM 17 - -static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM]; - -struct wlan_mem_prealloc { - void *mem_ptr; - unsigned long size; -}; - -static struct wlan_mem_prealloc wlan_mem_array[PREALLOC_WLAN_SEC_NUM] = { - {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)}, - {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)}, - {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)}, - {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)} -}; - -void *wlan_static_scan_buf0; -void *wlan_static_scan_buf1; - -static void *brcm_wlan_mem_prealloc(int section, unsigned long size) -{ - if (section == PREALLOC_WLAN_SEC_NUM) - return wlan_static_skb; - - if (section == WLAN_STATIC_SCAN_BUF0) - return wlan_static_scan_buf0; - - if (section == WLAN_STATIC_SCAN_BUF1) - return wlan_static_scan_buf1; - - if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM)) - return NULL; - - if (wlan_mem_array[section].size < size) - return NULL; - - return wlan_mem_array[section].mem_ptr; -} - -static int brcm_init_wlan_mem(void) -{ - int i; - int j; - - for (i = 0; i < 8; i++) { - wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_1PAGE_BUFSIZE); - if (!wlan_static_skb[i]) - goto err_skb_alloc; - } - - for (; i < 16; i++) { - wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_2PAGE_BUFSIZE); - if (!wlan_static_skb[i]) - goto err_skb_alloc; - } - - wlan_static_skb[i] = dev_alloc_skb(DHD_SKB_4PAGE_BUFSIZE); - if (!wlan_static_skb[i]) - goto err_skb_alloc; - - for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) { - wlan_mem_array[i].mem_ptr = - kmalloc(wlan_mem_array[i].size, GFP_KERNEL); - - if (!wlan_mem_array[i].mem_ptr) - goto err_mem_alloc; - } - - wlan_static_scan_buf0 = kmalloc (WLAN_SCAN_BUF_SIZE, GFP_KERNEL); - if (!wlan_static_scan_buf0) - goto err_mem_alloc; - - wlan_static_scan_buf1 = kmalloc (WLAN_SCAN_BUF_SIZE, GFP_KERNEL); - if (!wlan_static_scan_buf1) - goto err_mem_alloc; - - printk(KERN_INFO"%s: WIFI MEM Allocated\n", __func__); - return 0; - - err_mem_alloc: - pr_err("Failed to mem_alloc for WLAN\n"); - for (j = 0 ; j < i ; j++) - kfree(wlan_mem_array[j].mem_ptr); - - i = WLAN_SKB_BUF_NUM; - - err_skb_alloc: - pr_err("Failed to skb_alloc for WLAN\n"); - for (j = 0 ; j < i ; j++) - dev_kfree_skb(wlan_static_skb[j]); - - return -ENOMEM; -} -#endif /* CONFIG_BROADCOM_WIFI_RESERVED_MEM */ - -static unsigned int wlan_on_gpio_table[][4] = { - {GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_HIGH, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_HOST_WAKE, GPIO_WLAN_HOST_WAKE_AF, - GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN}, -}; - -static unsigned int wlan_off_gpio_table[][4] = { - {GPIO_WLAN_EN , GPIO_WLAN_EN_AF, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_HOST_WAKE, 0 , GPIO_LEVEL_NONE, S3C_GPIO_PULL_DOWN}, -}; - -static unsigned int wlan_sdio_on_table[][4] = { - {GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF, - GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF, - GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF, - GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF, - GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF, - GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF, - GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, -}; - -static unsigned int wlan_sdio_off_table[][4] = { - {GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, - {GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, -}; - -static void s3c_config_gpio_alive_table -(int array_size, unsigned int -(*gpio_table)[4]) -{ - u32 i, gpio; - printk(KERN_INFO"gpio_table = [%d] \r\n" , array_size); - for (i = 0; i < array_size; i++) { - gpio = gpio_table[i][0]; - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(gpio_table[i][1])); - s3c_gpio_setpull(gpio, gpio_table[i][3]); - if (gpio_table[i][2] != GPIO_LEVEL_NONE) - gpio_set_value(gpio, gpio_table[i][2]); - } -} - -static int brcm_wlan_power(int onoff) -{ - printk(KERN_INFO"------------------------------------------------"); - printk(KERN_INFO"------------------------------------------------\n"); - printk(KERN_INFO"%s Enter: power %s\n", __func__, onoff ? "on" : "off"); - if (onoff) { - s3c_config_gpio_alive_table - (ARRAY_SIZE(wlan_on_gpio_table), wlan_on_gpio_table); - udelay(200); - gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_HIGH); - printk(KERN_DEBUG"WLAN: GPIO_WLAN_EN = %d\n", - gpio_get_value(GPIO_WLAN_EN)); - } else { - gpio_set_value(GPIO_WLAN_EN, GPIO_LEVEL_LOW); - s3c_config_gpio_alive_table - (ARRAY_SIZE(wlan_off_gpio_table), wlan_off_gpio_table); - printk(KERN_DEBUG"WLAN: GPIO_WLAN_EN = %d\n", - gpio_get_value(GPIO_WLAN_EN)); - } - - return 0; -} - -static int brcm_wlan_reset(int onoff) -{ - gpio_set_value(GPIO_WLAN_EN, - onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); - return 0; -} - -static int brcm_wlan_set_carddetect(int onoff) -{ - if (onoff) { - s3c_config_gpio_alive_table( -ARRAY_SIZE(wlan_sdio_on_table), wlan_sdio_on_table); - } else { - s3c_config_gpio_alive_table( -ARRAY_SIZE(wlan_sdio_off_table), wlan_sdio_off_table); } - - udelay(200); - - mmc_force_presence_change(&s3c_device_hsmmc3); - msleep(500); /* wait for carddetect */ - return 0; -} - -/* Customized Locale table : OPTIONAL feature */ -#define WLC_CNTRY_BUF_SZ 4 -struct cntry_locales_custom { - char iso_abbrev[WLC_CNTRY_BUF_SZ]; - char custom_locale[WLC_CNTRY_BUF_SZ]; - int custom_locale_rev; -}; - -static struct cntry_locales_custom brcm_wlan_translate_custom_table[] = { - /* Table should be filled out based - on custom platform regulatory requirement */ - {"", "XY", 4}, /* universal */ - {"US", "US", 69}, /* input ISO "US" to : US regrev 69 */ - {"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */ - {"EU", "EU", 5}, /* European union countries */ - {"AT", "EU", 5}, - {"BE", "EU", 5}, - {"BG", "EU", 5}, - {"CY", "EU", 5}, - {"CZ", "EU", 5}, - {"DK", "EU", 5}, - {"EE", "EU", 5}, - {"FI", "EU", 5}, - {"FR", "EU", 5}, - {"DE", "EU", 5}, - {"GR", "EU", 5}, - {"HU", "EU", 5}, - {"IE", "EU", 5}, - {"IT", "EU", 5}, - {"LV", "EU", 5}, - {"LI", "EU", 5}, - {"LT", "EU", 5}, - {"LU", "EU", 5}, - {"MT", "EU", 5}, - {"NL", "EU", 5}, - {"PL", "EU", 5}, - {"PT", "EU", 5}, - {"RO", "EU", 5}, - {"SK", "EU", 5}, - {"SI", "EU", 5}, - {"ES", "EU", 5}, - {"SE", "EU", 5}, - {"GB", "EU", 5}, /* input ISO "GB" to : EU regrev 05 */ - {"IL", "IL", 0}, - {"CH", "CH", 0}, - {"TR", "TR", 0}, - {"NO", "NO", 0}, - {"KR", "XY", 3}, - {"AU", "XY", 3}, - {"CN", "XY", 3}, /* input ISO "CN" to : XY regrev 03 */ - {"TW", "XY", 3}, - {"AR", "XY", 3}, - {"MX", "XY", 3} -}; - -static void *brcm_wlan_get_country_code(char *ccode) -{ - int size = ARRAY_SIZE(brcm_wlan_translate_custom_table); - int i; - - if (!ccode) - return NULL; - - for (i = 0; i < size; i++) - if (strcmp(ccode, - brcm_wlan_translate_custom_table[i].iso_abbrev) == 0) - return &brcm_wlan_translate_custom_table[i]; - return &brcm_wlan_translate_custom_table[0]; -} - -static struct resource brcm_wlan_resources[] = { - [0] = { - .name = "bcmdhd_wlan_irq", - .start = IRQ_EINT(21), - .end = IRQ_EINT(21), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE, - }, -}; - -static struct wifi_platform_data brcm_wlan_control = { - .set_power = brcm_wlan_power, - .set_reset = brcm_wlan_reset, - .set_carddetect = brcm_wlan_set_carddetect, -#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM - .mem_prealloc = brcm_wlan_mem_prealloc, -#endif - .get_country_code = brcm_wlan_get_country_code, -}; - -static struct platform_device brcm_device_wlan = { - .name = "bcmdhd_wlan", - .id = 1, - .num_resources = ARRAY_SIZE(brcm_wlan_resources), - .resource = brcm_wlan_resources, - .dev = { - .platform_data = &brcm_wlan_control, - }, -}; - -int __init brcm_wlan_init(void) -{ - printk(KERN_INFO"%s: start\n", __func__); - -#ifdef CONFIG_BROADCOM_WIFI_RESERVED_MEM - brcm_init_wlan_mem(); -#endif - - return platform_device_register(&brcm_device_wlan); -} diff --git a/arch/arm/mach-exynos/board-p8ltevzw-modems.c b/arch/arm/mach-exynos/board-p8ltevzw-modems.c new file mode 100644 index 0000000..a2e0540 --- /dev/null +++ b/arch/arm/mach-exynos/board-p8ltevzw-modems.c @@ -0,0 +1,904 @@ +/* linux/arch/arm/mach-xxxx/board-p8vzw-modems.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/regulator/consumer.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/clk.h> + +/* inlcude platform specific file */ +#include <linux/platform_data/modem_na.h> +#include <mach/sec_modem.h> +#include <mach/gpio.h> +#include <mach/gpio-exynos4.h> +#include <plat/gpio-cfg.h> +#include <mach/regs-mem.h> +#include <plat/regs-srom.h> + +#include <plat/devs.h> +#include <plat/ehci.h> + + +#define IDPRAM_SIZE 0x4000 +#define IDPRAM_PHY_START 0x13A00000 +#define IDPRAM_PHY_END (IDPRAM_PHY_START + IDPRAM_SIZE) +#define MAGIC_DMDL 0x4445444C + +/*S5PV210 Interanl Dpram Special Function Register*/ +#define IDPRAM_MIFCON_INT2APEN (1<<2) +#define IDPRAM_MIFCON_INT2MSMEN (1<<3) +#define IDPRAM_MIFCON_DMATXREQEN_0 (1<<16) +#define IDPRAM_MIFCON_DMATXREQEN_1 (1<<17) +#define IDPRAM_MIFCON_DMARXREQEN_0 (1<<18) +#define IDPRAM_MIFCON_DMARXREQEN_1 (1<<19) +#define IDPRAM_MIFCON_FIXBIT (1<<20) + +#define IDPRAM_MIFPCON_ADM_MODE (1<<6) /* mux / demux mode */ + +#define IDPRAM_DMA_ADR_MASK 0x3FFF +#define IDPRAM_DMA_TX_ADR_0 /* shift 0 */ +#define IDPRAM_DMA_TX_ADR_1 /* shift 16 */ +#define IDPRAM_DMA_RX_ADR_0 /* shift 0 */ +#define IDPRAM_DMA_RX_ADR_1 /* shift 16 */ + +#define IDPRAM_SFR_PHYSICAL_ADDR 0x13A08000 +#define IDPRAM_SFR_SIZE 0x1C + +#define IDPRAM_ADDRESS_DEMUX + +static int __init init_modem(void); +static int p8_lte_ota_reset(void); + +struct idpram_sfr_reg { + unsigned int2ap; + unsigned int2msm; + unsigned mifcon; + unsigned mifpcon; + unsigned msmintclr; + unsigned dma_tx_adr; + unsigned dma_rx_adr; +}; + +/*S5PV210 Internal Dpram GPIO table*/ +struct idpram_gpio_data { + unsigned num; + unsigned cfg; + unsigned pud; + unsigned val; +}; + +static volatile void __iomem *s5pv310_dpram_sfr_va; + +static struct idpram_gpio_data idpram_gpio_address[] = { +#ifdef IDPRAM_ADDRESS_DEMUX + { + .num = EXYNOS4210_GPE1(0), /* MSM_ADDR 0 -12 */ + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE1(1), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE1(2), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE1(3), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE1(4), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE1(5), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE1(6), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE1(7), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE2(0), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE2(1), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE2(2), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE2(3), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE2(4), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE2(5), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, +#endif +}; + +static struct idpram_gpio_data idpram_gpio_data[] = { + { + .num = EXYNOS4210_GPE3(0), /* MSM_DATA 0 - 15 */ + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE3(1), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE3(2), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE3(3), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE3(4), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE3(5), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE3(6), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE3(7), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(0), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(1), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(2), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(3), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(4), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(5), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(6), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE4(7), + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, +}; + +static struct idpram_gpio_data idpram_gpio_init_control[] = { + { + .num = EXYNOS4210_GPE0(1), /* MDM_CSn */ + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE0(0), /* MDM_WEn */ + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE0(2), /* MDM_Rn */ + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, { + .num = EXYNOS4210_GPE0(3), /* MDM_IRQn */ + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_UP, + }, +#ifndef IDPRAM_ADDRESS_DEMUX + { + .num = EXYNOS4210_GPE0(4), /* MDM_ADVN */ + .cfg = S3C_GPIO_SFN(0x2), + .pud = S3C_GPIO_PULL_NONE, + }, +#endif +}; + +static void idpram_gpio_cfg(struct idpram_gpio_data *gpio) +{ + printk(KERN_DEBUG "MIF: idpram set gpio num=%d, cfg=0x%x, pud=%d, val=%d\n", + gpio->num, gpio->cfg, gpio->pud, gpio->val); + + s3c_gpio_cfgpin(gpio->num, gpio->cfg); + s3c_gpio_setpull(gpio->num, gpio->pud); + if (gpio->val) + gpio_set_value(gpio->num, gpio->val); +} + +static void idpram_gpio_init(void) +{ + int i; + +#ifdef IDPRAM_ADDRESS_DEMUX + for (i = 0; i < ARRAY_SIZE(idpram_gpio_address); i++) + idpram_gpio_cfg(&idpram_gpio_address[i]); +#endif + + for (i = 0; i < ARRAY_SIZE(idpram_gpio_data); i++) + idpram_gpio_cfg(&idpram_gpio_data[i]); + + for (i = 0; i < ARRAY_SIZE(idpram_gpio_init_control); i++) + idpram_gpio_cfg(&idpram_gpio_init_control[i]); +} + +static void idpram_sfr_init(void) +{ + volatile struct idpram_sfr_reg __iomem *sfr = s5pv310_dpram_sfr_va; + + sfr->mifcon = (IDPRAM_MIFCON_FIXBIT | IDPRAM_MIFCON_INT2APEN | + IDPRAM_MIFCON_INT2MSMEN); +#ifndef IDPRAM_ADDRESS_DEMUX + sfr->mifpcon = (IDPRAM_MIFPCON_ADM_MODE); +#endif +} + +static void idpram_init(void) +{ + struct clk *clk; + + /* enable internal dpram clock */ + clk = clk_get(NULL, "modem"); + if (!clk) + pr_err("MIF: idpram failed to get clock %s\n", __func__); + + clk_enable(clk); + + if (!s5pv310_dpram_sfr_va) { + s5pv310_dpram_sfr_va = (struct idpram_sfr_reg __iomem *) + ioremap_nocache(IDPRAM_SFR_PHYSICAL_ADDR, IDPRAM_SFR_SIZE); + if (!s5pv310_dpram_sfr_va) { + printk(KERN_ERR "MIF: idpram_sfr_base io-remap fail\n"); + /*iounmap(idpram_base);*/ + } + } + + idpram_sfr_init(); +} + +static void idpram_clr_intr(void) +{ + volatile struct idpram_sfr_reg __iomem *sfr = s5pv310_dpram_sfr_va; + sfr->msmintclr = 0xFF; +} + + +/* + magic_code + + access_enable + + fmt_tx_head + fmt_tx_tail + fmt_tx_buff + + raw_tx_head + raw_tx_tail + raw_tx_buff + + fmt_rx_head + fmt_rx_tail + fmt_rx_buff + + raw_rx_head + raw_rx_tail + raw_rx_buff + + padding + + mbx_cp2ap + + mbx_ap2cp + = 2 + + 2 + + 2 + 2 + 2044 + + 2 + 2 + 6128 + + 2 + 2 + 2044 + + 2 + 2 + 6128 + + 16 + + 2 + + 2 + = 16384 +*/ + +#define CBP_DP_FMT_TX_BUFF_SZ 2044 +#define CBP_DP_RAW_TX_BUFF_SZ 6128 +#define CBP_DP_FMT_RX_BUFF_SZ 2044 +#define CBP_DP_RAW_RX_BUFF_SZ 6128 + +#define MAX_CBP_IDPRAM_IPC_DEV (IPC_RAW + 1) /* FMT, RAW */ + +/* +** CDMA target platform data +*/ +static struct modem_io_t cdma_io_devices[] = { + [0] = { + .name = "multipdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .link = LINKDEV_DPRAM, + }, + [1] = { + .name = "cdma_ipc0", + .id = 0x1, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, + [2] = { + .name = "cdma_rfs0", + .id = 0x33, /* 0x13 (ch.id) | 0x20 (mask) */ + .format = IPC_RAW, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, + [3] = { + .name = "cdma_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, + [4] = { + .name = "cdma_rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_DPRAM, + }, + [5] = { + .name = "cdma_rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_DPRAM, + }, + [6] = { + .name = "cdma_rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_DPRAM, + }, + [7] = { + .name = "cdma_rmnet3", + .id = 0x2D, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_DPRAM, + }, + [8] = { + .name = "cdma_rmnet4", + .id = 0x27, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_DPRAM, + }, + [9] = { + .name = "cdma_rmnet5", /* DM Port IO device */ + .id = 0x3A, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, + [10] = { + .name = "cdma_rmnet6", /* AT CMD IO device */ + .id = 0x31, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, + [11] = { + .name = "cdma_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, + [12] = { + .name = "cdma_cplog", /* cp log io-device */ + .id = 0x3D, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, + [13] = { + .name = "cdma_router", /* AT commands */ + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .link = LINKDEV_DPRAM, + }, +}; + +static struct modem_data cdma_modem_data = { + .name = "cbp7.1", + + .gpio_cp_on = GPIO_PHONE_ON, + .gpio_cp_off = GPIO_VIA_PS_HOLD_OFF, + .gpio_cp_reset = GPIO_CP_RST, + .gpio_pda_active = GPIO_PDA_ACTIVE, + .gpio_phone_active = GPIO_PHONE_ACTIVE, + .gpio_ap_wakeup = GPIO_CP_AP_DPRAM_INT, + .gpio_mbx_intr = GPIO_VIA_DPRAM_INT_N, + + .modem_net = CDMA_NETWORK, + .modem_type = VIA_CBP71, + .link_type = LINKDEV_DPRAM, + + .num_iodevs = ARRAY_SIZE(cdma_io_devices), + .iodevs = cdma_io_devices, + + .clear_intr = idpram_clr_intr, + .ota_reset = p8_lte_ota_reset, + .sfr_init = idpram_sfr_init, + .align = 1, /* Adjust the IPC raw and Multi Raw HDLC buffer offsets */ +}; + +static struct resource cdma_modem_res[] = { + [0] = { + .name = "dpram", + .start = IDPRAM_PHY_START, + .end = IDPRAM_PHY_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "dpram_irq", + .start = IRQ_MODEM_IF, + .end = IRQ_MODEM_IF, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cdma_modem = { + .name = "modem_if", + .id = 1, + .num_resources = ARRAY_SIZE(cdma_modem_res), + .resource = cdma_modem_res, + .dev = { + .platform_data = &cdma_modem_data, + }, +}; +static int p8_lte_ota_reset(void) +{ + unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset; + unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on; + unsigned int *magickey_va; + int i; + + pr_err("[MODEM_IF] %s Modem OTA reset\n", __func__); + magickey_va = ioremap_nocache(IDPRAM_PHY_START, sizeof(unsigned int)); + if (!magickey_va) { + pr_err("%s: ioremap fail\n", __func__); + return -ENOMEM; + } + + gpio_set_value(gpio_cp_on, 1); + msleep(100); + gpio_set_value(gpio_cp_rst, 0); + + for (i = 0; i < 3; i++) { + *magickey_va = MAGIC_DMDL; + if (*magickey_va == MAGIC_DMDL) { + pr_err("magic key is ok!"); + break; + } + } + + msleep(500); + gpio_set_value(gpio_cp_rst, 1); + for (i = 0; i < 3; i++) { + *magickey_va = MAGIC_DMDL; + if (*magickey_va == MAGIC_DMDL) { + pr_err("magic key is ok!"); + break; + } + } + + iounmap(magickey_va); + + return 0; +} +static void config_cdma_modem_gpio(void) +{ + int err; + unsigned gpio_cp_on = cdma_modem_data.gpio_cp_on; + unsigned gpio_cp_off = cdma_modem_data.gpio_cp_off; + unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset; + unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active; + unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active; + unsigned gpio_ap_wakeup = cdma_modem_data.gpio_ap_wakeup; + + pr_info("MIF: <%s>\n", __func__); + + if (gpio_cp_on) { + err = gpio_request(gpio_cp_on, "VIACP_ON"); + if (err) + pr_err("fail to request gpio %s\n", "VIACP_ON"); + else + gpio_direction_output(gpio_cp_on, 0); + } + + if (gpio_cp_rst) { + err = gpio_request(gpio_cp_rst, "VAICP_RST"); + if (err) + pr_err("fail to request gpio %s\n", "VIACP_RST"); + else + gpio_direction_output(gpio_cp_rst, 0); + } + + if (gpio_cp_off) { + err = gpio_request(gpio_cp_off, "VAICP_OFF"); + if (err) + pr_err("fail to request gpio %s\n", "VIACP_OFF"); + else + gpio_direction_output(gpio_cp_off, 1); + } + + if (gpio_pda_active) { + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) + pr_err("fail to request gpio %s\n", "PDA_ACTIVE"); + else + gpio_direction_output(gpio_pda_active, 0); + } + + if (gpio_phone_active) { + err = gpio_request(gpio_phone_active, "PHONE_ACTIVE"); + if (err) { + pr_err("fail to request gpio %s\n", "PHONE_ACTIVE"); + } else { + s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); + } + } + if (gpio_ap_wakeup) { + err = gpio_request(GPIO_CP_AP_DPRAM_INT, "HOST_WAKEUP"); + if (err) { + pr_err("fail to request gpio %s\n", "HOST_WAKEUP"); + } else { + s3c_gpio_cfgpin(GPIO_CP_AP_DPRAM_INT, \ + S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(GPIO_CP_AP_DPRAM_INT, \ + S3C_GPIO_PULL_NONE); + } + } + +} + +/* lte target platform data */ +static struct modem_io_t lte_io_devices[] = { + [0] = { + .name = "lte_ipc0", + .id = 0x1, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .link = LINKDEV_USB, + }, + [1] = { + .name = "lte_rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_USB, + }, + [2] = { + .name = "lte_rfs0", + .id = 0x0, + .format = IPC_RFS, + .io_type = IODEV_MISC, + .link = LINKDEV_USB, + }, + [3] = { + .name = "lte_boot0", + .id = 0x0, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .link = LINKDEV_USB, + }, + [4] = { + .name = "lte_rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_USB, + }, + [5] = { + .name = "lte_rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_USB, + }, + [6] = { + .name = "lte_rmnet3", + .id = 0x2D, + .format = IPC_RAW, + .io_type = IODEV_NET, + .link = LINKDEV_USB, + }, + [7] = { + .name = "lte_multipdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .link = LINKDEV_USB, + }, + [8] = { + .name = "lte_rmnet4", /* DM Port io-device */ + .id = 0x3F, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .link = LINKDEV_USB, + }, + [9] = { + .name = "lte_ramdump0", + .id = 0x0, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .link = LINKDEV_USB, + }, +}; + +static struct modemlink_pm_data lte_link_pm_data = { + .name = "lte_link_pm", + + .gpio_link_enable = 0, + .gpio_link_active = GPIO_AP2LTE_STATUS, + .gpio_link_hostwake = GPIO_LTE2AP_WAKEUP, + .gpio_link_slavewake = GPIO_AP2LTE_WAKEUP, + + /* + .port_enable = host_port_enable, + .freqlock = ATOMIC_INIT(0), + .cpufreq_lock = exynos_cpu_frequency_lock, + .cpufreq_unlock = exynos_cpu_frequency_unlock, + */ +}; + +static struct modem_data lte_modem_data = { + .name = "cmc220", + .gpio_cp_on = GPIO_220_PMIC_PWRON, + .gpio_reset_req_n = 0, + .gpio_cp_reset = GPIO_CMC_RST, + .gpio_pda_active = 0,/*NOT YET CONNECTED*/ + .gpio_phone_active = GPIO_LTE_ACTIVE, + .gpio_cp_dump_int = GPIO_LTE_ACTIVE,/*TO BE CHECKED*/ + .gpio_cp_warm_reset = 0, + /*.gpio_cp_off = GPIO_220_PMIC_PWRHOLD_OFF,*/ +#ifdef CONFIG_LTE_MODEM_CMC220 + .gpio_cp_off = GPIO_LTE_PS_HOLD_OFF, + .gpio_slave_wakeup = GPIO_AP2LTE_WAKEUP, + .gpio_host_wakeup = GPIO_LTE2AP_WAKEUP, + .gpio_host_active = GPIO_AP2LTE_STATUS, +#endif + .modem_type = SEC_CMC220, + .link_type = LINKDEV_USB, + .modem_net = LTE_NETWORK, + + .num_iodevs = ARRAY_SIZE(lte_io_devices), + .iodevs = lte_io_devices, + + .link_pm_data = <e_link_pm_data, +}; + +static struct resource lte_modem_res[] = { + [0] = { + .name = "lte_phone_active", + /* phone active irq */ + .start = IRQ_LTE_ACTIVE, + .end = IRQ_LTE_ACTIVE, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "lte_host_wakeup", + /* host wakeup irq */ + .start = IRQ_LTE2AP_WAKEUP, + .end = IRQ_LTE2AP_WAKEUP, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device lte_modem_wake = { + .name = "modem_lte_wake", + .id = -1, +}; + +static struct platform_device lte_modem = { + .name = "modem_if", + .id = 2, + .num_resources = ARRAY_SIZE(lte_modem_res), + .resource = lte_modem_res, + .dev = { + .platform_data = <e_modem_data, + }, +}; + +static void lte_modem_cfg_gpio(void) +{ + unsigned gpio_cp_on = lte_modem_data.gpio_cp_on; + unsigned gpio_cp_rst = lte_modem_data.gpio_cp_reset; + unsigned gpio_phone_active = lte_modem_data.gpio_phone_active; +#ifdef CONFIG_LTE_MODEM_CMC220 + unsigned gpio_cp_off = lte_modem_data.gpio_cp_off; + unsigned gpio_slave_wakeup = lte_modem_data.gpio_slave_wakeup; + unsigned gpio_host_wakeup = lte_modem_data.gpio_host_wakeup; + unsigned gpio_host_active = lte_modem_data.gpio_host_active; +#endif + + if (gpio_cp_on) { + gpio_request(gpio_cp_on, "LTE_ON"); + gpio_direction_output(gpio_cp_on, 0); + s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); + } + + if (gpio_cp_rst) { + gpio_request(gpio_cp_rst, "LTE_RST"); + gpio_direction_output(gpio_cp_rst, 0); + s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); + } + + if (gpio_phone_active) { + gpio_request(gpio_phone_active, "LTE_ACTIVE"); + gpio_direction_input(gpio_phone_active); + s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_DOWN); + s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); + } + +#ifdef CONFIG_LTE_MODEM_CMC220 + if (gpio_cp_off) { + gpio_request(gpio_cp_off, "LTE_OFF"); + gpio_direction_output(gpio_cp_off, 1); + s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE); + } + + if (gpio_slave_wakeup) { + gpio_request(gpio_slave_wakeup, "LTE_SLAVE_WAKEUP"); + gpio_direction_output(gpio_slave_wakeup, 0); + s3c_gpio_setpull(gpio_slave_wakeup, S3C_GPIO_PULL_NONE); + } + + if (gpio_host_wakeup) { + gpio_request(gpio_host_wakeup, "LTE_HOST_WAKEUP"); + gpio_direction_input(gpio_host_wakeup); + s3c_gpio_setpull(gpio_host_wakeup, S3C_GPIO_PULL_DOWN); + s3c_gpio_cfgpin(gpio_host_wakeup, S3C_GPIO_SFN(0xF)); + } + + if (gpio_host_active) { + gpio_request(gpio_host_active, "LTE_HOST_ACTIVE"); + gpio_direction_output(gpio_host_active, 1); + s3c_gpio_setpull(gpio_host_active, S3C_GPIO_PULL_NONE); + } +#endif +} + +void set_host_states(struct platform_device *pdev, int type) +{ + int spin = 20; + + if (!type) { + gpio_direction_output(lte_modem_data.gpio_host_active, type); + return; + } + + if (gpio_get_value(lte_modem_data.gpio_host_wakeup)) { + gpio_direction_output(lte_modem_data.gpio_host_active, type); + mdelay(10); + while (spin--) { + if (!gpio_get_value(lte_modem_data.gpio_host_wakeup)) + break; + mdelay(10); + } + } else { + pr_err("mif: host wakeup is low\n"); + } +} + +int get_cp_active_state(void) +{ + return gpio_get_value(lte_modem_data.gpio_phone_active); +} + +void set_hsic_lpa_states(int states) +{ + int val = gpio_get_value(lte_modem_data.gpio_cp_reset); + + pr_info("mif: %s: states = %d\n", __func__, states); + + if (val) { + switch (states) { + case STATE_HSIC_LPA_ENTER: + /* + gpio_set_value(lte_modem_data.gpio_link_active, 0); + gpio_set_value(umts_modem_data.gpio_pda_active, 0); + pr_info(LOG_TAG "set hsic lpa enter: " + "active state (%d)" ", pda active (%d)\n", + gpio_get_value( + lte_modem_data.gpio_link_active), + gpio_get_value(umts_modem_data.gpio_pda_active) + ); + */ + break; + case STATE_HSIC_LPA_WAKE: + /* + gpio_set_value(umts_modem_data.gpio_pda_active, 1); + pr_info(LOG_TAG "set hsic lpa wake: " + "pda active (%d)\n", + gpio_get_value(umts_modem_data.gpio_pda_active) + ); + */ + break; + case STATE_HSIC_LPA_PHY_INIT: + /* + gpio_set_value(umts_modem_data.gpio_pda_active, 1); + gpio_set_value(lte_modem_data.gpio_link_slavewake, + 1); + pr_info(LOG_TAG "set hsic lpa phy init: " + "slave wake-up (%d)\n", + gpio_get_value( + lte_modem_data.gpio_link_slavewake) + ); + */ + break; + } + } +} + +/* lte_modem_wake must be registered before the ehci driver */ +void __init modem_p8ltevzw_init(void) +{ + lte_modem_wake.dev.platform_data = <e_modem_data; + platform_device_register(<e_modem_wake); +} + +static int __init init_modem(void) +{ + pr_err("[MDM] <%s>\n", __func__); + + /* interanl dpram gpio configure */ + idpram_gpio_init(); + idpram_init(); + config_cdma_modem_gpio(); + platform_device_register(&cdma_modem); + + /* lte gpios configuration */ + lte_modem_cfg_gpio(); + platform_device_register(<e_modem); + + return 0; +} +late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/board-s2plus-modems.c b/arch/arm/mach-exynos/board-s2plus-modems.c deleted file mode 100644 index 38ee0b2..0000000 --- a/arch/arm/mach-exynos/board-s2plus-modems.c +++ /dev/null @@ -1,479 +0,0 @@ -/* linux/arch/arm/mach-xxxx/board-m0-modems.c - * Copyright (C) 2010 Samsung Electronics. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Modem configuraiton for M0 (P-Q + XMM6262)*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <mach/gpio-exynos4.h> -#include <plat/gpio-cfg.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/delay.h> - -#include <linux/platform_data/modem.h> -#include <mach/sec_modem.h> - -extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); -/* umts target platform data */ -static struct modem_io_t umts_io_devices[] = { - [0] = { - .name = "umts_ipc0", - .id = 0x1, - .format = IPC_FMT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [1] = { - .name = "umts_rfs0", - .id = 0x41, - .format = IPC_RFS, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [2] = { - .name = "umts_boot0", - .id = 0x0, - .format = IPC_BOOT, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [3] = { - .name = "multipdp", - .id = 0x1, - .format = IPC_MULTI_RAW, - .io_type = IODEV_DUMMY, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [4] = { - .name = "rmnet0", - .id = 0x2A, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [5] = { - .name = "rmnet1", - .id = 0x2B, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [6] = { - .name = "rmnet2", - .id = 0x2C, - .format = IPC_RAW, - .io_type = IODEV_NET, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [7] = { - .name = "umts_router", - .id = 0x39, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [8] = { - .name = "umts_csd", - .id = 0x21, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [9] = { - .name = "umts_ramdump0", - .id = 0x0, - .format = IPC_RAMDUMP, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, - [10] = { - .name = "umts_loopback0", - .id = 0x3f, - .format = IPC_RAW, - .io_type = IODEV_MISC, - .links = LINKTYPE(LINKDEV_HSIC), - }, -}; - -/* To get modem state, register phone active irq using resource */ -static struct resource umts_modem_res[] = { -}; - -static int umts_link_ldo_enble(bool enable) -{ - /* Exynos HSIC V1.2 LDO was controlled by kernel */ - return 0; -} - -static int umts_link_reconnect(void); -static struct modemlink_pm_data modem_link_pm_data = { - .name = "link_pm", - .link_ldo_enable = umts_link_ldo_enble, - .gpio_link_enable = 0, - .gpio_link_active = GPIO_ACTIVE_STATE, - .gpio_link_hostwake = GPIO_IPC_HOST_WAKEUP, - .gpio_link_slavewake = GPIO_IPC_SLAVE_WAKEUP, - .link_reconnect = umts_link_reconnect, -}; - -static struct modemlink_pm_link_activectl active_ctl; - -static void xmm_gpio_revers_bias_clear(void); -static void xmm_gpio_revers_bias_restore(void); -static struct modem_data umts_modem_data = { - .name = "xmm6262", - - .gpio_cp_on = GPIO_PHONE_ON, - .gpio_reset_req_n = GPIO_CP_REQ_RESET, - .gpio_cp_reset = GPIO_CP_RST, - .gpio_pda_active = GPIO_PDA_ACTIVE, - .gpio_phone_active = GPIO_PHONE_ACTIVE, - .gpio_cp_dump_int = GPIO_CP_DUMP_INT, - .gpio_flm_uart_sel = 0, - .gpio_cp_warm_reset = 0, - - .modem_type = IMC_XMM6262, - .link_types = LINKTYPE(LINKDEV_HSIC), - .modem_net = UMTS_NETWORK, - .use_handover = false, - - .num_iodevs = ARRAY_SIZE(umts_io_devices), - .iodevs = umts_io_devices, - - .link_pm_data = &modem_link_pm_data, - .gpio_revers_bias_clear = xmm_gpio_revers_bias_clear, - .gpio_revers_bias_restore = xmm_gpio_revers_bias_restore, -}; - -/* HSIC specific function */ -void set_slave_wake(void) -{ - int spin = 20; - if (gpio_get_value(modem_link_pm_data.gpio_link_hostwake)) { - pr_info("[MODEM_IF]Slave Wake\n"); - if (gpio_get_value(modem_link_pm_data.gpio_link_slavewake)) { - gpio_direction_output( - modem_link_pm_data.gpio_link_slavewake, 0); - mdelay(10); - } - gpio_direction_output( - modem_link_pm_data.gpio_link_slavewake, 1); - mdelay(10); - while (spin--) { - if (!gpio_get_value( - modem_link_pm_data.gpio_link_hostwake)) - break; - mdelay(10); - } - } -} - -void set_host_states(struct platform_device *pdev, int type) -{ - if (active_ctl.gpio_initialized) { - if (type) - set_slave_wake(); - pr_err(LOG_TAG "Active States =%d, %s\n", type, pdev->name); - gpio_direction_output(modem_link_pm_data.gpio_link_active, - type); - } else - active_ctl.gpio_request_host_active = 1; -} - -void set_hsic_lpa_states(int states) -{ - int val = gpio_get_value(umts_modem_data.gpio_cp_reset); - - mif_trace("\n"); - - if (val) { - switch (states) { - case STATE_HSIC_LPA_ENTER: - gpio_set_value(modem_link_pm_data.gpio_link_active, 0); - gpio_set_value(umts_modem_data.gpio_pda_active, 0); - pr_info(LOG_TAG "set hsic lpa enter: " - "active state (%d)" ", pda active (%d)\n", - gpio_get_value( - modem_link_pm_data.gpio_link_active), - gpio_get_value(umts_modem_data.gpio_pda_active) - ); - break; - case STATE_HSIC_LPA_WAKE: - gpio_set_value(umts_modem_data.gpio_pda_active, 1); - pr_info(LOG_TAG "set hsic lpa wake: " - "pda active (%d)\n", - gpio_get_value(umts_modem_data.gpio_pda_active) - ); - break; - case STATE_HSIC_LPA_PHY_INIT: - gpio_set_value(umts_modem_data.gpio_pda_active, 1); - gpio_set_value(modem_link_pm_data.gpio_link_slavewake, - 1); - pr_info(LOG_TAG "set hsic lpa phy init: " - "slave wake-up (%d)\n", - gpio_get_value( - modem_link_pm_data.gpio_link_slavewake) - ); - break; - } - } -} - -int get_cp_active_state(void) -{ - return gpio_get_value(umts_modem_data.gpio_phone_active); -} - -static int umts_link_reconnect(void) -{ - if (gpio_get_value(umts_modem_data.gpio_phone_active) && - gpio_get_value(umts_modem_data.gpio_cp_reset)) { - pr_info("[MODEM_IF] trying reconnect link\n"); - gpio_set_value(modem_link_pm_data.gpio_link_active, 0); - mdelay(10); - set_slave_wake(); - gpio_set_value(modem_link_pm_data.gpio_link_active, 1); - } else - return -ENODEV; - - return 0; -} - -/* if use more than one modem device, then set id num */ -static struct platform_device umts_modem = { - .name = "modem_if", - .id = -1, - .num_resources = ARRAY_SIZE(umts_modem_res), - .resource = umts_modem_res, - .dev = { - .platform_data = &umts_modem_data, - }, -}; - -static void umts_modem_cfg_gpio(void) -{ - int err = 0; - - unsigned gpio_reset_req_n = umts_modem_data.gpio_reset_req_n; - unsigned gpio_cp_on = umts_modem_data.gpio_cp_on; - unsigned gpio_cp_rst = umts_modem_data.gpio_cp_reset; - unsigned gpio_pda_active = umts_modem_data.gpio_pda_active; - unsigned gpio_phone_active = umts_modem_data.gpio_phone_active; - unsigned gpio_cp_dump_int = umts_modem_data.gpio_cp_dump_int; - unsigned gpio_flm_uart_sel = umts_modem_data.gpio_flm_uart_sel; - unsigned irq_phone_active = umts_modem_res[0].start; - - if (gpio_reset_req_n) { - err = gpio_request(gpio_reset_req_n, "RESET_REQ_N"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "RESET_REQ_N", err); - } - s3c_gpio_slp_cfgpin(gpio_reset_req_n, S3C_GPIO_SLP_OUT1); - gpio_direction_output(gpio_reset_req_n, 0); - } - - if (gpio_cp_on) { - err = gpio_request(gpio_cp_on, "CP_ON"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "CP_ON", err); - } - gpio_direction_output(gpio_cp_on, 0); - } - - if (gpio_cp_rst) { - err = gpio_request(gpio_cp_rst, "CP_RST"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "CP_RST", err); - } - s3c_gpio_slp_cfgpin(gpio_cp_rst, S3C_GPIO_SLP_OUT1); - gpio_direction_output(gpio_cp_rst, 0); - } - - if (gpio_pda_active) { - err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "PDA_ACTIVE", err); - } - gpio_direction_output(gpio_pda_active, 0); - } - - if (gpio_phone_active) { - err = gpio_request(gpio_phone_active, "PHONE_ACTIVE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "PHONE_ACTIVE", err); - } - gpio_direction_input(gpio_phone_active); - pr_err(LOG_TAG "check phone active = %d\n", irq_phone_active); - } - - if (gpio_cp_dump_int) { - err = gpio_request(gpio_cp_dump_int, "CP_DUMP_INT"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "CP_DUMP_INT", err); - } - gpio_direction_input(gpio_cp_dump_int); - } - - if (gpio_flm_uart_sel) { - err = gpio_request(gpio_flm_uart_sel, "GPS_UART_SEL"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "GPS_UART_SEL", err); - } - gpio_direction_output(gpio_reset_req_n, 0); - } - - if (gpio_phone_active) - irq_set_irq_type(gpio_to_irq(gpio_phone_active), - IRQ_TYPE_LEVEL_HIGH); - /* set low unused gpios between AP and CP */ - err = gpio_request(GPIO_FLM_RXD, "FLM_RXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_RXD", - err); - else { - gpio_direction_output(GPIO_FLM_RXD, 0); - s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); - } - err = gpio_request(GPIO_FLM_TXD, "FLM_TXD"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "FLM_TXD", - err); - else { - gpio_direction_output(GPIO_FLM_TXD, 0); - s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); - } - err = gpio_request(GPIO_SUSPEND_REQUEST, "SUS_REQ"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "SUS_REQ", - err); - else { - gpio_direction_output(GPIO_SUSPEND_REQUEST, 0); - s3c_gpio_setpull(GPIO_SUSPEND_REQUEST, S3C_GPIO_PULL_NONE); - } - err = gpio_request(GPIO_GPS_CNTL, "GPS_CNTL"); - if (err) - pr_err(LOG_TAG "fail to request gpio %s : %d\n", "GPS_CNTL", - err); - else { - gpio_direction_output(GPIO_GPS_CNTL, 0); - s3c_gpio_setpull(GPIO_GPS_CNTL, S3C_GPIO_PULL_NONE); - } - - pr_info(LOG_TAG "umts_modem_cfg_gpio done\n"); -} - -static void xmm_gpio_revers_bias_clear(void) -{ - gpio_direction_output(umts_modem_data.gpio_pda_active, 0); - gpio_direction_output(umts_modem_data.gpio_phone_active, 0); - gpio_direction_output(umts_modem_data.gpio_cp_dump_int, 0); - gpio_direction_output(modem_link_pm_data.gpio_link_active, 0); - gpio_direction_output(modem_link_pm_data.gpio_link_hostwake, 0); - gpio_direction_output(modem_link_pm_data.gpio_link_slavewake, 0); - - msleep(20); -} - -static void xmm_gpio_revers_bias_restore(void) -{ - s3c_gpio_cfgpin(umts_modem_data.gpio_phone_active, S3C_GPIO_SFN(0xF)); - s3c_gpio_cfgpin(modem_link_pm_data.gpio_link_hostwake, - S3C_GPIO_SFN(0xF)); - gpio_direction_input(umts_modem_data.gpio_cp_dump_int); -} - -static void modem_link_pm_config_gpio(void) -{ - int err = 0; - - unsigned gpio_link_enable = modem_link_pm_data.gpio_link_enable; - unsigned gpio_link_active = modem_link_pm_data.gpio_link_active; - unsigned gpio_link_hostwake = modem_link_pm_data.gpio_link_hostwake; - unsigned gpio_link_slavewake = modem_link_pm_data.gpio_link_slavewake; - /* unsigned irq_link_hostwake = umts_modem_res[1].start; */ - - if (gpio_link_enable) { - err = gpio_request(gpio_link_enable, "LINK_EN"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "LINK_EN", err); - } - gpio_direction_output(gpio_link_enable, 0); - } - - if (gpio_link_active) { - err = gpio_request(gpio_link_active, "LINK_ACTIVE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "LINK_ACTIVE", err); - } - gpio_direction_output(gpio_link_active, 0); - } - - if (gpio_link_hostwake) { - err = gpio_request(gpio_link_hostwake, "HOSTWAKE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "HOSTWAKE", err); - } - gpio_direction_input(gpio_link_hostwake); - } - - if (gpio_link_slavewake) { - err = gpio_request(gpio_link_slavewake, "SLAVEWAKE"); - if (err) { - pr_err(LOG_TAG "fail to request gpio %s : %d\n", - "SLAVEWAKE", err); - } - gpio_direction_output(gpio_link_slavewake, 0); - } - - if (gpio_link_hostwake) - irq_set_irq_type(gpio_to_irq(gpio_link_hostwake), - IRQ_TYPE_EDGE_BOTH); - - active_ctl.gpio_initialized = 1; - if (active_ctl.gpio_request_host_active) { - pr_err(LOG_TAG "Active States = 1, %s\n", __func__); - gpio_direction_output(modem_link_pm_data.gpio_link_active, 1); - } - - pr_info(LOG_TAG "modem_link_pm_config_gpio done\n"); -} - -static int __init init_modem(void) -{ - int ret; - pr_info(LOG_TAG "init_modem\n"); - - /* umts gpios configuration */ - umts_modem_cfg_gpio(); - modem_link_pm_config_gpio(); - ret = platform_device_register(&umts_modem); - if (ret < 0) - return ret; - - return ret; -} -late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/board-t0cu-duos-modems.c b/arch/arm/mach-exynos/board-t0cu-duos-modems.c new file mode 100644 index 0000000..30e93ca --- /dev/null +++ b/arch/arm/mach-exynos/board-t0cu-duos-modems.c @@ -0,0 +1,1160 @@ +/* linux/arch/arm/mach-xxxx/board-t0cu-duos-modems.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Modem configuraiton for T0_CU (P-Q + ESC6270)*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <mach/gpio-exynos4.h> +#include <plat/gpio-cfg.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/delay.h> + +#include <linux/platform_data/modem.h> +#include <mach/sec_modem.h> + +#if defined(CONFIG_LINK_DEVICE_PLD) +#include <linux/spi/spi.h> +#include <mach/pld_pdata.h> +#endif + +#if defined(CONFIG_GSM_MODEM_ESC6270) +#include <linux/interrupt.h> +#include <linux/io.h> +#include <mach/gpio.h> +#include <mach/gpio-exynos4.h> +#include <plat/gpio-cfg.h> +#include <mach/regs-mem.h> +#include <plat/regs-srom.h> + +#define SROM_CS0_BASE 0x04000000 +#define SROM_WIDTH 0x01000000 + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define SROM_NUM_ADDR_BITS 15 +#else +#define SROM_NUM_ADDR_BITS 14 +#endif + +/* + * For SROMC Configuration: + * SROMC_ADDR_BYTE enable for byte access + */ +#define SROMC_DATA_16 0x1 +#define SROMC_ADDR_BYTE 0x2 +#define SROMC_WAIT_EN 0x4 +#define SROMC_BYTE_EN 0x8 +#define SROMC_MASK 0xF + +/* Memory attributes */ +enum sromc_attr { + MEM_DATA_BUS_8BIT = 0x00000000, + MEM_DATA_BUS_16BIT = 0x00000001, + MEM_BYTE_ADDRESSABLE = 0x00000002, + MEM_WAIT_EN = 0x00000004, + MEM_BYTE_EN = 0x00000008, + +}; + +/* DPRAM configuration */ +struct sromc_cfg { + enum sromc_attr attr; + unsigned size; + unsigned csn; /* CSn # */ + unsigned addr; /* Start address (physical) */ + unsigned end; /* End address (physical) */ +}; + +/* DPRAM access timing configuration */ +struct sromc_access_cfg { + u32 tacs; /* Address set-up before CSn */ + u32 tcos; /* Chip selection set-up before OEn */ + u32 tacc; /* Access cycle */ + u32 tcoh; /* Chip selection hold on OEn */ + u32 tcah; /* Address holding time after CSn */ + u32 tacp; /* Page mode access cycle at Page mode */ + u32 pmc; /* Page Mode config */ +}; + +/* For MDM6600 EDPRAM (External DPRAM) */ +#if defined(CONFIG_LINK_DEVICE_PLD) +#define MSM_EDPRAM_SIZE 0x10000 /* 8 KB (virtual)*/ +#else +#define MSM_EDPRAM_SIZE 0x4000 /* 16 KB */ +#endif + + +#define INT_MASK_REQ_ACK_F 0x0020 +#define INT_MASK_REQ_ACK_R 0x0010 +#define INT_MASK_RES_ACK_F 0x0008 +#define INT_MASK_RES_ACK_R 0x0004 +#define INT_MASK_SEND_F 0x0002 +#define INT_MASK_SEND_R 0x0001 + +#define INT_MASK_REQ_ACK_RFS 0x0400 /* Request RES_ACK_RFS */ +#define INT_MASK_RES_ACK_RFS 0x0200 /* Response of REQ_ACK_RFS */ +#define INT_MASK_SEND_RFS 0x0100 /* Indicate sending RFS data */ + + +#if (MSM_EDPRAM_SIZE == 0x4000) +/* + magic_code + + access_enable + + fmt_tx_head + fmt_tx_tail + fmt_tx_buff + + raw_tx_head + raw_tx_tail + raw_tx_buff + + fmt_rx_head + fmt_rx_tail + fmt_rx_buff + + raw_rx_head + raw_rx_tail + raw_rx_buff + + padding + + mbx_cp2ap + + mbx_ap2cp + = 2 + + 2 + + 2 + 2 + 2044 + + 2 + 2 + 6128 + + 2 + 2 + 2044 + + 2 + 2 + 6128 + + 16 + + 2 + + 2 + = 16384 +*/ + +#define MSM_DP_FMT_TX_BUFF_SZ 2044 +#define MSM_DP_RAW_TX_BUFF_SZ 6128 +#define MSM_DP_FMT_RX_BUFF_SZ 2044 +#define MSM_DP_RAW_RX_BUFF_SZ 6128 + +#define MAX_MSM_EDPRAM_IPC_DEV 2 /* FMT, RAW */ + +struct msm_edpram_ipc_cfg { + u16 magic; + u16 access; + + u16 fmt_tx_head; + u16 fmt_tx_tail; + u8 fmt_tx_buff[MSM_DP_FMT_TX_BUFF_SZ]; + + u16 raw_tx_head; + u16 raw_tx_tail; + u8 raw_tx_buff[MSM_DP_RAW_TX_BUFF_SZ]; + + u16 fmt_rx_head; + u16 fmt_rx_tail; + u8 fmt_rx_buff[MSM_DP_FMT_RX_BUFF_SZ]; + + u16 raw_rx_head; + u16 raw_rx_tail; + u8 raw_rx_buff[MSM_DP_RAW_RX_BUFF_SZ]; + + u8 padding[16]; + u16 mbx_ap2cp; + u16 mbx_cp2ap; +}; + + +/* +------------------ +Buffer : 15KByte +------------------ +Reserved: 1014Byte +------------------ +SIZE: 2Byte +------------------ +TAG: 2Byte +------------------ +COUNT: 2Byte +------------------ +AP -> CP Intr : 2Byte +------------------ +CP -> AP Intr : 2Byte +------------------ +*/ +#define DP_BOOT_CLEAR_OFFSET 4 +#define DP_BOOT_RSRVD_OFFSET 0x3C00 +#define DP_BOOT_SIZE_OFFSET 0x3FF6 +#define DP_BOOT_TAG_OFFSET 0x3FF8 +#define DP_BOOT_COUNT_OFFSET 0x3FFA + +#define DP_BOOT_FRAME_SIZE_LIMIT 0x3C00 /* 15KB = 15360byte = 0x3C00 */ + +#elif (MSM_EDPRAM_SIZE == 0x10000) + +/* + mbx_ap2cp + 0x0 + magic_code + + access_enable + + padding + + mbx_cp2ap + 0x1000 + magic_code + + access_enable + + padding + + fmt_tx_head + fmt_tx_tail + fmt_tx_buff + 0x2000 + raw_tx_head + raw_tx_tail + raw_tx_buff + + fmt_rx_head + fmt_rx_tail + fmt_rx_buff + 0x3000 + raw_rx_head + raw_rx_tail + raw_rx_buff + + = 2 + + 4094 + + 2 + + 4094 + + 2 + + 2 + + 2 + 2 + 1020 + + 2 + 2 + 3064 + + 2 + 2 + 1020 + + 2 + 2 + 3064 + */ + +#define MSM_DP_FMT_TX_BUFF_SZ 1024 +#define MSM_DP_RAW_TX_BUFF_SZ 3072 +#define MSM_DP_FMT_RX_BUFF_SZ 1024 +#define MSM_DP_RAW_RX_BUFF_SZ 3072 + +#define MAX_MSM_EDPRAM_IPC_DEV 2 /* FMT, RAW */ + +struct msm_edpram_ipc_cfg { + u16 mbx_ap2cp; + u16 magic_ap2cp; + u16 access_ap2cp; + u16 fmt_tx_head; + u16 raw_tx_head; + u16 fmt_rx_tail; + u16 raw_rx_tail; + u16 temp1; + u8 padding1[4080]; + + u16 mbx_cp2ap; + u16 magic_cp2ap; + u16 access_cp2ap; + u16 fmt_tx_tail; + u16 raw_tx_tail; + u16 fmt_rx_head; + u16 raw_rx_head; + u16 temp2; + u8 padding2[4080]; + + u8 fmt_tx_buff[MSM_DP_FMT_TX_BUFF_SZ]; + u8 raw_tx_buff[MSM_DP_RAW_TX_BUFF_SZ]; + u8 fmt_rx_buff[MSM_DP_FMT_RX_BUFF_SZ]; + u8 raw_rx_buff[MSM_DP_RAW_RX_BUFF_SZ]; + + u8 padding3[16384]; + + u16 address_buffer; +}; + +#define DP_BOOT_CLEAR_OFFSET 0 +#define DP_BOOT_RSRVD_OFFSET 0 +#define DP_BOOT_SIZE_OFFSET 0x2 +#define DP_BOOT_TAG_OFFSET 0x4 +#define DP_BOOT_COUNT_OFFSET 0x6 + +#define DP_BOOT_FRAME_SIZE_LIMIT 0x1000 /* 15KB = 15360byte = 0x3C00 */ + +#else +/* +------------------ +Buffer : 31KByte +------------------ +Reserved: 1014Byte +------------------ +SIZE: 2Byte +------------------ +TAG: 2Byte +------------------ +COUNT: 2Byte +------------------ +AP -> CP Intr : 2Byte +------------------ +CP -> AP Intr : 2Byte +------------------ +*/ +#define DP_BOOT_CLEAR_OFFSET 4 +#define DP_BOOT_RSRVD_OFFSET 0x7C00 +#define DP_BOOT_SIZE_OFFSET 0x7FF6 +#define DP_BOOT_TAG_OFFSET 0x7FF8 +#define DP_BOOT_COUNT_OFFSET 0x7FFA + +#define DP_BOOT_FRAME_SIZE_LIMIT 0x7C00 /* 31KB = 31744byte = 0x7C00 */ +#endif + +static struct dpram_ipc_map gsm_ipc_map; + +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct sromc_cfg gsm_edpram_cfg = { + .attr = (MEM_DATA_BUS_8BIT), + .size = 0x10000, +}; +#else +static struct sromc_cfg gsm_edpram_cfg = { + .attr = (MEM_DATA_BUS_16BIT | MEM_WAIT_EN | MEM_BYTE_EN), + .size = MSM_EDPRAM_SIZE, +}; +#endif + +static struct sromc_access_cfg gsm_edpram_access_cfg[] = { + [DPRAM_SPEED_LOW] = { + .tacs = 0x2 << 28, + .tcos = 0x2 << 24, + .tacc = 0x3 << 16, + .tcoh = 0x2 << 12, + .tcah = 0x2 << 8, + .tacp = 0x2 << 4, + .pmc = 0x0 << 0, + }, +}; + +static struct modemlink_dpram_control gsm_edpram_ctrl = { + .dp_type = EXT_DPRAM, + + .dpram_irq = ESC_DPRAM_INT_IRQ, + .dpram_irq_flags = IRQF_TRIGGER_FALLING, + + .max_ipc_dev = IPC_RFS, + .ipc_map = &gsm_ipc_map, + + .boot_size_offset = DP_BOOT_SIZE_OFFSET, + .boot_tag_offset = DP_BOOT_TAG_OFFSET, + .boot_count_offset = DP_BOOT_COUNT_OFFSET, + .max_boot_frame_size = DP_BOOT_FRAME_SIZE_LIMIT, + +#if defined(CONFIG_LINK_DEVICE_PLD) + .aligned = 1, +#endif +}; + +/* +** GSM target platform data +*/ +#if defined(CONFIG_LINK_DEVICE_PLD) +static struct modem_io_t gsm_io_devices[] = { + [0] = { + .name = "gsm_ipc0", + .id = 0x01, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [1] = { + .name = "gsm_rfs0", + .id = 0x28, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [2] = { + .name = "gsm_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [3] = { + .name = "gsm_multi_pdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_PLD), + }, + [4] = { + .name = "gsm_rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [5] = { + .name = "gsm_rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [6] = { + .name = "gsm_rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [7] = { + .name = "gsm_router", + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_PLD), + }, + [8] = { + .name = "gsm_csd", + .id = 0x21, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [9] = { + .name = "gsm_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, + [10] = { + .name = "gsm_loopback0", + .id = 0x3F, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_PLD), + }, +}; +#else +static struct modem_io_t gsm_io_devices[] = { + [0] = { + .name = "gsm_ipc0", + .id = 0x01, + .format = IPC_FMT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [1] = { + .name = "gsm_rfs0", + .id = 0x28, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [2] = { + .name = "gsm_boot0", + .id = 0x1, + .format = IPC_BOOT, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [3] = { + .name = "gsm_multi_pdp", + .id = 0x1, + .format = IPC_MULTI_RAW, + .io_type = IODEV_DUMMY, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [4] = { + .name = "gsm_rmnet0", + .id = 0x2A, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [5] = { + .name = "gsm_rmnet1", + .id = 0x2B, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [6] = { + .name = "gsm_rmnet2", + .id = 0x2C, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [7] = { + .name = "gsm_router", + .id = 0x39, + .format = IPC_RAW, + .io_type = IODEV_NET, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [8] = { + .name = "gsm_csd", + .id = 0x21, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [9] = { + .name = "gsm_ramdump0", + .id = 0x1, + .format = IPC_RAMDUMP, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, + [10] = { + .name = "gsm_loopback0", + .id = 0x3F, + .format = IPC_RAW, + .io_type = IODEV_MISC, + .links = LINKTYPE(LINKDEV_DPRAM), + }, +}; +#endif + +static struct modem_data gsm_modem_data = { + .name = "esc6270", + + .gpio_cp_on = GPIO_CP2_MSM_PWRON, + .gpio_cp_off = 0, + .gpio_reset_req_n = 0, /* GPIO_CP_MSM_PMU_RST, */ + .gpio_cp_reset = GPIO_CP2_MSM_RST, + .gpio_pda_active = 0, + .gpio_phone_active = GPIO_ESC_PHONE_ACTIVE, + .gpio_flm_uart_sel = GPIO_BOOT_SW_SEL_CP2, + + .gpio_dpram_int = GPIO_ESC_DPRAM_INT, + + .gpio_cp_dump_int = 0, + .gpio_cp_warm_reset = 0, + +#if defined(CONFIG_LINK_DEVICE_PLD) + .gpio_fpga1_creset = GPIO_FPGA1_CRESET, + .gpio_fpga1_cdone = GPIO_FPGA1_CDONE, + .gpio_fpga1_rst_n = GPIO_FPGA1_RST_N, + .gpio_fpga1_cs_n = GPIO_FPGA1_CS_N, +#endif + + .use_handover = false, + + .modem_net = CDMA_NETWORK, + .modem_type = QC_ESC6270, +#if defined(CONFIG_LINK_DEVICE_PLD) + .link_types = LINKTYPE(LINKDEV_PLD), +#else + .link_types = LINKTYPE(LINKDEV_DPRAM), +#endif + + .link_name = "esc6270_edpram", + .dpram_ctl = &gsm_edpram_ctrl, + + .ipc_version = SIPC_VER_41, + + .num_iodevs = ARRAY_SIZE(gsm_io_devices), + .iodevs = gsm_io_devices, +}; + +static struct resource gsm_modem_res[] = { + [0] = { + .name = "cp_active_irq", + .start = ESC_PHONE_ACTIVE_IRQ, + .end = ESC_PHONE_ACTIVE_IRQ, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .name = "dpram_irq", + .start = ESC_DPRAM_INT_IRQ, + .end = ESC_DPRAM_INT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device gsm_modem = { + .name = "modem_if", + .id = 2, + .num_resources = ARRAY_SIZE(gsm_modem_res), + .resource = gsm_modem_res, + .dev = { + .platform_data = &gsm_modem_data, + }, +}; + +static void config_dpram_port_gpio(void) +{ + int addr_bits = SROM_NUM_ADDR_BITS; + + pr_info("[MDM] <%s> address line = %d bits\n", __func__, addr_bits); + + /* + ** Config DPRAM address/data GPIO pins + */ + + /* Set GPIO for dpram address */ + switch (addr_bits) { + case 0: + break; + + case 13 ... 14: + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR, + S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0), + addr_bits - EXYNOS4_GPIO_Y3_NR, + S3C_GPIO_SFN(2)); + pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n", + __func__, addr_bits - EXYNOS4_GPIO_Y3_NR); + break; + + case 15: + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY3(0), EXYNOS4_GPIO_Y3_NR, + S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY4(0), EXYNOS4_GPIO_Y4_NR, + S3C_GPIO_SFN(2)); + pr_info("[MDM] <%s> last data gpio EXYNOS4_GPY4(0) ~ %d\n", + __func__, EXYNOS4_GPIO_Y4_NR); + break; + + default: + pr_err("[MDM/E] <%s> Invalid addr_bits!!!\n", __func__); + return; + } + + /* Set GPIO for dpram data - 16bit */ +#if defined(CONFIG_LINK_DEVICE_PLD) + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2)); +#elif defined(CONFIG_LINK_DEVICE_DPRAM) + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY5(0), 8, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4_GPY6(0), 8, S3C_GPIO_SFN(2)); +#endif + + /* Setup SROMC CSn pins */ + s3c_gpio_cfgpin(GPIO_DPRAM_CSN1, S3C_GPIO_SFN(2)); + +#if defined(CONFIG_GSM_MODEM_ESC6270) + s3c_gpio_cfgpin(GPIO_DPRAM_CSN0, S3C_GPIO_SFN(2)); +#endif + + /* Config OEn, WEn */ + s3c_gpio_cfgrange_nopull(GPIO_DPRAM_REN, 2, S3C_GPIO_SFN(2)); + + /* Config LBn, UBn */ + s3c_gpio_cfgrange_nopull(GPIO_DPRAM_LBN, 2, S3C_GPIO_SFN(2)); + + /* Config BUSY */ +#if !defined(CONFIG_LINK_DEVICE_PLD) + s3c_gpio_cfgpin(GPIO_DPRAM_BUSY, S3C_GPIO_SFN(2)); +#endif +} + + +static void init_sromc(void) +{ + struct clk *clk = NULL; + + /* SROMC clk enable */ + clk = clk_get(NULL, "sromc"); + if (!clk) { + pr_err("[MDM/E] <%s> SROMC clock gate fail\n", __func__); + return; + } + clk_enable(clk); +} + +static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, + struct sromc_access_cfg *acc_cfg) +{ + unsigned bw = 0; + unsigned bc = 0; + void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); + + pr_err("[MDM] <%s> SROMC settings for CS%d...\n", __func__, csn); + + bw = __raw_readl(S5P_SROM_BW); + bc = __raw_readl(bank_sfr); + pr_err("[MDM] <%s> Old SROMC settings = BW(0x%08X), BC%d(0x%08X)\n", + __func__, bw, csn, bc); + + /* Set the BW control field for the CSn */ + bw &= ~(SROMC_MASK << (csn * 4)); + + if (cfg->attr & MEM_DATA_BUS_16BIT) + bw |= (SROMC_DATA_16 << (csn * 4)); + + if (cfg->attr & MEM_WAIT_EN) + bw |= (SROMC_WAIT_EN << (csn * 4)); + + if (cfg->attr & MEM_BYTE_EN) + bw |= (SROMC_BYTE_EN << (csn * 4)); + + writel(bw, S5P_SROM_BW); + + /* Set SROMC memory access timing for the CSn */ + bc = acc_cfg->tacs | acc_cfg->tcos | acc_cfg->tacc | + acc_cfg->tcoh | acc_cfg->tcah | acc_cfg->tacp | acc_cfg->pmc; + + writel(bc, bank_sfr); + + /* Verify SROMC settings */ + bw = __raw_readl(S5P_SROM_BW); + bc = __raw_readl(bank_sfr); + pr_err("[MDM] <%s> New SROMC settings = BW(0x%08X), BC%d(0x%08X)\n", + __func__, bw, csn, bc); +} + + +void config_gsm_modem_gpio(void) +{ + int err = 0; + unsigned gpio_cp_on = gsm_modem_data.gpio_cp_on; + unsigned gpio_cp_off = gsm_modem_data.gpio_cp_off; + unsigned gpio_rst_req_n = gsm_modem_data.gpio_reset_req_n; + unsigned gpio_cp_rst = gsm_modem_data.gpio_cp_reset; + unsigned gpio_pda_active = gsm_modem_data.gpio_pda_active; + unsigned gpio_phone_active = gsm_modem_data.gpio_phone_active; + unsigned gpio_flm_uart_sel = gsm_modem_data.gpio_flm_uart_sel; + unsigned gpio_dpram_int = gsm_modem_data.gpio_dpram_int; + +#if defined(CONFIG_LINK_DEVICE_PLD) + unsigned gpio_fpga1_creset = gsm_modem_data.gpio_fpga1_creset; + unsigned gpio_fpga1_cdone = gsm_modem_data.gpio_fpga1_cdone; + unsigned gpio_fpga1_rst_n = gsm_modem_data.gpio_fpga1_rst_n; + unsigned gpio_fpga1_cs_n = gsm_modem_data.gpio_fpga1_cs_n; +#endif + + pr_err("[MODEMS] <%s>\n", __func__); + + if (gpio_pda_active) { + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "PDA_ACTIVE", gpio_pda_active, err); + } else { + gpio_direction_output(gpio_pda_active, 1); + s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_pda_active, 0); + } + } + + if (gpio_phone_active) { + err = gpio_request(gpio_phone_active, "ESC_ACTIVE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_ACTIVE", gpio_phone_active, err); + } else { + s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH); + } + } + + if (gpio_flm_uart_sel) { + err = gpio_request(gpio_flm_uart_sel, "BOOT_SW_SEL2"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "BOOT_SW_SEL2", gpio_flm_uart_sel, err); + } else { + gpio_direction_output(gpio_flm_uart_sel, 1); + s3c_gpio_setpull(gpio_flm_uart_sel, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_flm_uart_sel, 1); + } + } + + if (gpio_cp_on) { + err = gpio_request(gpio_cp_on, "ESC_ON"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_ON", gpio_cp_on, err); + } else { + gpio_direction_output(gpio_cp_on, 0); + s3c_gpio_setpull(gpio_cp_on, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio_cp_on, S5P_GPIO_DRVSTR_LV1); + gpio_set_value(gpio_cp_on, 0); + } + } + + if (gpio_cp_off) { + err = gpio_request(gpio_cp_off, "ESC_OFF"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_OFF", (gpio_cp_off), err); + } else { + gpio_direction_output(gpio_cp_off, 1); + s3c_gpio_setpull(gpio_cp_off, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio_cp_off, 1); + } + } + + if (gpio_rst_req_n) { + err = gpio_request(gpio_rst_req_n, "ESC_RST_REQ"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_RST_REQ", gpio_rst_req_n, err); + } else { + gpio_direction_output(gpio_rst_req_n, 1); + s3c_gpio_setpull(gpio_rst_req_n, S3C_GPIO_PULL_NONE); + } + gpio_set_value(gpio_rst_req_n, 0); + } + + if (gpio_cp_rst) { + err = gpio_request(gpio_cp_rst, "ESC_RST"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_RST", gpio_cp_rst, err); + } else { + gpio_direction_output(gpio_cp_rst, 0); + s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio_cp_rst, S5P_GPIO_DRVSTR_LV4); + } + gpio_set_value(gpio_cp_rst, 0); + } + + if (gpio_dpram_int) { + err = gpio_request(gpio_dpram_int, "ESC_DPRAM_INT"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "ESC_DPRAM_INT", gpio_dpram_int, err); + } else { + /* Configure as a wake-up source */ + s3c_gpio_cfgpin(gpio_dpram_int, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_dpram_int, S3C_GPIO_PULL_NONE); + } + } + + err = gpio_request(EXYNOS4_GPA1(4), "AP_CP2_UART_RXD"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "AP_CP2_UART_RXD", EXYNOS4_GPA1(4), err); + } else { + s3c_gpio_cfgpin(EXYNOS4_GPA1(4), S3C_GPIO_SFN(0x2)); + s3c_gpio_setpull(EXYNOS4_GPA1(4), S3C_GPIO_PULL_NONE); + } + + err = gpio_request(EXYNOS4_GPA1(5), "AP_CP2_UART_TXD"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "AP_CP2_UART_TXD", EXYNOS4_GPA1(5), err); + } else { + s3c_gpio_cfgpin(EXYNOS4_GPA1(5), S3C_GPIO_SFN(0x2)); + s3c_gpio_setpull(EXYNOS4_GPA1(5), S3C_GPIO_PULL_NONE); + } + +#if defined(CONFIG_LINK_DEVICE_PLD) + if (gpio_fpga1_creset) { + err = gpio_request(gpio_fpga1_creset, "FPGA1_CRESET"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA1_CRESET", gpio_fpga1_creset, err); + } else { + gpio_direction_output(gpio_fpga1_creset, 0); + s3c_gpio_setpull(gpio_fpga1_creset, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga1_cdone) { + err = gpio_request(gpio_fpga1_cdone, "FPGA1_CDONE"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA1_CDONE", gpio_fpga1_cdone, err); + } else { + s3c_gpio_cfgpin(gpio_fpga1_cdone, S3C_GPIO_INPUT); + s3c_gpio_setpull(gpio_fpga1_cdone, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga1_rst_n) { + err = gpio_request(gpio_fpga1_rst_n, "FPGA1_RST"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "FPGA1_RST", gpio_fpga1_rst_n, err); + } else { + gpio_direction_output(gpio_fpga1_rst_n, 0); + s3c_gpio_setpull(gpio_fpga1_rst_n, S3C_GPIO_PULL_NONE); + } + } + + if (gpio_fpga1_cs_n) { + err = gpio_request(gpio_fpga1_cs_n, "SPI_CS2_1"); + if (err) { + pr_err("fail to request gpio %s, gpio %d, errno %d\n", + "SPI_CS2_1", gpio_fpga1_cs_n, err); + } else { + gpio_direction_output(gpio_fpga1_cs_n, 0); + s3c_gpio_setpull(gpio_fpga1_cs_n, S3C_GPIO_PULL_NONE); + } + } +#endif + +} + +static u8 *gsm_edpram_remap_mem_region(struct sromc_cfg *cfg) +{ + int dp_addr = 0; + int dp_size = 0; + u8 __iomem *dp_base = NULL; + struct msm_edpram_ipc_cfg *ipc_map = NULL; + struct dpram_ipc_device *dev = NULL; + + dp_addr = cfg->addr; + dp_size = cfg->size; + dp_base = (u8 *)ioremap_nocache(dp_addr, dp_size); + if (!dp_base) { + pr_err("[MDM] <%s> dpram base ioremap fail\n", __func__); + return NULL; + } + pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base); + + gsm_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; + gsm_edpram_ctrl.dp_size = dp_size; + + /* Map for IPC */ + ipc_map = (struct msm_edpram_ipc_cfg *)dp_base; + +#if defined(CONFIG_LINK_DEVICE_PLD) + /* Magic code and access enable fields */ + gsm_ipc_map.magic_ap2cp = (u16 __iomem *) &ipc_map->magic_ap2cp; + gsm_ipc_map.access_ap2cp = (u16 __iomem *) &ipc_map->access_ap2cp; + + gsm_ipc_map.magic_cp2ap = (u16 __iomem *) &ipc_map->magic_cp2ap; + gsm_ipc_map.access_cp2ap = (u16 __iomem *) &ipc_map->access_cp2ap; + + gsm_ipc_map.address_buffer = (u16 __iomem *) &ipc_map->address_buffer; +#else + /* Magic code and access enable fields */ + gsm_ipc_map.magic = (u16 __iomem *) &ipc_map->magic; + gsm_ipc_map.access = (u16 __iomem *) &ipc_map->access; +#endif + + /* FMT */ + dev = &gsm_ipc_map.dev[IPC_FMT]; + + strcpy(dev->name, "FMT"); + dev->id = IPC_FMT; + + dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; + dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; + dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; + dev->txq.size = MSM_DP_FMT_TX_BUFF_SZ; + + dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; + dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; + dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; + dev->rxq.size = MSM_DP_FMT_RX_BUFF_SZ; + + dev->mask_req_ack = INT_MASK_REQ_ACK_F; + dev->mask_res_ack = INT_MASK_RES_ACK_F; + dev->mask_send = INT_MASK_SEND_F; + + /* RAW */ + dev = &gsm_ipc_map.dev[IPC_RAW]; + + strcpy(dev->name, "RAW"); + dev->id = IPC_RAW; + + dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; + dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; + dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; + dev->txq.size = MSM_DP_RAW_TX_BUFF_SZ; + + dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; + dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; + dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; + dev->rxq.size = MSM_DP_RAW_RX_BUFF_SZ; + + dev->mask_req_ack = INT_MASK_REQ_ACK_R; + dev->mask_res_ack = INT_MASK_RES_ACK_R; + dev->mask_send = INT_MASK_SEND_R; + + /* Mailboxes */ + gsm_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; + gsm_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; + + return dp_base; +} +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define PLD_BLOCK_SIZE 0x8000 + +static struct spi_device *p_spi; + +static int pld_spi_probe(struct spi_device *spi) +{ + int ret = 0; + + mif_err("pld spi proble.\n"); + + p_spi = spi; + p_spi->mode = SPI_MODE_0; + p_spi->bits_per_word = 32; + + ret = spi_setup(p_spi); + if (ret != 0) { + mif_err("spi_setup ERROR : %d\n", ret); + return ret; + } + + dev_info(&p_spi->dev, "(%d) spi probe Done.\n", __LINE__); + + return ret; +} + +static int pld_spi_remove(struct spi_device *spi) +{ + return 0; +} + +static struct spi_driver pld_spi_driver = { + .probe = pld_spi_probe, + .remove = __devexit_p(pld_spi_remove), + .driver = { + .name = "modem_if_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, +}; + +static int config_spi_dev_init(void) +{ + int ret = 0; + + ret = spi_register_driver(&pld_spi_driver); + if (ret < 0) { + pr_info("spi_register_driver() fail : %d\n", ret); + return ret; + } + + pr_info("[%s] Done\n", __func__); + return 0; +} + +int spi_tx_rx_sync(u8 *tx_d, u8 *rx_d, unsigned len) +{ + struct spi_transfer t; + struct spi_message msg; + + memset(&t, 0, sizeof t); + + t.len = len; + + t.tx_buf = tx_d; + t.rx_buf = rx_d; + + t.cs_change = 0; + + t.bits_per_word = 8; + t.speed_hz = 12000000; + + spi_message_init(&msg); + spi_message_add_tail(&t, &msg); + + return spi_sync(p_spi, &msg); +} + +static int pld_send_fgpa_bin(void) +{ + int retval = 0; + char *tx_b, *rx_b; + + unsigned gpio_fpga1_creset = gsm_modem_data.gpio_fpga1_creset; + unsigned gpio_fpga1_cdone = gsm_modem_data.gpio_fpga1_cdone; + unsigned gpio_fpga1_rst_n = gsm_modem_data.gpio_fpga1_rst_n; + unsigned gpio_fpga1_cs_n = gsm_modem_data.gpio_fpga1_cs_n; + + char dummy_data[8] = "abcdefg"; + + mif_info("sizeofpld : 0%d ", sizeof(fpga_bin)); + + if (gpio_fpga1_cs_n) { + s3c_gpio_cfgpin(gpio_fpga1_cs_n, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio_fpga1_cs_n, S3C_GPIO_PULL_NONE); + gpio_direction_output(gpio_fpga1_cs_n, 0); + } + + msleep(20); + + if (gpio_fpga1_creset) { + gpio_direction_output(gpio_fpga1_creset, 1); + s3c_gpio_setpull(gpio_fpga1_creset, S3C_GPIO_PULL_NONE); + } + + msleep(20); + + tx_b = kmalloc(PLD_BLOCK_SIZE*2, GFP_ATOMIC); + if (!tx_b) { + mif_err("(%d) tx_b kmalloc fail.", + __LINE__); + return -ENOMEM; + } + memset(tx_b, 0, PLD_BLOCK_SIZE*2); + memcpy(tx_b, fpga_bin, sizeof(fpga_bin)); + + rx_b = kmalloc(PLD_BLOCK_SIZE*2, GFP_ATOMIC); + if (!rx_b) { + mif_err("(%d) rx_b kmalloc fail.", + __LINE__); + retval = -ENOMEM; + goto err; + } + memset(rx_b, 0, PLD_BLOCK_SIZE*2); + + retval = spi_tx_rx_sync(tx_b, rx_b, sizeof(fpga_bin)); + if (retval != 0) { + mif_err("(%d) spi sync error : %d\n", + __LINE__, retval); + goto err; + } + + memset(tx_b, 0, PLD_BLOCK_SIZE*2); + memcpy(tx_b, dummy_data, sizeof(dummy_data)); + + retval = spi_tx_rx_sync(tx_b, rx_b, sizeof(dummy_data)); + if (retval != 0) { + mif_err("(%d) spi sync error : %d\n", + __LINE__, retval); + goto err; + } + + msleep(20); + + mif_info("PLD_CDone1[%d]\n", + gpio_get_value(gpio_fpga1_cdone)); + + if (gpio_fpga1_rst_n) { + gpio_direction_output(gpio_fpga1_rst_n, 1); + s3c_gpio_setpull(gpio_fpga1_rst_n, S3C_GPIO_PULL_NONE); + } + +err: + kfree(tx_b); + kfree(rx_b); + + return retval; + +} +#endif + +static int __init init_modem(void) +{ +#if defined(CONFIG_GSM_MODEM_ESC6270) + struct sromc_cfg *cfg = NULL; + struct sromc_access_cfg *acc_cfg = NULL; + + int ret; + pr_info(LOG_TAG "init_modem, system_rev = %d\n", system_rev); + + gsm_edpram_cfg.csn = 0; + gsm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * gsm_edpram_cfg.csn); + gsm_edpram_cfg.end = gsm_edpram_cfg.addr + gsm_edpram_cfg.size - 1; + + config_dpram_port_gpio(); + config_gsm_modem_gpio(); + +#if defined(CONFIG_LINK_DEVICE_PLD) + config_spi_dev_init(); + pld_send_fgpa_bin(); +#endif + + init_sromc(); + cfg = &gsm_edpram_cfg; + acc_cfg = &gsm_edpram_access_cfg[DPRAM_SPEED_LOW]; + setup_sromc(cfg->csn, cfg, acc_cfg); + + if (!gsm_edpram_remap_mem_region(&gsm_edpram_cfg)) + return -1; + + platform_device_register(&gsm_modem); +#endif + + return ret; +} +late_initcall(init_modem); diff --git a/arch/arm/mach-exynos/mach-u1cam.c b/arch/arm/mach-exynos/board-trats.c index c589751..cf725ab 100644 --- a/arch/arm/mach-exynos/mach-u1cam.c +++ b/arch/arm/mach-exynos/board-trats.c @@ -1,6 +1,6 @@ -/* linux/arch/arm/mach-exynos/mach-u1cam.c +/* linux/arch/arm/mach-exynos/mach-trats.c * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * * This program is free software; you can redistribute it and/or modify @@ -14,50 +14,43 @@ #include <linux/gpio_keys.h> #include <linux/gpio_event.h> #include <linux/lcd.h> +#include <linux/lcd-property.h> #include <linux/mmc/host.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/i2c.h> #include <linux/i2c-gpio.h> #include <linux/input.h> -#include <linux/switch.h> #include <linux/spi/spi.h> #include <linux/spi/spi_gpio.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> #include <linux/mfd/max8997.h> #include <linux/mfd/max8997-private.h> -#include <linux/sensor/k3g.h> -#include <linux/sensor/k3dh.h> #include <linux/sensor/ak8975.h> -#ifdef CONFIG_MACH_U1_BD -#include <linux/sensor/cm3663.h> -#include <linux/sensor/pas2m110.h> -#endif -#ifdef CONFIG_MACH_Q1_BD -#include <linux/sensor/gp2a_analog.h> -#endif +#include <linux/kr3dh.h> +#include <linux/utsname.h> #include <linux/pn544.h> -#ifdef CONFIG_SND_SOC_U1_MC1N2 -#include <linux/mfd/mc1n2_pdata.h> -#endif -#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E) -#include <linux/i2c/mxt540e.h> -#else -#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC -#include <linux/i2c/mxt224_gc.h> -#else -#include <linux/i2c/mxt224_u1.h> +#include <linux/sensor/gp2a.h> +#include <linux/printk.h> +#ifdef CONFIG_UART_SELECT +#include <linux/uart_select.h> #endif +#if defined(CONFIG_SND_SOC_SLP_TRATS_MC1N2) +#include <linux/mfd/mc1n2_pdata.h> #endif #include <linux/memblock.h> #include <linux/power_supply.h> #if defined(CONFIG_S5P_MEM_CMA) #include <linux/cma.h> #endif +#ifdef CONFIG_JACK_MON +#include <linux/jack.h> +#endif #ifdef CONFIG_ANDROID_PMEM #include <linux/android_pmem.h> #endif +#include <linux/k3g.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -71,7 +64,6 @@ #include <plat/hwmon.h> #include <plat/cpu.h> #include <plat/devs.h> -#include <plat/fb-s5p.h> #include <plat/fimc.h> #include <plat/csis.h> #include <plat/gpio-cfg.h> @@ -83,11 +75,9 @@ #include <plat/iic.h> #include <plat/sysmmu.h> #include <plat/pd.h> -#include <plat/regs-fb-v4.h> #include <plat/media.h> #include <plat/udc-hs.h> #include <plat/s5p-clock.h> -#include <plat/tvout.h> #include <plat/fimg2d.h> #include <plat/ehci.h> #include <plat/usbgadget.h> @@ -99,19 +89,19 @@ #include <mach/map.h> #include <mach/exynos-clock.h> #include <mach/media.h> -#include <plat/regs-fb.h> #include <mach/dev-sysmmu.h> #include <mach/dev.h> #include <mach/regs-clock.h> #include <mach/exynos-ion.h> -#ifdef CONFIG_FB_S5P_MIPI_DSIM -#include <mach/mipi_ddi.h> -#include <mach/dsim.h> -#include <plat/fb-s5p.h> -#endif +#include <drm/exynos_drm.h> +#include <plat/regs-fb.h> +#include <plat/fb-core.h> +#include <plat/mipi_dsim2.h> +#include <plat/fimd_lite_ext.h> +#include <plat/hdmi.h> #if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) || defined(CONFIG_VIDEO_MFC5X) #include <plat/s5p-mfc.h> #endif @@ -120,8 +110,8 @@ #include <mach/spi-clocks.h> #endif -#ifdef CONFIG_VIDEO_M9MO -#include <media/m9mo_platform.h> +#ifdef CONFIG_VIDEO_M5MO +#include <media/m5mo_platform.h> #endif #ifdef CONFIG_VIDEO_S5K5BAFX #include <media/s5k5bafx_platform.h> @@ -140,15 +130,6 @@ #include <mach/board-bluetooth-bcm.h> #endif -#ifdef CONFIG_FB_S5P_LD9040 -#include <linux/ld9040.h> -#endif - -#ifdef CONFIG_FB_S5P_MDNIE -#include <linux/mdnie.h> -#endif - -#include <../../../drivers/video/samsung/s3cfb.h> #include "u1.h" #include <mach/sec_debug.h> @@ -186,11 +167,6 @@ #include <linux/host_notify.h> #endif -#ifdef CONFIG_EPEN_WACOM_G5SP -#include <linux/wacom_i2c.h> -static struct wacom_g5_callbacks *wacom_callbacks; -#endif /* CONFIG_EPEN_WACOM_G5SP */ - #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) #include <mach/tdmb_pdata.h> @@ -200,6 +176,19 @@ static struct wacom_g5_callbacks *wacom_callbacks; #include <linux/leds-max8997.h> #endif +#if defined(CONFIG_PHONE_IPC_SPI) +#include <linux/phone_svn/ipc_spi.h> +#include <linux/irq.h> +#endif + +#ifdef CONFIG_TOUCHSCREEN_MELFAS_MMS +#include <linux/melfas_mms_ts.h> +#endif + +#ifdef CONFIG_GPS_GSD4T +#include <mach/gsd4t.h> +#endif + /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -214,11 +203,18 @@ static struct wacom_g5_callbacks *wacom_callbacks; S5PV210_UFCON_TXTRIG4 | \ S5PV210_UFCON_RXTRIG4) -#define SMDKC210_UFCON_GPS (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG8 | \ - S5PV210_UFCON_RXTRIG32) +enum fixed_regulator_id { + FIXED_REG_ID_LCD = 0, + FIXED_REG_ID_HDMI = 1, + FIXED_REG_ID_LED_A, +}; + +enum board_rev { + U1HD_5INCH_REV0_0 = 0x2, + U1HD_REV0_1 = 0x1, +}; -static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { +static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, @@ -234,7 +230,7 @@ static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { .flags = 0, .ucon = SMDKC210_UCON_DEFAULT, .ulcon = SMDKC210_ULCON_DEFAULT, - .ufcon = SMDKC210_UFCON_GPS, + .ufcon = SMDKC210_UFCON_DEFAULT, .set_runstate = set_gps_uart_op, }, [2] = { @@ -253,8 +249,6 @@ static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { }, }; -#define WRITEBACK_ENABLED - #ifdef CONFIG_VIDEO_FIMC /* * External camera reset @@ -264,7 +258,7 @@ static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { * Do optimization for cameras on your platform. */ -#ifdef CONFIG_VIDEO_M9MO +#ifdef CONFIG_VIDEO_M5MO #define CAM_CHECK_ERR_RET(x, msg) \ if (unlikely((x) < 0)) { \ printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \ @@ -275,66 +269,113 @@ static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { printk(KERN_ERR "\nfail to %s: err = %d\n", msg, x); \ } -static int m9mo_get_i2c_busnum(void) +static int m5mo_get_i2c_busnum(void) { -#ifdef CONFIG_VIDEO_M9MO_USE_SWI2C +#ifdef CONFIG_VIDEO_M5MO_USE_SWI2C return 25; #else return 0; #endif } -static int m9mo_power_on(void) +static int m5mo_power_on(void) { struct regulator *regulator; int ret = 0; - printk(KERN_ERR "%s: in\n", __func__); + printk(KERN_DEBUG "%s: in\n", __func__); - /* CIS_LDO_1.8V_EN -> CIS 1.2 */ + ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); + return ret; + } ret = gpio_request(GPIO_CAM_SENSOR_CORE, "GPE2"); if (ret) { printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); return ret; } - + ret = gpio_request(GPIO_CAM_IO_EN, "GPE2"); + if (ret) { + printk(KERN_ERR "fail to request gpio(CAM_IO_EN)\n"); + return ret; + } + ret = gpio_request(GPIO_VT_CAM_15V, "GPE2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n"); + return ret; + } ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET"); if (ret) { printk(KERN_ERR "faile to request gpio(ISP_RESET)\n"); return ret; } + ret = gpio_request(GPIO_8M_AF_EN, "GPK1"); + if (ret) { + printk(KERN_ERR "fail to request gpio(8M_AF_EN)\n"); + return ret; + } - /* CIS 1.8V */ - regulator = regulator_get(NULL, "cis_1.8v"); - if (IS_ERR(regulator)) - return -ENODEV; - ret = regulator_enable(regulator); - regulator_put(regulator); - CAM_CHECK_ERR_RET(ret, "cis_1.8v"); + /* CAM_VT_nSTBY low */ + ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + CAM_CHECK_ERR_RET(ret, "output VGA_nSTBY"); + + /* CAM_VT_nRST low */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + CAM_CHECK_ERR_RET(ret, "output VGA_nRST"); udelay(10); - /* CIS_2.8 */ - regulator = regulator_get(NULL, "cis_2.8v"); + /* CAM_ISP_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_isp_core"); if (IS_ERR(regulator)) return -ENODEV; ret = regulator_enable(regulator); regulator_put(regulator); - CAM_CHECK_ERR_RET(ret, "enable cis_2.8v"); - udelay(10); + CAM_CHECK_ERR_RET(ret, "enable cam_isp_core"); + /* No delay */ - /* CIS_1.2V */ + /* CAM_SENSOR_CORE_1.2V */ ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE, 1); - CAM_CHECK_ERR_RET(ret, "output reset"); + CAM_CHECK_ERR_RET(ret, "output senser_core"); + +#if defined(CONFIG_MACH_Q1_BD) + udelay(120); +#else udelay(10); +#endif - /* CAM_ISP_CORE_1.2V */ - regulator = regulator_get(NULL, "cam_isp_core"); + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 1); + CAM_CHECK_ERR_RET(ret, "output IO_EN"); + /* it takes about 100us at least during level transition. */ + udelay(160); /* 130us -> 160us */ + + /* VT_CORE_1.5V */ + ret = gpio_direction_output(GPIO_VT_CAM_15V, 1); + CAM_CHECK_ERR_RET(ret, "output VT_CAM_1.5V"); + udelay(20); + +#if defined(CONFIG_MACH_Q1_BD) + udelay(120); +#endif + + /* CAM_AF_2.8V */ + ret = gpio_direction_output(GPIO_8M_AF_EN, 1); + CAM_CHECK_ERR(ret, "output AF"); + mdelay(7); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); if (IS_ERR(regulator)) return -ENODEV; ret = regulator_enable(regulator); regulator_put(regulator); - CAM_CHECK_ERR_RET(ret, "enable cam_isp_core"); - + CAM_CHECK_ERR_RET(ret, "enable vt_1.8v"); udelay(10); /* CAM_ISP_1.8V */ @@ -346,6 +387,15 @@ static int m9mo_power_on(void) CAM_CHECK_ERR_RET(ret, "enable cam_isp"); udelay(120); /* at least */ + /* CAM_SENSOR_IO_1.8V */ + regulator = regulator_get(NULL, "cam_sensor_io"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable sensor_io"); + udelay(30); + /* MCLK */ ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); CAM_CHECK_ERR_RET(ret, "cfg mclk"); @@ -357,16 +407,19 @@ static int m9mo_power_on(void) CAM_CHECK_ERR_RET(ret, "output reset"); mdelay(4); + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_CAM_VGA_nRST); gpio_free(GPIO_CAM_SENSOR_CORE); + gpio_free(GPIO_CAM_IO_EN); + gpio_free(GPIO_VT_CAM_15V); gpio_free(GPIO_ISP_RESET); - + gpio_free(GPIO_8M_AF_EN); printk(KERN_DEBUG "%s: out\n", __func__); return ret; } -#ifdef CONFIG_SAMSUNG_MHL - +#ifdef CONFIG_SAMSUNG_MHL static void sii9234_cfg_gpio(void) { printk(KERN_INFO "%s()\n", __func__); @@ -387,21 +440,9 @@ static void sii9234_cfg_gpio(void) irq_set_irq_type(MHL_INT_IRQ, IRQ_TYPE_EDGE_RISING); s3c_gpio_cfgpin(GPIO_MHL_INT, GPIO_MHL_INT_AF); -#ifdef CONFIG_TARGET_LOCALE_KOR - s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT); - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW); - s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE); -#else - if (system_rev < 7) { - s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT); - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW); - s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE); - } else { - s3c_gpio_cfgpin(GPIO_HDMI_EN_REV07, S3C_GPIO_OUTPUT); - gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW); - s3c_gpio_setpull(GPIO_HDMI_EN_REV07, S3C_GPIO_PULL_NONE); - } -#endif + s3c_gpio_cfgpin(GPIO_HDMI_EN_REV07, S3C_GPIO_OUTPUT); + gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW); + s3c_gpio_setpull(GPIO_HDMI_EN_REV07, S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE); @@ -418,31 +459,22 @@ void sii9234_power_onoff(bool on) pr_info("%s(%d)\n", __func__, on); if (on) { - /*s3c_gpio_cfgpin(GPIO_HDMI_EN,S3C_GPIO_OUTPUT);*/ -#ifdef CONFIG_TARGET_LOCALE_KOR - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH); -#else - if (system_rev < 7) - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH); - else - gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_HIGH); -#endif + /* To avoid floating state of the HPD pin * + * in the absence of external pull-up */ + s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_HIGH); s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_DOWN); s3c_gpio_setpull(GPIO_AP_SCL_18V, S3C_GPIO_PULL_NONE); - } else { gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); usleep_range(10000, 20000); gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH); -#ifdef CONFIG_TARGET_LOCALE_KOR - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH); -#else - if (system_rev < 7) - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW); - else - gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW); -#endif + + /* To avoid floating state of the HPD pin * + * in the absence of external pull-up */ + s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN); + gpio_set_value(GPIO_HDMI_EN_REV07, GPIO_LEVEL_LOW); gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); } pr_info("[MHL]%s : %d\n", __func__, on); @@ -450,13 +482,14 @@ void sii9234_power_onoff(bool on) void sii9234_reset(void) { + printk(KERN_INFO "%s()\n", __func__); + s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE); gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); usleep_range(10000, 20000); gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH); - } void mhl_usb_switch_control(bool on) @@ -488,6 +521,9 @@ static struct sii9234_platform_data sii9234_pdata = { .hw_reset = sii9234_reset, .enable_vbus = NULL, .vbus_present = NULL, +#ifdef CONFIG_EXTCON + .extcon_name = "max8997-muic", +#endif }; static struct i2c_board_info __initdata tuna_i2c15_boardinfo[] = { @@ -526,33 +562,75 @@ struct platform_device s3c_device_i2c15 = { .platform_data = &gpio_i2c_data15, } }; +#endif + +#ifdef CONFIG_JACK_MON +static struct jack_platform_data trats_jack_data = { + .usb_online = 0, + .charger_online = 0, + .hdmi_online = 0, + .earjack_online = 0, + .earkey_online = 0, + .ums_online = -1, + .cdrom_online = -1, + .jig_online = -1, + .host_online = 0, +}; +static struct platform_device trats_jack = { + .name = "jack", + .id = -1, + .dev = { + .platform_data = &trats_jack_data, + }, +}; #endif -static int m9mo_power_down(void) +static int m5mo_power_down(void) { struct regulator *regulator; int ret = 0; printk(KERN_DEBUG "%s: in\n", __func__); + ret = gpio_request(GPIO_8M_AF_EN, "GPK1"); + if (ret) { + printk(KERN_ERR "fail to request gpio(8M_AF_EN)\n"); + return ret; + } ret = gpio_request(GPIO_ISP_RESET, "ISP_RESET"); if (ret) { printk(KERN_ERR "faile to request gpio(ISP_RESET)\n"); return ret; } - + ret = gpio_request(GPIO_CAM_IO_EN, "GPE2"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_CAM_IO_EN)\n"); + return ret; + } ret = gpio_request(GPIO_CAM_SENSOR_CORE, "GPE2"); if (ret) { - printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); + printk(KERN_ERR "fail to request gpio(CAM_SENSOR_COR)\n"); + return ret; + } + ret = gpio_request(GPIO_VT_CAM_15V, "GPE2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n"); return ret; } + /* s3c_i2c0_force_stop(); */ + + mdelay(3); + /* ISP_RESET */ ret = gpio_direction_output(GPIO_ISP_RESET, 0); CAM_CHECK_ERR(ret, "output reset"); - +#ifdef CONFIG_TARGET_LOCALE_KOR + mdelay(3); /* fix without seeing signal form for kor. */ +#else mdelay(2); +#endif /* MCLK */ ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); @@ -560,6 +638,21 @@ static int m9mo_power_down(void) CAM_CHECK_ERR(ret, "cfg mclk"); udelay(20); + /* CAM_AF_2.8V */ + /* 8M_AF_2.8V_EN */ + ret = gpio_direction_output(GPIO_8M_AF_EN, 0); + CAM_CHECK_ERR(ret, "output AF"); + + /* CAM_SENSOR_IO_1.8V */ + regulator = regulator_get(NULL, "cam_sensor_io"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable, sensor_io"); + udelay(10); + /* CAM_ISP_1.8V */ regulator = regulator_get(NULL, "cam_isp"); if (IS_ERR(regulator)) @@ -570,39 +663,49 @@ static int m9mo_power_down(void) CAM_CHECK_ERR(ret, "disable cam_isp"); udelay(500); /* 100us -> 500us */ - /* CAM_ISP_CORE_1.2V */ - regulator = regulator_get(NULL, "cam_isp_core"); + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); if (IS_ERR(regulator)) return -ENODEV; if (regulator_is_enabled(regulator)) - ret = regulator_force_disable(regulator); + ret = regulator_disable(regulator); regulator_put(regulator); - CAM_CHECK_ERR(ret, "disable isp_core"); + CAM_CHECK_ERR(ret, "disable vt_1.8v"); + udelay(250); /* 10us -> 250us */ + /* VT_CORE_1.5V */ + ret = gpio_direction_output(GPIO_VT_CAM_15V, 0); + CAM_CHECK_ERR(ret, "output VT_CAM_1.5V"); + udelay(300); /*10 -> 300 us */ + + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 0); + CAM_CHECK_ERR(ret, "output IO_EN"); + udelay(800); + + /* CAM_SENSOR_CORE_1.2V */ ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE, 0); - CAM_CHECK_ERR_RET(ret, "output reset"); - udelay(10); + CAM_CHECK_ERR(ret, "output SENSOR_CORE"); + udelay(5); - regulator = regulator_get(NULL, "cis_2.8v"); + /* CAM_ISP_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_isp_core"); if (IS_ERR(regulator)) return -ENODEV; if (regulator_is_enabled(regulator)) ret = regulator_force_disable(regulator); regulator_put(regulator); - CAM_CHECK_ERR(ret, "disable cis_2.8v"); - udelay(500); /* 100us -> 500us */ + CAM_CHECK_ERR(ret, "disable isp_core"); - regulator = regulator_get(NULL, "cis_1.8v"); - if (IS_ERR(regulator)) - return -ENODEV; - if (regulator_is_enabled(regulator)) - ret = regulator_force_disable(regulator); - regulator_put(regulator); - CAM_CHECK_ERR(ret, "disable cis_1.8v"); - udelay(500); /* 100us -> 500us */ +#if defined(CONFIG_MACH_Q1_BD) + mdelay(250); +#endif + gpio_free(GPIO_8M_AF_EN); gpio_free(GPIO_ISP_RESET); + gpio_free(GPIO_CAM_IO_EN); gpio_free(GPIO_CAM_SENSOR_CORE); + gpio_free(GPIO_VT_CAM_15V); return ret; } @@ -654,7 +757,7 @@ error_out: static bool is_torch; #endif -static int m9mo_flash_power(int enable) +static int m5mo_flash_power(int enable) { struct regulator *flash = regulator_get(NULL, "led_flash"); struct regulator *movie = regulator_get(NULL, "led_movie"); @@ -663,7 +766,7 @@ static int m9mo_flash_power(int enable) #if defined(CONFIG_MACH_Q1_BD) if (regulator_is_enabled(movie)) { - printk(KERN_DEBUG "%s: m9mo_torch set~~~~", __func__); + printk(KERN_DEBUG "%s: m5mo_torch set~~~~", __func__); is_torch = true; goto torch_exit; } @@ -692,56 +795,56 @@ torch_exit: return 0; } -static int m9mo_power(int enable) +static int m5mo_power(int enable) { int ret = 0; printk(KERN_DEBUG "%s %s\n", __func__, enable ? "on" : "down"); if (enable) { - ret = m9mo_power_on(); + ret = m5mo_power_on(); if (unlikely(ret)) goto error_out; } else - ret = m9mo_power_down(); + ret = m5mo_power_down(); ret = s3c_csis_power(enable); -/* m9mo_flash_power(enable);*/ + m5mo_flash_power(enable); error_out: return ret; } -static int m9mo_config_isp_irq(void) +static int m5mo_config_isp_irq(void) { s3c_gpio_cfgpin(GPIO_ISP_INT, S3C_GPIO_SFN(0xF)); s3c_gpio_setpull(GPIO_ISP_INT, S3C_GPIO_PULL_NONE); return 0; } -static struct m9mo_platform_data m9mo_plat = { +static struct m5mo_platform_data m5mo_plat = { .default_width = 640, /* 1920 */ .default_height = 480, /* 1080 */ .pixelformat = V4L2_PIX_FMT_UYVY, .freq = 24000000, .is_mipi = 1, - .config_isp_irq = m9mo_config_isp_irq, + .config_isp_irq = m5mo_config_isp_irq, .irq = IRQ_EINT(13), }; -static struct i2c_board_info m9mo_i2c_info = { - I2C_BOARD_INFO("M9MO", 0x1F), - .platform_data = &m9mo_plat, +static struct i2c_board_info m5mo_i2c_info = { + I2C_BOARD_INFO("M5MO", 0x1F), + .platform_data = &m5mo_plat, }; -static struct s3c_platform_camera m9mo = { +static struct s3c_platform_camera m5mo = { .id = CAMERA_CSI_C, .clk_name = "sclk_cam0", - .get_i2c_busnum = m9mo_get_i2c_busnum, - .cam_power = m9mo_power, /*smdkv310_mipi_cam0_reset, */ + .get_i2c_busnum = m5mo_get_i2c_busnum, + .cam_power = m5mo_power, /*smdkv310_mipi_cam0_reset, */ .type = CAM_TYPE_MIPI, .fmt = ITU_601_YCBCR422_8BIT, /*MIPI_CSI_YCBCR422_8BIT */ .order422 = CAM_ORDER422_8BIT_CBYCRY, - .info = &m9mo_i2c_info, + .info = &m5mo_i2c_info, .pixelformat = V4L2_PIX_FMT_UYVY, .srclk_name = "xusbxti", /* "mout_mpll" */ .clk_rate = 24000000, /* 48000000 */ @@ -755,7 +858,7 @@ static struct s3c_platform_camera m9mo = { .height = 480, }, - .mipi_lanes = 4, + .mipi_lanes = 2, .mipi_settle = 12, .mipi_align = 32, @@ -767,7 +870,7 @@ static struct s3c_platform_camera m9mo = { .reset_camera = 0, .initialized = 0, }; -#endif /* #ifdef CONFIG_VIDEO_M9MO */ +#endif /* #ifdef CONFIG_VIDEO_M5MO */ #ifdef CONFIG_VIDEO_S5K5BAFX static int s5k5bafx_get_i2c_busnum(void) @@ -1075,6 +1178,9 @@ static struct s3c_platform_camera s5k5bafx = { }; #endif +#ifdef CONFIG_WRITEBACK_ENABLED +#define WRITEBACK_ENABLED +#endif #ifdef WRITEBACK_ENABLED static int get_i2c_busnum_writeback(void) { @@ -1113,6 +1219,23 @@ void cam_cfg_gpio(struct platform_device *pdev) if (pdev->id != 0) return; + +#ifdef CONFIG_VIDEO_S5K5BAFX +#ifndef CONFIG_MACH_U1_KOR_LGT + if (system_rev >= 9) { +#endif + /* Rev0.9 */ + ret = gpio_direction_input(VT_CAM_SDA_18V); + CAM_CHECK_ERR(ret, "VT_CAM_SDA_18V"); + s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_DOWN); + + ret = gpio_direction_input(VT_CAM_SCL_18V); + CAM_CHECK_ERR(ret, "VT_CAM_SCL_18V"); + s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_DOWN); +#ifndef CONFIG_MACH_U1_KOR_LGT + } +#endif +#endif } /* Interface setting */ @@ -1130,8 +1253,8 @@ static struct s3c_platform_fimc fimc_plat = { .default_cam = CAMERA_CSI_D, #endif .camera = { -#ifdef CONFIG_VIDEO_M9MO - &m9mo, +#ifdef CONFIG_VIDEO_M5MO + &m5mo, #endif #ifdef CONFIG_VIDEO_S5K5BAFX &s5k5bafx, @@ -1182,12 +1305,11 @@ void mmc_force_presence_change(struct platform_device *pdev) void (*notify_func)(struct platform_device *, int state) = NULL; mutex_lock(¬ify_lock); #ifdef CONFIG_S3C_DEV_HSMMC3 - printk(KERN_INFO "---------test logs pdev : %p s3c_device_hsmmc3 %p\n", + pr_info("---------test logs pdev : %p s3c_device_hsmmc3 %p\n", pdev, &s3c_device_hsmmc3); if (pdev == &s3c_device_hsmmc3) { notify_func = hsmmc3_notify_func; - printk(KERN_INFO "---------test logs notify_func : %p\n", - notify_func); + pr_info("---------test logs notify_func : %p\n", notify_func); } #endif @@ -1256,305 +1378,6 @@ static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = { }; #endif -#ifdef CONFIG_VIDEO_FIMG2D -static struct fimg2d_platdata fimg2d_data __initdata = { - .hw_ver = 30, - .parent_clkname = "mout_g2d0", - .clkname = "sclk_fimg2d", - .gate_clkname = "fimg2d", - .clkrate = 267 * 1000000, /* 266 Mhz */ -}; -#endif - -#ifdef CONFIG_FB_S3C -#if defined(CONFIG_LCD_AMS369FG06) -static int lcd_power_on(struct lcd_device *ld, int enable) -{ - return 1; -} - -static int reset_lcd(struct lcd_device *ld) -{ - int err = 0; - - err = gpio_request(EXYNOS4_GPX0(6), "GPX0"); - if (err) { - printk(KERN_ERR "failed to request GPX0 for " - "lcd reset control\n"); - return err; - } - - gpio_direction_output(EXYNOS4_GPX0(6), 1); - mdelay(100); - - gpio_set_value(EXYNOS4_GPX0(6), 1); - mdelay(100); - - gpio_free(EXYNOS4_GPX0(6)); - - return 1; -} - -static struct lcd_platform_data ams369fg06_platform_data = { - .reset = reset_lcd, - .power_on = lcd_power_on, - .lcd_enabled = 0, - .reset_delay = 100, /* 100ms */ -}; - -#define LCD_BUS_NUM 3 -#define DISPLAY_CS EXYNOS4_GPB(5) -#define DISPLAY_CLK EXYNOS4_GPB(4) -#define DISPLAY_SI EXYNOS4_GPB(7) - -static struct spi_board_info spi_board_info[] __initdata = { - { - .modalias = "ams369fg06", - .platform_data = (void *)&ams369fg06_platform_data, - .max_speed_hz = 1200000, - .bus_num = LCD_BUS_NUM, - .chip_select = 0, - .mode = SPI_MODE_3, - .controller_data = (void *)DISPLAY_CS, - } -}; - -static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = { - .sck = DISPLAY_CLK, - .mosi = DISPLAY_SI, - .miso = -1, - .num_chipselect = 1, -}; - -static struct platform_device s3c_device_spi_gpio = { - .name = "spi_gpio", - .id = LCD_BUS_NUM, - .dev = { - .parent = &s5p_device_fimd0.dev, - .platform_data = &ams369fg06_spi_gpio_data, - }, -}; - -static struct s3c_fb_pd_win smdkc210_fb_win0 = { - .win_mode = { - .left_margin = 9, - .right_margin = 9, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 2, - .vsync_len = 2, - .xres = 480, - .yres = 800, - }, - .virtual_x = 480, - .virtual_y = 1600, - .width = 48, - .height = 80, - .max_bpp = 32, - .default_bpp = 24, -}; - -static struct s3c_fb_pd_win smdkc210_fb_win1 = { - .win_mode = { - .left_margin = 9, - .right_margin = 9, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 2, - .vsync_len = 2, - .xres = 480, - .yres = 800, - }, - .virtual_x = 480, - .virtual_y = 1600, - .width = 48, - .height = 80, - .max_bpp = 32, - .default_bpp = 24, -}; - -static struct s3c_fb_pd_win smdkc210_fb_win2 = { - .win_mode = { - .left_margin = 9, - .right_margin = 9, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 2, - .vsync_len = 2, - .xres = 480, - .yres = 800, - }, - .virtual_x = 480, - .virtual_y = 1600, - .width = 48, - .height = 80, - .max_bpp = 32, - .default_bpp = 24, -}; - -#elif defined(CONFIG_LCD_WA101S) -static void lcd_wa101s_set_power(struct plat_lcd_data *pd, unsigned int power) -{ - if (power) { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request(EXYNOS4_GPD0(1), "GPD0"); - gpio_direction_output(EXYNOS4_GPD0(1), 1); - gpio_free(EXYNOS4_GPD0(1)); -#endif - } else { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request(EXYNOS4_GPD0(1), "GPD0"); - gpio_direction_output(EXYNOS4_GPD0(1), 0); - gpio_free(EXYNOS4_GPD0(1)); -#endif - } -} - -static struct plat_lcd_data smdkc210_lcd_wa101s_data = { - .set_power = lcd_wa101s_set_power, -}; - -static struct platform_device smdkc210_lcd_wa101s = { - .name = "platform-lcd", - .dev.parent = &s5p_device_fimd0.dev, - .dev.platform_data = &smdkc210_lcd_wa101s_data, -}; - -static struct s3c_fb_pd_win smdkc210_fb_win0 = { - .win_mode = { - .left_margin = 80, - .right_margin = 48, - .upper_margin = 14, - .lower_margin = 3, - .hsync_len = 32, - .vsync_len = 5, - .xres = 1366, - .yres = 768, - }, - .virtual_x = 1366, - .virtual_y = 768 * 2, - .width = 223, - .height = 125, - .max_bpp = 32, - .default_bpp = 24, -}; - -#ifndef CONFIG_LCD_WA101S /* temporarily disables window1 */ -static struct s3c_fb_pd_win smdkc210_fb_win1 = { - .win_mode = { - .left_margin = 80, - .right_margin = 48, - .upper_margin = 14, - .lower_margin = 3, - .hsync_len = 32, - .vsync_len = 5, - .xres = 1366, - .yres = 768, - }, - .virtual_x = 1366, - .virtual_y = 768 * 2, - .max_bpp = 32, - .default_bpp = 24, -}; -#endif - -#elif defined(CONFIG_LCD_LTE480WV) -static void lcd_lte480wv_set_power(struct plat_lcd_data *pd, unsigned int power) -{ - if (power) { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request(EXYNOS4_GPD0(1), "GPD0"); - gpio_direction_output(EXYNOS4_GPD0(1), 1); - gpio_free(EXYNOS4_GPD0(1)); -#endif - /* fire nRESET on power up */ - gpio_request(EXYNOS4_GPX0(6), "GPX0"); - - gpio_direction_output(EXYNOS4_GPX0(6), 1); - mdelay(100); - - gpio_set_value(EXYNOS4_GPX0(6), 0); - mdelay(10); - - gpio_set_value(EXYNOS4_GPX0(6), 1); - mdelay(10); - - gpio_free(EXYNOS4_GPX0(6)); - } else { -#if !defined(CONFIG_BACKLIGHT_PWM) - gpio_request(EXYNOS4_GPD0(1), "GPD0"); - gpio_direction_output(EXYNOS4_GPD0(1), 0); - gpio_free(EXYNOS4_GPD0(1)); -#endif - } -} - -static struct plat_lcd_data smdkc210_lcd_lte480wv_data = { - .set_power = lcd_lte480wv_set_power, -}; - -static struct platform_device smdkc210_lcd_lte480wv = { - .name = "platform-lcd", - .dev.parent = &s5p_device_fimd0.dev, - .dev.platform_data = &smdkc210_lcd_lte480wv_data, -}; - -static struct s3c_fb_pd_win smdkc210_fb_win0 = { - .win_mode = { - .left_margin = 13, - .right_margin = 8, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - .virtual_x = 800, - .virtual_y = 960, - .max_bpp = 32, - .default_bpp = 24, -}; - -static struct s3c_fb_pd_win smdkc210_fb_win1 = { - .win_mode = { - .left_margin = 13, - .right_margin = 8, - .upper_margin = 7, - .lower_margin = 5, - .hsync_len = 3, - .vsync_len = 1, - .xres = 800, - .yres = 480, - }, - .virtual_x = 800, - .virtual_y = 960, - .max_bpp = 32, - .default_bpp = 24, -}; -#endif - -static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = { -#if defined(CONFIG_LCD_AMS369FG06) || defined(CONFIG_LCD_WA101S) || \ - defined(CONFIG_LCD_LTE480WV) - .win[0] = &smdkc210_fb_win0, -#ifndef CONFIG_LCD_WA101S /* temporarily disables window1 */ - .win[1] = &smdkc210_fb_win1, -#endif -#endif - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, -#if defined(CONFIG_LCD_AMS369FG06) - .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN | - VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -#elif defined(CONFIG_LCD_WA101S) - .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -#elif defined(CONFIG_LCD_LTE480WV) - .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, -#endif - .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, -}; -#endif - #ifdef CONFIG_S3C64XX_DEV_SPI static struct s3c64xx_spi_csinfo spi0_csi[] = { [0] = { @@ -1586,6 +1409,15 @@ static struct spi_board_info spi0_board_info[] __initdata = { .controller_data = &spi0_csi[0], }, +#elif defined(CONFIG_PHONE_IPC_SPI) + { + .modalias = "ipc_spi", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 12*1000*1000, + .mode = SPI_MODE_1, + .controller_data = &spi0_csi[0], + }, #else { .modalias = "spidev", @@ -1600,377 +1432,453 @@ static struct spi_board_info spi0_board_info[] __initdata = { }; #endif -#ifdef CONFIG_FB_S5P -unsigned int lcdtype; -static int __init lcdtype_setup(char *str) -{ - get_option(&str, &lcdtype); - return 1; -} -__setup("lcdtype=", lcdtype_setup); +#if defined(CONFIG_PHONE_IPC_SPI) +static void ipc_spi_cfg_gpio(void); -#ifdef CONFIG_FB_S5P_LD9040 -unsigned int ld9040_lcdtype; -static int __init ld9040_lcdtype_setup(char *str) -{ - get_option(&str, &ld9040_lcdtype); - return 1; -} +static struct ipc_spi_platform_data ipc_spi_data = { + .gpio_ipc_mrdy = GPIO_IPC_MRDY, + .gpio_ipc_srdy = GPIO_IPC_SRDY, + .gpio_ipc_sub_mrdy = GPIO_IPC_SUB_MRDY, + .gpio_ipc_sub_srdy = GPIO_IPC_SUB_SRDY, -__setup("ld9040.get_lcdtype=0x", ld9040_lcdtype_setup); + .cfg_gpio = ipc_spi_cfg_gpio, +}; + +static struct resource ipc_spi_res[] = { + [0] = { + .start = IRQ_IPC_SRDY, + .end = IRQ_IPC_SRDY, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ipc_spi_device = { + .name = "onedram", + .id = -1, + .num_resources = ARRAY_SIZE(ipc_spi_res), + .resource = ipc_spi_res, + .dev = { + .platform_data = &ipc_spi_data, + }, +}; -static int lcd_cfg_gpio(void) +static void ipc_spi_cfg_gpio(void) { - int i, f3_end = 4; + int err = 0; - for (i = 0; i < 8; i++) { - /* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */ - s3c_gpio_cfgpin(EXYNOS4_GPF0(i), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPF0(i), S3C_GPIO_PULL_NONE); + unsigned gpio_ipc_mrdy = ipc_spi_data.gpio_ipc_mrdy; + unsigned gpio_ipc_srdy = ipc_spi_data.gpio_ipc_srdy; + unsigned gpio_ipc_sub_mrdy = ipc_spi_data.gpio_ipc_sub_mrdy; + unsigned gpio_ipc_sub_srdy = ipc_spi_data.gpio_ipc_sub_srdy; + err = gpio_request(gpio_ipc_mrdy, "IPC_MRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_MRDY", err); + } else { + gpio_direction_output(gpio_ipc_mrdy, 0); + s3c_gpio_setpull(gpio_ipc_mrdy, S3C_GPIO_PULL_DOWN); } - for (i = 0; i < 8; i++) { - s3c_gpio_cfgpin(EXYNOS4_GPF1(i), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPF1(i), S3C_GPIO_PULL_NONE); + + err = gpio_request(gpio_ipc_srdy, "IPC_SRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_SRDY", err); + } else { + gpio_direction_input(gpio_ipc_srdy); + s3c_gpio_cfgpin(gpio_ipc_srdy, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_ipc_srdy, S3C_GPIO_PULL_NONE); } - for (i = 0; i < 8; i++) { - s3c_gpio_cfgpin(EXYNOS4_GPF2(i), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPF2(i), S3C_GPIO_PULL_NONE); + err = gpio_request(gpio_ipc_sub_mrdy, "IPC_SUB_MRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_SUB_MRDY", err); + } else { + gpio_direction_output(gpio_ipc_sub_mrdy, 0); + s3c_gpio_setpull(gpio_ipc_sub_mrdy, S3C_GPIO_PULL_DOWN); } - for (i = 0; i < f3_end; i++) { - s3c_gpio_cfgpin(EXYNOS4_GPF3(i), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE); + err = gpio_request(gpio_ipc_sub_srdy, "IPC_SUB_SRDY"); + if (err) { + printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", + "IPC_SUB_SRDY", err); + } else { + gpio_direction_input(gpio_ipc_sub_srdy); + s3c_gpio_cfgpin(gpio_ipc_sub_srdy, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_ipc_sub_srdy, S3C_GPIO_PULL_NONE); } -#ifdef MAX_DRVSTR - /* drive strength to max */ - writel(0xffffffff, S5P_VA_GPIO + 0x18c); - writel(0xffffffff, S5P_VA_GPIO + 0x1ac); - writel(0xffffffff, S5P_VA_GPIO + 0x1cc); - writel(readl(S5P_VA_GPIO + 0x1ec) | 0xffffff, S5P_VA_GPIO + 0x1ec); -#else - /* drive strength to 2X */ - writel(0xaaaaaaaa, S5P_VA_GPIO + 0x18c); - writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1ac); - writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1cc); - writel(readl(S5P_VA_GPIO + 0x1ec) | 0xaaaaaa, S5P_VA_GPIO + 0x1ec); -#endif - -#if !defined(CONFIG_MACH_U1_KOR_LGT) - /* MLCD_RST */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE); - - /* LCD_nCS */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE); - /* LCD_SCLK */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE); - /* LCD_SDI */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE); -#else - /* MLCD_RST */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPX1(3), S3C_GPIO_PULL_NONE); - /* LCD_nCS */ - s3c_gpio_cfgpin(EXYNOS4_GPY0(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY0(3), S3C_GPIO_PULL_NONE); - /* LCD_SCLK */ - s3c_gpio_cfgpin(EXYNOS4210_GPE2(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4210_GPE2(3), S3C_GPIO_PULL_NONE); - /* LCD_SDI */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(1), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_to_irq(GPIO_IPC_SRDY), IRQ_TYPE_EDGE_RISING); + irq_set_irq_type(gpio_to_irq(GPIO_IPC_SUB_SRDY), IRQ_TYPE_EDGE_RISING); +} #endif - return 0; +#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_FLEXRATE +static void flexrate_work(struct work_struct *work) +{ + cpufreq_ondemand_flexrate_request(10000, 10); } +static DECLARE_WORK(flex_work, flexrate_work); +#endif -static int lcd_power_on(struct lcd_device *ld, int enable) +#include <linux/pm_qos_params.h> +static struct pm_qos_request_list busfreq_qos; +static void flexrate_qos_cancel(struct work_struct *work) { - struct regulator *regulator; + pm_qos_update_request(&busfreq_qos, 0); +} - if (ld == NULL) { - printk(KERN_ERR "lcd device object is NULL.\n"); - return 0; +static DECLARE_DELAYED_WORK(busqos_work, flexrate_qos_cancel); + +void tsp_request_qos(void *data) +{ +#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_FLEXRATE + if (!work_pending(&flex_work)) + schedule_work_on(0, &flex_work); +#endif + /* Guarantee that the bus runs at >= 266MHz */ + if (!pm_qos_request_active(&busfreq_qos)) + pm_qos_add_request(&busfreq_qos, PM_QOS_BUS_DMA_THROUGHPUT, + 266000); + else { + cancel_delayed_work_sync(&busqos_work); + pm_qos_update_request(&busfreq_qos, 266000); } - if (enable) { - regulator = regulator_get(NULL, "vlcd_3.0v"); - if (IS_ERR(regulator)) - return 0; + /* Cancel the QoS request after 1/10 sec */ + schedule_delayed_work_on(0, &busqos_work, HZ / 5); +} - regulator_enable(regulator); - regulator_put(regulator); - } else { - regulator = regulator_get(NULL, "vlcd_3.0v"); +#ifdef CONFIG_TOUCHSCREEN_MELFAS_MMS +static int melfas_mms_power(int on) +{ + if (on) { + gpio_request(GPIO_TSP_LDO_ON, "TSP_LDO_ON"); + s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_TSP_LDO_ON, GPIO_LEVEL_HIGH); - if (IS_ERR(regulator)) - return 0; + mdelay(70); + gpio_request(GPIO_TSP_INT, "TSP_INT"); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); + printk(KERN_INFO "[TSP]melfas power on\n"); + return 0; + } else { + gpio_request(GPIO_TSP_INT, "TSP_INT"); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN); - regulator_put(regulator); - } + gpio_request(GPIO_TSP_LDO_ON, "TSP_LDO_ON"); + s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_TSP_LDO_ON, GPIO_LEVEL_LOW); - return 1; + printk(KERN_INFO "[TSP]melfas power on\n"); + return 0; + } } -static int reset_lcd(struct lcd_device *ld) +static int melfas_mms_mux_fw_flash(bool to_gpios) { - int reset_gpio = -1; - int err; - -#if !defined(CONFIG_MACH_U1_KOR_LGT) - reset_gpio = EXYNOS4_GPY4(5); -#else - reset_gpio = EXYNOS4_GPX1(3); -#endif + pr_info("%s:to_gpios=%d\n", __func__, to_gpios); - err = gpio_request(reset_gpio, "MLCD_RST"); - if (err) { - printk(KERN_ERR "failed to request MLCD_RST for " - "lcd reset control\n"); - return err; - } + /* TOUCH_EN is always an output */ + if (to_gpios) { + if (gpio_request(GPIO_TSP_SCL, "GPIO_TSP_SCL")) + pr_err("failed to request gpio(GPIO_TSP_SCL)\n"); + if (gpio_request(GPIO_TSP_SDA, "GPIO_TSP_SDA")) + pr_err("failed to request gpio(GPIO_TSP_SDA)\n"); - gpio_request(reset_gpio, "MLCD_RST"); + gpio_direction_output(GPIO_TSP_INT, 0); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); - gpio_direction_output(reset_gpio, 1); - mdelay(5); - gpio_direction_output(reset_gpio, 0); - mdelay(5); - gpio_direction_output(reset_gpio, 1); + gpio_direction_output(GPIO_TSP_SCL, 0); + s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_NONE); - gpio_free(reset_gpio); + gpio_direction_output(GPIO_TSP_SDA, 0); + s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_NONE); - return 1; + } else { + gpio_direction_output(GPIO_TSP_INT, 1); + gpio_direction_input(GPIO_TSP_INT); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); + /*s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); */ + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + /*S3C_GPIO_PULL_UP */ + + gpio_direction_output(GPIO_TSP_SCL, 1); + gpio_direction_input(GPIO_TSP_SCL); + s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_NONE); + + gpio_direction_output(GPIO_TSP_SDA, 1); + gpio_direction_input(GPIO_TSP_SDA); + s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_NONE); + + gpio_free(GPIO_TSP_SCL); + gpio_free(GPIO_TSP_SDA); + } + return 0; } -static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld) +static int is_melfas_mms_vdd_on(void) { - int reset_gpio = -1; - int err; - -#if !defined(CONFIG_MACH_U1_KOR_LGT) - reset_gpio = EXYNOS4_GPY4(5); -#else - reset_gpio = EXYNOS4_GPX1(3); -#endif + int ret; + /* 3.3V */ + static struct regulator *regulator; - err = gpio_request(reset_gpio, "MLCD_RST"); - if (err) { - printk(KERN_ERR "failed to request MLCD_RST for " - "lcd reset control\n"); - return err; + if (!regulator) { + regulator = regulator_get(NULL, "touch"); + if (IS_ERR(regulator)) { + ret = PTR_ERR(regulator); + pr_err("could not get touch, rc = %d\n", ret); + return ret; + } } - mdelay(5); - gpio_direction_output(reset_gpio, 0); + if (regulator_is_enabled(regulator)) + return 1; + else + return 0; +} - gpio_free(reset_gpio); +struct tsp_callbacks *charger_callbacks; +struct tsp_callbacks { + void (*inform_charger)(struct tsp_callbacks *, bool); +}; - return 0; +static void tsp_charger_infom(bool en) +{ + if (charger_callbacks && charger_callbacks->inform_charger) + charger_callbacks->inform_charger(charger_callbacks, en); } -static int lcd_gpio_cfg_lateresume(struct lcd_device *ld) +static void melfas_register_callback(void *cb) { -#if !defined(CONFIG_MACH_U1_KOR_LGT) - /* MLCD_RST */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE); - - /* LCD_nCS */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE); - /* LCD_SCLK */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE); - /* LCD_SDI */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE); -#else - /* MLCD_RST */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPX1(3), S3C_GPIO_PULL_NONE); - /* LCD_nCS */ - s3c_gpio_cfgpin(EXYNOS4_GPY0(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY0(3), S3C_GPIO_PULL_NONE); - /* LCD_SCLK */ - s3c_gpio_cfgpin(EXYNOS4210_GPE2(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4210_GPE2(3), S3C_GPIO_PULL_NONE); - /* LCD_SDI */ - s3c_gpio_cfgpin(EXYNOS4_GPX1(1), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPX1(1), S3C_GPIO_PULL_NONE); -#endif - - return 0; + charger_callbacks = cb; + pr_debug("[TSP] melfas_register_callback\n"); } -static struct s3cfb_lcd ld9040_info = { - .width = 480, - .height = 800, - .p_width = 56, - .p_height = 93, - .bpp = 24, - - .freq = 60, - .timing = { - .h_fp = 16, - .h_bp = 14, - .h_sw = 2, - .v_fp = 10, - .v_fpe = 1, - .v_bp = 4, - .v_bpe = 1, - .v_sw = 2, - }, - .polarity = { - .rise_vclk = 1, - .inv_hsync = 1, - .inv_vsync = 1, - .inv_vden = 1, +static struct melfas_mms_platform_data melfas_mms_ts_pdata = { + .max_x = 720, + .max_y = 1280, + .invert_x = 0, + .invert_y = 0, + .gpio_int = GPIO_TSP_INT, + .gpio_scl = GPIO_TSP_SCL, + .gpio_sda = GPIO_TSP_SDA, + .power = melfas_mms_power, + .mux_fw_flash = melfas_mms_mux_fw_flash, + .is_vdd_on = is_melfas_mms_vdd_on, + .input_event = tsp_request_qos, + .register_cb = melfas_register_callback, +}; + +static struct melfas_mms_platform_data melfas_mms_ts_pdata_rotate = { + .max_x = 720, + .max_y = 1280, + .invert_x = 720, + .invert_y = 1280, + .gpio_int = GPIO_TSP_INT, + .gpio_scl = GPIO_TSP_SCL, + .gpio_sda = GPIO_TSP_SDA, + .power = melfas_mms_power, + .mux_fw_flash = melfas_mms_mux_fw_flash, + .is_vdd_on = is_melfas_mms_vdd_on, + .input_event = tsp_request_qos, + .register_cb = melfas_register_callback, +}; + +#endif + +#ifdef CONFIG_DRM_EXYNOS +static struct resource exynos_drm_resource[] = { + [0] = { + .start = IRQ_FIMD0_VSYNC, + .end = IRQ_FIMD0_VSYNC, + .flags = IORESOURCE_IRQ, }, }; -static struct lcd_platform_data ld9040_platform_data = { - .reset = reset_lcd, - .power_on = lcd_power_on, - .gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend, - .gpio_cfg_lateresume = lcd_gpio_cfg_lateresume, - /* it indicates whether lcd panel is enabled from u-boot. */ - .lcd_enabled = 1, - .reset_delay = 20, /* 10ms */ - .power_on_delay = 20, /* 20ms */ - .power_off_delay = 200, /* 120ms */ - .pdata = &u1_panel_data, +static struct platform_device exynos_drm_device = { + .name = "exynos-drm", + .id = -1, + .num_resources = ARRAY_SIZE(exynos_drm_resource), + .resource = exynos_drm_resource, + .dev = { + .dma_mask = &exynos_drm_device.dev.coherent_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + } }; - -#define LCD_BUS_NUM 3 -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define DISPLAY_CS EXYNOS4_GPY4(3) -#else -#define DISPLAY_CS EXYNOS4_GPY0(3) #endif -static struct spi_board_info spi_board_info[] __initdata = { - { - .max_speed_hz = 1200000, - .bus_num = LCD_BUS_NUM, - .chip_select = 0, - .mode = SPI_MODE_3, - .controller_data = (void *)DISPLAY_CS, + +#ifdef CONFIG_DRM_EXYNOS_FIMD +static struct exynos_drm_fimd_pdata drm_fimd_pdata = { + .panel = { + .timing = { + .xres = 720, + .yres = 1280, + .hsync_len = 5, + .left_margin = 5, + .right_margin = 5, + .vsync_len = 2, + .upper_margin = 1, + .lower_margin = 13, + .refresh = 60, + }, + .width_mm = 58, + .height_mm = 103, }, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_VCLK, + .default_win = 3, + .bpp = 32, + .dynamic_refresh = 0, + .high_freq = 1, }; -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define DISPLAY_CLK EXYNOS4_GPY3(1) -#define DISPLAY_SI EXYNOS4_GPY3(3) -#else -#define DISPLAY_CLK EXYNOS4210_GPE2(3) -#define DISPLAY_SI EXYNOS4_GPX1(1) -#endif -static struct spi_gpio_platform_data lcd_spi_gpio_data = { - .sck = DISPLAY_CLK, - .mosi = DISPLAY_SI, - .miso = SPI_GPIO_NO_MISO, - .num_chipselect = 1, +#ifdef CONFIG_MDNIE_SUPPORT +static struct resource exynos4_fimd_lite_resource[] = { + [0] = { + .start = EXYNOS4_PA_LCD_LITE0, + .end = EXYNOS4_PA_LCD_LITE0 + S5P_SZ_LCD_LITE0 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_LCD_LITE0, + .end = IRQ_LCD_LITE0, + .flags = IORESOURCE_IRQ, + }, }; -static struct platform_device ld9040_spi_gpio = { - .name = "spi_gpio", - .id = LCD_BUS_NUM, - .dev = { - .parent = &s3c_device_fb.dev, - .platform_data = &lcd_spi_gpio_data, +static struct resource exynos4_mdnie_resource[] = { + [0] = { + .start = EXYNOS4_PA_MDNIE0, + .end = EXYNOS4_PA_MDNIE0 + S5P_SZ_MDNIE0 - 1, + .flags = IORESOURCE_MEM, }, }; -static struct s3c_platform_fb fb_platform_data __initdata = { - .hw_ver = 0x70, - .clk_name = "fimd", - .nr_wins = 5, -#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW - .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, -#else - .default_win = 0, -#endif - .swap = FB_SWAP_HWORD | FB_SWAP_WORD, - .lcd = &ld9040_info, +static struct mdnie_platform_data exynos4_mdnie_pdata = { + .width = 720, + .height = 1280, }; -/* reading with 3-WIRE SPI with GPIO */ -static inline void setcs(u8 is_on) -{ - gpio_set_value(DISPLAY_CS, is_on); -} +static struct s5p_fimd_ext_device exynos4_fimd_lite_device = { + .name = "fimd_lite", + .id = -1, + .num_resources = ARRAY_SIZE(exynos4_fimd_lite_resource), + .resource = exynos4_fimd_lite_resource, + .dev = { + .platform_data = &drm_fimd_pdata, + }, +}; -static inline void setsck(u8 is_on) -{ - gpio_set_value(DISPLAY_CLK, is_on); -} +static struct s5p_fimd_ext_device exynos4_mdnie_device = { + .name = "mdnie", + .id = -1, + .num_resources = ARRAY_SIZE(exynos4_mdnie_resource), + .resource = exynos4_mdnie_resource, + .dev = { + .platform_data = &exynos4_mdnie_pdata, + }, +}; -static inline void setmosi(u8 is_on) +/* FIXME:!! why init at this point ? */ +int exynos4_common_setup_clock(const char *sclk_name, const char *pclk_name, + unsigned long rate, unsigned int rate_set) { - gpio_set_value(DISPLAY_SI, is_on); -} + struct clk *sclk = NULL; + struct clk *pclk = NULL; -static inline unsigned int getmiso(void) -{ - return !!gpio_get_value(DISPLAY_SI); -} + sclk = clk_get(NULL, sclk_name); + if (IS_ERR(sclk)) { + printk(KERN_ERR "failed to get %s clock.\n", sclk_name); + goto err_clk; + } -static inline void setmosi2miso(u8 is_on) -{ - if (is_on) - s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_INPUT); - else - s3c_gpio_cfgpin(DISPLAY_SI, S3C_GPIO_OUTPUT); -} + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + printk(KERN_ERR "failed to get %s clock.\n", pclk_name); + goto err_clk; + } -struct spi_ops ops = { - .setcs = setcs, - .setsck = setsck, - .setmosi = setmosi, - .setmosi2miso = setmosi2miso, - .getmiso = getmiso, -}; + clk_set_parent(sclk, pclk); -static void __init ld9040_fb_init(void) -{ - struct ld9040_panel_data *pdata; + printk(KERN_INFO "set parent clock of %s to %s\n", sclk_name, + pclk_name); + if (!rate_set) + goto set_end; - strcpy(spi_board_info[0].modalias, "ld9040"); - spi_board_info[0].platform_data = (void *)&ld9040_platform_data; + if (!rate) + rate = 200 * MHZ; - lcdtype = max(ld9040_lcdtype, lcdtype); + clk_set_rate(sclk, rate); - if (lcdtype == LCDTYPE_SM2_A2) - ld9040_platform_data.pdata = &u1_panel_data_a2; - else if (lcdtype == LCDTYPE_M2) - ld9040_platform_data.pdata = &u1_panel_data_m2; +set_end: + clk_put(sclk); + clk_put(pclk); - pdata = ld9040_platform_data.pdata; - pdata->ops = &ops; + return 0; - printk(KERN_INFO "%s :: lcdtype=%d\n", __func__, lcdtype); +err_clk: + clk_put(sclk); + clk_put(pclk); - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + return -EINVAL; - if (!ld9040_platform_data.lcd_enabled) - lcd_cfg_gpio(); - s3cfb_set_platdata(&fb_platform_data); } #endif -#ifdef CONFIG_FB_S5P_NT35560 -static int lcd_cfg_gpio(void) +static int reset_lcd(struct lcd_device *ld) +{ + static unsigned int first = 1; + int reset_gpio = -1; + + reset_gpio = EXYNOS4_GPY4(5); + + if (first) { + gpio_request(reset_gpio, "MLCD_RST"); + first = 0; + } + + gpio_direction_output(reset_gpio, 1); + usleep_range(1000, 2000); + gpio_direction_output(reset_gpio, 0); + usleep_range(1000, 2000); + gpio_direction_output(reset_gpio, 1); + + dev_info(&ld->dev, "reset completed.\n"); + + return 0; +} + +static struct lcd_property s6e8aa0_property = { + .flip = LCD_PROPERTY_FLIP_VERTICAL | + LCD_PROPERTY_FLIP_HORIZONTAL, + .dynamic_refresh = false, +}; + +static struct lcd_platform_data s6e8aa0_pdata = { + .reset = reset_lcd, + .reset_delay = 25, + .power_off_delay = 120, + .power_on_delay = 120, + .lcd_enabled = 1, + .pdata = &s6e8aa0_property, +}; + +static void lcd_cfg_gpio(void) { int i, f3_end = 4; + int reg; for (i = 0; i < 8; i++) { /* set GPF0,1,2[0:7] for RGB Interface and Data line (32bit) */ @@ -1993,309 +1901,189 @@ static int lcd_cfg_gpio(void) s3c_gpio_setpull(EXYNOS4_GPF3(i), S3C_GPIO_PULL_NONE); } -#ifdef MAX_DRVSTR - /* drive strength to max */ - writel(0xffffffff, S5P_VA_GPIO + 0x18c); - writel(0xffffffff, S5P_VA_GPIO + 0x1ac); - writel(0xffffffff, S5P_VA_GPIO + 0x1cc); - writel(readl(S5P_VA_GPIO + 0x1ec) | 0xffffff, S5P_VA_GPIO + 0x1ec); -#else - /* drive strength to 2X */ - writel(0xaaaaaaaa, S5P_VA_GPIO + 0x18c); - writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1ac); - writel(0xaaaaaaaa, S5P_VA_GPIO + 0x1cc); - writel(readl(S5P_VA_GPIO + 0x1ec) | 0xaaaaaa, S5P_VA_GPIO + 0x1ec); -#endif - - /* MLCD_RST */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE); - - /* LCD_nCS */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE); + reg = __raw_readl(S3C_VA_SYS + 0x210); + reg |= 1 << 1; + __raw_writel(reg, S3C_VA_SYS + 0x210); - /* LCD_SCLK */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE); - - /* LCD_SDI */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE); - - return 0; + return; } -static int lcd_power_on(struct lcd_device *ld, int enable) -{ - struct regulator *regulator; - - if (ld == NULL) { - printk(KERN_ERR "lcd device object is NULL.\n"); - return 0; - } - - if (enable) { - regulator = regulator_get(NULL, "vlcd_3.0v"); - if (IS_ERR(regulator)) - return 0; - - regulator_enable(regulator); - regulator_put(regulator); +#ifdef CONFIG_S5P_MIPI_DSI2 +static struct mipi_dsim_config dsim_config = { + .e_interface = DSIM_VIDEO, + .e_virtual_ch = DSIM_VIRTUAL_CH_0, + .e_pixel_format = DSIM_24BPP_888, + .e_burst_mode = DSIM_BURST_SYNC_EVENT, + .e_no_data_lane = DSIM_DATA_LANE_4, + .e_byte_clk = DSIM_PLL_OUT_DIV8, + .cmd_allow = 0xf, - regulator = regulator_get(NULL, "vlcd_1.8v"); - if (IS_ERR(regulator)) - return 0; - - regulator_enable(regulator); - regulator_put(regulator); - } else { - regulator = regulator_get(NULL, "vlcd_1.8v"); - - if (IS_ERR(regulator)) - return 0; - - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - - regulator_put(regulator); - - regulator = regulator_get(NULL, "vlcd_3.0v"); - - if (IS_ERR(regulator)) - return 0; - - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - - regulator_put(regulator); - } + /* + * =========================================== + * | P | M | S | MHz | + * ------------------------------------------- + * | 3 | 100 | 3 | 100 | + * | 3 | 100 | 2 | 200 | + * | 3 | 63 | 1 | 252 | + * | 4 | 100 | 1 | 300 | + * | 4 | 110 | 1 | 330 | + * | 12 | 350 | 1 | 350 | + * | 3 | 100 | 1 | 400 | + * | 4 | 150 | 1 | 450 | + * | 3 | 120 | 1 | 480 | + * | 12 | 250 | 0 | 500 | + * | 4 | 100 | 0 | 600 | + * | 3 | 81 | 0 | 648 | + * | 3 | 88 | 0 | 704 | + * | 3 | 90 | 0 | 720 | + * | 3 | 100 | 0 | 800 | + * | 12 | 425 | 0 | 850 | + * | 4 | 150 | 0 | 900 | + * | 12 | 475 | 0 | 950 | + * | 6 | 250 | 0 | 1000 | + * ------------------------------------------- + */ - return 1; -} + .p = 12, + .m = 250, + .s = 0, -static int reset_lcd(struct lcd_device *ld) -{ - int reset_gpio = -1; - int err; + /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ + .pll_stable_time = 500, - reset_gpio = EXYNOS4_GPY4(5); + /* escape clk : 10MHz */ + .esc_clk = 10 * 1000000, - err = gpio_request(reset_gpio, "MLCD_RST"); - if (err) { - printk(KERN_ERR "failed to request MLCD_RST for " - "lcd reset control\n"); - return err; - } - - gpio_request(reset_gpio, "MLCD_RST"); + /* stop state holding counter after bta change count 0 ~ 0xfff */ + .stop_holding_cnt = 0x7ff, + /* bta timeout 0 ~ 0xff */ + .bta_timeout = 0xff, + /* lp rx timeout 0 ~ 0xffff */ + .rx_timeout = 0xffff, +}; - gpio_direction_output(reset_gpio, 1); - mdelay(5); - gpio_direction_output(reset_gpio, 0); - mdelay(5); - gpio_direction_output(reset_gpio, 1); +static struct s5p_platform_mipi_dsim dsim_platform_data = { + /* already enabled at boot loader. FIXME!!! */ + .enabled = true, + .phy_enable = s5p_dsim_phy_enable, + .dsim_config = &dsim_config, +}; - gpio_free(reset_gpio); +static struct mipi_dsim_lcd_device mipi_lcd_device = { + .name = "s6e8aa0", + .id = -1, + .bus_id = 0, - return 1; -} + .platform_data = (void *)&s6e8aa0_pdata, +}; +#endif -static int lcd_gpio_cfg_earlysuspend(struct lcd_device *ld) +static void __init trats_fb_init(void) { - int reset_gpio = -1; - int err; - - reset_gpio = EXYNOS4_GPY4(5); - - err = gpio_request(reset_gpio, "MLCD_RST"); - if (err) { - printk(KERN_ERR "failed to request MLCD_RST for " - "lcd reset control\n"); - return err; - } +#ifdef CONFIG_S5P_MIPI_DSI2 + struct s5p_platform_mipi_dsim *dsim_pdata; - mdelay(5); - gpio_direction_output(reset_gpio, 0); + dsim_pdata = (struct s5p_platform_mipi_dsim *)&dsim_platform_data; + strcpy(dsim_pdata->lcd_panel_name, "s6e8aa0"); + dsim_pdata->lcd_panel_info = (void *)&drm_fimd_pdata.panel.timing; - gpio_free(reset_gpio); + s5p_mipi_dsi_register_lcd_device(&mipi_lcd_device); +#ifdef CONFIG_MDNIE_SUPPORT + s5p_fimd_ext_device_register(&exynos4_mdnie_device); + s5p_fimd_ext_device_register(&exynos4_fimd_lite_device); + exynos4_common_setup_clock("sclk_mdnie", "mout_mpll_user", + 400 * MHZ, 1); +#endif + s5p_device_mipi_dsim0.dev.platform_data = (void *)&dsim_platform_data; + platform_device_register(&s5p_device_mipi_dsim0); +#endif - return 0; + s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; + lcd_cfg_gpio(); } -static int lcd_gpio_cfg_lateresume(struct lcd_device *ld) +static unsigned long fbmem_start; +static int __init early_fbmem(char *p) { - /* MLCD_RST */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE); - - /* LCD_nCS */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(3), S3C_GPIO_PULL_NONE); + char *endp; + unsigned long size; - /* LCD_SCLK */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(1), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(1), S3C_GPIO_PULL_NONE); + if (!p) + return -EINVAL; - /* LCD_SDI */ - s3c_gpio_cfgpin(EXYNOS4_GPY3(3), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY3(3), S3C_GPIO_PULL_NONE); + size = memparse(p, &endp); + if (*endp == '@') + fbmem_start = memparse(endp + 1, &endp); - return 0; + return endp > p ? 0 : -EINVAL; } +early_param("fbmem", early_fbmem); +#endif -static struct s3cfb_lcd nt35560_info = { - .width = 480, - .height = 800, - .p_width = 52, - .p_height = 86, - .bpp = 24, - - .freq = 60, - .timing = { - .h_fp = 10, - .h_bp = 10, - .h_sw = 10, - .v_fp = 9, - .v_fpe = 1, - .v_bp = 4, - .v_bpe = 1, - .v_sw = 2, - }, - .polarity = { - .rise_vclk = 1, - .inv_hsync = 1, - .inv_vsync = 1, - .inv_vden = 1, - }, -}; - -static struct lcd_platform_data nt35560_platform_data = { - .reset = reset_lcd, - .power_on = lcd_power_on, - .gpio_cfg_earlysuspend = lcd_gpio_cfg_earlysuspend, - .gpio_cfg_lateresume = lcd_gpio_cfg_lateresume, - /* it indicates whether lcd panel is enabled from u-boot. */ - .lcd_enabled = 1, - .reset_delay = 10, /* 10ms */ - .power_on_delay = 10, /* 10ms */ - .power_off_delay = 150, /* 150ms */ +#ifdef CONFIG_DRM_EXYNOS_HDMI +/* I2C HDMIPHY */ +static struct s3c2410_platform_i2c hdmiphy_i2c_data __initdata = { + .bus_num = 8, + .flags = 0, + .slave_addr = 0x10, + .frequency = 100*1000, + .sda_delay = 100, }; -#define LCD_BUS_NUM 3 -#define DISPLAY_CS EXYNOS4_GPY4(3) -static struct spi_board_info spi_board_info[] __initdata = { +static struct i2c_board_info i2c_hdmiphy_devs[] __initdata = { { - .max_speed_hz = 1200000, - .bus_num = LCD_BUS_NUM, - .chip_select = 0, - .mode = SPI_MODE_3, - .controller_data = (void *)DISPLAY_CS, + /* hdmiphy */ + I2C_BOARD_INFO("s5p_hdmiphy", (0x70 >> 1)), }, }; -#define DISPLAY_CLK EXYNOS4_GPY3(1) -#define DISPLAY_SI EXYNOS4_GPY3(3) -static struct spi_gpio_platform_data lcd_spi_gpio_data = { - .sck = DISPLAY_CLK, - .mosi = DISPLAY_SI, - .miso = SPI_GPIO_NO_MISO, - .num_chipselect = 1, +static struct exynos_drm_hdmi_pdata drm_hdmi_pdata = { + .is_v13 = true, + .cfg_hpd = s5p_hdmi_cfg_hpd, + .get_hpd = s5p_hdmi_get_hpd, }; -static struct platform_device nt35560_spi_gpio = { - .name = "spi_gpio", - .id = LCD_BUS_NUM, - .dev = { - .parent = &s3c_device_fb.dev, - .platform_data = &lcd_spi_gpio_data, - }, +static struct exynos_drm_common_hdmi_pd drm_common_hdmi_pdata = { + .hdmi_dev = &s5p_device_hdmi.dev, + .mixer_dev = &s5p_device_mixer.dev, }; -static struct s3c_platform_fb fb_platform_data __initdata = { - .hw_ver = 0x70, - .clk_name = "fimd", - .nr_wins = 5, -#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW - .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, -#else - .default_win = 0, -#endif - .swap = FB_SWAP_HWORD | FB_SWAP_WORD, - .lcd = &nt35560_info, +static struct platform_device exynos_drm_hdmi_device = { + .name = "exynos-drm-hdmi", + .dev = { + .platform_data = &drm_common_hdmi_pdata, + }, }; -static void __init nt35560_fb_init(void) +static void trats_tv_init(void) { - struct ld9040_panel_data *pdata; - - strcpy(spi_board_info[0].modalias, "nt35560"); - spi_board_info[0].platform_data = (void *)&nt35560_platform_data; - - pdata = nt35560_platform_data.pdata; + /* HDMI PHY */ + s5p_i2c_hdmiphy_set_platdata(&hdmiphy_i2c_data); + i2c_register_board_info(8, i2c_hdmiphy_devs, + ARRAY_SIZE(i2c_hdmiphy_devs)); - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); + gpio_request(GPIO_HDMI_HPD, "HDMI_HPD"); + gpio_direction_input(GPIO_HDMI_HPD); + s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0x3)); + s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN); - if (!nt35560_platform_data.lcd_enabled) - lcd_cfg_gpio(); - s3cfb_set_platdata(&fb_platform_data); -} +#ifdef CONFIG_EXYNOS_DEV_PD + s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev; + s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev; #endif + s5p_device_hdmi.dev.platform_data = &drm_hdmi_pdata; +} -#ifdef CONFIG_FB_S5P_AMS369FG06 -static struct s3c_platform_fb ams369fg06_data __initdata = { - .hw_ver = 0x70, - .clk_name = "sclk_lcd", - .nr_wins = 5, - .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, - .swap = FB_SWAP_HWORD | FB_SWAP_WORD, -}; - -#define LCD_BUS_NUM 3 -#define DISPLAY_CS EXYNOS4_GPB(5) -#define DISPLAY_CLK EXYNOS4_GPB(4) -#define DISPLAY_SI EXYNOS4_GPB(7) - -static struct spi_board_info spi_board_info[] __initdata = { - { - .modalias = "ams369fg06", - .platform_data = NULL, - .max_speed_hz = 1200000, - .bus_num = LCD_BUS_NUM, - .chip_select = 0, - .mode = SPI_MODE_3, - .controller_data = (void *)DISPLAY_CS, - } -}; - -static struct spi_gpio_platform_data ams369fg06_spi_gpio_data = { - .sck = DISPLAY_CLK, - .mosi = DISPLAY_SI, - .miso = -1, - .num_chipselect = 1, -}; - -static struct platform_device s3c_device_spi_gpio = { - .name = "spi_gpio", - .id = LCD_BUS_NUM, - .dev = { - .parent = &s3c_device_fb.dev, - .platform_data = &ams369fg06_spi_gpio_data, - }, -}; +void mhl_hpd_handler(bool onoff) +{ + printk(KERN_INFO "hpd(%d)\n", onoff); +} +EXPORT_SYMBOL(mhl_hpd_handler); #endif -#ifdef CONFIG_FB_S5P_MDNIE -static struct platform_device mdnie_device = { - .name = "mdnie", - .id = -1, - .dev = { - .parent = &exynos4_device_pd[PD_LCD0].dev, - }, +static struct platform_device exynos_drm_vidi_device = { + .name = "exynos-drm-vidi", }; -#endif - -#endif static struct platform_device u1_regulator_consumer = { .name = "u1-regulator-consumer", @@ -2305,22 +2093,31 @@ static struct platform_device u1_regulator_consumer = { #ifdef CONFIG_REGULATOR_MAX8997 static struct regulator_consumer_supply ldo1_supply[] = { REGULATOR_SUPPLY("vadc_3.3v", NULL), + REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), }; static struct regulator_consumer_supply ldo3_supply[] = { REGULATOR_SUPPLY("vusb_1.1v", "usb_otg"), - REGULATOR_SUPPLY("vmipi_1.1v", "m9mo"), + REGULATOR_SUPPLY("vmipi_1.1v", "m5mo"), REGULATOR_SUPPLY("vmipi_1.1v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), + REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), }; static struct regulator_consumer_supply ldo4_supply[] = { REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"), }; static struct regulator_consumer_supply ldo5_supply[] = { REGULATOR_SUPPLY("vhsic", NULL), }; +static struct regulator_consumer_supply ldo6_supply[] = { + REGULATOR_SUPPLY("v_gps_1.8v", "gsd4t"), +}; + static struct regulator_consumer_supply ldo7_supply[] = { REGULATOR_SUPPLY("cam_isp", NULL), }; @@ -2339,28 +2136,17 @@ static struct regulator_consumer_supply ldo10_supply[] = { }; #endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -static struct regulator_consumer_supply ldo11_supply[] = { - REGULATOR_SUPPLY("top_3.3v", NULL), -}; -#else static struct regulator_consumer_supply ldo11_supply[] = { REGULATOR_SUPPLY("touch", NULL), }; -#endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -static struct regulator_consumer_supply ldo12_supply[] = { - REGULATOR_SUPPLY("vlcd_1.8v", NULL), -}; -#else static struct regulator_consumer_supply ldo12_supply[] = { REGULATOR_SUPPLY("vt_cam_1.8v", NULL), }; -#endif static struct regulator_consumer_supply ldo13_supply[] = { REGULATOR_SUPPLY("vlcd_3.0v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), }; #ifdef CONFIG_MACH_Q1_BD @@ -2373,39 +2159,22 @@ static struct regulator_consumer_supply ldo14_supply[] = { }; #endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -static struct regulator_consumer_supply ldo15_supply[] = { - REGULATOR_SUPPLY("ois_1.5v", NULL), -}; -#else static struct regulator_consumer_supply ldo15_supply[] = { - REGULATOR_SUPPLY("vled", NULL), + REGULATOR_SUPPLY("vlcd_2.2v", NULL), + REGULATOR_SUPPLY("VDD3", "s6e8aa0"), }; -#endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -static struct regulator_consumer_supply ldo16_supply[] = { - REGULATOR_SUPPLY("cis_1.8v", NULL), -}; -#else static struct regulator_consumer_supply ldo16_supply[] = { REGULATOR_SUPPLY("cam_sensor_io", NULL), }; -#endif static struct regulator_consumer_supply ldo17_supply[] = { REGULATOR_SUPPLY("vtf_2.8v", NULL), }; -#if defined(CONFIG_MACH_U1CAMERA_BD) -static struct regulator_consumer_supply ldo18_supply[] = { - REGULATOR_SUPPLY("cis_2.8v", NULL), -}; -#else static struct regulator_consumer_supply ldo18_supply[] = { REGULATOR_SUPPLY("touch_led", NULL), }; -#endif static struct regulator_consumer_supply ldo21_supply[] = { @@ -2454,6 +2223,12 @@ static struct regulator_consumer_supply led_torch_supply[] = { }; #endif /* CONFIG_MACH_Q1_BD */ +static struct regulator_consumer_supply enp_32khz_ap_consumer[] = { + REGULATOR_SUPPLY("gps_clk", "gsd4t"), + REGULATOR_SUPPLY("bt_clk", NULL), + REGULATOR_SUPPLY("wifi_clk", NULL), +}; + #define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ _disabled) \ static struct regulator_init_data _ldo##_init_data = { \ @@ -2477,7 +2252,7 @@ static struct regulator_consumer_supply led_torch_supply[] = { }; REGULATOR_INIT(ldo1, "VADC_3.3V_C210", 3300000, 3300000, 1, - REGULATOR_CHANGE_STATUS, 1); + REGULATOR_CHANGE_STATUS, 0); REGULATOR_INIT(ldo3, "VUSB_1.1V", 1100000, 1100000, 1, REGULATOR_CHANGE_STATUS, 1); REGULATOR_INIT(ldo4, "VMIPI_1.8V", 1800000, 1800000, 1, @@ -2489,6 +2264,8 @@ REGULATOR_INIT(ldo5, "VHSIC_1.2V", 1200000, 1200000, 0, REGULATOR_INIT(ldo5, "VHSIC_1.2V", 1200000, 1200000, 1, REGULATOR_CHANGE_STATUS, 1); #endif +REGULATOR_INIT(ldo6, "VCC_1.8V_PDA", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 1); REGULATOR_INIT(ldo7, "CAM_ISP_1.8V", 1800000, 1800000, 0, REGULATOR_CHANGE_STATUS, 1); REGULATOR_INIT(ldo8, "VUSB_3.3V", 3300000, 3300000, 1, @@ -2500,54 +2277,36 @@ REGULATOR_INIT(ldo10, "VPLL_1.2V", 1200000, 1200000, 1, REGULATOR_INIT(ldo10, "VPLL_1.1V", 1100000, 1100000, 1, REGULATOR_CHANGE_STATUS, 1); #endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -REGULATOR_INIT(ldo11, "TOP_3.3V", 3300000, 3300000, 1, - REGULATOR_CHANGE_STATUS, 1); -#else REGULATOR_INIT(ldo11, "TOUCH_2.8V", 2800000, 2800000, 0, REGULATOR_CHANGE_STATUS, 1); -#endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -REGULATOR_INIT(ldo12, "VLCD_1.8V", 1800000, 1800000, 1, - REGULATOR_CHANGE_STATUS, 1); -#else REGULATOR_INIT(ldo12, "VT_CAM_1.8V", 1800000, 1800000, 0, REGULATOR_CHANGE_STATUS, 1); -#endif +#if defined(CONFIG_MACH_Q1_BD) +REGULATOR_INIT(ldo13, "VCC_3.0V_LCD", 3100000, 3100000, 1, + REGULATOR_CHANGE_STATUS, 1); +#else REGULATOR_INIT(ldo13, "VCC_3.0V_LCD", 3000000, 3000000, 1, REGULATOR_CHANGE_STATUS, 1); +#endif #if defined(CONFIG_MACH_Q1_BD) REGULATOR_INIT(ldo14, "VCC_2.2V_LCD", 2200000, 2200000, 1, REGULATOR_CHANGE_STATUS, 1); -#elif defined(CONFIG_MACH_U1CAMERA_BD) -REGULATOR_INIT(ldo14, "MOT_3.3V", 3300000, 3300000, 1, - REGULATOR_CHANGE_STATUS, 1); #else REGULATOR_INIT(ldo14, "VCC_2.8V_MOTOR", 2800000, 2800000, 0, REGULATOR_CHANGE_STATUS, 1); #endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -REGULATOR_INIT(ldo15, "OIS_1.5V", 1500000, 1500000, 0, - REGULATOR_CHANGE_STATUS, 1); -#else -REGULATOR_INIT(ldo15, "LED_A_2.8V", 2800000, 2800000, 0, - REGULATOR_CHANGE_STATUS, -1); -#endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -REGULATOR_INIT(ldo16, "CIS_1.8V", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -#else +REGULATOR_INIT(ldo15, "VDD_2.2V_LCD", 2200000, 2200000, 1, + REGULATOR_CHANGE_STATUS, 1); REGULATOR_INIT(ldo16, "CAM_SENSOR_IO_1.8V", 1800000, 1800000, 0, REGULATOR_CHANGE_STATUS, 1); -#endif REGULATOR_INIT(ldo17, "VTF_2.8V", 2800000, 2800000, 0, REGULATOR_CHANGE_STATUS, 1); -#if defined(CONFIG_MACH_U1CAMERA_BD) -REGULATOR_INIT(ldo18, "CIS_2.8V", 2800000, 2800000, 0, +#if defined(CONFIG_MACH_Q1_BD) +REGULATOR_INIT(ldo18, "TOUCH_LED_3.3V", 3300000, 3300000, 0, REGULATOR_CHANGE_STATUS, 1); #else REGULATOR_INIT(ldo18, "TOUCH_LED_3.3V", 3000000, 3300000, 0, - REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, 1); + REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE, 1); #endif REGULATOR_INIT(ldo21, "VDDQ_M1M2_1.2V", 1200000, 1200000, 1, REGULATOR_CHANGE_STATUS, 1); @@ -2656,6 +2415,20 @@ static struct regulator_init_data buck7_init_data = { .consumer_supplies = &buck7_supply[0], }; +static struct regulator_init_data enp_32khz_ap_data = { + .constraints = { + .name = "32KHz AP", + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(enp_32khz_ap_consumer), + .consumer_supplies = enp_32khz_ap_consumer, +}; + static struct regulator_init_data safeout1_init_data = { .constraints = { .name = "safeout1 range", @@ -2734,6 +2507,7 @@ static struct max8997_regulator_data max8997_regulators[] = { { MAX8997_LDO3, &ldo3_init_data, NULL, }, { MAX8997_LDO4, &ldo4_init_data, NULL, }, { MAX8997_LDO5, &ldo5_init_data, NULL, }, + { MAX8997_LDO6, &ldo6_init_data, NULL, }, { MAX8997_LDO7, &ldo7_init_data, NULL, }, { MAX8997_LDO8, &ldo8_init_data, NULL, }, { MAX8997_LDO10, &ldo10_init_data, NULL, }, @@ -2759,6 +2533,7 @@ static struct max8997_regulator_data max8997_regulators[] = { #if defined CONFIG_MACH_Q1_BD { MAX8997_FLASH_TORCH, &led_torch_init_data, NULL, }, #endif /* CONFIG_MACH_Q1_BD */ + {MAX8997_EN32KHZ_AP, &enp_32khz_ap_data, NULL}, }; static struct max8997_power_data max8997_power = { @@ -2925,7 +2700,11 @@ static int max8997_muic_charger_cb(int cable_type) if (!psy) { pr_err("%s: fail to get battery ps\n", __func__); +#if defined(CONFIG_MACH_Q1_BD) + return 0; +#else return -ENODEV; +#endif } switch (cable_type) { @@ -2960,6 +2739,9 @@ static int max8997_muic_charger_cb(int cable_type) if (charging_cbs.tsp_set_charging_cable) charging_cbs.tsp_set_charging_cable(value.intval); +#ifdef CONFIG_JACK_MON + jack_event_handler("charger", is_cable_attached); +#endif return psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &value); } @@ -3060,6 +2842,15 @@ static void max8997_muic_usb_cb(u8 usb_mode) if (usb_mode == USB_OTGHOST_DETACHED) usb_otg_accessory_power(0); +#ifdef CONFIG_JACK_MON + if (usb_mode == USB_OTGHOST_ATTACHED) + jack_event_handler("host", USB_CABLE_ATTACHED); + else if (usb_mode == USB_OTGHOST_DETACHED) + jack_event_handler("host", USB_CABLE_DETACHED); + else if ((usb_mode == USB_CABLE_ATTACHED) + || (usb_mode == USB_CABLE_DETACHED)) + jack_event_handler("usb", usb_mode); +#endif } else pr_info("otg error s3c_udc is null.\n"); } @@ -3071,7 +2862,9 @@ static void max8997_muic_mhl_cb(int attached) if (attached == MAX8997_MUIC_ATTACHED) { #ifdef CONFIG_SAMSUNG_MHL - sii9234_mhl_detection_sched(); + mhl_onoff_ex(true); + } else if (attached == MAX8997_MUIC_DETACHED) { + mhl_onoff_ex(false); #endif } } @@ -3087,34 +2880,41 @@ static bool max8997_muic_is_mhl_attached(void) return !!val; } -static struct switch_dev switch_dock = { - .name = "dock", -}; - static void max8997_muic_deskdock_cb(bool attached) { +#ifdef CONFIG_JACK_MON if (attached) - switch_set_state(&switch_dock, 1); + jack_event_handler("cradle", 1); else - switch_set_state(&switch_dock, 0); + jack_event_handler("cradle", 0); +#endif } static void max8997_muic_cardock_cb(bool attached) { +#ifdef CONFIG_JACK_MON if (attached) - switch_set_state(&switch_dock, 2); + jack_event_handler("cradle", 2); else - switch_set_state(&switch_dock, 0); + jack_event_handler("cradle", 0); +#endif } -static void max8997_muic_init_cb(void) +static int max8997_muic_cfg_uart_gpio(void) { - int ret; + int val, path; - /* for CarDock, DeskDock */ - ret = switch_dev_register(&switch_dock); - if (ret < 0) - pr_err("Failed to register dock switch. %d\n", ret); + val = gpio_get_value(GPIO_UART_SEL); + path = val ? UART_PATH_AP : UART_PATH_CP; +#if 0 + /* Workaround + * Sometimes sleep current is 15 ~ 20mA if UART path was CP. + */ + if (path == UART_PATH_CP) + gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_HIGH); +#endif + pr_info("%s: path=%d\n", __func__, path); + return path; } static void max8997_muic_jig_uart_cb(int path) @@ -3148,12 +2948,61 @@ static struct max8997_muic_data max8997_muic = { .mhl_cb = max8997_muic_mhl_cb, .is_mhl_attached = max8997_muic_is_mhl_attached, .set_safeout = max8997_muic_set_safeout, - .init_cb = max8997_muic_init_cb, .deskdock_cb = max8997_muic_deskdock_cb, .cardock_cb = max8997_muic_cardock_cb, + .cfg_uart_gpio = max8997_muic_cfg_uart_gpio, .jig_uart_cb = max8997_muic_jig_uart_cb, .host_notify_cb = max8997_muic_host_notify_cb, + .gpio_usb_sel = GPIO_USB_SEL, +}; + +#ifdef CONFIG_UART_SELECT +/* Uart Select */ +static void trats_set_uart_switch(int path) +{ + gpio_request(GPIO_UART_SEL, "UART_SEL"); + + /* trats target is gpio_high == AP */ + if (path == UART_SW_PATH_AP) + gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_HIGH); + else if (path == UART_SW_PATH_CP) + gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_LOW); + + gpio_free(GPIO_UART_SEL); + return; +} + +static int trats_get_uart_switch(void) +{ + int val; + + gpio_request(GPIO_UART_SEL, "UART_SEL"); + val = gpio_get_value(GPIO_UART_SEL); + gpio_free(GPIO_UART_SEL); + + /* trats target is gpio_high == AP */ + if (val == GPIO_LEVEL_HIGH) + return UART_SW_PATH_AP; + else if (val == GPIO_LEVEL_LOW) + return UART_SW_PATH_CP; + else + return UART_SW_PATH_NA; +} + +static struct uart_select_platform_data trats_uart_select_data = { + .set_uart_switch = trats_set_uart_switch, + .get_uart_switch = trats_get_uart_switch, +}; + +static struct platform_device trats_uart_select = { + .name = "uart-select", + .id = -1, + .dev = { + .platform_data = &trats_uart_select_data, + }, }; +#endif + static struct max8997_buck1_dvs_funcs *buck1_dvs_funcs; @@ -3204,13 +3053,40 @@ static struct platform_device bcm4330_bluetooth_device = { }; #endif /* CONFIG_BT_BCM4330 */ +#ifdef CONFIG_GPS_GSD4T +/* GSD4T GPS */ +static struct gsd4t_platform_data u1_gsd4t_data = { + .onoff = GPIO_GPS_PWR_EN, + .nrst = GPIO_GPS_nRST, + .uart_rxd = GPIO_GPS_RXD, + .uart_txd = GPIO_GPS_TXD, + .uart_cts = GPIO_GPS_CTS, + .uart_rts = GPIO_GPS_RTS, +}; + +static struct platform_device u1_gsd4t = { + .name = "gsd4t", + .id = -1, + .dev = { + .platform_data = &u1_gsd4t_data, + }, +}; +#endif + #ifdef CONFIG_TARGET_LOCALE_KOR #define SYSTEM_REV_SND 0x05 #else #define SYSTEM_REV_SND 0x09 #endif -#ifdef CONFIG_SND_SOC_U1_MC1N2 +#if defined(CONFIG_SND_SOC_SLP_TRATS_MC1N2) +void sec_set_sub_mic_bias(bool on) +{ +#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS + gpio_set_value(GPIO_SUB_MIC_BIAS_EN, on); +#endif +} + void sec_set_main_mic_bias(bool on) { #ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS @@ -3242,10 +3118,11 @@ int sec_set_ldo1_constraints(int disabled) static struct mc1n2_platform_data mc1n2_pdata = { .set_main_mic_bias = sec_set_main_mic_bias, + .set_sub_mic_bias = sec_set_sub_mic_bias, .set_adc_power_constraints = sec_set_ldo1_constraints, }; -static void u1_sound_init(void) +static void trats_sound_init(void) { #ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS int err; @@ -3268,6 +3145,27 @@ static void u1_sound_init(void) gpio_set_value(GPIO_EAR_MIC_BIAS_EN, 0); gpio_free(GPIO_EAR_MIC_BIAS_EN); +#if defined(CONFIG_MACH_Q1_BD) + err = gpio_request(GPIO_SUB_MIC_BIAS_EN, "submic_bias"); + if (err) { + pr_err(KERN_ERR "SUB_MIC_BIAS_EN GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_SUB_MIC_BIAS_EN, 1); + gpio_set_value(GPIO_SUB_MIC_BIAS_EN, 0); + gpio_free(GPIO_SUB_MIC_BIAS_EN); + +#else + if (system_rev >= SYSTEM_REV_SND) { + err = gpio_request(GPIO_SUB_MIC_BIAS_EN, "submic_bias"); + if (err) { + pr_err(KERN_ERR "SUB_MIC_BIAS_EN GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_SUB_MIC_BIAS_EN, 0); + gpio_free(GPIO_SUB_MIC_BIAS_EN); + } +#endif /* #if defined(CONFIG_MACH_Q1_BD) */ #endif } #endif @@ -4021,6 +3919,113 @@ static struct i2c_board_info i2c_devs19_emul[] = { #endif #if defined(CONFIG_SEC_THERMISTOR) +#if defined(CONFIG_MACH_Q1_BD) +/* temperature table for ADC CH 6 */ +static struct sec_therm_adc_table adc_ch6_table[] = { + /* ADC, Temperature */ + { 165, 800 }, + { 173, 790 }, + { 179, 780 }, + { 185, 770 }, + { 191, 760 }, + { 197, 750 }, + { 203, 740 }, + { 209, 730 }, + { 215, 720 }, + { 221, 710 }, + { 227, 700 }, + { 236, 690 }, + { 247, 680 }, + { 258, 670 }, + { 269, 660 }, + { 281, 650 }, + { 296, 640 }, + { 311, 630 }, + { 326, 620 }, + { 341, 610 }, + { 356, 600 }, + { 372, 590 }, + { 386, 580 }, + { 400, 570 }, + { 414, 560 }, + { 428, 550 }, + { 442, 540 }, + { 456, 530 }, + { 470, 520 }, + { 484, 510 }, + { 498, 500 }, + { 508, 490 }, + { 517, 480 }, + { 526, 470 }, + { 535, 460 }, + { 544, 450 }, + { 553, 440 }, + { 562, 430 }, + { 576, 420 }, + { 594, 410 }, + { 612, 400 }, + { 630, 390 }, + { 648, 380 }, + { 666, 370 }, + { 684, 360 }, + { 702, 350 }, + { 725, 340 }, + { 749, 330 }, + { 773, 320 }, + { 797, 310 }, + { 821, 300 }, + { 847, 290 }, + { 870, 280 }, + { 893, 270 }, + { 916, 260 }, + { 939, 250 }, + { 962, 240 }, + { 985, 230 }, + { 1008, 220 }, + { 1031, 210 }, + { 1054, 200 }, + { 1081, 190 }, + { 1111, 180 }, + { 1141, 170 }, + { 1171, 160 }, + { 1201, 150 }, + { 1231, 140 }, + { 1261, 130 }, + { 1291, 120 }, + { 1321, 110 }, + { 1351, 100 }, + { 1358, 90 }, + { 1364, 80 }, + { 1370, 70 }, + { 1376, 60 }, + { 1382, 50 }, + { 1402, 40 }, + { 1422, 30 }, + { 1442, 20 }, + { 1462, 10 }, + { 1482, 0 }, + { 1519, -10 }, + { 1528, -20 }, + { 1546, -30 }, + { 1563, -40 }, + { 1587, -50 }, + { 1601, -60 }, + { 1614, -70 }, + { 1625, -80 }, + { 1641, -90 }, + { 1663, -100 }, + { 1680, -110 }, + { 1695, -120 }, + { 1710, -130 }, + { 1725, -140 }, + { 1740, -150 }, + { 1755, -160 }, + { 1770, -170 }, + { 1785, -180 }, + { 1800, -190 }, + { 1815, -200 }, +}; +#else /* temperature table for ADC CH 6 */ static struct sec_therm_adc_table adc_ch6_table[] = { /* ADC, Temperature */ @@ -4126,6 +4131,7 @@ static struct sec_therm_adc_table adc_ch6_table[] = { { 1834, -190 }, { 1845, -200 }, }; +#endif static struct sec_therm_platform_data sec_therm_pdata = { .adc_channel = 6, @@ -4143,87 +4149,6 @@ static struct platform_device sec_device_thermistor = { struct gpio_keys_button u1_buttons[] = { -#if defined(CONFIG_MACH_U1CAMERA_BD) - { - .code = KEY_POWER, - .gpio = GPIO_nPOWER, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - .isr_hook = sec_debug_check_crash_key, - }, - { - .code = KEY_RESERVED, - .gpio = GPIO_RSERVED_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_PLAY, - .gpio = GPIO_PLAY_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_RECORD, - .gpio = GPIO_RECORD_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_MENU, - .gpio = GPIO_MENU_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_HOME, - .gpio = GPIO_HOME_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_BACK, - .gpio = GPIO_BACK_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_CAMERA_FOCUS, - .gpio = GPIO_S1_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - /*KEY_CAMERA_SHUTTER*/ - .code = 0x220, - .gpio = GPIO_S2_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_CAMERA_ZOOMIN, - .gpio = GPIO_TELE_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, - { - .code = KEY_CAMERA_ZOOMOUT, - .gpio = GPIO_WIDE_KEY, - .active_low = 1, - .type = EV_KEY, - .wakeup = 1, - }, -#else { .code = KEY_VOLUMEUP, .gpio = GPIO_VOL_UP, @@ -4231,6 +4156,7 @@ struct gpio_keys_button u1_buttons[] = { .type = EV_KEY, .wakeup = 1, .isr_hook = sec_debug_check_crash_key, + .debounce_interval = 10, }, /* vol up */ { .code = KEY_VOLUMEDOWN, @@ -4239,6 +4165,7 @@ struct gpio_keys_button u1_buttons[] = { .type = EV_KEY, .wakeup = 1, .isr_hook = sec_debug_check_crash_key, + .debounce_interval = 10, }, /* vol down */ { .code = KEY_POWER, @@ -4247,6 +4174,7 @@ struct gpio_keys_button u1_buttons[] = { .type = EV_KEY, .wakeup = 1, .isr_hook = sec_debug_check_crash_key, + .debounce_interval = 10, }, /* power key */ { .code = KEY_HOME, @@ -4254,8 +4182,8 @@ struct gpio_keys_button u1_buttons[] = { .active_low = 1, .type = EV_KEY, .wakeup = 1, + .debounce_interval = 10, }, /* ok key */ -#endif }; struct gpio_keys_platform_data u1_keypad_platform_data = { @@ -4271,7 +4199,16 @@ struct platform_device u1_keypad = { #ifdef CONFIG_SEC_DEV_JACK static void sec_set_jack_micbias(bool on) { +#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS +#if defined(CONFIG_MACH_Q1_BD) + gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on); +#else + if (system_rev >= 3) gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on); + else + gpio_set_value(GPIO_MIC_BIAS_EN, on); +#endif /* #if defined(CONFIG_MACH_Q1_BD) */ +#endif /* #ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS */ } static struct sec_jack_zone sec_jack_zones[] = { @@ -4307,8 +4244,13 @@ static struct sec_jack_zone sec_jack_zones[] = { * stays in this range for 100ms (10ms delays, 10 samples) */ .adc_high = 3800, +#if defined(CONFIG_MACH_Q1_BD) + .delay_ms = 15, + .check_count = 20, +#else .delay_ms = 10, .check_count = 5, +#endif .jack_type = SEC_HEADSET_4POLE, }, { @@ -4328,12 +4270,20 @@ static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = { /* 0 <= adc <=170, stable zone */ .code = KEY_MEDIA, .adc_low = 0, +#if defined(CONFIG_TARGET_LOCALE_NTT) + .adc_high = 150, +#else .adc_high = 170, +#endif }, { /* 171 <= adc <= 370, stable zone */ .code = KEY_VOLUMEUP, +#if defined(CONFIG_TARGET_LOCALE_NTT) + .adc_low = 151, +#else .adc_low = 171, +#endif .adc_high = 370, }, { @@ -4361,839 +4311,6 @@ static struct platform_device sec_device_jack = { }; #endif -void tsp_register_callback(void *function) -{ - charging_cbs.tsp_set_charging_cable = function; -} - -void tsp_read_ta_status(void *ta_status) -{ - *(bool *)ta_status = is_cable_attached; -} -#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC -static void mxt224_power_on(void) -{ - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_LDO_ON, 1); - mdelay(70); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); - mdelay(40); -} - -static void mxt224_power_off(void) -{ - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN); - - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_LDO_ON, 0); -} - -static u8 t7_config[] = {GEN_POWERCONFIG_T7, - 64, 255, 50 -}; -static u8 t8_config[] = {GEN_ACQUISITIONCONFIG_T8, - 10, 0, 5, 1, 0, 0, 9, 27 -}; -static u8 t9_config[] = {TOUCH_MULTITOUCHSCREEN_T9, - 143, 0, 0, 18, 11, 0, 16, 32, 2, 0, - 0, 3, 1, 46, 10, 5, 40, 10, 31, 3, - 223, 1, 0, 0, 0, 0, 0, 0, 0, 0, - 18 -}; -static u8 t15_config[] = {TOUCH_KEYARRAY_T15, - 131, 16, 11, 2, 1, 0, 0, 45, 4, 0, - 0 -}; -static u8 t18_config[] = {SPT_COMCONFIG_T18, - 0, 0 -}; -static u8 t19_config[] = {SPT_GPIOPWM_T19, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0 -}; -static u8 t20_config[] = {PROCI_GRIPFACESUPPRESSION_T20, - 19, 0, 0, 5, 5, 0, 0, 30, 20, 4, 15, - 10 -}; -static u8 t22_config[] = {PROCG_NOISESUPPRESSION_T22, - 5, 0, 0, 0, 0, 0, 0, 3, 27, 0, - 0, 29, 34, 39, 49, 58, 3 -}; -static u8 t23_config[] = {TOUCH_PROXIMITY_T23, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0 -}; -static u8 t24_config[] = {PROCI_ONETOUCHGESTUREPROCESSOR_T24, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; -static u8 t25_config[] = {SPT_SELFTEST_T25, - 0, 0 -}; -static u8 t27_config[] = {PROCI_TWOTOUCHGESTUREPROCESSOR_T27, - 0, 0, 0, 0, 0, 0, 0 -}; -static u8 t28_config[] = {SPT_CTECONFIG_T28, - 1, 0, 2, 16, 63, 60 -}; -static u8 end_config[] = {RESERVED_T255}; - -static const u8 *mxt224_config[] = { - t7_config, - t8_config, - t9_config, - t15_config, - t18_config, - t19_config, - t20_config, - t22_config, - t23_config, - t24_config, - t25_config, - t27_config, - t28_config, - end_config, -}; - - -static struct mxt224_platform_data mxt224_data = { - .max_finger_touches = 10, - .gpio_read_done = GPIO_TSP_INT, - .config = mxt224_config, - .min_x = 0, - .max_x = 479, - .min_y = 0, - .max_y = 799, - .min_z = 0, - .max_z = 255, - .min_w = 0, - .max_w = 30, - .power_on = mxt224_power_on, - .power_off = mxt224_power_off, -}; - - -#endif -#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 -static void mxt224_power_on(void) -{ - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_LDO_ON, 1); - mdelay(70); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); - mdelay(40); - /* printk("mxt224_power_on is finished\n"); */ -} - -static void mxt224_power_off(void) -{ - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN); - - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_LDO_ON, 0); - /* printk("mxt224_power_off is finished\n"); */ -} - -/* - Configuration for MXT224 -*/ -#define MXT224_THRESHOLD_BATT 40 -#define MXT224_THRESHOLD_BATT_INIT 55 -#define MXT224_THRESHOLD_CHRG 70 -#define MXT224_NOISE_THRESHOLD_BATT 30 -#define MXT224_NOISE_THRESHOLD_CHRG 40 -#define MXT224_MOVFILTER_BATT 47 -#define MXT224_MOVFILTER_CHRG 47 -#define MXT224_ATCHCALST 4 -#define MXT224_ATCHCALTHR 35 - -static u8 t7_config[] = { GEN_POWERCONFIG_T7, - 48, /* IDLEACQINT */ - 255, /* ACTVACQINT */ - 25 /* ACTV2IDLETO: 25 * 200ms = 5s */ -}; - -static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8, - 10, 0, 5, 1, 0, 0, MXT224_ATCHCALST, MXT224_ATCHCALTHR -}; /*byte 3: 0 */ - -static u8 t9_config[] = { TOUCH_MULTITOUCHSCREEN_T9, - 131, 0, 0, 19, 11, 0, 32, MXT224_THRESHOLD_BATT, 2, 1, - 0, - 15, /* MOVHYSTI */ - 1, MXT224_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3, - 223, 1, 0, 0, 0, 0, 143, 55, 143, 90, 18 -}; - -static u8 t18_config[] = { SPT_COMCONFIG_T18, - 0, 1 -}; - -static u8 t20_config[] = { PROCI_GRIPFACESUPPRESSION_T20, - 7, 0, 0, 0, 0, 0, 0, 30, 20, 4, 15, 10 -}; - -static u8 t22_config[] = { PROCG_NOISESUPPRESSION_T22, - 143, 0, 0, 0, 0, 0, 0, 3, MXT224_NOISE_THRESHOLD_BATT, 0, - 0, 29, 34, 39, 49, 58, 3 -}; - -static u8 t28_config[] = { SPT_CTECONFIG_T28, - 0, 0, 3, 16, 19, 60 -}; -static u8 end_config[] = { RESERVED_T255 }; - -static const u8 *mxt224_config[] = { - t7_config, - t8_config, - t9_config, - t18_config, - t20_config, - t22_config, - t28_config, - end_config, -}; - -/* - Configuration for MXT224-E -*/ -#define MXT224E_THRESHOLD_BATT 50 -#define MXT224E_THRESHOLD_CHRG 40 -#define MXT224E_CALCFG_BATT 0x42 -#define MXT224E_CALCFG_CHRG 0x52 -#define MXT224E_ATCHFRCCALTHR_NORMAL 40 -#define MXT224E_ATCHFRCCALRATIO_NORMAL 55 -#define MXT224E_GHRGTIME_BATT 27 -#define MXT224E_GHRGTIME_CHRG 22 -#define MXT224E_ATCHCALST 4 -#define MXT224E_ATCHCALTHR 35 -#define MXT224E_BLEN_BATT 32 -#define MXT224E_BLEN_CHRG 16 -#define MXT224E_MOVFILTER_BATT 46 -#define MXT224E_MOVFILTER_CHRG 46 -#define MXT224E_ACTVSYNCSPERX_NORMAL 32 -#define MXT224E_NEXTTCHDI_NORMAL 0 - -#if defined(CONFIG_TARGET_LOCALE_NAATT) -static u8 t7_config_e[] = { GEN_POWERCONFIG_T7, - 48, 255, 25 -}; - -static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8, - 27, 0, 5, 1, 0, 0, 8, 8, 8, 180 -}; - -/* MXT224E_0V5_CONFIG */ -/* NEXTTCHDI added */ -static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, - 139, 0, 0, 19, 11, 0, 32, 50, 2, 1, - 10, 3, 1, 11, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3, - 223, 1, 10, 10, 10, 10, 143, 40, 143, 80, - 18, 15, 50, 50, 2 -}; - -static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t18_config_e[] = { SPT_COMCONFIG_T18, - 0, 0 -}; - -static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t25_config_e[] = { SPT_SELFTEST_T25, - 0, 0, 188, 52, 124, 21, 188, 52, 124, 21, 0, 0, 0, 0 -}; - -static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40, - 0, 0, 0, 0, 0 -}; - -static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42, - 0, 32, 120, 100, 0, 0, 0, 0 -}; - -static u8 t46_config_e[] = { SPT_CTECONFIG_T46, - 0, 3, 16, 35, 0, 0, 1, 0 -}; - -static u8 t47_config_e[] = { PROCI_STYLUS_T47, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -/*MXT224E_0V5_CONFIG */ -static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 4, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 5, - 0, 0, 0, 0, 0, 0, 32, 50, 2, 3, 1, 11, 10, 5, 40, 10, 10, - 10, 10, 143, 40, 143, 80, 18, 15, 2 -}; - -static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, - 1, 4, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 6, 6, 0, 0, 100, 4, 64, 10, 0, 20, 5, 0, 38, 0, 20, - 0, 0, 0, 0, 0, 0, 16, 70, 2, 5, 2, 46, 10, 5, 40, 10, 0, - 10, 10, 143, 40, 143, 80, 18, 15, 2 -}; - -#else -static u8 t7_config_e[] = { GEN_POWERCONFIG_T7, - 48, /* IDLEACQINT */ - 255, /* ACTVACQINT */ - 25 /* ACTV2IDLETO: 25 * 200ms = 5s */ -}; - -static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8, - MXT224E_GHRGTIME_BATT, 0, 5, 1, 0, 0, - MXT224E_ATCHCALST, MXT224E_ATCHCALTHR, - MXT224E_ATCHFRCCALTHR_NORMAL, - MXT224E_ATCHFRCCALRATIO_NORMAL -}; - -/* MXT224E_0V5_CONFIG */ -/* NEXTTCHDI added */ -#ifdef CONFIG_TARGET_LOCALE_NA -#ifdef CONFIG_MACH_U1_NA_USCC_REV05 -static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, - 139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1, - 10, - 10, /* MOVHYSTI */ - 1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3, - 223, 1, 10, 10, 10, 10, 143, 40, 143, 80, - 18, 15, 50, 50, 0 -}; - -#else -static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, - 139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1, - 10, - 10, /* MOVHYSTI */ - 1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3, - 223, 1, 10, 10, 10, 10, 143, 40, 143, 80, - 18, 15, 50, 50, 2 -}; -#endif -#else -static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, - 139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1, - 10, - 15, /* MOVHYSTI */ - 1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3, - 223, 1, 10, 10, 10, 10, 143, 40, 143, 80, - 18, 15, 50, 50, MXT224E_NEXTTCHDI_NORMAL -}; -#endif - -static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t18_config_e[] = { SPT_COMCONFIG_T18, - 0, 0 -}; - -static u8 t23_config_e[] = { TOUCH_PROXIMITY_T23, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t25_config_e[] = { SPT_SELFTEST_T25, - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -#ifdef CONFIG_MACH_U1_NA_USCC_REV05 -static u8 t38_config_e[] = { SPT_USERDATA_T38, - 0, 1, 13, 19, 44, 0, 0, 0 -}; -#else -static u8 t38_config_e[] = { SPT_USERDATA_T38, - 0, 1, 14, 23, 44, 0, 0, 0 -}; -#endif - -static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40, - 0, 0, 0, 0, 0 -}; - -static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42, - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t46_config_e[] = { SPT_CTECONFIG_T46, - 0, 3, 16, MXT224E_ACTVSYNCSPERX_NORMAL, 0, 0, 1, 0, 0 -}; - -static u8 t47_config_e[] = { PROCI_STYLUS_T47, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -/*MXT224E_0V5_CONFIG */ -#ifdef CONFIG_TARGET_LOCALE_NA -#ifdef CONFIG_MACH_U1_NA_USCC_REV05 -static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15, - 0, 0, 0, 6, 6, 0, 0, 64, 4, 64, - 10, 0, 10, 5, 0, 19, 0, 20, 0, 0, - 0, 0, 0, 0, 0, 40, 2, /*blen=0,threshold=50 */ - 10, /* MOVHYSTI */ - 1, 47, - 10, 5, 40, 240, 245, 10, 10, 148, 50, 143, - 80, 18, 10, 0 -}; - -static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15, - 0, 0, 0, 6, 6, 0, 0, 64, 4, 64, - 10, 0, 20, 5, 0, 38, 0, 5, 0, 0, /*byte 27 original value 20 */ - 0, 0, 0, 0, 32, MXT224E_THRESHOLD, 2, - 10, - 1, 46, - MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143, - 80, 18, 15, 0 -}; -#else -static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, - 1, 4, 0x50, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 6, 6, 0, 0, 100, 4, 64, - 10, 0, 20, 5, 0, 38, 0, 20, 0, 0, - 0, 0, 0, 0, 0, 40, 2, /*blen=0,threshold=50 */ - 10, /* MOVHYSTI */ - 1, 15, - 10, 5, 40, 240, 245, 10, 10, 148, 50, 143, - 80, 18, 10, 2 -}; - -static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, - 1, 4, 0x40, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 6, 6, 0, 0, 100, 4, 64, - 10, 0, 20, 5, 0, 38, 0, 5, 0, 0, /*byte 27 original value 20 */ - 0, 0, 0, 0, 32, 50, 2, - 10, - 1, 46, - MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143, - 80, 18, 15, 2 -}; -#endif /*CONFIG_MACH_U1_NA_USCC_REV05 */ -#else -static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, MXT224E_CALCFG_CHRG, 0, 0, 0, 0, 0, 10, 15, - 0, 0, 0, 6, 6, 0, 0, 64, 4, 64, - 10, 0, 9, 5, 0, 15, 0, 20, 0, 0, - 0, 0, 0, 0, 0, MXT224E_THRESHOLD_CHRG, 2, - 15, /* MOVHYSTI */ - 1, 47, - MXT224_MAX_MT_FINGERS, 5, 40, 235, 235, 10, 10, 160, 50, 143, - 80, 18, 10, 0 -}; - -static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, MXT224E_CALCFG_BATT, 0, 0, 0, 0, 0, 10, 15, - 0, 0, 0, 6, 6, 0, 0, 48, 4, 48, - 10, 0, 10, 5, 0, 20, 0, 5, 0, 0, /*byte 27 original value 20 */ - 0, 0, 0, 0, 32, MXT224E_THRESHOLD_BATT, 2, - 15, - 1, 46, - MXT224_MAX_MT_FINGERS, 5, 40, 10, 10, 10, 10, 143, 40, 143, - 80, 18, 15, 0 -}; -#endif /*CONFIG_TARGET_LOCALE_NA */ -#endif /*CONFIG_TARGET_LOCALE_NAATT */ - -static u8 end_config_e[] = { RESERVED_T255 }; - -static const u8 *mxt224e_config[] = { - t7_config_e, - t8_config_e, - t9_config_e, - t15_config_e, - t18_config_e, - t23_config_e, - t25_config_e, - t38_config_e, - t40_config_e, - t42_config_e, - t46_config_e, - t47_config_e, - t48_config_e, - end_config_e, -}; - -static struct mxt224_platform_data mxt224_data = { - .max_finger_touches = MXT224_MAX_MT_FINGERS, - .gpio_read_done = GPIO_TSP_INT, - .config = mxt224_config, - .config_e = mxt224e_config, - .t48_config_batt_e = t48_config_e, - .t48_config_chrg_e = t48_config_chrg_e, - .min_x = 0, - .max_x = 479, - .min_y = 0, - .max_y = 799, - .min_z = 0, - .max_z = 255, - .min_w = 0, - .max_w = 30, - .atchcalst = MXT224_ATCHCALST, - .atchcalsthr = MXT224_ATCHCALTHR, - .tchthr_batt = MXT224_THRESHOLD_BATT, - .tchthr_batt_init = MXT224_THRESHOLD_BATT_INIT, - .tchthr_charging = MXT224_THRESHOLD_CHRG, - .noisethr_batt = MXT224_NOISE_THRESHOLD_BATT, - .noisethr_charging = MXT224_NOISE_THRESHOLD_CHRG, - .movfilter_batt = MXT224_MOVFILTER_BATT, - .movfilter_charging = MXT224_MOVFILTER_CHRG, - .atchcalst_e = MXT224E_ATCHCALST, - .atchcalsthr_e = MXT224E_ATCHCALTHR, - .tchthr_batt_e = MXT224E_THRESHOLD_BATT, - .tchthr_charging_e = MXT224E_THRESHOLD_CHRG, - .calcfg_batt_e = MXT224E_CALCFG_BATT, - .calcfg_charging_e = MXT224E_CALCFG_CHRG, - .atchfrccalthr_e = MXT224E_ATCHFRCCALTHR_NORMAL, - .atchfrccalratio_e = MXT224E_ATCHFRCCALRATIO_NORMAL, - .chrgtime_batt_e = MXT224E_GHRGTIME_BATT, - .chrgtime_charging_e = MXT224E_GHRGTIME_CHRG, - .blen_batt_e = MXT224E_BLEN_BATT, - .blen_charging_e = MXT224E_BLEN_CHRG, - .movfilter_batt_e = MXT224E_MOVFILTER_BATT, - .movfilter_charging_e = MXT224E_MOVFILTER_CHRG, - .actvsyncsperx_e = MXT224E_ACTVSYNCSPERX_NORMAL, - .nexttchdi_e = MXT224E_NEXTTCHDI_NORMAL, - .power_on = mxt224_power_on, - .power_off = mxt224_power_off, - .register_cb = tsp_register_callback, - .read_ta_status = tsp_read_ta_status, -}; - -#endif /*CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */ - -#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E) -static void mxt540e_power_on(void) -{ - gpio_request(GPIO_TSP_SDA, "TSP_SDA"); - gpio_request(GPIO_TSP_SCL, "TSP_SCL"); - - s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_UP); - s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_UP); - - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_direction_output(GPIO_TSP_LDO_ON, GPIO_LEVEL_HIGH); - msleep(MXT540E_HW_RESET_TIME); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); - - gpio_free(GPIO_TSP_SDA); - gpio_free(GPIO_TSP_SCL); -} - -static void mxt540e_power_off(void) -{ - gpio_request(GPIO_TSP_SDA, "TSP_SDA"); - gpio_request(GPIO_TSP_SCL, "TSP_SCL"); - - s3c_gpio_cfgpin(GPIO_TSP_SDA, S3C_GPIO_OUTPUT); - s3c_gpio_cfgpin(GPIO_TSP_SCL, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_SDA, S3C_GPIO_PULL_NONE); - s3c_gpio_setpull(GPIO_TSP_SCL, S3C_GPIO_PULL_NONE); - gpio_direction_output(GPIO_TSP_SDA, GPIO_LEVEL_LOW); - gpio_direction_output(GPIO_TSP_SCL, GPIO_LEVEL_LOW); - - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN); - gpio_direction_output(GPIO_TSP_INT, GPIO_LEVEL_LOW); - - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_direction_output(GPIO_TSP_LDO_ON, GPIO_LEVEL_LOW); - - gpio_free(GPIO_TSP_SDA); - gpio_free(GPIO_TSP_SCL); -} - -static void mxt540e_power_on_oled(void) -{ - gpio_request(GPIO_OLED_DET, "OLED_DET"); - - mxt540e_power_on(); - - s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_SFN(0xf)); - - gpio_free(GPIO_OLED_DET); - - printk(KERN_INFO "[TSP] %s\n", __func__); -} - -static void mxt540e_power_off_oled(void) -{ - gpio_request(GPIO_OLED_DET, "OLED_DET"); - - s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); - gpio_direction_output(GPIO_OLED_DET, GPIO_LEVEL_LOW); - - mxt540e_power_off(); - - gpio_free(GPIO_OLED_DET); - - printk(KERN_INFO "[TSP] %s\n", __func__); -} - -/* - Configuration for MXT540E -*/ -#define MXT540E_MAX_MT_FINGERS 10 -#define MXT540E_CHRGTIME_BATT 48 -#define MXT540E_CHRGTIME_CHRG 48 -#define MXT540E_THRESHOLD_BATT 50 -#define MXT540E_THRESHOLD_CHRG 40 -#define MXT540E_ACTVSYNCSPERX_BATT 24 -#define MXT540E_ACTVSYNCSPERX_CHRG 28 -#define MXT540E_CALCFG_BATT 98 -#define MXT540E_CALCFG_CHRG 114 -#define MXT540E_ATCHFRCCALTHR_WAKEUP 8 -#define MXT540E_ATCHFRCCALRATIO_WAKEUP 180 -#define MXT540E_ATCHFRCCALTHR_NORMAL 40 -#define MXT540E_ATCHFRCCALRATIO_NORMAL 55 - -static u8 t7_config_e[] = { GEN_POWERCONFIG_T7, - 48, 255, 50 -}; - -static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8, - MXT540E_CHRGTIME_BATT, 0, 5, 1, 0, 0, 4, 20, - MXT540E_ATCHFRCCALTHR_WAKEUP, MXT540E_ATCHFRCCALRATIO_WAKEUP -}; - -static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, - 131, 0, 0, 16, 26, 0, 192, MXT540E_THRESHOLD_BATT, 2, 6, - 10, 10, 10, 80, MXT540E_MAX_MT_FINGERS, 20, 40, 20, 31, 3, - 255, 4, 3, 3, 2, 2, 136, 60, 136, 40, - 18, 15, 0, 0, 0 -}; - -static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t18_config_e[] = { SPT_COMCONFIG_T18, - 0, 0 -}; - -static u8 t19_config_e[] = { SPT_GPIOPWM_T19, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t24_config_e[] = { PROCI_ONETOUCHGESTUREPROCESSOR_T24, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t25_config_e[] = { SPT_SELFTEST_T25, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t27_config_e[] = { PROCI_TWOTOUCHGESTUREPROCESSOR_T27, - 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40, - 0, 0, 0, 0, 0 -}; - -static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42, - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t43_config_e[] = { SPT_DIGITIZER_T43, - 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t46_config_e[] = { SPT_CTECONFIG_T46, - 0, 0, 16, MXT540E_ACTVSYNCSPERX_BATT, 0, 0, 1, 0 -}; - -static u8 t47_config_e[] = { PROCI_STYLUS_T47, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, MXT540E_CALCFG_BATT, 0, 0, 0, 0, 0, 1, 2, - 0, 0, 0, 6, 6, 0, 0, 28, 4, 64, - 10, 0, 20, 6, 0, 30, 0, 0, 0, 0, - 0, 0, 0, 0, 192, MXT540E_THRESHOLD_BATT, 2, 10, 10, 47, - MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136, - 0, 18, 5, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0 -}; - -static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, MXT540E_CALCFG_CHRG, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 6, 6, 0, 0, 36, 4, 64, - 10, 0, 10, 6, 0, 20, 0, 0, 0, 0, - 0, 0, 0, 0, 112, MXT540E_THRESHOLD_CHRG, 2, 10, 5, 47, - MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136, - 0, 18, 10, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0 -}; - -static u8 t52_config_e[] = { TOUCH_PROXKEY_T52, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t55_config_e[] = {ADAPTIVE_T55, - 0, 0, 0, 0, 0, 0 -}; - -static u8 t57_config_e[] = {SPT_GENERICDATA_T57, - 243, 25, 1 -}; - -static u8 t61_config_e[] = {SPT_TIMER_T61, - 0, 0, 0, 0, 0 -}; - -static u8 end_config_e[] = { RESERVED_T255 }; - -static const u8 *mxt540e_config[] = { - t7_config_e, - t8_config_e, - t9_config_e, - t15_config_e, - t18_config_e, - t19_config_e, - t24_config_e, - t25_config_e, - t27_config_e, - t40_config_e, - t42_config_e, - t43_config_e, - t46_config_e, - t47_config_e, - t48_config_e, - t52_config_e, - t55_config_e, - t57_config_e, - t61_config_e, - end_config_e, -}; - -struct mxt540e_platform_data mxt540e_data = { - .max_finger_touches = MXT540E_MAX_MT_FINGERS, - .gpio_read_done = GPIO_TSP_INT, - .config_e = mxt540e_config, - .min_x = 0, - .max_x = 799, - .min_y = 0, - .max_y = 1279, - .min_z = 0, - .max_z = 255, - .min_w = 0, - .max_w = 30, - .chrgtime_batt = MXT540E_CHRGTIME_BATT, - .chrgtime_charging = MXT540E_CHRGTIME_CHRG, - .tchthr_batt = MXT540E_THRESHOLD_BATT, - .tchthr_charging = MXT540E_THRESHOLD_CHRG, - .actvsyncsperx_batt = MXT540E_ACTVSYNCSPERX_BATT, - .actvsyncsperx_charging = MXT540E_ACTVSYNCSPERX_CHRG, - .calcfg_batt_e = MXT540E_CALCFG_BATT, - .calcfg_charging_e = MXT540E_CALCFG_CHRG, - .atchfrccalthr_e = MXT540E_ATCHFRCCALTHR_NORMAL, - .atchfrccalratio_e = MXT540E_ATCHFRCCALRATIO_NORMAL, - .t48_config_batt_e = t48_config_e, - .t48_config_chrg_e = t48_config_chrg_e, - .power_on = mxt540e_power_on, - .power_off = mxt540e_power_off, - .power_on_with_oleddet = mxt540e_power_on_oled, - .power_off_with_oleddet = mxt540e_power_off_oled, - .register_cb = tsp_register_callback, - .read_ta_status = tsp_read_ta_status, -}; -#endif - -#ifdef CONFIG_EPEN_WACOM_G5SP -static int p6_wacom_init_hw(void); -static int p6_wacom_exit_hw(void); -static int p6_wacom_suspend_hw(void); -static int p6_wacom_resume_hw(void); -static int p6_wacom_early_suspend_hw(void); -static int p6_wacom_late_resume_hw(void); -static int p6_wacom_reset_hw(void); -static void p6_wacom_register_callbacks(struct wacom_g5_callbacks *cb); - -static struct wacom_g5_platform_data p6_wacom_platform_data = { - .x_invert = 1, - .y_invert = 0, - .xy_switch = 1, - .min_x = 0, - .max_x = WACOM_POSX_MAX, - .min_y = 0, - .max_y = WACOM_POSY_MAX, - .min_pressure = 0, - .max_pressure = WACOM_PRESSURE_MAX, - .init_platform_hw = p6_wacom_init_hw, -/* .exit_platform_hw =, */ - .suspend_platform_hw = p6_wacom_suspend_hw, - .resume_platform_hw = p6_wacom_resume_hw, - .early_suspend_platform_hw = p6_wacom_early_suspend_hw, - .late_resume_platform_hw = p6_wacom_late_resume_hw, - .reset_platform_hw = p6_wacom_reset_hw, - .register_cb = p6_wacom_register_callbacks, -}; - -#endif - -#ifdef CONFIG_EPEN_WACOM_G5SP -static int p6_wacom_suspend_hw(void) -{ - return p6_wacom_early_suspend_hw(); -} - -static int p6_wacom_resume_hw(void) -{ - return p6_wacom_late_resume_hw(); -} - -static int p6_wacom_early_suspend_hw(void) -{ - gpio_set_value(GPIO_PEN_RESET, 0); - return 0; -} - -static int p6_wacom_late_resume_hw(void) -{ - gpio_set_value(GPIO_PEN_RESET, 1); - return 0; -} - -static int p6_wacom_reset_hw(void) -{ - gpio_set_value(GPIO_PEN_RESET, 0); - msleep(200); - gpio_set_value(GPIO_PEN_RESET, 1); - return 0; -} - -static void p6_wacom_register_callbacks(struct wacom_g5_callbacks *cb) -{ - wacom_callbacks = cb; -}; - -#endif /* CONFIG_EPEN_WACOM_G5SP */ - #ifdef CONFIG_I2C_S3C2410 /* I2C0 */ static struct i2c_board_info i2c_devs0[] __initdata = { @@ -5201,15 +4318,66 @@ static struct i2c_board_info i2c_devs0[] __initdata = { {I2C_BOARD_INFO("24c128", 0x52),}, /* Samsung S524AD0XD1 */ }; +static struct k3g_platform_data trats_k3g_data = { + .irq2 = IRQ_EINT(1), + .powerdown = K3G_POWERDOWN_NORMAL, + .zen = K3G_Z_EN, + .yen = K3G_Y_EN, + .xen = K3G_X_EN, + .block_data_update = K3G_BLOCK_DATA_UPDATE, + .fullscale = K3G_FULL_SCALE_500DPS, + .fifo_mode = K3G_FIFO_FIFO_MODE, + .int2_src = K3G_INT2_OVERRUN, + .fifo_threshold = 16, + .int1_z_high_enable = K3G_Z_HIGH_INT_EN, + .int1_y_high_enable = K3G_Y_HIGH_INT_EN, + .int1_x_high_enable = K3G_X_HIGH_INT_EN, + .int1_latch = K3G_INTERRUPT_LATCHED, + .int1_z_threshold = 0x12, + .int1_y_threshold = 0x25, + .int1_x_threshold = 0x25, + .int1_wait_enable = K3G_INT1_WAIT_EN, + .int1_wait_duration = 0x10, +}; + +static struct kr3dh_platform_data trats_kr3dh_data = { + .power_mode = KR3DH_LOW_POWER_ONE_HALF_HZ, + .data_rate = KR3DH_ODR_50HZ, + .zen = 1, + .yen = 1, + .xen = 1, + .int1_latch = 1, + .int1_cfg = KR3DH_INT_SOURCE, + .block_data_update = 1, + .fullscale = KR3DH_RANGE_2G, + .int1_combination = KR3DH_OR_COMBINATION, + .int1_6d_enable = 1, + .int1_z_high_enable = 1, + .int1_z_low_enable = 1, + .int1_y_high_enable = 1, + .int1_y_low_enable = 1, + .int1_x_high_enable = 1, + .int1_x_low_enable = 1, + .int1_threshold = 0x25, + .int1_duration = 0x01, + .negate_x = 0, + .negate_y = 0, + .negate_z = 1, + .change_xy = 1, +}; + #ifdef CONFIG_S3C_DEV_I2C1 /* I2C1 */ static struct i2c_board_info i2c_devs1[] __initdata = { { - I2C_BOARD_INFO("k3g", 0x69), - .irq = IRQ_EINT(1), - }, - { - I2C_BOARD_INFO("k3dh", 0x19), + I2C_BOARD_INFO("K3G_1", 0x69), + .platform_data = &trats_k3g_data, + .irq = IRQ_EINT(0), + }, { + /* Accelerometer */ + I2C_BOARD_INFO("KR3DH", 0x19), + .platform_data = &trats_kr3dh_data, + .irq = IRQ_EINT(24), }, #ifdef CONFIG_MACH_Q1_BD { @@ -5226,22 +4394,10 @@ static struct i2c_board_info i2c_devs2[] __initdata = { #ifdef CONFIG_S3C_DEV_I2C3 /* I2C3 */ static struct i2c_board_info i2c_devs3[] __initdata = { -#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 - { - I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a), - .platform_data = &mxt224_data, - }, -#endif -#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT540E - { - I2C_BOARD_INFO(MXT540E_DEV_NAME, 0x4c), - .platform_data = &mxt540e_data, - }, -#endif -#ifdef CONFIG_TOUCHSCREEN_ATMEL_MXT224_GC +#ifdef CONFIG_TOUCHSCREEN_MELFAS_MMS { - I2C_BOARD_INFO(MXT224_DEV_NAME, 0x4a), - .platform_data = &mxt224_data, + I2C_BOARD_INFO(MELFAS_TS_NAME, MELFAS_DEV_ADDR), + .platform_data = &melfas_mms_ts_pdata_rotate, }, #endif }; @@ -5272,18 +4428,12 @@ static struct i2c_board_info i2c_devs5[] __initdata = { #ifdef CONFIG_S3C_DEV_I2C6 /* I2C6 */ static struct i2c_board_info i2c_devs6[] __initdata = { -#ifdef CONFIG_SND_SOC_U1_MC1N2 +#if defined(CONFIG_SND_SOC_SLP_TRATS_MC1N2) { I2C_BOARD_INFO("mc1n2", 0x3a), /* MC1N2 */ .platform_data = &mc1n2_pdata, }, #endif -#ifdef CONFIG_EPEN_WACOM_G5SP - { - I2C_BOARD_INFO("wacom_g5sp_i2c", 0x56), - .platform_data = &p6_wacom_platform_data, - }, -#endif }; #endif #ifdef CONFIG_S3C_DEV_I2C7 @@ -5297,30 +4447,29 @@ static struct i2c_board_info i2c_devs7[] __initdata = { I2C_BOARD_INFO("ak8975", 0x0C), .platform_data = &akm8975_pdata, }, -#ifdef CONFIG_VIDEO_TVOUT +#ifdef CONFIG_DRM_EXYNOS_HDMI { I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)), }, #endif }; -#endif -#ifdef CONFIG_S3C_DEV_I2C8_EMUL -static struct i2c_gpio_platform_data gpio_i2c_data8 = { - .sda_pin = GPIO_3_TOUCH_SDA, - .scl_pin = GPIO_3_TOUCH_SCL, -}; -struct platform_device s3c_device_i2c8 = { - .name = "i2c-gpio", - .id = 8, - .dev.platform_data = &gpio_i2c_data8, -}; +static void s3c_i2c7_cfg_gpio_u1(struct platform_device *dev) +{ + /* u1 magnetic sensor & MHL are using i2c7 + * and the i2c line has external pull-resistors. + */ + s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE); +} -/* I2C8 */ -static struct i2c_board_info i2c_devs8_emul[] = { - { - I2C_BOARD_INFO("sec_touchkey", 0x20), - }, +static struct s3c2410_platform_i2c default_i2c7_data __initdata = { + .bus_num = 7, + .flags = 0, + .slave_addr = 0x10, + .frequency = 100*1000, + .sda_delay = 100, + .cfg_gpio = s3c_i2c7_cfg_gpio_u1, }; #endif @@ -5464,6 +4613,36 @@ static struct i2c_board_info i2c_devs10_emul[] __initdata = { }; #endif +static struct regulator_consumer_supply supplies_ps_on_led_a[] = { + REGULATOR_SUPPLY("led_a_2.8v", NULL), +}; +static struct regulator_init_data ps_on_led_a_data = { + .constraints = { + .name = "LED_A_2.8V", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 0, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(supplies_ps_on_led_a), + .consumer_supplies = supplies_ps_on_led_a, +}; +static struct fixed_voltage_config ps_on_led_a_pdata = { + .supply_name = "LED_A_2.8V", + .microvolts = 2800000, + .gpio = EXYNOS4210_GPE2(3), /* PS_ON */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &ps_on_led_a_data, +}; +static struct platform_device ps_on_led_a_fixed_reg_dev = { + .name = "reg-fixed-voltage", + .id = FIXED_REG_ID_LED_A, + .dev = { .platform_data = &ps_on_led_a_pdata }, +}; + #ifdef CONFIG_S3C_DEV_I2C11_EMUL static struct i2c_gpio_platform_data gpio_i2c_data11 = { .sda_pin = GPIO_PS_ALS_SDA, @@ -5477,88 +4656,64 @@ struct platform_device s3c_device_i2c11 = { }; /* I2C11 */ -#ifdef CONFIG_SENSORS_CM3663 -static int cm3663_ldo(bool on) +static int gp2a_leda_on(bool enable) { struct regulator *regulator; + DEFINE_MUTEX(lock); + int ret = 0; - if (on) { - regulator = regulator_get(NULL, "vled"); - if (IS_ERR(regulator)) - return 0; - regulator_enable(regulator); - regulator_put(regulator); - } else { - regulator = regulator_get(NULL, "vled"); - if (IS_ERR(regulator)) - return 0; - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - regulator_put(regulator); + pr_info("%s, enable = %d\n", __func__, enable); + mutex_lock(&lock); + + regulator = regulator_get(NULL, "led_a_2.8v"); + WARN(IS_ERR_OR_NULL(regulator), "%s cannot get regulator\n", __func__); + if (IS_ERR_OR_NULL(regulator)) { + regulator = NULL; + ret = -ENODEV; + goto leda_out; } - return 0; + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + + if (enable) + regulator_enable(regulator); + +leda_out: + if (regulator) + regulator_put(regulator); + mutex_unlock(&lock); + return ret; } -static struct cm3663_platform_data cm3663_pdata = { - .proximity_power = cm3663_ldo, -}; -#ifdef CONFIG_SENSORS_PAS2M110 -static struct pas2m110_platform_data pas2m110_pdata = { - .proximity_power = cm3663_ldo, -}; -#endif -#endif -#ifdef CONFIG_SENSORS_GP2A_ANALOG -static int gp2a_power(bool on) +static int gp2a_get_threshold(void) { - struct regulator *regulator; + int new_threshold = 7; /* LTH value */ - if (on) { - regulator = regulator_get(NULL, "vled"); - if (IS_ERR(regulator)) - return 0; - regulator_enable(regulator); - regulator_put(regulator); - } else { - regulator = regulator_get(NULL, "vled"); - if (IS_ERR(regulator)) - return 0; - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - regulator_put(regulator); - } + if (system_rev == 2) /* U1HD Linchbox board is not calibrated */ + new_threshold = 100; - return 0; + return new_threshold; } -static struct gp2a_platform_data gp2a_pdata = { +static struct gp2a_platform_data trats_gp2a_pdata = { + .gp2a_led_on = gp2a_leda_on, .p_out = GPIO_PS_ALS_INT, - .power = gp2a_power, + .gp2a_get_threshold = gp2a_get_threshold, }; -#endif -static struct i2c_board_info i2c_devs11_emul[] __initdata = { -#ifdef CONFIG_MACH_U1_BD - { - I2C_BOARD_INFO("cm3663", 0x20), - .irq = GPIO_PS_ALS_INT, - .platform_data = &cm3663_pdata, - }, -#ifdef CONFIG_SENSORS_PAS2M110 - { - I2C_BOARD_INFO("pas2m110", (0x88>>1)), - .irq = GPIO_PS_ALS_INT, - .platform_data = &pas2m110_pdata, +static struct platform_device opt_gp2a = { + .name = "gp2a-opt", + .id = -1, + .dev = { + .platform_data = &trats_gp2a_pdata, }, -#endif -#endif -#ifdef CONFIG_MACH_Q1_BD +}; + +static struct i2c_board_info i2c_devs11_emul[] __initdata = { { - I2C_BOARD_INFO("gp2a", (0x88 >> 1)), - .platform_data = &gp2a_pdata, + I2C_BOARD_INFO("gp2a", (0x72 >> 1)), }, -#endif }; #endif @@ -5666,19 +4821,6 @@ static struct i2c_board_info i2c_devs16[] __initdata = { #endif -#ifdef CONFIG_TOUCHSCREEN_S3C2410 -static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, - .cal_x_max = 480, - .cal_y_max = 800, - .cal_param = { - 33, -9156, 34720100, 14819, 57, -4234968, 65536, - }, -}; -#endif - #ifdef CONFIG_ISDBT_FC8100 static struct i2c_board_info i2c_devs17[] __initdata = { { @@ -5702,221 +4844,6 @@ static struct platform_device s3c_device_i2c17 = { }; #endif - -#ifdef CONFIG_FB_S5P_MIPI_DSIM -#ifdef CONFIG_FB_S5P_S6E8AA0 -/* for Geminus based on MIPI-DSI interface */ -static struct s3cfb_lcd s6e8aa0 = { - .name = "s6e8aa0", - .width = 800, - .height = 1280, - .p_width = 64, - .p_height = 106, - .bpp = 24, - - .freq = 57, - - /* minumun value is 0 except for wr_act time. */ - .cpu_timing = { - .cs_setup = 0, - .wr_setup = 0, - .wr_act = 1, - .wr_hold = 0, - }, - - .timing = { - .h_fp = 10, - .h_bp = 10, - .h_sw = 10, - .v_fp = 13, - .v_fpe = 1, - .v_bp = 1, - .v_bpe = 1, - .v_sw = 2, - .cmd_allow_len = 11, /*v_fp=stable_vfp + cmd_allow_len */ - .stable_vfp = 2, - }, - - .polarity = { - .rise_vclk = 1, - .inv_hsync = 0, - .inv_vsync = 0, - .inv_vden = 0, - }, -}; -#endif -static struct s3c_platform_fb fb_platform_data __initdata = { - .hw_ver = 0x70, - .clk_name = "fimd", - .nr_wins = 5, -#ifdef CONFIG_FB_S5P_DEFAULT_WINDOW - .default_win = CONFIG_FB_S5P_DEFAULT_WINDOW, -#else - .default_win = 0, -#endif - .swap = FB_SWAP_HWORD | FB_SWAP_WORD, -#ifdef CONFIG_FB_S5P_S6E8AA0 - .lcd = &s6e8aa0 -#endif -}; - -#ifdef CONFIG_FB_S5P_S6E8AA0 -static int reset_lcd(void) -{ - int err; - - /* Set GPY4[5] OUTPUT HIGH */ - err = gpio_request(EXYNOS4_GPY4(5), "MLCD_RST"); - if (err) { - printk(KERN_ERR "failed to request GPY4(5) for " - "lcd reset control\n"); - return -EPERM; - } - - gpio_direction_output(EXYNOS4_GPY4(5), 1); - msleep(5); - gpio_set_value(EXYNOS4_GPY4(5), 0); - msleep(5); - gpio_set_value(EXYNOS4_GPY4(5), 1); - msleep(5); - - gpio_free(EXYNOS4_GPY4(5)); - - return 0; -} -#endif -static void lcd_cfg_gpio(void) -{ - /* MLCD_RST */ - s3c_gpio_cfgpin(EXYNOS4_GPY4(5), S3C_GPIO_OUTPUT); - s3c_gpio_setpull(EXYNOS4_GPY4(5), S3C_GPIO_PULL_NONE); - - /* LCD_EN */ - s3c_gpio_cfgpin(GPIO_LCD_EN, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_LCD_EN, S3C_GPIO_PULL_NONE); - - return; -} - -static int lcd_power_on(void *ld, int enable) -{ - struct regulator *regulator; - int err; - - printk(KERN_INFO "%s : enable=%d\n", __func__, enable); - - if (ld == NULL) { - printk(KERN_ERR "lcd device object is NULL.\n"); - return -EPERM; - } - - err = gpio_request(EXYNOS4_GPY4(5), "MLCD_RST"); - if (err) { - printk(KERN_ERR "failed to request GPY4[5] for " - "MLCD_RST control\n"); - return -EPERM; - } - - err = gpio_request(GPIO_LCD_EN, "LCD_EN"); - if (err) { - printk(KERN_ERR "failed to request GPY3[1] for " - "LCD_EN control\n"); - return -EPERM; - } - - if (enable) { -#ifdef CONFIG_MACH_Q1_BD - if (system_rev < 8) { - regulator = regulator_get(NULL, "vlcd_2.2v"); - if (IS_ERR(regulator)) - return 0; - regulator_enable(regulator); - regulator_put(regulator); - } else - gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_HIGH); -#endif - regulator = regulator_get(NULL, "vlcd_3.0v"); - if (IS_ERR(regulator)) - return 0; - regulator_enable(regulator); - regulator_put(regulator); - } else { - regulator = regulator_get(NULL, "vlcd_3.0v"); - if (IS_ERR(regulator)) - return 0; - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - regulator_put(regulator); -#ifdef CONFIG_MACH_Q1_BD - if (system_rev < 8) { - regulator = regulator_get(NULL, "vlcd_2.2v"); - if (IS_ERR(regulator)) - return 0; - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - regulator_put(regulator); - } else - gpio_set_value(GPIO_LCD_EN, GPIO_LEVEL_LOW); -#endif - - gpio_set_value(EXYNOS4_GPY4(5), 0); - } - - /* Release GPIO */ - gpio_free(EXYNOS4_GPY4(5)); - gpio_free(GPIO_LCD_EN); - - return 0; -} - -static void __init mipi_fb_init(void) -{ - struct s5p_platform_dsim *dsim_pd = NULL; - struct mipi_ddi_platform_data *mipi_ddi_pd = NULL; - struct dsim_lcd_config *dsim_lcd_info = NULL; - - /* set platform data */ - - /* gpio pad configuration for rgb and spi interface. */ - lcd_cfg_gpio(); - - /* - * register lcd panel data. - */ - printk(KERN_INFO "%s :: fb_platform_data.hw_ver = 0x%x\n", - __func__, fb_platform_data.hw_ver); - - dsim_pd = (struct s5p_platform_dsim *) - s5p_device_dsim.dev.platform_data; - - dsim_pd->platform_rev = 1; - - dsim_lcd_info = dsim_pd->dsim_lcd_info; - -#ifdef CONFIG_FB_S5P_S6E8AA0 - dsim_lcd_info->lcd_panel_info = (void *)&s6e8aa0; - - /* 483Mbps for Q1 */ - dsim_pd->dsim_info->p = 4; - dsim_pd->dsim_info->m = 161; - dsim_pd->dsim_info->s = 1; -#endif - - mipi_ddi_pd = (struct mipi_ddi_platform_data *) - dsim_lcd_info->mipi_ddi_pd; - mipi_ddi_pd->lcd_reset = reset_lcd; - mipi_ddi_pd->lcd_power_on = lcd_power_on; - - platform_device_register(&s5p_device_dsim); - - s3cfb_set_platdata(&fb_platform_data); - - printk(KERN_INFO - "platform data of %s lcd panel has been registered.\n", - dsim_pd->lcd_panel_name); -} -#endif - #ifdef CONFIG_ANDROID_PMEM static struct android_pmem_platform_data pmem_pdata = { .name = "pmem", @@ -5991,25 +4918,10 @@ static void __init smdkc210_ohci_init(void) #ifdef CONFIG_USB_GADGET static struct s5p_usbgadget_platdata smdkc210_usbgadget_pdata; -#include <linux/usb/android_composite.h> static void __init smdkc210_usbgadget_init(void) { struct s5p_usbgadget_platdata *pdata = &smdkc210_usbgadget_pdata; -#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID) - struct android_usb_platform_data *android_pdata = - s3c_device_android_usb.dev.platform_data; - if (android_pdata) { - unsigned int newluns = 2; - printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n", - __func__, android_pdata->nluns, newluns); - android_pdata->nluns = newluns; - } else { - printk(KERN_DEBUG "usb: %s android_pdata is not available\n", - __func__); - } -#endif - s5p_usbgadget_set_platdata(pdata); pdata = s3c_device_usbgadget.dev.platform_data; @@ -6050,6 +4962,42 @@ static void __init smdkc210_usbgadget_init(void) } #endif +#ifdef CONFIG_USB_G_SLP +#include <linux/usb/slp_multi.h> +static struct slp_multi_func_data midas_slp_multi_funcs[] = { + { + .name = "mtp", + .usb_config_id = USB_CONFIGURATION_DUAL, + }, { + .name = "acm", + .usb_config_id = USB_CONFIGURATION_2, + }, { + .name = "sdb", + .usb_config_id = USB_CONFIGURATION_2, + }, { + .name = "mass_storage", + .usb_config_id = USB_CONFIGURATION_1, + }, { + .name = "rndis", + .usb_config_id = USB_CONFIGURATION_1, + }, +}; + +static struct slp_multi_platform_data midas_slp_multi_pdata = { + .nluns = 2, + .funcs = midas_slp_multi_funcs, + .nfuncs = ARRAY_SIZE(midas_slp_multi_funcs), +}; + +static struct platform_device midas_slp_usb_multi = { + .name = "slp_multi", + .id = -1, + .dev = { + .platform_data = &midas_slp_multi_pdata, + }, +}; +#endif + #ifdef CONFIG_BUSFREQ_OPP /* BUSFREQ to control memory/bus*/ static struct device_domain busfreq; @@ -6082,10 +5030,23 @@ static struct platform_device *smdkc210_devices[] __initdata = { #ifdef CONFIG_BATTERY_SAMSUNG &samsung_device_battery, #endif -#ifdef CONFIG_FB_S5P - &s3c_device_fb, -#endif +#ifdef CONFIG_DRM_EXYNOS_FIMD + &s5p_device_fimd0, +#endif +#ifdef CONFIG_DRM_EXYNOS_HDMI + &s5p_device_i2c_hdmiphy, + &s5p_device_hdmi, + &s5p_device_mixer, + &exynos_drm_hdmi_device, +#endif + &exynos_drm_vidi_device, +#ifdef CONFIG_DRM_EXYNOS_G2D + &s5p_device_fimg2d, +#endif +#ifdef CONFIG_DRM_EXYNOS + &exynos_drm_device, +#endif #ifdef CONFIG_I2C_S3C2410 &s3c_device_i2c0, #if defined(CONFIG_S3C_DEV_I2C1) @@ -6109,9 +5070,6 @@ static struct platform_device *smdkc210_devices[] __initdata = { #if defined(CONFIG_S3C_DEV_I2C7) &s3c_device_i2c7, #endif -#if defined(CONFIG_S3C_DEV_I2C8_EMUL) - &s3c_device_i2c8, -#endif #if defined(CONFIG_S3C_DEV_I2C9_EMUL) &s3c_device_i2c9, #endif @@ -6128,7 +5086,10 @@ static struct platform_device *smdkc210_devices[] __initdata = { &s3c_device_i2c12, #endif #ifdef CONFIG_SAMSUNG_MHL - &s3c_device_i2c15, + &s3c_device_i2c15, +#endif +#ifdef CONFIG_JACK_MON + &trats_jack, #endif #ifdef CONFIG_FM_SI4709_MODULE &s3c_device_i2c16, @@ -6164,12 +5125,8 @@ static struct platform_device *smdkc210_devices[] __initdata = { #ifdef CONFIG_S3C_ADC &s3c_device_adc, #endif -#ifdef CONFIG_TOUCHSCREEN_S3C2410 -#ifdef CONFIG_S3C_DEV_ADC - &s3c_device_ts, -#elif CONFIG_S3C_DEV_ADC1 - &s3c_device_ts1, -#endif +#ifdef CONFIG_UART_SELECT + &trats_uart_select, #endif &u1_keypad, &s3c_device_rtc, @@ -6199,11 +5156,16 @@ static struct platform_device *smdkc210_devices[] __initdata = { &max8922_device_charger, #endif #ifdef CONFIG_S5P_SYSTEM_MMU +#ifdef CONFIG_DRM_EXYNOS_FIMD + &SYSMMU_PLATDEV(fimd0), +#endif +#ifdef CONFIG_DRM_EXYNOS_G2D + &SYSMMU_PLATDEV(g2d_acp), +#endif &SYSMMU_PLATDEV(fimc0), &SYSMMU_PLATDEV(fimc1), &SYSMMU_PLATDEV(fimc2), &SYSMMU_PLATDEV(fimc3), - &SYSMMU_PLATDEV(2d), &SYSMMU_PLATDEV(tv), &SYSMMU_PLATDEV(mfc_l), &SYSMMU_PLATDEV(mfc_r), @@ -6221,35 +5183,10 @@ static struct platform_device *smdkc210_devices[] __initdata = { &exynos_device_spi0, #endif -/* mainline fimd */ -#ifdef CONFIG_FB_S3C - &s5p_device_fimd0, -#if defined(CONFIG_LCD_AMS369FG06) - &s3c_device_spi_gpio, -#elif defined(CONFIG_LCD_WA101S) - &smdkc210_lcd_wa101s, -#elif defined(CONFIG_LCD_LTE480WV) - &smdkc210_lcd_lte480wv, -#endif -#endif -/* legacy fimd */ -#ifdef CONFIG_FB_S5P_AMS369FG06 - &s3c_device_spi_gpio, -#endif -#ifdef CONFIG_FB_S5P_LD9040 - &ld9040_spi_gpio, -#endif -#ifdef CONFIG_FB_S5P_NT35560 - &nt35560_spi_gpio, -#endif -#ifdef CONFIG_FB_S5P_MDNIE - &mdnie_device, -#endif -#ifdef CONFIG_VIDEO_TVOUT - &s5p_device_tvout, - &s5p_device_cec, - &s5p_device_hpd, +#ifdef CONFIG_PHONE_IPC_SPI + &ipc_spi_device, #endif + #ifdef CONFIG_ANDROID_PMEM &pmem_device, &pmem_gpu1_device, @@ -6267,9 +5204,6 @@ static struct platform_device *smdkc210_devices[] __initdata = { #if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) &s5p_device_mfc, #endif -#ifdef CONFIG_VIDEO_FIMG2D - &s5p_device_fimg2d, -#endif #ifdef CONFIG_VIDEO_JPEG &s5p_device_jpeg, #endif @@ -6282,12 +5216,8 @@ static struct platform_device *smdkc210_devices[] __initdata = { #ifdef CONFIG_USB_GADGET &s3c_device_usbgadget, #endif -#ifdef CONFIG_USB_ANDROID_RNDIS - &s3c_device_rndis, -#endif -#if defined(CONFIG_USB_ANDROID) || defined(CONFIG_USB_G_ANDROID) - &s3c_device_android_usb, - &s3c_device_usb_mass_storage, +#ifdef CONFIG_USB_G_SLP + &midas_slp_usb_multi, #endif #ifdef CONFIG_HAVE_PWM &s3c_device_timer[0], @@ -6317,6 +5247,11 @@ static struct platform_device *smdkc210_devices[] __initdata = { &host_notifier_device, #endif &s3c_device_usb_otghcd, +#ifdef CONFIG_GPS_GSD4T + &u1_gsd4t, +#endif + &ps_on_led_a_fixed_reg_dev, + &opt_gp2a, }; #ifdef CONFIG_EXYNOS4_SETUP_THERMAL @@ -6347,16 +5282,6 @@ static int __init s5p_ehci_device_initcall(void) late_initcall(s5p_ehci_device_initcall); #endif -#if defined(CONFIG_VIDEO_TVOUT) -static struct s5p_platform_hpd hdmi_hpd_data __initdata = { - -}; - -static struct s5p_platform_cec hdmi_cec_data __initdata = { - -}; -#endif - #if defined(CONFIG_S5P_MEM_CMA) static void __init exynos4_cma_region_reserve(struct cma_region *regions_normal, struct cma_region *regions_secure) @@ -6378,7 +5303,7 @@ static void __init exynos4_cma_region_reserve(struct cma_region *regions_normal, reg->reserved = 1; } else { paddr = __memblock_alloc_base(reg->size, reg->alignment, - MEMBLOCK_ALLOC_ACCESSIBLE); + MEMBLOCK_ALLOC_ACCESSIBLE); if (paddr) { reg->start = paddr; reg->reserved = 1; @@ -6414,6 +5339,17 @@ static void __init exynos4_cma_region_reserve(struct cma_region *regions_normal, static void __init exynos4_reserve_mem(void) { static struct cma_region regions[] = { + /* + * caution : do not allowed other region definitions above of drm. + * drm only using region 0 for startup screen display. + */ +#ifdef CONFIG_DRM_EXYNOS + { + .name = "drm", + .size = CONFIG_DRM_EXYNOS_MEMSIZE * SZ_1K, + .start = 0 + }, +#endif #ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM { .name = "pmem", @@ -6428,13 +5364,6 @@ static void __init exynos4_reserve_mem(void) .start = 0, }, #endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD - { - .name = "fimd", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K, - .start = 0, - }, -#endif #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC0 { .name = "fimc0", @@ -6442,6 +5371,7 @@ static void __init exynos4_reserve_mem(void) .start = 0, }, #endif +#ifndef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 { .name = "fimc1", @@ -6449,6 +5379,7 @@ static void __init exynos4_reserve_mem(void) .start = 0, }, #endif +#endif #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC2 { .name = "fimc2", @@ -6463,6 +5394,12 @@ static void __init exynos4_reserve_mem(void) .start = 0, }, #endif +#ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE + { + .name = "ion", + .size = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K, + }, +#endif #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 { .name = "mfc1", @@ -6507,30 +5444,21 @@ static void __init exynos4_reserve_mem(void) .start = 0, }, #endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D - { - .name = "fimg2d", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMG2D * SZ_1K, - .start = 0, - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT - { - .name = "tvout", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TVOUT * SZ_1K, - .start = 0, - }, -#endif { .size = 0, }, }; static const char map[] __initconst = +#ifdef CONFIG_DRM_EXYNOS + "exynos-drm=drm;" +#endif "android_pmem.0=pmem;android_pmem.1=pmem_gpu1;" - "s3cfb.0=fimd;exynos4-fb.0=fimd;" - "s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;" + "s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;s3c-fimc.3=fimc3;" "exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc3=fimc3;" +#ifdef CONFIG_ION_EXYNOS + "ion-exynos=ion;" +#endif #ifdef CONFIG_VIDEO_MFC5X "s3c-mfc/A=mfc0,mfc-secure;" "s3c-mfc/B=mfc1,mfc-normal;" @@ -6541,8 +5469,7 @@ static void __init exynos4_reserve_mem(void) #ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS "exynos4-fimc-is=fimc_is;" #endif - "s5p-fimg2d=fimg2d;" - "s5p-tvout=tvout"; + ; cma_set_defaults(regions, map); exynos4_cma_region_reserve(regions, NULL); @@ -6558,7 +5485,6 @@ static void __init exynos_sysmmu_init(void) ASSIGN_SYSMMU_POWERDOMAIN(fimc3, &exynos4_device_pd[PD_CAM].dev); ASSIGN_SYSMMU_POWERDOMAIN(jpeg, &exynos4_device_pd[PD_CAM].dev); ASSIGN_SYSMMU_POWERDOMAIN(fimd0, &exynos4_device_pd[PD_LCD0].dev); - ASSIGN_SYSMMU_POWERDOMAIN(2d, &exynos4_device_pd[PD_LCD0].dev); ASSIGN_SYSMMU_POWERDOMAIN(rot, &exynos4_device_pd[PD_LCD0].dev); ASSIGN_SYSMMU_POWERDOMAIN(tv, &exynos4_device_pd[PD_TV].dev); ASSIGN_SYSMMU_POWERDOMAIN(mfc_l, &exynos4_device_pd[PD_MFC].dev); @@ -6577,14 +5503,14 @@ static void __init exynos_sysmmu_init(void) #ifdef CONFIG_VIDEO_JPEG sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev); #endif -#ifdef CONFIG_FB_S3C +#ifdef CONFIG_DRM_EXYNOS_FIMD sysmmu_set_owner(&SYSMMU_PLATDEV(fimd0).dev, &s5p_device_fimd0.dev); #endif -#ifdef CONFIG_VIDEO_FIMG2D - sysmmu_set_owner(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev); +#ifdef CONFIG_DRM_EXYNOS_HDMI + sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_hdmi.dev); #endif -#ifdef CONFIG_VIDEO_TVOUT - sysmmu_set_owner(&SYSMMU_PLATDEV(tv).dev, &s5p_device_tvout.dev); +#ifdef CONFIG_DRM_EXYNOS_G2D + sysmmu_set_owner(&SYSMMU_PLATDEV(g2d_acp).dev, &s5p_device_fimg2d.dev); #endif #if defined(CONFIG_VIDEO_MFC5X) || defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) sysmmu_set_owner(&SYSMMU_PLATDEV(mfc_l).dev, &s5p_device_mfc.dev); @@ -6592,7 +5518,7 @@ static void __init exynos_sysmmu_init(void) #endif } -static void __init smdkc210_map_io(void) +static void __init trats_map_io(void) { clk_xusbxti.rate = 24000000; @@ -6610,6 +5536,17 @@ static void __init smdkc210_map_io(void) sec_debug_init(); } +#ifdef CONFIG_TOUCHSCREEN_MELFAS_MMS +static void __init universal_tsp_set_platdata(struct melfas_mms_platform_data + *pdata) +{ + if (!pdata) + pdata = &melfas_mms_ts_pdata; + + i2c_devs3[0].platform_data = pdata; +} +#endif + static void __init universal_tsp_init(void) { int gpio; @@ -6635,58 +5572,38 @@ static void __init universal_tsp_init(void) #endif } -#ifdef CONFIG_EPEN_WACOM_G5SP -static int p6_wacom_init_hw(void) +static void check_hw_revision(void) { - int gpio; - int ret; - - gpio = GPIO_PEN_RESET; - ret = gpio_request(gpio, "PEN_RESET"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); - gpio_direction_output(gpio, 1); - - gpio = GPIO_PEN_SLP; - ret = gpio_request(gpio, "PEN_SLP"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0x1)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - gpio_direction_output(gpio, 0); - - gpio = GPIO_PEN_PDCT; - ret = gpio_request(gpio, "PEN_PDCT"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0x0)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - gpio_direction_input(gpio); - - gpio = GPIO_PEN_IRQ; - ret = gpio_request(gpio, "PEN_IRQ"); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_register_gpio_interrupt(gpio); - gpio_direction_input(gpio); - - i2c_devs6[1].irq = gpio_to_irq(gpio); - irq_set_irq_type(i2c_devs6[1].irq, IRQ_TYPE_EDGE_RISING); - - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); - - return 0; -} + unsigned int hwrev = system_rev & 0xff; + + switch (hwrev) { + case U1HD_5INCH_REV0_0: /* U1HD_5INCH_REV0.0_111228 */ + universal_tsp_set_platdata(&melfas_mms_ts_pdata_rotate); + universal_tsp_init(); + s3c_i2c3_set_platdata(NULL); + i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); + break; + case U1HD_REV0_1: /* U1HD_REV0_1 */ + universal_tsp_set_platdata(&melfas_mms_ts_pdata); + universal_tsp_init(); + s3c_i2c3_set_platdata(NULL); + i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); + break; -static int __init p6_wacom_init(void) -{ - p6_wacom_init_hw(); - printk(KERN_INFO "[E-PEN] : wacom IC initialized.\n"); - return 0; + default: + break; + } } -#endif -static void __init smdkc210_machine_init(void) +static void __init trats_machine_init(void) { #ifdef CONFIG_S3C64XX_DEV_SPI struct clk *sclk = NULL; struct clk *prnt = NULL; struct device *spi0_dev = &exynos_device_spi0.dev; #endif + + strcpy(utsname()->nodename, machine_desc->name); /* initialise the gpios */ u1_config_gpio_table(); exynos4_sleep_gpio_table_set = u1_config_sleep_gpio_table; @@ -6703,11 +5620,7 @@ static void __init smdkc210_machine_init(void) s3c_i2c2_set_platdata(NULL); i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2)); #endif -#ifdef CONFIG_S3C_DEV_I2C3 - universal_tsp_init(); - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); -#endif + #ifdef CONFIG_S3C_DEV_I2C4 s3c_i2c4_set_platdata(NULL); i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4)); @@ -6727,7 +5640,7 @@ static void __init smdkc210_machine_init(void) i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6)); #endif #ifdef CONFIG_S3C_DEV_I2C7 - s3c_i2c7_set_platdata(NULL); + s3c_i2c7_set_platdata(&default_i2c7_data); i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7)); #endif #ifdef CONFIG_SAMSUNG_MHL @@ -6736,12 +5649,6 @@ static void __init smdkc210_machine_init(void) i2c_register_board_info(15, tuna_i2c15_boardinfo, ARRAY_SIZE(tuna_i2c15_boardinfo)); #endif -#ifdef CONFIG_S3C_DEV_I2C8_EMUL - i2c_register_board_info(8, i2c_devs8_emul, ARRAY_SIZE(i2c_devs8_emul)); - gpio_request(GPIO_3_TOUCH_INT, "sec_touchkey"); - s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT); - -#endif #ifdef CONFIG_S3C_DEV_I2C9_EMUL i2c_register_board_info(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul)); #endif @@ -6800,25 +5707,17 @@ static void __init smdkc210_machine_init(void) s3c_mshci_set_platdata(&exynos4_mshc_pdata); #endif -#ifdef CONFIG_FB_S3C -#ifdef CONFIG_LCD_AMS369FG06 - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); -#endif - s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata); -#ifdef CONFIG_EXYNOS_DEV_PD +#ifdef CONFIG_DRM_EXYNOS_FIMD + /* + * platform device name for fimd driver should be changed + * because we can get source clock with this name. + * + * P.S. refer to sclk_fimd definition of clock-exynos4.c + */ + s5p_fb_setname(0, "s3cfb"); s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev; -#endif -#endif - -#ifdef CONFIG_FB_S5P -#ifdef CONFIG_FB_S5P_AMS369FG06 - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - s3cfb_set_platdata(&ams369fg06_data); -#else - s3cfb_set_platdata(NULL); -#endif -#ifdef CONFIG_EXYNOS_DEV_PD - s3c_device_fb.dev.parent = &exynos4_device_pd[PD_LCD0].dev; +#ifdef CONFIG_S5P_MIPI_DSI2 + s5p_device_mipi_dsim0.dev.parent = &exynos4_device_pd[PD_LCD0].dev; #endif #endif @@ -6827,30 +5726,19 @@ static void __init smdkc210_machine_init(void) s5p_device_jpeg.dev.parent = &exynos4_device_pd[PD_CAM].dev; #endif #endif -#if defined(CONFIG_VIDEO_TVOUT) - s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data); - s5p_hdmi_cec_set_platdata(&hdmi_cec_data); -#ifdef CONFIG_EXYNOS_DEV_PD - s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev; -#endif -#endif -#ifdef CONFIG_TOUCHSCREEN_S3C2410 -#ifdef CONFIG_S3C_DEV_ADC - s3c24xx_ts_set_platdata(&s3c_ts_platform); -#endif -#ifdef CONFIG_S3C_DEV_ADC1 - s3c24xx_ts1_set_platdata(&s3c_ts_platform); -#endif -#endif #ifdef CONFIG_ANDROID_PMEM android_pmem_set_platdata(); #endif #ifdef CONFIG_VIDEO_FIMC /* fimc */ s3c_fimc0_set_platdata(&fimc_plat); - s3c_fimc1_set_platdata(NULL); - s3c_fimc2_set_platdata(&fimc_plat); + s3c_fimc1_set_platdata(&fimc_plat); + s3c_fimc2_set_platdata(NULL); +#ifdef CONFIG_DRM_EXYNOS_FIMD_WB + s3c_fimc3_set_platdata(&fimc_plat); +#else s3c_fimc3_set_platdata(NULL); +#endif #ifdef CONFIG_VIDEO_FIMC_MIPI s3c_csis0_set_platdata(NULL); s3c_csis1_set_platdata(NULL); @@ -6888,12 +5776,6 @@ static void __init smdkc210_machine_init(void) s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc"); #endif -#ifdef CONFIG_VIDEO_FIMG2D - s5p_fimg2d_set_platdata(&fimg2d_data); -#ifdef CONFIG_EXYNOS_DEV_PD - s5p_device_fimg2d.dev.parent = &exynos4_device_pd[PD_LCD0].dev; -#endif -#endif #ifdef CONFIG_USB_EHCI_S5P smdkc210_ehci_init(); #endif @@ -6903,18 +5785,9 @@ static void __init smdkc210_machine_init(void) #ifdef CONFIG_USB_GADGET smdkc210_usbgadget_init(); #endif -#ifdef CONFIG_FB_S5P_LD9040 - ld9040_fb_init(); -#endif -#ifdef CONFIG_FB_S5P_NT35560 - nt35560_fb_init(); -#endif -#if defined(CONFIG_FB_S5P_MIPI_DSIM) - mipi_fb_init(); -#endif -#ifdef CONFIG_SND_SOC_U1_MC1N2 - u1_sound_init(); +#if defined(CONFIG_SND_SOC_SLP_TRATS_MC1N2) + trats_sound_init(); #endif brcm_wlan_init(); @@ -6923,13 +5796,15 @@ static void __init smdkc210_machine_init(void) platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); -#ifdef CONFIG_SEC_THERMISTOR - platform_device_register(&sec_device_thermistor); +#ifdef CONFIG_DRM_EXYNOS_FIMD + trats_fb_init(); +#endif +#ifdef CONFIG_DRM_EXYNOS_HDMI + trats_tv_init(); #endif -#ifdef CONFIG_FB_S3C - exynos4_fimd0_setup_clock(&s5p_device_fimd0.dev, "mout_mpll", - 800 * MHZ); +#ifdef CONFIG_SEC_THERMISTOR + platform_device_register(&sec_device_thermistor); #endif #ifdef CONFIG_S3C64XX_DEV_SPI @@ -6961,6 +5836,7 @@ static void __init smdkc210_machine_init(void) #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) tdmb_dev_init(); #endif + check_hw_revision(); } @@ -6979,12 +5855,27 @@ static void __init exynos_init_reserve(void) #define MODEL_NAME "SMDK4210" #endif -MACHINE_START(SMDKC210, MODEL_NAME) - /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ +MACHINE_START(TRATS, "TRATS") + /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ + .boot_params = S5P_PA_SDRAM + 0x100, + .init_irq = exynos4_init_irq, + .map_io = trats_map_io, + .init_machine = trats_machine_init, + .timer = &exynos4_timer, + .init_early = &exynos_init_reserve, +MACHINE_END + +/* + * This is just for backward compatability because the old TRATS have been + * shipped with this id. MACH_DDNAS also has same but we don't care. + */ +MACHINE_START(U1HD, "U1HD") + /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = exynos4_init_irq, - .map_io = smdkc210_map_io, - .init_machine = smdkc210_machine_init, + .map_io = trats_map_io, + .init_machine = trats_machine_init, .timer = &exynos4_timer, .init_early = &exynos_init_reserve, MACHINE_END + diff --git a/arch/arm/mach-exynos/board-u1-lgt-modems.c b/arch/arm/mach-exynos/board-u1-lgt-modems.c index 9fce9e3..241d99f 100644 --- a/arch/arm/mach-exynos/board-u1-lgt-modems.c +++ b/arch/arm/mach-exynos/board-u1-lgt-modems.c @@ -70,8 +70,8 @@ struct sromc_access_cfg { u32 pmc; /* Page Mode config */ }; -/* For CBP7.2 EDPRAM (External DPRAM) */ -#define CBP_EDPRAM_SIZE 0x8000 /* 32 KB */ +/* For EDPRAM (External DPRAM) */ +#define MDM_EDPRAM_SIZE 0x8000 /* 32 KB */ #define INT_MASK_REQ_ACK_F 0x0020 @@ -93,12 +93,12 @@ static void setup_sromc(unsigned csn, struct sromc_cfg *cfg, struct sromc_access_cfg *acc_cfg); static int __init init_modem(void); -static struct sromc_cfg cbp_edpram_cfg = { +static struct sromc_cfg mdm_edpram_cfg = { .attr = (SROMC_DATA_16 | SROMC_WAIT_EN | SROMC_BYTE_EN), - .size = CBP_EDPRAM_SIZE, + .size = MDM_EDPRAM_SIZE, }; -static struct sromc_access_cfg cbp_edpram_access_cfg[] = { +static struct sromc_access_cfg mdm_edpram_access_cfg[] = { [DPRAM_SPEED_LOW] = { .tacs = 0x2 << 28, .tcos = 0x2 << 24, @@ -132,46 +132,46 @@ static struct sromc_access_cfg cbp_edpram_access_cfg[] = { = 32768 */ -#define CBP_DP_FMT_TX_BUFF_SZ 4092 -#define CBP_DP_RAW_TX_BUFF_SZ 12272 -#define CBP_DP_FMT_RX_BUFF_SZ 4092 -#define CBP_DP_RAW_RX_BUFF_SZ 12272 +#define MDM_DP_FMT_TX_BUFF_SZ 4092 +#define MDM_DP_RAW_TX_BUFF_SZ 12272 +#define MDM_DP_FMT_RX_BUFF_SZ 4092 +#define MDM_DP_RAW_RX_BUFF_SZ 12272 -#define MAX_CBP_EDPRAM_IPC_DEV 2 /* FMT, RAW */ +#define MAX_MDM_EDPRAM_IPC_DEV 2 /* FMT, RAW */ -struct cbp_edpram_ipc_cfg { +struct mdm_edpram_ipc_cfg { u16 magic; u16 access; u16 fmt_tx_head; u16 fmt_tx_tail; - u8 fmt_tx_buff[CBP_DP_FMT_TX_BUFF_SZ]; + u8 fmt_tx_buff[MDM_DP_FMT_TX_BUFF_SZ]; u16 raw_tx_head; u16 raw_tx_tail; - u8 raw_tx_buff[CBP_DP_RAW_TX_BUFF_SZ]; + u8 raw_tx_buff[MDM_DP_RAW_TX_BUFF_SZ]; u16 fmt_rx_head; u16 fmt_rx_tail; - u8 fmt_rx_buff[CBP_DP_FMT_RX_BUFF_SZ]; + u8 fmt_rx_buff[MDM_DP_FMT_RX_BUFF_SZ]; u16 raw_rx_head; u16 raw_rx_tail; - u8 raw_rx_buff[CBP_DP_RAW_RX_BUFF_SZ]; + u8 raw_rx_buff[MDM_DP_RAW_RX_BUFF_SZ]; u8 padding[16]; u16 mbx_ap2cp; u16 mbx_cp2ap; }; -struct cbp_edpram_boot_map { +struct mdm_edpram_boot_map { u8 __iomem *buff; u16 __iomem *frame_size; u16 __iomem *tag; u16 __iomem *count; }; -static struct dpram_ipc_map cbp_ipc_map; +static struct dpram_ipc_map mdm_ipc_map; struct _param_nv { unsigned char *addr; @@ -220,40 +220,10 @@ static struct _param_nv *data_param; static struct _param_check check_param; static unsigned int boot_start_complete; -static struct cbp_edpram_boot_map cbp_edpram_bt_map; - -static void cbp_edpram_reset(void); -static void cbp_edpram_clr_intr(void); -static u16 cbp_edpram_recv_intr(void); -static void cbp_edpram_send_intr(u16 irq_mask); -static u16 cbp_edpram_recv_msg(void); -static void cbp_edpram_send_msg(u16 msg); - -static u16 cbp_edpram_get_magic(void); -static void cbp_edpram_set_magic(u16 value); -static u16 cbp_edpram_get_access(void); -static void cbp_edpram_set_access(u16 value); - -static u32 cbp_edpram_get_tx_head(int dev_id); -static u32 cbp_edpram_get_tx_tail(int dev_id); -static void cbp_edpram_set_tx_head(int dev_id, u32 head); -static void cbp_edpram_set_tx_tail(int dev_id, u32 tail); -static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id); -static u32 cbp_edpram_get_tx_buff_size(int dev_id); - -static u32 cbp_edpram_get_rx_head(int dev_id); -static u32 cbp_edpram_get_rx_tail(int dev_id); -static void cbp_edpram_set_rx_head(int dev_id, u32 head); -static void cbp_edpram_set_rx_tail(int dev_id, u32 tail); -static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id); -static u32 cbp_edpram_get_rx_buff_size(int dev_id); - -static u16 cbp_edpram_get_mask_req_ack(int dev_id); -static u16 cbp_edpram_get_mask_res_ack(int dev_id); -static u16 cbp_edpram_get_mask_send(int dev_id); - -static void msm_vbus_on(void); -static void msm_vbus_off(void); +static struct mdm_edpram_boot_map mdm_edpram_bt_map; + +static void mdm_vbus_on(void); +static void mdm_vbus_off(void); static void mdm_log_disp(struct modemlink_dpram_control *dpctl); static int mdm_uload_step1(struct modemlink_dpram_control *dpctl); @@ -268,61 +238,27 @@ static void mdm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd); static void mdm_bt_map_init(struct modemlink_dpram_control *dpctl); static void mdm_load_init(struct modemlink_dpram_control *dpctl); -static struct modemlink_dpram_control cbp_edpram_ctrl = { - .reset = cbp_edpram_reset, - - .clear_intr = cbp_edpram_clr_intr, - .recv_intr = cbp_edpram_recv_intr, - .send_intr = cbp_edpram_send_intr, - .recv_msg = cbp_edpram_recv_msg, - .send_msg = cbp_edpram_send_msg, - - .get_magic = cbp_edpram_get_magic, - .set_magic = cbp_edpram_set_magic, - .get_access = cbp_edpram_get_access, - .set_access = cbp_edpram_set_access, - - .get_tx_head = cbp_edpram_get_tx_head, - .get_tx_tail = cbp_edpram_get_tx_tail, - .set_tx_head = cbp_edpram_set_tx_head, - .set_tx_tail = cbp_edpram_set_tx_tail, - .get_tx_buff = cbp_edpram_get_tx_buff, - .get_tx_buff_size = cbp_edpram_get_tx_buff_size, - - .get_rx_head = cbp_edpram_get_rx_head, - .get_rx_tail = cbp_edpram_get_rx_tail, - .set_rx_head = cbp_edpram_set_rx_head, - .set_rx_tail = cbp_edpram_set_rx_tail, - .get_rx_buff = cbp_edpram_get_rx_buff, - .get_rx_buff_size = cbp_edpram_get_rx_buff_size, - - .get_mask_req_ack = cbp_edpram_get_mask_req_ack, - .get_mask_res_ack = cbp_edpram_get_mask_res_ack, - .get_mask_send = cbp_edpram_get_mask_send, - - .log_disp = mdm_log_disp, - .cpupload_step1 = mdm_uload_step1, - .cpupload_step2 = mdm_uload_step2, - .cpimage_load_prepare = mdm_dload_prep, - .cpimage_load = mdm_dload, - .nvdata_load = mdm_nv_load, - .phone_boot_start = mdm_boot_start, - .phone_boot_start_post_process = mdm_boot_start_post_proc, - .phone_boot_start_handler = mdm_boot_start_handler, - .dload_cmd_hdlr = mdm_dload_handler, - .bt_map_init = mdm_bt_map_init, - .load_init = mdm_load_init, - - .dp_base = NULL, - .dp_size = 0, +static struct modemlink_dpram_control mdm_edpram_ctrl = { + .log_disp = mdm_log_disp, + .cpupload_step1 = mdm_uload_step1, + .cpupload_step2 = mdm_uload_step2, + .cpimage_load_prepare = mdm_dload_prep, + .cpimage_load = mdm_dload, + .nvdata_load = mdm_nv_load, + .phone_boot_start = mdm_boot_start, + .phone_boot_start_post_process = mdm_boot_start_post_proc, + .phone_boot_start_handler = mdm_boot_start_handler, + .dload_cmd_hdlr = mdm_dload_handler, + .bt_map_init = mdm_bt_map_init, + .load_init = mdm_load_init, + .dp_type = EXT_DPRAM, - .dpram_irq = IRQ_EINT(8), - .dpram_irq_flags = IRQF_TRIGGER_FALLING, - .dpram_irq_name = "MDM6600_EDPRAM_IRQ", - .dpram_wlock_name = "MDM6600_EDPRAM_WLOCK", + .dpram_irq = IRQ_EINT(8), + .dpram_irq_flags = IRQF_TRIGGER_FALLING, .max_ipc_dev = IPC_RFS, + .ipc_map = &mdm_ipc_map, }; /* @@ -485,10 +421,10 @@ static struct modem_data cdma_modem_data = { .gpio_cp_reset = GPIO_CP_RST, .gpio_pda_active = GPIO_PDA_ACTIVE, .gpio_phone_active = GPIO_PHONE_ACTIVE, - .gpio_cp_reset_msm = GPIO_CP_RST_MSM, + .gpio_cp_reset_mdm = GPIO_CP_RST_MSM, .gpio_boot_sw_sel = GPIO_BOOT_SW_SEL, - .vbus_on = msm_vbus_on, - .vbus_off = msm_vbus_off, + .vbus_on = mdm_vbus_on, + .vbus_off = mdm_vbus_off, .cp_vbus = NULL, .gpio_cp_dump_int = 0, .gpio_cp_warm_reset = 0, @@ -497,14 +433,12 @@ static struct modem_data cdma_modem_data = { .modem_type = QC_MDM6600, .link_types = LINKTYPE(LINKDEV_DPRAM), .link_name = "mdm6600_edpram", - .dpram_ctl = &cbp_edpram_ctrl, + .dpram_ctl = &mdm_edpram_ctrl, + + .ipc_version = SIPC_VER_41, .num_iodevs = ARRAY_SIZE(cdma_io_devices), .iodevs = cdma_io_devices, - - .use_handover = false, - - .ipc_version = SIPC_VER_41, }; static struct resource cdma_modem_res[] = { @@ -526,132 +460,7 @@ static struct platform_device cdma_modem = { }, }; -static void cbp_edpram_reset(void) -{ - return; -} - -static void cbp_edpram_clr_intr(void) -{ - ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static u16 cbp_edpram_recv_intr(void) -{ - return ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static void cbp_edpram_send_intr(u16 irq_mask) -{ - iowrite16(irq_mask, cbp_ipc_map.mbx_ap2cp); -} - -static u16 cbp_edpram_recv_msg(void) -{ - return ioread16(cbp_ipc_map.mbx_cp2ap); -} - -static void cbp_edpram_send_msg(u16 msg) -{ - iowrite16(msg, cbp_ipc_map.mbx_ap2cp); -} - -static u16 cbp_edpram_get_magic(void) -{ - return ioread16(cbp_ipc_map.magic); -} - -static void cbp_edpram_set_magic(u16 value) -{ - iowrite16(value, cbp_ipc_map.magic); -} - -static u16 cbp_edpram_get_access(void) -{ - return ioread16(cbp_ipc_map.access); -} - -static void cbp_edpram_set_access(u16 value) -{ - iowrite16(value, cbp_ipc_map.access); -} - -static u32 cbp_edpram_get_tx_head(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].txq.head); -} - -static u32 cbp_edpram_get_tx_tail(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].txq.tail); -} - -static void cbp_edpram_set_tx_head(int dev_id, u32 head) -{ - iowrite16((u16)head, cbp_ipc_map.dev[dev_id].txq.head); -} - -static void cbp_edpram_set_tx_tail(int dev_id, u32 tail) -{ - iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].txq.tail); -} - -static u8 __iomem *cbp_edpram_get_tx_buff(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].txq.buff; -} - -static u32 cbp_edpram_get_tx_buff_size(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].txq.size; -} - -static u32 cbp_edpram_get_rx_head(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].rxq.head); -} - -static u32 cbp_edpram_get_rx_tail(int dev_id) -{ - return ioread16(cbp_ipc_map.dev[dev_id].rxq.tail); -} - -static void cbp_edpram_set_rx_head(int dev_id, u32 head) -{ - return iowrite16((u16)head, cbp_ipc_map.dev[dev_id].rxq.head); -} - -static void cbp_edpram_set_rx_tail(int dev_id, u32 tail) -{ - return iowrite16((u16)tail, cbp_ipc_map.dev[dev_id].rxq.tail); -} - -static u8 __iomem *cbp_edpram_get_rx_buff(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].rxq.buff; -} - -static u32 cbp_edpram_get_rx_buff_size(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].rxq.size; -} - -static u16 cbp_edpram_get_mask_req_ack(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_req_ack; -} - -static u16 cbp_edpram_get_mask_res_ack(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_res_ack; -} - -static u16 cbp_edpram_get_mask_send(int dev_id) -{ - return cbp_ipc_map.dev[dev_id].mask_send; -} - -static void msm_vbus_on(void) +static void mdm_vbus_on(void) { int err; @@ -686,7 +495,7 @@ static void msm_vbus_on(void) } } -static void msm_vbus_off(void) +static void mdm_vbus_off(void) { if (cdma_modem_data.cp_vbus) { pr_info("%s\n", __func__); @@ -747,10 +556,10 @@ static int mdm_data_upload(struct _param_nv *param, } } - param->size = ioread16(cbp_edpram_bt_map.frame_size); - memcpy(param->addr, cbp_edpram_bt_map.buff, param->size); - param->tag = ioread16(cbp_edpram_bt_map.tag); - param->count = ioread16(cbp_edpram_bt_map.count); + param->size = ioread16(mdm_edpram_bt_map.frame_size); + memcpy(param->addr, mdm_edpram_bt_map.buff, param->size); + param->tag = ioread16(mdm_edpram_bt_map.tag); + param->count = ioread16(mdm_edpram_bt_map.count); dpctl->clear_intr(); dpctl->send_msg(0xDB12); @@ -765,10 +574,10 @@ static int mdm_data_load(struct _param_nv *param, int retval = 0; if (param->size <= DP_BOOT_FRAME_SIZE_LIMIT) { - memcpy(cbp_edpram_bt_map.buff, param->addr, param->size); - iowrite16(param->size, cbp_edpram_bt_map.frame_size); - iowrite16(param->tag, cbp_edpram_bt_map.tag); - iowrite16(param->count, cbp_edpram_bt_map.count); + memcpy(mdm_edpram_bt_map.buff, param->addr, param->size); + iowrite16(param->size, mdm_edpram_bt_map.frame_size); + iowrite16(param->tag, mdm_edpram_bt_map.tag); + iowrite16(param->count, mdm_edpram_bt_map.count); dpctl->clear_intr(); dpctl->send_msg(0xDB12); @@ -843,7 +652,7 @@ static int mdm_uload_step2(void *arg, if (param.tag == 4) { dpctl->clear_intr(); - enable_irq(cbp_edpram_ctrl.dpram_irq); + enable_irq(mdm_edpram_ctrl.dpram_irq); pr_info("[LNK] [param->tag]:%d\n", param.tag); } @@ -1129,12 +938,12 @@ static void mdm_dload_handler(struct modemlink_dpram_control *dpctl, u16 cmd) static void mdm_bt_map_init(struct modemlink_dpram_control *dpctl) { - cbp_edpram_bt_map.buff = (u8 *)(dpctl->dp_base); - cbp_edpram_bt_map.frame_size = + mdm_edpram_bt_map.buff = (u8 *)(dpctl->dp_base); + mdm_edpram_bt_map.frame_size = (u16 *)(dpctl->dp_base + DP_BOOT_SIZE_OFFSET); - cbp_edpram_bt_map.tag = + mdm_edpram_bt_map.tag = (u16 *)(dpctl->dp_base + DP_BOOT_TAG_OFFSET); - cbp_edpram_bt_map.count = + mdm_edpram_bt_map.count = (u16 *)(dpctl->dp_base + DP_BOOT_COUNT_OFFSET); } @@ -1163,7 +972,7 @@ static void config_cdma_modem_gpio(void) unsigned gpio_cp_rst = cdma_modem_data.gpio_cp_reset; unsigned gpio_pda_active = cdma_modem_data.gpio_pda_active; unsigned gpio_phone_active = cdma_modem_data.gpio_phone_active; - unsigned gpio_cp_reset_msm = cdma_modem_data.gpio_cp_reset_msm; + unsigned gpio_cp_reset_mdm = cdma_modem_data.gpio_cp_reset_mdm; unsigned gpio_boot_sw_sel = cdma_modem_data.gpio_boot_sw_sel; pr_info("[MDM] <%s>\n", __func__); @@ -1187,15 +996,15 @@ static void config_cdma_modem_gpio(void) s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); } - if (gpio_cp_reset_msm) { - err = gpio_request(gpio_cp_reset_msm, "CP_RST_MSM"); + if (gpio_cp_reset_mdm) { + err = gpio_request(gpio_cp_reset_mdm, "CP_RST_MSM"); if (err) { printk(KERN_ERR "fail to request gpio %s : %d\n", "CP_RST_MSM", err); } - gpio_direction_output(gpio_cp_reset_msm, 0); - s3c_gpio_cfgpin(gpio_cp_reset_msm, S3C_GPIO_SFN(0x1)); - s3c_gpio_setpull(gpio_cp_reset_msm, S3C_GPIO_PULL_NONE); + gpio_direction_output(gpio_cp_reset_mdm, 0); + s3c_gpio_cfgpin(gpio_cp_reset_mdm, S3C_GPIO_SFN(0x1)); + s3c_gpio_setpull(gpio_cp_reset_mdm, S3C_GPIO_PULL_NONE); } if (gpio_boot_sw_sel) { @@ -1232,12 +1041,12 @@ static void config_cdma_modem_gpio(void) } -static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg) +static u8 *mdm_edpram_remap_mem_region(struct sromc_cfg *cfg) { int dp_addr = 0; int dp_size = 0; u8 __iomem *dp_base = NULL; - struct cbp_edpram_ipc_cfg *ipc_map = NULL; + struct mdm_edpram_ipc_cfg *ipc_map = NULL; struct dpram_ipc_device *dev = NULL; dp_addr = cfg->addr; @@ -1249,18 +1058,18 @@ static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg) } pr_info("[MDM] <%s> DPRAM VA=0x%08X\n", __func__, (int)dp_base); - cbp_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; - cbp_edpram_ctrl.dp_size = dp_size; + mdm_edpram_ctrl.dp_base = (u8 __iomem *)dp_base; + mdm_edpram_ctrl.dp_size = dp_size; /* Map for IPC */ - ipc_map = (struct cbp_edpram_ipc_cfg *)dp_base; + ipc_map = (struct mdm_edpram_ipc_cfg *)dp_base; /* Magic code and access enable fields */ - cbp_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; - cbp_ipc_map.access = (u16 __iomem *)&ipc_map->access; + mdm_ipc_map.magic = (u16 __iomem *)&ipc_map->magic; + mdm_ipc_map.access = (u16 __iomem *)&ipc_map->access; /* FMT */ - dev = &cbp_ipc_map.dev[IPC_FMT]; + dev = &mdm_ipc_map.dev[IPC_FMT]; strcpy(dev->name, "FMT"); dev->id = IPC_FMT; @@ -1268,19 +1077,19 @@ static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg) dev->txq.head = (u16 __iomem *)&ipc_map->fmt_tx_head; dev->txq.tail = (u16 __iomem *)&ipc_map->fmt_tx_tail; dev->txq.buff = (u8 __iomem *)&ipc_map->fmt_tx_buff[0]; - dev->txq.size = CBP_DP_FMT_TX_BUFF_SZ; + dev->txq.size = MDM_DP_FMT_TX_BUFF_SZ; dev->rxq.head = (u16 __iomem *)&ipc_map->fmt_rx_head; dev->rxq.tail = (u16 __iomem *)&ipc_map->fmt_rx_tail; dev->rxq.buff = (u8 __iomem *)&ipc_map->fmt_rx_buff[0]; - dev->rxq.size = CBP_DP_FMT_RX_BUFF_SZ; + dev->rxq.size = MDM_DP_FMT_RX_BUFF_SZ; dev->mask_req_ack = INT_MASK_REQ_ACK_F; dev->mask_res_ack = INT_MASK_RES_ACK_F; dev->mask_send = INT_MASK_SEND_F; /* RAW */ - dev = &cbp_ipc_map.dev[IPC_RAW]; + dev = &mdm_ipc_map.dev[IPC_RAW]; strcpy(dev->name, "RAW"); dev->id = IPC_RAW; @@ -1288,42 +1097,20 @@ static u8 *cbp_edpram_remap_mem_region(struct sromc_cfg *cfg) dev->txq.head = (u16 __iomem *)&ipc_map->raw_tx_head; dev->txq.tail = (u16 __iomem *)&ipc_map->raw_tx_tail; dev->txq.buff = (u8 __iomem *)&ipc_map->raw_tx_buff[0]; - dev->txq.size = CBP_DP_RAW_TX_BUFF_SZ; + dev->txq.size = MDM_DP_RAW_TX_BUFF_SZ; dev->rxq.head = (u16 __iomem *)&ipc_map->raw_rx_head; dev->rxq.tail = (u16 __iomem *)&ipc_map->raw_rx_tail; dev->rxq.buff = (u8 __iomem *)&ipc_map->raw_rx_buff[0]; - dev->rxq.size = CBP_DP_RAW_RX_BUFF_SZ; + dev->rxq.size = MDM_DP_RAW_RX_BUFF_SZ; dev->mask_req_ack = INT_MASK_REQ_ACK_R; dev->mask_res_ack = INT_MASK_RES_ACK_R; dev->mask_send = INT_MASK_SEND_R; -#if 0 - /* RFS */ - dev = &cbp_ipc_map.dev[IPC_RFS]; - - strcpy(dev->name, "RFS"); - dev->id = IPC_RFS; - - dev->txq.head = (u16 __iomem *)&ipc_map->rfs_tx_head; - dev->txq.tail = (u16 __iomem *)&ipc_map->rfs_tx_tail; - dev->txq.buff = (u8 __iomem *)&ipc_map->rfs_tx_buff[0]; - dev->txq.size = CBP_DP_RFS_TX_BUFF_SZ; - - dev->rxq.head = (u16 __iomem *)&ipc_map->rfs_rx_head; - dev->rxq.tail = (u16 __iomem *)&ipc_map->rfs_rx_tail; - dev->rxq.buff = (u8 __iomem *)&ipc_map->rfs_rx_buff[0]; - dev->rxq.size = CBP_DP_RFS_RX_BUFF_SZ; - - dev->mask_req_ack = INT_MASK_REQ_ACK_RFS; - dev->mask_res_ack = INT_MASK_RES_ACK_RFS; - dev->mask_send = INT_MASK_SEND_RFS; -#endif - /* Mailboxes */ - cbp_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; - cbp_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; + mdm_ipc_map.mbx_ap2cp = (u16 __iomem *)&ipc_map->mbx_ap2cp; + mdm_ipc_map.mbx_cp2ap = (u16 __iomem *)&ipc_map->mbx_cp2ap; return dp_base; } @@ -1437,21 +1224,21 @@ static int __init init_modem(void) struct sromc_cfg *cfg = NULL; struct sromc_access_cfg *acc_cfg = NULL; - cbp_edpram_cfg.csn = 0; - cbp_edpram_ctrl.dpram_irq = IRQ_EINT(8); - cbp_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * cbp_edpram_cfg.csn); - cbp_edpram_cfg.end = cbp_edpram_cfg.addr + cbp_edpram_cfg.size - 1; + mdm_edpram_cfg.csn = 0; + mdm_edpram_ctrl.dpram_irq = IRQ_EINT(8); + mdm_edpram_cfg.addr = SROM_CS0_BASE + (SROM_WIDTH * mdm_edpram_cfg.csn); + mdm_edpram_cfg.end = mdm_edpram_cfg.addr + mdm_edpram_cfg.size - 1; config_dpram_port_gpio(); config_cdma_modem_gpio(); init_sromc(); - cfg = &cbp_edpram_cfg; - acc_cfg = &cbp_edpram_access_cfg[DPRAM_SPEED_LOW]; + cfg = &mdm_edpram_cfg; + acc_cfg = &mdm_edpram_access_cfg[DPRAM_SPEED_LOW]; setup_sromc(cfg->csn, cfg, acc_cfg); - if (!cbp_edpram_remap_mem_region(&cbp_edpram_cfg)) + if (!mdm_edpram_remap_mem_region(&mdm_edpram_cfg)) return -1; platform_device_register(&cdma_modem); diff --git a/arch/arm/mach-exynos/board-u1-modems.c b/arch/arm/mach-exynos/board-u1-modems.c index 1b35070..793b89a 100644 --- a/arch/arm/mach-exynos/board-u1-modems.c +++ b/arch/arm/mach-exynos/board-u1-modems.c @@ -58,21 +58,33 @@ static struct modem_io_t umts_io_devices[] = { .links = LINKTYPE(LINKDEV_HSIC), }, [4] = { +#ifdef CONFIG_SLP + .name = "pdp0", +#else .name = "rmnet0", +#endif .id = 0x2A, .format = IPC_RAW, .io_type = IODEV_NET, .links = LINKTYPE(LINKDEV_HSIC), }, [5] = { +#ifdef CONFIG_SLP + .name = "pdp1", +#else .name = "rmnet1", +#endif .id = 0x2B, .format = IPC_RAW, .io_type = IODEV_NET, .links = LINKTYPE(LINKDEV_HSIC), }, [6] = { +#ifdef CONFIG_SLP + .name = "pdp2", +#else .name = "rmnet2", +#endif .id = 0x2C, .format = IPC_RAW, .io_type = IODEV_NET, @@ -253,8 +265,6 @@ void set_host_states(struct platform_device *pdev, int type) } if (active_ctl.gpio_initialized) { - if (type) - set_slave_wake(); pr_err("[MODEM_IF]Active States =%d, %s\n", type, pdev->name); gpio_direction_output(modem_link_pm_data.gpio_link_active, type); @@ -289,8 +299,7 @@ void set_hsic_lpa_states(int states) break; case STATE_HSIC_LPA_PHY_INIT: gpio_set_value(umts_modem_data.gpio_pda_active, 1); - gpio_set_value(modem_link_pm_data.gpio_link_slavewake, - 1); + set_slave_wake(); pr_info(LOG_TAG "set hsic lpa phy init: " "slave wake-up (%d)\n", gpio_get_value( diff --git a/arch/arm/mach-exynos/busfreq.c b/arch/arm/mach-exynos/busfreq.c index 38a31b1..bab94fc 100644 --- a/arch/arm/mach-exynos/busfreq.c +++ b/arch/arm/mach-exynos/busfreq.c @@ -154,8 +154,8 @@ static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = { #elif defined(CONFIG_BUSFREQ_QOS_1280X800) /* For Q1, P8 */ static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = { { - {0x07, 0x03, 0x07, 0x0f}, - {0x07, 0x03, 0x07, 0x0f}, + {0x06, 0x03, 0x06, 0x2f}, + {0x06, 0x03, 0x06, 0x2f}, {0x03, 0x0b, 0x00, 0x00}, }, { diff --git a/arch/arm/mach-exynos/busfreq_opp_4x12.c b/arch/arm/mach-exynos/busfreq_opp_4x12.c index 5f310ba..54837b4 100644 --- a/arch/arm/mach-exynos/busfreq_opp_4x12.c +++ b/arch/arm/mach-exynos/busfreq_opp_4x12.c @@ -64,6 +64,9 @@ unsigned int cpu_slope_size = CPU_SLOPE_SIZE; unsigned int dmc_max_threshold; unsigned int load_history_size = LOAD_HISTORY_SIZE; +static bool mif_locking; +static bool int_locking; + /* To save/restore DMC_PAUSE_CTRL register */ static unsigned int dmc_pause_ctrl; @@ -78,7 +81,9 @@ enum busfreq_level_idx { LV_END }; -static struct busfreq_table exynos4_busfreq_table[] = { +static struct busfreq_table *exynos4_busfreq_table; + +static struct busfreq_table exynos4_busfreq_table_orig[] = { {LV_0, 400266, 1100000, 0, 0, 0}, /* MIF : 400MHz INT : 200MHz */ {LV_1, 400200, 1100000, 0, 0, 0}, /* MIF : 400MHz INT : 200MHz */ {LV_2, 267200, 1000000, 0, 0, 0}, /* MIF : 267MHz INT : 200MHz */ @@ -88,6 +93,16 @@ static struct busfreq_table exynos4_busfreq_table[] = { {LV_6, 100100, 950000, 0, 0, 0}, /* MIF : 100MHz INT : 100MHz */ }; +static struct busfreq_table exynos4_busfreq_table_rev2[] = { + {LV_0, 440293, 1100000, 0, 0, 0}, /* MIF : 440MHz INT : 220MHz */ + {LV_1, 440220, 1100000, 0, 0, 0}, /* MIF : 440MHz INT : 220MHz */ + {LV_2, 293220, 1000000, 0, 0, 0}, /* MIF : 293MHz INT : 220MHz */ + {LV_3, 293176, 1000000, 0, 0, 0}, /* MIF : 293MHz INT : 176MHz */ + {LV_4, 176176, 950000, 0, 0, 0}, /* MIF : 176MHz INT : 176MHz */ + {LV_5, 147147, 950000, 0, 0, 0}, /* MIF : 147MHz INT : 147MHz */ + {LV_6, 110110, 950000, 0, 0, 0}, /* MIF : 110MHz INT : 110MHz */ +}; + enum busfreq_qos_target { BUS_QOS_0, BUS_QOS_1, @@ -95,9 +110,10 @@ enum busfreq_qos_target { }; static enum busfreq_qos_target busfreq_qos = BUS_QOS_0; +static unsigned int (*exynos4_qos_value)[LV_END][4]; #if defined(CONFIG_BUSFREQ_QOS_1280X800) /* P4NOTE */ -static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = { +static unsigned int exynos4_qos_value_orig[BUS_QOS_MAX][LV_END][4] = { { {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, @@ -105,7 +121,7 @@ static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = { {0x06, 0x03, 0x06, 0x0e}, {0x03, 0x03, 0x03, 0x0e}, {0x03, 0x03, 0x03, 0x0e}, - {0x03, 0x0B, 0x00, 0x00}, + {0x02, 0x0B, 0x00, 0x00}, }, { {0x06, 0x0b, 0x06, 0x0f}, @@ -114,11 +130,32 @@ static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = { {0x06, 0x0b, 0x06, 0x0f}, {0x06, 0x03, 0x06, 0x0e}, {0x04, 0x03, 0x04, 0x0e}, - {0x03, 0x0b, 0x00, 0x00}, + {0x02, 0x0b, 0x00, 0x00}, + }, +}; + +static unsigned int exynos4_qos_value_rev2[BUS_QOS_MAX][LV_END][4] = { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x06, 0x03, 0x06, 0x0e}, + {0x06, 0x03, 0x06, 0x0e}, + {0x03, 0x03, 0x03, 0x0e}, + {0x03, 0x03, 0x03, 0x0e}, + {0x02, 0x0B, 0x00, 0x00}, + }, + { + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x03, 0x06, 0x0e}, + {0x04, 0x03, 0x04, 0x0e}, + {0x02, 0x0b, 0x00, 0x00}, }, }; #else -static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = { +static unsigned int exynos4_qos_value_orig[BUS_QOS_MAX][LV_END][4] = { { {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, @@ -138,10 +175,31 @@ static unsigned int exynos4_qos_value[BUS_QOS_MAX][LV_END][4] = { {0x03, 0x0b, 0x00, 0x00}, }, }; + +static unsigned int exynos4_qos_value_rev2[BUS_QOS_MAX][LV_END][4] = { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x06, 0x03, 0x06, 0x0e}, + {0x06, 0x03, 0x06, 0x0e}, + {0x03, 0x03, 0x03, 0x0e}, + {0x03, 0x03, 0x03, 0x0e}, + {0x02, 0x03, 0x02, 0x0e}, + }, + { + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x0b, 0x06, 0x0f}, + {0x06, 0x03, 0x06, 0x0e}, + {0x04, 0x03, 0x04, 0x0e}, + {0x03, 0x0b, 0x00, 0x00}, + }, +}; #endif #define ASV_GROUP 12 - +#define PRIME_ASV_GROUP 13 static unsigned int asv_group_index; static unsigned int (*exynos4_mif_volt)[LV_END]; @@ -178,42 +236,7 @@ static unsigned int exynos4212_int_volt[ASV_GROUP][LV_END] = { {1037500, 987500, 987500, 900000, 900000, 862500, 850000}, /* ASV10 */ {1035000, 975000, 975000, 887500, 887500, 850000, 850000}, /* RESERVED */ }; -#if 0 -/* 20120105 DVFS table */ -static unsigned int exynos4412_mif_volt[ASV_GROUP][LV_END] = { - /* 400 267 267 160 133 100 */ - {1100000, 1000000, 1000000, 950000, 950000, 950000}, /* ASV 0 */ - {1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV 1 */ - {1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV 2 */ - {1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV 3 */ - {1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV 4 */ - {1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV 5 */ - {1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV 6 */ - {1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV 7 */ - {1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV 8 */ - {1000000, 950000, 950000, 900000, 900000, 850000}, /* ASV 9 */ - {1000000, 900000, 900000, 900000, 900000, 850000}, /* ASV10 */ - {1000000, 900000, 900000, 900000, 900000, 850000}, /* ASV11 */ -}; - -static unsigned int exynos4412_int_volt[ASV_GROUP][LV_END] = { - /* 200 200 160 160 133 100 */ - {1062500, 1062500, 975000, 975000, 925000, 900000}, /* ASV 0 */ - {1050000, 1050000, 962500, 962500, 912500, 887500}, /* ASV 1 */ - {1037500, 1037500, 950000, 950000, 900000, 875000}, /* ASV 2 */ - {1025000, 1025000, 950000, 950000, 875000, 862500}, /* ASV 3 */ - {1025000, 1025000, 937500, 937500, 875000, 862500}, /* ASV 4 */ - {1012500, 1012500, 937500, 937500, 862500, 850000}, /* ASV 5 */ - {1012500, 1012500, 925000, 925000, 862500, 850000}, /* ASV 6 */ - {1000000, 1000000, 925000, 925000, 850000, 850000}, /* ASV 7 */ - {1000000, 1000000, 912500, 912500, 850000, 850000}, /* ASV 8 */ - {1000000, 1000000, 912500, 912500, 850000, 850000}, /* ASV 9 */ - {1000000, 1000000, 912500, 912500, 850000, 850000}, /* ASV10 */ - { 987500, 987500, 900000, 900000, 837500, 837500}, /* ASV11 */ -}; -#else -/* 20120210 DVFS table */ static unsigned int exynos4412_mif_volt[ASV_GROUP][LV_END] = { /* 400 400 267 267 160 133 100 */ {1100000, 1100000, 1000000, 1000000, 950000, 950000, 950000}, /* RESERVED */ @@ -246,7 +269,76 @@ static unsigned int exynos4412_int_volt[ASV_GROUP][LV_END] = { {1025000, 975000, 975000, 887500, 887500, 850000, 850000}, /* RESERVED */ }; -#endif + +/* 20120822 DVFS table for pega prime */ +/* Because buck1 of pmic can be set to 50mV step size, 50mV table is used */ +static unsigned int exynos4412_mif_volt_rev2[PRIME_ASV_GROUP][LV_END] = { + /* 440 440 293 293 176 147 110 */ + {1100000, 1100000, 1000000, 1000000, 950000, 950000, 950000}, /* RESERVED */ + {1100000, 1100000, 1000000, 1000000, 950000, 950000, 950000}, /* ASV1 */ + {1100000, 1100000, 1000000, 1000000, 950000, 950000, 900000}, /* ASV2 */ + {1100000, 1100000, 1000000, 1000000, 950000, 900000, 900000}, /* ASV3 */ + {1050000, 1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV4 */ + {1050000, 1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV5 */ + {1050000, 1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV6 */ + {1050000, 1050000, 950000, 950000, 900000, 900000, 850000}, /* ASV7 */ + {1050000, 1050000, 950000, 950000, 900000, 850000, 850000}, /* ASV8 */ + {1000000, 1000000, 900000, 900000, 850000, 850000, 850000}, /* ASV9 */ + {1000000, 1000000, 900000, 900000, 850000, 850000, 850000}, /* ASV10 */ + {1000000, 1000000, 900000, 900000, 850000, 850000, 850000}, /* ASV11 */ + { 950000, 950000, 850000, 850000, 850000, 850000, 850000}, /* ASV12 */ +}; + +/* 20120822 DVFS table for pega prime */ +static unsigned int exynos4412_int_volt_rev2[PRIME_ASV_GROUP][LV_END] = { + /* GDR : 293 220 220 176 176 147 110 */ + {1087500, 1062500, 1062500, 1000000, 1000000, 962500, 950000}, /* RESERVED */ + {1075000, 1050000, 1050000, 987500, 987500, 950000, 937500}, /* ASV1 */ + {1062500, 1037500, 1037500, 975000, 975000, 937500, 912500}, /* ASV2 */ + {1050000, 1037500, 1037500, 975000, 975000, 937500, 900000}, /* ASV3 */ + {1037500, 1025000, 1025000, 962500, 962500, 925000, 887500}, /* ASV4 */ + {1025000, 1012500, 1012500, 950000, 950000, 912500, 887500}, /* ASV5 */ + {1012500, 1000000, 1000000, 937500, 937500, 900000, 887500}, /* ASV6 */ + {1000000, 987500, 987500, 925000, 925000, 887500, 875000}, /* ASV7 */ + {1037500, 975000, 975000, 912500, 912500, 875000, 875000}, /* ASV8 */ + {1025000, 962500, 962500, 900000, 900000, 875000, 875000}, /* ASV9 */ + {1012500, 937500, 937500, 875000, 875000, 850000, 850000}, /* ASV10 */ + {1000000, 925000, 925000, 862500, 862500, 850000, 850000}, /* ASV11 */ + {1000000, 912500, 912500, 850000, 850000, 850000, 850000}, /* ASV12 */ +}; + +static unsigned int exynos4412_1ghz_mif_volt[ASV_GROUP][LV_END] = { + /* 400 400 267 267 160 133 100 */ + {1100000, 1100000, 1000000, 1000000, 950000, 950000, 950000}, /* RESERVED */ + {1050000, 1050000, 1000000, 1000000, 950000, 950000, 950000}, /* RESERVED */ + {1050000, 1050000, 1000000, 1000000, 950000, 950000, 950000}, /* ASV2 */ + {1050000, 1050000, 1000000, 1000000, 950000, 950000, 950000}, /* ASV3 */ + {1050000, 1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV4 */ + {1050000, 1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV5 */ + {1050000, 1050000, 950000, 950000, 900000, 900000, 900000}, /* ASV6 */ + {1000000, 1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV7 */ + {1000000, 1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV8 */ + {1000000, 1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV9 */ + {1000000, 1000000, 950000, 950000, 900000, 900000, 900000}, /* ASV10 */ + {1025000, 1025000, 925000, 925000, 925000, 925000, 875000}, /* RESERVED */ +}; + +static unsigned int exynos4412_1ghz_int_volt[ASV_GROUP][LV_END] = { +/* GDR : 266 200 200 160 160 133 100 */ + {0, 1087500, 1087500, 1000000, 1000000, 975000, 950000}, /* RESERVED */ + {0, 1050000, 1050000, 1000000, 1000000, 975000, 950000}, /* RESERVED */ + {0, 1050000, 1050000, 1000000, 1000000, 975000, 950000}, /* ASV2 */ + {0, 1050000, 1050000, 1000000, 1000000, 975000, 950000}, /* ASV3 */ + {0, 1037500, 1037500, 950000, 950000, 925000, 900000}, /* ASV4 */ + {0, 1037500, 1037500, 950000, 950000, 925000, 900000}, /* ASV5 */ + {0, 1037500, 1037500, 950000, 950000, 925000, 900000}, /* ASV6 */ + {0, 1012500, 1012500, 937500, 937500, 887500, 875000}, /* ASV7 */ + {0, 1012500, 1012500, 937500, 937500, 887500, 875000}, /* ASV8 */ + {0, 1012500, 1012500, 937500, 937500, 887500, 875000}, /* ASV9 */ + {0, 1012500, 1012500, 937500, 937500, 887500, 875000}, /* ASV10 */ + {0, 1000000, 1000000, 912500, 912500, 875000, 875000}, /* RESERVED */ +}; + static unsigned int exynos4x12_timingrow[LV_END] = { 0x34498691, 0x34498691, 0x24488490, 0x24488490, 0x154882D0, 0x154882D0, 0x0D488210 }; @@ -430,12 +522,25 @@ static void exynos4x12_set_bus_volt(void) if (asv_group_index == 0xff) asv_group_index = 0; + if ((is_special_flag() >> MIF_LOCK_FLAG) & 0x1) + mif_locking = true; + + if ((is_special_flag() >> INT_LOCK_FLAG) & 0x1) + int_locking = true; + printk(KERN_INFO "DVFS : VDD_INT Voltage table set with %d Group\n", asv_group_index); - for (i = 0 ; i < LV_END ; i++) + for (i = 0 ; i < LV_END ; i++) { exynos4_busfreq_table[i].volt = exynos4_mif_volt[asv_group_index][i]; + if (mif_locking) + exynos4_busfreq_table[i].volt += 50000; + + if (int_locking) + exynos4_int_volt[asv_group_index][i] += 25000; + } + return; } @@ -561,6 +666,11 @@ void exynos4x12_target(int index) tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); } while (tmp & 0x1111); + /* if pega-prime, ABB value is not changed */ + if (samsung_rev() >= EXYNOS4412_REV_2_0) + return; + + /* ABB value is changed in below case */ if (soc_is_exynos4412() && (exynos_result_of_asv > 3)) { if (index == LV_6) { /* MIF:100 / INT:100 */ exynos4x12_set_abb_member(ABB_INT, ABB_MODE_100V); @@ -842,14 +952,37 @@ int exynos4x12_init(struct device *dev, struct busfreq_data *data) struct clk *sclk_dmc; int ret; + if (soc_is_exynos4412() && samsung_rev() >= EXYNOS4412_REV_2_0) { + exynos4_busfreq_table = exynos4_busfreq_table_rev2; + exynos4_qos_value = exynos4_qos_value_rev2; + } else { + exynos4_busfreq_table = exynos4_busfreq_table_orig; + exynos4_qos_value = exynos4_qos_value_orig; + } + if (soc_is_exynos4212()) { exynos4_mif_volt = exynos4212_mif_volt; exynos4_int_volt = exynos4212_int_volt; dmc_max_threshold = EXYNOS4212_DMC_MAX_THRESHOLD; } else if (soc_is_exynos4412()) { - exynos4_mif_volt = exynos4412_mif_volt; - exynos4_int_volt = exynos4412_int_volt; - dmc_max_threshold = EXYNOS4412_DMC_MAX_THRESHOLD; +#ifdef CONFIG_EXYNOS4X12_1000MHZ_SUPPORT + exynos4_mif_volt = exynos4412_1ghz_mif_volt; + exynos4_int_volt = exynos4412_1ghz_int_volt; +#else + if (samsung_rev() >= EXYNOS4412_REV_2_0) { + exynos4_mif_volt = exynos4412_mif_volt_rev2; + exynos4_int_volt = exynos4412_int_volt_rev2; + dmc_max_threshold = PRIME_DMC_MAX_THRESHOLD; + } else if (exynos_armclk_max == 1000000) { + exynos4_mif_volt = exynos4412_1ghz_mif_volt; + exynos4_int_volt = exynos4412_1ghz_int_volt; + dmc_max_threshold = EXYNOS4412_DMC_MAX_THRESHOLD; + } else { + exynos4_mif_volt = exynos4412_mif_volt; + exynos4_int_volt = exynos4412_int_volt; + dmc_max_threshold = EXYNOS4412_DMC_MAX_THRESHOLD; + } +#endif } else { pr_err("Unsupported model.\n"); return -EINVAL; @@ -891,8 +1024,12 @@ int exynos4x12_init(struct device *dev, struct busfreq_data *data) } } - /* Disable MIF 267 INT 200 Level */ - /* opp_disable(dev, 267200); */ + if (samsung_rev() >= EXYNOS4412_REV_2_0) { + opp_disable(dev, 440293); + maxfreq = 440220; + } else { + /* opp_disable(dev, 267200); */ + } data->table = exynos4_busfreq_table; data->table_size = LV_END; diff --git a/arch/arm/mach-exynos/busfreq_opp_5250.c b/arch/arm/mach-exynos/busfreq_opp_5250.c deleted file mode 100644 index bcedb46..0000000 --- a/arch/arm/mach-exynos/busfreq_opp_5250.c +++ /dev/null @@ -1,892 +0,0 @@ -/* linux/arch/arm/mach-exynos/busfreq_opp_5250.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS5 - BUS clock frequency scaling support with OPP - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/types.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/regulator/consumer.h> -#include <linux/sysfs.h> -#include <linux/platform_device.h> -#include <linux/device.h> -#include <linux/module.h> -#include <linux/cpu.h> -#include <linux/ktime.h> -#include <linux/tick.h> -#include <linux/kernel_stat.h> -#include <linux/reboot.h> -#include <linux/slab.h> -#include <linux/opp.h> -#include <linux/clk.h> -#include <mach/busfreq_exynos5.h> - -#include <asm/mach-types.h> - -#include <mach/ppmu.h> -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <mach/gpio.h> -#include <mach/regs-mem.h> -#include <mach/dev.h> -#include <mach/asv.h> -#include <mach/regs-pmu-5250.h> - -#include <plat/map-s5p.h> -#include <plat/gpio-cfg.h> -#include <plat/cpu.h> -#include <plat/clock.h> - -#undef BUSFREQ_PROFILE_DEBUG - -#define IDLE_THRESHOLD 4 -#define MIF_R1_THRESHOLD 20 -#define MIF_MAX_THRESHOLD 20 -#define INT_MAX_THRESHOLD 20 -#define INT_RIGHT0_THRESHOLD 25 -#define INT_VIDEOPLAY_LIMIT_FREQ 200000UL -#define INT_RBB 6 /* +300mV */ - -static struct device busfreq_for_int; - -/* To save/restore DREX2_PAUSE_CTRL register */ -static unsigned int drex2_pause_ctrl; - -static struct busfreq_table exynos5_busfreq_table_for800[] = { - {LV_0, 800000, 1000000, 0, 0, 0}, - {LV_1, 400000, 1000000, 0, 0, 0}, - {LV_2, 160000, 1000000, 0, 0, 0}, -}; - -static struct busfreq_table exynos5_busfreq_table_for667[] = { - {LV_0, 667000, 1000000, 0, 0, 0}, - {LV_1, 334000, 1000000, 0, 0, 0}, - {LV_2, 111000, 1000000, 0, 0, 0}, -}; - -static struct busfreq_table exynos5_busfreq_table_for533[] = { - {LV_0, 533000, 1000000, 0, 0, 0}, - {LV_1, 267000, 1000000, 0, 0, 0}, - {LV_2, 107000, 1000000, 0, 0, 0}, -}; - -static struct busfreq_table exynos5_busfreq_table_for400[] = { - {LV_0, 400000, 1000000, 0, 0, 0}, - {LV_1, 267000, 1000000, 0, 0, 0}, - {LV_2, 100000, 1000000, 0, 0, 0}, -}; -#define ASV_GROUP 10 -static unsigned int asv_group_index; - -static unsigned int exynos5_mif_volt_for800[ASV_GROUP+1][LV_MIF_END] = { - /* L0 L1 L2 */ - { 0, 0, 0}, /* ASV0 */ - {1200000, 1000000, 950000}, /* ASV1 */ - {1200000, 1000000, 900000}, /* ASV2 */ - {1200000, 1050000, 950000}, /* ASV3 */ - {1150000, 1000000, 900000}, /* ASV4 */ - {1150000, 1050000, 950000}, /* ASV5 */ - {1150000, 1050000, 950000}, /* ASV6 */ - {1100000, 1000000, 900000}, /* ASV7 */ - {1100000, 1000000, 900000}, /* ASV8 */ - {1100000, 1000000, 900000}, /* ASV9 */ - {1100000, 1000000, 900000}, /* ASV10 */ -}; - -static unsigned int exynos5_mif_volt_for667[ASV_GROUP+1][LV_MIF_END] = { - /* L0 L1 L2 */ - { 0, 0, 0}, /* ASV0 */ - {1100000, 1000000, 950000}, /* ASV1 */ - {1050000, 1000000, 950000}, /* ASV2 */ - {1050000, 1050000, 950000}, /* ASV3 */ - {1050000, 1000000, 950000}, /* ASV4 */ - {1050000, 1050000, 1000000}, /* ASV5 */ - {1050000, 1050000, 950000}, /* ASV6 */ - {1050000, 1000000, 900000}, /* ASV7 */ - {1050000, 1000000, 900000}, /* ASV8 */ - {1050000, 1000000, 900000}, /* ASV9 */ - {1050000, 1000000, 900000}, /* ASV10 */ -}; - -static unsigned int exynos5_mif_volt_for533[ASV_GROUP+1][LV_MIF_END] = { - /* L0 L1 L2 */ - { 0, 0, 0}, /* ASV0 */ - {1050000, 1000000, 950000}, /* ASV1 */ - {1000000, 950000, 950000}, /* ASV2 */ - {1050000, 1000000, 950000}, /* ASV3 */ - {1000000, 950000, 950000}, /* ASV4 */ - {1050000, 1000000, 1000000}, /* ASV5 */ - {1050000, 950000, 950000}, /* ASV6 */ - {1000000, 950000, 900000}, /* ASV7 */ - {1000000, 950000, 900000}, /* ASV8 */ - {1000000, 950000, 900000}, /* ASV9 */ - {1000000, 950000, 900000}, /* ASV10 */ -}; - -static unsigned int exynos5_mif_volt_for400[ASV_GROUP+1][LV_MIF_END] = { - /* L0 L1 L2 */ - { 0, 0, 0}, /* ASV0 */ - {1000000, 1000000, 950000}, /* ASV1 */ - {1000000, 950000, 900000}, /* ASV2 */ - {1050000, 1000000, 950000}, /* ASV3 */ - {1000000, 950000, 900000}, /* ASV4 */ - {1050000, 1000000, 950000}, /* ASV5 */ - {1050000, 950000, 950000}, /* ASV6 */ - {1000000, 950000, 900000}, /* ASV7 */ - {1000000, 950000, 900000}, /* ASV8 */ - {1000000, 950000, 900000}, /* ASV9 */ - {1000000, 950000, 900000}, /* ASV10 */ -}; - -static struct busfreq_table *exynos5_busfreq_table_mif; - -static unsigned int (*exynos5_mif_volt)[LV_MIF_END]; - -static struct busfreq_table exynos5_busfreq_table_int[] = { - {LV_0, 267000, 1000000, 0, 0, 0}, - {LV_1, 200000, 1000000, 0, 0, 0}, - {LV_2, 160000, 1000000, 0, 0, 0}, - {LV_3, 133000, 1000000, 0, 0, 0}, -}; - -static unsigned int exynos5_int_volt[ASV_GROUP+1][LV_INT_END] = { - /* L0 L1 L2 L3 */ - { 0, 0, 0, 0}, /* ASV0 */ - {1025000, 987500, 975000, 950000}, /* ASV1 */ - {1012500, 975000, 962500, 937500}, /* ASV2 */ - {1012500, 987500, 975000, 950000}, /* ASV3 */ - {1000000, 975000, 962500, 937500}, /* ASV4 */ - {1012500, 987500, 975000, 950000}, /* ASV5 */ - {1000000, 975000, 962500, 937500}, /* ASV6 */ - { 987500, 962500, 950000, 925000}, /* ASV7 */ - { 975000, 950000, 937500, 912500}, /* ASV8 */ - { 962500, 937500, 925000, 900000}, /* ASV9 */ - { 962500, 937500, 925000, 900000}, /* ASV10 */ -}; - - -/* For CMU_LEX */ -static unsigned int clkdiv_lex[LV_INT_END][2] = { - /* - * Clock divider value for following - * { DIVATCLK_LEX, DIVPCLK_LEX } - */ - - /* ATCLK_LEX L0 : 200MHz */ - {0, 1}, - - /* ATCLK_LEX L1 : 166MHz */ - {0, 1}, - - /* ATCLK_LEX L2 : 133MHz */ - {0, 1}, - - /* ATCLK_LEX L3 : 114MHz */ - {0, 1}, -}; - -/* For CMU_R0X */ -static unsigned int clkdiv_r0x[LV_INT_END][1] = { - /* - * Clock divider value for following - * { DIVPCLK_R0X } - */ - - /* ACLK_PR0X L0 : 133MHz */ - {1}, - - /* ACLK_DR0X L1 : 100MHz */ - {1}, - - /* ACLK_PR0X L2 : 80MHz */ - {1}, - - /* ACLK_PR0X L3 : 67MHz */ - {1}, -}; - -/* For CMU_R1X */ -static unsigned int clkdiv_r1x[LV_INT_END][1] = { - /* - * Clock divider value for following - * { DIVPCLK_R1X } - */ - - /* ACLK_PR1X L0 : 133MHz */ - {1}, - - /* ACLK_DR1X L1 : 100MHz */ - {1}, - - /* ACLK_PR1X L2 : 80MHz */ - {1}, - - /* ACLK_PR1X L3 : 67MHz */ - {1}, -}; - -/* For CMU_TOP */ -static unsigned int clkdiv_top[LV_INT_END][10] = { - /* - * Clock divider value for following - * { DIVACLK400_ISP, DIVACLK400_IOP, DIVACLK266, DIVACLK_200, DIVACLK_66_PRE, - DIVACLK_66, DIVACLK_333, DIVACLK_166, DIVACLK_300_DISP1, DIVACLK300_GSCL } - */ - - /* ACLK_400_ISP L0 : 400MHz */ - {1, 1, 2, 3, 1, 5, 0, 1, 2, 2}, - - /* ACLK_400_ISP L1 : 267MHz */ - {2, 3, 3, 4, 1, 5, 1, 2, 2, 2}, - - /* ACLK_400_ISP L2 : 200MHz */ - {3, 3, 4, 4, 1, 5, 2, 3, 2, 2}, - - /* ACLK_400_ISP L3 : 160MHz */ - {4, 4, 5, 5, 1, 5, 2, 3, 5, 5}, -}; - -/* For CMU_CDREX */ -static unsigned int clkdiv_cdrex_for800[LV_MIF_END][9] = { - /* - * Clock divider value for following - * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX, - DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON } - */ - - /* MCLK_CDREX L0: 800MHz */ - {0, 0, 1, 0, 5, 1, 1, 4, 1}, - - /* MCLK_CDREX L1: 400MHz */ - {0, 1, 1, 1, 3, 2, 1, 5, 1}, - - /* MCLK_CDREX L2: 100MHz */ - {0, 4, 1, 1, 7, 7, 1, 15, 1}, -}; - -static unsigned int clkdiv_cdrex_for667[LV_MIF_END][9] = { - /* - * Clock divider value for following - * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX, - DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON } - */ - - /* MCLK_CDREX L0: 667MHz */ - {0, 0, 1, 0, 4, 1, 1, 4, 1}, - - /* MCLK_CDREX L1: 334MHz */ - {0, 1, 1, 1, 4, 2, 1, 5, 1}, - - /* MCLK_CDREX L2: 111MHz */ - {0, 5, 1, 4, 4, 5, 1, 8, 1}, -}; - -static unsigned int clkdiv_cdrex_for533[LV_MIF_END][9] = { - /* - * Clock divider value for following - * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX, - DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON } - */ - - /* MCLK_CDREX L0: 533MHz */ - {0, 0, 1, 0, 3, 1, 1, 4, 1}, - - /* MCLK_CDREX L1: 267MHz */ - {0, 1, 1, 1, 3, 2, 1, 5, 1}, - - /* MCLK_CDREX L2: 107MHz */ - {0, 4, 1, 4, 3, 5, 1, 8, 1}, -}; - -static unsigned int __maybe_unused clkdiv_cdrex_for400[LV_MIF_END][9] = { - /* - * Clock divider value for following - * { DIVMCLK_DPHY, DIVMCLK_CDREX2, DIVACLK_CDREX, DIVMCLK_CDREX, - DIVPCLK_CDREX, DIVC2C, DIVC2C_ACLK, DIVMCLK_EFPHY, DIVACLK_EFCON } - */ - - /* MCLK_CDREX L0: 400MHz */ - {1, 1, 1, 0, 5, 1, 1, 4, 1}, - - /* MCLK_CDREX L1: 267MHz */ - {1, 2, 1, 2, 2, 2, 1, 5, 1}, - - /* MCLK_CDREX L2: 100MHz */ - {1, 7, 1, 2, 7, 7, 1, 15, 1}, -}; - -static unsigned int (*clkdiv_cdrex)[9]; - -static void exynos5250_set_bus_volt(void) -{ - unsigned int i; - - if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0) - asv_group_index = 0; - else - asv_group_index = exynos_result_of_asv; - - if (asv_group_index == 0xff) - asv_group_index = 0; - - printk(KERN_INFO "DVFS : VDD_INT Voltage table set with %d Group\n", asv_group_index); - printk(KERN_INFO "DVFS : VDD_INT Voltage of L0 level is %d \n", exynos5_mif_volt[asv_group_index][0]); - - for (i = LV_0; i < LV_MIF_END; i++) - exynos5_busfreq_table_mif[i].volt = - exynos5_mif_volt[asv_group_index][i]; - - for (i = LV_0; i < LV_INT_END; i++) - exynos5_busfreq_table_int[i].volt = - exynos5_int_volt[asv_group_index][i]; - return; -} - -static void exynos5250_target_for_mif(struct busfreq_data *data, int div_index) -{ - unsigned int tmp; - - /* Change Divider - CDREX */ - tmp = data->cdrex_divtable[div_index]; - - __raw_writel(tmp, EXYNOS5_CLKDIV_CDREX); - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX); - } while (tmp & 0x11111111); - } else { - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX); - } while (tmp & 0x11110011); \ - } - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - tmp = data->cdrex2_divtable[div_index]; - - __raw_writel(tmp, EXYNOS5_CLKDIV_CDREX2); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX2); - } while (tmp & 0x1); - } -} - -static void exynos5250_target_for_int(struct busfreq_data *data, int div_index) -{ - unsigned int tmp; - unsigned int tmp2; - - /* Change Divider - TOP */ - tmp = __raw_readl(EXYNOS5_CLKDIV_TOP0); - - tmp &= ~(EXYNOS5_CLKDIV_TOP0_ACLK266_MASK | - EXYNOS5_CLKDIV_TOP0_ACLK200_MASK | - EXYNOS5_CLKDIV_TOP0_ACLK66_MASK | - EXYNOS5_CLKDIV_TOP0_ACLK333_MASK | - EXYNOS5_CLKDIV_TOP0_ACLK166_MASK | - EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK); - - tmp |= ((clkdiv_top[div_index][2] << EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT) | - (clkdiv_top[div_index][3] << EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT) | - (clkdiv_top[div_index][5] << EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT) | - (clkdiv_top[div_index][6] << EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT) | - (clkdiv_top[div_index][7] << EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT) | - (clkdiv_top[div_index][8] << EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT)); - - __raw_writel(tmp, EXYNOS5_CLKDIV_TOP0); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_TOP0); - } while (tmp & 0x151101); - - tmp = __raw_readl(EXYNOS5_CLKDIV_TOP1); - - tmp &= ~(EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK | - EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK | - EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK | - EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK); - - tmp |= ((clkdiv_top[div_index][0] << EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT) | - (clkdiv_top[div_index][1] << EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT) | - (clkdiv_top[div_index][4] << EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT) | - (clkdiv_top[div_index][9] << EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT)); - - - __raw_writel(tmp, EXYNOS5_CLKDIV_TOP1); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_TOP1); - tmp2 = __raw_readl(EXYNOS5_CLKDIV_STAT_TOP0); - } while ((tmp & 0x1110000) && (tmp2 & 0x80000)); - - /* Change Divider - LEX */ - tmp = data->lex_divtable[div_index]; - - __raw_writel(tmp, EXYNOS5_CLKDIV_LEX); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_LEX); - } while (tmp & 0x110); - - /* Change Divider - R0X */ - tmp = __raw_readl(EXYNOS5_CLKDIV_R0X); - - tmp &= ~EXYNOS5_CLKDIV_R0X_PCLK_R0X_MASK; - - tmp |= (clkdiv_r0x[div_index][0] << EXYNOS5_CLKDIV_R0X_PCLK_R0X_SHIFT); - - __raw_writel(tmp, EXYNOS5_CLKDIV_R0X); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_R0X); - } while (tmp & 0x10); - - /* Change Divider - R1X */ - tmp = data->r1x_divtable[div_index]; - - __raw_writel(tmp, EXYNOS5_CLKDIV_R1X); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_R1X); - } while (tmp & 0x10); -} - -static void exynos5250_target(struct busfreq_data *data, enum ppmu_type type, - int index) -{ - if (type == PPMU_MIF) - exynos5250_target_for_mif(data, index); - else - exynos5250_target_for_int(data, index); -} - -static int exynos5250_get_table_index(unsigned long freq, enum ppmu_type type) -{ - int index; - - if (type == PPMU_MIF) { - for (index = LV_0; index < LV_MIF_END; index++) - if (freq == exynos5_busfreq_table_mif[index].mem_clk) - return index; - } else { - for (index = LV_0; index < LV_INT_END; index++) - if (freq == exynos5_busfreq_table_int[index].mem_clk) - return index; - } - return -EINVAL; -} - -static void exynos5250_suspend(void) -{ - /* Nothing to do */ -} - -static void exynos5250_resume(void) -{ - __raw_writel(drex2_pause_ctrl, EXYNOS5_DREX2_PAUSE); -} - -static void exynos5250_monitor(struct busfreq_data *data, - struct opp **mif_opp, struct opp **int_opp) -{ - int i; - unsigned int cpu_load_average = 0; - unsigned int ddr_c_load_average = 0; - unsigned int ddr_l_load_average = 0; - unsigned int ddr_r1_load_average = 0; - unsigned int right0_load_average = 0; - unsigned int ddr_load_average; - unsigned long cpufreq = 0; - unsigned long freq_int_right0 = 0; - unsigned long lockfreq[PPMU_TYPE_END]; - unsigned long freq[PPMU_TYPE_END]; - unsigned long cpu_load; - unsigned long ddr_load=0; - unsigned long ddr_load_int=0; - unsigned long ddr_c_load; - unsigned long ddr_r1_load; - unsigned long ddr_l_load; - unsigned long right0_load; - struct opp *opp[PPMU_TYPE_END]; - unsigned long newfreq[PPMU_TYPE_END]; - - ppmu_update(data->dev[PPMU_MIF], 3); - - /* Convert from base xxx to base maxfreq */ - cpu_load = div64_u64(ppmu_load[PPMU_CPU] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]); - ddr_c_load = div64_u64(ppmu_load[PPMU_DDR_C] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]); - ddr_r1_load = div64_u64(ppmu_load[PPMU_DDR_R1] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]); - ddr_l_load = div64_u64(ppmu_load[PPMU_DDR_L] * data->curr_freq[PPMU_MIF], data->max_freq[PPMU_MIF]); - right0_load = div64_u64(ppmu_load[PPMU_RIGHT0_BUS] * data->curr_freq[PPMU_INT], data->max_freq[PPMU_INT]); - - data->load_history[PPMU_CPU][data->index] = cpu_load; - data->load_history[PPMU_DDR_C][data->index] = ddr_c_load; - data->load_history[PPMU_DDR_R1][data->index] = ddr_r1_load; - data->load_history[PPMU_DDR_L][data->index] = ddr_l_load; - data->load_history[PPMU_RIGHT0_BUS][data->index++] = right0_load; - - if (data->index >= LOAD_HISTORY_SIZE) - data->index = 0; - - for (i = 0; i < LOAD_HISTORY_SIZE; i++) { - cpu_load_average += data->load_history[PPMU_CPU][i]; - ddr_c_load_average += data->load_history[PPMU_DDR_C][i]; - ddr_r1_load_average += data->load_history[PPMU_DDR_R1][i]; - ddr_l_load_average += data->load_history[PPMU_DDR_L][i]; - right0_load_average += data->load_history[PPMU_RIGHT0_BUS][i]; - } - - /* Calculate average Load */ - cpu_load_average /= LOAD_HISTORY_SIZE; - ddr_c_load_average /= LOAD_HISTORY_SIZE; - ddr_r1_load_average /= LOAD_HISTORY_SIZE; - ddr_l_load_average /= LOAD_HISTORY_SIZE; - right0_load_average /= LOAD_HISTORY_SIZE; - - if (ddr_c_load >= ddr_l_load) { - ddr_load = ddr_c_load; - ddr_load_average = ddr_c_load_average; - } else { - ddr_load = ddr_l_load; - ddr_load_average = ddr_l_load_average; - } - - ddr_load_int = ddr_load; - - //Calculate MIF/INT frequency level - if (ddr_r1_load >= MIF_R1_THRESHOLD) { - freq[PPMU_MIF] = data->max_freq[PPMU_MIF]; - if (right0_load >= INT_RIGHT0_THRESHOLD) { - freq[PPMU_INT] = data->max_freq[PPMU_INT]; - goto go_max; - } else { - freq_int_right0 = div64_u64(data->max_freq[PPMU_INT] * right0_load, INT_RIGHT0_THRESHOLD); - } - } else { - // Caculate next MIF frequency - if (ddr_load >= MIF_MAX_THRESHOLD) { - freq[PPMU_MIF] = data->max_freq[PPMU_MIF]; - } else if ( ddr_load < IDLE_THRESHOLD) { - if (ddr_load_average < IDLE_THRESHOLD) - freq[PPMU_MIF] = step_down(data, PPMU_MIF, 1); - else - freq[PPMU_MIF] = data->curr_freq[PPMU_MIF]; - } else { - if (ddr_load < ddr_load_average) { - ddr_load = ddr_load_average; - if (ddr_load >= MIF_MAX_THRESHOLD) - ddr_load = MIF_MAX_THRESHOLD; - } - freq[PPMU_MIF] = div64_u64(data->max_freq[PPMU_MIF] * ddr_load, MIF_MAX_THRESHOLD); - } - - freq_int_right0 = div64_u64(data->max_freq[PPMU_INT] * right0_load, INT_RIGHT0_THRESHOLD); - } - - // Caculate next INT frequency - if (ddr_load_int >= INT_MAX_THRESHOLD) { - freq[PPMU_INT] = data->max_freq[PPMU_INT]; - } else if ( ddr_load_int < IDLE_THRESHOLD) { - if (ddr_load_average < IDLE_THRESHOLD) - freq[PPMU_INT] = step_down(data, PPMU_INT, 1); - else - freq[PPMU_INT] = data->curr_freq[PPMU_INT]; - } else { - if (ddr_load_int < ddr_load_average) { - ddr_load_int = ddr_load_average; - if (ddr_load_int >= INT_MAX_THRESHOLD) - ddr_load_int = INT_MAX_THRESHOLD; - } - freq[PPMU_INT] = div64_u64(data->max_freq[PPMU_INT] * ddr_load_int, INT_MAX_THRESHOLD); - } - - freq[PPMU_INT] = max(freq[PPMU_INT], freq_int_right0); - - if (freq[PPMU_INT] == data->max_freq[PPMU_INT]) - freq[PPMU_MIF] = data->max_freq[PPMU_MIF]; - -go_max: -#ifdef BUSFREQ_PROFILE_DEBUG - printk(KERN_DEBUG "cpu[%ld] l[%ld] c[%ld] r1[%ld] rt[%ld] m_load[%ld] i_load[%ld]\n", - cpu_load, ddr_l_load, ddr_c_load, ddr_r1_load, right0_load, ddr_load, ddr_load_int); -#endif - lockfreq[PPMU_MIF] = (dev_max_freq(data->dev[PPMU_MIF])/1000)*1000; - lockfreq[PPMU_INT] = (dev_max_freq(data->dev[PPMU_MIF])%1000)*1000; -#ifdef BUSFREQ_PROFILE_DEBUG - printk(KERN_DEBUG "i_cf[%ld] m_cf[%ld] i_nf[%ld] m_nf[%ld] lock_Mfreq[%ld] lock_Ifreq[%ld]\n", - data->curr_freq[PPMU_INT],data->curr_freq[PPMU_MIF],freq[PPMU_INT], freq[PPMU_MIF], lockfreq[PPMU_MIF], lockfreq[PPMU_INT]); -#endif - newfreq[PPMU_MIF] = max(lockfreq[PPMU_MIF], freq[PPMU_MIF]); - newfreq[PPMU_INT] = max(lockfreq[PPMU_INT], freq[PPMU_INT]); - opp[PPMU_MIF] = opp_find_freq_ceil(data->dev[PPMU_MIF], &newfreq[PPMU_MIF]); - opp[PPMU_INT] = opp_find_freq_ceil(data->dev[PPMU_INT], &newfreq[PPMU_INT]); - - *mif_opp = opp[PPMU_MIF]; - *int_opp = opp[PPMU_INT]; -} - -static void busfreq_early_suspend(struct early_suspend *h) -{ - unsigned long freq; - struct busfreq_data *data = container_of(h, struct busfreq_data, - busfreq_early_suspend_handler); - freq = data->min_freq[PPMU_MIF] + data->min_freq[PPMU_INT] / 1000; - //dev_lock(data->dev[PPMU_MIF], data->dev[PPMU_MIF], freq); - dev_unlock(data->dev[PPMU_MIF], data->dev[PPMU_MIF]); -} - -static void busfreq_late_resume(struct early_suspend *h) -{ - struct busfreq_data *data = container_of(h, struct busfreq_data, - busfreq_early_suspend_handler); - /* Request min MIF/INT 300MHz */ - dev_lock(data->dev[PPMU_MIF], data->dev[PPMU_MIF], 300150); -} - -int exynos5250_init(struct device *dev, struct busfreq_data *data) -{ - unsigned int i, tmp; - unsigned long maxfreq = ULONG_MAX; - unsigned long minfreq = 0; - unsigned long cdrexfreq; - unsigned long lrbusfreq; - struct clk *clk; - int ret; - - /* Enable pause function for DREX2 DVFS */ - drex2_pause_ctrl = __raw_readl(EXYNOS5_DREX2_PAUSE); - drex2_pause_ctrl |= DMC_PAUSE_ENABLE; - __raw_writel(drex2_pause_ctrl, EXYNOS5_DREX2_PAUSE); - - clk = clk_get(NULL, "mclk_cdrex"); - if (IS_ERR(clk)) { - dev_err(dev, "Fail to get mclk_cdrex clock"); - ret = PTR_ERR(clk); - return ret; - } - cdrexfreq = clk_get_rate(clk) / 1000; - clk_put(clk); - - clk = clk_get(NULL, "aclk_266"); - if (IS_ERR(clk)) { - dev_err(dev, "Fail to get aclk_266 clock"); - ret = PTR_ERR(clk); - return ret; - } - lrbusfreq = clk_get_rate(clk) / 1000; - clk_put(clk); - - if (cdrexfreq == 800000) { - clkdiv_cdrex = clkdiv_cdrex_for800; - exynos5_busfreq_table_mif = exynos5_busfreq_table_for800; - exynos5_mif_volt = exynos5_mif_volt_for800; - } else if (cdrexfreq == 666857) { - clkdiv_cdrex = clkdiv_cdrex_for667; - exynos5_busfreq_table_mif = exynos5_busfreq_table_for667; - exynos5_mif_volt = exynos5_mif_volt_for667; - } else if (cdrexfreq == 533000) { - clkdiv_cdrex = clkdiv_cdrex_for533; - exynos5_busfreq_table_mif = exynos5_busfreq_table_for533; - exynos5_mif_volt = exynos5_mif_volt_for533; - } else if (cdrexfreq == 400000) { - clkdiv_cdrex = clkdiv_cdrex_for400; - exynos5_busfreq_table_mif = exynos5_busfreq_table_for400; - exynos5_mif_volt = exynos5_mif_volt_for400; - } else { - dev_err(dev, "Don't support cdrex table\n"); - return -EINVAL; - } - - tmp = __raw_readl(EXYNOS5_CLKDIV_LEX); - - for (i = LV_0; i < LV_INT_END; i++) { - tmp &= ~(EXYNOS5_CLKDIV_LEX_ATCLK_LEX_MASK | EXYNOS5_CLKDIV_LEX_PCLK_LEX_MASK); - - tmp |= ((clkdiv_lex[i][0] << EXYNOS5_CLKDIV_LEX_ATCLK_LEX_SHIFT) | - (clkdiv_lex[i][1] << EXYNOS5_CLKDIV_LEX_PCLK_LEX_SHIFT)); - - data->lex_divtable[i] = tmp; - } - - tmp = __raw_readl(EXYNOS5_CLKDIV_R0X); - - for (i = LV_0; i < LV_INT_END; i++) { - - tmp &= ~EXYNOS5_CLKDIV_R0X_PCLK_R0X_MASK; - - tmp |= (clkdiv_r0x[i][0] << EXYNOS5_CLKDIV_R0X_PCLK_R0X_SHIFT); - - data->r0x_divtable[i] = tmp; - } - - tmp = __raw_readl(EXYNOS5_CLKDIV_R1X); - - for (i = LV_0; i < LV_INT_END; i++) { - tmp &= ~EXYNOS5_CLKDIV_R1X_PCLK_R1X_MASK; - - tmp |= (clkdiv_r1x[i][0] << EXYNOS5_CLKDIV_R1X_PCLK_R1X_SHIFT); - - data->r1x_divtable[i] = tmp; - } - - tmp = __raw_readl(EXYNOS5_CLKDIV_CDREX); - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - for (i = LV_0; i < LV_MIF_END; i++) { - tmp &= ~(EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_MASK | - EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_MASK | - EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_MASK | - EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_MASK | - EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_MASK | - EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_MASK | - EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_MASK | - EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_MASK); - - tmp |= ((clkdiv_cdrex[i][0] << EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT) | - (clkdiv_cdrex[i][1] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT) | - (clkdiv_cdrex[i][2] << EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT) | - (clkdiv_cdrex[i][3] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT) | - (clkdiv_cdrex[i][4] << EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT) | - (clkdiv_cdrex[i][5] << EXYNOS5_CLKDIV_CDREX_ACLK_CLK400_SHIFT) | - (clkdiv_cdrex[i][6] << EXYNOS5_CLKDIV_CDREX_ACLK_C2C200_SHIFT) | - (clkdiv_cdrex[i][8] << EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT)); - - data->cdrex_divtable[i] = tmp; - } - } else { - for (i = LV_0; i < LV_MIF_END; i++) { - tmp &= ~(EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_MASK | - EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_MASK | - EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_MASK | - EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_MASK | - EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_MASK | - EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_MASK); - - tmp |= ((clkdiv_cdrex[i][0] << EXYNOS5_CLKDIV_CDREX_MCLK_DPHY_SHIFT) | - (clkdiv_cdrex[i][1] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX2_SHIFT) | - (clkdiv_cdrex[i][2] << EXYNOS5_CLKDIV_CDREX_ACLK_CDREX_SHIFT) | - (clkdiv_cdrex[i][3] << EXYNOS5_CLKDIV_CDREX_MCLK_CDREX_SHIFT) | - (clkdiv_cdrex[i][4] << EXYNOS5_CLKDIV_CDREX_PCLK_CDREX_SHIFT) | - (clkdiv_cdrex[i][8] << EXYNOS5_CLKDIV_CDREX_ACLK_EFCON_SHIFT)); - - data->cdrex_divtable[i] = tmp; - } - } - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - tmp = __raw_readl(EXYNOS5_CLKDIV_CDREX2); - - for (i = LV_0; i < LV_MIF_END; i++) { - tmp &= ~EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_MASK; - - tmp |= clkdiv_cdrex[i][7] << EXYNOS5_CLKDIV_CDREX2_MCLK_EFPHY_SHIFT; - - data->cdrex2_divtable[i] = tmp; - - } - } - - exynos5250_set_bus_volt(); - - data->dev[PPMU_MIF] = dev; - data->dev[PPMU_INT] = &busfreq_for_int; - - for (i = LV_0; i < LV_MIF_END; i++) { - ret = opp_add(data->dev[PPMU_MIF], exynos5_busfreq_table_mif[i].mem_clk, - exynos5_busfreq_table_mif[i].volt); - if (ret) { - dev_err(dev, "Fail to add opp entries.\n"); - return ret; - } - } - -#if defined(CONFIG_DP_60HZ_P11) || defined(CONFIG_DP_60HZ_P10) - if (cdrexfreq == 666857) { - opp_disable(data->dev[PPMU_MIF], 334000); - opp_disable(data->dev[PPMU_MIF], 110000); - } else if (cdrexfreq == 533000) { - opp_disable(data->dev[PPMU_MIF], 267000); - opp_disable(data->dev[PPMU_MIF], 107000); - } else if (cdrexfreq == 400000) { - opp_disable(data->dev[PPMU_MIF], 267000); - opp_disable(data->dev[PPMU_MIF], 100000); - } -#endif - - for (i = LV_0; i < LV_INT_END; i++) { - ret = opp_add(data->dev[PPMU_INT], exynos5_busfreq_table_int[i].mem_clk, - exynos5_busfreq_table_int[i].volt); - if (ret) { - dev_err(dev, "Fail to add opp entries.\n"); - return ret; - } - } - - data->target = exynos5250_target; - data->get_table_index = exynos5250_get_table_index; - data->monitor = exynos5250_monitor; - data->busfreq_suspend = exynos5250_suspend; - data->busfreq_resume = exynos5250_resume; - data->sampling_rate = usecs_to_jiffies(100000); - - data->table[PPMU_MIF] = exynos5_busfreq_table_mif; - data->table[PPMU_INT] = exynos5_busfreq_table_int; - - /* Find max frequency for mif */ - data->max_freq[PPMU_MIF] = - opp_get_freq(opp_find_freq_floor(data->dev[PPMU_MIF], &maxfreq)); - data->min_freq[PPMU_MIF] = - opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &minfreq)); - data->curr_freq[PPMU_MIF] = - opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_MIF], &cdrexfreq)); - /* Find max frequency for int */ - maxfreq = ULONG_MAX; - minfreq = 0; - data->max_freq[PPMU_INT] = - opp_get_freq(opp_find_freq_floor(data->dev[PPMU_INT], &maxfreq)); - data->min_freq[PPMU_INT] = - opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &minfreq)); - data->curr_freq[PPMU_INT] = - opp_get_freq(opp_find_freq_ceil(data->dev[PPMU_INT], &lrbusfreq)); - - data->vdd_reg[PPMU_INT] = regulator_get(NULL, "vdd_int"); - if (IS_ERR(data->vdd_reg[PPMU_INT])) { - pr_err("failed to get resource %s\n", "vdd_int"); - return -ENODEV; - } - - data->vdd_reg[PPMU_MIF] = regulator_get(NULL, "vdd_mif"); - if (IS_ERR(data->vdd_reg[PPMU_MIF])) { - pr_err("failed to get resource %s\n", "vdd_mif"); - regulator_put(data->vdd_reg[PPMU_INT]); - return -ENODEV; - } - - data->busfreq_early_suspend_handler.suspend = &busfreq_early_suspend; - data->busfreq_early_suspend_handler.resume = &busfreq_late_resume; - - data->busfreq_early_suspend_handler.suspend = &busfreq_early_suspend; - data->busfreq_early_suspend_handler.resume = &busfreq_late_resume; - - /* Request min 300MHz for MIF and 150MHz for INT*/ - dev_lock(dev, dev, 300150); - - register_early_suspend(&data->busfreq_early_suspend_handler); - - tmp = __raw_readl(EXYNOS5_ABBG_INT_CONTROL); - tmp &= ~(0x1f | (1 << 31) | (1 << 7)); - tmp |= ((8 + INT_RBB) | (1 << 31) | (1 << 7)); - __raw_writel(tmp, EXYNOS5_ABBG_INT_CONTROL); - - return 0; -} diff --git a/arch/arm/mach-exynos/busfreq_opp_exynos5.c b/arch/arm/mach-exynos/busfreq_opp_exynos5.c deleted file mode 100644 index b685cd2..0000000 --- a/arch/arm/mach-exynos/busfreq_opp_exynos5.c +++ /dev/null @@ -1,498 +0,0 @@ -/* linux/arch/arm/mach-exynos/busfreq_opp_exynos5.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS4 - BUS clock frequency scaling support with OPP - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/types.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/regulator/consumer.h> -#include <linux/sysfs.h> -#include <linux/platform_device.h> -#include <linux/device.h> -#include <linux/module.h> -#include <linux/cpu.h> -#include <linux/ktime.h> -#include <linux/tick.h> -#include <linux/kernel_stat.h> -#include <linux/suspend.h> -#include <linux/reboot.h> -#include <linux/slab.h> -#include <linux/opp.h> -#include <linux/clk.h> -#include <linux/workqueue.h> - -#include <asm/mach-types.h> - -#include <mach/ppmu.h> -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <mach/gpio.h> -#include <mach/regs-mem.h> -#include <mach/cpufreq.h> -#include <mach/dev.h> -#include <mach/busfreq_exynos5.h> - -#include <plat/map-s5p.h> -#include <plat/cpu.h> -#include <plat/clock.h> - -#define BUSFREQ_DEBUG 1 - -static DEFINE_MUTEX(busfreq_lock); -BLOCKING_NOTIFIER_HEAD(exynos_busfreq_notifier_list); - -struct busfreq_control { - struct opp *lock[PPMU_TYPE_END]; - struct device *dev[PPMU_TYPE_END]; -}; - -static struct busfreq_control bus_ctrl; - -void update_busfreq_stat(struct busfreq_data *data, - enum ppmu_type type, unsigned int index) -{ -#ifdef BUSFREQ_DEBUG - unsigned long long cur_time = get_jiffies_64(); - data->time_in_state[type][index] = - cputime64_add(data->time_in_state[type][index], cputime_sub(cur_time, data->last_time[type])); - data->last_time[type] = cur_time; -#endif -} - - -static unsigned long __maybe_unused step_up(struct busfreq_data *data, - enum ppmu_type type, int step) -{ - int i; - struct opp *opp; - unsigned long newfreq = data->curr_freq[type]; - - if (data->max_freq[type] == data->curr_freq[type]) - return newfreq; - - for (i = 0; i < step; i++) { - newfreq += 1; - opp = opp_find_freq_ceil(data->dev[type], &newfreq); - - if (opp_get_freq(opp) == data->max_freq[type]) - break; - } - - return newfreq; -} - -unsigned long step_down(struct busfreq_data *data, - enum ppmu_type type, int step) -{ - int i; - struct opp *opp; - unsigned long newfreq = data->curr_freq[type]; - - if (data->min_freq[type] == data->curr_freq[type]) - return newfreq; - - for (i = 0; i < step; i++) { - newfreq -= 1; - opp = opp_find_freq_floor(data->dev[type], &newfreq); - - if (opp_get_freq(opp) == data->min_freq[type]) - break; - } - - return newfreq; -} - -static void _target(struct busfreq_data *data, - enum ppmu_type type, unsigned long newfreq) -{ - struct opp *opp; - unsigned int voltage; - int index; - - opp = opp_find_freq_exact(data->dev[type], newfreq, true); - - if (bus_ctrl.lock[type]) { - opp = bus_ctrl.lock[type]; - newfreq = opp_get_freq(opp); - } - - index = data->get_table_index(newfreq, type); - - if (newfreq == 0 || newfreq == data->curr_freq[type] || - data->use == false) { - update_busfreq_stat(data, type, index); - return; - } - - voltage = opp_get_voltage(opp); - - if (newfreq > data->curr_freq[type]) { - regulator_set_voltage(data->vdd_reg[type], voltage, - voltage + 25000); - if (type == PPMU_MIF && data->busfreq_prepare) - data->busfreq_prepare(index); - } - - data->target(data, type, index); - - if (newfreq < data->curr_freq[type]) { - if (type == PPMU_MIF && data->busfreq_post) - data->busfreq_post(index); - regulator_set_voltage(data->vdd_reg[type], voltage, - voltage + 25000); - } - data->curr_freq[type] = newfreq; - - update_busfreq_stat(data, type, index); -} - -static void exynos_busfreq_timer(struct work_struct *work) -{ - struct delayed_work *delayed_work = to_delayed_work(work); - struct busfreq_data *data = container_of(delayed_work, struct busfreq_data, - worker); - int i; - struct opp *opp[PPMU_TYPE_END]; - unsigned long newfreq; - - data->monitor(data, &opp[PPMU_MIF], &opp[PPMU_INT]); - - ppmu_start(data->dev[PPMU_MIF]); - - mutex_lock(&busfreq_lock); - - for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) { - newfreq = opp_get_freq(opp[i]); - _target(data, i, newfreq); - } - - mutex_unlock(&busfreq_lock); - queue_delayed_work(system_freezable_wq, &data->worker, data->sampling_rate); -} - -static int exynos_buspm_notifier_event(struct notifier_block *this, - unsigned long event, void *ptr) -{ - struct busfreq_data *data = container_of(this, struct busfreq_data, - exynos_buspm_notifier); - int i; - - switch (event) { - case PM_SUSPEND_PREPARE: - mutex_lock(&busfreq_lock); - for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) - _target(data, i, data->max_freq[i]); - mutex_unlock(&busfreq_lock); - data->use = false; - return NOTIFY_OK; - case PM_POST_RESTORE: - case PM_POST_SUSPEND: - data->use = true; - return NOTIFY_OK; - } - return NOTIFY_DONE; -} - -static int exynos_busfreq_reboot_event(struct notifier_block *this, - unsigned long code, void *unused) -{ - struct busfreq_data *data = container_of(this, struct busfreq_data, - exynos_reboot_notifier); - int i; - struct opp *opp; - unsigned int voltage[PPMU_TYPE_END]; - for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) { - opp = opp_find_freq_exact(data->dev[i], data->max_freq[i], true); - voltage[i] = opp_get_voltage(opp); - - regulator_set_voltage(data->vdd_reg[i], voltage[i], voltage[i] + 25000); - } - data->use = false; - - printk(KERN_INFO "REBOOT Notifier for BUSFREQ\n"); - return NOTIFY_DONE; -} - -static int exynos_busfreq_request_event(struct notifier_block *this, - unsigned long req_newfreq, void *device) -{ - struct busfreq_data *data = container_of(this, struct busfreq_data, - exynos_request_notifier); - int i; - struct opp *opp[PPMU_TYPE_END]; - unsigned long newfreq[PPMU_TYPE_END]; - unsigned long freq; - - if (req_newfreq == 0 || data->use == false) - return -EINVAL; - - mutex_lock(&busfreq_lock); - - newfreq[PPMU_MIF] = (req_newfreq / 1000) * 1000; - newfreq[PPMU_INT] = (req_newfreq % 1000) * 1000; - - for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) { - opp[i] = opp_find_freq_ceil(data->dev[i], &newfreq[i]); - freq = opp_get_freq(opp[i]); - if (freq > data->curr_freq[i]) - _target(data, i, freq); - } - - mutex_unlock(&busfreq_lock); - printk(KERN_INFO "REQUEST Notifier for BUSFREQ\n"); - return NOTIFY_DONE; -} - -int exynos_busfreq_lock(unsigned int nId, - enum busfreq_level_request busfreq_level) -{ - return 0; -} - -void exynos_busfreq_lock_free(unsigned int nId) -{ -} - -static ssize_t show_level_lock(struct device *device, - struct device_attribute *attr, char *buf) -{ - struct platform_device *pdev = to_platform_device(bus_ctrl.dev[PPMU_MIF]); - struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev); - int len = 0; - unsigned long mif_freq, int_freq; - - mif_freq = bus_ctrl.lock[PPMU_MIF] == NULL ? 0 : opp_get_freq(bus_ctrl.lock[PPMU_MIF]); - int_freq = bus_ctrl.lock[PPMU_INT] == NULL ? 0 : opp_get_freq(bus_ctrl.lock[PPMU_INT]); - - len = sprintf(buf, "Current Freq(MIF/INT) : (%lu - %lu)\n", - data->curr_freq[PPMU_MIF], data->curr_freq[PPMU_INT]); - len += sprintf(buf + len, "Current Lock Freq(MIF/INT) : (%lu - %lu)\n", mif_freq, int_freq); - - return len; -} - -static ssize_t store_level_lock(struct device *device, struct device_attribute *attr, - const char *buf, size_t count) -{ - struct platform_device *pdev = to_platform_device(bus_ctrl.dev[PPMU_MIF]); - struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev); - struct opp *opp[PPMU_TYPE_END]; - unsigned long freq[PPMU_TYPE_END]; - int i; - int ret; - - ret = sscanf(buf, "%lu %lu", &freq[PPMU_MIF], &freq[PPMU_INT]); - if (freq[PPMU_MIF] == 0 || freq[PPMU_INT] == 0 || ret != 2) { - pr_info("Release bus level lock.\n"); - bus_ctrl.lock[PPMU_MIF] = NULL; - bus_ctrl.lock[PPMU_INT] = NULL; - return count; - } - - for (i = PPMU_MIF; i < PPMU_TYPE_END; i++) { - if (freq[i] > data->max_freq[i]) - freq[i] = data->max_freq[i]; - - opp[i] = opp_find_freq_ceil(bus_ctrl.dev[i], &freq[i]); - bus_ctrl.lock[i] = opp[i]; - } - pr_info("Lock Freq : MIF/INT(%lu - %lu)\n", opp_get_freq(opp[PPMU_MIF]), opp_get_freq(opp[PPMU_INT])); - return count; -} - -static ssize_t show_locklist(struct device *device, - struct device_attribute *attr, char *buf) -{ - return dev_lock_list(bus_ctrl.dev[PPMU_MIF], buf); -} - -static ssize_t show_time_in_state(struct device *device, - struct device_attribute *attr, char *buf) -{ - struct platform_device *pdev = to_platform_device(bus_ctrl.dev[PPMU_MIF]); - struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev); - struct busfreq_table *table; - ssize_t len = 0; - int i; - - table = data->table[PPMU_MIF]; - len += sprintf(buf, "%s\n", "MIF stat"); - for (i = LV_0; i < LV_MIF_END; i++) - len += sprintf(buf + len, "%u %llu\n", table[i].mem_clk, - (unsigned long long)cputime64_to_clock_t(data->time_in_state[PPMU_MIF][i])); - - table = data->table[PPMU_INT]; - len += sprintf(buf + len, "\n%s\n", "INT stat"); - for (i = LV_0; i < LV_INT_END; i++) - len += sprintf(buf + len, "%u %llu\n", table[i].mem_clk, - (unsigned long long)cputime64_to_clock_t(data->time_in_state[PPMU_INT][i])); - return len; -} - -static DEVICE_ATTR(curr_freq, 0664, show_level_lock, store_level_lock); -static DEVICE_ATTR(lock_list, 0664, show_locklist, NULL); -static DEVICE_ATTR(time_in_state, 0664, show_time_in_state, NULL); - -static struct attribute *busfreq_attributes[] = { - &dev_attr_curr_freq.attr, - &dev_attr_lock_list.attr, - &dev_attr_time_in_state.attr, - NULL -}; - -int exynos_request_register(struct notifier_block *n) -{ - return blocking_notifier_chain_register(&exynos_busfreq_notifier_list, n); -} - -void exynos_request_apply(unsigned long freq) -{ - blocking_notifier_call_chain(&exynos_busfreq_notifier_list, freq, NULL); -} - -static __devinit int exynos_busfreq_probe(struct platform_device *pdev) -{ - struct busfreq_data *data; - - data = kzalloc(sizeof(struct busfreq_data), GFP_KERNEL); - if (!data) { - pr_err("Unable to create busfreq_data struct.\n"); - return -ENOMEM; - } - - data->exynos_buspm_notifier.notifier_call = - exynos_buspm_notifier_event; - data->exynos_reboot_notifier.notifier_call = - exynos_busfreq_reboot_event; - data->busfreq_attr_group.attrs = busfreq_attributes; - data->exynos_request_notifier.notifier_call = - exynos_busfreq_request_event; - - INIT_DELAYED_WORK(&data->worker, exynos_busfreq_timer); - - if (soc_is_exynos5250()) { - data->init = exynos5250_init; - } else { - pr_err("Unsupport device type.\n"); - goto err_busfreq; - } - - if (data->init(&pdev->dev, data)) { - pr_err("Failed to init busfreq.\n"); - goto err_busfreq; - } - - bus_ctrl.dev[PPMU_MIF] = data->dev[PPMU_MIF]; - bus_ctrl.dev[PPMU_INT] = data->dev[PPMU_INT]; - - data->last_time[PPMU_MIF] = get_jiffies_64(); - data->last_time[PPMU_INT] = get_jiffies_64(); - - data->busfreq_kobject = kobject_create_and_add("busfreq", - &cpu_sysdev_class.kset.kobj); - if (!data->busfreq_kobject) - pr_err("Failed to create busfreq kobject.!\n"); - - if (sysfs_create_group(data->busfreq_kobject, &data->busfreq_attr_group)) - pr_err("Failed to create attributes group.!\n"); - - if (register_pm_notifier(&data->exynos_buspm_notifier)) { - pr_err("Failed to setup buspm notifier\n"); - goto err_busfreq; - } - - data->use = true; - - if (register_reboot_notifier(&data->exynos_reboot_notifier)) - pr_err("Failed to setup reboot notifier\n"); - - if (exynos_request_register(&data->exynos_request_notifier)) - pr_err("Failed to setup request notifier\n"); - - platform_set_drvdata(pdev, data); - - queue_delayed_work(system_freezable_wq, &data->worker, data->sampling_rate); - return 0; - -err_busfreq: - if (!IS_ERR(data->vdd_reg[PPMU_INT])) - regulator_put(data->vdd_reg[PPMU_INT]); - - if (!IS_ERR(data->vdd_reg[PPMU_MIF])) - regulator_put(data->vdd_reg[PPMU_MIF]); - - kfree(data); - return -ENODEV; -} - -static __devexit int exynos_busfreq_remove(struct platform_device *pdev) -{ - struct busfreq_data *data = platform_get_drvdata(pdev); - - unregister_pm_notifier(&data->exynos_buspm_notifier); - unregister_reboot_notifier(&data->exynos_reboot_notifier); - regulator_put(data->vdd_reg[PPMU_INT]); - regulator_put(data->vdd_reg[PPMU_MIF]); - sysfs_remove_group(data->busfreq_kobject, &data->busfreq_attr_group); - kfree(data); - - return 0; -} - -static int exynos_busfreq_suspend(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev); - - if (data->busfreq_suspend) - data->busfreq_suspend(); - return 0; -} - -static int exynos_busfreq_resume(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - struct busfreq_data *data = (struct busfreq_data *)platform_get_drvdata(pdev); - ppmu_reset(dev); - - if (data->busfreq_resume) - data->busfreq_resume(); - return 0; -} - -static const struct dev_pm_ops exynos_busfreq_pm = { - .suspend = exynos_busfreq_suspend, - .resume = exynos_busfreq_resume, -}; - -static struct platform_driver exynos_busfreq_driver = { - .probe = exynos_busfreq_probe, - .remove = __devexit_p(exynos_busfreq_remove), - .driver = { - .name = "exynos-busfreq", - .owner = THIS_MODULE, - .pm = &exynos_busfreq_pm, - }, -}; - -static int __init exynos_busfreq_init(void) -{ - return platform_driver_register(&exynos_busfreq_driver); -} -late_initcall(exynos_busfreq_init); - -static void __exit exynos_busfreq_exit(void) -{ - platform_driver_unregister(&exynos_busfreq_driver); -} -module_exit(exynos_busfreq_exit); diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index 3aead34..3e227c0 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -1498,6 +1498,14 @@ static struct clk exynos4_init_clocks[] = { .ctrlbit = (1 << 5), }, #endif +#ifdef CONFIG_INTERNAL_MODEM_IF + { + .name = "modem", + .id = -1, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 28), + }, +#endif }; struct clk *exynos4_clkset_group_list[] = { @@ -2143,18 +2151,21 @@ static struct clksrc_clk exynos4_clksrcs[] = { }, { .clk = { .name = "sclk_pcm", + .devname = "samsung-pcm.0", .parent = &exynos4_clk_sclk_audio0.clk, }, .reg_div = { .reg = EXYNOS4_CLKDIV_MAUDIO, .shift = 4, .size = 8 }, }, { .clk = { .name = "sclk_pcm", + .devname = "samsung-pcm.1", .parent = &exynos4_clk_sclk_audio1.clk, }, .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL4, .shift = 4, .size = 8 }, }, { .clk = { .name = "sclk_pcm", + .devname = "samsung-pcm.2", .parent = &exynos4_clk_sclk_audio2.clk, }, .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL4, .shift = 20, .size = 8 }, @@ -2342,6 +2353,15 @@ void __init_or_cpufreq exynos4_setup_clocks(void) clk_fout_epll.ops = &exynos4_epll_ops; +#ifdef CONFIG_EXYNOS4_MSHC_SUPPORT_PQPRIME_EPLL + /* This is code for support PegasusQ Prime dynamically */ + if (soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_2_0)) { + /* PegasusQ Prime use EPLL rather than MPLL */ + if (clk_set_parent(&exynos4_clk_dout_mmc4.clk, &exynos4_clk_mout_epll.clk)) + printk(KERN_ERR "Unable to set parent %s of clock %s.\n", + exynos4_clk_mout_epll.clk.name, exynos4_clk_dout_mmc4.clk.name); + } +#endif #ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ if (clk_set_parent(&exynos4_clk_dout_mmc4.clk, &exynos4_clk_mout_epll.clk)) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", @@ -2355,27 +2375,6 @@ void __init_or_cpufreq exynos4_setup_clocks(void) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", exynos4_clk_fout_vpll.clk.name, exynos4_clk_sclk_vpll.clk.name); #endif - - if (clk_set_parent(&exynos4_clk_mout_audss.clk, &clk_fout_epll)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - clk_fout_epll.name, exynos4_clk_mout_audss.clk.name); - -#if defined(CONFIG_SND_SAMSUNG_PCM) && !defined(CONFIG_SND_SAMSUNG_PCM_USE_EPLL) - if (clk_set_parent(&exynos4_clk_sclk_audio0.clk, &exynos4_clk_audiocdclk0.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos4_clk_audiocdclk0.clk.name, exynos4_clk_sclk_audio0.clk.name); -#else - if (clk_set_parent(&exynos4_clk_sclk_audio0.clk, &exynos4_clk_mout_epll.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos4_clk_mout_epll.clk.name, exynos4_clk_sclk_audio0.clk.name); -#endif - - if (clk_set_parent(&exynos4_clk_sclk_audio1.clk, &exynos4_clk_mout_epll.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos4_clk_mout_epll.clk.name, exynos4_clk_sclk_audio1.clk.name); - if (clk_set_parent(&exynos4_clk_sclk_audio2.clk, &exynos4_clk_mout_epll.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos4_clk_mout_epll.clk.name, exynos4_clk_sclk_audio2.clk.name); if (clk_set_parent(&exynos4_clk_mout_epll.clk, &clk_fout_epll)) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", clk_fout_epll.name, exynos4_clk_mout_epll.clk.name); diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c index 569c523..67aecbf 100644 --- a/arch/arm/mach-exynos/clock-exynos4210.c +++ b/arch/arm/mach-exynos/clock-exynos4210.c @@ -147,10 +147,12 @@ static struct clk init_clocks_off[] = { .devname = SYSMMU_CLOCK_NAME(2d, 9), .enable = exynos4_clk_ip_image_ctrl, .ctrlbit = (1 << 3), +#ifdef CONFIG_INTERNAL_MODEM_IF }, { .name = "modem", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 28), +#endif } }; diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c index 0ed0197..a2f5d41 100644 --- a/arch/arm/mach-exynos/clock-exynos4212.c +++ b/arch/arm/mach-exynos/clock-exynos4212.c @@ -982,6 +982,7 @@ static struct vpll_div_data vpll_div_4212[] = { {333000000, 2, 111, 2, 0, 0, 0, 0}, {350000000, 3, 175, 2, 0, 0, 0, 0}, {440000000, 3, 110, 1, 0, 0, 0, 0}, + {533000000, 3, 133, 1, 16384, 0, 0, 0}, }; static unsigned long exynos4212_vpll_get_rate(struct clk *clk) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c deleted file mode 100644 index 8ee9e42..0000000 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ /dev/null @@ -1,2921 +0,0 @@ -/* linux/arch/arm/mach-exynos/clock-exynos5.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS5 - Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/syscore_ops.h> - -#include <plat/cpu-freq.h> -#include <plat/clock.h> -#include <plat/cpu.h> -#include <plat/pll.h> -#include <plat/s5p-clock.h> -#include <plat/clock-clksrc.h> -#include <plat/devs.h> -#include <plat/pm.h> - -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <mach/regs-audss.h> -#include <mach/sysmmu.h> -#include <mach/exynos-clock.h> -#include <mach/clock-domain.h> - -#ifdef CONFIG_PM -static struct sleep_save exynos5_clock_save[] = { - /* CMU side */ - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_ISP), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_SYSRGT), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_ACP), - SAVE_ITEM(EXYNOS5_CLKGATE_ISP0), - SAVE_ITEM(EXYNOS5_CLKGATE_ISP1), - SAVE_ITEM(EXYNOS5_CLKGATE_SCLK_ISP), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS), - SAVE_ITEM(EXYNOS5_CLKGATE_IP_CDREX), - SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK), - SAVE_ITEM(EXYNOS5_CLKDIV_ACP), - SAVE_ITEM(EXYNOS5_CLKDIV_ISP0), - SAVE_ITEM(EXYNOS5_CLKDIV_ISP1), - SAVE_ITEM(EXYNOS5_CLKDIV_ISP2), - SAVE_ITEM(EXYNOS5_CLKDIV_TOP0), - SAVE_ITEM(EXYNOS5_CLKDIV_TOP1), - SAVE_ITEM(EXYNOS5_CLKDIV_GSCL), - SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0), - SAVE_ITEM(EXYNOS5_CLKDIV_GEN), - SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO), - SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0), - SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1), - SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2), - SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3), - SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0), - SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1), - SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2), - SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3), - SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4), - SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5), - SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP), - SAVE_ITEM(EXYNOS5_CLKDIV2_RATIO0), - SAVE_ITEM(EXYNOS5_CLKDIV2_RATIO1), - SAVE_ITEM(EXYNOS5_CLKDIV4_RATIO), - SAVE_ITEM(EXYNOS5_CLKSRC_TOP0), - SAVE_ITEM(EXYNOS5_CLKSRC_TOP1), - SAVE_ITEM(EXYNOS5_CLKSRC_TOP2), - SAVE_ITEM(EXYNOS5_CLKSRC_TOP3), - SAVE_ITEM(EXYNOS5_CLKSRC_GSCL), - SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0), - SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO), - SAVE_ITEM(EXYNOS5_CLKSRC_FSYS), - SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0), - SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1), - SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP), -#ifdef CONFIG_EXYNOS5_ENABLE_CLOCK_DOWN - SAVE_ITEM(EXYNOS5_PWR_CTRL1), - SAVE_ITEM(EXYNOS5_PWR_CTRL2), -#endif -}; - -static struct sleep_save exynos5_epll_save[] = { - SAVE_ITEM(EXYNOS5_EPLL_LOCK), - SAVE_ITEM(EXYNOS5_EPLL_CON0), - SAVE_ITEM(EXYNOS5_EPLL_CON1), - SAVE_ITEM(EXYNOS5_EPLL_CON2), -}; - -static struct sleep_save exynos5_vpll_save[] = { - SAVE_ITEM(EXYNOS5_VPLL_LOCK), - SAVE_ITEM(EXYNOS5_VPLL_CON0), - SAVE_ITEM(EXYNOS5_VPLL_CON1), - SAVE_ITEM(EXYNOS5_VPLL_CON2), -#ifdef CONFIG_EXYNOS5_ENABLE_CLOCK_DOWN - SAVE_ITEM(EXYNOS5_PWR_CTRL1), - SAVE_ITEM(EXYNOS5_PWR_CTRL2), -#endif -}; - -static struct sleep_save exynos5_gpll_save[] = { - SAVE_ITEM(EXYNOS5_GPLL_LOCK), - SAVE_ITEM(EXYNOS5_GPLL_CON0), - SAVE_ITEM(EXYNOS5_GPLL_CON1), -}; - -static struct sleep_save exynos5250_clock_save_rev0[] = { - SAVE_ITEM(EXYNOS5_CLKGATE_IP_GPS), -}; - -#endif - -static struct clk exynos5_clk_sclk_hdmi24m = { - .name = "sclk_hdmi24m", - .rate = 24000000, -}; - -static struct clk exynos5_clk_sclk_hdmi27m = { - .name = "sclk_hdmi27m", - .rate = 27000000, -}; - -static struct clk exynos5_clk_sclk_hdmiphy = { - .name = "sclk_hdmiphy", -}; - -static struct clk exynos5_clk_sclk_dptxphy = { - .name = "sclk_dptx", -}; - -static struct clk exynos5_clk_sclk_usbphy = { - .name = "sclk_usbphy", - .rate = 48000000, -}; - -struct clksrc_clk exynos5_clk_audiocdclk0 = { - .clk = { - .name = "audiocdclk", - .rate = 16934400, - }, -}; - -static struct clk exynos5_clk_audiocdclk1 = { - .name = "audiocdclk", -}; - -static struct clk exynos5_clk_audiocdclk2 = { - .name = "audiocdclk", -}; - -static struct clk exynos5_clk_spdifcdclk = { - .name = "spdifcdclk", -}; - -static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable); -} - -static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable); -} - -static int exynos5_clk_ip_sysrgt_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_SYSRGT, clk, enable); -} - -static int exynos5_clk_ip_cpu_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CPU, clk, enable); -} - -static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable); -} - -static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable); -} - -static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable); -} - -static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); -} - -static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable); -} - -static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable); -} - -static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable); -} - -static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable); -} - -static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable); -} - -static int exynos5_clk_ip_g3d_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_G3D, clk, enable); -} - -static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); -} - -static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable); -} - -static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable); -} - -static int exynos5_clksrc_mask_maudio_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_MAUDIO, clk, enable); -} - -static int exynos5_clk_audss_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_AUDSS, clk, enable); -} - -static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable); -} - -static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable); -} - -static int exynos5_clksrc_mask_gen_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GEN, clk, enable); -} - -static int exynos5_clk_gate_block(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable); -} - -static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); -} - -static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_ISP0, clk, enable); -} - -static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKGATE_ISP1, clk, enable); -} - -static int exynos5_clk_clkout_cpu_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_CPU, clk, enable); -} - -static int exynos5_clk_clkout_core_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_CORE, clk, enable); -} - -static int exynos5_clk_clkout_acp_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_ACP, clk, enable); -} - -static int exynos5_clk_clkout_isp_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_ISP, clk, enable); -} - -static int exynos5_clk_clkout_top_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_TOP, clk, enable); -} - -static int exynos5_clk_clkout_lex_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_LEX, clk, enable); -} - -static int exynos5_clk_clkout_r0x_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_R0X, clk, enable); -} - -static int exynos5_clk_clkout_r1x_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_R1X, clk, enable); -} - -static int exynos5_clk_clkout_cdrex_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(EXYNOS5_CLKOUT_CMU_CDREX, clk, enable); -} - -/* BPLL clock output - * No need .ctrlbit, this is always on -*/ -static struct clk clk_fout_bpll = { - .name = "fout_bpll", - .id = -1, -}; - -/* MOUT_BPLL_FOUT - * No need .ctrlbit, this is always on -*/ -static struct clk clk_fout_bpll_div2 = { - .name = "fout_bpll_div2", - .id = -1, -}; - -/* MOUT_MPLL_FOUT - * No need .ctrlbit, this is always on -*/ -static struct clk clk_fout_mpll_div2 = { - .name = "fout_mpll_div2", - .id = -1, -}; - -/* Possible clock sources for BPLL Mux */ -static struct clk *clk_src_bpll_list[] = { - [0] = &clk_fin_bpll, - [1] = &clk_fout_bpll, -}; - -static struct clksrc_sources clk_src_bpll = { - .sources = clk_src_bpll_list, - .nr_sources = ARRAY_SIZE(clk_src_bpll_list), -}; - -/* Possible clock source for BPLL_FOUT Mux */ -static struct clk *exynos5_clkset_mout_bpll_fout_list[] = { - [0] = &clk_fout_bpll_div2, - [1] = &clk_fout_bpll, -}; - -static struct clksrc_sources exynos5_clkset_mout_bpll_fout = { - .sources = exynos5_clkset_mout_bpll_fout_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_bpll_fout_list), -}; - -/* GPLL clock output */ -static struct clk clk_fout_gpll = { - .name = "fout_gpll", - .id = -1, -}; - -/* Possible clock sources for GPLL Mux */ -static struct clk *clk_src_gpll_list[] = { - [0] = &clk_fin_gpll, - [1] = &clk_fout_gpll, -}; - -static struct clksrc_sources clk_src_gpll = { - .sources = clk_src_gpll_list, - .nr_sources = ARRAY_SIZE(clk_src_gpll_list), -}; - -/* CPLL clock output */ -static struct clk clk_fout_cpll = { - .name = "fout_cpll", - .id = -1, -}; - -/* Possible clock sources for CPLL Mux */ -static struct clk *clk_src_cpll_list[] = { - [0] = &clk_fin_cpll, - [1] = &clk_fout_cpll, -}; - -static struct clksrc_sources clk_src_cpll = { - .sources = clk_src_cpll_list, - .nr_sources = ARRAY_SIZE(clk_src_cpll_list), -}; - -/* Possible clock source for MPLL_FOUT Mux */ -static struct clk *exynos5_clkset_mout_mpll_fout_list[] = { - [0] = &clk_fout_mpll_div2, - [1] = &clk_fout_mpll, -}; - -static struct clksrc_sources exynos5_clkset_mout_mpll_fout = { - .sources = exynos5_clkset_mout_mpll_fout_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_mpll_fout_list), -}; - -static struct clksrc_clk exynos5_clk_mout_mpll_fout = { - .clk = { - .name = "mout_mpll_fout", - }, - .sources = &exynos5_clkset_mout_mpll_fout, - .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 }, -}; - -/* Possible clock source for MPLL Mux */ -static struct clk *exynos5_clkset_mout_mpll_list[] = { - [0] = &clk_fin_mpll, - [1] = &exynos5_clk_mout_mpll_fout.clk, -}; - -static struct clksrc_sources exynos5_clkset_mout_mpll = { - .sources = exynos5_clkset_mout_mpll_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_mpll_list), -}; - -static struct clksrc_clk exynos5_clk_mout_bpll_fout = { - .clk = { - .name = "mout_bpll_fout", - }, - .sources = &exynos5_clkset_mout_bpll_fout, - .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 }, -}; - -/* Possible clock source for BPLL Mux */ -static struct clk *exynos5_clkset_mout_bpll_list[] = { - [0] = &clk_fin_bpll, - [1] = &exynos5_clk_mout_bpll_fout.clk, -}; - -static struct clksrc_sources exynos5_clkset_mout_bpll = { - .sources = exynos5_clkset_mout_bpll_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_bpll_list), -}; - -/* Core list of CMU_CPU side */ -static struct clksrc_clk exynos5_clk_mout_apll = { - .clk = { - .name = "mout_apll", - }, - .sources = &clk_src_apll, - .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_apll = { - .clk = { - .name = "sclk_apll", - .parent = &exynos5_clk_mout_apll.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 }, -}; - -static struct clksrc_clk exynos5_clk_mout_bpll = { - .clk = { - .name = "mout_bpll", - }, - .sources = &clk_src_bpll, - .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_mout_gpll = { - .clk = { - .name = "mout_gpll", - }, - .sources = &clk_src_gpll, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_mout_cpll = { - .clk = { - .name = "mout_cpll", - }, - .sources = &clk_src_cpll, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_mout_epll = { - .clk = { - .name = "mout_epll", - }, - .sources = &clk_src_epll, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 }, -}; - -struct clksrc_clk exynos5_clk_mout_mpll = { - .clk = { - .name = "mout_mpll", - }, - .sources = &clk_src_mpll, - .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, -}; - -/* CMU_ACP */ -static struct clksrc_clk exynos5_clk_aclk_acp = { - .clk = { - .name = "aclk_acp", - .parent = &exynos5_clk_mout_mpll.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 }, -}; - -static struct clksrc_clk exynos5_clk_pclk_acp = { - .clk = { - .name = "pclk_acp", - .parent = &exynos5_clk_aclk_acp.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 }, -}; - -/* For VPLL */ -static struct clk *exynos5_clkset_mout_vpllsrc_list[] = { - [0] = &clk_fin_vpll, - [1] = &exynos5_clk_sclk_hdmi27m, -}; - -static struct clksrc_sources exynos5_clkset_mout_vpllsrc = { - .sources = exynos5_clkset_mout_vpllsrc_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_vpllsrc_list), -}; - -static struct clksrc_clk exynos5_clk_mout_vpllsrc = { - .clk = { - .name = "vpll_src", - .enable = exynos5_clksrc_mask_top_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_mout_vpllsrc, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 }, -}; - -static struct clk *exynos5_clkset_sclk_vpll_list[] = { - [0] = &exynos5_clk_mout_vpllsrc.clk, - [1] = &clk_fout_vpll, -}; - -static struct clksrc_sources exynos5_clkset_sclk_vpll = { - .sources = exynos5_clkset_sclk_vpll_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_vpll = { - .clk = { - .name = "sclk_vpll", - }, - .sources = &exynos5_clkset_sclk_vpll, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_pixel = { - .clk = { - .name = "sclk_pixel", - .parent = &exynos5_clk_sclk_vpll.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 }, -}; - -static struct clk *exynos5_clkset_sclk_hdmi_list[] = { - [0] = &exynos5_clk_sclk_pixel.clk, - [1] = &exynos5_clk_sclk_hdmiphy, -}; - -static struct clksrc_sources exynos5_clkset_sclk_hdmi = { - .sources = exynos5_clkset_sclk_hdmi_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_hdmi = { - .clk = { - .name = "sclk_hdmi", - .enable = exynos5_clksrc_mask_disp1_0_ctrl, - .ctrlbit = (1 << 20), - }, - .sources = &exynos5_clkset_sclk_hdmi, - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 }, -}; - -static struct clk *exynos5_clkset_sclk_cec_list[] = { - [0] = &exynos5_clk_sclk_pixel.clk, - [1] = &exynos5_clk_sclk_hdmiphy, -}; - -static struct clksrc_sources exynos5_clkset_sclk_cec = { - .sources = exynos5_clkset_sclk_cec_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_cec_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_cec = { - .clk = { - .name = "sclk_cec", - .enable = exynos5_clksrc_mask_disp1_0_ctrl, - .ctrlbit = (1 << 20), - }, - .sources = &exynos5_clkset_sclk_cec, - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 }, -}; - -static struct clksrc_clk *exynos5_sclk_tv[] = { - &exynos5_clk_sclk_pixel, - &exynos5_clk_sclk_hdmi, - &exynos5_clk_sclk_cec, -}; - -/* BPLL USER */ -static struct clk *exynos5_clk_src_bpll_user_list[] = { - [0] = &clk_fin_mpll, - [1] = &exynos5_clk_mout_bpll.clk, -}; - -static struct clksrc_sources exynos5_clk_src_bpll_user = { - .sources = exynos5_clk_src_bpll_user_list, - .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list), -}; - -static struct clksrc_clk exynos5_clk_mout_bpll_user = { - .clk = { - .name = "mout_bpll_user", - }, - .sources = &exynos5_clk_src_bpll_user, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 }, -}; - -/* MPLL USER */ -static struct clk *exynos5_clk_src_mpll_user_list[] = { - [0] = &clk_fin_mpll, - [1] = &exynos5_clk_mout_mpll.clk, -}; - -static struct clksrc_sources exynos5_clk_src_mpll_user = { - .sources = exynos5_clk_src_mpll_user_list, - .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list), -}; - -static struct clksrc_clk exynos5_clk_mout_mpll_user = { - .clk = { - .name = "mout_mpll_user", - }, - .sources = &exynos5_clk_src_mpll_user, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 }, -}; - -static struct clk *exynos5_clkset_mout_cpu_list[] = { - [0] = &exynos5_clk_mout_apll.clk, - [1] = &exynos5_clk_mout_mpll.clk, -}; - -static struct clksrc_sources exynos5_clkset_mout_cpu = { - .sources = exynos5_clkset_mout_cpu_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list), -}; - -static struct clksrc_clk exynos5_clk_mout_cpu = { - .clk = { - .name = "moutcpu", - }, - .sources = &exynos5_clkset_mout_cpu, - .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_dout_armclk = { - .clk = { - .name = "dout_arm_clk", - .parent = &exynos5_clk_mout_cpu.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 }, -}; - -static struct clksrc_clk exynos5_clk_dout_arm2clk = { - .clk = { - .name = "dout_arm_clk", - .parent = &exynos5_clk_dout_armclk.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 }, -}; - -static struct clk exynos5_clk_armclk = { - .name = "armclk", - .parent = &exynos5_clk_dout_arm2clk.clk, -}; - -/* Core list of CMU_CDREX side */ - -static struct clk *exynos5_clkset_cdrex_list[] = { - [0] = &exynos5_clk_mout_mpll.clk, - [1] = &exynos5_clk_mout_bpll.clk, -}; - -static struct clksrc_sources exynos5_clkset_mclk_cdrex = { - .sources = exynos5_clkset_cdrex_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list), -}; - -static struct clksrc_clk exynos5_clk_mclk_cdrex = { - .clk = { - .name = "mclk_cdrex", - }, - .sources = &exynos5_clkset_mclk_cdrex, - .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 8, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 28, .size = 3 }, -}; - -/* Core list of CMU_TOP side */ - -struct clk *exynos5_clkset_aclk_top_list[] = { - [0] = &exynos5_clk_mout_mpll_user.clk, - [1] = &exynos5_clk_mout_bpll_user.clk, -}; - -struct clksrc_sources exynos5_clkset_aclk = { - .sources = exynos5_clkset_aclk_top_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list), -}; - -/* For ACLK_400_G3D_MID */ -static struct clksrc_clk exynos5_clk_aclk_400_g3d_mid = { - .clk = { - .name = "aclk_400_g3d_mid", - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 }, -}; - -/* For ACLK_400_G3D */ -struct clk *exynos5_clkset_aclk_g3d_list[] = { - [0] = &exynos5_clk_aclk_400_g3d_mid.clk, - [1] = &exynos5_clk_mout_gpll.clk, -}; - -struct clksrc_sources exynos5_clkset_aclk_g3d = { - .sources = exynos5_clkset_aclk_g3d_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_g3d_list), -}; - -static struct clksrc_clk exynos5_clk_aclk_400 = { - .clk = { - .name = "aclk_400", - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 28, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 }, -}; - -/* For ACLK_333 */ -struct clk *exynos5_clkset_mout_aclk_333_166_list[] = { - [0] = &exynos5_clk_mout_cpll.clk, - [1] = &exynos5_clk_mout_mpll_user.clk, -}; - -struct clksrc_sources exynos5_clkset_mout_aclk_333_166 = { - .sources = exynos5_clkset_mout_aclk_333_166_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_aclk_333_166_list), -}; - -static struct clksrc_clk exynos5_clk_mout_aclk_333 = { - .clk = { - .name = "mout_aclk_333", - }, - .sources = &exynos5_clkset_mout_aclk_333_166, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_dout_aclk_333 = { - .clk = { - .name = "dout_aclk_333", - .parent = &exynos5_clk_mout_aclk_333.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 }, -}; - -struct clk *exynos5_clkset_aclk_333_sub_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = &exynos5_clk_dout_aclk_333.clk, -}; - -struct clksrc_sources exynos5_clkset_aclk_333_sub = { - .sources = exynos5_clkset_aclk_333_sub_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_sub_list), -}; - -static struct clksrc_clk exynos5_clk_aclk_333 = { - .clk = { - .name = "aclk_333", - }, - .sources = &exynos5_clkset_aclk_333_sub, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 24, .size = 1 }, -}; - -/* For ACLK_300_disp1_mid */ -static struct clksrc_clk exynos5_clk_mout_aclk_300_disp1_mid = { - .clk = { - .name = "mout_aclk_300_disp1_mid", - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 14, .size = 1 }, -}; - -static struct clk *clk_src_mid1_list[] = { - [0] = &exynos5_clk_sclk_vpll.clk, - [1] = &exynos5_clk_mout_cpll.clk, -}; - -static struct clksrc_sources exynos5_clkset_mid1 = { - .sources = clk_src_mid1_list, - .nr_sources = ARRAY_SIZE(clk_src_mid1_list), -}; - -/* For ACLK_300_disp1_mid1 */ -static struct clksrc_clk exynos5_clk_mout_aclk_300_disp1_mid1 = { - .clk = { - .name = "mout_aclk_300_disp1_mid1", - }, - .sources = &exynos5_clkset_mid1, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 8, .size = 1 }, -}; - -/* For ACLK_300_disp1 */ -struct clk *exynos5_clkset_mout_aclk_300_disp1_list[] = { - [0] = &exynos5_clk_mout_aclk_300_disp1_mid.clk, - [1] = &exynos5_clk_sclk_vpll.clk, -}; - -struct clksrc_sources exynos5_clkset_mout_aclk_300_disp1 = { - .sources = exynos5_clkset_mout_aclk_300_disp1_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_aclk_300_disp1_list), -}; - -struct clk *exynos5_clkset_mout_aclk_300_disp1_rev1_list[] = { - [0] = &exynos5_clk_mout_aclk_300_disp1_mid.clk, - [1] = &exynos5_clk_mout_aclk_300_disp1_mid1.clk, -}; - -struct clksrc_sources exynos5_clkset_mout_aclk_300_disp1_rev1 = { - .sources = exynos5_clkset_mout_aclk_300_disp1_rev1_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_aclk_300_disp1_rev1_list), -}; - -static struct clksrc_clk exynos5_clk_mout_aclk_300_disp1 = { - .clk = { - .name = "mout_aclk_300_disp1", - }, - .sources = &exynos5_clkset_mout_aclk_300_disp1, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 15, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_dout_aclk_300_disp1 = { - .clk = { - .name = "dout_aclk_300_disp1", - .parent = &exynos5_clk_mout_aclk_300_disp1.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 28, .size = 3 }, -}; - -static struct clk *clk_src_aclk_300_disp1_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = &exynos5_clk_dout_aclk_300_disp1.clk, -}; - -static struct clksrc_sources exynos5_clkset_aclk_300_disp1 = { - .sources = clk_src_aclk_300_disp1_list, - .nr_sources = ARRAY_SIZE(clk_src_aclk_300_disp1_list), -}; - -static struct clksrc_clk exynos5_clk_aclk_300_disp1 = { - .clk = { - .name = "aclk_300_disp1", - }, - .sources = &exynos5_clkset_aclk_300_disp1, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 6, .size = 1 }, -}; - -/* For ACLK_300_gscl_mid */ -static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = { - .clk = { - .name = "mout_aclk_300_gscl_mid", - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 }, -}; - -/* For ACLK_300_gscl_mid1 */ -static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = { - .clk = { - .name = "mout_aclk_300_gscl_mid1", - }, - .sources = &exynos5_clkset_mid1, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 }, -}; - -/* For ACLK_300_gscl */ -struct clk *exynos5_clkset_aclk_300_gscl_list[] = { - [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk, - [1] = &exynos5_clk_sclk_vpll.clk, -}; - -struct clksrc_sources exynos5_clkset_aclk_300_gscl = { - .sources = exynos5_clkset_aclk_300_gscl_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list), -}; - -struct clk *exynos5_clkset_aclk_300_gscl_rev1_list[] = { - [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk, - [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk, -}; - -struct clksrc_sources exynos5_clkset_aclk_300_gscl_rev1 = { - .sources = exynos5_clkset_aclk_300_gscl_rev1_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_rev1_list), -}; - -static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = { - .clk = { - .name = "mout_aclk_300_gscl", - }, - .sources = &exynos5_clkset_aclk_300_gscl, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = { - .clk = { - .name = "dout_aclk_300_gscl", - .parent = &exynos5_clk_mout_aclk_300_gscl.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 }, -}; - -/* Possible clock sources for aclk_300_gscl_sub Mux */ -static struct clk *clk_src_gscl_300_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = &exynos5_clk_dout_aclk_300_gscl.clk, -}; - -static struct clksrc_sources clk_src_gscl_300 = { - .sources = clk_src_gscl_300_list, - .nr_sources = ARRAY_SIZE(clk_src_gscl_300_list), -}; - -static struct clksrc_clk exynos5_clk_aclk_300_gscl = { - .clk = { - .name = "aclk_300_gscl", - }, - .sources = &clk_src_gscl_300, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 }, -}; - -/* For ACLK_266 */ -static struct clksrc_clk exynos5_clk_aclk_266 = { - .clk = { - .name = "aclk_266", - .parent = &exynos5_clk_mout_mpll_user.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 }, -}; - -/* For ACLK_200 */ -static struct clksrc_clk exynos5_clk_aclk_200 = { - .clk = { - .name = "aclk_200", - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 }, -}; - -/* For ACLK_166 */ -static struct clksrc_clk exynos5_clk_aclk_166 = { - .clk = { - .name = "aclk_166", - }, - .sources = &exynos5_clkset_mout_aclk_333_166, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 }, -}; - -/* For ACLK_66 */ -static struct clksrc_clk exynos5_clk_dout_aclk_66_pre = { - .clk = { - .name = "aclk_66_pre", - .parent = &exynos5_clk_mout_mpll_user.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 }, -}; - -static struct clksrc_clk exynos5_clk_aclk_66 = { - .clk = { - .name = "aclk_66", - .parent = &exynos5_clk_dout_aclk_66_pre.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 }, -}; - -static struct clk *clk_src_aclk_200_disp1_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = &exynos5_clk_aclk_200.clk, -}; - -static struct clksrc_sources exynos5_clkset_aclk_200_disp1 = { - .sources = clk_src_aclk_200_disp1_list, - .nr_sources = ARRAY_SIZE(clk_src_aclk_200_disp1_list), -}; - -static struct clksrc_clk exynos5_clk_aclk_200_disp1 = { - .clk = { - .name = "aclk_200_disp1", - }, - .sources = &exynos5_clkset_aclk_200_disp1, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 4, .size = 1 }, -}; - -static struct clk exynos5_init_clocks[] = { - { - .name = "uart", - .devname = "s5pv210-uart.0", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "uart", - .devname = "s5pv210-uart.1", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 1), - }, { - .name = "uart", - .devname = "s5pv210-uart.2", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 2), - }, { - .name = "uart", - .devname = "s5pv210-uart.3", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "uart", - .devname = "s5pv210-uart.4", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "uart", - .devname = "s5pv210-uart.5", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 5), - }, -}; - - -/* TN Feature.. these clocks was enabled at booloader */ - -static struct clk exynos5_init_clock_on[] = { - { - .name = "timers", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1<<24), - }, { - .name = "lcd", - .devname = "s3cfb.1", - .enable = exynos5_clk_ip_disp1_ctrl, - .ctrlbit = ((0x7 << 10) | (1 << 0)), - }, { - .name = "dp", - .devname = "s5p-dp", - .enable = exynos5_clk_ip_disp1_ctrl, - .ctrlbit = (1 << 4), - }, -}; - -static struct clk exynos5_init_clocks_off[] = { - { - .name = "watchdog", - .enable = exynos5_clk_ip_peris_ctrl, - .ctrlbit = (1 << 19), - }, { - .name = "hdmicec", - .enable = exynos5_clk_ip_peris_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "rtc", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peris_ctrl, - .ctrlbit = (1<<20), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 12), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 13), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.2", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 14), - }, { - .name = "hsmmc", - .devname = "s3c-sdhci.3", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 15), - }, { - .name = "dwmci", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "sata", - .devname = "ahci", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "sata_phy", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 24), - }, { - .name = "sata_phy_i2c", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 25), - }, { - .name = "usbdrd30", - .parent = &exynos5_clk_aclk_200.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 19), - }, { - .name = "mfc", - .devname = "s3c-mfc", - .enable = exynos5_clk_ip_mfc_ctrl, - .ctrlbit = ((1 << 4) | (1 << 3) | (1 << 0)), - }, { - .name = "g3d", - .enable = exynos5_clk_ip_g3d_ctrl, - .ctrlbit = ((1 << 1) | (1 << 0)), - }, { - .name = "g3d", - .enable = exynos5_clk_ip_g3d_ctrl, - .ctrlbit = ((1 << 1) | (1 << 0)), - }, { - .name = "isp0", - .devname = "exynos5-fimc-is", - .enable = exynos5_clk_ip_isp0_ctrl, - .ctrlbit = (0xDFFFC0FF << 0), - }, { - .name = "isp1", - .devname = "exynos5-fimc-is", - .enable = exynos5_clk_ip_isp1_ctrl, - .ctrlbit = (0x3F07 << 0), - }, { - .name = "hdmi", - .devname = "exynos5-hdmi", - .enable = exynos5_clk_ip_disp1_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "mixer", - .devname = "s5p-mixer", - .enable = exynos5_clk_ip_disp1_ctrl, - .ctrlbit = ((0x3 << 13) | (1 << 5)), - }, { - .name = "hdmiphy", - .devname = "exynos5-hdmi", - .enable = exynos5_clk_hdmiphy_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "gscl", - .devname = "exynos-gsc.0", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = ((1 << 15) | (1 << 0)), - }, { - .name = "gscl", - .devname = "exynos-gsc.1", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = ((1 << 16) | (1 << 1)), - }, { - .name = "gscl", - .devname = "exynos-gsc.2", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = ((1 << 17) | (1 << 2)), - }, { - .name = "gscl", - .devname = "exynos-gsc.3", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = ((1 << 18) | (1 << 3)), - }, { - .name = "camif_top", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 4), - }, { - .name = "gscl_wrap0", - .devname = "s5p-mipi-csis.0", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 5), - }, { - .name = "gscl_wrap1", - .devname = "s5p-mipi-csis.1", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "rotator", - .devname = "exynos-rot", - .enable = exynos5_clk_ip_gen_ctrl, - .ctrlbit = ((1 << 11) | (1 << 1)), - }, { - .name = "jpeg", - .enable = exynos5_clk_ip_gen_ctrl, - .ctrlbit = ((1 << 12) | (1 << 2)), - }, { - .name = "dsim0", - .enable = exynos5_clk_ip_disp1_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "iis", - .devname = "samsung-i2s.1", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 20), - }, { - .name = "iis", - .devname = "samsung-i2s.2", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 21), - }, { - .name = "pcm", - .devname = "samsung-pcm.1", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 22), - }, { - .name = "pcm", - .devname = "samsung-pcm.2", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 23), - }, { - .name = "spdif", - .devname = "samsung-spdif", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 26), - }, { - .name = "ac97", - .devname = "samsung-ac97", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 27), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(mfc_lr, 0), - .enable = &exynos5_clk_ip_mfc_ctrl, - .ctrlbit = (3 << 1), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(tv, 2), - .enable = &exynos5_clk_ip_disp1_ctrl, - .ctrlbit = (1 << 9) - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3), - .enable = &exynos5_clk_ip_gen_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(rot, 4), - .enable = &exynos5_clk_ip_gen_ctrl, - .ctrlbit = (1 << 6) - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5), - .enable = &exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6), - .enable = &exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 8), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7), - .enable = &exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 9), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8), - .enable = &exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 10), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), - .enable = &exynos5_clk_ip_isp0_ctrl, - .ctrlbit = (0x3F << 8), - }, { - .name = SYSMMU_CLOCK_NAME2, - .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), - .enable = &exynos5_clk_ip_isp1_ctrl, - .ctrlbit = (0xF << 4), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(camif0, 12), - .enable = &exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 11), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(camif1, 13), - .enable = &exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 12), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(camif2, 14), - .enable = &exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 20), - }, { - .name = SYSMMU_CLOCK_NAME, - .devname = SYSMMU_CLOCK_DEVNAME(2d, 15), - .enable = &exynos5_clk_ip_acp_ctrl, - .ctrlbit = (1 << 7) - }, { - .name = "usbhost", - .enable = exynos5_clk_ip_fsys_ctrl , - .ctrlbit = (1 << 18), - }, { - .name = "usbotg", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "fimg2d", - .devname = "s5p-fimg2d", - .enable = exynos5_clk_ip_acp_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "gps", - .enable = exynos5_clk_ip_gps_ctrl, - .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)), - }, { - .name = "nfcon", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 22), - }, -#ifdef CONFIG_CPU_EXYNOS5250 - { - .name = "iop", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)), - }, { - .name = "core_iop", - .enable = exynos5_clk_ip_core_ctrl, - .ctrlbit = ((1 << 21) | (1 << 3)), - }, { - .name = "mcu_iop", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 0), - }, { - .name = "adc", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 15), - }, { - .name = "spi", - .devname = "s3c64xx-spi.0", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "spi", - .devname = "s3c64xx-spi.1", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 17), - }, { - .name = "spi", - .devname = "s3c64xx-spi.2", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 18), - }, -#endif - { - .name = "ppmufsys", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = ((1 << 29) | (1 << 28)), - }, { - .name = "ppmudisp1", - .enable = exynos5_clk_ip_disp1_ctrl, - .ctrlbit = ((1 << 17) | (1 << 18)), - }, { - .name = "ppmumfc", - .enable = exynos5_clk_ip_mfc_ctrl, - .ctrlbit = ((1 << 5) | (1 << 6)), - }, { - .name = "ppmug3d", - .enable = exynos5_clk_ip_g3d_ctrl, - .ctrlbit = (1 << 2), - }, { - .name = "ppmugen", - .enable = exynos5_clk_ip_gen_ctrl, - .ctrlbit = (1 << 15), - }, { - .name = "ppmugscl", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = (1 << 19), - }, { - .name = "acp", - .enable = exynos5_clk_ip_acp_ctrl, - .ctrlbit = (1 << 11), - }, { - .name = "rtic", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = ((1 << 11) | (1 << 9)), - }, { - .name = "disp1", - .enable = exynos5_clk_ip_disp1_ctrl, - .ctrlbit = (1 << 8), - }, { - .name = "gscl", - .enable = exynos5_clk_ip_gscl_ctrl, - .ctrlbit = ((0xF << 11) | (1 << 19)), - }, { - .name = "secss", - .parent = &exynos5_clk_aclk_acp.clk, - .enable = exynos5_clk_ip_acp_ctrl, - .ctrlbit = (1 << 2), - }, { - .name = "sromc", - .enable = exynos5_clk_ip_fsys_ctrl , - .ctrlbit = (1 << 17), - }, { - .name = "mipi-hsi", - .enable = exynos5_clk_ip_fsys_ctrl , - .ctrlbit = (1 << 8), - }, { - .name = "mie", - .enable = exynos5_clk_ip_disp1_ctrl , - .ctrlbit = (1 << 1), - }, { - .name = "clkout_cpu", - .enable = exynos5_clk_clkout_cpu_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_core", - .enable = exynos5_clk_clkout_core_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_acp", - .enable = exynos5_clk_clkout_acp_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_isp", - .enable = exynos5_clk_clkout_isp_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_top", - .enable = exynos5_clk_clkout_top_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_lex", - .enable = exynos5_clk_clkout_lex_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_r0x", - .enable = exynos5_clk_clkout_r0x_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_r1x", - .enable = exynos5_clk_clkout_r1x_ctrl, - .ctrlbit = (1 << 16), - }, { - .name = "clkout_cdrex", - .enable = exynos5_clk_clkout_cdrex_ctrl, - .ctrlbit = (1 << 16), - } -}; - -static struct clk exynos5_i2cs_clocks[] = { - { - .name = "i2c", - .devname = "s3c2440-i2c.0", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 6), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.1", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 7), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.2", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 8), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.3", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 9), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.4", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 10), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.5", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 11), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.6", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 12), - }, { - .name = "i2c", - .devname = "s3c2440-i2c.7", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 13), - }, { - .name = "i2c", - .devname = "s3c2440-hdmiphy-i2c", - .parent = &exynos5_clk_aclk_66.clk, - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 14), - } -}; - -struct clk exynos5_uis_clocks[] = { - { - .name = "uis", - .devname = "s3c2440-uis.0", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 28), - }, { - .name = "uis", - .devname = "exynos-uis.1", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 29), - }, { - .name = "uis", - .devname = "exynos-uis.2", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 30), - }, { - .name = "uis", - .devname = "exynos-uis.3", - .enable = exynos5_clk_ip_peric_ctrl, - .ctrlbit = (1 << 31), - }, -}; - -struct clk exynos5_init_dmaclocks[] = { - { - .name = "pdma", - .devname = "s3c-pl330.0", - .enable = exynos5_clk_ip_gen_ctrl, - .ctrlbit = ((1 << 4) | (1 << 14)), - }, { - .name = "pdma", - .devname = "s3c-pl330.1", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 1), - }, { - .name = "pdma", - .devname = "s3c-pl330.2", - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 2), - }, { - .name = "pdma", - .enable = exynos5_clk_ip_acp_ctrl, - .ctrlbit = ((1 << 1) | (1 << 8)), - }, -}; - -#ifndef CONFIG_SAMSUNG_C2C -struct clk exynos5_c2c_clock = { - .name = "c2c", - .devname = "samsung-c2c", - .enable = exynos5_clk_ip_cpu_ctrl, - .ctrlbit = (0x3f << 11), -}; -#endif - -static struct clk *clkset_sclk_audio0_list[] = { - [0] = &exynos5_clk_audiocdclk0.clk, - [1] = &clk_ext_xtal_mux, - [2] = &exynos5_clk_sclk_hdmi27m, - [3] = &exynos5_clk_sclk_dptxphy, - [4] = &exynos5_clk_sclk_usbphy, - [5] = &exynos5_clk_sclk_hdmiphy, - [6] = &exynos5_clk_mout_mpll.clk, - [7] = &exynos5_clk_mout_epll.clk, - [8] = &exynos5_clk_sclk_vpll.clk, - [9] = &exynos5_clk_mout_cpll.clk, -}; - -static struct clksrc_sources exynos5_clkset_sclk_audio0 = { - .sources = clkset_sclk_audio0_list, - .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_audio0 = { - .clk = { - .name = "audio-bus", - .enable = exynos5_clksrc_mask_maudio_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_sclk_audio0, - .reg_src = { .reg = EXYNOS5_CLKSRC_MAUDIO, .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 0, .size = 4 }, -}; - -static struct clk *exynos5_clkset_mout_audss_list[] = { - &clk_ext_xtal_mux, - &clk_fout_epll, -}; - -static struct clksrc_sources clkset_mout_audss = { - .sources = exynos5_clkset_mout_audss_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_audss_list), -}; - -static struct clksrc_clk exynos5_clk_mout_audss = { - .clk = { - .name = "mout_audss", - }, - .sources = &clkset_mout_audss, - .reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 0, .size = 1 }, -}; - -static struct clk *exynos5_clkset_sclk_audss_list[] = { - &exynos5_clk_mout_audss.clk, - &exynos5_clk_audiocdclk0.clk, - &exynos5_clk_sclk_audio0.clk, -}; - -static struct clksrc_sources exynos5_clkset_sclk_audss = { - .sources = exynos5_clkset_sclk_audss_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_audss_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_audss_i2s = { - .clk = { - .name = "i2sclk", - .enable = exynos5_clk_audss_ctrl, - .ctrlbit = S5P_AUDSS_CLKGATE_I2SSPECIAL, - }, - .sources = &exynos5_clkset_sclk_audss, - .reg_src = { .reg = S5P_CLKSRC_AUDSS, .shift = 2, .size = 2 }, - .reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 8, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_dout_audss_srp = { - .clk = { - .name = "dout_srp", - .parent = &exynos5_clk_mout_audss.clk, - }, - .reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_audss_bus = { - .clk = { - .name = "busclk", - .parent = &exynos5_clk_dout_audss_srp.clk, - .enable = exynos5_clk_audss_ctrl, - .ctrlbit = S5P_AUDSS_CLKGATE_I2SBUS, - }, - .reg_div = { .reg = S5P_CLKDIV_AUDSS, .shift = 4, .size = 4 }, -}; - -static struct clk exynos5_init_audss_clocks[] = { - { - .name = "srpclk", - .parent = &exynos5_clk_dout_audss_srp.clk, - .enable = exynos5_clk_audss_ctrl, - .ctrlbit = S5P_AUDSS_CLKGATE_RP | S5P_AUDSS_CLKGATE_UART - | S5P_AUDSS_CLKGATE_TIMER, - }, { - .name = "iis", - .devname = "samsung-i2s.0", - .enable = exynos5_clk_audss_ctrl, - .ctrlbit = S5P_AUDSS_CLKGATE_I2SSPECIAL | - S5P_AUDSS_CLKGATE_I2SBUS, - }, { - .name = "pcm", - .devname = "samsung-pcm.0", - .enable = exynos5_clk_audss_ctrl, - .ctrlbit = S5P_AUDSS_CLKGATE_PCMSPECIAL | - S5P_AUDSS_CLKGATE_PCMBUS, - }, -}; - -static struct clk *exynos5_clkset_sclk_audio1_list[] = { - [0] = &exynos5_clk_audiocdclk1, - [1] = &clk_ext_xtal_mux, - [2] = &exynos5_clk_sclk_hdmi27m, - [3] = &exynos5_clk_sclk_dptxphy, - [4] = &exynos5_clk_sclk_usbphy, - [5] = &exynos5_clk_sclk_hdmiphy, - [6] = &exynos5_clk_mout_mpll.clk, - [7] = &exynos5_clk_mout_epll.clk, - [8] = &exynos5_clk_sclk_vpll.clk, - [9] = &exynos5_clk_mout_cpll.clk, -}; - -static struct clksrc_sources exynos5_clkset_sclk_audio1 = { - .sources = exynos5_clkset_sclk_audio1_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_audio1_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_audio1 = { - .clk = { - .name = "audio-bus1", - .enable = exynos5_clksrc_mask_peric1_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_sclk_audio1, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 0, .size = 4 }, -}; - -static struct clk *exynos5_clkset_sclk_audio2_list[] = { - [0] = &exynos5_clk_audiocdclk2, - [1] = &clk_ext_xtal_mux, - [2] = &exynos5_clk_sclk_hdmi27m, - [3] = &exynos5_clk_sclk_dptxphy, - [4] = &exynos5_clk_sclk_usbphy, - [5] = &exynos5_clk_sclk_hdmiphy, - [6] = &exynos5_clk_mout_mpll.clk, - [7] = &exynos5_clk_mout_epll.clk, - [8] = &exynos5_clk_sclk_vpll.clk, - [9] = &exynos5_clk_mout_cpll.clk, -}; - -static struct clksrc_sources exynos5_clkset_sclk_audio2 = { - .sources = exynos5_clkset_sclk_audio2_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_audio2_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_audio2 = { - .clk = { - .name = "audio-bus2", - .enable = exynos5_clksrc_mask_peric1_ctrl, - .ctrlbit = (1 << 4), - }, - .sources = &exynos5_clkset_sclk_audio2, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 4, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 16, .size = 4 }, -}; - -static struct clk *exynos5_clkset_sclk_spdif_list[] = { - [0] = &exynos5_clk_sclk_audio0.clk, - [1] = &exynos5_clk_sclk_audio1.clk, - [2] = &exynos5_clk_sclk_audio2.clk, - [3] = &exynos5_clk_spdifcdclk, -}; - -static struct clksrc_sources exynos5_clkset_sclk_spdif = { - .sources = exynos5_clkset_sclk_spdif_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_spdif_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_spdif = { - .clk = { - .name = "sclk_spdif", - .enable = exynos5_clksrc_mask_peric1_ctrl, - .ctrlbit = (1 << 8), - .ops = &s5p_sclk_spdif_ops, - }, - .sources = &exynos5_clkset_sclk_spdif, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 8, .size = 2 }, -}; - -struct clk *exynos5_clkset_usbdrd30_list[] = { - [0] = &exynos5_clk_mout_mpll.clk, - [1] = &exynos5_clk_mout_cpll.clk, -}; - -struct clksrc_sources exynos5_clkset_usbdrd30 = { - .sources = exynos5_clkset_usbdrd30_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list), -}; - -struct clk *exynos5_clkset_group_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = NULL, - [2] = &exynos5_clk_sclk_hdmi24m, - [3] = &exynos5_clk_sclk_dptxphy, - [4] = &exynos5_clk_sclk_usbphy, - [5] = &exynos5_clk_sclk_hdmiphy, - [6] = &exynos5_clk_mout_mpll_user.clk, - [7] = &exynos5_clk_mout_epll.clk, - [8] = &exynos5_clk_sclk_vpll.clk, - [9] = &exynos5_clk_mout_cpll.clk, -}; - -struct clksrc_sources exynos5_clkset_group = { - .sources = exynos5_clkset_group_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list), -}; - -/* Possible clock sources for aclk_266_gscl_sub Mux */ -static struct clk *clk_src_gscl_266_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = &exynos5_clk_aclk_266.clk, -}; - -static struct clksrc_sources clk_src_gscl_266 = { - .sources = clk_src_gscl_266_list, - .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list), -}; - -/* For ACLK_400_ISP */ -static struct clksrc_clk exynos5_clk_mout_aclk_400_isp = { - .clk = { - .name = "mout_aclk_400_isp", - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 24, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_dout_aclk_400_isp = { - .clk = { - .name = "dout_aclk_400_isp", - .parent = &exynos5_clk_mout_aclk_400_isp.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 20, .size = 3 }, -}; - -static struct clk *exynos5_clkset_aclk_400_isp_list[] = { - [0] = &clk_ext_xtal_mux, - [1] = &exynos5_clk_dout_aclk_400_isp.clk, -}; - -static struct clksrc_sources exynos5_clkset_aclk_400_isp = { - .sources = exynos5_clkset_aclk_400_isp_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_400_isp_list), -}; - -static struct clksrc_clk exynos5_clk_aclk_400_isp = { - .clk = { - .name = "aclk_400_isp", - }, - .sources = &exynos5_clkset_aclk_400_isp, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 20, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_uart_isp = { - .clk = { - .name = "sclk_uart_src_isp", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_SCLK_SRC_ISP, .shift = 8, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_aclk_266_isp = { - .clk = { - .name = "aclk_266_isp", - - }, - .sources = &clk_src_gscl_266, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 16, .size = 1 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_mmc0 = { - .clk = { - .name = "sclk_mmc0", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_mmc1 = { - .clk = { - .name = "sclk_mmc1", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_mmc2 = { - .clk = { - .name = "sclk_mmc2", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_mmc3 = { - .clk = { - .name = "sclk_mmc3", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_mmc4 = { - .clk = { - .name = "sclk_mmc4", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_spi0 = { - .clk = { - .name = "sclk_spi0", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_spi1 = { - .clk = { - .name = "sclk_spi1", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_spi2 = { - .clk = { - .name = "sclk_spi2", - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clksrcs[] = { - { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.0", - .enable = exynos5_clksrc_mask_peric0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, - .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, - .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.1", - .enable = exynos5_clksrc_mask_peric0_ctrl, - .ctrlbit = (1 << 4), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, - .shift = 4, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, - .shift = 4, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.2", - .enable = exynos5_clksrc_mask_peric0_ctrl, - .ctrlbit = (1 << 8), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 }, - }, { - .clk = { - .name = "uclk1", - .devname = "s5pv210-uart.3", - .enable = exynos5_clksrc_mask_peric0_ctrl, - .ctrlbit = (1 << 12), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 }, - }, { - .clk = { - .name = "sclk_usbdrd30", - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 28), - }, - .sources = &exynos5_clkset_usbdrd30, - .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.0", - .parent = &exynos5_clk_sclk_mmc0.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 0), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.1", - .parent = &exynos5_clk_sclk_mmc1.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 4), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.2", - .parent = &exynos5_clk_sclk_mmc2.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 8), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_mmc", - .devname = "s3c-sdhci.3", - .parent = &exynos5_clk_sclk_mmc3.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 12), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, - }, { - .clk = { - .name = "sclk_dwmci", - .parent = &exynos5_clk_sclk_mmc4.clk, - .enable = exynos5_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 16), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_pcm", - .parent = &exynos5_clk_sclk_audio0.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 4, .size = 8 }, - }, { - .clk = { - .name = "sclk_pcm", - .parent = &exynos5_clk_sclk_audio1.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 4, .size = 8 }, - }, { - .clk = { - .name = "sclk_pcm", - .parent = &exynos5_clk_sclk_audio2.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC4, .shift = 20, .size = 8 }, - }, { - .clk = { - .name = "sclk_i2s", - .parent = &exynos5_clk_sclk_audio1.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC5, .shift = 0, .size = 6 }, - }, { - .clk = { - .name = "sclk_i2s", - .parent = &exynos5_clk_sclk_audio2.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC5, .shift = 8, .size = 6 }, - }, { - .clk = { - .name = "sclk_fimd", - .devname = "s3cfb.1", - .enable = exynos5_clksrc_mask_disp1_0_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 }, - }, { - .clk = { - .name = "aclk_266_gscl", - .parent = &exynos5_clk_aclk_266.clk, - }, - .sources = &clk_src_gscl_266, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 }, - }, { - .clk = { - .name = "sclk_g3d", - .devname = "mali-t604.0", - .enable = exynos5_clk_gate_block, - .ctrlbit = (1 << 1), - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 }, - }, { - .clk = { - .name = "sclk_sata", - .devname = "ahci", - .parent = &exynos5_clk_mout_mpll_user.clk, - .enable = exynos5_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &exynos5_clkset_aclk, - .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 }, - }, { - .clk = { - .name = "sclk_gscl_wrap0", - .devname = "s5p-mipi-csis.0", - .enable = exynos5_clksrc_mask_gscl_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 }, - }, { - .clk = { - .name = "sclk_gscl_wrap1", - .devname = "s5p-mipi-csis.1", - .enable = exynos5_clksrc_mask_gscl_ctrl, - .ctrlbit = (1 << 28), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 }, - }, { - .clk = { - .name = "sclk_cam0", - .enable = exynos5_clksrc_mask_gscl_ctrl, - .ctrlbit = (1 << 16), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "sclk_cam1", - .enable = exynos5_clksrc_mask_gscl_ctrl, - .ctrlbit = (1 << 20), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 }, - }, { - .clk = { - .name = "aclk_266_isp_div0", - .parent = &exynos5_clk_aclk_266_isp.clk, - - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 0, .size = 3 }, - }, { - .clk = { - .name = "aclk_266_isp_div1", - .parent = &exynos5_clk_aclk_266_isp.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_ISP0, .shift = 4, .size = 3 }, - }, { - .clk = { - .name = "aclk_266_isp_divmpwm", - .parent = &exynos5_clk_aclk_266_isp.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_ISP2, .shift = 0, .size = 3 }, - }, { - .clk = { - .name = "aclk_400_isp_div0", - .parent = &exynos5_clk_aclk_400_isp.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 0, .size = 3 }, - }, { - .clk = { - .name = "aclk_400_isp_div1", - .parent = &exynos5_clk_aclk_400_isp.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_ISP1, .shift = 4, .size = 3 }, - }, { - .clk = { - .name = "sclk_uart_isp", - .parent = &exynos5_clk_sclk_uart_isp.clk, - }, - .reg_div = { .reg = EXYNOS5_SCLK_DIV_ISP, .shift = 24, .size = 4 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.0", - .parent = &exynos5_clk_sclk_spi0.clk, - .enable = exynos5_clksrc_mask_peric1_ctrl, - .ctrlbit = (1 << 16), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.1", - .parent = &exynos5_clk_sclk_spi1.clk, - .enable = exynos5_clksrc_mask_peric1_ctrl, - .ctrlbit = (1 << 20), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 }, - }, { - .clk = { - .name = "sclk_spi", - .devname = "s3c64xx-spi.2", - .parent = &exynos5_clk_sclk_spi2.clk, - .enable = exynos5_clksrc_mask_peric1_ctrl, - .ctrlbit = (1 << 24), - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, - }, -}; - -static struct clksrc_clk exynos5_clk_sclk_jpeg = { - .clk = { - .name = "sclk_jpeg", - .enable = exynos5_clksrc_mask_gen_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &exynos5_clkset_group, - .reg_src = { .reg = EXYNOS5_CLKSRC_GEN, .shift = 0, .size = 4 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 4 }, -}; - -static struct clksrc_clk exynos5_clk_sclk_c2c = { - .clk = { - .name = "sclk_c2c", - .id = -1, - }, - .sources = &exynos5_clkset_mout_mpll, - .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_SYSRGT, .shift = 4, .size = 3 }, -}; - -static struct clksrc_clk exynos5_clk_aclk_c2c = { - .clk = { - .name = "aclk_c2c", - .id = -1, - .parent = &exynos5_clk_sclk_c2c.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_SYSRGT, .shift = 8, .size = 3 }, -}; - -static struct clk *exynos5_clkset_c2c_list[] = { - [0] = &exynos5_clk_mout_mpll.clk, - [1] = &exynos5_clk_mout_bpll.clk, -}; - -static struct clksrc_sources exynos5_clkset_sclk_c2c = { - .sources = exynos5_clkset_c2c_list, - .nr_sources = ARRAY_SIZE(exynos5_clkset_c2c_list), -}; - -static struct clksrc_clk exynos5_clk_sclk_c2c_rev0 = { - .clk = { - .name = "sclk_c2c", - .id = -1, - }, - .sources = &exynos5_clkset_sclk_c2c, - .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 12, .size = 1 }, - .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 8, .size = 3 }, -}; - -static struct clksrc_clk exynos5_clk_aclk_c2c_rev0 = { - .clk = { - .name = "aclk_c2c", - .id = -1, - .parent = &exynos5_clk_sclk_c2c.clk, - }, - .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 12, .size = 3 }, -}; - -/* Clock initialization code */ -static struct clksrc_clk *exynos5_sysclks[] = { - &exynos5_clk_audiocdclk0, - &exynos5_clk_mout_apll, - &exynos5_clk_sclk_apll, - &exynos5_clk_mout_bpll, - &exynos5_clk_mout_bpll_user, - &exynos5_clk_mout_gpll, - &exynos5_clk_mout_cpll, - &exynos5_clk_mout_epll, - &exynos5_clk_mout_mpll_fout, - &exynos5_clk_mout_bpll_fout, - &exynos5_clk_mout_mpll, - &exynos5_clk_mout_mpll_user, - &exynos5_clk_mout_vpllsrc, - &exynos5_clk_sclk_vpll, - &exynos5_clk_mout_cpu, - &exynos5_clk_dout_armclk, - &exynos5_clk_dout_arm2clk, - &exynos5_clk_mclk_cdrex, - &exynos5_clk_aclk_400, - &exynos5_clk_aclk_400_g3d_mid, - &exynos5_clk_mout_aclk_333, - &exynos5_clk_dout_aclk_333, - &exynos5_clk_aclk_333, - &exynos5_clk_mout_aclk_300_disp1_mid, - &exynos5_clk_mout_aclk_300_disp1_mid1, - &exynos5_clk_mout_aclk_300_disp1, - &exynos5_clk_dout_aclk_300_disp1, - &exynos5_clk_aclk_300_disp1, - &exynos5_clk_mout_aclk_300_gscl_mid, - &exynos5_clk_mout_aclk_300_gscl_mid1, - &exynos5_clk_mout_aclk_300_gscl, - &exynos5_clk_dout_aclk_300_gscl, - &exynos5_clk_aclk_300_gscl, - &exynos5_clk_aclk_266, - &exynos5_clk_aclk_200, - &exynos5_clk_aclk_166, - &exynos5_clk_dout_aclk_66_pre, - &exynos5_clk_aclk_200_disp1, - &exynos5_clk_mout_aclk_400_isp, - &exynos5_clk_dout_aclk_400_isp, - &exynos5_clk_aclk_400_isp, - &exynos5_clk_aclk_66, - &exynos5_clk_sclk_mmc0, - &exynos5_clk_sclk_mmc1, - &exynos5_clk_sclk_mmc2, - &exynos5_clk_sclk_mmc3, - &exynos5_clk_sclk_mmc4, - &exynos5_clk_mout_audss, - &exynos5_clk_sclk_audss_bus, - &exynos5_clk_sclk_audss_i2s, - &exynos5_clk_dout_audss_srp, - &exynos5_clk_sclk_audio0, - &exynos5_clk_sclk_audio1, - &exynos5_clk_sclk_audio2, - &exynos5_clk_sclk_spdif, - &exynos5_clk_aclk_acp, - &exynos5_clk_pclk_acp, - &exynos5_clk_aclk_266_isp, - &exynos5_clk_sclk_uart_isp, - &exynos5_clk_sclk_c2c, - &exynos5_clk_aclk_c2c, - &exynos5_clk_sclk_spi0, - &exynos5_clk_sclk_spi1, - &exynos5_clk_sclk_spi2, - &exynos5_clk_sclk_jpeg, -}; - -static unsigned long exynos5_epll_get_rate(struct clk *clk) -{ - return clk->rate; -} - -static struct clk *exynos5_clks[] __initdata = { - &exynos5_clk_sclk_hdmi27m, - &exynos5_clk_sclk_hdmiphy, - &clk_fout_bpll, - &clk_fout_cpll, - &clk_fout_mpll_div2, - &clk_fout_bpll_div2, - &clk_fout_gpll, - &exynos5_clk_armclk, -}; - -static u32 epll_div[][6] = { - { 192000000, 0, 48, 3, 1, 0 }, - { 180000000, 0, 45, 3, 1, 0 }, - { 73728000, 1, 73, 3, 3, 47710 }, - { 67737600, 1, 90, 4, 3, 20762 }, - { 49152000, 0, 49, 3, 3, 9961 }, - { 45158400, 0, 45, 3, 3, 10381 }, - { 180633600, 0, 45, 3, 1, 10381 }, -}; - -static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int epll_con, epll_con_k; - unsigned int i; - unsigned int tmp; - unsigned int epll_rate; - unsigned int locktime; - unsigned int lockcnt; - - /* Return if nothing changed */ - if (clk->rate == rate) - return 0; - - if (clk->parent) - epll_rate = clk_get_rate(clk->parent); - else - epll_rate = clk_ext_xtal_mux.rate; - - if (epll_rate != 24000000) { - pr_err("Invalid Clock : recommended clock is 24MHz.\n"); - return -EINVAL; - } - - epll_con = __raw_readl(EXYNOS5_EPLL_CON0); - epll_con &= ~(0x1 << 27 | \ - PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ - PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ - PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); - - for (i = 0; i < ARRAY_SIZE(epll_div); i++) { - if (epll_div[i][0] == rate) { - epll_con_k = epll_div[i][5] << 0; - epll_con |= epll_div[i][1] << 27; - epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT; - epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT; - epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT; - break; - } - } - - if (i == ARRAY_SIZE(epll_div)) { - printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", - __func__); - return -EINVAL; - } - - epll_rate /= 1000000; - - /* 3000 max_cycls : specification data */ - locktime = 3000 / epll_rate * epll_div[i][3]; - lockcnt = locktime * 10000 / (10000 / epll_rate); - - __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK); - - __raw_writel(epll_con, EXYNOS5_EPLL_CON0); - __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1); - - do { - tmp = __raw_readl(EXYNOS5_EPLL_CON0); - } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT)); - - clk->rate = rate; - - return 0; -} - -static struct clk_ops exynos5_epll_ops = { - .get_rate = exynos5_epll_get_rate, - .set_rate = exynos5_epll_set_rate, -}; - -static int xtal_rate; - -static unsigned long exynos5_fout_apll_get_rate(struct clk *clk) -{ - return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0)); -} - -static struct clk_ops exynos5_fout_apll_ops = { - .get_rate = exynos5_fout_apll_get_rate, -}; - -static struct vpll_div_data exynos5_vpll_div[] = { - {268000000, 6, 268, 2, 41104, 0, 0, 0}, - {86000000, 6, 344, 4, 2936, 0, 0, 0}, -}; - -static unsigned long exynos5_vpll_get_rate(struct clk *clk) -{ - return clk->rate; -} - -static int exynos5_vpll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int vpll_con0, vpll_con1; - unsigned int tmp; - - /* Return if nothing changed */ - if (clk->rate == rate) - return 0; - - vpll_con0 = __raw_readl(EXYNOS5_VPLL_CON0); - vpll_con0 &= ~(PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT | \ - PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT | \ - PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); - - vpll_con1 = __raw_readl(EXYNOS5_VPLL_CON1); - vpll_con1 &= ~(0xffff << 0); -#if 0 - for (i = 0; i < ARRAY_SIZE(exynos5_vpll_div); i++) { - if (exynos5_vpll_div[i].rate == rate) { - vpll_con0 |= exynos5_vpll_div[i].pdiv << PLL36XX_PDIV_SHIFT; - vpll_con0 |= exynos5_vpll_div[i].mdiv << PLL36XX_MDIV_SHIFT; - vpll_con0 |= exynos5_vpll_div[i].sdiv << PLL36XX_SDIV_SHIFT; - vpll_con1 |= exynos5_vpll_div[i].k << 0; - break; - } - } - - if (i == ARRAY_SIZE(exynos5_vpll_div)) { - printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", - __func__); - return -EINVAL; - } - - /* 3000 max_cycls : specification data */ - locktime = 3000 * exynos5_vpll_div[i].pdiv + 1; - - __raw_writel(locktime, EXYNOS5_VPLL_LOCK); -#endif -#if defined(CONFIG_DP_40HZ_P11) || defined(CONFIG_DP_40HZ_P10) - vpll_con0 = 0xA0b30602; - vpll_con1 = 0x15b5; -#elif defined(CONFIG_DP_60HZ_P11) || defined(CONFIG_DP_60HZ_P10) - vpll_con0 = 0xA10c0602; - vpll_con1 = 0xA090; -#endif - - - __raw_writel(vpll_con0, EXYNOS5_VPLL_CON0); - __raw_writel(vpll_con1, EXYNOS5_VPLL_CON1); - - do { - tmp = __raw_readl(EXYNOS5_VPLL_CON0); - } while (!(tmp & (0x1 << EXYNOS5_VPLLCON0_LOCKED_SHIFT))); - - clk->rate = rate; - - return 0; -} - -static struct clk_ops exynos5_vpll_ops = { - .get_rate = exynos5_vpll_get_rate, - .set_rate = exynos5_vpll_set_rate, -}; - -static u32 exynos5_gpll_div[][6] = { - /*rate, P, M, S, AFC_DNB, AFC*/ - {1400000000, 3, 175, 0, 0, 0}, /* for 466MHz */ - {800000000, 3, 100, 0, 0, 0}, /* for 400MHz, 200MHz */ - {667000000, 7, 389, 1, 0, 0}, /* for 333MHz, 222MHz, 166MHz */ - {600000000, 4, 200, 1, 0, 0}, /* for 300MHz, 200MHz, 150MHz */ - {533000000, 12, 533, 1, 0, 0}, /* for 533MHz, 266MHz, 133MHz */ - {450000000, 12, 450, 1, 0, 0}, /* for 450 Hz */ - {400000000, 3, 100, 1, 0, 0}, - {333000000, 4, 222, 2, 0, 0}, - {200000000, 3, 100, 2, 0, 0}, -}; - -static unsigned long exynos5_gpll_get_rate(struct clk *clk) -{ - return clk->rate; -} - -static int exynos5_gpll_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned int gpll_con0; - unsigned int locktime; - unsigned int tmp; - unsigned int i; - - /* Return if nothing changed */ - if (clk->rate == rate) - return 0; - - gpll_con0 = __raw_readl(EXYNOS5_GPLL_CON0); - gpll_con0 &= ~(PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT | \ - PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT | \ - PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); - - for (i = 0; i < ARRAY_SIZE(exynos5_gpll_div); i++) { - if (exynos5_gpll_div[i][0] == rate) { - gpll_con0 |= exynos5_gpll_div[i][1] << PLL35XX_PDIV_SHIFT; - gpll_con0 |= exynos5_gpll_div[i][2] << PLL35XX_MDIV_SHIFT; - gpll_con0 |= exynos5_gpll_div[i][3] << PLL35XX_SDIV_SHIFT; - break; - } - } - - if (i == ARRAY_SIZE(exynos5_gpll_div)) { - printk(KERN_ERR "%s: Invalid Clock GPLL Frequency\n", - __func__); - return -EINVAL; - } - - /* 250 max_cycls : specification data */ - /* 270@p=1, 1cycle=1/24=41.6ns */ - /* calc >> p=5, 270 * 5 = 1350cycle * 41.6ns = 56.16us */ - - locktime = 270 * exynos5_gpll_div[i][1] + 1; - - __raw_writel(locktime, EXYNOS5_GPLL_LOCK); - - __raw_writel(gpll_con0, EXYNOS5_GPLL_CON0); - - do { - tmp = __raw_readl(EXYNOS5_GPLL_CON0); - } while (!(tmp & (0x1 << EXYNOS5_GPLLCON0_LOCKED_SHIFT))); - - clk->rate = rate; - - return 0; -} - -static struct clk_ops exynos5_gpll_ops = { - .get_rate = exynos5_gpll_get_rate, - .set_rate = exynos5_gpll_set_rate, -}; - -#ifdef CONFIG_PM -static int exynos5_clock_suspend(void) -{ - s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save)); - - if (samsung_rev() < EXYNOS5250_REV_1_0) - s3c_pm_do_save(exynos5250_clock_save_rev0, - ARRAY_SIZE(exynos5250_clock_save_rev0)); - - s3c_pm_do_save(exynos5_epll_save, ARRAY_SIZE(exynos5_epll_save)); - s3c_pm_do_save(exynos5_vpll_save, ARRAY_SIZE(exynos5_vpll_save)); - - if (samsung_rev() >= EXYNOS5250_REV_1_0) - s3c_pm_do_save(exynos5_gpll_save, ARRAY_SIZE(exynos5_gpll_save)); - return 0; -} - -static void exynos5_clock_resume(void) -{ - unsigned int tmp; - - s3c_pm_do_restore_core(exynos5_epll_save, ARRAY_SIZE(exynos5_epll_save)); - s3c_pm_do_restore_core(exynos5_vpll_save, ARRAY_SIZE(exynos5_vpll_save)); - - if (samsung_rev() >= EXYNOS5250_REV_1_0) - s3c_pm_do_restore_core(exynos5_gpll_save, ARRAY_SIZE(exynos5_gpll_save)); - - /* waiting epll & vpll locking time */ - do { - tmp = __raw_readl(EXYNOS5_EPLL_CON0); - } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT)); - - do { - tmp = __raw_readl(EXYNOS5_VPLL_CON0); - } while (!(tmp & 0x1 << EXYNOS5_VPLLCON0_LOCKED_SHIFT)); - - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - do { - tmp = __raw_readl(EXYNOS5_GPLL_CON0); - } while (!(tmp & (0x1 << EXYNOS5_GPLLCON0_LOCKED_SHIFT))); - } - - if (samsung_rev() < EXYNOS5250_REV_1_0) - s3c_pm_do_restore_core(exynos5250_clock_save_rev0, - ARRAY_SIZE(exynos5250_clock_save_rev0)); - - s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save)); -} -#else -#define exynos5_clock_suspend NULL -#define exynos5_clock_resume NULL -#endif - -struct syscore_ops exynos5_clock_syscore_ops = { - .suspend = exynos5_clock_suspend, - .resume = exynos5_clock_resume, -}; - -void __init_or_cpufreq exynos5_setup_clocks(void) -{ - struct clk *xtal_clk; - unsigned long apll; - unsigned long bpll; - unsigned long cpll; - unsigned long mpll; - unsigned long epll; - unsigned long vpll; - unsigned long gpll; - unsigned long vpllsrc; - unsigned long xtal; - unsigned long armclk; - unsigned long mclk_cdrex; - unsigned long aclk_400; - unsigned long aclk_333; - unsigned long aclk_266; - unsigned long aclk_200; - unsigned long aclk_166; - unsigned long aclk_66; - unsigned int ptr; - - printk(KERN_DEBUG "%s: registering clocks\n", __func__); - - xtal_clk = clk_get(NULL, "xtal"); - BUG_ON(IS_ERR(xtal_clk)); - - xtal = clk_get_rate(xtal_clk); - - xtal_rate = xtal; - - clk_put(xtal_clk); - - printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - -#if defined(CONFIG_MACH_P10_DP_01) - /* setting vpll 268627200 Hz */ - if (exynos5_vpll_set_rate(&clk_fout_vpll, 268000000)) - printk(KERN_ERR "Unable to set %s of clock vpll.\n", clk_fout_vpll.name); -#elif defined(CONFIG_MACH_P10_DP_00) - /* setting vpll 86011199 Hz */ - if (exynos5_vpll_set_rate(&clk_fout_vpll, 86000000)) - printk(KERN_ERR "Unable to set %s of clock vpll.\n", clk_fout_vpll.name); -#endif - - /* Set and check PLLs */ - apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0)); - bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0)); - cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0)); - mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0)); - epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0), - __raw_readl(EXYNOS5_EPLL_CON1)); - - if ((soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0)) - gpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_GPLL_CON0)); - else - gpll = 0; - - vpllsrc = clk_get_rate(&exynos5_clk_mout_vpllsrc.clk); - vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0), - __raw_readl(EXYNOS5_VPLL_CON1)); - - clk_fout_apll.ops = &exynos5_fout_apll_ops; - clk_fout_bpll.rate = bpll; - clk_fout_bpll_div2.rate = bpll / 2; - clk_fout_cpll.rate = cpll; - clk_fout_mpll.rate = mpll; - clk_fout_mpll_div2.rate = mpll / 2; - clk_fout_epll.rate = epll; - clk_fout_vpll.rate = vpll; - - if (soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) { - gpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_GPLL_CON0)); - clk_fout_gpll.rate = gpll; - - printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n" - "M=%ld, E=%ld, V=%ld, G=%ld\n", - apll, bpll, cpll, mpll, epll, vpll, gpll); - } else { - printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n" - "M=%ld, E=%ld, V=%ld\n", - apll, bpll, cpll, mpll, epll, vpll); - } - - /* Set parent for bus clocks */ - if ((soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0)) - clk_set_parent(&exynos5_clk_mout_mpll.clk, - &exynos5_clk_mout_mpll_fout.clk); - - armclk = clk_get_rate(&exynos5_clk_armclk); - mclk_cdrex = clk_get_rate(&exynos5_clk_mclk_cdrex.clk); - - aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk); - aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk); - aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk); - aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk); - aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk); - aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk); - - printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n" - "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n" - "ACLK166=%ld, ACLK66=%ld\n", - armclk, mclk_cdrex, aclk_400, - aclk_333, aclk_266, aclk_200, - aclk_166, aclk_66); - - clk_fout_epll.ops = &exynos5_epll_ops; - clk_fout_vpll.ops = &exynos5_vpll_ops; - clk_fout_gpll.ops = &exynos5_gpll_ops; - - if (clk_set_parent(&exynos5_clk_mout_audss.clk, &clk_fout_epll)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - clk_fout_epll.name, exynos5_clk_mout_audss.clk.name); -#if defined(CONFIG_SND_SAMSUNG_PCM) && !defined(CONFIG_SND_SAMSUNG_PCM_USE_EPLL) - if (clk_set_parent(&exynos5_clk_sclk_audio0.clk, &exynos5_clk_audiocdclk0.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_audiocdclk0.clk.name, exynos5_clk_sclk_audio0.clk.name); -#else - if (clk_set_parent(&exynos5_clk_sclk_audio0.clk, &exynos5_clk_mout_epll.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_mout_epll.clk.name, exynos5_clk_sclk_audio0.clk.name); -#endif - if (clk_set_parent(&exynos5_clk_sclk_audio1.clk, &exynos5_clk_mout_epll.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_mout_epll.clk.name, exynos5_clk_sclk_audio1.clk.name); - if (clk_set_parent(&exynos5_clk_sclk_audio2.clk, &exynos5_clk_mout_epll.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_mout_epll.clk.name, exynos5_clk_sclk_audio2.clk.name); - if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - clk_fout_epll.name, exynos5_clk_mout_epll.clk.name); - - if (clk_set_parent(&exynos5_clk_mout_aclk_400_isp.clk, &exynos5_clk_mout_mpll_user.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_mout_mpll_user.clk.name, exynos5_clk_mout_aclk_400_isp.clk.name); - if (clk_set_parent(&exynos5_clk_aclk_266_isp.clk, &exynos5_clk_aclk_266.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_aclk_266.clk.name, exynos5_clk_aclk_266_isp.clk.name); - if (clk_set_parent(&exynos5_clk_aclk_400_isp.clk, &exynos5_clk_dout_aclk_400_isp.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_mout_aclk_400_isp.clk.name, exynos5_clk_aclk_400_isp.clk.name); - if (clk_set_parent(&exynos5_clk_sclk_uart_isp.clk, &exynos5_clk_mout_mpll_user.clk)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - exynos5_clk_mout_mpll_user.clk.name, exynos5_clk_sclk_uart_isp.clk.name); - - clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000); - clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000); - - clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000); - clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000); - - for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++) - s3c_set_clksrc(&exynos5_clksrcs[ptr], true); -} - -void __init exynos5_register_clocks(void) -{ - int ptr; - - if (soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) { - exynos5_clk_mout_mpll.sources = &exynos5_clkset_mout_mpll; - exynos5_clk_mout_bpll.sources = &exynos5_clkset_mout_bpll; - exynos5_clk_aclk_400.sources = &exynos5_clkset_aclk_g3d; - exynos5_clk_mout_aclk_300_gscl.sources = &exynos5_clkset_aclk_300_gscl_rev1; - exynos5_clk_mout_aclk_300_disp1.sources = &exynos5_clkset_mout_aclk_300_disp1_rev1; - } else if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0) { - exynos5_clk_sclk_jpeg.sources = NULL; - exynos5_clk_sclk_jpeg.reg_src.reg = 0; - exynos5_clk_sclk_jpeg.clk.parent = &exynos5_clk_mout_cpll.clk; - exynos5_clk_sclk_jpeg.clk.enable = NULL; - exynos5_clk_sclk_jpeg.clk.ctrlbit = 0; - } - - s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks)); - - for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++) - s3c_register_clksrc(exynos5_sysclks[ptr], 1); - - for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++) - s3c_register_clksrc(exynos5_sclk_tv[ptr], 1); - - s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs)); - s3c_register_clocks(exynos5_init_clocks, ARRAY_SIZE(exynos5_init_clocks)); - - s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off)); - s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off)); - - /* TN Feature.. these clocks was enabled at booloader */ - s3c_register_clocks(exynos5_init_clock_on, ARRAY_SIZE(exynos5_init_clock_on)); - - s3c_register_clocks(exynos5_init_audss_clocks, ARRAY_SIZE(exynos5_init_audss_clocks)); - s3c_disable_clocks(exynos5_init_audss_clocks, ARRAY_SIZE(exynos5_init_audss_clocks)); - - if (soc_is_exynos5250() && (samsung_rev() < EXYNOS5250_REV_1_0)) - exynos5_init_dmaclocks[2].ctrlbit = exynos5_init_dmaclocks[1].ctrlbit; - s3c_register_clocks(exynos5_init_dmaclocks, ARRAY_SIZE(exynos5_init_dmaclocks)); - s3c_disable_clocks(exynos5_init_dmaclocks, ARRAY_SIZE(exynos5_init_dmaclocks)); - - s3c_register_clocks(exynos5_i2cs_clocks, ARRAY_SIZE(exynos5_i2cs_clocks)); - s3c_disable_clocks(exynos5_i2cs_clocks, ARRAY_SIZE(exynos5_i2cs_clocks)); - - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - s3c_register_clocks(exynos5_uis_clocks, ARRAY_SIZE(exynos5_uis_clocks)); - s3c_disable_clocks(exynos5_uis_clocks, ARRAY_SIZE(exynos5_uis_clocks)); - } - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - s3c_register_clksrc(&exynos5_clk_sclk_c2c_rev0, 1); - s3c_register_clksrc(&exynos5_clk_aclk_c2c_rev0, 1); - } - -#ifndef CONFIG_SAMSUNG_C2C - if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) { - exynos5_c2c_clock.enable = exynos5_clk_ip_sysrgt_ctrl; - exynos5_c2c_clock.ctrlbit = ((1 << 2) | (1 << 1)); - } - - s3c24xx_register_clock(&exynos5_c2c_clock); - s3c_disable_clocks(&exynos5_c2c_clock, 1); -#endif - - register_syscore_ops(&exynos5_clock_syscore_ops); - s3c_pwmclk_init(); -} - -static int __init clock_domain_init(void) -{ - int index; - - /* Add dma clock */ - for (index = 0; index < ARRAY_SIZE(exynos5_init_dmaclocks); index++) - clock_add_domain(LPA_DOMAIN, &exynos5_init_dmaclocks[index]); - - /* Add i2c clock */ - for (index = 0; index < ARRAY_SIZE(exynos5_i2cs_clocks); index++) - clock_add_domain(LPA_DOMAIN, &exynos5_i2cs_clocks[index]); - - return 0; -} -late_initcall(clock_domain_init); diff --git a/arch/arm/mach-exynos/coresight-etb.c b/arch/arm/mach-exynos/coresight-etb.c new file mode 100644 index 0000000..2e887aa --- /dev/null +++ b/arch/arm/mach-exynos/coresight-etb.c @@ -0,0 +1,441 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/miscdevice.h> +#include <linux/uaccess.h> +#include <linux/slab.h> +#include <linux/delay.h> + +#include "coresight.h" +#include <mach/sec_debug.h> + +#define etb_writel(etb, val, off) __raw_writel((val), etb.base + off) +#define etb_readl(etb, off) __raw_readl(etb.base + off) + +#define ETB_RAM_DEPTH_REG (0x004) +#define ETB_STATUS_REG (0x00C) +#define ETB_RAM_READ_DATA_REG (0x010) +#define ETB_RAM_READ_POINTER (0x014) +#define ETB_RAM_WRITE_POINTER (0x018) +#define ETB_TRG (0x01C) +#define ETB_CTL_REG (0x020) +#define ETB_RWD_REG (0x024) +#define ETB_FFSR (0x300) +#define ETB_FFCR (0x304) +#define ETB_ITMISCOP0 (0xEE0) +#define ETB_ITTRFLINACK (0xEE4) +#define ETB_ITTRFLIN (0xEE8) +#define ETB_ITATBDATA0 (0xEEC) +#define ETB_ITATBCTR2 (0xEF0) +#define ETB_ITATBCTR1 (0xEF4) +#define ETB_ITATBCTR0 (0xEF8) + + +#define BYTES_PER_WORD 4 +#define ETB_SIZE_WORDS 4096 +#define FRAME_SIZE_WORDS 4 + +#define ETB_LOCK() \ +do { \ + mb(); \ + etb_writel(etb, 0x0, CS_LAR); \ +} while (0) +#define ETB_UNLOCK() \ +do { \ + etb_writel(etb, CS_UNLOCK_MAGIC, CS_LAR); \ + mb(); \ +} while (0) + +struct etb_ctx { + uint8_t *buf; + void __iomem *base; + bool enabled; + bool reading; + spinlock_t spinlock; + atomic_t in_use; + struct device *dev; + struct kobject *kobj; + uint32_t trigger_cntr; +}; + +static struct etb_ctx etb; +static unsigned int etbbuf_paddr; +static unsigned int etbbuf_size; + +static void __etb_enable(void) +{ + int i; + + ETB_UNLOCK(); + + etb_writel(etb, 0x0, ETB_RAM_WRITE_POINTER); + for (i = 0; i < ETB_SIZE_WORDS; i++) + etb_writel(etb, 0x0, ETB_RWD_REG); + + etb_writel(etb, 0x0, ETB_RAM_WRITE_POINTER); + etb_writel(etb, 0x0, ETB_RAM_READ_POINTER); + + etb_writel(etb, etb.trigger_cntr, ETB_TRG); + etb_writel(etb, BIT(13) | BIT(0), ETB_FFCR); + etb_writel(etb, BIT(0), ETB_CTL_REG); + + ETB_LOCK(); +} + +void etb_enable(void) +{ + unsigned long flags; + + spin_lock_irqsave(&etb.spinlock, flags); + __etb_enable(); + etb.enabled = true; + spin_unlock_irqrestore(&etb.spinlock, flags); +} + +void __etb_disable(void) +{ + int count; + uint32_t ffcr; + + ETB_UNLOCK(); + + ffcr = etb_readl(etb, ETB_FFCR); + ffcr |= (BIT(12) | BIT(6)); + etb_writel(etb, ffcr, ETB_FFCR); + + for (count = TIMEOUT_US; BVAL(etb_readl(etb, ETB_FFCR), 6) != 0 + && count > 0; count--) + udelay(1); + WARN(count == 0, "timeout while flushing ETB, ETB_FFCR: %#x\n", + etb_readl(etb, ETB_FFCR)); + + etb_writel(etb, 0x0, ETB_CTL_REG); + + for (count = TIMEOUT_US; BVAL(etb_readl(etb, ETB_FFSR), 1) != 1 + && count > 0; count--) + udelay(1); + WARN(count == 0, "timeout while disabling ETB, ETB_FFSR: %#x\n", + etb_readl(etb, ETB_FFSR)); + + ETB_LOCK(); +} + +void etb_disable(void) +{ + unsigned long flags; + + spin_lock_irqsave(&etb.spinlock, flags); + __etb_disable(); + etb.enabled = false; + spin_unlock_irqrestore(&etb.spinlock, flags); +} + +static void __etb_dump(void) +{ + int i; + uint8_t *buf_ptr; + uint32_t read_data; + uint32_t read_ptr; + uint32_t write_ptr; + uint32_t frame_off; + uint32_t frame_endoff; + + ETB_UNLOCK(); + + read_ptr = etb_readl(etb, ETB_RAM_READ_POINTER); + write_ptr = etb_readl(etb, ETB_RAM_WRITE_POINTER); + + frame_off = write_ptr % FRAME_SIZE_WORDS; + frame_endoff = FRAME_SIZE_WORDS - frame_off; + if (frame_off) { + dev_err(etb.dev, "write_ptr: %lu not aligned to formatter " + "frame size\n", (unsigned long)write_ptr); + dev_err(etb.dev, "frameoff: %lu, frame_endoff: %lu\n", + (unsigned long)frame_off, (unsigned long)frame_endoff); + write_ptr += frame_endoff; + } + + if ((etb_readl(etb, ETB_STATUS_REG) & BIT(0)) == 0) + etb_writel(etb, 0x0, ETB_RAM_READ_POINTER); + else + etb_writel(etb, write_ptr, ETB_RAM_READ_POINTER); + + buf_ptr = etb.buf; + for (i = 0; i < ETB_SIZE_WORDS; i++) { + read_data = etb_readl(etb, ETB_RAM_READ_DATA_REG); + *buf_ptr++ = read_data >> 0; + *buf_ptr++ = read_data >> 8; + *buf_ptr++ = read_data >> 16; + *buf_ptr++ = read_data >> 24; + } + + if (frame_off) { + buf_ptr -= (frame_endoff * BYTES_PER_WORD); + for (i = 0; i < frame_endoff; i++) { + *buf_ptr++ = 0x0; + *buf_ptr++ = 0x0; + *buf_ptr++ = 0x0; + *buf_ptr++ = 0x0; + } + } + + etb_writel(etb, read_ptr, ETB_RAM_READ_POINTER); + + ETB_LOCK(); +} + +void etb_dump(void) +{ + unsigned long flags; + + spin_lock_irqsave(&etb.spinlock, flags); + if (etb.enabled) { + __etb_disable(); + __etb_dump(); + __etb_enable(); + + } + spin_unlock_irqrestore(&etb.spinlock, flags); +} + +static int etb_open(struct inode *inode, struct file *file) +{ + if (atomic_cmpxchg(&etb.in_use, 0, 1)) + return -EBUSY; + + dev_dbg(etb.dev, "%s: successfully opened\n", __func__); + return 0; +} + +static ssize_t etb_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + if (etb.reading == false) { + etb_dump(); + etb.reading = true; + } + + if (*ppos + len > ETB_SIZE_WORDS * BYTES_PER_WORD) + len = ETB_SIZE_WORDS * BYTES_PER_WORD - *ppos; + + if (copy_to_user(data, etb.buf + *ppos, len)) { + dev_dbg(etb.dev, "%s: copy_to_user failed\n", __func__); + return -EFAULT; + } + + *ppos += len; + + dev_dbg(etb.dev, "%s: %d bytes copied, %d bytes left\n", + __func__, len, (int) (ETB_SIZE_WORDS * BYTES_PER_WORD - *ppos)); + + return len; +} + +static int etb_release(struct inode *inode, struct file *file) +{ + etb.reading = false; + + atomic_set(&etb.in_use, 0); + + dev_dbg(etb.dev, "%s: released\n", __func__); + + return 0; +} + +static const struct file_operations etb_fops = { + .owner = THIS_MODULE, + .open = etb_open, + .read = etb_read, + .release = etb_release, +}; + +static struct miscdevice etb_misc = { + .name = "coresight_etb", + .minor = MISC_DYNAMIC_MINOR, + .fops = &etb_fops, +}; + +static int __init etb_buf_setup(char *str) +{ + unsigned size = memparse(str, &str); + + pr_emerg("%s: str=%s\n", __func__, str); + + if (size && (size == roundup_pow_of_two(size)) && (*str == '@')) { + etbbuf_paddr = (unsigned int)memparse(++str, NULL); + etbbuf_size = size; + } + + pr_emerg("%s: secdbg_paddr = 0x%x\n", __func__, etbbuf_paddr); + pr_emerg("%s: secdbg_size = 0x%x\n", __func__, etbbuf_size); + + return 1; +} +__setup("etb_buf=", etb_buf_setup); + +#define ETB_ATTR(name) \ +static struct kobj_attribute name##_attr = \ + __ATTR(name, S_IRUGO | S_IWUSR, name##_show, name##_store) + +static ssize_t trigger_cntr_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + etb.trigger_cntr = val; + return n; +} +static ssize_t trigger_cntr_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val = etb.trigger_cntr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETB_ATTR(trigger_cntr); + +static int __init etb_sysfs_init(void) +{ + int ret; + + etb.kobj = kobject_create_and_add("etb", coresight_get_modulekobj()); + if (!etb.kobj) { + dev_err(etb.dev, "failed to create ETB sysfs kobject\n"); + ret = -ENOMEM; + goto err_create; + } + + ret = sysfs_create_file(etb.kobj, &trigger_cntr_attr.attr); + if (ret) { + dev_err(etb.dev, "failed to create ETB sysfs trigger_cntr" + " attribute\n"); + goto err_file; + } + + return 0; +err_file: + kobject_put(etb.kobj); +err_create: + return ret; +} + +static void etb_sysfs_exit(void) +{ + sysfs_remove_file(etb.kobj, &trigger_cntr_attr.attr); + kobject_put(etb.kobj); +} + +static int __devinit etb_probe(struct platform_device *pdev) +{ + int ret; + struct resource *res; + + if (!sec_debug_level.en.kernel_fault) { + pr_info("%s: debug level is low\n",__func__); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -EINVAL; + goto err_res; + } + + etb.base = ioremap_nocache(res->start, resource_size(res)); + if (!etb.base) { + ret = -EINVAL; + goto err_ioremap; + } + + etb.dev = &pdev->dev; + + spin_lock_init(&etb.spinlock); + + ret = misc_register(&etb_misc); + if (ret) + goto err_misc; + + /* Free up the 16 KB of kernel Space as there is already + * predefined buffer in LK why not reuse the same space + * if Lk did not reserve than we can + */ + + if (etbbuf_paddr == 0) { + etb.buf = kzalloc(ETB_SIZE_WORDS * BYTES_PER_WORD, GFP_KERNEL); + pr_info("%s: etb buffer not provided. Using kmalloc..\n", + __func__); + } else { + etb.buf = ioremap_nocache(etbbuf_paddr, etbbuf_size); + } + + if (!etb.buf) { + ret = -ENOMEM; + goto err_alloc; + } + + etb_sysfs_init(); + + dev_info(etb.dev, "ETB initialized\n"); + return 0; + +err_alloc: + misc_deregister(&etb_misc); +err_misc: + iounmap(etb.base); +err_ioremap: +err_res: + dev_err(etb.dev, "ETB init failed\n"); + return ret; +} + +static int etb_remove(struct platform_device *pdev) +{ + if (etb.enabled) + etb_disable(); + etb_sysfs_exit(); + kfree(etb.buf); + misc_deregister(&etb_misc); + iounmap(etb.base); + + return 0; +} + +static struct platform_driver etb_driver = { + .probe = etb_probe, + .remove = etb_remove, + .driver = { + .name = "coresight_etb", + }, +}; + +int __init etb_init(void) +{ + return platform_driver_register(&etb_driver); +} + +void etb_exit(void) +{ + platform_driver_unregister(&etb_driver); +} diff --git a/arch/arm/mach-exynos/coresight-etm.c b/arch/arm/mach-exynos/coresight-etm.c new file mode 100644 index 0000000..8165e19 --- /dev/null +++ b/arch/arm/mach-exynos/coresight-etm.c @@ -0,0 +1,1292 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/smp.h> +#include <linux/wakelock.h> +#include <linux/pm_qos_params.h> +#include <linux/sysfs.h> +#include <linux/stat.h> +#include <asm/sections.h> + +#include "coresight.h" +#include <mach/sec_debug.h> + +#define etm_writel(etm, cpu, val, off) \ + __raw_writel((val), etm.base + (SZ_4K * cpu) + off) +#define etm_readl(etm, cpu, off) \ + __raw_readl(etm.base + (SZ_4K * cpu) + off) + +/* + * Device registers: + * 0x000 - 0x2FC: Trace registers + * 0x300 - 0x314: Management registers + * 0x318 - 0xEFC: Trace registers + * + * Coresight registers + * 0xF00 - 0xF9C: Management registers + * 0xFA0 - 0xFA4: Management registers in PFTv1.0 + * Trace registers in PFTv1.1 + * 0xFA8 - 0xFFC: Management registers + */ + +/* Trace registers (0x000-0x2FC) */ +#define ETMCR (0x000) +#define ETMCCR (0x004) +#define ETMTRIGGER (0x008) +#define ETMSR (0x010) +#define ETMSCR (0x014) +#define ETMTSSCR (0x018) +#define ETMTEEVR (0x020) +#define ETMTECR1 (0x024) +#define ETMFFLR (0x02C) +#define ETMACVRn(n) (0x040 + (n * 4)) +#define ETMACTRn(n) (0x080 + (n * 4)) +#define ETMCNTRLDVRn(n) (0x140 + (n * 4)) +#define ETMCNTENRn(n) (0x150 + (n * 4)) +#define ETMCNTRLDEVRn(n) (0x160 + (n * 4)) +#define ETMCNTVRn(n) (0x170 + (n * 4)) +#define ETMSQ12EVR (0x180) +#define ETMSQ21EVR (0x184) +#define ETMSQ23EVR (0x188) +#define ETMSQ31EVR (0x18C) +#define ETMSQ32EVR (0x190) +#define ETMSQ13EVR (0x194) +#define ETMSQR (0x19C) +#define ETMEXTOUTEVRn(n) (0x1A0 + (n * 4)) +#define ETMCIDCVRn(n) (0x1B0 + (n * 4)) +#define ETMCIDCMR (0x1BC) +#define ETMIMPSPEC0 (0x1C0) +#define ETMIMPSPEC1 (0x1C4) +#define ETMIMPSPEC2 (0x1C8) +#define ETMIMPSPEC3 (0x1CC) +#define ETMIMPSPEC4 (0x1D0) +#define ETMIMPSPEC5 (0x1D4) +#define ETMIMPSPEC6 (0x1D8) +#define ETMIMPSPEC7 (0x1DC) +#define ETMSYNCFR (0x1E0) +#define ETMIDR (0x1E4) +#define ETMCCER (0x1E8) +#define ETMEXTINSELR (0x1EC) +#define ETMTESSEICR (0x1F0) +#define ETMEIBCR (0x1F4) +#define ETMTSEVR (0x1F8) +#define ETMAUXCR (0x1FC) +#define ETMTRACEIDR (0x200) +#define ETMVMIDCVR (0x240) +/* Management registers (0x300-0x314) */ +#define ETMOSLAR (0x300) +#define ETMOSLSR (0x304) +#define ETMOSSRR (0x308) +#define ETMPDCR (0x310) +#define ETMPDSR (0x314) + +#define ETM_MAX_ADDR_CMP (16) +#define ETM_MAX_CNTR (4) +#define ETM_MAX_CTXID_CMP (3) + +#define ETM_MODE_EXCLUDE BIT(0) +#define ETM_MODE_CYCACC BIT(1) +#define ETM_MODE_STALL BIT(2) +#define ETM_MODE_TIMESTAMP BIT(3) +#define ETM_MODE_CTXID BIT(4) +#define ETM_MODE_ALL (0x1F) + +#define ETM_EVENT_MASK (0x1FFFF) +#define ETM_SYNC_MASK (0xFFF) +#define ETM_ALL_MASK (0xFFFFFFFF) + +#define ETM_SEQ_STATE_MAX_VAL (0x2) + +enum { + ETM_ADDR_TYPE_NONE, + ETM_ADDR_TYPE_SINGLE, + ETM_ADDR_TYPE_RANGE, + ETM_ADDR_TYPE_START, + ETM_ADDR_TYPE_STOP, +}; + +#define ETM_LOCK(cpu) \ +do { \ + mb(); \ + etm_writel(etm, cpu, 0x0, CS_LAR); \ +} while (0) +#define ETM_UNLOCK(cpu) \ +do { \ + etm_writel(etm, cpu, CS_UNLOCK_MAGIC, CS_LAR); \ + mb(); \ +} while (0) + + +#ifdef MODULE_PARAM_PREFIX +#undef MODULE_PARAM_PREFIX +#endif +#define MODULE_PARAM_PREFIX "coresight." + +#ifdef CONFIG_CORESIGHT_ETM_DEFAULT_ENABLE +static int etm_boot_enable = 1; +#else +static int etm_boot_enable; +#endif +module_param_named( + etm_boot_enable, etm_boot_enable, int, S_IRUGO +); + +struct etm_ctx { + void __iomem *base; + bool enabled; + struct wake_lock wake_lock; + struct pm_qos_request_list qos_req; + struct mutex mutex; + struct device *dev; + struct kobject *kobj; + uint8_t arch; + uint8_t nr_addr_cmp; + uint8_t nr_cntr; + uint8_t nr_ext_inp; + uint8_t nr_ext_out; + uint8_t nr_ctxid_cmp; + uint8_t reset; + uint32_t mode; + uint32_t ctrl; + uint32_t trigger_event; + uint32_t startstop_ctrl; + uint32_t enable_event; + uint32_t enable_ctrl1; + uint32_t fifofull_level; + uint8_t addr_idx; + uint32_t addr_val[ETM_MAX_ADDR_CMP]; + uint32_t addr_acctype[ETM_MAX_ADDR_CMP]; + uint32_t addr_type[ETM_MAX_ADDR_CMP]; + uint8_t cntr_idx; + uint32_t cntr_rld_val[ETM_MAX_CNTR]; + uint32_t cntr_event[ETM_MAX_CNTR]; + uint32_t cntr_rld_event[ETM_MAX_CNTR]; + uint32_t cntr_val[ETM_MAX_CNTR]; + uint32_t seq_12_event; + uint32_t seq_21_event; + uint32_t seq_23_event; + uint32_t seq_31_event; + uint32_t seq_32_event; + uint32_t seq_13_event; + uint32_t seq_curr_state; + uint8_t ctxid_idx; + uint32_t ctxid_val[ETM_MAX_CTXID_CMP]; + uint32_t ctxid_mask; + uint32_t sync_freq; + uint32_t timestamp_event; +}; + +static struct etm_ctx etm = { + .trigger_event = 0x406F, + .enable_event = 0x6F, + .enable_ctrl1 = 0x1, + .fifofull_level = 0x28, + .addr_val = {(uint32_t) _stext, (uint32_t) _etext}, + .addr_type = {ETM_ADDR_TYPE_RANGE, ETM_ADDR_TYPE_RANGE}, + .cntr_event = {[0 ... (ETM_MAX_CNTR - 1)] = 0x406F}, + .cntr_rld_event = {[0 ... (ETM_MAX_CNTR - 1)] = 0x406F}, + .seq_12_event = 0x406F, + .seq_21_event = 0x406F, + .seq_23_event = 0x406F, + .seq_31_event = 0x406F, + .seq_32_event = 0x406F, + .seq_13_event = 0x406F, + .sync_freq = 0x80, + .timestamp_event = 0x406F, +}; + + +/* ETM clock is derived from the processor clock and gets enabled on a + * logical OR of below items on Krait (pass2 onwards): + * 1.CPMR[ETMCLKEN] is 1 + * 2.ETMCR[PD] is 0 + * 3.ETMPDCR[PU] is 1 + * 4.Reset is asserted (core or debug) + * 5.APB memory mapped requests (eg. EDAP access) + * + * 1., 2. and 3. above are permanent enables whereas 4. and 5. are temporary + * enables + * + * We rely on 5. to be able to access ETMCR and then use 2. above for ETM + * clock vote in the driver and the save-restore code uses 1. above + * for its vote + */ +static void etm_set_pwrdwn(int cpu) +{ + uint32_t etmcr; + + etmcr = etm_readl(etm, cpu, ETMCR); + etmcr |= BIT(0); + etm_writel(etm, cpu, etmcr, ETMCR); +} + +static void etm_clr_pwrdwn(int cpu) +{ + uint32_t etmcr; + + etmcr = etm_readl(etm, cpu, ETMCR); + etmcr &= ~BIT(0); + etm_writel(etm, cpu, etmcr, ETMCR); +} + +static void etm_set_prog(int cpu) +{ + uint32_t etmcr; + int count; + + etmcr = etm_readl(etm, cpu, ETMCR); + etmcr |= BIT(10); + etm_writel(etm, cpu, etmcr, ETMCR); + + for (count = TIMEOUT_US; BVAL(etm_readl(etm, cpu, ETMSR), 1) != 1 + && count > 0; count--) + udelay(1); + WARN(count == 0, "timeout while setting prog bit, ETMSR: %#x\n", + etm_readl(etm, cpu, ETMSR)); +} + +static void etm_clr_prog(int cpu) +{ + uint32_t etmcr; + int count; + + etmcr = etm_readl(etm, cpu, ETMCR); + etmcr &= ~BIT(10); + etm_writel(etm, cpu, etmcr, ETMCR); + + for (count = TIMEOUT_US; BVAL(etm_readl(etm, cpu, ETMSR), 1) != 0 + && count > 0; count--) + udelay(1); + WARN(count == 0, "timeout while clearing prog bit, ETMSR: %#x\n", + etm_readl(etm, cpu, ETMSR)); +} + +static void __etm_enable(int cpu) +{ + int i; + + ETM_UNLOCK(cpu); + /* Vote for ETM power/clock enable */ + etm_clr_pwrdwn(cpu); + etm_set_prog(cpu); + + etm_writel(etm, cpu, etm.ctrl | BIT(10), ETMCR); + etm_writel(etm, cpu, etm.trigger_event, ETMTRIGGER); + etm_writel(etm, cpu, etm.startstop_ctrl, ETMTSSCR); + etm_writel(etm, cpu, etm.enable_event, ETMTEEVR); + etm_writel(etm, cpu, etm.enable_ctrl1, ETMTECR1); + etm_writel(etm, cpu, etm.fifofull_level, ETMFFLR); + for (i = 0; i < etm.nr_addr_cmp; i++) { + etm_writel(etm, cpu, etm.addr_val[i], ETMACVRn(i)); + etm_writel(etm, cpu, etm.addr_acctype[i], ETMACTRn(i)); + } + for (i = 0; i < etm.nr_cntr; i++) { + etm_writel(etm, cpu, etm.cntr_rld_val[i], ETMCNTRLDVRn(i)); + etm_writel(etm, cpu, etm.cntr_event[i], ETMCNTENRn(i)); + etm_writel(etm, cpu, etm.cntr_rld_event[i], ETMCNTRLDEVRn(i)); + etm_writel(etm, cpu, etm.cntr_val[i], ETMCNTVRn(i)); + } + etm_writel(etm, cpu, etm.seq_12_event, ETMSQ12EVR); + etm_writel(etm, cpu, etm.seq_21_event, ETMSQ21EVR); + etm_writel(etm, cpu, etm.seq_23_event, ETMSQ23EVR); + etm_writel(etm, cpu, etm.seq_31_event, ETMSQ31EVR); + etm_writel(etm, cpu, etm.seq_32_event, ETMSQ32EVR); + etm_writel(etm, cpu, etm.seq_13_event, ETMSQ13EVR); + etm_writel(etm, cpu, etm.seq_curr_state, ETMSQR); + for (i = 0; i < etm.nr_ext_out; i++) + etm_writel(etm, cpu, 0x0000406F, ETMEXTOUTEVRn(i)); + for (i = 0; i < etm.nr_ctxid_cmp; i++) + etm_writel(etm, cpu, etm.ctxid_val[i], ETMCIDCVRn(i)); + etm_writel(etm, cpu, etm.ctxid_mask, ETMCIDCMR); + etm_writel(etm, cpu, etm.sync_freq, ETMSYNCFR); + etm_writel(etm, cpu, 0x00000000, ETMEXTINSELR); + etm_writel(etm, cpu, etm.timestamp_event, ETMTSEVR); + etm_writel(etm, cpu, 0x00000000, ETMAUXCR); + etm_writel(etm, cpu, cpu+1, ETMTRACEIDR); + etm_writel(etm, cpu, 0x00000000, ETMVMIDCVR); + + etm_clr_prog(cpu); + ETM_LOCK(cpu); +} + +int etm_enable(int pm_enable) +{ + int ret, cpu; + + if (!sec_debug_level.en.kernel_fault) { + return -ENODEV; + } + + if (etm.enabled) { + dev_err(etm.dev, "ETM tracing already enabled\n"); + ret = -EPERM; + goto err; + } + + wake_lock(&etm.wake_lock); + /* 1. causes all online cpus to come out of idle PC + * 2. prevents idle PC until save restore flag is enabled atomically + * + * we rely on the user to prevent hotplug on/off racing with this + * operation and to ensure cores where trace is expected to be turned + * on are already hotplugged on + */ + if (pm_enable) + pm_qos_update_request(&etm.qos_req, 0); + + etb_disable(); + tpiu_disable(); + /* enable ETB first to avoid loosing any trace data */ + etb_enable(); + funnel_enable(0x0, 0x3); + for_each_online_cpu(cpu) + __etm_enable(cpu); + + etm.enabled = true; + + if (pm_enable) + pm_qos_update_request(&etm.qos_req, PM_QOS_DEFAULT_VALUE); + wake_unlock(&etm.wake_lock); + + return 0; +err: + return ret; +} + +static void __etm_disable(int cpu) +{ + ETM_UNLOCK(cpu); + etm_set_prog(cpu); + + /* program trace enable to low by using always false event */ + etm_writel(etm, cpu, 0x6F | BIT(14), ETMTEEVR); + + /* Vote for ETM power/clock disable */ + etm_set_pwrdwn(cpu); + ETM_LOCK(cpu); +} + +int etm_disable(int pm_enable) +{ + int ret, cpu; + + if (!sec_debug_level.en.kernel_fault) { + return -ENODEV; + } + + if (!etm.enabled) { + dev_err(etm.dev, "ETM tracing already disabled\n"); + ret = -EPERM; + goto err; + } + + wake_lock(&etm.wake_lock); + /* 1. causes all online cpus to come out of idle PC + * 2. prevents idle PC until save restore flag is disabled atomically + * + * we rely on the user to prevent hotplug on/off racing with this + * operation and to ensure cores where trace is expected to be turned + * off are already hotplugged on + */ + if (pm_enable) + pm_qos_update_request(&etm.qos_req, 0); + + for_each_online_cpu(cpu) + __etm_disable(cpu); + + etb_dump(); + etb_disable(); + funnel_disable(0x0, 0x3); + + etm.enabled = false; + + if (pm_enable) + pm_qos_update_request(&etm.qos_req, PM_QOS_DEFAULT_VALUE); + wake_unlock(&etm.wake_lock); + + return 0; +err: + return ret; +} + +#define ETM_STORE(name, mask) \ +static ssize_t name##_store(struct kobject *kobj, \ + struct kobj_attribute *attr, \ + const char *buf, size_t n) \ +{ \ + unsigned long val; \ + \ + if (sscanf(buf, "%lx", &val) != 1) \ + return -EINVAL; \ + \ + etm.name = val & mask; \ + return n; \ +} + +#define ETM_SHOW(name) \ +static ssize_t name##_show(struct kobject *kobj, \ + struct kobj_attribute *attr, \ + char *buf) \ +{ \ + unsigned long val = etm.name; \ + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); \ +} + +#define ETM_ATTR(name) \ +static struct kobj_attribute name##_attr = \ + __ATTR(name, S_IRUGO | S_IWUSR, name##_show, name##_store) +#define ETM_ATTR_RO(name) \ +static struct kobj_attribute name##_attr = \ + __ATTR(name, S_IRUGO, name##_show, NULL) + +static ssize_t enabled_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + int ret = 0; + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + if (val) + ret = etm_enable(1); + else + ret = etm_disable(1); + mutex_unlock(&etm.mutex); + + if (ret) + return ret; + return n; +} +ETM_SHOW(enabled); +ETM_ATTR(enabled); + +ETM_SHOW(nr_addr_cmp); +ETM_ATTR_RO(nr_addr_cmp); +ETM_SHOW(nr_cntr); +ETM_ATTR_RO(nr_cntr); +ETM_SHOW(nr_ctxid_cmp); +ETM_ATTR_RO(nr_ctxid_cmp); + +/* Reset to trace everything i.e. exclude nothing. */ +static ssize_t reset_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + int i; + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + if (val) { + etm.mode = ETM_MODE_EXCLUDE; + etm.ctrl = 0x0; + etm.trigger_event = 0x406F; + etm.startstop_ctrl = 0x0; + etm.enable_event = 0x6F; + etm.enable_ctrl1 = 0x1000000; + etm.fifofull_level = 0x28; + etm.addr_idx = 0x0; + for (i = 0; i < etm.nr_addr_cmp; i++) { + etm.addr_val[i] = 0x0; + etm.addr_acctype[i] = 0x0; + etm.addr_type[i] = ETM_ADDR_TYPE_NONE; + } + etm.cntr_idx = 0x0; + for (i = 0; i < etm.nr_cntr; i++) { + etm.cntr_rld_val[i] = 0x0; + etm.cntr_event[i] = 0x406F; + etm.cntr_rld_event[i] = 0x406F; + etm.cntr_val[i] = 0x0; + } + etm.seq_12_event = 0x406F; + etm.seq_21_event = 0x406F; + etm.seq_23_event = 0x406F; + etm.seq_31_event = 0x406F; + etm.seq_32_event = 0x406F; + etm.seq_13_event = 0x406F; + etm.seq_curr_state = 0x0; + etm.ctxid_idx = 0x0; + for (i = 0; i < etm.nr_ctxid_cmp; i++) + etm.ctxid_val[i] = 0x0; + etm.ctxid_mask = 0x0; + etm.sync_freq = 0x80; + etm.timestamp_event = 0x406F; + } + mutex_unlock(&etm.mutex); + return n; +} +ETM_SHOW(reset); +ETM_ATTR(reset); + +static ssize_t mode_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + etm.mode = val & ETM_MODE_ALL; + + if (etm.mode & ETM_MODE_EXCLUDE) + etm.enable_ctrl1 |= BIT(24); + else + etm.enable_ctrl1 &= ~BIT(24); + + if (etm.mode & ETM_MODE_CYCACC) + etm.ctrl |= BIT(12); + else + etm.ctrl &= ~BIT(12); + + if (etm.mode & ETM_MODE_STALL) + etm.ctrl |= BIT(7); + else + etm.ctrl &= ~BIT(7); + + if (etm.mode & ETM_MODE_TIMESTAMP) + etm.ctrl |= BIT(28); + else + etm.ctrl &= ~BIT(28); + if (etm.mode & ETM_MODE_CTXID) + etm.ctrl |= (BIT(14) | BIT(15)); + else + etm.ctrl &= ~(BIT(14) | BIT(15)); + mutex_unlock(&etm.mutex); + + return n; +} +ETM_SHOW(mode); +ETM_ATTR(mode); + +ETM_STORE(trigger_event, ETM_EVENT_MASK); +ETM_SHOW(trigger_event); +ETM_ATTR(trigger_event); + +ETM_STORE(enable_event, ETM_EVENT_MASK); +ETM_SHOW(enable_event); +ETM_ATTR(enable_event); + +ETM_STORE(fifofull_level, ETM_ALL_MASK); +ETM_SHOW(fifofull_level); +ETM_ATTR(fifofull_level); + +static ssize_t addr_idx_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + if (val >= etm.nr_addr_cmp) + return -EINVAL; + + /* Use mutex to ensure index doesn't change while it gets dereferenced + * multiple times within a mutex block elsewhere. + */ + mutex_lock(&etm.mutex); + etm.addr_idx = val; + mutex_unlock(&etm.mutex); + return n; +} +ETM_SHOW(addr_idx); +ETM_ATTR(addr_idx); + +static ssize_t addr_single_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + uint8_t idx; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (!(etm.addr_type[idx] == ETM_ADDR_TYPE_NONE || + etm.addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + etm.addr_val[idx] = val; + etm.addr_type[idx] = ETM_ADDR_TYPE_SINGLE; + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t addr_single_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + uint8_t idx; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (!(etm.addr_type[idx] == ETM_ADDR_TYPE_NONE || + etm.addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + val = etm.addr_val[idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(addr_single); + +static ssize_t addr_range_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val1, val2; + uint8_t idx; + + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + /* lower address comparator cannot have a higher address value */ + if (val1 > val2) + return -EINVAL; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (idx % 2 != 0) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + if (!((etm.addr_type[idx] == ETM_ADDR_TYPE_NONE && + etm.addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || + (etm.addr_type[idx] == ETM_ADDR_TYPE_RANGE && + etm.addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + etm.addr_val[idx] = val1; + etm.addr_type[idx] = ETM_ADDR_TYPE_RANGE; + etm.addr_val[idx + 1] = val2; + etm.addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE; + etm.enable_ctrl1 |= (1 << (idx/2)); + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t addr_range_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val1, val2; + uint8_t idx; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (idx % 2 != 0) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + if (!((etm.addr_type[idx] == ETM_ADDR_TYPE_NONE && + etm.addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) || + (etm.addr_type[idx] == ETM_ADDR_TYPE_RANGE && + etm.addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + val1 = etm.addr_val[idx]; + val2 = etm.addr_val[idx + 1]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx %#lx\n", val1, val2); +} +ETM_ATTR(addr_range); + +static ssize_t addr_start_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + uint8_t idx; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (!(etm.addr_type[idx] == ETM_ADDR_TYPE_NONE || + etm.addr_type[idx] == ETM_ADDR_TYPE_START)) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + etm.addr_val[idx] = val; + etm.addr_type[idx] = ETM_ADDR_TYPE_START; + etm.startstop_ctrl |= (1 << idx); + etm.enable_ctrl1 |= BIT(25); + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t addr_start_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + uint8_t idx; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (!(etm.addr_type[idx] == ETM_ADDR_TYPE_NONE || + etm.addr_type[idx] == ETM_ADDR_TYPE_START)) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + val = etm.addr_val[idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(addr_start); + +static ssize_t addr_stop_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + uint8_t idx; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (!(etm.addr_type[idx] == ETM_ADDR_TYPE_NONE || + etm.addr_type[idx] == ETM_ADDR_TYPE_STOP)) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + etm.addr_val[idx] = val; + etm.addr_type[idx] = ETM_ADDR_TYPE_STOP; + etm.startstop_ctrl |= (1 << (idx + 16)); + etm.enable_ctrl1 |= BIT(25); + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t addr_stop_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + uint8_t idx; + + mutex_lock(&etm.mutex); + idx = etm.addr_idx; + if (!(etm.addr_type[idx] == ETM_ADDR_TYPE_NONE || + etm.addr_type[idx] == ETM_ADDR_TYPE_STOP)) { + mutex_unlock(&etm.mutex); + return -EPERM; + } + + val = etm.addr_val[idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(addr_stop); + +static ssize_t addr_acctype_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + etm.addr_acctype[etm.addr_idx] = val; + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t addr_acctype_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + + mutex_lock(&etm.mutex); + val = etm.addr_acctype[etm.addr_idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(addr_acctype); + +static ssize_t cntr_idx_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + if (val >= etm.nr_cntr) + return -EINVAL; + + /* Use mutex to ensure index doesn't change while it gets dereferenced + * multiple times within a mutex block elsewhere. + */ + mutex_lock(&etm.mutex); + etm.cntr_idx = val; + mutex_unlock(&etm.mutex); + return n; +} +ETM_SHOW(cntr_idx); +ETM_ATTR(cntr_idx); + +static ssize_t cntr_rld_val_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + etm.cntr_rld_val[etm.cntr_idx] = val; + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t cntr_rld_val_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + mutex_lock(&etm.mutex); + val = etm.cntr_rld_val[etm.cntr_idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(cntr_rld_val); + +static ssize_t cntr_event_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + etm.cntr_event[etm.cntr_idx] = val & ETM_EVENT_MASK; + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t cntr_event_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + + mutex_lock(&etm.mutex); + val = etm.cntr_event[etm.cntr_idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(cntr_event); + +static ssize_t cntr_rld_event_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + etm.cntr_rld_event[etm.cntr_idx] = val & ETM_EVENT_MASK; + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t cntr_rld_event_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + + mutex_lock(&etm.mutex); + val = etm.cntr_rld_event[etm.cntr_idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(cntr_rld_event); + +static ssize_t cntr_val_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + etm.cntr_val[etm.cntr_idx] = val; + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t cntr_val_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + + mutex_lock(&etm.mutex); + val = etm.cntr_val[etm.cntr_idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(cntr_val); + +ETM_STORE(seq_12_event, ETM_EVENT_MASK); +ETM_SHOW(seq_12_event); +ETM_ATTR(seq_12_event); + +ETM_STORE(seq_21_event, ETM_EVENT_MASK); +ETM_SHOW(seq_21_event); +ETM_ATTR(seq_21_event); + +ETM_STORE(seq_23_event, ETM_EVENT_MASK); +ETM_SHOW(seq_23_event); +ETM_ATTR(seq_23_event); + +ETM_STORE(seq_31_event, ETM_EVENT_MASK); +ETM_SHOW(seq_31_event); +ETM_ATTR(seq_31_event); + +ETM_STORE(seq_32_event, ETM_EVENT_MASK); +ETM_SHOW(seq_32_event); +ETM_ATTR(seq_32_event); + +ETM_STORE(seq_13_event, ETM_EVENT_MASK); +ETM_SHOW(seq_13_event); +ETM_ATTR(seq_13_event); + +static ssize_t seq_curr_state_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + if (val > ETM_SEQ_STATE_MAX_VAL) + return -EINVAL; + + etm.seq_curr_state = val; + return n; +} +ETM_SHOW(seq_curr_state); +ETM_ATTR(seq_curr_state); + +static ssize_t ctxid_idx_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + if (val >= etm.nr_ctxid_cmp) + return -EINVAL; + + /* Use mutex to ensure index doesn't change while it gets dereferenced + * multiple times within a mutex block elsewhere. + */ + mutex_lock(&etm.mutex); + etm.ctxid_idx = val; + mutex_unlock(&etm.mutex); + return n; +} +ETM_SHOW(ctxid_idx); +ETM_ATTR(ctxid_idx); + +static ssize_t ctxid_val_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + mutex_lock(&etm.mutex); + etm.ctxid_val[etm.ctxid_idx] = val; + mutex_unlock(&etm.mutex); + return n; +} +static ssize_t ctxid_val_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val; + + mutex_lock(&etm.mutex); + val = etm.ctxid_val[etm.ctxid_idx]; + mutex_unlock(&etm.mutex); + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +ETM_ATTR(ctxid_val); + +ETM_STORE(ctxid_mask, ETM_ALL_MASK); +ETM_SHOW(ctxid_mask); +ETM_ATTR(ctxid_mask); + +ETM_STORE(sync_freq, ETM_SYNC_MASK); +ETM_SHOW(sync_freq); +ETM_ATTR(sync_freq); + +ETM_STORE(timestamp_event, ETM_EVENT_MASK); +ETM_SHOW(timestamp_event); +ETM_ATTR(timestamp_event); + +static struct attribute *etm_attrs[] = { + &nr_addr_cmp_attr.attr, + &nr_cntr_attr.attr, + &nr_ctxid_cmp_attr.attr, + &reset_attr.attr, + &mode_attr.attr, + &trigger_event_attr.attr, + &enable_event_attr.attr, + &fifofull_level_attr.attr, + &addr_idx_attr.attr, + &addr_single_attr.attr, + &addr_range_attr.attr, + &addr_start_attr.attr, + &addr_stop_attr.attr, + &addr_acctype_attr.attr, + &cntr_idx_attr.attr, + &cntr_rld_val_attr.attr, + &cntr_event_attr.attr, + &cntr_rld_event_attr.attr, + &cntr_val_attr.attr, + &seq_12_event_attr.attr, + &seq_21_event_attr.attr, + &seq_23_event_attr.attr, + &seq_31_event_attr.attr, + &seq_32_event_attr.attr, + &seq_13_event_attr.attr, + &seq_curr_state_attr.attr, + &ctxid_idx_attr.attr, + &ctxid_val_attr.attr, + &ctxid_mask_attr.attr, + &sync_freq_attr.attr, + ×tamp_event_attr.attr, + NULL, +}; + +static struct attribute_group etm_attr_grp = { + .attrs = etm_attrs, +}; + +static int __init etm_sysfs_init(void) +{ + int ret; + + etm.kobj = kobject_create_and_add("etm", coresight_get_modulekobj()); + if (!etm.kobj) { + dev_err(etm.dev, "failed to create ETM sysfs kobject\n"); + ret = -ENOMEM; + goto err_create; + } + + ret = sysfs_create_file(etm.kobj, &enabled_attr.attr); + if (ret) { + dev_err(etm.dev, "failed to create ETM sysfs enabled" + " attribute\n"); + goto err_file; + } + + if (sysfs_create_group(etm.kobj, &etm_attr_grp)) + dev_err(etm.dev, "failed to create ETM sysfs group\n"); + + return 0; +err_file: + kobject_put(etm.kobj); +err_create: + return ret; +} + +static void etm_sysfs_exit(void) +{ + sysfs_remove_group(etm.kobj, &etm_attr_grp); + sysfs_remove_file(etm.kobj, &enabled_attr.attr); + kobject_put(etm.kobj); +} + +static int __init etm_arch_init(void) +{ + /* use cpu 0 for setup */ + int cpu = 0; + uint32_t etmidr; + uint32_t etmccr; + + ETM_UNLOCK(cpu); + /* Vote for ETM power/clock enable */ + etm_clr_pwrdwn(cpu); + /* Set prog bit. It will be set from reset but this is included to + * ensure it is set + */ + etm_set_prog(cpu); + + /* find all capabilities */ + etmidr = etm_readl(etm, cpu, ETMIDR); + etm.arch = BMVAL(etmidr, 4, 11); + + etmccr = etm_readl(etm, cpu, ETMCCR); + etm.nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2; + etm.nr_cntr = BMVAL(etmccr, 13, 15); + etm.nr_ext_inp = BMVAL(etmccr, 17, 19); + etm.nr_ext_out = BMVAL(etmccr, 20, 22); + etm.nr_ctxid_cmp = BMVAL(etmccr, 24, 25); + + /* Vote for ETM power/clock disable */ + etm_set_pwrdwn(cpu); + ETM_LOCK(cpu); + + return 0; +} + +static int __devinit etm_probe(struct platform_device *pdev) +{ + int ret; + struct resource *res; + + if (!sec_debug_level.en.kernel_fault) { + pr_info("%s: debug level is low\n",__func__); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -EINVAL; + goto err_res; + } + + etm.base = ioremap_nocache(res->start, resource_size(res)); + if (!etm.base) { + ret = -EINVAL; + goto err_ioremap; + } + + etm.dev = &pdev->dev; + + mutex_init(&etm.mutex); + wake_lock_init(&etm.wake_lock, WAKE_LOCK_SUSPEND, "coresight_etm"); + pm_qos_add_request(&etm.qos_req, PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); + + ret = etm_arch_init(); + if (ret) + goto err_arch; + + ret = etm_sysfs_init(); + if (ret) + goto err_sysfs; + + etm.enabled = false; + + dev_info(etm.dev, "ETM initialized\n"); + + if (etm_boot_enable) + etm_enable(1); + + return 0; + +err_sysfs: +err_arch: + pm_qos_remove_request(&etm.qos_req); + wake_lock_destroy(&etm.wake_lock); + mutex_destroy(&etm.mutex); + iounmap(etm.base); +err_ioremap: +err_res: + dev_err(etm.dev, "ETM init failed\n"); + return ret; +} + +static int etm_remove(struct platform_device *pdev) +{ + if (etm.enabled) + etm_disable(1); + etm_sysfs_exit(); + pm_qos_remove_request(&etm.qos_req); + wake_lock_destroy(&etm.wake_lock); + mutex_destroy(&etm.mutex); + iounmap(etm.base); + + return 0; +} + +static int etm_suspend(struct device *dev) +{ + etm_disable(1); + return 0; +} + +static int etm_resume(struct device *dev) +{ + etm_enable(1); + return 0; +} + +static const struct dev_pm_ops etm_pm = { + .suspend = etm_suspend, + .resume = etm_resume, +}; + +static struct platform_driver etm_driver = { + .probe = etm_probe, + .remove = etm_remove, + .driver = { + .name = "coresight_etm", + .owner = THIS_MODULE, + .pm = &etm_pm, + }, +}; + +int __init etm_init(void) +{ + return platform_driver_register(&etm_driver); +} + +void etm_exit(void) +{ + platform_driver_unregister(&etm_driver); +} diff --git a/arch/arm/mach-exynos/coresight-funnel.c b/arch/arm/mach-exynos/coresight-funnel.c new file mode 100644 index 0000000..e7e399d --- /dev/null +++ b/arch/arm/mach-exynos/coresight-funnel.c @@ -0,0 +1,224 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/err.h> + +#include "coresight.h" +#include <mach/sec_debug.h> + +#define funnel_writel(funnel, id, val, off) \ + __raw_writel((val), funnel.base + (SZ_4K * id) + off) +#define funnel_readl(funnel, id, off) \ + __raw_readl(funnel.base + (SZ_4K * id) + off) + +#define FUNNEL_FUNCTL (0x000) +#define FUNNEL_PRICTL (0x004) +#define FUNNEL_ITATBDATA0 (0xEEC) +#define FUNNEL_ITATBCTR2 (0xEF0) +#define FUNNEL_ITATBCTR1 (0xEF4) +#define FUNNEL_ITATBCTR0 (0xEF8) + + +#define FUNNEL_LOCK(id) \ +do { \ + mb(); \ + funnel_writel(funnel, id, 0x0, CS_LAR); \ +} while (0) +#define FUNNEL_UNLOCK(id) \ +do { \ + funnel_writel(funnel, id, CS_UNLOCK_MAGIC, CS_LAR); \ + mb(); \ +} while (0) + +#define FUNNEL_HOLDTIME_MASK (0xF00) +#define FUNNEL_HOLDTIME_SHFT (0x8) +#define FUNNEL_HOLDTIME (0x7 << FUNNEL_HOLDTIME_SHFT) + +struct funnel_ctx { + void __iomem *base; + bool enabled; + struct device *dev; + struct kobject *kobj; + uint32_t priority; +}; + +static struct funnel_ctx funnel = { + .priority = 0xFAC680, +}; + +static void __funnel_enable(uint8_t id, uint32_t port_mask) +{ + uint32_t functl; + + FUNNEL_UNLOCK(id); + + functl = funnel_readl(funnel, id, FUNNEL_FUNCTL); + functl &= ~FUNNEL_HOLDTIME_MASK; + functl |= FUNNEL_HOLDTIME; + functl |= port_mask; + funnel_writel(funnel, id, functl, FUNNEL_FUNCTL); + funnel_writel(funnel, id, funnel.priority, FUNNEL_PRICTL); + + FUNNEL_LOCK(id); +} + +void funnel_enable(uint8_t id, uint32_t port_mask) +{ + __funnel_enable(id, port_mask); + funnel.enabled = true; +} + +static void __funnel_disable(uint8_t id, uint32_t port_mask) +{ + uint32_t functl; + + FUNNEL_UNLOCK(id); + + functl = funnel_readl(funnel, id, FUNNEL_FUNCTL); + functl &= ~port_mask; + funnel_writel(funnel, id, functl, FUNNEL_FUNCTL); + + FUNNEL_LOCK(id); +} + +void funnel_disable(uint8_t id, uint32_t port_mask) +{ + __funnel_disable(id, port_mask); + funnel.enabled = false; +} + +#define FUNNEL_ATTR(name) \ +static struct kobj_attribute name##_attr = \ + __ATTR(name, S_IRUGO | S_IWUSR, name##_show, name##_store) + +static ssize_t priority_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + funnel.priority = val; + return n; +} +static ssize_t priority_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val = funnel.priority; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +FUNNEL_ATTR(priority); + +static int __init funnel_sysfs_init(void) +{ + int ret; + + funnel.kobj = kobject_create_and_add("funnel", \ + coresight_get_modulekobj()); + if (!funnel.kobj) { + dev_err(funnel.dev, "failed to create FUNNEL sysfs kobject\n"); + ret = -ENOMEM; + goto err_create; + } + + ret = sysfs_create_file(funnel.kobj, &priority_attr.attr); + if (ret) { + dev_err(funnel.dev, "failed to create FUNNEL sysfs priority" + " attribute\n"); + goto err_file; + } + + return 0; +err_file: + kobject_put(funnel.kobj); +err_create: + return ret; +} + +static void funnel_sysfs_exit(void) +{ + sysfs_remove_file(funnel.kobj, &priority_attr.attr); + kobject_put(funnel.kobj); +} + +static int __devinit funnel_probe(struct platform_device *pdev) +{ + int ret; + struct resource *res; + + if (!sec_debug_level.en.kernel_fault) { + pr_info("%s: debug level is low\n",__func__); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -EINVAL; + goto err_res; + } + + funnel.base = ioremap_nocache(res->start, resource_size(res)); + if (!funnel.base) { + ret = -EINVAL; + goto err_ioremap; + } + + funnel.dev = &pdev->dev; + + funnel_sysfs_init(); + + dev_info(funnel.dev, "FUNNEL initialized\n"); + return 0; + +err_ioremap: +err_res: + dev_err(funnel.dev, "FUNNEL init failed\n"); + return ret; +} + +static int funnel_remove(struct platform_device *pdev) +{ + if (funnel.enabled) + funnel_disable(0x0, 0xFF); + funnel_sysfs_exit(); + iounmap(funnel.base); + + return 0; +} + +static struct platform_driver funnel_driver = { + .probe = funnel_probe, + .remove = funnel_remove, + .driver = { + .name = "coresight_funnel", + }, +}; + +int __init funnel_init(void) +{ + return platform_driver_register(&funnel_driver); +} + +void funnel_exit(void) +{ + platform_driver_unregister(&funnel_driver); +} diff --git a/arch/arm/mach-exynos/coresight-tpiu.c b/arch/arm/mach-exynos/coresight-tpiu.c new file mode 100644 index 0000000..7d8b48a --- /dev/null +++ b/arch/arm/mach-exynos/coresight-tpiu.c @@ -0,0 +1,141 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/err.h> + +#include "coresight.h" +#include <mach/sec_debug.h> + +#define tpiu_writel(tpiu, val, off) __raw_writel((val), tpiu.base + off) +#define tpiu_readl(tpiu, off) __raw_readl(tpiu.base + off) + +#define TPIU_SUPP_PORTSZ (0x000) +#define TPIU_CURR_PORTSZ (0x004) +#define TPIU_SUPP_TRIGMODES (0x100) +#define TPIU_TRIG_CNTRVAL (0x104) +#define TPIU_TRIG_MULT (0x108) +#define TPIU_SUPP_TESTPATM (0x200) +#define TPIU_CURR_TESTPATM (0x204) +#define TPIU_TEST_PATREPCNTR (0x208) +#define TPIU_FFSR (0x300) +#define TPIU_FFCR (0x304) +#define TPIU_FSYNC_CNTR (0x308) +#define TPIU_EXTCTL_INPORT (0x400) +#define TPIU_EXTCTL_OUTPORT (0x404) +#define TPIU_ITTRFLINACK (0xEE4) +#define TPIU_ITTRFLIN (0xEE8) +#define TPIU_ITATBDATA0 (0xEEC) +#define TPIU_ITATBCTR2 (0xEF0) +#define TPIU_ITATBCTR1 (0xEF4) +#define TPIU_ITATBCTR0 (0xEF8) + + +#define TPIU_LOCK() \ +do { \ + mb(); \ + tpiu_writel(tpiu, 0x0, CS_LAR); \ +} while (0) +#define TPIU_UNLOCK() \ +do { \ + tpiu_writel(tpiu, CS_UNLOCK_MAGIC, CS_LAR); \ + mb(); \ +} while (0) + +struct tpiu_ctx { + void __iomem *base; + bool enabled; + struct device *dev; +}; + +static struct tpiu_ctx tpiu; + +static void __tpiu_disable(void) +{ + TPIU_UNLOCK(); + + tpiu_writel(tpiu, 0x3000, TPIU_FFCR); + tpiu_writel(tpiu, 0x3040, TPIU_FFCR); + + TPIU_LOCK(); +} + +void tpiu_disable(void) +{ + __tpiu_disable(); + tpiu.enabled = false; +} + +static int __devinit tpiu_probe(struct platform_device *pdev) +{ + int ret; + struct resource *res; + + if (!sec_debug_level.en.kernel_fault) { + pr_info("%s: debug level is low\n",__func__); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -EINVAL; + goto err_res; + } + + tpiu.base = ioremap_nocache(res->start, resource_size(res)); + if (!tpiu.base) { + ret = -EINVAL; + goto err_ioremap; + } + + tpiu.dev = &pdev->dev; + + dev_info(tpiu.dev, "TPIU initialized\n"); + return 0; + +err_ioremap: +err_res: + dev_err(tpiu.dev, "TPIU init failed\n"); + return ret; +} + +static int tpiu_remove(struct platform_device *pdev) +{ + if (tpiu.enabled) + tpiu_disable(); + iounmap(tpiu.base); + + return 0; +} + +static struct platform_driver tpiu_driver = { + .probe = tpiu_probe, + .remove = tpiu_remove, + .driver = { + .name = "coresight_tpiu", + }, +}; + +int __init tpiu_init(void) +{ + return platform_driver_register(&tpiu_driver); +} + +void tpiu_exit(void) +{ + platform_driver_unregister(&tpiu_driver); +} diff --git a/arch/arm/mach-exynos/coresight.c b/arch/arm/mach-exynos/coresight.c new file mode 100644 index 0000000..26e25b0 --- /dev/null +++ b/arch/arm/mach-exynos/coresight.c @@ -0,0 +1,142 @@ +/* Copyright (c) 2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/err.h> + +#include "coresight.h" + +enum { + CORESIGHT_CLK_OFF, + CORESIGHT_CLK_ON_DBG, + CORESIGHT_CLK_ON_HSDBG, +}; + +struct coresight_ctx { + struct kobject *modulekobj; + uint8_t max_clk; +}; + +static struct coresight_ctx coresight; + + +struct kobject *coresight_get_modulekobj(void) +{ + return coresight.modulekobj; +} + +#define CORESIGHT_ATTR(name) \ +static struct kobj_attribute name##_attr = \ + __ATTR(name, S_IRUGO | S_IWUSR, name##_show, name##_store) + +static ssize_t max_clk_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + unsigned long val; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + coresight.max_clk = val; + return n; +} +static ssize_t max_clk_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + unsigned long val = coresight.max_clk; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +CORESIGHT_ATTR(max_clk); + +static int __init coresight_sysfs_init(void) +{ + int ret; + + coresight.modulekobj = kset_find_obj(module_kset, KBUILD_MODNAME); + if (!coresight.modulekobj) { + pr_err("failed to find CORESIGHT sysfs module kobject\n"); + ret = -ENOENT; + goto err; + } + + ret = sysfs_create_file(coresight.modulekobj, &max_clk_attr.attr); + if (ret) { + pr_err("failed to create CORESIGHT sysfs max_clk attribute\n"); + goto err; + } + + return 0; +err: + return ret; +} + +static void coresight_sysfs_exit(void) +{ + sysfs_remove_file(coresight.modulekobj, &max_clk_attr.attr); +} + +static int __init coresight_init(void) +{ + int ret; + + ret = coresight_sysfs_init(); + if (ret) + goto err_sysfs; + ret = etb_init(); + if (ret) + goto err_etb; + ret = tpiu_init(); + if (ret) + goto err_tpiu; + ret = funnel_init(); + if (ret) + goto err_funnel; + ret = etm_init(); + if (ret) + goto err_etm; + + pr_info("CORESIGHT initialized\n"); + return 0; +err_etm: + funnel_exit(); +err_funnel: + tpiu_exit(); +err_tpiu: + etb_exit(); +err_etb: + coresight_sysfs_exit(); +err_sysfs: + pr_err("CORESIGHT init failed\n"); + return ret; +} +module_init(coresight_init); + +static void __exit coresight_exit(void) +{ + coresight_sysfs_exit(); + etm_exit(); + funnel_exit(); + tpiu_exit(); + etb_exit(); +} +module_exit(coresight_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("CoreSight ETM Debug System Driver"); diff --git a/arch/arm/mach-exynos/coresight.h b/arch/arm/mach-exynos/coresight.h new file mode 100644 index 0000000..71c10ee --- /dev/null +++ b/arch/arm/mach-exynos/coresight.h @@ -0,0 +1,80 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ARCH_ARM_MACH_EXYNOS_CORESIGHT_H_ +#define _ARCH_ARM_MACH_EXYNOS_CORESIGHT_H_ + +#include <linux/bitops.h> + +/* Coresight management registers (0xF00-0xFCC) + * 0xFA0 - 0xFA4: Management registers in PFTv1.0 + * Trace registers in PFTv1.1 + */ +#define CS_ITCTRL (0xF00) +#define CS_CLAIMSET (0xFA0) +#define CS_CLAIMCLR (0xFA4) +#define CS_LAR (0xFB0) +#define CS_LSR (0xFB4) +#define CS_AUTHSTATUS (0xFB8) +#define CS_DEVID (0xFC8) +#define CS_DEVTYPE (0xFCC) +/* Peripheral id registers (0xFD0-0xFEC) */ +#define CS_PIDR4 (0xFD0) +#define CS_PIDR5 (0xFD4) +#define CS_PIDR6 (0xFD8) +#define CS_PIDR7 (0xFDC) +#define CS_PIDR0 (0xFE0) +#define CS_PIDR1 (0xFE4) +#define CS_PIDR2 (0xFE8) +#define CS_PIDR3 (0xFEC) +/* Component id registers (0xFF0-0xFFC) */ +#define CS_CIDR0 (0xFF0) +#define CS_CIDR1 (0xFF4) +#define CS_CIDR2 (0xFF8) +#define CS_CIDR3 (0xFFC) + +/* DBGv7 with baseline CP14 registers implemented */ +#define ARM_DEBUG_ARCH_V7B (0x3) +/* DBGv7 with all CP14 registers implemented */ +#define ARM_DEBUG_ARCH_V7 (0x4) +#define ARM_DEBUG_ARCH_V7_1 (0x5) +#define ETM_ARCH_V3_3 (0x23) +#define PFT_ARCH_V1_1 (0x31) + +#define TIMEOUT_US (100) +#define OSLOCK_MAGIC (0xC5ACCE55) +#define CS_UNLOCK_MAGIC (0xC5ACCE55) + +#define BM(lsb, msb) ((BIT(msb) - BIT(lsb)) + BIT(msb)) +#define BMVAL(val, lsb, msb) ((val & BM(lsb, msb)) >> lsb) +#define BVAL(val, n) ((val & BIT(n)) >> n) + +int etb_init(void); +void etb_exit(void); +int tpiu_init(void); +void tpiu_exit(void); +int funnel_init(void); +void funnel_exit(void); +int etm_init(void); +void etm_exit(void); + +void __etb_disable(void); +void etb_enable(void); +void etb_disable(void); +void etb_dump(void); +void tpiu_disable(void); +void funnel_enable(uint8_t id, uint32_t port_mask); +void funnel_disable(uint8_t id, uint32_t port_mask); + +struct kobject *coresight_get_modulekobj(void); + +#endif diff --git a/arch/arm/mach-exynos/cpu-exynos4.c b/arch/arm/mach-exynos/cpu-exynos4.c index ffd9387..7f2245e 100644 --- a/arch/arm/mach-exynos/cpu-exynos4.c +++ b/arch/arm/mach-exynos/cpu-exynos4.c @@ -287,7 +287,7 @@ void __init exynos4_map_io(void) s3c_i2c2_setname("s3c2440-i2c"); #ifdef CONFIG_S5P_DEV_ACE - s5p_ace_setname("exynos4-ace"); + s5p_ace_setname("exynos-ace"); #endif } diff --git a/arch/arm/mach-exynos/cpu-exynos5.c b/arch/arm/mach-exynos/cpu-exynos5.c deleted file mode 100644 index 87f2bbd..0000000 --- a/arch/arm/mach-exynos/cpu-exynos5.c +++ /dev/null @@ -1,381 +0,0 @@ -/* linux/arch/arm/mach-exynos/cpu-exynos5.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/sched.h> -#include <linux/sysdev.h> -#include <linux/delay.h> - -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <asm/proc-fns.h> - -#include <plat/cpu.h> -#include <plat/clock.h> -#include <plat/devs.h> -#include <plat/fb-core.h> -#include <plat/exynos5.h> -#include <plat/sdhci.h> -#include <plat/pm.h> -#include <plat/iic-core.h> -#include <plat/tv-core.h> -#include <plat/ace-core.h> -#include <plat/reset.h> -#include <plat/rtc-core.h> -#include <plat/adc-core.h> - -#include <mach/regs-irq.h> -#include <mach/regs-pmu.h> -#include <mach/regs-pmu5.h> -#include <mach/smc.h> - -unsigned int gic_bank_offset __read_mostly; - -extern int combiner_init(unsigned int combiner_nr, void __iomem *base, - unsigned int irq_start); -extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); - -/* Initial IO mappings */ -static struct map_desc exynos5_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSTIMER, - .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_CMU, - .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), - .length = 144 * SZ_1K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_PMU, - .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), - .length = SZ_64K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_COMBINER_BASE, - .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_UART, - .pfn = __phys_to_pfn(S3C_PA_UART), - .length = SZ_512K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GPIO1, - .pfn = __phys_to_pfn(EXYNOS5_PA_GPIO1), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GPIO2, - .pfn = __phys_to_pfn(EXYNOS5_PA_GPIO2), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GPIO3, - .pfn = __phys_to_pfn(EXYNOS5_PA_GPIO3), - .length = SZ_256, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GPIO4, - .pfn = __phys_to_pfn(EXYNOS5_PA_GPIO4), - .length = SZ_256, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_AUDSS, - .pfn = __phys_to_pfn(EXYNOS5_PA_AUDSS), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S3C_VA_USB_HSPHY, - .pfn = __phys_to_pfn(EXYNOS5_PA_HSPHY), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SS_PHY, - .pfn = __phys_to_pfn(EXYNOS5_PA_SS_PHY), - .length = SZ_4K, - .type = MT_DEVICE, -#ifdef CONFIG_ARM_TRUSTZONE - }, { - .virtual = (unsigned long)S5P_VA_SYSRAM_NS, - .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM_NS), - .length = SZ_4K, - .type = MT_DEVICE, -#endif - }, { - .virtual = (unsigned long)S5P_VA_PPMU_CPU, - .pfn = __phys_to_pfn(EXYNOS5_PA_PPMU_CPU), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_PPMU_DDR_C, - .pfn = __phys_to_pfn(EXYNOS5_PA_PPMU_DDR_C), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_PPMU_DDR_R1, - .pfn = __phys_to_pfn(EXYNOS5_PA_PPMU_DDR_R1), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_PPMU_DDR_L, - .pfn = __phys_to_pfn(EXYNOS5_PA_PPMU_DDR_L), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_PPMU_RIGHT0_BUS, - .pfn = __phys_to_pfn(EXYNOS5_PA_PPMU_RIGHT0_BUS), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_FIMCLITE0, - .pfn = __phys_to_pfn(EXYNOS5_PA_FIMC_LITE0), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_FIMCLITE1, - .pfn = __phys_to_pfn(EXYNOS5_PA_FIMC_LITE1), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_FIMCLITE2, - .pfn = __phys_to_pfn(EXYNOS5_PA_FIMC_LITE2), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_MIPICSI0, - .pfn = __phys_to_pfn(EXYNOS5_PA_MIPI_CSIS0), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_MIPICSI1, - .pfn = __phys_to_pfn(EXYNOS5_PA_MIPI_CSIS1), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_DMC0, - .pfn = __phys_to_pfn(EXYNOS5_PA_DMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos5250_rev_0_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_GIC_CPU, - .pfn = __phys_to_pfn(EXYNOS5250_REV0_PA_GIC_CPU), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GIC_DIST, - .pfn = __phys_to_pfn(EXYNOS5250_REV0_PA_GIC_DIST), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos5250_rev_1_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_GIC_CPU, - .pfn = __phys_to_pfn(EXYNOS5250_REV1_PA_GIC_CPU), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_GIC_DIST, - .pfn = __phys_to_pfn(EXYNOS5250_REV1_PA_GIC_DIST), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static void exynos5_idle(void) -{ - if (!need_resched()) - cpu_do_idle(); - - local_irq_enable(); -} - -/* - * exynos5_map_io - * - * register the standard cpu IO areas - */ -void __init exynos5_map_io(void) -{ - iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); - - if (soc_is_exynos5250()) { - if (samsung_rev() >= EXYNOS5250_REV_1_0) - iotable_init(exynos5250_rev_1_iodesc, - ARRAY_SIZE(exynos5250_rev_1_iodesc)); - else - iotable_init(exynos5250_rev_0_iodesc, - ARRAY_SIZE(exynos5250_rev_0_iodesc)); - } - -#ifdef CONFIG_S3C_DEV_HSMMC - exynos5_default_sdhci0(); -#endif -#ifdef CONFIG_S3C_DEV_HSMMC1 - exynos5_default_sdhci1(); -#endif -#ifdef CONFIG_S3C_DEV_HSMMC2 - exynos5_default_sdhci2(); -#endif -#ifdef CONFIG_S3C_DEV_HSMMC3 - exynos5_default_sdhci3(); -#endif -#ifdef CONFIG_S3C_DEV_RTC - s3c_rtc_setname("exynos-rtc"); -#endif - - s5p_fb_setname(1, "exynos5-fb"); /* FIMD1 */ - - s3c_adc_setname("samsung-adc-v4"); - - s5p_hdmi_setname("exynos5-hdmi"); - - /* The I2C bus controllers are directly compatible with s3c2440 */ - s3c_i2c0_setname("s3c2440-i2c"); - s3c_i2c1_setname("s3c2440-i2c"); - s3c_i2c2_setname("s3c2440-i2c"); - -#ifdef CONFIG_S5P_DEV_ACE - s5p_ace_setname("exynos4-ace"); -#endif -} - -void __init exynos5_init_clocks(int xtal) -{ - printk(KERN_DEBUG "%s: initializing clocks\n", __func__); - - s3c24xx_register_baseclocks(xtal); - - s5p_register_clocks(xtal); - exynos5_register_clocks(); - exynos5_setup_clocks(); -} - -void __init exynos5_init_irq(void) -{ - int irq; - - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); - gic_arch_extn.irq_set_wake = s3c_irq_wake; - - for (irq = 0; irq < MAX_COMBINER_NR; irq++) { - combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), - COMBINER_IRQ(irq, 0)); - combiner_cascade_irq(irq, IRQ_SPI(irq)); - } - - /* The parameters of s5p_init_irq() are for VIC init. - * Theses parameters should be NULL and 0 because EXYNOS5 - * uses GIC instead of VIC. - */ - s5p_init_irq(NULL, 0); -} - -struct sysdev_class exynos5_sysclass = { - .name = "exynos5-core", -}; - -static struct sys_device exynos5_sysdev = { - .cls = &exynos5_sysclass, -}; - -static int __init exynos5_core_init(void) -{ - return sysdev_class_register(&exynos5_sysclass); -} - -core_initcall(exynos5_core_init); - -#define TAG_RAM_SETUP_SHIFT (9) -#define DATA_RAM_SETUP_SHIFT (5) -#define TAG_RAM_LATENCY_SHIFT (6) -#define DATA_RAM_LATENCY_SHIFT (0) - -static int __init exynos5_l2_cache_init(void) -{ - unsigned int val; - - if (soc_is_exynos5250()) { - asm volatile( - "mrc p15, 0, %0, c1, c0, 0\n" - "bic %0, %0, #(1 << 2)\n" /* cache disable */ - "mcr p15, 0, %0, c1, c0, 0\n" - "mrc p15, 1, %0, c9, c0, 2\n" - : "=r"(val)); - - val |= (1 << TAG_RAM_SETUP_SHIFT) | - (1 << DATA_RAM_SETUP_SHIFT) | - (2 << TAG_RAM_LATENCY_SHIFT) | - (2 << DATA_RAM_LATENCY_SHIFT); - -#ifdef CONFIG_ARM_TRUSTZONE - exynos_smc(SMC_CMD_REG, SMC_REG_ID_CP15(9, 1, 0, 2), val, 0); -#else - asm volatile("mcr p15, 1, %0, c9, c0, 2\n": : "r"(val)); -#endif - asm volatile( - "mrc p15, 0, %0, c1, c0, 0\n" - "orr %0, %0, #(1 << 2)\n" /* cache enable */ - "mcr p15, 0, %0, c1, c0, 0\n" - : : "r"(val)); - } - - return 0; -} - -early_initcall(exynos5_l2_cache_init); - -static void exynos5_sw_reset(void) -{ - int count = 3; - - while (count--) { - __raw_writel(0x1, S5P_SWRESET); - mdelay(500); - } -} - -int __init exynos5_init(void) -{ - unsigned int value; - printk(KERN_INFO "EXYNOS5: Initializing architecture\n"); - - /* set idle function */ - pm_idle = exynos5_idle; - - /* set sw_reset function */ - s5p_reset_hook = exynos5_sw_reset; - - value = __raw_readl(EXYNOS5_AUTOMATIC_WDT_RESET_DISABLE); - value &= ~EXYNOS5_SYS_WDTRESET; - __raw_writel(value, EXYNOS5_AUTOMATIC_WDT_RESET_DISABLE); - value = __raw_readl(EXYNOS5_MASK_WDT_RESET_REQUEST); - value &= ~EXYNOS5_SYS_WDTRESET; - __raw_writel(value, EXYNOS5_MASK_WDT_RESET_REQUEST); - - if (soc_is_exynos5250() && samsung_rev() >= EXYNOS5250_REV_1_0) { - __raw_writel(0x1, EXYNOS5_ADC_PHY_CONTROL); - } - - return sysdev_register(&exynos5_sysdev); -} diff --git a/arch/arm/mach-exynos/cpufreq-4x12.c b/arch/arm/mach-exynos/cpufreq-4x12.c index d5dd249..5213da1 100644 --- a/arch/arm/mach-exynos/cpufreq-4x12.c +++ b/arch/arm/mach-exynos/cpufreq-4x12.c @@ -25,7 +25,7 @@ #include <plat/clock.h> #include <plat/cpu.h> -#define CPUFREQ_LEVEL_END (L13 + 1) +#define CPUFREQ_LEVEL_END (L14 + 1) #undef PRINT_DIV_VAL @@ -37,6 +37,7 @@ static struct clk *cpu_clk; static struct clk *moutcore; static struct clk *mout_mpll; static struct clk *mout_apll; +static bool need_dynamic_ema = false; struct cpufreq_clkdiv { unsigned int index; @@ -47,20 +48,21 @@ struct cpufreq_clkdiv { static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END]; static struct cpufreq_frequency_table exynos4x12_freq_table[] = { - {L0, 1500*1000}, - {L1, 1400*1000}, - {L2, 1300*1000}, - {L3, 1200*1000}, - {L4, 1100*1000}, - {L5, 1000*1000}, - {L6, 900*1000}, - {L7, 800*1000}, - {L8, 700*1000}, - {L9, 600*1000}, - {L10, 500*1000}, - {L11, 400*1000}, - {L12, 300*1000}, - {L13, 200*1000}, + {L0, 1600*1000}, + {L1, 1500*1000}, + {L2, 1400*1000}, + {L3, 1300*1000}, + {L4, 1200*1000}, + {L5, 1100*1000}, + {L6, 1000*1000}, + {L7, 900*1000}, + {L8, 800*1000}, + {L9, 700*1000}, + {L10, 600*1000}, + {L11, 500*1000}, + {L12, 400*1000}, + {L13, 300*1000}, + {L14, 200*1000}, {0, CPUFREQ_TABLE_END}, }; @@ -72,46 +74,49 @@ static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = { * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } */ - /* ARM L0: 1500Mhz */ + /* ARM L0: 1600Mhz */ { 0, 3, 7, 0, 6, 1, 2, 0 }, - /* ARM L1: 1400Mhz */ + /* ARM L1: 1500Mhz */ { 0, 3, 7, 0, 6, 1, 2, 0 }, - /* ARM L2: 1300Mhz */ + /* ARM L2: 1400Mhz */ + { 0, 3, 7, 0, 6, 1, 2, 0 }, + + /* ARM L3: 1300Mhz */ { 0, 3, 7, 0, 5, 1, 2, 0 }, - /* ARM L3: 1200Mhz */ + /* ARM L4: 1200Mhz */ { 0, 3, 7, 0, 5, 1, 2, 0 }, - /* ARM L4: 1100MHz */ + /* ARM L5: 1100MHz */ { 0, 3, 6, 0, 4, 1, 2, 0 }, - /* ARM L5: 1000MHz */ + /* ARM L6: 1000MHz */ { 0, 2, 5, 0, 4, 1, 1, 0 }, - /* ARM L6: 900MHz */ + /* ARM L7: 900MHz */ { 0, 2, 5, 0, 3, 1, 1, 0 }, - /* ARM L7: 800MHz */ + /* ARM L8: 800MHz */ { 0, 2, 5, 0, 3, 1, 1, 0 }, - /* ARM L8: 700MHz */ + /* ARM L9: 700MHz */ { 0, 2, 4, 0, 3, 1, 1, 0 }, - /* ARM L9: 600MHz */ + /* ARM L10: 600MHz */ { 0, 2, 4, 0, 3, 1, 1, 0 }, - /* ARM L10: 500MHz */ + /* ARM L11: 500MHz */ { 0, 2, 4, 0, 3, 1, 1, 0 }, - /* ARM L11: 400MHz */ + /* ARM L12: 400MHz */ { 0, 2, 4, 0, 3, 1, 1, 0 }, - /* ARM L12: 300MHz */ + /* ARM L13: 300MHz */ { 0, 2, 4, 0, 2, 1, 1, 0 }, - /* ARM L13: 200MHz */ + /* ARM L14: 200MHz */ { 0, 1, 3, 0, 1, 1, 1, 0 }, }; @@ -121,46 +126,49 @@ static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = { * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } */ - /* ARM L0: 1500Mhz */ - { 0, 3, 7, 0, 6, 1, 2, 0 }, + /* ARM L0: 1600Mhz */ + { 0, 3, 7, 0, 6, 1, 7, 0 }, - /* ARM L1: 1400Mhz */ - { 0, 3, 7, 0, 6, 1, 2, 0 }, + /* ARM L1: 1500Mhz */ + { 0, 3, 7, 0, 6, 1, 7, 0 }, - /* ARM L2: 1300Mhz */ - { 0, 3, 7, 0, 5, 1, 2, 0 }, + /* ARM L2: 1400Mhz */ + { 0, 3, 7, 0, 6, 1, 6, 0 }, - /* ARM L3: 1200Mhz */ - { 0, 3, 7, 0, 5, 1, 2, 0 }, + /* ARM L3: 1300Mhz */ + { 0, 3, 7, 0, 5, 1, 6, 0 }, - /* ARM L4: 1100MHz */ - { 0, 3, 6, 0, 4, 1, 2, 0 }, + /* ARM L4: 1200Mhz */ + { 0, 3, 7, 0, 5, 1, 5, 0 }, - /* ARM L5: 1000MHz */ - { 0, 2, 5, 0, 4, 1, 1, 0 }, + /* ARM L5: 1100MHz */ + { 0, 3, 6, 0, 4, 1, 5, 0 }, - /* ARM L6: 900MHz */ - { 0, 2, 5, 0, 3, 1, 1, 0 }, + /* ARM L6: 1000MHz */ + { 0, 2, 5, 0, 4, 1, 4, 0 }, - /* ARM L7: 800MHz */ - { 0, 2, 5, 0, 3, 1, 1, 0 }, + /* ARM L7: 900MHz */ + { 0, 2, 5, 0, 3, 1, 4, 0 }, - /* ARM L8: 700MHz */ - { 0, 2, 4, 0, 3, 1, 1, 0 }, + /* ARM L8: 800MHz */ + { 0, 2, 5, 0, 3, 1, 3, 0 }, - /* ARM L9: 600MHz */ - { 0, 2, 4, 0, 3, 1, 1, 0 }, + /* ARM L9: 700MHz */ + { 0, 2, 4, 0, 3, 1, 3, 0 }, - /* ARM L10: 500MHz */ - { 0, 2, 4, 0, 3, 1, 1, 0 }, + /* ARM L10: 600MHz */ + { 0, 2, 4, 0, 3, 1, 2, 0 }, + + /* ARM L11: 500MHz */ + { 0, 2, 4, 0, 3, 1, 2, 0 }, - /* ARM L11: 400MHz */ + /* ARM L12: 400MHz */ { 0, 2, 4, 0, 3, 1, 1, 0 }, - /* ARM L12: 300MHz */ + /* ARM L13: 300MHz */ { 0, 2, 4, 0, 2, 1, 1, 0 }, - /* ARM L13: 200MHz */ + /* ARM L14: 200MHz */ { 0, 1, 3, 0, 1, 1, 1, 0 }, }; @@ -168,46 +176,49 @@ static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = { /* Clock divider value for following * { DIVCOPY, DIVHPM } */ - /* ARM L0: 1500MHz */ + /* ARM L0: 1600MHz */ { 6, 0 }, - /* ARM L1: 1400MHz */ + /* ARM L1: 1500MHz */ { 6, 0 }, - /* ARM L2: 1300MHz */ + /* ARM L2: 1400MHz */ + { 6, 0 }, + + /* ARM L3: 1300MHz */ { 5, 0 }, - /* ARM L3: 1200MHz */ + /* ARM L4: 1200MHz */ { 5, 0 }, - /* ARM L4: 1100MHz */ + /* ARM L5: 1100MHz */ { 4, 0 }, - /* ARM L5: 1000MHz */ + /* ARM L6: 1000MHz */ { 4, 0 }, - /* ARM L6: 900MHz */ + /* ARM L7: 900MHz */ { 3, 0 }, - /* ARM L7: 800MHz */ + /* ARM L8: 800MHz */ { 3, 0 }, - /* ARM L8: 700MHz */ + /* ARM L9: 700MHz */ { 3, 0 }, - /* ARM L9: 600MHz */ + /* ARM L10: 600MHz */ { 3, 0 }, - /* ARM L10: 500MHz */ + /* ARM L11: 500MHz */ { 3, 0 }, - /* ARM L11: 400MHz */ + /* ARM L12: 400MHz */ { 3, 0 }, - /* ARM L12: 300MHz */ + /* ARM L13: 300MHz */ { 3, 0 }, - /* ARM L13: 200MHz */ + /* ARM L14: 200MHz */ { 3, 0 }, }; @@ -215,90 +226,96 @@ static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = { /* Clock divider value for following * { DIVCOPY, DIVHPM, DIVCORES } */ - /* ARM L0: 1500MHz */ + /* ARM L0: 1600MHz */ + { 6, 0, 7 }, + + /* ARM L1: 1500MHz */ { 6, 0, 7 }, - /* ARM L1: 1400MHz */ + /* ARM L2: 1400MHz */ { 6, 0, 6 }, - /* ARM L2: 1300MHz */ + /* ARM L3: 1300MHz */ { 5, 0, 6 }, - /* ARM L3: 1200MHz */ + /* ARM L4: 1200MHz */ { 5, 0, 5 }, - /* ARM L4: 1100MHz */ + /* ARM L5: 1100MHz */ { 4, 0, 5 }, - /* ARM L5: 1000MHz */ + /* ARM L6: 1000MHz */ { 4, 0, 4 }, - /* ARM L6: 900MHz */ + /* ARM L7: 900MHz */ { 3, 0, 4 }, - /* ARM L7: 800MHz */ + /* ARM L8: 800MHz */ { 3, 0, 3 }, - /* ARM L8: 700MHz */ + /* ARM L9: 700MHz */ { 3, 0, 3 }, - /* ARM L9: 600MHz */ + /* ARM L10: 600MHz */ { 3, 0, 2 }, - /* ARM L10: 500MHz */ + /* ARM L11: 500MHz */ { 3, 0, 2 }, - /* ARM L11: 400MHz */ + /* ARM L12: 400MHz */ { 3, 0, 1 }, - /* ARM L12: 300MHz */ + /* ARM L13: 300MHz */ { 3, 0, 1 }, - /* ARM L13: 200MHz */ + /* ARM L14: 200MHz */ { 3, 0, 0 }, }; static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = { - /* APLL FOUT L0: 1500MHz */ + /* APLL FOUT L0: 1600MHz */ + ((200<<16)|(3<<8)|(0x0)), + + /* APLL FOUT L1: 1500MHz */ ((250<<16)|(4<<8)|(0x0)), - /* APLL FOUT L1: 1400MHz */ + /* APLL FOUT L2: 1400MHz */ ((175<<16)|(3<<8)|(0x0)), - /* APLL FOUT L2: 1300MHz */ + /* APLL FOUT L3: 1300MHz */ ((325<<16)|(6<<8)|(0x0)), - /* APLL FOUT L3: 1200MHz */ + /* APLL FOUT L4: 1200MHz */ ((200<<16)|(4<<8)|(0x0)), - /* APLL FOUT L4: 1100MHz */ + /* APLL FOUT L5: 1100MHz */ ((275<<16)|(6<<8)|(0x0)), - /* APLL FOUT L5: 1000MHz */ + /* APLL FOUT L6: 1000MHz */ ((125<<16)|(3<<8)|(0x0)), - /* APLL FOUT L6: 900MHz */ + /* APLL FOUT L7: 900MHz */ ((150<<16)|(4<<8)|(0x0)), - /* APLL FOUT L7: 800MHz */ + /* APLL FOUT L8: 800MHz */ ((100<<16)|(3<<8)|(0x0)), - /* APLL FOUT L8: 700MHz */ + /* APLL FOUT L9: 700MHz */ ((175<<16)|(3<<8)|(0x1)), - /* APLL FOUT L9: 600MHz */ + /* APLL FOUT L10: 600MHz */ ((200<<16)|(4<<8)|(0x1)), - /* APLL FOUT L10: 500MHz */ + /* APLL FOUT L11: 500MHz */ ((125<<16)|(3<<8)|(0x1)), - /* APLL FOUT L11 400MHz */ + /* APLL FOUT L12 400MHz */ ((100<<16)|(3<<8)|(0x1)), - /* APLL FOUT L12: 300MHz */ + /* APLL FOUT L13: 300MHz */ ((200<<16)|(4<<8)|(0x2)), - /* APLL FOUT L13: 200MHz */ + /* APLL FOUT L14: 200MHz */ ((100<<16)|(3<<8)|(0x2)), }; @@ -312,19 +329,20 @@ static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = { static const unsigned int asv_voltage_4212[CPUFREQ_LEVEL_END][12] = { /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */ { 0, 1300000, 1300000, 1275000, 1300000, 1287500, 1275000, 1250000, 1237500, 1225000, 1225000, 1212500 }, /* L0 */ - { 1300000, 1287500, 1250000, 1225000, 1237500, 1237500, 1225000, 1200000, 1187500, 1175000, 1175000, 1162500 }, /* L1 */ - { 1237500, 1225000, 1200000, 1175000, 1187500, 1187500, 1162500, 1150000, 1137500, 1125000, 1125000, 1112500 }, /* L2 */ - { 1187500, 1175000, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1087500, 1075000, 1075000, 1062500 }, /* L3 */ - { 1137500, 1125000, 1112500, 1087500, 1112500, 1112500, 1075000, 1062500, 1050000, 1025000, 1025000, 1012500 }, /* L4 */ - { 1100000, 1087500, 1075000, 1050000, 1075000, 1062500, 1037500, 1025000, 1012500, 1000000, 987500, 975000 }, /* L5 */ - { 1050000, 1037500, 1025000, 1000000, 1025000, 1025000, 987500, 975000, 962500, 950000, 937500, 925000 }, /* L6 */ - { 1012500, 1000000, 987500, 962500, 987500, 975000, 962500, 937500, 925000, 912500, 912500, 900000 }, /* L7 */ - { 962500, 950000, 937500, 912500, 937500, 937500, 925000, 900000, 900000, 900000, 900000, 900000 }, /* L8 */ - { 925000, 912500, 912500, 900000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L9 */ - { 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L10 */ + { 0, 1300000, 1300000, 1275000, 1300000, 1287500, 1275000, 1250000, 1237500, 1225000, 1225000, 1212500 }, /* L1 */ + { 1300000, 1287500, 1250000, 1225000, 1237500, 1237500, 1225000, 1200000, 1187500, 1175000, 1175000, 1162500 }, /* L2 */ + { 1237500, 1225000, 1200000, 1175000, 1187500, 1187500, 1162500, 1150000, 1137500, 1125000, 1125000, 1112500 }, /* L3 */ + { 1187500, 1175000, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1087500, 1075000, 1075000, 1062500 }, /* L4 */ + { 1137500, 1125000, 1112500, 1087500, 1112500, 1112500, 1075000, 1062500, 1050000, 1025000, 1025000, 1012500 }, /* L5 */ + { 1100000, 1087500, 1075000, 1050000, 1075000, 1062500, 1037500, 1025000, 1012500, 1000000, 987500, 975000 }, /* L6 */ + { 1050000, 1037500, 1025000, 1000000, 1025000, 1025000, 987500, 975000, 962500, 950000, 937500, 925000 }, /* L7 */ + { 1012500, 1000000, 987500, 962500, 987500, 975000, 962500, 937500, 925000, 912500, 912500, 900000 }, /* L8 */ + { 962500, 950000, 937500, 912500, 937500, 937500, 925000, 900000, 900000, 900000, 900000, 900000 }, /* L9 */ + { 925000, 912500, 912500, 900000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L10 */ { 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L11 */ { 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L12 */ { 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L13 */ + { 912500, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000, 900000 }, /* L14 */ }; static const unsigned int asv_voltage_s[CPUFREQ_LEVEL_END] = { @@ -333,30 +351,10 @@ static const unsigned int asv_voltage_s[CPUFREQ_LEVEL_END] = { }; /* ASV table for 12.5mV step */ -#if 0 -/* 20120105 DVFS table version */ -static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = { - /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */ - { 1300000, 1300000, 1300000, 1287500, 1300000, 1287500, 1275000, 1250000, 1250000, 1237500, 1225000, 1212500 }, - { 1300000, 1300000, 1237500, 1237500, 1250000, 1250000, 1237500, 1212500, 1200000, 1200000, 1187500, 1175000 }, - { 1225000, 1212500, 1200000, 1187500, 1200000, 1187500, 1175000, 1150000, 1137500, 1125000, 1125000, 1112500 }, - { 1175000, 1162500, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1100000, 1075000, 1075000, 1062500 }, - { 1125000, 1112500, 1100000, 1087500, 1100000, 1087500, 1075000, 1050000, 1037500, 1025000, 1025000, 1012500 }, - { 1075000, 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 987500, 975000 }, - { 1037500, 1025000, 1012500, 1012500, 1012500, 1000000, 987500, 975000, 975000, 975000, 975000, 962500 }, - { 1012500, 1000000, 987500, 987500, 987500, 987500, 975000, 975000, 962500, 962500, 962500, 950000 }, - { 1000000, 987500, 975000, 975000, 975000, 975000, 962500, 962500, 950000, 950000, 950000, 937500 }, - { 987500, 975000, 962500, 950000, 962500, 950000, 950000, 950000, 925000, 925000, 925000, 912500 }, - { 975000, 962500, 950000, 925000, 950000, 925000, 925000, 925000, 900000, 900000, 900000, 887500 }, - { 950000, 937500, 925000, 900000, 925000, 900000, 900000, 900000, 900000, 887500, 875000, 862500 }, - { 925000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 887500, 875000, 875000, 862500 }, -}; -#else -/* 20120210 DVFS table version */ static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = { /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L1 - Not used */ { 1325000, 1312500, 1300000, 1287500, 1300000, 1287500, 1275000, 1250000, 1250000, 1237500, 1225000, 1212500 }, { 1300000, 1275000, 1237500, 1237500, 1250000, 1250000, 1237500, 1212500, 1200000, 1200000, 1187500, 1175000 }, { 1225000, 1212500, 1200000, 1187500, 1200000, 1187500, 1175000, 1150000, 1137500, 1125000, 1125000, 1112500 }, @@ -371,7 +369,46 @@ static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = { { 950000, 937500, 925000, 900000, 925000, 900000, 900000, 900000, 900000, 887500, 875000, 862500 }, { 925000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 887500, 875000, 875000, 862500 }, }; -#endif + +/* 20120725 DVFS table for pega prime */ +static const unsigned int asv_voltage_step_12_5_rev2[CPUFREQ_LEVEL_END][13] = { + /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 ASV12 */ + { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 }, /* L0 */ + { 1275000, 1262500, 1262500, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1162500, 1150000, 1137500 }, /* L1 */ + { 1237500, 1225000, 1225000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1125000, 1112500, 1100000 }, /* L2 */ + { 1187500, 1175000, 1175000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1075000, 1062500, 1050000 }, /* L3 */ + { 1150000, 1137500, 1137500, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1037500, 1025000, 1012500 }, /* L4 */ + { 1112500, 1100000, 1100000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1000000, 987500, 975000 }, /* L5 */ + { 1087500, 1075000, 1075000, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 975000, 962500, 950000 }, /* L6 */ + { 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, 950000, 937500, 925000 }, /* L7 */ + { 1025000, 1012500, 1012500, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500, 912500, 900000, 887500 }, /* L8 */ + { 1000000, 987500, 987500, 987500, 975000, 962500, 950000, 937500, 925000, 912500, 887500, 887500, 887500 }, /* L9 */ + { 975000, 962500, 962500, 962500, 950000, 937500, 925000, 912500, 900000, 887500, 875000, 875000, 875000 }, /* L10 */ + { 962500, 950000, 950000, 950000, 937500, 925000, 912500, 900000, 887500, 887500, 875000, 875000, 875000 }, /* L11 */ + { 950000, 937500, 937500, 937500, 925000, 912500, 900000, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L12 */ + { 937500, 925000, 925000, 925000, 912500, 900000, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L13 */ + { 925000, 912500, 912500, 912500, 900000, 887500, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L14 */ +}; + +static const unsigned int asv_voltage_step_1ghz[CPUFREQ_LEVEL_END][12] = { + /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L1 - Not used */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L2 - Not used */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L3 - Not used */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L4 - Not used */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L5 - Not used */ + { 1200000, 1200000, 1200000, 1200000, 1125000, 1125000, 1125000, 1075000, 1075000, 1075000, 1075000, 1037500 }, + { 1150000, 1150000, 1150000, 1150000, 1075000, 1075000, 1075000, 1037500, 1037500, 1037500, 1037500, 1000000 }, + { 1100000, 1100000, 1100000, 1100000, 1025000, 1025000, 1025000, 987500, 987500, 987500, 987500, 975000 }, + { 1050000, 1050000, 1050000, 1050000, 1000000, 1000000, 1000000, 987500, 987500, 987500, 987500, 962500 }, + { 1025000, 1025000, 1025000, 1025000, 987500, 987500, 987500, 975000, 975000, 975000, 975000, 950000 }, + { 1000000, 1000000, 1000000, 1000000, 975000, 975000, 975000, 962500, 962500, 962500, 962500, 925000 }, + { 1000000, 1000000, 1000000, 1000000, 975000, 975000, 975000, 950000, 950000, 950000, 950000, 912500 }, + { 975000, 975000, 975000, 975000, 950000, 950000, 950000, 925000, 925000, 925000, 925000, 887500 }, + { 975000, 975000, 975000, 975000, 937500, 937500, 937500, 925000, 925000, 925000, 925000, 887500 }, +}; + static void set_clkdiv(unsigned int div_index) { unsigned int tmp; @@ -470,6 +507,16 @@ static void exynos4x12_set_frequency(unsigned int old_index, unsigned int tmp; if (old_index > new_index) { + if (exynos4x12_volt_table[new_index] >= 950000 && + need_dynamic_ema) + __raw_writel(0x101, EXYNOS4_EMA_CONF); + + if ((samsung_rev() >= EXYNOS4412_REV_2_0) + && (exynos_result_of_asv > 2) + && (old_index > L8) && (new_index <= L8)) { + exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V); + } + if (!exynos4x12_pms_change(old_index, new_index)) { /* 1. Change the system clock divider values */ set_clkdiv(new_index); @@ -502,62 +549,53 @@ static void exynos4x12_set_frequency(unsigned int old_index, /* 2. Change the system clock divider values */ set_clkdiv(new_index); } + if ((samsung_rev() >= EXYNOS4412_REV_2_0) + && (exynos_result_of_asv > 2) + && (old_index <= L8) && (new_index > L8)) { + exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_100V); + } + if (exynos4x12_volt_table[new_index] < 950000 && + need_dynamic_ema) + __raw_writel(0x404, EXYNOS4_EMA_CONF); } /* ABB value is changed in below case */ - if (soc_is_exynos4412() && (exynos_result_of_asv > 3)) { - if (new_index == L13) + if (soc_is_exynos4412() && (exynos_result_of_asv > 3) + && (samsung_rev() < EXYNOS4412_REV_2_0)) { + if (new_index == L14) exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V); } } -static void __init set_volt_table(void) +/* Get maximum cpufreq index of chip */ +static unsigned int get_max_cpufreq_idx(void) { - bool for_1500 = false, for_1200 = false, for_1400 = false; - unsigned int i; - -#ifdef CONFIG_EXYNOS4X12_1500MHZ_SUPPORT - for_1500 = true; - max_support_idx = L0; -#elif defined(CONFIG_EXYNOS4X12_1200MHZ_SUPPORT) - for_1200 = true; - max_support_idx = L3; -#elif defined(CONFIG_EXYNOS4X12_1400MHZ_SUPPORT) - for_1400 = true; - max_support_idx = L1; - - /* It doesn't support 1400Mhz under EVT1 or when IDS >= 40 */ - if (samsung_rev() < EXYNOS4412_REV_1_0 || exynos_result_of_asv > 9) { - for_1200 = true; - max_support_idx = L3; - } -#else - max_support_idx = L5; -#endif - /* - * Should be fixed !!! - */ -#if 0 - if ((asv_group == 0) || !for_1400) - exynos4212_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID; -#else - if (!for_1500 && !for_1200 && !for_1400) { - exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID; - exynos4x12_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID; - exynos4x12_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID; - exynos4x12_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID; - exynos4x12_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID; - } else if (for_1200) { - exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID; - exynos4x12_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID; - exynos4x12_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID; - } else if (for_1400) { - exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID; + unsigned int index; + + /* exynos4x12 prime supports 1.6GHz */ + if (samsung_rev() >= EXYNOS4412_REV_2_0) + index = L0; + else { + /* exynos4x12 supports only 1.4GHz and 1.1GHz */ + if (exynos_armclk_max != 1400000) + index = L6; + else + index = L2; } -#endif + return index; +} + +static void __init set_volt_table(void) +{ + unsigned int i, tmp; + + max_support_idx = get_max_cpufreq_idx(); + + for (i = 0; i < max_support_idx; i++) + exynos4x12_freq_table[i].frequency = CPUFREQ_ENTRY_INVALID; pr_info("DVFS : VDD_ARM Voltage table set with %d Group\n", exynos_result_of_asv); @@ -570,13 +608,62 @@ static void __init set_volt_table(void) exynos4x12_volt_table[i] = asv_voltage_4212[i][exynos_result_of_asv]; } else if (soc_is_exynos4412()) { - for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) - exynos4x12_volt_table[i] = - asv_voltage_step_12_5[i][exynos_result_of_asv]; + if (samsung_rev() >= EXYNOS4412_REV_2_0) { + for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) + exynos4x12_volt_table[i] = + asv_voltage_step_12_5_rev2[i][exynos_result_of_asv]; + } else { + if (exynos_armclk_max == 1000000) { + for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) + exynos4x12_volt_table[i] = + asv_voltage_step_1ghz[i][exynos_result_of_asv]; + } else { + for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) + exynos4x12_volt_table[i] = + asv_voltage_step_12_5[i][exynos_result_of_asv]; + } + } } else { pr_err("%s: Can't find SoC type \n", __func__); } } + + if (soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_2_0)) { + tmp = (is_special_flag() >> ARM_LOCK_FLAG) & 0x3; + + if (tmp) { + pr_info("%s : special flag[%d]\n", __func__, tmp); + switch (tmp) { + case 1: + /* 500MHz fixed volt */ + i = L11; + break; + case 2: + /* 700MHz fixed volt */ + i = L9; + break; + case 3: + /* 800MHz fixed volt */ + i = L8; + break; + default: + break; + } + + pr_info("ARM voltage locking at L%d\n", i); + + for (tmp = (i + 1) ; tmp < CPUFREQ_LEVEL_END ; tmp++) { + exynos4x12_volt_table[tmp] = + exynos4x12_volt_table[i]; + pr_info("CPUFREQ: L%d : %d\n", tmp, exynos4x12_volt_table[tmp]); + } + } + + if (exynos_dynamic_ema) { + need_dynamic_ema = true; + pr_info("%s: Dynamic EMA is enabled\n", __func__); + } + } } /* @@ -586,10 +673,10 @@ static void __init set_volt_table(void) */ #ifdef CONFIG_SLP static struct dvfs_qos_info exynos4x12_dma_lat_qos[] = { - { 118, 200000, L13 }, - { 40, 500000, L10 }, - { 24, 800000, L7 }, - { 16, 1000000, L5 }, + { 118, 200000, L14 }, + { 40, 500000, L11 }, + { 24, 800000, L8 }, + { 16, 1000000, L6 }, {}, }; #endif @@ -677,8 +764,8 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) info->mpll_freq_khz = rate; #ifdef CONFIG_SLP - /* S-Boot at 20120406 uses L7 at bootup */ - info->pm_lock_idx = L7; + /* S-Boot at 20120406 uses L8 at bootup */ + info->pm_lock_idx = L8; /* * However, the bootup frequency might get changed anytime. @@ -695,9 +782,20 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) pr_info("Bootup CPU Frequency = [%d] %dMHz\n", info->pm_lock_idx, rate / 1000); #else - info->pm_lock_idx = L5; + info->pm_lock_idx = L6; #endif - info->pll_safe_idx = L7; + /* + * ARM clock source will be changed APLL to MPLL temporary + * in exynos4x12_set_frequency. + * To support MPLL, vdd_arm is supplied to voltage at frequency + * higher than MPLL. + * So, pll_safe_idx set to value based on MPLL clock.(800MHz or 880MHz) + */ + if (samsung_rev() >= EXYNOS4412_REV_2_0) + info->pll_safe_idx = L7; + else + info->pll_safe_idx = L8; + info->max_support_idx = max_support_idx; info->min_support_idx = min_support_idx; info->cpu_clk = cpu_clk; diff --git a/arch/arm/mach-exynos/cpufreq-5250.c b/arch/arm/mach-exynos/cpufreq-5250.c deleted file mode 100644 index cf78c81..0000000 --- a/arch/arm/mach-exynos/cpufreq-5250.c +++ /dev/null @@ -1,526 +0,0 @@ -/* linux/arch/arm/mach-exynos/cpufreq-5250.c - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS5250 - CPU frequency scaling support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/cpufreq.h> - -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu.h> -#include <mach/regs-pmu-5250.h> -#include <mach/cpufreq.h> -#include <mach/asv.h> - -#include <plat/clock.h> -#include <plat/cpu.h> - -#define CPUFREQ_LEVEL_END (L20 + 1) - -#undef PRINT_DIV_VAL - -#undef ENABLE_CLKOUT - -static int max_support_idx; -static int min_support_idx = (CPUFREQ_LEVEL_END - 1); -static struct clk *cpu_clk; -static struct clk *moutcore; -static struct clk *mout_mpll; -static struct clk *mout_apll; - -struct cpufreq_clkdiv { - unsigned int index; - unsigned int clkdiv; - unsigned int clkdiv1; -}; - -static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END]; - -static struct cpufreq_frequency_table exynos5250_freq_table[] = { - {L0, 2200*1000}, - {L1, 2100*1000}, - {L2, 2000*1000}, - {L3, 1900*1000}, - {L4, 1800*1000}, - {L5, 1700*1000}, - {L6, 1600*1000}, - {L7, 1500*1000}, - {L8, 1400*1000}, - {L9, 1300*1000}, - {L10, 1200*1000}, - {L11, 1100*1000}, - {L12, 1000*1000}, - {L13, 900*1000}, - {L14, 800*1000}, - {L15, 700*1000}, - {L16, 600*1000}, - {L17, 500*1000}, - {L18, 400*1000}, - {L19, 300*1000}, - {L20, 200*1000}, - {0, CPUFREQ_TABLE_END}, -}; - -static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END]; - -static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = { - /* - * Clock divider value for following - * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 } - */ - { 0, 5, 7, 7, 7, 1, 5, 0 }, /* L0: 2200Mhz */ - { 0, 5, 7, 7, 7, 1, 5, 0 }, /* L1: 2100Mhz */ - { 0, 5, 7, 7, 7, 1, 5, 0 }, /* L2: 2000Mhz */ - { 0, 4, 7, 7, 7, 1, 5, 0 }, /* L3: 1900Mhz */ - { 0, 4, 7, 7, 7, 1, 4, 0 }, /* L4: 1800Mhz */ - { 0, 3, 7, 7, 7, 3, 5, 0 }, /* L5: 1700Mhz */ - { 0, 3, 7, 7, 7, 1, 4, 0 }, /* L6: 1600MHz */ - { 0, 2, 7, 7, 7, 1, 4, 0 }, /* L7: 1500Mhz */ - { 0, 2, 7, 7, 6, 1, 4, 0 }, /* L8: 1400Mhz */ - { 0, 2, 7, 7, 6, 1, 3, 0 }, /* L9: 1300Mhz */ - { 0, 2, 7, 7, 5, 1, 3, 0 }, /* L10: 1200Mhz */ - { 0, 3, 7, 7, 5, 1, 3, 0 }, /* L11: 1100MHz */ - { 0, 1, 7, 7, 4, 1, 2, 0 }, /* L12: 1000MHz */ - { 0, 1, 7, 7, 4, 1, 2, 0 }, /* L13: 900MHz */ - { 0, 1, 7, 7, 4, 1, 2, 0 }, /* L14: 800MHz */ - { 0, 1, 7, 7, 3, 1, 1, 0 }, /* L15: 700MHz */ - { 0, 1, 7, 7, 3, 1, 1, 0 }, /* L16: 600MHz */ - { 0, 1, 7, 7, 2, 1, 1, 0 }, /* L17: 500MHz */ - { 0, 1, 7, 7, 2, 1, 1, 0 }, /* L18: 400MHz */ - { 0, 1, 7, 7, 1, 1, 1, 0 }, /* L19: 300MHz */ - { 0, 1, 7, 7, 1, 1, 1, 0 }, /* L20: 200MHz */ -}; - -static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = { - /* Clock divider value for following - * { COPY, HPM } - */ - { 0, 2 }, /* L0: 2200Mhz */ - { 0, 2 }, /* L1: 2100Mhz */ - { 0, 2 }, /* L2: 2000Mhz */ - { 0, 2 }, /* L3: 1900Mhz */ - { 0, 2 }, /* L4: 1800Mhz */ - { 0, 2 }, /* L5: 1700Mhz */ - { 0, 2 }, /* L6: 1600MHz */ - { 0, 2 }, /* L7: 1500Mhz */ - { 0, 2 }, /* L8: 1400Mhz */ - { 0, 2 }, /* L9: 1300Mhz */ - { 0, 2 }, /* L10: 1200Mhz */ - { 0, 2 }, /* L11: 1100MHz */ - { 0, 2 }, /* L12: 1000MHz */ - { 0, 2 }, /* L13: 900MHz */ - { 0, 2 }, /* L14: 800MHz */ - { 0, 2 }, /* L15: 700MHz */ - { 0, 2 }, /* L16: 600MHz */ - { 0, 2 }, /* L17: 500MHz */ - { 0, 2 }, /* L18: 400MHz */ - { 0, 2 }, /* L19: 300MHz */ - { 0, 2 }, /* L20: 200MHz */ -}; - -static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = { - ((275<<16)|(3<<8)|(0)), /* L0: 2200Mhz */ - ((350<<16)|(4<<8)|(0)), /* L1: 2100Mhz */ - ((250<<16)|(3<<8)|(0)), /* L2: 2000Mhz */ - ((475<<16)|(6<<8)|(0)), /* L3: 1900Mhz */ - ((225<<16)|(3<<8)|(0)), /* L4: 1800Mhz */ - ((425<<16)|(6<<8)|(0)), /* L5: 1700Mhz */ - ((200<<16)|(3<<8)|(0)), /* L6: 1600MHz */ - ((250<<16)|(4<<8)|(0)), /* L7: 1500Mhz */ - ((175<<16)|(3<<8)|(0)), /* L8: 1400Mhz */ - ((325<<16)|(6<<8)|(0)), /* L9: 1300Mhz */ - ((200<<16)|(4<<8)|(0)), /* L10: 1200Mhz */ - ((275<<16)|(6<<8)|(0)), /* L11: 1100MHz */ - ((125<<16)|(3<<8)|(0)), /* L12: 1000MHz */ - ((150<<16)|(4<<8)|(0)), /* L13: 900MHz */ - ((100<<16)|(3<<8)|(0)), /* L14: 800MHz */ - ((175<<16)|(3<<8)|(1)), /* L15: 700MHz */ - ((200<<16)|(4<<8)|(1)), /* L16: 600MHz */ - ((125<<16)|(3<<8)|(1)), /* L17: 500MHz */ - ((100<<16)|(3<<8)|(1)), /* L18: 400MHz */ - ((200<<16)|(4<<8)|(2)), /* L19: 300MHz */ - ((100<<16)|(3<<8)|(2)), /* L20: 200MHz */ -}; - -/* - * ASV group voltage table - */ - -#define NUM_ASV_GROUP L10 - - -static const unsigned int asv_voltage[CPUFREQ_LEVEL_END][NUM_ASV_GROUP+1] = { - /* ASV0 is not exist */ - /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10 */ - { 0 }, /* L0 */ - { 0 }, /* L1 */ - { 0 }, /* L2 */ - { 0 }, /* L3 */ - { 0 }, /* L4 */ - { 0, 1300000, 1275000, 1287500, 1275000, 1275000, 1262500, 1250000, 1237500, 1225000, 1225000 }, /* L5 */ - { 0, 1250000, 1237500, 1250000, 1237500, 1250000, 1237500, 1225000, 1212500, 1200000, 1200000 }, /* L6 */ - { 0, 1225000, 1200000, 1212500, 1200000, 1212500, 1200000, 1187500, 1175000, 1175000, 1150000 }, /* L7 */ - { 0, 1200000, 1175000, 1200000, 1175000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000 }, /* L8 */ - { 0, 1150000, 1125000, 1150000, 1125000, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000 }, /* L9 */ - { 0, 1125000, 1112500, 1125000, 1112500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 }, /* L10 */ - { 0, 1100000, 1075000, 1100000, 1087500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500 }, /* L11 */ - { 0, 1075000, 1050000, 1062500, 1050000, 1062500, 1050000, 1050000, 1037500, 1025000, 1012500 }, /* L12 */ - { 0, 1050000, 1025000, 1050000, 1037500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500 }, /* L13 */ - { 0, 1025000, 1012500, 1025000, 1012500, 1025000, 1012500, 1000000, 1000000, 987500, 975000 }, /* L14 */ - { 0, 1012500, 1000000, 1012500, 1000000, 1012500, 1000000, 987500, 975000, 975000, 962500 }, /* L15 */ - { 0, 1000000, 975000, 1000000, 975000, 1000000, 987500, 975000, 962500, 962500, 950000 }, /* L16 */ - { 0, 975000, 962500, 975000, 962500, 975000, 962500, 950000, 937500, 925000, 925000 }, /* L17 */ - { 0, 950000, 937500, 950000, 937500, 950000, 937500, 925000, 925000, 925000, 912500 }, /* L18 */ - { 0, 937500, 925000, 937500, 925000, 937500, 925000, 912500, 912500, 900000, 900000 }, /* L19 */ - { 0, 925000, 912500, 925000, 912500, 925000, 912500, 900000, 900000, 887500, 887500 }, /* L20 */ -}; - -static const unsigned int asv_voltage_rev0[CPUFREQ_LEVEL_END][NUM_ASV_GROUP] = { - { 0 }, /* L0 */ - { 0 }, /* L1 */ - { 0 }, /* L2 */ - { 0 }, /* L3 */ - { 0 }, /* L4 */ - { 1200000 }, /* L5 */ - { 1200000 }, /* L6 */ - { 1200000 }, /* L7 */ - { 1200000 }, /* L8 */ - { 1200000 }, /* L9 */ - { 1200000 }, /* L10 */ - { 1200000 }, /* L11 */ - { 1175000 }, /* L12 */ - { 1125000 }, /* L13 */ - { 1075000 }, /* L14 */ - { 1050000 }, /* L15 */ - { 1000000 }, /* L16 */ - { 950000 }, /* L17 */ - { 925000 }, /* L18 */ - { 925000 }, /* L19 */ - { 900000 }, /* L20 */ -}; - -#if defined(CONFIG_EXYNOS5250_ABB_WA) -#define ARM_RBB 6 /* +300mV */ -unsigned int exynos5250_arm_volt; - -#define INT_VOLT 1050000 -#endif - -static void set_clkdiv(unsigned int div_index) -{ - unsigned int tmp; - - /* Change Divider - CPU0 */ - - tmp = exynos5250_clkdiv_table[div_index].clkdiv; - - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STATCPU0); - } while (tmp & 0x11111111); - -#ifdef PRINT_DIV_VAL - tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0); - pr_info("DIV_CPU0[0x%x]\n", tmp); - -#endif - - /* Change Divider - CPU1 */ - tmp = exynos5250_clkdiv_table[div_index].clkdiv1; - - __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1); - - do { - tmp = __raw_readl(EXYNOS5_CLKDIV_STATCPU1); - } while (tmp & 0x11); -#ifdef PRINT_DIV_VAL - tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1); - pr_info("DIV_CPU1[0x%x]\n", tmp); -#endif -} - -static void set_apll(unsigned int new_index, - unsigned int old_index) -{ - unsigned int tmp, pdiv; - - /* 1. MUX_CORE_SEL = MPLL, - * ARMCLK uses MPLL for lock time */ - if (clk_set_parent(moutcore, mout_mpll)) - pr_err("Unable to set parent %s of clock %s.\n", - mout_mpll->name, moutcore->name); - - do { - tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16); - tmp &= 0x7; - } while (tmp != 0x2); - - /* 2. Set APLL Lock time */ - pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f); - - __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK); - - /* 3. Change PLL PMS values */ - tmp = __raw_readl(EXYNOS5_APLL_CON0); - tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); - tmp |= exynos5_apll_pms_table[new_index]; - __raw_writel(tmp, EXYNOS5_APLL_CON0); - - /* 4. wait_lock_time */ - do { - tmp = __raw_readl(EXYNOS5_APLL_CON0); - } while (!(tmp & (0x1 << 29))); - - /* 5. MUX_CORE_SEL = APLL */ - if (clk_set_parent(moutcore, mout_apll)) - pr_err("Unable to set parent %s of clock %s.\n", - mout_apll->name, moutcore->name); - - do { - tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU); - tmp &= (0x7 << 16); - } while (tmp != (0x1 << 16)); - -} - -bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index) -{ - unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8); - unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8); - - return (old_pm == new_pm) ? 0 : 1; -} - -#if defined(CONFIG_EXYNOS5250_ABB_WA) -static DEFINE_SPINLOCK(abb_lock); -void exynos5250_set_arm_abbg(unsigned int arm_volt, unsigned int int_volt) -{ - unsigned int setbits = 8; - unsigned int tmp, diff_volt; - unsigned long flag; - - spin_lock_irqsave(&abb_lock, flag); - if (arm_volt >= int_volt) { - diff_volt = arm_volt - int_volt; - setbits += diff_volt / 50000; - } else { - diff_volt = int_volt - arm_volt; - setbits -= diff_volt / 50000; - } - tmp = __raw_readl(EXYNOS5_ABBG_ARM_CONTROL); - tmp &= ~(0x1f | (1 << 31) | (1 << 7)); - tmp |= ((setbits + ARM_RBB) | (1 << 31) | (1 << 7)); - __raw_writel(tmp, EXYNOS5_ABBG_ARM_CONTROL); - spin_unlock_irqrestore(&abb_lock, flag); -} -EXPORT_SYMBOL(exynos5250_set_arm_abbg); -#endif - -static void exynos5250_set_frequency(unsigned int old_index, - unsigned int new_index) -{ - unsigned int tmp; -#if defined(CONFIG_EXYNOS5250_ABB_WA) - unsigned int voltage; - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - voltage = asv_voltage_rev0[new_index][0]; - exynos5250_set_arm_abbg(voltage, INT_VOLT); - } -#endif - if (old_index > new_index) { - if (!exynos5250_pms_change(old_index, new_index)) { - /* 1. Change the system clock divider values */ - set_clkdiv(new_index); - /* 2. Change just s value in apll m,p,s value */ - tmp = __raw_readl(EXYNOS5_APLL_CON0); - tmp &= ~(0x7 << 0); - tmp |= (exynos5_apll_pms_table[new_index] & 0x7); - __raw_writel(tmp, EXYNOS5_APLL_CON0); - - } else { - /* Clock Configuration Procedure */ - /* 1. Change the system clock divider values */ - set_clkdiv(new_index); - /* 2. Change the apll m,p,s value */ - set_apll(new_index, old_index); - } - } else if (old_index < new_index) { - if (!exynos5250_pms_change(old_index, new_index)) { - /* 1. Change just s value in apll m,p,s value */ - tmp = __raw_readl(EXYNOS5_APLL_CON0); - tmp &= ~(0x7 << 0); - tmp |= (exynos5_apll_pms_table[new_index] & 0x7); - __raw_writel(tmp, EXYNOS5_APLL_CON0); - /* 2. Change the system clock divider values */ - set_clkdiv(new_index); - } else { - /* Clock Configuration Procedure */ - /* 1. Change the apll m,p,s value */ - set_apll(new_index, old_index); - /* 2. Change the system clock divider values */ - set_clkdiv(new_index); - } - } -} - -static void __init set_volt_table(void) -{ - unsigned int asv_group; - unsigned int i; - - if (soc_is_exynos5250()) { - exynos5250_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID; - - switch (samsung_rev() & 0xf0) { - case EXYNOS5250_REV_0: - exynos5250_freq_table[L5].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L6].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L7].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L8].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L9].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L10].frequency = CPUFREQ_ENTRY_INVALID; - exynos5250_freq_table[L11].frequency = CPUFREQ_ENTRY_INVALID; - - max_support_idx = L12; - break; - case EXYNOS5250_REV_1_0: - max_support_idx = L5; - break; - default: - pr_err("%s: Can't find cpu revision(%d) type\n", __func__, - samsung_rev()); - break; - } - } - - if (soc_is_exynos5250() && samsung_rev() < EXYNOS5250_REV_1_0) - asv_group = 0; - else - asv_group = exynos_result_of_asv; - - pr_info("DVFS : VDD_ARM Voltage table set with %d Group\n", asv_group); - pr_info("DVFS : VDD_ARM Voltage of max level is %d\n", asv_voltage[max_support_idx][asv_group]); - - for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) { - if (samsung_rev() < EXYNOS5250_REV_1_0) - exynos5250_volt_table[i] = asv_voltage_rev0[i][asv_group]; - else - exynos5250_volt_table[i] = asv_voltage[i][asv_group]; - } -} - -int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) -{ - int i; - unsigned int tmp; - unsigned long rate; - - set_volt_table(); - - cpu_clk = clk_get(NULL, "armclk"); - if (IS_ERR(cpu_clk)) - return PTR_ERR(cpu_clk); - - moutcore = clk_get(NULL, "moutcpu"); - if (IS_ERR(moutcore)) - goto err_moutcore; - - mout_mpll = clk_get(NULL, "mout_mpll"); - if (IS_ERR(mout_mpll)) - goto err_mout_mpll; - - rate = clk_get_rate(mout_mpll) / 1000; - - mout_apll = clk_get(NULL, "mout_apll"); - if (IS_ERR(mout_apll)) - goto err_mout_apll; - - for (i = L0; i < CPUFREQ_LEVEL_END; i++) { - - exynos5250_clkdiv_table[i].index = i; - - tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0); - - tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) | - (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | - (0x7 << 24) | (0x7 << 28)); - - tmp |= ((clkdiv_cpu0_5250[i][0] << 0) | - (clkdiv_cpu0_5250[i][1] << 4) | - (clkdiv_cpu0_5250[i][2] << 8) | - (clkdiv_cpu0_5250[i][3] << 12) | - (clkdiv_cpu0_5250[i][4] << 16) | - (clkdiv_cpu0_5250[i][5] << 20) | - (clkdiv_cpu0_5250[i][6] << 24) | - (clkdiv_cpu0_5250[i][7] << 28)); - - exynos5250_clkdiv_table[i].clkdiv = tmp; - - tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1); - - tmp &= ~((0x7 << 0) | (0x7 << 4)); - - tmp |= ((clkdiv_cpu1_5250[i][0] << 0) | - (clkdiv_cpu1_5250[i][1] << 4)); - - exynos5250_clkdiv_table[i].clkdiv1 = tmp; - } - - info->mpll_freq_khz = rate; - /* 1000Mhz */ - info->pm_lock_idx = L12; - /* 800Mhz */ - info->pll_safe_idx = L14; - info->max_support_idx = max_support_idx; - info->min_support_idx = min_support_idx; - info->cpu_clk = cpu_clk; - info->volt_table = exynos5250_volt_table; - info->freq_table = exynos5250_freq_table; - info->set_freq = exynos5250_set_frequency; - info->need_apll_change = exynos5250_pms_change; - -#ifdef ENABLE_CLKOUT - tmp = __raw_readl(EXYNOS5_CLKOUT_CMU_CPU); - p &= ~0xffff; - tmp |= 0x1904; - __raw_writel(tmp, EXYNOS5_CLKOUT_CMU_CPU); - - tmp = __raw_readl(S5P_PMU_DEBUG); - tmp &= ~0xf00; - tmp |= 0x400; - __raw_writel(tmp, S5P_PMU_DEBUG); - -#endif - return 0; - -err_mout_apll: - if (!IS_ERR(mout_mpll)) - clk_put(mout_mpll); -err_mout_mpll: - if (!IS_ERR(moutcore)) - clk_put(moutcore); -err_moutcore: - if (!IS_ERR(cpu_clk)) - clk_put(cpu_clk); - - pr_err("%s: failed initialization\n", __func__); - return -EINVAL; -} -EXPORT_SYMBOL(exynos5250_cpufreq_init); diff --git a/arch/arm/mach-exynos/cpufreq.c b/arch/arm/mach-exynos/cpufreq.c index e78dad9..cdfec03 100644 --- a/arch/arm/mach-exynos/cpufreq.c +++ b/arch/arm/mach-exynos/cpufreq.c @@ -32,6 +32,11 @@ #include <plat/pm.h> #include <plat/cpu.h> +#if defined(CONFIG_MACH_PX) || defined(CONFIG_MACH_Q1_BD) ||\ + defined(CONFIG_MACH_P4NOTE) || defined(CONFIG_MACH_GC1) +#include <mach/sec_debug.h> +#endif + struct exynos_dvfs_info *exynos_info; static struct regulator *arm_regulator; @@ -316,6 +321,7 @@ int exynos_cpufreq_lock(unsigned int nId, mutex_lock(&set_freq_lock); freq_old = policy->cur; freq_new = freq_table[cpufreq_level].frequency; + if (freq_old < freq_new) { /* Find out current level index */ for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { @@ -348,6 +354,7 @@ int exynos_cpufreq_lock(unsigned int nId, cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); } + mutex_unlock(&set_freq_lock); return ret; @@ -470,6 +477,7 @@ int exynos_cpufreq_upper_limit(unsigned int nId, /* If cur frequency is higher than limit freq, it needs to update */ freq_old = policy->cur; freq_new = freq_table[cpufreq_level].frequency; + if (freq_old > freq_new) { /* Find out current level index */ for (i = 0; i <= exynos_info->min_support_idx; i++) { diff --git a/arch/arm/mach-exynos/cpuidle-exynos4.c b/arch/arm/mach-exynos/cpuidle-exynos4.c index 6afdacd..08c5b05 100644 --- a/arch/arm/mach-exynos/cpuidle-exynos4.c +++ b/arch/arm/mach-exynos/cpuidle-exynos4.c @@ -60,6 +60,10 @@ extern unsigned long sys_pwr_conf_addr; extern unsigned int l2x0_save[3]; extern unsigned int scu_save[2]; +#ifdef CONFIG_FAST_RESUME +static void exynos4_init_cpuidle_post_hib(void); +#endif + enum hc_type { HC_SDHC, HC_MSHC, @@ -338,6 +342,9 @@ static int check_usb_op(void) } #ifdef CONFIG_SND_SAMSUNG_RP +#if defined(CONFIG_MACH_U1_NA_SPR) +#include "../../../sound/soc/samsung/srp-types.h" +#endif extern int srp_get_op_level(void); /* By srp driver */ #endif @@ -363,6 +370,33 @@ static inline int check_gps_uart_op(void) return gps_is_running; } +#ifdef CONFIG_INTERNAL_MODEM_IF +static int check_idpram_op(void) +{ + /* This pin is high when CP might be accessing dpram */ + int cp_int = gpio_get_value(GPIO_CP_AP_DPRAM_INT); + if (cp_int != 0) + pr_info("%s cp_int is high.\n", __func__); + return cp_int; +} +#endif + +static atomic_t sromc_use_count; + +void set_sromc_access(bool access) +{ + if (access) + atomic_set(&sromc_use_count, 1); + else + atomic_set(&sromc_use_count, 0); +} +EXPORT_SYMBOL(set_sromc_access); + +static inline int check_sromc_access(void) +{ + return atomic_read(&sromc_use_count); +} + static int exynos4_check_operation(void) { if (check_power_domain()) @@ -376,6 +410,10 @@ static int exynos4_check_operation(void) #ifdef CONFIG_SND_SAMSUNG_RP if (srp_get_op_level()) return 1; +#if defined(CONFIG_MACH_U1_NA_SPR) + if (!srp_get_status(IS_RUNNING)) + return 1; +#endif #endif if (check_usb_op()) return 1; @@ -385,12 +423,22 @@ static int exynos4_check_operation(void) return 1; #endif +#ifdef CONFIG_INTERNAL_MODEM_IF + if (check_idpram_op()) + return 1; +#endif + if (check_gps_uart_op()) return 1; if (exynos4_check_usb_op()) return 1; + if (check_sromc_access()) { + pr_info("%s: SROMC is in use!!!\n", __func__); + return 1; + } + return 0; } @@ -586,6 +634,10 @@ static int exynos4_enter_core0_lpa(struct cpuidle_device *dev, #endif local_irq_disable(); +#ifdef CONFIG_INTERNAL_MODEM_IF + gpio_set_value(GPIO_PDA_ACTIVE, 0); +#endif + if (log_en) pr_info("+++lpa\n"); @@ -678,6 +730,9 @@ early_wakeup: if (log_en) pr_info("---lpa\n"); +#ifdef CONFIG_INTERNAL_MODEM_IF + gpio_set_value(GPIO_PDA_ACTIVE, 1); +#endif local_irq_enable(); idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + @@ -807,12 +862,18 @@ static int exynos4_check_entermode(void) return ret; } +#ifdef CONFIG_CORESIGHT_ETM +extern int etm_enable(int pm_enable); +extern int etm_disable(int pm_enable); +#endif + static int exynos4_enter_lowpower(struct cpuidle_device *dev, struct cpuidle_state *state) { struct cpuidle_state *new_state = state; unsigned int enter_mode; unsigned int tmp; + int ret; /* This mode only can be entered when only Core0 is online */ if (num_online_cpus() != 1) { @@ -832,10 +893,20 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev, enter_mode = exynos4_check_entermode(); if (!enter_mode) return exynos4_enter_idle(dev, new_state); - else if (enter_mode == S5P_CHECK_DIDLE) - return exynos4_enter_core0_aftr(dev, new_state); - else - return exynos4_enter_core0_lpa(dev, new_state); + else { +#ifdef CONFIG_CORESIGHT_ETM + etm_disable(0); +#endif + if (enter_mode == S5P_CHECK_DIDLE) + ret = exynos4_enter_core0_aftr(dev, new_state); + else + ret = exynos4_enter_core0_lpa(dev, new_state); +#ifdef CONFIG_CORESIGHT_ETM + etm_enable(0); +#endif + } + + return ret; } static int exynos4_cpuidle_notifier_event(struct notifier_block *this, @@ -844,9 +915,15 @@ static int exynos4_cpuidle_notifier_event(struct notifier_block *this, { switch (event) { case PM_SUSPEND_PREPARE: + case PM_HIBERNATION_PREPARE: + case PM_RESTORE_PREPARE: disable_hlt(); pr_debug("PM_SUSPEND_PREPARE for CPUIDLE\n"); return NOTIFY_OK; + case PM_POST_HIBERNATION: +#ifdef CONFIG_FAST_RESUME + exynos4_init_cpuidle_post_hib(); +#endif case PM_POST_RESTORE: case PM_POST_SUSPEND: enable_hlt(); @@ -920,6 +997,35 @@ static void __init exynos4_core_down_clk(void) #define exynos4_core_down_clk() do { } while (0) #endif +#ifdef CONFIG_FAST_RESUME +static void exynos4_init_cpuidle_post_hib(void) +{ + if (soc_is_exynos4210()) + use_clock_down = SW_CLK_DWN; + else + use_clock_down = HW_CLK_DWN; + + /* Clock down feature can use only EXYNOS4212 */ + if (use_clock_down == HW_CLK_DWN) + exynos4_core_down_clk(); + + sys_pwr_conf_addr = (unsigned long)S5P_CENTRAL_SEQ_CONFIGURATION; + + /* Save register value for SCU */ + scu_save[0] = __raw_readl(S5P_VA_SCU + 0x30); + scu_save[1] = __raw_readl(S5P_VA_SCU + 0x0); + + /* Save register value for L2X0 */ + l2x0_save[0] = __raw_readl(S5P_VA_L2CC + 0x108); + l2x0_save[1] = __raw_readl(S5P_VA_L2CC + 0x10C); + l2x0_save[2] = __raw_readl(S5P_VA_L2CC + 0xF60); + + flush_cache_all(); + outer_clean_range(virt_to_phys(l2x0_save), ARRAY_SIZE(l2x0_save)); + outer_clean_range(virt_to_phys(scu_save), ARRAY_SIZE(scu_save)); +} +#endif + static int __init exynos4_init_cpuidle(void) { int i, max_cpuidle_state, cpu_id, ret; diff --git a/arch/arm/mach-exynos/cpuidle-exynos5.c b/arch/arm/mach-exynos/cpuidle-exynos5.c deleted file mode 100644 index fbe063d..0000000 --- a/arch/arm/mach-exynos/cpuidle-exynos5.c +++ /dev/null @@ -1,674 +0,0 @@ -/* linux/arch/arm/mach-exynos/cpuidle-exynos5.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/cpuidle.h> -#include <linux/io.h> -#include <linux/suspend.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> - -#include <asm/proc-fns.h> -#include <asm/tlbflush.h> -#include <asm/cacheflush.h> - -#include <plat/pm.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-core.h> -#include <plat/regs-otg.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -#include <mach/regs-pmu5.h> -#include <mach/pm-core.h> -#include <mach/pmu.h> -#include <mach/regs-clock.h> -#include <mach/smc.h> -#include <mach/clock-domain.h> -#include <mach/regs-usb-phy.h> - -#ifdef CONFIG_ARM_TRUSTZONE -#define REG_DIRECTGO_ADDR (S5P_VA_SYSRAM_NS + 0x24) -#define REG_DIRECTGO_FLAG (S5P_VA_SYSRAM_NS + 0x20) -#else -#define REG_DIRECTGO_ADDR (S5P_VA_SYSRAM + 0x24) -#define REG_DIRECTGO_FLAG (S5P_VA_SYSRAM + 0x20) -#endif - -extern unsigned long sys_pwr_conf_addr; - -static int exynos5_enter_idle(struct cpuidle_device *dev, - struct cpuidle_state *state); - -static int __maybe_unused exynos5_enter_lowpower(struct cpuidle_device *dev, - struct cpuidle_state *state); - -struct check_reg_lpa { - void __iomem *check_reg; - unsigned int check_bit; -}; - -/* - * List of check power domain list for LPA mode - * These register are have to power off to enter LPA mode - */ -static struct check_reg_lpa exynos5_power_domain[] = { - {.check_reg = EXYNOS5_GSCL_STATUS, .check_bit = 0x7}, - {.check_reg = EXYNOS5_G3D_STATUS, .check_bit = 0x7}, -}; - -/* - * List of check clock gating list for LPA mode - * If clock of list is not gated, system can not enter LPA mode. - */ -static struct check_reg_lpa exynos5_clock_gating[] = { - {.check_reg = EXYNOS5_CLKSRC_MASK_DISP1_0, .check_bit = 0x00000001}, - {.check_reg = EXYNOS5_CLKGATE_IP_DISP1, .check_bit = 0x00000010}, - {.check_reg = EXYNOS5_CLKGATE_IP_MFC, .check_bit = 0x00000001}, - {.check_reg = EXYNOS5_CLKGATE_IP_GEN, .check_bit = 0x00004016}, - {.check_reg = EXYNOS5_CLKGATE_IP_FSYS, .check_bit = 0x00000002}, - {.check_reg = EXYNOS5_CLKGATE_IP_PERIC, .check_bit = 0x00377FC0}, -}; - -enum hc_type { - HC_SDHC, - HC_MSHC, -}; - -struct check_device_op { - void __iomem *base; - struct platform_device *pdev; - enum hc_type type; -}; - -static struct check_device_op chk_sdhc_op[] = { -#if defined(CONFIG_EXYNOS4_DEV_DWMCI) - {.base = 0, .pdev = &exynos_device_dwmci, .type = HC_MSHC}, -#endif -#if defined(CONFIG_S3C_DEV_HSMMC) - {.base = 0, .pdev = &s3c_device_hsmmc0, .type = HC_SDHC}, -#endif -#if defined(CONFIG_S3C_DEV_HSMMC1) - {.base = 0, .pdev = &s3c_device_hsmmc1, .type = HC_SDHC}, -#endif -#if defined(CONFIG_S3C_DEV_HSMMC2) - {.base = 0, .pdev = &s3c_device_hsmmc2, .type = HC_SDHC}, -#endif -#if defined(CONFIG_S3C_DEV_HSMMC3) - {.base = 0, .pdev = &s3c_device_hsmmc3, .type = HC_SDHC}, -#endif -}; - -static struct check_device_op chk_sdhc_op_exynos5250_rev1[] = { -#if defined(CONFIG_EXYNOS4_DEV_DWMCI) - {.base = 0, .pdev = &exynos_device_dwmci0, .type = HC_MSHC}, - {.base = 0, .pdev = &exynos_device_dwmci1, .type = HC_MSHC}, - {.base = 0, .pdev = &exynos_device_dwmci2, .type = HC_MSHC}, - {.base = 0, .pdev = &exynos_device_dwmci3, .type = HC_MSHC}, -#endif -}; - -#define S3C_HSMMC_PRNSTS (0x24) -#define S3C_HSMMC_CLKCON (0x2c) -#define S3C_HSMMC_CMD_INHIBIT 0x00000001 -#define S3C_HSMMC_DATA_INHIBIT 0x00000002 -#define S3C_HSMMC_CLOCK_CARD_EN 0x0004 - -#define MSHCI_CLKENA (0x10) /* Clock enable */ -#define MSHCI_STATUS (0x48) /* Status */ -#define MSHCI_DATA_BUSY (0x1<<9) -#define MSHCI_DATA_STAT_BUSY (0x1<<10) -#define MSHCI_ENCLK (0x1) - -static int sdmmc_dev_num; -/* If SD/MMC interface is working: return = 1 or not 0 */ -static int check_sdmmc_op(unsigned int ch) -{ - unsigned int reg1, reg2; - void __iomem *base_addr; - - if (unlikely(ch >= sdmmc_dev_num)) { - printk(KERN_ERR "Invalid ch[%d] for SD/MMC\n", ch); - return 0; - } - - if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) { - if (chk_sdhc_op_exynos5250_rev1[ch].type == HC_MSHC) { - base_addr = chk_sdhc_op_exynos5250_rev1[ch].base; - /* Check STATUS [9] for data busy */ - reg1 = readl(base_addr + MSHCI_STATUS); - return (reg1 & (MSHCI_DATA_BUSY)) || - (reg1 & (MSHCI_DATA_STAT_BUSY)); - } - } else { - if (chk_sdhc_op[ch].type == HC_SDHC) { - base_addr = chk_sdhc_op[ch].base; - /* Check CLKCON [2]: ENSDCLK */ - reg2 = readl(base_addr + S3C_HSMMC_CLKCON); - return !!(reg2 & (S3C_HSMMC_CLOCK_CARD_EN)); - } else if (chk_sdhc_op[ch].type == HC_MSHC) { - base_addr = chk_sdhc_op[ch].base; - /* Check STATUS [9] for data busy */ - reg1 = readl(base_addr + MSHCI_STATUS); - return (reg1 & (MSHCI_DATA_BUSY)) || - (reg1 & (MSHCI_DATA_STAT_BUSY)); - } - } - /* should not be here */ - return 0; -} - -/* Check all sdmmc controller */ -static int loop_sdmmc_check(void) -{ - unsigned int iter; - - for (iter = 0; iter < sdmmc_dev_num; iter++) { - if (check_sdmmc_op(iter)) { - printk(KERN_DEBUG "SDMMC [%d] working\n", iter); - return 1; - } - } - return 0; -} - -static int exynos5_check_reg_status(struct check_reg_lpa *reg_list, - unsigned int list_cnt) -{ - unsigned int i; - unsigned int tmp; - - for (i = 0; i < list_cnt; i++) { - tmp = __raw_readl(reg_list[i].check_reg); - if (tmp & reg_list[i].check_bit) - return -EBUSY; - } - - return 0; -} - -static int exynos5_uart_fifo_check(void) -{ - unsigned int ret; - unsigned int check_val; - - ret = 0; - - /* Check UART for console is empty */ - check_val = __raw_readl(S5P_VA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT) + - 0x18); - - ret = ((check_val >> 16) & 0xff); - - return ret; -} - -static struct cpuidle_state exynos5_cpuidle_set[] = { - [0] = { - .enter = exynos5_enter_idle, - .exit_latency = 1, - .target_residency = 10000, - .flags = CPUIDLE_FLAG_TIME_VALID, - .name = "IDLE", - .desc = "ARM clock gating(WFI)", - }, -#ifdef CONFIG_EXYNOS5_LOWPWR_IDLE - [1] = { - .enter = exynos5_enter_lowpower, - .exit_latency = 300, - .target_residency = 10000, - .flags = CPUIDLE_FLAG_TIME_VALID, - .name = "LOW_POWER", - .desc = "ARM power down", - }, -#endif -}; - -static DEFINE_PER_CPU(struct cpuidle_device, exynos5_cpuidle_device); - -static struct cpuidle_driver exynos5_idle_driver = { - .name = "exynos5_idle", - .owner = THIS_MODULE, -}; - -/* - * To keep value of gpio on power down mode - * set Power down register of gpio - */ -static void exynos5_gpio_set_pd_reg(void) -{ - struct s3c_gpio_chip *target_chip; - unsigned int gpio_nr; - unsigned int tmp; - - for (gpio_nr = 0; gpio_nr < EXYNOS5_GPIO_END; gpio_nr++) { - target_chip = s3c_gpiolib_getchip(gpio_nr); - - if (!target_chip) - continue; - - if (!target_chip->pm) - continue; - - /* Keep the previous state in LPA mode */ - s5p_gpio_set_pd_cfg(gpio_nr, 0x3); - - /* Pull up-down state in LPA mode is same as normal */ - tmp = s3c_gpio_getpull(gpio_nr); - s5p_gpio_set_pd_pull(gpio_nr, tmp); - } -} - -static int exynos5_enter_idle(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - struct timeval before, after; - int idle_time; - - local_irq_disable(); - do_gettimeofday(&before); - - cpu_do_idle(); - - do_gettimeofday(&after); - local_irq_enable(); - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - - return idle_time; -} - -static void exynos5_set_wakeupmask(void) -{ - __raw_writel(0x0000ff3e, EXYNOS5_WAKEUP_MASK); -} - -static inline void vfp_enable(void *unused) -{ - u32 access = get_copro_access(); - - /* - * Enable full access to VFP (cp10 and cp11) - */ - set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); -} - -static struct sleep_save exynos5_lpa_save[] = { - /* CMU side */ - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0), - SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1), - SAVE_ITEM(EXYNOS5_CLKSRC_TOP3), -}; - -static struct sleep_save exynos5_set_clksrc[] = { - { .reg = EXYNOS5_CLKSRC_MASK_TOP , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_GSCL , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_DISP1_0 , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_MAUDIO , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_FSYS , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_PERIC0 , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_PERIC1 , .val = 0xffffffff, }, -}; - -static int exynos5_enter_core0_lpa(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - struct timeval before, after; - int idle_time; - - unsigned long tmp; - - s3c_pm_do_save(exynos5_lpa_save, ARRAY_SIZE(exynos5_lpa_save)); - /* - * Before enter central sequence mode, clock src register have to set - */ - s3c_pm_do_restore_core(exynos5_set_clksrc, - ARRAY_SIZE(exynos5_set_clksrc)); - - local_irq_disable(); - - do_gettimeofday(&before); - - /* - * Unmasking all wakeup source. - */ - __raw_writel(0x0, S5P_WAKEUP_MASK); - - /* Configure GPIO Power down control register */ - exynos5_gpio_set_pd_reg(); - - /* ensure at least INFORM0 has the resume address */ - __raw_writel(virt_to_phys(exynos5_idle_resume), REG_DIRECTGO_ADDR); - __raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG); - - __raw_writel(S5P_CHECK_LPA, EXYNOS5_INFORM1); - - exynos5_sys_powerdown_conf(SYS_LPA); - - /* Disable USE_RETENTION of JPEG_MEM_OPTION */ - tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); - tmp |= EXYNOS5_OPTION_USE_RETENTION; - __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); - - do { - /* Waiting for flushing UART fifo */ - } while (exynos5_uart_fifo_check()); - - /* - * GPS can not turn off. - */ - if (samsung_rev() < EXYNOS5250_REV_1_0) - __raw_writel(0x10000, EXYNOS5_GPS_LPI); - - if (exynos5_enter_lp(0, PLAT_PHYS_OFFSET - PAGE_OFFSET) == 0) { - /* - * Clear Central Sequence Register in exiting early wakeup - */ - tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - tmp |= (EXYNOS5_CENTRAL_LOWPWR_CFG); - __raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - - goto early_wakeup; - } - - flush_tlb_all(); - - cpu_init(); - - vfp_enable(NULL); - - /* For release retention */ - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MAU_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_UART_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCA_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCB_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIA_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIB_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_SPI_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_OPTION); - -early_wakeup: - s3c_pm_do_restore_core(exynos5_lpa_save, - ARRAY_SIZE(exynos5_lpa_save)); - - /* Clear wakeup state register */ - __raw_writel(0x0, EXYNOS5_WAKEUP_STAT); - - __raw_writel(0x0, EXYNOS5_WAKEUP_MASK); - - do_gettimeofday(&after); - - local_irq_enable(); - - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - - return idle_time; -} - -static int exynos5_enter_core0_aftr(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - struct timeval before, after; - int idle_time; - unsigned long tmp; - - local_irq_disable(); - do_gettimeofday(&before); - - exynos5_set_wakeupmask(); - - __raw_writel(virt_to_phys(exynos5_idle_resume), REG_DIRECTGO_ADDR); - __raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG); - - /* Set value of power down register for aftr mode */ - exynos5_sys_powerdown_conf(SYS_AFTR); - - if (exynos5_enter_lp(0, PLAT_PHYS_OFFSET - PAGE_OFFSET) == 0) { - /* - * Clear Central Sequence Register in exiting early wakeup - */ - tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - tmp |= EXYNOS5_CENTRAL_LOWPWR_CFG; - __raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - - goto early_wakeup; - } - - flush_tlb_all(); - - cpu_init(); - - vfp_enable(NULL); - -early_wakeup: - /* Clear wakeup state register */ - __raw_writel(0x0, EXYNOS5_WAKEUP_STAT); - - do_gettimeofday(&after); - - local_irq_enable(); - idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + - (after.tv_usec - before.tv_usec); - - return idle_time; -} - -static int __maybe_unused exynos5_check_enter_mode(void) -{ - /* Check power domain */ - if (exynos5_check_reg_status(exynos5_power_domain, - ARRAY_SIZE(exynos5_power_domain))) - return S5P_CHECK_DIDLE; - - /* Check clock gating */ - if (exynos5_check_reg_status(exynos5_clock_gating, - ARRAY_SIZE(exynos5_clock_gating))) - return S5P_CHECK_DIDLE; - - if (clock_domain_enabled(LPA_DOMAIN)) - return S5P_CHECK_DIDLE; - - if (loop_sdmmc_check()) - return S5P_CHECK_DIDLE; - - if (exynos_check_usb_op()) - return S5P_CHECK_DIDLE; - - return S5P_CHECK_LPA; -} - -static int __maybe_unused exynos5_enter_lowpower(struct cpuidle_device *dev, - struct cpuidle_state *state) -{ - struct cpuidle_state *new_state = state; - unsigned int tmp; - - /* This mode only can be entered when only Core0 is online */ - if (num_online_cpus() != 1) { - BUG_ON(!dev->safe_state); - new_state = dev->safe_state; - } - dev->last_state = new_state; - - if (new_state == &dev->states[0]) - return exynos5_enter_idle(dev, new_state); - - tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_OPTION); - tmp = (EXYNOS5_USE_STANDBYWFI_ARM_CORE0 | - EXYNOS5_USE_STANDBYWFE_ARM_CORE0); - __raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_OPTION); - - if (exynos5_check_enter_mode() == S5P_CHECK_DIDLE) - return exynos5_enter_core0_aftr(dev, new_state); - else - return exynos5_enter_core0_aftr(dev, new_state); - //return exynos5_enter_core0_lpa(dev, new_state); -} - -static int exynos5_cpuidle_notifier_event(struct notifier_block *this, - unsigned long event, - void *ptr) -{ - switch (event) { - case PM_SUSPEND_PREPARE: - disable_hlt(); - pr_debug("PM_SUSPEND_PREPARE for CPUIDLE\n"); - return NOTIFY_OK; - case PM_POST_RESTORE: - case PM_POST_SUSPEND: - enable_hlt(); - pr_debug("PM_POST_SUSPEND for CPUIDLE\n"); - return NOTIFY_OK; - } - return NOTIFY_DONE; -} - -static struct notifier_block exynos5_cpuidle_notifier = { - .notifier_call = exynos5_cpuidle_notifier_event, -}; - -#ifdef CONFIG_EXYNOS5_ENABLE_CLOCK_DOWN -static void __init exynos5_core_down_clk(void) -{ - unsigned int tmp; - - tmp = __raw_readl(EXYNOS5_PWR_CTRL1); - - tmp &= ~(PWR_CTRL1_CORE2_DOWN_MASK | PWR_CTRL1_CORE1_DOWN_MASK); - - /* set arm clock divider value on idle state */ - tmp |= ((0x7 << PWR_CTRL1_CORE2_DOWN_RATIO) | - (0x7 << PWR_CTRL1_CORE1_DOWN_RATIO)); - - tmp |= (PWR_CTRL1_DIV2_DOWN_EN | - PWR_CTRL1_DIV1_DOWN_EN | - PWR_CTRL1_USE_CORE1_WFE | - PWR_CTRL1_USE_CORE0_WFE | - PWR_CTRL1_USE_CORE1_WFI | - PWR_CTRL1_USE_CORE0_WFI); - - __raw_writel(tmp, EXYNOS5_PWR_CTRL1); - - tmp = __raw_readl(EXYNOS5_PWR_CTRL2); - - tmp &= ~(PWR_CTRL2_DUR_STANDBY2_MASK | PWR_CTRL2_DUR_STANDBY1_MASK | - PWR_CTRL2_CORE2_UP_MASK | PWR_CTRL2_CORE1_UP_MASK); - - /* set duration value on middle wakeup step */ - tmp |= ((0x1 << PWR_CTRL2_DUR_STANDBY2) | - (0x1 << PWR_CTRL2_DUR_STANDBY1)); - - /* set arm clock divier value on middle wakeup step */ - tmp |= ((0x1 << PWR_CTRL2_CORE2_UP_RATIO) | - (0x1 << PWR_CTRL2_CORE1_UP_RATIO)); - - /* Set PWR_CTRL2 register to use step up for arm clock */ - tmp |= (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN); - - __raw_writel(tmp, EXYNOS5_PWR_CTRL2); - printk(KERN_INFO "Exynos5 : ARM Clock down on idle mode is enabled\n"); -} -#else -#define exynos5_core_down_clk() do { } while (0) -#endif - -static int __init exynos5_init_cpuidle(void) -{ - int i, max_cpuidle_state, cpu_id, ret; - struct cpuidle_device *device; - struct platform_device *pdev; - struct resource *res; - void __iomem *base; - - if (samsung_rev() >= EXYNOS5250_REV_1_0) - exynos4_reset_assert_ctrl(1); - - exynos5_core_down_clk(); - - ret = cpuidle_register_driver(&exynos5_idle_driver); - - if(ret < 0){ - printk(KERN_ERR "exynos5 idle register driver failed\n"); - return ret; - } - - - for_each_cpu(cpu_id, cpu_online_mask) { - device = &per_cpu(exynos5_cpuidle_device, cpu_id); - device->cpu = cpu_id; - - if (cpu_id == 0) - device->state_count = ARRAY_SIZE(exynos5_cpuidle_set); - else - device->state_count = 1; /* Support IDLE only */ - - max_cpuidle_state = device->state_count; - - for (i = 0; i < max_cpuidle_state; i++) { - memcpy(&device->states[i], &exynos5_cpuidle_set[i], - sizeof(struct cpuidle_state)); - } - - device->safe_state = &device->states[0]; - - if (cpuidle_register_device(device)) { - cpuidle_unregister_driver(&exynos5_idle_driver); - printk(KERN_ERR "CPUidle register device failed\n,"); - return -EIO; - } - } - - if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) - sdmmc_dev_num = ARRAY_SIZE(chk_sdhc_op_exynos5250_rev1); - else - sdmmc_dev_num = ARRAY_SIZE(chk_sdhc_op); - - for (i = 0; i < sdmmc_dev_num; i++) { - - if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) - pdev = chk_sdhc_op_exynos5250_rev1[i].pdev; - else - pdev = chk_sdhc_op[i].pdev; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - printk(KERN_ERR "failed to get iomem region\n"); - return -EINVAL; - } - - if (soc_is_exynos5250() && (samsung_rev() >= EXYNOS5250_REV_1_0)) { - chk_sdhc_op_exynos5250_rev1[i].base = ioremap(res->start, resource_size(res)); - base = chk_sdhc_op_exynos5250_rev1[i].base; - } else { - chk_sdhc_op[i].base = ioremap(res->start, resource_size(res)); - base = chk_sdhc_op[i].base; - } - - - if (!base) { - printk(KERN_ERR "failed to map io region\n"); - return -EINVAL; - } - } - - register_pm_notifier(&exynos5_cpuidle_notifier); - sys_pwr_conf_addr = (unsigned long)EXYNOS5_CENTRAL_SEQ_CONFIGURATION; - - return 0; -} -device_initcall(exynos5_init_cpuidle); diff --git a/arch/arm/mach-exynos/cyttsp4_img.h b/arch/arm/mach-exynos/cyttsp4_img.h new file mode 100644 index 0000000..18f91ce --- /dev/null +++ b/arch/arm/mach-exynos/cyttsp4_img.h @@ -0,0 +1,7113 @@ +static u8 cyttsp4_ver[] = {
+ 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x05, 0x82, 0x23
+};
+
+static u8 cyttsp4_img[] = {
+ 0x00, 0x00, 0x24, 0x00, 0x80, 0x00, 0x20, 0x00,
+ 0x20, 0x25, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00, 0xDD, 0x13, 0x00,
+ 0x00, 0xDD, 0x13, 0x00, 0x00,
+ 0x00, 0x00, 0x25, 0x00, 0x80, 0x00, 0xF0, 0x02,
+ 0xF8, 0x00, 0xF0, 0x40, 0xF8, 0x0C, 0xA0, 0x30,
+ 0xC8, 0x08, 0x38, 0x24, 0x18, 0x2D, 0x18, 0xA2,
+ 0x46, 0x67, 0x1E, 0xAB, 0x46, 0x54, 0x46, 0x5D,
+ 0x46, 0xAC, 0x42, 0x01, 0xD1, 0x00, 0xF0, 0x32,
+ 0xF8, 0x7E, 0x46, 0x0F, 0x3E, 0x0F, 0xCC, 0xB6,
+ 0x46, 0x01, 0x26, 0x33, 0x42, 0x00, 0xD0, 0xFB,
+ 0x1A, 0xA2, 0x46, 0xAB, 0x46, 0x33, 0x43, 0x18,
+ 0x47, 0x6C, 0xBD, 0x00, 0x00, 0x9C, 0xBD, 0x00,
+ 0x00, 0x10, 0x3A, 0x02, 0xD3, 0x78, 0xC8, 0x78,
+ 0xC1, 0xFA, 0xD8, 0x52, 0x07, 0x01, 0xD3, 0x30,
+ 0xC8, 0x30, 0xC1, 0x01, 0xD5, 0x04, 0x68, 0x0C,
+ 0x60, 0x70, 0x47, 0x00, 0x00, 0x00, 0x23, 0x00,
+ 0x24, 0x00, 0x25, 0x00, 0x26, 0x10, 0x3A, 0x01,
+ 0xD3, 0x78, 0xC1, 0xFB, 0xD8, 0x52, 0x07, 0x00,
+ 0xD3, 0x30, 0xC1, 0x00, 0xD5, 0x0B, 0x60, 0x70,
+ 0x47, 0x1F, 0xB5, 0xC0, 0x46,
+ 0x00, 0x00, 0x26, 0x00, 0x80, 0xC0, 0x46, 0x1F,
+ 0xBD, 0x10, 0xB5, 0x10, 0xBD, 0x03, 0x48, 0x85,
+ 0x46, 0xFF, 0xF7, 0xF6, 0xFF, 0x00, 0xF0, 0x7D,
+ 0xF8, 0x0B, 0xF0, 0x22, 0xFC, 0x00, 0x20, 0x00,
+ 0x20, 0xFF, 0xF7, 0xF2, 0xFF, 0x0B, 0xF0, 0x22,
+ 0xFC, 0x01, 0x4B, 0x9D, 0x46, 0x01, 0x48, 0x00,
+ 0x47, 0x00, 0x20, 0x00, 0x20, 0x81, 0x12, 0x00,
+ 0x00, 0x70, 0xB5, 0x05, 0x46, 0x0C, 0x46, 0x16,
+ 0x46, 0x02, 0xE0, 0x0F, 0xCC, 0x0F, 0xC5, 0x10,
+ 0x3E, 0x10, 0x2E, 0xFA, 0xD2, 0x08, 0x2E, 0x02,
+ 0xD3, 0x03, 0xCC, 0x03, 0xC5, 0x08, 0x3E, 0x04,
+ 0x2E, 0x07, 0xD3, 0x01, 0xCC, 0x01, 0xC5, 0x36,
+ 0x1F, 0x03, 0xE0, 0x21, 0x78, 0x29, 0x70, 0x64,
+ 0x1C, 0x6D, 0x1C, 0x76, 0x1E, 0xF9, 0xD2, 0x70,
+ 0xBD, 0x10, 0xB5, 0x19, 0x4C, 0x19, 0x4B, 0x00,
+ 0x20, 0x21, 0x5C, 0x00, 0x29, 0x0F, 0xD0, 0x4A,
+ 0x07, 0x52, 0x0F, 0x52, 0x1C,
+ 0x00, 0x00, 0x27, 0x00, 0x80, 0x09, 0x06, 0xC9,
+ 0x0E, 0x05, 0xD1, 0x07, 0x2A, 0x03, 0xD9, 0x20,
+ 0x18, 0x00, 0x7A, 0xD8, 0x61, 0x03, 0xE0, 0x80,
+ 0x18, 0x40, 0x1C, 0x80, 0x28, 0xEC, 0xD3, 0x0E,
+ 0x49, 0x0E, 0x4A, 0x00, 0x20, 0x80, 0x31, 0x20,
+ 0x32, 0x84, 0x00, 0x0C, 0x59, 0x94, 0x42, 0x04,
+ 0xD1, 0x80, 0x00, 0x40, 0x18, 0x40, 0x68, 0x18,
+ 0x62, 0x02, 0xE0, 0x80, 0x1C, 0x10, 0x28, 0xF3,
+ 0xD3, 0x03, 0x20, 0x01, 0x21, 0x00, 0x04, 0x89,
+ 0x07, 0x48, 0x61, 0x00, 0xF0, 0xA3, 0xFA, 0x00,
+ 0xF0, 0xC7, 0xF8, 0x00, 0xF0, 0x62, 0xF9, 0xFE,
+ 0xE7, 0x80, 0xF0, 0xFF, 0x0F, 0x00, 0xFF, 0x00,
+ 0x40, 0xFE, 0xE7, 0x70, 0xB5, 0x0D, 0x4A, 0x0E,
+ 0x4B, 0x00, 0x20, 0x81, 0x00, 0x54, 0x58, 0x40,
+ 0x1C, 0x5C, 0x50, 0x20, 0x28, 0xF9, 0xD3, 0x0B,
+ 0x49, 0x01, 0x20, 0x08, 0x60, 0x0A, 0x49, 0x80,
+ 0x04, 0x08, 0x60, 0x0A, 0x4C,
+ 0x00, 0x00, 0x28, 0x00, 0x80, 0xE5, 0x69, 0x26,
+ 0x6A, 0x02, 0xF0, 0x70, 0xF8, 0xE5, 0x61, 0x26,
+ 0x62, 0x70, 0xBD, 0xFF, 0xF7, 0xE6, 0xFF, 0xFF,
+ 0xF7, 0xAB, 0xFF, 0xFE, 0xE7, 0x00, 0x12, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10,
+ 0x40, 0x00, 0x00, 0x01, 0x40, 0x00, 0xFF, 0x00,
+ 0x40, 0xF0, 0xB5, 0x2A, 0x4D, 0x84, 0x46, 0x00,
+ 0x24, 0xAF, 0x88, 0x9E, 0x46, 0x20, 0x46, 0x28,
+ 0x4E, 0x8F, 0x42, 0x04, 0xD8, 0xF7, 0x68, 0xEB,
+ 0x88, 0xFF, 0x1A, 0x8F, 0x42, 0x08, 0xD2, 0x29,
+ 0x8A, 0x91, 0x42, 0x16, 0xD2, 0x31, 0x69, 0x6B,
+ 0x8A, 0xC9, 0x1A, 0x91, 0x42, 0x11, 0xD9, 0x0F,
+ 0xE0, 0x2F, 0x89, 0x8F, 0x42, 0x0D, 0xD2, 0xF7,
+ 0x68, 0x6B, 0x89, 0xFF, 0x1A, 0x8F, 0x42, 0x08,
+ 0xD9, 0xA9, 0x89, 0x91, 0x42, 0x04, 0xD8, 0x31,
+ 0x69, 0xEB, 0x89, 0xC9, 0x1A, 0x91, 0x42, 0x00,
+ 0xD2, 0x01, 0x24, 0x18, 0x4A,
+ 0x00, 0x00, 0x29, 0x00, 0x80, 0x01, 0x27, 0x61,
+ 0x46, 0x73, 0x46, 0x16, 0x88, 0x8F, 0x40, 0x01,
+ 0x2B, 0x05, 0xD1, 0x01, 0x2C, 0x0A, 0xD1, 0x39,
+ 0x46, 0x31, 0x43, 0x11, 0x80, 0x06, 0xE0, 0x00,
+ 0x2C, 0x04, 0xD1, 0x69, 0x7D, 0x00, 0x29, 0x01,
+ 0xD1, 0xBE, 0x43, 0x16, 0x80, 0x61, 0x46, 0x00,
+ 0x29, 0x02, 0xD1, 0x29, 0x7D, 0x01, 0x29, 0x0E,
+ 0xD0, 0x01, 0x2C, 0x03, 0xD1, 0x11, 0x88, 0x0F,
+ 0x42, 0x09, 0xD0, 0x07, 0xE0, 0x00, 0x2C, 0x06,
+ 0xD1, 0x11, 0x88, 0x0F, 0x42, 0x03, 0xD0, 0x69,
+ 0x7D, 0x01, 0x29, 0x00, 0xD1, 0x01, 0x20, 0x00,
+ 0x21, 0x51, 0x80, 0xF0, 0xBD, 0x60, 0xDC, 0x00,
+ 0x00, 0x90, 0xDD, 0x00, 0x00, 0x84, 0x00, 0x00,
+ 0x20, 0x01, 0x46, 0x00, 0x20, 0xC9, 0x1E, 0x04,
+ 0x29, 0x00, 0xD8, 0x02, 0x20, 0x70, 0x47, 0x00,
+ 0xB5, 0x0A, 0x46, 0x00, 0x23, 0xFF, 0xF7, 0xF4,
+ 0xFF, 0x00, 0x28, 0x05, 0xD0,
+ 0x00, 0x00, 0x2A, 0x00, 0x80, 0x82, 0x42, 0x03,
+ 0xD2, 0x0B, 0x49, 0x90, 0x00, 0x43, 0x18, 0x9B,
+ 0x1C, 0x18, 0x46, 0x00, 0xBD, 0x01, 0x46, 0x00,
+ 0x20, 0x89, 0x1E, 0x05, 0x29, 0x00, 0xD8, 0x06,
+ 0x48, 0x70, 0x47, 0x05, 0x49, 0x08, 0x79, 0x09,
+ 0x7A, 0x00, 0x07, 0x00, 0x0F, 0x09, 0x07, 0x09,
+ 0x0F, 0x88, 0x42, 0x00, 0xD2, 0x08, 0x46, 0x70,
+ 0x47, 0xF0, 0xDC, 0x00, 0x00, 0x06, 0x48, 0x00,
+ 0x79, 0x06, 0x49, 0xC0, 0x07, 0xC0, 0x0F, 0x08,
+ 0x70, 0x70, 0x47, 0x04, 0x49, 0x00, 0x20, 0x08,
+ 0x70, 0x70, 0x47, 0x02, 0x48, 0x00, 0x78, 0x70,
+ 0x47, 0x40, 0xDE, 0x00, 0x00, 0x88, 0x00, 0x00,
+ 0x20, 0xFE, 0xB5, 0x04, 0xF0, 0xA5, 0xFB, 0x04,
+ 0xF0, 0xD1, 0xFB, 0xD0, 0x48, 0x04, 0xF0, 0xFE,
+ 0xFA, 0x01, 0x20, 0x04, 0xF0, 0xEE, 0xFA, 0x04,
+ 0xF0, 0x55, 0xFB, 0xC0, 0x21, 0xCC, 0x48, 0x0A,
+ 0x79, 0x02, 0x70, 0x49, 0x79,
+ 0x00, 0x00, 0x2B, 0x00, 0x80, 0x41, 0x70, 0xCB,
+ 0x48, 0x80, 0x7A, 0xCB, 0x4C, 0xCB, 0x4D, 0x00,
+ 0x28, 0x3C, 0xD0, 0xA6, 0x68, 0x07, 0x21, 0xC9,
+ 0x03, 0x30, 0x46, 0x88, 0x43, 0xC8, 0x49, 0x08,
+ 0x43, 0xA0, 0x60, 0xA7, 0x69, 0x20, 0x21, 0x38,
+ 0x46, 0x88, 0x43, 0xA0, 0x61, 0x60, 0x69, 0x0F,
+ 0x22, 0x12, 0x05, 0x00, 0x90, 0x90, 0x43, 0x60,
+ 0x61, 0x20, 0x68, 0x01, 0x90, 0x88, 0x43, 0x2C,
+ 0x21, 0x08, 0x43, 0x20, 0x60, 0x28, 0x68, 0x02,
+ 0x90, 0x80, 0x08, 0x80, 0x00, 0x01, 0x21, 0x08,
+ 0x43, 0x28, 0x60, 0x7D, 0x20, 0xC0, 0x00, 0x04,
+ 0xF0, 0xDB, 0xFB, 0x60, 0x68, 0x81, 0x06, 0xCA,
+ 0x0F, 0xB3, 0x49, 0x89, 0x1E, 0x0A, 0x70, 0x02,
+ 0x07, 0xD2, 0x0F, 0x52, 0x00, 0x0B, 0x78, 0x40,
+ 0x07, 0x1A, 0x43, 0xC0, 0x0F, 0x80, 0x00, 0xD2,
+ 0xB2, 0x10, 0x43, 0x08, 0x70, 0xA6, 0x60, 0xA7,
+ 0x61, 0x00, 0x98, 0x60, 0x61,
+ 0x00, 0x00, 0x2C, 0x00, 0x80, 0x01, 0x98, 0x20,
+ 0x60, 0x02, 0x98, 0x28, 0x60, 0xA8, 0x48, 0x08,
+ 0xF0, 0x52, 0xF8, 0x08, 0xF0, 0x34, 0xF8, 0xC0,
+ 0x26, 0xB0, 0x79, 0xC1, 0x07, 0x05, 0xD1, 0x80,
+ 0x07, 0x01, 0xD4, 0x04, 0x20, 0x07, 0xE0, 0x02,
+ 0x20, 0x05, 0xE0, 0x01, 0x21, 0x80, 0x07, 0x01,
+ 0xD4, 0x05, 0x20, 0x00, 0xE0, 0x03, 0x20, 0x08,
+ 0xF0, 0x56, 0xF8, 0x07, 0xF0, 0xBF, 0xFF, 0x28,
+ 0x68, 0xB0, 0x43, 0x28, 0x60, 0x9B, 0x48, 0x40,
+ 0x30, 0x40, 0x7D, 0x07, 0x21, 0x49, 0x02, 0x01,
+ 0x28, 0x0D, 0xD0, 0x02, 0x28, 0x0A, 0xD1, 0x28,
+ 0x68, 0x80, 0x22, 0x10, 0x43, 0x28, 0x60, 0x99,
+ 0x4A, 0x90, 0x68, 0x88, 0x43, 0xFF, 0x30, 0xFF,
+ 0x30, 0x02, 0x30, 0x90, 0x60, 0xFE, 0xBD, 0x28,
+ 0x68, 0x30, 0x43, 0x28, 0x60, 0xA0, 0x68, 0x88,
+ 0x43, 0xFF, 0x30, 0xFF, 0x30, 0x02, 0x30, 0xA0,
+ 0x60, 0xFE, 0xBD, 0x10, 0xB5,
+ 0x00, 0x00, 0x2D, 0x00, 0x80, 0x04, 0xF0, 0xF4,
+ 0xFB, 0x8F, 0x4C, 0x20, 0x70, 0xC0, 0xB2, 0x04,
+ 0xF0, 0xFC, 0xFB, 0x20, 0x78, 0x04, 0xF0, 0x21,
+ 0xFC, 0x10, 0xBD, 0xF8, 0xB5, 0x04, 0xF0, 0xC2,
+ 0xFA, 0x8A, 0x48, 0x00, 0x24, 0x04, 0x80, 0x04,
+ 0xF0, 0x23, 0xF9, 0x89, 0x49, 0x01, 0x25, 0x08,
+ 0x80, 0xAD, 0x07, 0xAC, 0x60, 0x01, 0x26, 0xAE,
+ 0x61, 0x08, 0x88, 0x86, 0x4F, 0x80, 0x07, 0x7E,
+ 0xD5, 0xFF, 0xF7, 0xDF, 0xFF, 0x7B, 0x49, 0x88,
+ 0x7E, 0xC0, 0x07, 0x28, 0x68, 0x02, 0xD1, 0x38,
+ 0x43, 0x28, 0x60, 0x06, 0xE0, 0xB8, 0x43, 0x28,
+ 0x60, 0x88, 0x7E, 0x00, 0x09, 0x40, 0x00, 0x30,
+ 0x43, 0xA8, 0x61, 0x7D, 0x48, 0x00, 0x68, 0x00,
+ 0x28, 0x13, 0xD0, 0x01, 0x20, 0x04, 0xF0, 0x50,
+ 0xFB, 0x02, 0x27, 0x6F, 0x60, 0x04, 0x20, 0x01,
+ 0xF0, 0x96, 0xFF, 0xAF, 0x60, 0x77, 0x49, 0x04,
+ 0x20, 0x01, 0xF0, 0x68, 0xFF,
+ 0x00, 0x00, 0x2E, 0x00, 0x80, 0x00, 0x21, 0x04,
+ 0x20, 0x01, 0xF0, 0x6E, 0xFF, 0x04, 0x20, 0x01,
+ 0xF0, 0x7B, 0xFF, 0x73, 0x4D, 0x6E, 0x4A, 0x2E,
+ 0x70, 0x10, 0x88, 0x08, 0x21, 0x08, 0x43, 0x10,
+ 0x80, 0x80, 0xB2, 0x83, 0x07, 0x02, 0xD4, 0x2C,
+ 0x70, 0x88, 0x43, 0x10, 0x80, 0x10, 0x88, 0x83,
+ 0x05, 0x02, 0xD4, 0x2C, 0x70, 0x88, 0x43, 0x10,
+ 0x80, 0x10, 0x88, 0x43, 0x07, 0x9B, 0x0F, 0x03,
+ 0x2B, 0x07, 0xD0, 0x5C, 0x4B, 0x20, 0x33, 0x9B,
+ 0x7C, 0xDB, 0x07, 0x02, 0xD0, 0x2C, 0x70, 0x88,
+ 0x43, 0x10, 0x80, 0x57, 0x4F, 0x00, 0x20, 0xBF,
+ 0x1E, 0x62, 0x49, 0x78, 0x70, 0x55, 0x4C, 0x08,
+ 0x70, 0xA0, 0x7C, 0x61, 0x4E, 0x00, 0x09, 0x00,
+ 0x01, 0x30, 0x70, 0xE0, 0x7C, 0x5F, 0x49, 0x08,
+ 0x70, 0x20, 0x7D, 0x5F, 0x49, 0x08, 0x70, 0x60,
+ 0x7E, 0x21, 0x7E, 0x00, 0x02, 0x08, 0x43, 0x5D,
+ 0x49, 0x08, 0x80, 0xE0, 0x7D,
+ 0x00, 0x00, 0x2F, 0x00, 0x80, 0xA1, 0x7D, 0x00,
+ 0x02, 0x08, 0x43, 0x5B, 0x49, 0x08, 0x80, 0x60,
+ 0x7C, 0x5A, 0x49, 0x08, 0x70, 0x20, 0x46, 0x40,
+ 0x30, 0x00, 0x7D, 0x59, 0x49, 0x08, 0x70, 0x03,
+ 0xF0, 0xA8, 0xFB, 0x28, 0x78, 0x00, 0x28, 0x06,
+ 0xD0, 0x06, 0xF0, 0xBE, 0xFD, 0x08, 0xF0, 0x9C,
+ 0xF8, 0x01, 0x20, 0x07, 0xF0, 0x96, 0xFE, 0x53,
+ 0x49, 0x30, 0x78, 0x08, 0x70, 0x00, 0xE0, 0x1C,
+ 0xE0, 0x01, 0x20, 0x04, 0xF0, 0xDB, 0xF9, 0x20,
+ 0x7C, 0x04, 0x21, 0x08, 0x40, 0x4E, 0x4E, 0xC0,
+ 0xB2, 0x10, 0x24, 0x20, 0x43, 0x30, 0x70, 0x79,
+ 0x78, 0x01, 0x20, 0x07, 0xF0, 0xB2, 0xFF, 0x31,
+ 0x78, 0x00, 0x20, 0x07, 0xF0, 0xAE, 0xFF, 0x07,
+ 0xF0, 0x6A, 0xFF, 0x48, 0x4D, 0x2C, 0x70, 0x02,
+ 0xF0, 0xA3, 0xFE, 0x47, 0x49, 0x00, 0x20, 0x08,
+ 0x70, 0x41, 0xE0, 0x28, 0x68, 0xB8, 0x43, 0x67,
+ 0xE7, 0x04, 0xF0, 0x10, 0xFA,
+ 0x00, 0x00, 0x30, 0x00, 0x80, 0x28, 0x78, 0x00,
+ 0x28, 0x3E, 0xD0, 0x10, 0x28, 0x3F, 0xD0, 0x20,
+ 0x28, 0x01, 0xD1, 0x02, 0xF0, 0x39, 0xFC, 0x00,
+ 0x20, 0x07, 0xF0, 0x97, 0xFF, 0x30, 0x70, 0xC0,
+ 0xB2, 0xC0, 0x07, 0x01, 0xD0, 0x01, 0xF0, 0x06,
+ 0xFF, 0x30, 0x78, 0x01, 0x07, 0xE8, 0xD5, 0x30,
+ 0x21, 0x08, 0x40, 0x28, 0x70, 0x00, 0x2C, 0x2D,
+ 0xD0, 0x10, 0x2C, 0x2E, 0xD0, 0x20, 0x2C, 0x01,
+ 0xD1, 0x02, 0xF0, 0xF1, 0xFC, 0x01, 0x20, 0x04,
+ 0xF0, 0x99, 0xF9, 0x28, 0x78, 0x00, 0x28, 0x27,
+ 0xD0, 0x10, 0x28, 0x28, 0xD0, 0x20, 0x28, 0x01,
+ 0xD1, 0x01, 0xF0, 0x46, 0xFF, 0x79, 0x78, 0xEF,
+ 0x20, 0x01, 0x40, 0x01, 0x20, 0x07, 0xF0, 0x6D,
+ 0xFF, 0x30, 0x78, 0xC7, 0x21, 0x2C, 0x78, 0x08,
+ 0x40, 0xC0, 0xB2, 0x20, 0x43, 0x30, 0x70, 0xC1,
+ 0xB2, 0x00, 0x20, 0x07, 0xF0, 0x62, 0xFF, 0x03,
+ 0xF0, 0xAD, 0xFD, 0x03, 0xF0,
+ 0x00, 0x00, 0x31, 0x00, 0x80, 0xE3, 0xFD, 0xBB,
+ 0xE7, 0x03, 0xF0, 0x68, 0xFC, 0xC3, 0xE7, 0x02,
+ 0xF0, 0x27, 0xFF, 0xC0, 0xE7, 0x03, 0xF0, 0x09,
+ 0xFD, 0xD4, 0xE7, 0x02, 0xF0, 0x25, 0xFF, 0xD1,
+ 0xE7, 0x02, 0xF0, 0xBA, 0xFF, 0xDA, 0xE7, 0x02,
+ 0xF0, 0x47, 0xFE, 0xD7, 0xE7, 0x10, 0x27, 0x00,
+ 0x00, 0x8B, 0x00, 0x00, 0x20, 0x00, 0xDC, 0x00,
+ 0x00, 0x00, 0x00, 0x14, 0x40, 0x00, 0x20, 0x14,
+ 0x40, 0x80, 0x04, 0x01, 0x00, 0x00, 0x10, 0x14,
+ 0x40, 0x64, 0x01, 0x00, 0x20, 0x2C, 0x01, 0x00,
+ 0x20, 0x3C, 0x01, 0x00, 0x20, 0x00, 0x00, 0x80,
+ 0x00, 0x44, 0x01, 0x00, 0x20, 0x89, 0x36, 0x00,
+ 0x00, 0x2A, 0x01, 0x00, 0x20, 0xDC, 0x00, 0x00,
+ 0x20, 0xDD, 0x00, 0x00, 0x20, 0xD6, 0x00, 0x00,
+ 0x20, 0xD7, 0x00, 0x00, 0x20, 0xE2, 0x00, 0x00,
+ 0x20, 0xE4, 0x00, 0x00, 0x20, 0xD8, 0x00, 0x00,
+ 0x20, 0xD9, 0x00, 0x00, 0x20,
+ 0x00, 0x00, 0x32, 0x00, 0x80, 0x32, 0x02, 0x00,
+ 0x20, 0x40, 0x01, 0x00, 0x20, 0x2B, 0x01, 0x00,
+ 0x20, 0x3F, 0x01, 0x00, 0x20, 0x02, 0x48, 0x40,
+ 0x68, 0x02, 0x49, 0x08, 0x61, 0x70, 0x47, 0x00,
+ 0x00, 0xA0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x40, 0xFE, 0x49, 0xFF, 0x4A, 0x00, 0x28, 0x05,
+ 0xD1, 0x08, 0x46, 0x40, 0x38, 0xC0, 0x79, 0xD0,
+ 0x71, 0xC8, 0x7B, 0x06, 0xE0, 0x02, 0x28, 0x05,
+ 0xD1, 0xF8, 0x48, 0x20, 0x38, 0xC0, 0x78, 0xD0,
+ 0x71, 0x08, 0x7C, 0x50, 0x71, 0xD0, 0x79, 0x10,
+ 0x72, 0x70, 0x47, 0xF8, 0xB5, 0xF3, 0x4A, 0x40,
+ 0x3A, 0xD0, 0x68, 0x14, 0x46, 0x20, 0x34, 0x0B,
+ 0x21, 0x61, 0x56, 0x40, 0x18, 0x0C, 0x21, 0x61,
+ 0x56, 0xEF, 0x4E, 0x40, 0x18, 0x00, 0x02, 0x30,
+ 0x61, 0x11, 0x69, 0x0D, 0x23, 0xE3, 0x56, 0xC9,
+ 0x18, 0x0E, 0x23, 0xE3, 0x56, 0xC9, 0x18, 0x09,
+ 0x02, 0x71, 0x61, 0x00, 0x91,
+ 0x00, 0x00, 0x33, 0x00, 0x80, 0x51, 0x69, 0xE9,
+ 0x4D, 0x01, 0x29, 0x14, 0xD1, 0xA9, 0x69, 0x0B,
+ 0xF0, 0x3A, 0xF8, 0x30, 0x61, 0xE9, 0x69, 0x07,
+ 0x46, 0x00, 0x98, 0x0B, 0xF0, 0x34, 0xF8, 0x05,
+ 0x46, 0x05, 0x21, 0x70, 0x61, 0xC9, 0x01, 0x38,
+ 0x46, 0x0B, 0xF0, 0x37, 0xF8, 0x05, 0x21, 0x30,
+ 0x62, 0xC9, 0x01, 0x28, 0x46, 0x11, 0xE0, 0xE9,
+ 0x69, 0x0B, 0xF0, 0x25, 0xF8, 0x30, 0x61, 0xA9,
+ 0x69, 0x07, 0x46, 0x00, 0x98, 0x0B, 0xF0, 0x1F,
+ 0xF8, 0x05, 0x25, 0xED, 0x01, 0x29, 0x46, 0x70,
+ 0x61, 0x0B, 0xF0, 0x23, 0xF8, 0x30, 0x62, 0x29,
+ 0x46, 0x38, 0x46, 0x0B, 0xF0, 0x1E, 0xF8, 0x70,
+ 0x62, 0x30, 0x6A, 0x40, 0x10, 0xB0, 0x61, 0x70,
+ 0x6A, 0x40, 0x10, 0x00, 0x23, 0xF0, 0x61, 0xB3,
+ 0x70, 0x73, 0x72, 0x60, 0x79, 0x30, 0x70, 0x18,
+ 0x46, 0xFF, 0xF7, 0x96, 0xFF, 0xB3, 0x71, 0xB3,
+ 0x72, 0xF3, 0x72, 0x33, 0x71,
+ 0x00, 0x00, 0x34, 0x00, 0x80, 0xF8, 0xBD, 0x10,
+ 0xB5, 0xC7, 0x4C, 0x60, 0x78, 0x00, 0x28, 0x03,
+ 0xD1, 0xFF, 0xF7, 0x9F, 0xFF, 0x01, 0x20, 0x60,
+ 0x70, 0x10, 0xBD, 0x0A, 0x88, 0x02, 0x80, 0xCA,
+ 0x7A, 0xC2, 0x72, 0x8A, 0x79, 0x82, 0x71, 0x8A,
+ 0x88, 0x82, 0x80, 0x4A, 0x88, 0x42, 0x80, 0xCA,
+ 0x79, 0xC2, 0x71, 0x0A, 0x7A, 0x02, 0x72, 0x4A,
+ 0x7A, 0x42, 0x72, 0x8A, 0x7A, 0x82, 0x72, 0x09,
+ 0x7B, 0x01, 0x73, 0x70, 0x47, 0x30, 0xB5, 0x0C,
+ 0x46, 0x43, 0x1C, 0xB9, 0x4D, 0x07, 0xE0, 0x0E,
+ 0x20, 0x58, 0x43, 0x41, 0x19, 0x08, 0x46, 0x0E,
+ 0x38, 0xFF, 0xF7, 0xDF, 0xFF, 0x5B, 0x1C, 0xA3,
+ 0x42, 0xF5, 0xD3, 0x60, 0x1E, 0x30, 0xBD, 0xF0,
+ 0xB5, 0xAE, 0x4C, 0x06, 0x46, 0x02, 0x68, 0x00,
+ 0x20, 0x20, 0x3C, 0x0B, 0x23, 0xE3, 0x56, 0x0F,
+ 0x68, 0xD2, 0x1A, 0x03, 0xD5, 0x00, 0x22, 0x00,
+ 0x2B, 0x00, 0xD0, 0x01, 0x20,
+ 0x00, 0x00, 0x35, 0x00, 0x80, 0x0D, 0x25, 0x65,
+ 0x57, 0x7B, 0x1B, 0x03, 0xD5, 0x00, 0x23, 0x00,
+ 0x2D, 0x00, 0xD0, 0x01, 0x20, 0xA3, 0x4F, 0x40,
+ 0x3F, 0xFD, 0x68, 0x6D, 0x1E, 0xAA, 0x42, 0x05,
+ 0xD9, 0x2A, 0x46, 0x0C, 0x25, 0x65, 0x57, 0x00,
+ 0x2D, 0x00, 0xDD, 0x01, 0x20, 0x3D, 0x69, 0x6D,
+ 0x1E, 0xAB, 0x42, 0x05, 0xD9, 0x2B, 0x46, 0x0E,
+ 0x25, 0x65, 0x57, 0x00, 0x2D, 0x00, 0xDD, 0x01,
+ 0x20, 0x32, 0x60, 0x0B, 0x60, 0xF0, 0xBD, 0xFF,
+ 0xB5, 0x0E, 0x23, 0x58, 0x43, 0x98, 0x4B, 0x83,
+ 0xB0, 0xC0, 0x18, 0x80, 0x79, 0x83, 0x07, 0x9B,
+ 0x0F, 0x00, 0x93, 0x00, 0x07, 0x85, 0x0F, 0x95,
+ 0x48, 0x00, 0x23, 0x07, 0x78, 0x08, 0x46, 0x78,
+ 0x43, 0x80, 0x18, 0x9E, 0x46, 0x9C, 0x46, 0x1E,
+ 0x46, 0x1C, 0x46, 0x00, 0x2D, 0x12, 0xD0, 0x8C,
+ 0x49, 0x00, 0x2A, 0xCB, 0x69, 0x49, 0x6A, 0x9C,
+ 0x46, 0x8E, 0x46, 0x01, 0xD0,
+ 0x00, 0x00, 0x36, 0x00, 0x80, 0x43, 0x1E, 0x02,
+ 0xE0, 0x43, 0x1C, 0x00, 0x24, 0xE4, 0x43, 0x7F,
+ 0x1E, 0xBA, 0x42, 0x01, 0xD2, 0x46, 0x1C, 0x1F,
+ 0xE0, 0x46, 0x1E, 0x1C, 0xE0, 0x00, 0x9F, 0x00,
+ 0x2F, 0x1A, 0xD0, 0x81, 0x4B, 0x9E, 0x69, 0x1B,
+ 0x6A, 0xB4, 0x46, 0x9E, 0x46, 0x81, 0x4B, 0x0E,
+ 0x46, 0x1B, 0x78, 0x5E, 0x43, 0xB2, 0x18, 0xD6,
+ 0x1A, 0xD7, 0x18, 0x00, 0x29, 0x01, 0xD0, 0x33,
+ 0x46, 0x02, 0xE0, 0x00, 0x24, 0x3B, 0x46, 0xE4,
+ 0x43, 0x7B, 0x4A, 0x12, 0x78, 0x52, 0x1E, 0x91,
+ 0x42, 0x01, 0xD2, 0x3E, 0x46, 0x00, 0xE0, 0x01,
+ 0x24, 0x00, 0x99, 0x29, 0x43, 0x02, 0x91, 0x34,
+ 0xD0, 0x76, 0x4F, 0x38, 0x56, 0x81, 0x10, 0x40,
+ 0x1A, 0x01, 0x90, 0xFA, 0x56, 0xBB, 0x57, 0x00,
+ 0x20, 0x9A, 0x42, 0x01, 0xDD, 0x44, 0x1E, 0x03,
+ 0xE0, 0x1A, 0x46, 0x00, 0x2C, 0x00, 0xD1, 0x01,
+ 0x24, 0x8A, 0x42, 0x0B, 0xDD,
+ 0x00, 0x00, 0x37, 0x00, 0x80, 0x52, 0x1A, 0x60,
+ 0x46, 0x02, 0x99, 0x50, 0x43, 0x01, 0x29, 0x02,
+ 0xD0, 0x10, 0x46, 0x71, 0x46, 0x48, 0x43, 0x01,
+ 0x99, 0x0A, 0xF0, 0x3F, 0xFF, 0x44, 0x43, 0x61,
+ 0x48, 0x00, 0x21, 0x40, 0x38, 0x40, 0x69, 0x00,
+ 0x2D, 0x11, 0xD0, 0x01, 0x28, 0x06, 0xD1, 0x0C,
+ 0x98, 0x00, 0x68, 0x00, 0x19, 0x00, 0xD4, 0x01,
+ 0x46, 0x0C, 0x98, 0x05, 0xE0, 0x06, 0x98, 0x00,
+ 0x68, 0x00, 0x19, 0x00, 0xD4, 0x01, 0x46, 0x06,
+ 0x98, 0x01, 0x60, 0x07, 0xB0, 0xF0, 0xBD, 0x01,
+ 0x28, 0xF4, 0xD0, 0xEC, 0xE7, 0x30, 0xB5, 0x00,
+ 0x22, 0x13, 0x46, 0x14, 0x21, 0x4B, 0x43, 0x19,
+ 0x18, 0xC4, 0x58, 0x0D, 0x69, 0xC5, 0x50, 0x0C,
+ 0x61, 0xCC, 0x68, 0x4B, 0x68, 0x52, 0x1C, 0x4C,
+ 0x60, 0xCB, 0x60, 0x05, 0x2A, 0xF0, 0xDB, 0x30,
+ 0xBD, 0x30, 0xB5, 0x00, 0x22, 0x93, 0x00, 0x19,
+ 0x18, 0xC4, 0x58, 0x0D, 0x6D,
+ 0x00, 0x00, 0x38, 0x00, 0x80, 0xC5, 0x50, 0x0C,
+ 0x65, 0xCC, 0x6B, 0x4B, 0x69, 0x52, 0x1C, 0x4C,
+ 0x61, 0xCB, 0x63, 0x05, 0x2A, 0xF2, 0xDB, 0x30,
+ 0xBD, 0xF8, 0xB5, 0x86, 0x46, 0x08, 0x46, 0x00,
+ 0x23, 0x14, 0x21, 0x5A, 0x1C, 0x9C, 0x00, 0x59,
+ 0x43, 0x0D, 0x18, 0x0A, 0xE0, 0x97, 0x00, 0x14,
+ 0x21, 0xEE, 0x59, 0x51, 0x43, 0x09, 0x18, 0xB4,
+ 0x46, 0x0E, 0x59, 0xEE, 0x51, 0x66, 0x46, 0x0E,
+ 0x51, 0x52, 0x1C, 0x05, 0x2A, 0xF2, 0xDB, 0x5B,
+ 0x1C, 0x04, 0x2B, 0xE9, 0xDB, 0x71, 0x46, 0x01,
+ 0x29, 0x02, 0xD1, 0xFF, 0xF7, 0xD1, 0xFF, 0xF8,
+ 0xBD, 0xFF, 0xF7, 0xBC, 0xFF, 0xF8, 0xBD, 0xF3,
+ 0xB5, 0x0C, 0x46, 0xA0, 0x6A, 0x01, 0x21, 0x83,
+ 0xB0, 0x00, 0x28, 0x00, 0xD0, 0x01, 0x46, 0x2D,
+ 0x48, 0x40, 0x38, 0x80, 0x7A, 0x23, 0x6A, 0x03,
+ 0x9A, 0x02, 0x93, 0xA7, 0x69, 0x00, 0x2A, 0x02,
+ 0xD1, 0x3E, 0x46, 0x1A, 0x46,
+ 0x00, 0x00, 0x39, 0x00, 0x80, 0x01, 0xE0, 0x26,
+ 0x6C, 0xA2, 0x6C, 0x56, 0x43, 0x46, 0x43, 0x03,
+ 0x9A, 0xE0, 0x69, 0x01, 0x90, 0x00, 0x2A, 0x00,
+ 0xD0, 0x60, 0x6C, 0x00, 0x28, 0x00, 0xD1, 0x01,
+ 0x20, 0x40, 0x43, 0x05, 0x01, 0x62, 0x69, 0x69,
+ 0x43, 0x10, 0x46, 0x50, 0x43, 0x70, 0x43, 0x00,
+ 0x92, 0x0A, 0xF0, 0xB3, 0xFE, 0x20, 0x60, 0x00,
+ 0x9A, 0x90, 0x42, 0x00, 0xDD, 0x22, 0x60, 0xE0,
+ 0x6A, 0x01, 0x21, 0x00, 0x28, 0x00, 0xD0, 0x01,
+ 0x46, 0x38, 0x46, 0x78, 0x43, 0x70, 0x43, 0x69,
+ 0x43, 0x0A, 0xF0, 0xA3, 0xFE, 0x60, 0x60, 0xB8,
+ 0x42, 0x00, 0xDD, 0x67, 0x60, 0x03, 0x98, 0x21,
+ 0x6B, 0x00, 0x28, 0x02, 0xD1, 0x09, 0x01, 0x30,
+ 0x46, 0x03, 0xE0, 0x01, 0x98, 0x69, 0x43, 0x40,
+ 0x43, 0x70, 0x43, 0x0A, 0xF0, 0x92, 0xFE, 0xA0,
+ 0x60, 0x01, 0x99, 0x88, 0x42, 0x00, 0xDD, 0xA1,
+ 0x60, 0x01, 0x27, 0x60, 0x6B,
+ 0x00, 0x00, 0x3A, 0x00, 0x80, 0x39, 0x46, 0x00,
+ 0x28, 0x00, 0xD0, 0x01, 0x46, 0x02, 0x98, 0x69,
+ 0x43, 0x40, 0x43, 0x70, 0x43, 0x0A, 0xF0, 0x81,
+ 0xFE, 0xE0, 0x60, 0x02, 0x99, 0x88, 0x42, 0x00,
+ 0xDD, 0xE1, 0x60, 0x0D, 0xE0, 0xD0, 0xDD, 0x00,
+ 0x00, 0x90, 0x00, 0x00, 0x20, 0x88, 0xDF, 0x00,
+ 0x00, 0x4C, 0x03, 0x00, 0x20, 0x6E, 0x01, 0x00,
+ 0x20, 0x6D, 0x01, 0x00, 0x20, 0x64, 0x08, 0x00,
+ 0x20, 0xA1, 0x6B, 0x38, 0x46, 0x00, 0x29, 0x00,
+ 0xD0, 0x08, 0x46, 0x67, 0x6A, 0x29, 0x46, 0x3A,
+ 0x46, 0x7A, 0x43, 0x72, 0x43, 0x41, 0x43, 0x10,
+ 0x46, 0x0A, 0xF0, 0x5F, 0xFE, 0x20, 0x61, 0xB8,
+ 0x42, 0x00, 0xDD, 0x27, 0x61, 0x61, 0x68, 0xA0,
+ 0x68, 0x81, 0x42, 0x00, 0xDD, 0x60, 0x60, 0xE1,
+ 0x68, 0x81, 0x42, 0x00, 0xDD, 0xE0, 0x60, 0x21,
+ 0x68, 0x60, 0x68, 0x81, 0x42, 0x00, 0xDD, 0x20,
+ 0x60, 0x21, 0x69, 0xE0, 0x68,
+ 0x00, 0x00, 0x3B, 0x00, 0x80, 0x81, 0x42, 0x00,
+ 0xDD, 0x20, 0x61, 0x05, 0xB0, 0xF0, 0xBD, 0xF0,
+ 0xB5, 0x04, 0x46, 0xFD, 0x48, 0x8B, 0xB0, 0xC0,
+ 0x7A, 0x00, 0x90, 0x61, 0x6C, 0x01, 0x20, 0x00,
+ 0x29, 0x00, 0xD0, 0x08, 0x46, 0x05, 0x90, 0xE0,
+ 0x6B, 0x01, 0x22, 0x00, 0x28, 0x00, 0xD0, 0x02,
+ 0x46, 0x04, 0x92, 0x21, 0x6C, 0x0A, 0x91, 0xA0,
+ 0x6C, 0x09, 0x90, 0x41, 0x43, 0x00, 0x98, 0x41,
+ 0x43, 0x03, 0x91, 0x20, 0x6B, 0x08, 0x90, 0x40,
+ 0x43, 0x07, 0x90, 0xE5, 0x6A, 0x66, 0x6B, 0x28,
+ 0x46, 0x00, 0x99, 0x70, 0x43, 0x48, 0x43, 0x00,
+ 0x02, 0x07, 0x99, 0x0A, 0xF0, 0x1E, 0xFE, 0x07,
+ 0x46, 0x05, 0x98, 0x03, 0x99, 0x40, 0x43, 0x06,
+ 0x90, 0x08, 0x02, 0x06, 0x99, 0x0A, 0xF0, 0x15,
+ 0xFE, 0x38, 0x18, 0x02, 0x90, 0x06, 0x98, 0x04,
+ 0x9A, 0x01, 0x01, 0x01, 0x91, 0xA7, 0x6A, 0x03,
+ 0x99, 0x38, 0x46, 0x78, 0x43,
+ 0x00, 0x00, 0x3C, 0x00, 0x80, 0x48, 0x43, 0x01,
+ 0x99, 0x51, 0x43, 0x0A, 0xF0, 0x06, 0xFE, 0x60,
+ 0x61, 0xB8, 0x42, 0x00, 0xDD, 0x67, 0x61, 0x01,
+ 0x27, 0x0A, 0x98, 0x39, 0x46, 0x00, 0x28, 0x00,
+ 0xD0, 0x01, 0x46, 0x28, 0x46, 0x02, 0x9A, 0x68,
+ 0x43, 0x50, 0x43, 0x49, 0x03, 0x0A, 0xF0, 0xF5,
+ 0xFD, 0xA0, 0x61, 0xA8, 0x42, 0x00, 0xDD, 0xA5,
+ 0x61, 0x3A, 0x46, 0x00, 0x2D, 0x00, 0xD0, 0x2A,
+ 0x46, 0x00, 0x2E, 0x00, 0xD0, 0x72, 0x43, 0xD0,
+ 0x49, 0x07, 0x98, 0x20, 0x31, 0xC9, 0x7B, 0x08,
+ 0x41, 0x90, 0x42, 0x00, 0xDA, 0x10, 0x46, 0x05,
+ 0x99, 0x00, 0x9A, 0x09, 0x01, 0x50, 0x43, 0x0A,
+ 0xF0, 0xDC, 0xFD, 0xE0, 0x61, 0x08, 0x99, 0x4A,
+ 0x00, 0x89, 0x18, 0xCA, 0x0F, 0x51, 0x18, 0x49,
+ 0x10, 0x88, 0x42, 0x00, 0xDD, 0xE1, 0x61, 0x09,
+ 0x98, 0x39, 0x46, 0x00, 0x28, 0x00, 0xD0, 0x01,
+ 0x46, 0x30, 0x46, 0x02, 0x9A,
+ 0x00, 0x00, 0x3D, 0x00, 0x80, 0x70, 0x43, 0x50,
+ 0x43, 0x49, 0x03, 0x0A, 0xF0, 0xC6, 0xFD, 0x20,
+ 0x62, 0xB0, 0x42, 0x00, 0xDD, 0x26, 0x62, 0xE0,
+ 0x6C, 0x00, 0x28, 0x00, 0xD0, 0x07, 0x46, 0xA5,
+ 0x6B, 0x03, 0x99, 0x28, 0x46, 0x68, 0x43, 0x48,
+ 0x43, 0x01, 0x99, 0x79, 0x43, 0x0A, 0xF0, 0xB5,
+ 0xFD, 0x60, 0x62, 0xA8, 0x42, 0x00, 0xDD, 0x65,
+ 0x62, 0xA1, 0x69, 0xE0, 0x69, 0x81, 0x42, 0x03,
+ 0xDD, 0xC1, 0x0F, 0x09, 0x18, 0x49, 0x10, 0xA1,
+ 0x61, 0x21, 0x6A, 0x81, 0x42, 0x03, 0xDD, 0xC1,
+ 0x0F, 0x08, 0x18, 0x40, 0x10, 0x20, 0x62, 0x61,
+ 0x69, 0xA0, 0x69, 0x81, 0x42, 0x03, 0xDD, 0xC1,
+ 0x0F, 0x08, 0x18, 0x40, 0x10, 0x60, 0x61, 0x61,
+ 0x6A, 0x20, 0x6A, 0x81, 0x42, 0x03, 0xDD, 0xC1,
+ 0x0F, 0x08, 0x18, 0x40, 0x10, 0x60, 0x62, 0x21,
+ 0x46, 0x01, 0x20, 0xFF, 0xF7, 0xB0, 0xFE, 0x0B,
+ 0xB0, 0xF0, 0xBD, 0xF0, 0xB5,
+ 0x00, 0x00, 0x3E, 0x00, 0x80, 0xA0, 0x49, 0xCA,
+ 0x7A, 0x89, 0x7A, 0x4B, 0x00, 0xC9, 0x18, 0x8C,
+ 0x46, 0x02, 0x23, 0x14, 0x24, 0x02, 0x21, 0x5C,
+ 0x43, 0x27, 0x18, 0x8E, 0x00, 0xBD, 0x59, 0x00,
+ 0x24, 0x05, 0x2D, 0x00, 0xDD, 0x6C, 0x1F, 0x49,
+ 0x1C, 0xBC, 0x51, 0x05, 0x29, 0xF5, 0xD3, 0x5B,
+ 0x1C, 0x05, 0x2B, 0xEE, 0xD3, 0x43, 0x6C, 0x01,
+ 0x6B, 0xC9, 0x1A, 0x51, 0x43, 0x09, 0x11, 0xC1,
+ 0x61, 0x83, 0x6C, 0x41, 0x6B, 0xC9, 0x1A, 0x51,
+ 0x43, 0x09, 0x11, 0x01, 0x62, 0x81, 0x6B, 0xC3,
+ 0x6C, 0x89, 0x10, 0xC9, 0x1A, 0x51, 0x43, 0x09,
+ 0x11, 0x41, 0x62, 0x02, 0x21, 0x8B, 0x00, 0x1C,
+ 0x18, 0x64, 0x69, 0x65, 0x46, 0x6C, 0x43, 0x24,
+ 0x12, 0x49, 0x1C, 0xC4, 0x50, 0x05, 0x29, 0xF5,
+ 0xD3, 0x81, 0x68, 0xC3, 0x68, 0x89, 0x10, 0xC9,
+ 0x1A, 0x51, 0x43, 0x09, 0x11, 0x41, 0x60, 0x03,
+ 0x6A, 0xC1, 0x69, 0xC9, 0x1A,
+ 0x00, 0x00, 0x3F, 0x00, 0x80, 0x51, 0x43, 0x09,
+ 0x11, 0x81, 0x61, 0x43, 0x6B, 0x01, 0x6B, 0xC9,
+ 0x1A, 0x51, 0x43, 0x09, 0x11, 0xC1, 0x62, 0x83,
+ 0x6C, 0x41, 0x6C, 0xC9, 0x1A, 0x51, 0x43, 0x09,
+ 0x11, 0x01, 0x64, 0x81, 0x6D, 0xC3, 0x6D, 0x89,
+ 0x10, 0xC9, 0x1A, 0x51, 0x43, 0x09, 0x11, 0x41,
+ 0x65, 0x00, 0x21, 0x14, 0x22, 0x4A, 0x43, 0x13,
+ 0x18, 0x5B, 0x68, 0x64, 0x46, 0x63, 0x43, 0x1B,
+ 0x12, 0x49, 0x1C, 0x83, 0x50, 0x05, 0x29, 0xF4,
+ 0xD3, 0xF0, 0xBD, 0xFF, 0xB5, 0x85, 0xB0, 0x00,
+ 0x25, 0x9D, 0x63, 0xDD, 0x64, 0x1D, 0x66, 0xDD,
+ 0x65, 0x9D, 0x65, 0x98, 0x6C, 0x1C, 0x46, 0x05,
+ 0x28, 0x00, 0xDD, 0x45, 0x1F, 0x02, 0x20, 0xA5,
+ 0x64, 0x02, 0x2D, 0x00, 0xDD, 0x28, 0x46, 0x01,
+ 0x90, 0x60, 0x6C, 0x04, 0x90, 0x61, 0x6B, 0x03,
+ 0x91, 0x46, 0x18, 0x02, 0x2E, 0x00, 0xDA, 0x02,
+ 0x26, 0x61, 0x48, 0x30, 0x21,
+ 0x00, 0x00, 0x40, 0x00, 0x80, 0x41, 0x5E, 0x0F,
+ 0x02, 0x32, 0x21, 0x41, 0x5E, 0x69, 0x43, 0x08,
+ 0x02, 0x31, 0x46, 0x0A, 0xF0, 0x02, 0xFD, 0xC0,
+ 0x19, 0x5B, 0x4A, 0x34, 0x21, 0x51, 0x5E, 0x71,
+ 0x43, 0x09, 0x02, 0xC9, 0x11, 0x08, 0x18, 0x36,
+ 0x21, 0x51, 0x5E, 0x69, 0x43, 0x09, 0x02, 0xC9,
+ 0x11, 0x08, 0x18, 0x38, 0x21, 0x51, 0x5E, 0x24,
+ 0x6B, 0x69, 0x43, 0x89, 0x02, 0xC9, 0x11, 0x0F,
+ 0x18, 0x03, 0x98, 0x21, 0x1A, 0x04, 0x98, 0x08,
+ 0x1A, 0x11, 0x46, 0x3A, 0x22, 0x8A, 0x5E, 0x01,
+ 0x99, 0x50, 0x43, 0x00, 0x02, 0x09, 0x01, 0x0A,
+ 0xF0, 0xE0, 0xFC, 0xC0, 0x19, 0x4A, 0x4A, 0x3C,
+ 0x21, 0x51, 0x5E, 0x61, 0x43, 0x09, 0x02, 0xC9,
+ 0x11, 0x0F, 0x18, 0x11, 0x46, 0x3E, 0x20, 0x08,
+ 0x5E, 0x80, 0x21, 0x09, 0x1B, 0x48, 0x43, 0x00,
+ 0x02, 0x21, 0x46, 0x0A, 0xF0, 0xCE, 0xFC, 0xC1,
+ 0x19, 0x41, 0x4F, 0x60, 0x1B,
+ 0x00, 0x00, 0x41, 0x00, 0x80, 0x40, 0x37, 0x02,
+ 0x91, 0x00, 0x21, 0x79, 0x5E, 0x48, 0x43, 0x00,
+ 0x02, 0xB1, 0x00, 0x0A, 0xF0, 0xC2, 0xFC, 0x02,
+ 0x99, 0x46, 0x18, 0x04, 0x20, 0x38, 0x5E, 0x21,
+ 0x46, 0x68, 0x43, 0x00, 0x02, 0x0A, 0xF0, 0xB9,
+ 0xFC, 0x80, 0x19, 0x02, 0x90, 0x28, 0x19, 0x01,
+ 0x90, 0x06, 0x20, 0x38, 0x5E, 0x04, 0x99, 0x06,
+ 0x02, 0x03, 0x98, 0x0D, 0x1A, 0x08, 0x20, 0x38,
+ 0x5E, 0x21, 0x46, 0x68, 0x43, 0x00, 0x02, 0x0A,
+ 0xF0, 0xA8, 0xFC, 0x84, 0x19, 0x0C, 0x20, 0x38,
+ 0x5E, 0x01, 0x99, 0x45, 0x43, 0x28, 0x02, 0x0A,
+ 0xF0, 0xA0, 0xFC, 0x01, 0x19, 0x02, 0x98, 0x00,
+ 0x12, 0x0C, 0x12, 0x29, 0x49, 0x49, 0x69, 0x29,
+ 0x4A, 0x01, 0x29, 0x56, 0x69, 0x15, 0x69, 0x10,
+ 0xD1, 0x70, 0x43, 0x07, 0x14, 0x76, 0x43, 0x30,
+ 0x12, 0x60, 0x43, 0x29, 0x46, 0x0A, 0xF0, 0x8D,
+ 0xFC, 0x6C, 0x43, 0x21, 0x14,
+ 0x00, 0x00, 0x42, 0x00, 0x80, 0x7A, 0x18, 0x05,
+ 0x99, 0x00, 0x12, 0x0A, 0x60, 0x39, 0x1A, 0x06,
+ 0x98, 0x0F, 0xE0, 0x68, 0x43, 0x07, 0x14, 0x6D,
+ 0x43, 0x28, 0x12, 0x60, 0x43, 0x31, 0x46, 0x0A,
+ 0xF0, 0x7C, 0xFC, 0x74, 0x43, 0x21, 0x14, 0x06,
+ 0x9A, 0x79, 0x18, 0x00, 0x12, 0x11, 0x60, 0x39,
+ 0x1A, 0x05, 0x98, 0x01, 0x60, 0x09, 0xB0, 0xF0,
+ 0xBD, 0xFF, 0xB5, 0x91, 0xB0, 0x1C, 0x46, 0x00,
+ 0x20, 0x09, 0xE0, 0x0E, 0x22, 0x12, 0x4B, 0x42,
+ 0x43, 0xD2, 0x18, 0xD3, 0x7A, 0x20, 0x2B, 0x01,
+ 0xD1, 0x00, 0x23, 0x93, 0x71, 0x40, 0x1C, 0x11,
+ 0x9A, 0x90, 0x42, 0xF2, 0xD3, 0x48, 0x00, 0x12,
+ 0x90, 0x09, 0x48, 0x05, 0x92, 0x40, 0x30, 0x10,
+ 0x90, 0x14, 0xE3, 0x40, 0x1E, 0x0E, 0x21, 0x05,
+ 0x90, 0x48, 0x43, 0x07, 0x49, 0x46, 0x18, 0xF0,
+ 0x7A, 0x10, 0x28, 0xF5, 0xD0, 0xB5, 0x88, 0x70,
+ 0x88, 0x0B, 0x90, 0x00, 0x20,
+ 0x00, 0x00, 0x43, 0x00, 0x80, 0x28, 0xE0, 0x00,
+ 0x00, 0x90, 0xDD, 0x00, 0x00, 0x90, 0x00, 0x00,
+ 0x20, 0x4C, 0x03, 0x00, 0x20, 0x13, 0x99, 0x0B,
+ 0x9A, 0x09, 0x5C, 0x52, 0x1A, 0x00, 0xD5, 0x52,
+ 0x42, 0x13, 0x99, 0x09, 0x18, 0x49, 0x78, 0x69,
+ 0x1A, 0x00, 0xD5, 0x49, 0x42, 0x13, 0x46, 0x0B,
+ 0x43, 0x11, 0xD0, 0x03, 0x2A, 0x0F, 0xDC, 0x03,
+ 0x29, 0x0D, 0xDC, 0x02, 0x2A, 0x02, 0xDA, 0xB2,
+ 0x79, 0x12, 0x1D, 0xB2, 0x71, 0x02, 0x29, 0x02,
+ 0xDA, 0xB1, 0x79, 0x49, 0x1C, 0xB1, 0x71, 0xB1,
+ 0x79, 0xF0, 0x22, 0x11, 0x43, 0xB1, 0x71, 0x80,
+ 0x1C, 0x12, 0x99, 0x88, 0x42, 0xDA, 0xD3, 0x0B,
+ 0x98, 0xC0, 0x1E, 0x84, 0x46, 0x00, 0x20, 0x06,
+ 0x90, 0x60, 0x46, 0x40, 0x1C, 0x84, 0x46, 0x03,
+ 0xD4, 0xFF, 0x49, 0x09, 0x78, 0x8C, 0x45, 0x0B,
+ 0xDB, 0x06, 0x9A, 0x00, 0x20, 0x14, 0x23, 0x5A,
+ 0x43, 0x01, 0x46, 0x12, 0x19,
+ 0x00, 0x00, 0x44, 0x00, 0x80, 0x83, 0x00, 0x40,
+ 0x1C, 0xD1, 0x50, 0x05, 0x28, 0xFA, 0xDB, 0x24,
+ 0xE0, 0xF8, 0x4A, 0x60, 0x46, 0x12, 0x78, 0xA9,
+ 0x1E, 0x50, 0x43, 0x40, 0x18, 0x06, 0x9A, 0x0A,
+ 0x90, 0x14, 0x23, 0x00, 0x20, 0x5A, 0x43, 0x17,
+ 0x19, 0x00, 0x29, 0x03, 0xDB, 0xF1, 0x4A, 0x12,
+ 0x78, 0x91, 0x42, 0x02, 0xDB, 0x00, 0x22, 0x83,
+ 0x00, 0x07, 0xE0, 0xEF, 0x4A, 0x0A, 0x9B, 0xD2,
+ 0x56, 0x83, 0x00, 0xFA, 0x50, 0x00, 0x2A, 0x01,
+ 0xDA, 0x00, 0x22, 0xFA, 0x50, 0x0A, 0x9A, 0x49,
+ 0x1C, 0x52, 0x1C, 0x40, 0x1C, 0x0A, 0x92, 0x05,
+ 0x28, 0xE6, 0xDB, 0x06, 0x98, 0x40, 0x1C, 0x06,
+ 0x90, 0x05, 0x28, 0xC1, 0xDB, 0x20, 0x6B, 0x00,
+ 0x28, 0x01, 0xD1, 0x01, 0x20, 0x20, 0x63, 0x00,
+ 0x20, 0x04, 0x90, 0x03, 0x90, 0x02, 0x90, 0x0B,
+ 0x98, 0x01, 0x28, 0x39, 0xDC, 0x00, 0x28, 0x32,
+ 0xD1, 0x00, 0x2D, 0x04, 0xD0,
+ 0x00, 0x00, 0x45, 0x00, 0x80, 0xDB, 0x48, 0x00,
+ 0x78, 0x40, 0x1E, 0x85, 0x42, 0x25, 0xD1, 0x08,
+ 0x20, 0x02, 0x90, 0x00, 0x2D, 0x02, 0xD0, 0x20,
+ 0x46, 0xFF, 0xF7, 0x9C, 0xFC, 0x10, 0x98, 0x40,
+ 0x7C, 0x01, 0x28, 0x06, 0xD1, 0x23, 0x46, 0x03,
+ 0xA9, 0x04, 0xA8, 0x05, 0x9A, 0xFF, 0xF7, 0x8D,
+ 0xFE, 0x02, 0xE0, 0x20, 0x46, 0xFF, 0xF7, 0x25,
+ 0xFE, 0x00, 0x2D, 0x7E, 0xD0, 0xCF, 0x48, 0x40,
+ 0x69, 0x01, 0x28, 0x03, 0xD1, 0x03, 0x98, 0x40,
+ 0x42, 0x03, 0x90, 0x02, 0xE0, 0x04, 0x98, 0x40,
+ 0x42, 0x04, 0x90, 0x20, 0x46, 0xFF, 0xF7, 0x7E,
+ 0xFC, 0x63, 0xE0, 0x01, 0x20, 0x02, 0x90, 0x20,
+ 0x46, 0xFF, 0xF7, 0x55, 0xFD, 0x5D, 0xE0, 0x21,
+ 0x46, 0x00, 0x20, 0xFF, 0xF7, 0xB8, 0xFC, 0x58,
+ 0xE0, 0xBF, 0x4F, 0x02, 0x46, 0x39, 0x78, 0x88,
+ 0x1E, 0x82, 0x42, 0x52, 0xDB, 0x01, 0x23, 0x18,
+ 0x46, 0x00, 0x2D, 0x05, 0xD0,
+ 0x00, 0x00, 0x46, 0x00, 0x80, 0xBB, 0x4A, 0x12,
+ 0x78, 0x52, 0x1E, 0x95, 0x42, 0x00, 0xD0, 0x00,
+ 0x20, 0x0B, 0x9A, 0x49, 0x1E, 0x8A, 0x42, 0x00,
+ 0xD0, 0x00, 0x23, 0x18, 0x42, 0x2C, 0xD0, 0x09,
+ 0x20, 0x02, 0x90, 0x20, 0x46, 0xFF, 0xF7, 0x68,
+ 0xFC, 0x00, 0x2D, 0x02, 0xD0, 0x20, 0x46, 0xFF,
+ 0xF7, 0x51, 0xFC, 0x10, 0x98, 0x40, 0x7C, 0x01,
+ 0x28, 0x06, 0xD1, 0x23, 0x46, 0x03, 0xA9, 0x04,
+ 0xA8, 0x05, 0x9A, 0xFF, 0xF7, 0x42, 0xFE, 0x02,
+ 0xE0, 0x20, 0x46, 0xFF, 0xF7, 0xDA, 0xFD, 0x20,
+ 0x46, 0xFF, 0xF7, 0x52, 0xFC, 0x00, 0x2D, 0x0B,
+ 0xD1, 0xA8, 0x48, 0x40, 0x69, 0x01, 0x28, 0x03,
+ 0xD1, 0x04, 0x98, 0x40, 0x42, 0x04, 0x90, 0x23,
+ 0xE0, 0x03, 0x98, 0x40, 0x42, 0x03, 0x90, 0x1F,
+ 0xE0, 0x04, 0x98, 0x40, 0x42, 0x04, 0x90, 0xA5,
+ 0xE7, 0x20, 0x46, 0xFF, 0xF7, 0x3D, 0xFC, 0x38,
+ 0x78, 0x0B, 0x99, 0x40, 0x1E,
+ 0x00, 0x00, 0x47, 0x00, 0x80, 0x81, 0x42, 0x05,
+ 0xD1, 0x02, 0x20, 0x02, 0x90, 0x20, 0x46, 0xFF,
+ 0xF7, 0xFE, 0xFC, 0x03, 0xE0, 0x21, 0x46, 0x00,
+ 0x20, 0xFF, 0xF7, 0x61, 0xFC, 0x20, 0x46, 0xFF,
+ 0xF7, 0x2B, 0xFC, 0x01, 0x2D, 0x1F, 0xDC, 0x00,
+ 0x2D, 0x0A, 0xD1, 0x0B, 0x98, 0x00, 0x28, 0x41,
+ 0xD0, 0x8F, 0x48, 0x0B, 0x99, 0x00, 0x78, 0x40,
+ 0x1E, 0x00, 0xE0, 0x3B, 0xE0, 0x81, 0x42, 0x39,
+ 0xD0, 0x21, 0x46, 0x00, 0x20, 0xFF, 0xF7, 0x28,
+ 0xFC, 0x00, 0x2D, 0x05, 0xD1, 0x03, 0x20, 0x02,
+ 0x90, 0x20, 0x46, 0xFF, 0xF7, 0xDC, 0xFC, 0x03,
+ 0xE0, 0x21, 0x46, 0x00, 0x20, 0xFF, 0xF7, 0x3F,
+ 0xFC, 0x21, 0x46, 0x01, 0x20, 0x24, 0xE0, 0x83,
+ 0x4F, 0x38, 0x78, 0x81, 0x1E, 0x8D, 0x42, 0x21,
+ 0xDB, 0x40, 0x1E, 0x85, 0x42, 0x08, 0xD1, 0x0B,
+ 0x98, 0x00, 0x28, 0x1B, 0xD0, 0x01, 0x46, 0x7C,
+ 0x48, 0x00, 0x78, 0x40, 0x1E,
+ 0x00, 0x00, 0x48, 0x00, 0x80, 0x81, 0x42, 0x15,
+ 0xD0, 0x21, 0x46, 0x01, 0x20, 0xFF, 0xF7, 0x04,
+ 0xFC, 0x38, 0x78, 0x40, 0x1E, 0x85, 0x42, 0x05,
+ 0xD1, 0x04, 0x20, 0x02, 0x90, 0x20, 0x46, 0xFF,
+ 0xF7, 0xB6, 0xFC, 0x03, 0xE0, 0x21, 0x46, 0x00,
+ 0x20, 0xFF, 0xF7, 0x19, 0xFC, 0x21, 0x46, 0x00,
+ 0x20, 0xFF, 0xF7, 0xF2, 0xFB, 0x02, 0x98, 0x00,
+ 0x07, 0x13, 0xD4, 0x00, 0x21, 0x14, 0x22, 0x00,
+ 0x20, 0x4A, 0x43, 0x17, 0x19, 0x83, 0x00, 0x9C,
+ 0x46, 0xFB, 0x58, 0x00, 0x22, 0x05, 0x2B, 0x00,
+ 0xDD, 0x5A, 0x1F, 0x63, 0x46, 0x40, 0x1C, 0xFA,
+ 0x50, 0x05, 0x28, 0xF3, 0xDB, 0x49, 0x1C, 0x05,
+ 0x29, 0xEC, 0xDB, 0x20, 0x6B, 0x00, 0x28, 0x01,
+ 0xD1, 0x01, 0x20, 0x20, 0x63, 0xE1, 0x69, 0xA0,
+ 0x69, 0xE2, 0x6A, 0x40, 0x18, 0x21, 0x6A, 0x00,
+ 0x27, 0x89, 0x18, 0x40, 0x18, 0x21, 0x6B, 0x40,
+ 0x18, 0x61, 0x6B, 0x40, 0x18,
+ 0x00, 0x00, 0x49, 0x00, 0x80, 0x21, 0x6C, 0x40,
+ 0x18, 0x61, 0x6C, 0x40, 0x18, 0xA1, 0x6C, 0x07,
+ 0x97, 0x40, 0x18, 0x08, 0x97, 0x09, 0x90, 0xB0,
+ 0x79, 0x00, 0x28, 0x7E, 0xD1, 0x82, 0x00, 0x96,
+ 0x46, 0xA1, 0x58, 0x13, 0x19, 0x5A, 0x69, 0x9C,
+ 0x46, 0x89, 0x18, 0x9A, 0x6A, 0xDB, 0x6B, 0xD2,
+ 0x18, 0x89, 0x18, 0x63, 0x46, 0x1A, 0x6D, 0x89,
+ 0x18, 0xCF, 0x19, 0x14, 0x22, 0x01, 0x46, 0x51,
+ 0x43, 0x0A, 0x19, 0x12, 0x69, 0x61, 0x58, 0x40,
+ 0x1C, 0x51, 0x1A, 0x07, 0x9A, 0x89, 0x18, 0x07,
+ 0x91, 0x72, 0x46, 0xA2, 0x58, 0x19, 0x6D, 0x89,
+ 0x1A, 0x08, 0x9A, 0x89, 0x18, 0x08, 0x91, 0x05,
+ 0x28, 0xDC, 0xDB, 0x07, 0x98, 0x40, 0x00, 0x07,
+ 0x90, 0x48, 0x00, 0x08, 0x90, 0x00, 0x20, 0x14,
+ 0x21, 0x41, 0x43, 0x09, 0x19, 0xCA, 0x68, 0x49,
+ 0x68, 0x51, 0x1A, 0x07, 0x9A, 0x89, 0x18, 0x07,
+ 0x91, 0x81, 0x00, 0x09, 0x19,
+ 0x00, 0x00, 0x4A, 0x00, 0x80, 0xCA, 0x6B, 0x49,
+ 0x69, 0x40, 0x1C, 0x51, 0x1A, 0x08, 0x9A, 0x89,
+ 0x18, 0x08, 0x91, 0x05, 0x28, 0xEB, 0xDB, 0x02,
+ 0x98, 0x39, 0x46, 0x01, 0x28, 0x20, 0xD1, 0x00,
+ 0x20, 0x06, 0x90, 0x14, 0x22, 0x50, 0x43, 0x22,
+ 0x58, 0x00, 0x19, 0x43, 0x68, 0x96, 0x46, 0xD2,
+ 0x18, 0x0F, 0x93, 0x84, 0x46, 0x83, 0x68, 0xC0,
+ 0x68, 0x1B, 0x18, 0xD2, 0x18, 0x63, 0x46, 0x1B,
+ 0x69, 0xD2, 0x18, 0x89, 0x1A, 0x72, 0x46, 0x9A,
+ 0x1A, 0x0F, 0x9B, 0x52, 0x00, 0xC0, 0x1A, 0x10,
+ 0x18, 0x07, 0x9A, 0x10, 0x1A, 0x07, 0x90, 0x06,
+ 0x98, 0x40, 0x1C, 0x06, 0x90, 0x02, 0x28, 0xE0,
+ 0xDB, 0x02, 0x98, 0x02, 0x28, 0x22, 0xD1, 0x03,
+ 0x20, 0x06, 0x90, 0x14, 0x22, 0x50, 0x43, 0x22,
+ 0x58, 0x00, 0x19, 0x43, 0x68, 0x96, 0x46, 0xD2,
+ 0x18, 0x0E, 0x93, 0x84, 0x46, 0x83, 0x68, 0xC0,
+ 0x68, 0x1B, 0x18, 0xD2, 0x18,
+ 0x00, 0x00, 0x4B, 0x00, 0x80, 0x63, 0x46, 0x1B,
+ 0x69, 0xD2, 0x18, 0x89, 0x1A, 0x72, 0x46, 0x9A,
+ 0x1A, 0x0E, 0x9B, 0x52, 0x00, 0xC0, 0x1A, 0x10,
+ 0x18, 0x00, 0xE0, 0x57, 0xE0, 0x07, 0x9A, 0x10,
+ 0x1A, 0x07, 0x90, 0x06, 0x98, 0x40, 0x1C, 0x06,
+ 0x90, 0x05, 0x28, 0xDE, 0xDB, 0x02, 0x98, 0x03,
+ 0x28, 0x28, 0xD1, 0x00, 0x20, 0x06, 0x90, 0x80,
+ 0x00, 0x22, 0x58, 0x00, 0x19, 0x43, 0x69, 0x96,
+ 0x46, 0xD2, 0x18, 0x0D, 0x93, 0x84, 0x46, 0x83,
+ 0x6A, 0xC0, 0x6B, 0x1B, 0x18, 0xD2, 0x18, 0x63,
+ 0x46, 0x1B, 0x6D, 0xD2, 0x18, 0xBF, 0x1A, 0x72,
+ 0x46, 0x9A, 0x1A, 0x0D, 0x9B, 0x52, 0x00, 0xC0,
+ 0x1A, 0x10, 0x18, 0x08, 0x9A, 0x10, 0x1A, 0x08,
+ 0x90, 0x06, 0x98, 0x40, 0x1C, 0x06, 0x90, 0x07,
+ 0xE0, 0x6D, 0x01, 0x00, 0x20, 0x6E, 0x01, 0x00,
+ 0x20, 0x64, 0x08, 0x00, 0x20, 0x90, 0xDD, 0x00,
+ 0x00, 0x02, 0x28, 0xD8, 0xDB,
+ 0x00, 0x00, 0x4C, 0x00, 0x80, 0x02, 0x98, 0x04,
+ 0x28, 0x5F, 0xD1, 0x03, 0x20, 0x06, 0x90, 0x80,
+ 0x00, 0x22, 0x58, 0x00, 0x19, 0x43, 0x69, 0x96,
+ 0x46, 0xD2, 0x18, 0x0C, 0x93, 0x84, 0x46, 0x83,
+ 0x6A, 0xC0, 0x6B, 0x1B, 0x18, 0xD2, 0x18, 0x63,
+ 0x46, 0x1B, 0x6D, 0xD2, 0x18, 0xBF, 0x1A, 0x72,
+ 0x46, 0x9A, 0x1A, 0x0C, 0x9B, 0x52, 0x00, 0xC0,
+ 0x1A, 0x10, 0x18, 0x08, 0x9A, 0x10, 0x1A, 0x08,
+ 0x90, 0x06, 0x98, 0x40, 0x1C, 0x06, 0x90, 0x05,
+ 0x28, 0xE1, 0xDB, 0x3E, 0xE0, 0x09, 0x9F, 0x01,
+ 0x20, 0x39, 0x46, 0x14, 0x22, 0x42, 0x43, 0x12,
+ 0x19, 0xD3, 0x68, 0x52, 0x68, 0x9A, 0x1A, 0x07,
+ 0x9B, 0xD2, 0x18, 0x07, 0x92, 0x82, 0x00, 0x12,
+ 0x19, 0xD3, 0x6B, 0x52, 0x69, 0x40, 0x1C, 0x9A,
+ 0x1A, 0x08, 0x9B, 0xD2, 0x18, 0x08, 0x92, 0x04,
+ 0x28, 0xEB, 0xDB, 0x02, 0x98, 0x01, 0x28, 0x04,
+ 0xD1, 0xA2, 0x69, 0xE0, 0x69,
+ 0x00, 0x00, 0x4D, 0x00, 0x80, 0x13, 0x18, 0x20,
+ 0x6A, 0x05, 0xE0, 0x02, 0x28, 0x0A, 0xD1, 0x22,
+ 0x6C, 0x60, 0x6C, 0x13, 0x18, 0xA0, 0x6C, 0x1B,
+ 0x18, 0x80, 0x1A, 0x07, 0x9A, 0xC9, 0x1A, 0x10,
+ 0x1A, 0x07, 0x90, 0x12, 0xE0, 0x03, 0x28, 0x04,
+ 0xD1, 0xA2, 0x69, 0xE0, 0x6A, 0x13, 0x18, 0x20,
+ 0x6C, 0x05, 0xE0, 0x04, 0x28, 0x09, 0xD1, 0x22,
+ 0x6A, 0x60, 0x6B, 0x13, 0x18, 0xA0, 0x6C, 0x1B,
+ 0x18, 0x80, 0x1A, 0x08, 0x9A, 0xFF, 0x1A, 0x10,
+ 0x1A, 0x08, 0x90, 0x07, 0x98, 0x00, 0x02, 0x0A,
+ 0xF0, 0xA4, 0xF9, 0x29, 0x02, 0x40, 0x18, 0x80,
+ 0x30, 0x07, 0x90, 0x08, 0x98, 0x39, 0x46, 0x00,
+ 0x02, 0x0A, 0xF0, 0x9B, 0xF9, 0x0B, 0x99, 0x09,
+ 0x02, 0x40, 0x18, 0x80, 0x30, 0xFF, 0x4F, 0x08,
+ 0x90, 0x79, 0x69, 0x01, 0x29, 0x0B, 0xD1, 0xFE,
+ 0x49, 0x07, 0x98, 0x4A, 0x69, 0x50, 0x43, 0x00,
+ 0x14, 0x07, 0x90, 0x08, 0x98,
+ 0x00, 0x00, 0x4E, 0x00, 0x80, 0x09, 0x69, 0x48,
+ 0x43, 0x00, 0x14, 0x08, 0x90, 0x0A, 0xE0, 0xF8,
+ 0x49, 0x4A, 0x69, 0x09, 0x69, 0x50, 0x43, 0x07,
+ 0x9A, 0x00, 0x14, 0x4A, 0x43, 0x11, 0x14, 0x07,
+ 0x90, 0x08, 0x91, 0x08, 0x46, 0x04, 0x99, 0x40,
+ 0x18, 0x08, 0x90, 0x03, 0x99, 0x07, 0x98, 0x40,
+ 0x18, 0x00, 0x21, 0x0A, 0x46, 0x07, 0x90, 0x00,
+ 0x28, 0x00, 0xDB, 0x02, 0x46, 0x08, 0x98, 0x07,
+ 0x92, 0x00, 0x28, 0x00, 0xDB, 0x01, 0x46, 0x08,
+ 0x91, 0xB0, 0x79, 0x00, 0x07, 0x07, 0xD0, 0x07,
+ 0xAA, 0x00, 0x92, 0x2A, 0x46, 0x08, 0xAB, 0x0B,
+ 0x99, 0x05, 0x98, 0xFF, 0xF7, 0xB4, 0xF9, 0x07,
+ 0xA9, 0x08, 0xA8, 0xFF, 0xF7, 0x80, 0xF9, 0x00,
+ 0x28, 0x05, 0xD0, 0x11, 0x99, 0x05, 0x98, 0xFF,
+ 0xF7, 0x69, 0xF9, 0x11, 0x90, 0x0E, 0xE0, 0x07,
+ 0x98, 0xB0, 0x80, 0x08, 0x98, 0x70, 0x80, 0xB9,
+ 0x69, 0x09, 0x98, 0x50, 0x22,
+ 0x00, 0x00, 0x4F, 0x00, 0x80, 0x50, 0x43, 0x41,
+ 0x43, 0xC8, 0x0B, 0xFF, 0x21, 0xFF, 0x28, 0x00,
+ 0xD8, 0xC1, 0xB2, 0xB1, 0x71, 0x05, 0x98, 0x00,
+ 0x28, 0x00, 0xD0, 0xE6, 0xE4, 0x11, 0x98, 0x15,
+ 0xB0, 0xF0, 0xBD, 0xF0, 0xB5, 0xD3, 0x4E, 0x00,
+ 0x24, 0x02, 0x22, 0x73, 0x1F, 0xA4, 0x18, 0x35,
+ 0x5D, 0x1F, 0x5D, 0x45, 0x43, 0x4F, 0x43, 0xBD,
+ 0x42, 0x00, 0xD9, 0xA4, 0x1A, 0x52, 0x08, 0xF5,
+ 0xD1, 0x22, 0x01, 0x94, 0x46, 0x1D, 0x5D, 0x32,
+ 0x5D, 0x64, 0x1C, 0x1B, 0x5D, 0x4D, 0x43, 0x4B,
+ 0x43, 0x31, 0x5D, 0x42, 0x43, 0x5B, 0x1B, 0x41,
+ 0x43, 0x8C, 0x1A, 0x2E, 0x01, 0x15, 0x01, 0x08,
+ 0x21, 0x00, 0x20, 0x40, 0x18, 0x02, 0x46, 0x07,
+ 0x46, 0x62, 0x43, 0x5F, 0x43, 0x52, 0x19, 0xBF,
+ 0x19, 0xBA, 0x42, 0x00, 0xD9, 0x40, 0x1A, 0x49,
+ 0x08, 0xF3, 0xD1, 0x60, 0x44, 0xF0, 0xBD, 0xFF,
+ 0xB5, 0x83, 0xB0, 0x00, 0x25,
+ 0x00, 0x00, 0x50, 0x00, 0x80, 0x03, 0x98, 0x0C,
+ 0x9C, 0x00, 0x95, 0x00, 0x28, 0x03, 0xD0, 0xB8,
+ 0x48, 0x00, 0x78, 0x80, 0x07, 0x03, 0xD1, 0x00,
+ 0x20, 0xE0, 0x71, 0x20, 0x72, 0x99, 0xE0, 0x00,
+ 0x20, 0x02, 0x90, 0x40, 0x1E, 0x01, 0x90, 0xB1,
+ 0x48, 0x40, 0x69, 0x01, 0x28, 0x03, 0xD1, 0x60,
+ 0x88, 0x86, 0x46, 0xA0, 0x88, 0x02, 0xE0, 0xA0,
+ 0x88, 0x86, 0x46, 0x60, 0x88, 0x00, 0x22, 0x84,
+ 0x46, 0x23, 0xE0, 0x08, 0x78, 0x05, 0x9B, 0x06,
+ 0x9E, 0x58, 0x43, 0x5B, 0x08, 0xC0, 0x18, 0x03,
+ 0x0A, 0x70, 0x46, 0x1B, 0x1A, 0x48, 0x78, 0x70,
+ 0x43, 0x76, 0x08, 0x80, 0x19, 0x00, 0x0A, 0x66,
+ 0x46, 0x86, 0x1B, 0x18, 0x46, 0x37, 0x46, 0x58,
+ 0x43, 0x77, 0x43, 0xC0, 0x19, 0x02, 0x9F, 0xB8,
+ 0x42, 0x04, 0xD3, 0x02, 0x90, 0x30, 0xB2, 0x1D,
+ 0xB2, 0x00, 0x90, 0x03, 0xE0, 0x01, 0x9B, 0x98,
+ 0x42, 0x00, 0xD8, 0x01, 0x90,
+ 0x00, 0x00, 0x51, 0x00, 0x80, 0x52, 0x1C, 0xD2,
+ 0xB2, 0x89, 0x1C, 0x03, 0x98, 0x82, 0x42, 0xD8,
+ 0xD3, 0x02, 0x98, 0x00, 0xF0, 0xC5, 0xFD, 0x46,
+ 0x00, 0x01, 0x98, 0x01, 0x01, 0x02, 0x98, 0xC2,
+ 0x00, 0x80, 0x18, 0x81, 0x42, 0x01, 0xD9, 0x37,
+ 0x46, 0x13, 0xE0, 0x01, 0x98, 0x00, 0xF0, 0xB8,
+ 0xFD, 0x47, 0x00, 0x8E, 0x48, 0x40, 0x69, 0x01,
+ 0x28, 0x02, 0xD0, 0x00, 0x98, 0x00, 0x95, 0x05,
+ 0x46, 0x8B, 0x48, 0x00, 0x78, 0x80, 0x07, 0x04,
+ 0xD5, 0x00, 0x98, 0x40, 0x42, 0x02, 0xB2, 0x00,
+ 0x2D, 0x01, 0xD1, 0x00, 0x20, 0x18, 0xE0, 0x00,
+ 0x2A, 0x03, 0xDA, 0x50, 0x42, 0x02, 0xB2, 0x68,
+ 0x42, 0x05, 0xB2, 0x68, 0x42, 0x00, 0x2D, 0x00,
+ 0xDB, 0x28, 0x46, 0x82, 0x42, 0x04, 0xD9, 0x01,
+ 0x46, 0x10, 0x46, 0xFF, 0xF7, 0x56, 0xFF, 0x04,
+ 0xE0, 0x11, 0x46, 0xFF, 0xF7, 0x52, 0xFF, 0x7F,
+ 0x21, 0x08, 0x1A, 0x00, 0x2D,
+ 0x00, 0x00, 0x52, 0x00, 0x80, 0x00, 0xDA, 0x40,
+ 0x42, 0x79, 0x49, 0x09, 0x78, 0xC9, 0x07, 0x02,
+ 0xD1, 0x00, 0x22, 0x11, 0x46, 0x1B, 0xE0, 0x75,
+ 0x49, 0x20, 0x31, 0x8A, 0x79, 0xB2, 0x42, 0x02,
+ 0xD2, 0x8A, 0x79, 0xB2, 0x1A, 0x00, 0xE0, 0x00,
+ 0x22, 0xCB, 0x79, 0x53, 0x43, 0x1A, 0x0A, 0xFF,
+ 0x2A, 0x00, 0xD9, 0xFF, 0x22, 0x0B, 0x7A, 0xBB,
+ 0x42, 0x02, 0xD2, 0x0B, 0x7A, 0xFB, 0x1A, 0x00,
+ 0xE0, 0x00, 0x23, 0x49, 0x7A, 0x59, 0x43, 0x09,
+ 0x0A, 0xFF, 0x29, 0x00, 0xD9, 0xFF, 0x21, 0xE2,
+ 0x71, 0x21, 0x72, 0x60, 0x72, 0x07, 0xB0, 0xF0,
+ 0xBD, 0xF7, 0xB5, 0x64, 0x4D, 0xD0, 0xB0, 0x6C,
+ 0x69, 0x63, 0x4B, 0x01, 0x2C, 0x1A, 0x69, 0x58,
+ 0x69, 0x02, 0xD1, 0x1C, 0x92, 0x1B, 0x90, 0x01,
+ 0xE0, 0x1B, 0x92, 0x1C, 0x90, 0x60, 0x48, 0x00,
+ 0x78, 0x40, 0x1E, 0x36, 0x90, 0x5F, 0x48, 0x00,
+ 0x78, 0x40, 0x1E, 0x35, 0x90,
+ 0x00, 0x00, 0x53, 0x00, 0x80, 0x00, 0x20, 0x1F,
+ 0x90, 0x58, 0x48, 0x42, 0x79, 0x1E, 0x92, 0x80,
+ 0x79, 0x1D, 0x90, 0x56, 0x48, 0x5A, 0x7A, 0x20,
+ 0x30, 0x4F, 0x90, 0x00, 0x2A, 0x15, 0xD0, 0x98,
+ 0x7A, 0x01, 0x28, 0x0A, 0xD1, 0x4F, 0x98, 0x02,
+ 0x78, 0x1E, 0x98, 0x10, 0x18, 0x1E, 0x90, 0x4F,
+ 0x98, 0x40, 0x78, 0x1D, 0x9A, 0x10, 0x1A, 0x1D,
+ 0x90, 0x07, 0xE0, 0xD8, 0x7A, 0x01, 0x28, 0x04,
+ 0xD1, 0x4F, 0x98, 0x00, 0x78, 0x1E, 0x9A, 0x10,
+ 0x1A, 0x1E, 0x90, 0x49, 0x48, 0x00, 0x24, 0x84,
+ 0x72, 0xC4, 0x72, 0x4B, 0x48, 0x40, 0x6A, 0x42,
+ 0x09, 0x52, 0x1C, 0x20, 0x46, 0x04, 0xE0, 0x00,
+ 0x23, 0x84, 0x00, 0x22, 0xAD, 0x2B, 0x51, 0x40,
+ 0x1C, 0x90, 0x42, 0xF8, 0xD3, 0x48, 0x00, 0x51,
+ 0x90, 0x00, 0x20, 0x21, 0xE2, 0x52, 0x99, 0x22,
+ 0xAD, 0x0A, 0x5C, 0x08, 0x46, 0x32, 0x99, 0x21,
+ 0x92, 0x40, 0x18, 0x41, 0x78,
+ 0x00, 0x00, 0x54, 0x00, 0x80, 0x20, 0x91, 0x35,
+ 0x99, 0x01, 0x23, 0x49, 0x1C, 0x4A, 0x43, 0x4E,
+ 0x91, 0x20, 0x99, 0x00, 0x24, 0x51, 0x18, 0x4A,
+ 0x09, 0x92, 0x00, 0x94, 0x46, 0xAA, 0x58, 0xCE,
+ 0x06, 0xF6, 0x0E, 0x1D, 0x46, 0xB5, 0x40, 0x16,
+ 0x46, 0x20, 0x46, 0x2E, 0x42, 0x6C, 0xD1, 0x6A,
+ 0x40, 0x22, 0xAE, 0x65, 0x46, 0x72, 0x51, 0x33,
+ 0x4A, 0x52, 0x56, 0x4F, 0x99, 0x09, 0x79, 0x00,
+ 0x25, 0x51, 0x43, 0xC9, 0x11, 0x34, 0x91, 0x21,
+ 0x99, 0x39, 0x91, 0x20, 0x9E, 0x3C, 0x91, 0x3A,
+ 0x91, 0x3B, 0x96, 0x38, 0x96, 0x37, 0x96, 0x05,
+ 0x2A, 0x00, 0xDD, 0x55, 0x1F, 0x3C, 0x99, 0x33,
+ 0x95, 0x69, 0x43, 0x75, 0x43, 0x00, 0x22, 0x1A,
+ 0x92, 0x3B, 0x9F, 0x35, 0x9A, 0x97, 0x42, 0x5A,
+ 0xD0, 0x7F, 0x1C, 0x3C, 0x9A, 0x4E, 0x9E, 0x4C,
+ 0x92, 0x72, 0x43, 0xD6, 0x19, 0x72, 0x11, 0xB4,
+ 0x46, 0x92, 0x00, 0x3B, 0x97,
+ 0x00, 0x00, 0x55, 0x00, 0x80, 0x4D, 0x97, 0x22,
+ 0xAE, 0x4B, 0x92, 0xB2, 0x58, 0x66, 0x46, 0xF7,
+ 0x06, 0xFF, 0x0E, 0x01, 0x26, 0xBE, 0x40, 0x4A,
+ 0x92, 0x32, 0x42, 0x41, 0xD1, 0x4A, 0x9A, 0x22,
+ 0xAF, 0x72, 0x40, 0x4B, 0x9E, 0xBA, 0x51, 0x17,
+ 0x4A, 0x66, 0x46, 0x92, 0x57, 0x34, 0x9E, 0x94,
+ 0x46, 0xB2, 0x42, 0x08, 0xDD, 0x50, 0x9A, 0x4C,
+ 0x9E, 0x16, 0x54, 0x50, 0x9A, 0x3B, 0x9E, 0x12,
+ 0x18, 0x56, 0x70, 0x80, 0x1C, 0x0A, 0xE0, 0x30,
+ 0x2C, 0x08, 0xD2, 0x62, 0x00, 0x02, 0xAE, 0x4C,
+ 0x9F, 0xB7, 0x54, 0x92, 0x19, 0x4D, 0x9F, 0x64,
+ 0x1C, 0x57, 0x70, 0xE4, 0xB2, 0x66, 0x46, 0x76,
+ 0x1F, 0x00, 0x2E, 0x1C, 0xDD, 0x33, 0x9A, 0x92,
+ 0x19, 0x33, 0x92, 0x0E, 0xE0, 0x90, 0xDD, 0x00,
+ 0x00, 0x90, 0x00, 0x00, 0x20, 0xF5, 0xCB, 0x00,
+ 0x00, 0x6D, 0x01, 0x00, 0x20, 0x6E, 0x01, 0x00,
+ 0x20, 0x88, 0xDF, 0x00, 0x00,
+ 0x00, 0x00, 0x56, 0x00, 0x80, 0x64, 0x08, 0x00,
+ 0x20, 0x88, 0xE1, 0x3C, 0x9A, 0x72, 0x43, 0x51,
+ 0x18, 0x3B, 0x9A, 0x56, 0x43, 0x75, 0x19, 0x37,
+ 0x9E, 0x96, 0x42, 0x00, 0xD2, 0x37, 0x92, 0x5B,
+ 0x1C, 0x3B, 0x9A, 0x52, 0x1E, 0x3B, 0x92, 0x36,
+ 0x9E, 0x3C, 0x9A, 0xB2, 0x42, 0x4B, 0xD0, 0x52,
+ 0x1C, 0x49, 0x92, 0x4E, 0x9E, 0x3C, 0x92, 0x72,
+ 0x43, 0x3B, 0x9E, 0x48, 0x96, 0x96, 0x19, 0x72,
+ 0x11, 0xB4, 0x46, 0x92, 0x00, 0x22, 0xAE, 0x47,
+ 0x92, 0xB2, 0x58, 0x66, 0x46, 0xF7, 0x06, 0xFF,
+ 0x0E, 0x01, 0x26, 0xBE, 0x40, 0x46, 0x92, 0x32,
+ 0x42, 0x32, 0xD1, 0x46, 0x9A, 0x22, 0xAF, 0x72,
+ 0x40, 0x47, 0x9E, 0xBA, 0x51, 0xFD, 0x4A, 0x66,
+ 0x46, 0x92, 0x57, 0x34, 0x9E, 0x94, 0x46, 0xB2,
+ 0x42, 0x08, 0xDD, 0x50, 0x9A, 0x49, 0x9E, 0x16,
+ 0x54, 0x50, 0x9A, 0x3B, 0x9E, 0x12, 0x18, 0x56,
+ 0x70, 0x80, 0x1C, 0x0A, 0xE0,
+ 0x00, 0x00, 0x57, 0x00, 0x80, 0x30, 0x2C, 0x08,
+ 0xD2, 0x62, 0x00, 0x02, 0xAE, 0x49, 0x9F, 0xB7,
+ 0x54, 0x92, 0x19, 0x48, 0x9F, 0x64, 0x1C, 0x57,
+ 0x70, 0xE4, 0xB2, 0x62, 0x46, 0x52, 0x1F, 0x00,
+ 0x2A, 0x0D, 0xDD, 0x33, 0x9E, 0x17, 0x46, 0xB6,
+ 0x18, 0x33, 0x96, 0x3C, 0x9E, 0x77, 0x43, 0x79,
+ 0x18, 0x3B, 0x9F, 0x7A, 0x43, 0x55, 0x19, 0x39,
+ 0x9A, 0xB2, 0x42, 0x00, 0xD2, 0x39, 0x96, 0x5B,
+ 0x1C, 0x3C, 0x9A, 0x52, 0x1E, 0x3C, 0x92, 0x3B,
+ 0x9F, 0x00, 0x2F, 0x49, 0xD0, 0x44, 0x92, 0x7F,
+ 0x1E, 0x4E, 0x9E, 0x3B, 0x97, 0x72, 0x43, 0xD6,
+ 0x19, 0x72, 0x11, 0xB4, 0x46, 0x92, 0x00, 0x45,
+ 0x97, 0x22, 0xAE, 0x43, 0x92, 0xB2, 0x58, 0x66,
+ 0x46, 0xF7, 0x06, 0xFF, 0x0E, 0x01, 0x26, 0xBE,
+ 0x40, 0x42, 0x92, 0x32, 0x42, 0x31, 0xD1, 0x42,
+ 0x9A, 0x22, 0xAF, 0x72, 0x40, 0x43, 0x9E, 0xBA,
+ 0x51, 0xD6, 0x4A, 0x66, 0x46,
+ 0x00, 0x00, 0x58, 0x00, 0x80, 0x92, 0x57, 0x34,
+ 0x9E, 0x94, 0x46, 0xB2, 0x42, 0x08, 0xDD, 0x50,
+ 0x9A, 0x44, 0x9E, 0x16, 0x54, 0x50, 0x9A, 0x3B,
+ 0x9E, 0x12, 0x18, 0x56, 0x70, 0x80, 0x1C, 0x0A,
+ 0xE0, 0x30, 0x2C, 0x08, 0xD2, 0x62, 0x00, 0x02,
+ 0xAE, 0x44, 0x9F, 0xB7, 0x54, 0x92, 0x19, 0x45,
+ 0x9F, 0x64, 0x1C, 0x57, 0x70, 0xE4, 0xB2, 0x66,
+ 0x46, 0x76, 0x1F, 0x00, 0x2E, 0x0C, 0xDD, 0x33,
+ 0x9A, 0x92, 0x19, 0x33, 0x92, 0x3C, 0x9A, 0x72,
+ 0x43, 0x51, 0x18, 0x3B, 0x9A, 0x56, 0x43, 0x75,
+ 0x19, 0x38, 0x9E, 0x96, 0x42, 0x00, 0xD9, 0x38,
+ 0x92, 0x5B, 0x1C, 0x3B, 0x9A, 0x52, 0x1C, 0x3B,
+ 0x92, 0x3C, 0x9A, 0x00, 0x2A, 0x4B, 0xD0, 0x52,
+ 0x1E, 0x3C, 0x92, 0x4E, 0x9E, 0x41, 0x92, 0x72,
+ 0x43, 0x3B, 0x9E, 0x40, 0x96, 0x96, 0x19, 0x72,
+ 0x11, 0xB4, 0x46, 0x92, 0x00, 0x22, 0xAE, 0x3F,
+ 0x92, 0xB2, 0x58, 0x66, 0x46,
+ 0x00, 0x00, 0x59, 0x00, 0x80, 0xF7, 0x06, 0xFF,
+ 0x0E, 0x01, 0x26, 0xBE, 0x40, 0x3E, 0x92, 0x32,
+ 0x42, 0x32, 0xD1, 0x3E, 0x9A, 0x22, 0xAF, 0x72,
+ 0x40, 0x3F, 0x9E, 0xBA, 0x51, 0xAF, 0x4A, 0x66,
+ 0x46, 0x92, 0x57, 0x34, 0x9E, 0x94, 0x46, 0xB2,
+ 0x42, 0x08, 0xDD, 0x50, 0x9A, 0x41, 0x9E, 0x16,
+ 0x54, 0x50, 0x9A, 0x3B, 0x9E, 0x12, 0x18, 0x56,
+ 0x70, 0x80, 0x1C, 0x0A, 0xE0, 0x30, 0x2C, 0x08,
+ 0xD2, 0x62, 0x00, 0x02, 0xAE, 0x41, 0x9F, 0xB7,
+ 0x54, 0x92, 0x19, 0x40, 0x9F, 0x64, 0x1C, 0x57,
+ 0x70, 0xE4, 0xB2, 0x62, 0x46, 0x52, 0x1F, 0x00,
+ 0x2A, 0x0D, 0xDD, 0x33, 0x9E, 0x17, 0x46, 0xB6,
+ 0x18, 0x33, 0x96, 0x3C, 0x9E, 0x77, 0x43, 0x79,
+ 0x18, 0x3B, 0x9F, 0x7A, 0x43, 0x55, 0x19, 0x3A,
+ 0x9A, 0xB2, 0x42, 0x00, 0xD9, 0x3A, 0x96, 0x5B,
+ 0x1C, 0x3C, 0x9A, 0x52, 0x1C, 0x3C, 0x92, 0x00,
+ 0x28, 0x22, 0xD0, 0x50, 0x9A,
+ 0x00, 0x00, 0x5A, 0x00, 0x80, 0x80, 0x1E, 0x12,
+ 0x56, 0x3C, 0x92, 0x50, 0x9A, 0x01, 0x27, 0x12,
+ 0x18, 0xD7, 0x57, 0x00, 0x22, 0x94, 0x46, 0x3C,
+ 0x9A, 0x3B, 0x97, 0x3D, 0x92, 0x10, 0xE0, 0x52,
+ 0x9A, 0x66, 0x46, 0x92, 0x5D, 0x3D, 0x9E, 0xB2,
+ 0x42, 0x06, 0xD1, 0x52, 0x9A, 0x62, 0x44, 0x52,
+ 0x78, 0xBA, 0x42, 0x01, 0xD1, 0x01, 0x22, 0x1A,
+ 0x92, 0x62, 0x46, 0x92, 0x1C, 0xD2, 0xB2, 0x94,
+ 0x46, 0x51, 0x9E, 0xB4, 0x45, 0xEB, 0xD3, 0x8F,
+ 0xE6, 0x1E, 0x98, 0x98, 0x42, 0x67, 0xD3, 0x1F,
+ 0x9A, 0x32, 0x98, 0x0E, 0x26, 0x72, 0x43, 0xC0,
+ 0x03, 0x81, 0x4E, 0x00, 0x0C, 0xB0, 0x52, 0x00,
+ 0x20, 0x96, 0x19, 0xF0, 0x71, 0x30, 0x72, 0x70,
+ 0x72, 0x1D, 0x9A, 0x9A, 0x42, 0x0A, 0xD3, 0x1A,
+ 0x9A, 0x00, 0x2A, 0x07, 0xD1, 0x21, 0x99, 0x3C,
+ 0x91, 0x20, 0x99, 0x3B, 0x91, 0x20, 0x21, 0xF1,
+ 0x72, 0x30, 0x73, 0x42, 0xE0,
+ 0x00, 0x00, 0x5B, 0x00, 0x80, 0x77, 0x48, 0x40,
+ 0x69, 0x00, 0x28, 0x03, 0xD1, 0x08, 0x46, 0x3C,
+ 0x91, 0x29, 0x46, 0x05, 0x46, 0x74, 0x48, 0x02,
+ 0x69, 0x10, 0x46, 0x48, 0x43, 0x17, 0x46, 0x33,
+ 0x99, 0x09, 0xF0, 0x3B, 0xFE, 0x79, 0x10, 0x40,
+ 0x18, 0x00, 0x12, 0x3C, 0x90, 0x6E, 0x48, 0x33,
+ 0x99, 0x42, 0x69, 0x10, 0x46, 0x17, 0x46, 0x68,
+ 0x43, 0x09, 0xF0, 0x2F, 0xFE, 0x79, 0x10, 0x40,
+ 0x18, 0x00, 0x12, 0x3B, 0x90, 0x3B, 0xA9, 0x3C,
+ 0xA8, 0xFE, 0xF7, 0x4D, 0xFE, 0x01, 0x28, 0x31,
+ 0xD0, 0x64, 0x48, 0x80, 0x69, 0x33, 0x99, 0x50,
+ 0x22, 0x51, 0x43, 0x48, 0x43, 0xC0, 0x0B, 0xFF,
+ 0x21, 0xFF, 0x28, 0x00, 0xD8, 0xC1, 0xB2, 0xB1,
+ 0x71, 0x10, 0x20, 0xF0, 0x72, 0x30, 0x73, 0x3C,
+ 0x98, 0x70, 0x80, 0x3B, 0x98, 0xB0, 0x80, 0x00,
+ 0x96, 0x02, 0xA9, 0x20, 0x46, 0x1B, 0x9B, 0x1C,
+ 0x9A, 0xFF, 0xF7, 0xFD, 0xFC,
+ 0x00, 0x00, 0x5C, 0x00, 0x80, 0x58, 0x49, 0x01,
+ 0x20, 0x88, 0x72, 0x3C, 0x98, 0x70, 0x80, 0x3B,
+ 0x98, 0xB0, 0x80, 0x1F, 0x98, 0x40, 0x1C, 0x1F,
+ 0x90, 0x0B, 0x28, 0x12, 0xD0, 0x0A, 0xE0, 0x51,
+ 0x48, 0x00, 0x79, 0x02, 0x28, 0x03, 0xD1, 0x50,
+ 0x49, 0xC8, 0x78, 0x40, 0x1C, 0xC8, 0x70, 0x4E,
+ 0x49, 0x01, 0x20, 0xC8, 0x72, 0x32, 0x98, 0x80,
+ 0x1C, 0x51, 0x99, 0x32, 0x90, 0x88, 0x42, 0x00,
+ 0xD2, 0xD8, 0xE5, 0x1F, 0x98, 0x53, 0xB0, 0xC0,
+ 0xB2, 0xF0, 0xBD, 0xF3, 0xB5, 0x8E, 0xB0, 0x40,
+ 0x00, 0x00, 0x21, 0x0E, 0x90, 0x44, 0x48, 0x01,
+ 0x91, 0x0A, 0x91, 0x00, 0x79, 0x0D, 0x90, 0x43,
+ 0x48, 0x0A, 0x46, 0x00, 0x78, 0x8C, 0x46, 0x40,
+ 0x1E, 0x0C, 0x90, 0x41, 0x48, 0x00, 0x78, 0x0B,
+ 0x90, 0x40, 0x1E, 0x86, 0x46, 0x00, 0x25, 0x96,
+ 0xE0, 0x0F, 0x99, 0x60, 0x46, 0x0C, 0x5C, 0x08,
+ 0x18, 0x0B, 0x99, 0x40, 0x78,
+ 0x00, 0x00, 0x5D, 0x00, 0x80, 0x61, 0x43, 0x09,
+ 0x18, 0x01, 0x23, 0x00, 0x2C, 0x07, 0xD0, 0x00,
+ 0x28, 0x05, 0xD0, 0x0C, 0x9E, 0xB4, 0x42, 0x02,
+ 0xD0, 0x70, 0x45, 0x00, 0xD0, 0x00, 0x23, 0x00,
+ 0x93, 0x00, 0x23, 0x9E, 0x00, 0x02, 0xAF, 0x5B,
+ 0x1C, 0xBD, 0x51, 0x08, 0x2B, 0xF9, 0xD3, 0x00,
+ 0x9B, 0x00, 0x2B, 0x2C, 0x4B, 0x01, 0xD1, 0x5B,
+ 0x7F, 0x00, 0xE0, 0x9B, 0x7F, 0x27, 0x4E, 0x76,
+ 0x56, 0x73, 0x43, 0xDB, 0x08, 0x9A, 0x18, 0x0D,
+ 0x9B, 0x01, 0x2B, 0x03, 0xD1, 0x23, 0x4B, 0x5B,
+ 0x56, 0x5B, 0x10, 0x9A, 0x18, 0x0C, 0x9B, 0x9C,
+ 0x42, 0x13, 0xD2, 0x0B, 0x9B, 0xCF, 0x18, 0x1F,
+ 0x4B, 0x70, 0x45, 0xDB, 0x57, 0x08, 0x93, 0x04,
+ 0xD2, 0x1C, 0x4B, 0xFB, 0x18, 0x01, 0x26, 0x9E,
+ 0x57, 0x09, 0x96, 0x00, 0x28, 0x05, 0xD0, 0x19,
+ 0x4B, 0xFB, 0x18, 0x20, 0x3B, 0x1F, 0x26, 0x9E,
+ 0x57, 0x07, 0x96, 0x00, 0x2C,
+ 0x00, 0x00, 0x5E, 0x00, 0x80, 0x11, 0xD0, 0x0B,
+ 0x9B, 0x14, 0x4F, 0xCB, 0x1A, 0xFC, 0x56, 0x03,
+ 0x94, 0x70, 0x45, 0x03, 0xD2, 0xDC, 0x19, 0x01,
+ 0x26, 0xA6, 0x57, 0x04, 0x96, 0x00, 0x28, 0x04,
+ 0xD0, 0xDB, 0x19, 0x20, 0x3B, 0x1F, 0x24, 0x1C,
+ 0x57, 0x02, 0x94, 0x70, 0x45, 0x04, 0xD2, 0x0B,
+ 0x4B, 0x5B, 0x18, 0x01, 0x24, 0x1C, 0x57, 0x06,
+ 0x94, 0x00, 0x28, 0x05, 0xD0, 0x07, 0x48, 0x40,
+ 0x18, 0x20, 0x38, 0x1F, 0x21, 0x41, 0x56, 0x05,
+ 0x91, 0x00, 0x99, 0x03, 0x20, 0x00, 0x29, 0x00,
+ 0xD0, 0x02, 0x20, 0x00, 0x23, 0x02, 0xAF, 0x00,
+ 0x90, 0x1F, 0xE0, 0x00, 0x00, 0x64, 0x08, 0x00,
+ 0x20, 0x4C, 0x03, 0x00, 0x20, 0x90, 0xDD, 0x00,
+ 0x00, 0x90, 0x00, 0x00, 0x20, 0x6D, 0x01, 0x00,
+ 0x20, 0x6E, 0x01, 0x00, 0x20, 0x00, 0x21, 0x01,
+ 0x20, 0x84, 0x00, 0x8E, 0x00, 0x3C, 0x59, 0xBE,
+ 0x59, 0xB4, 0x42, 0x00, 0xDD,
+ 0x00, 0x00, 0x5F, 0x00, 0x80, 0x01, 0x46, 0x40,
+ 0x1C, 0x08, 0x28, 0xF5, 0xD3, 0x88, 0x00, 0x39,
+ 0x58, 0x0A, 0x9C, 0x09, 0x19, 0x0A, 0x91, 0x3D,
+ 0x50, 0x5B, 0x1C, 0x00, 0x98, 0x83, 0x42, 0xE9,
+ 0xD3, 0x60, 0x46, 0x80, 0x1C, 0x84, 0x46, 0x0E,
+ 0x99, 0x8C, 0x45, 0x00, 0xD2, 0x64, 0xE7, 0x0A,
+ 0x98, 0x90, 0x42, 0x01, 0xD2, 0x01, 0x20, 0x01,
+ 0x90, 0x0D, 0x98, 0xF9, 0x49, 0x00, 0x28, 0x01,
+ 0x98, 0x08, 0x71, 0x02, 0xD1, 0x00, 0x20, 0x10,
+ 0xB0, 0xF0, 0xBD, 0x01, 0x20, 0xFB, 0xE7, 0xFE,
+ 0xB5, 0x94, 0x46, 0xF3, 0x4A, 0x04, 0x46, 0x50,
+ 0x7A, 0x84, 0x42, 0x58, 0xD0, 0xD3, 0x79, 0x00,
+ 0x93, 0x00, 0x2C, 0x01, 0xD1, 0x18, 0x46, 0x05,
+ 0xE0, 0x00, 0x28, 0x05, 0xD1, 0xED, 0x48, 0xC3,
+ 0x7F, 0x00, 0x98, 0xC0, 0x1A, 0x10, 0x72, 0x4A,
+ 0xE0, 0x84, 0x42, 0x48, 0xD9, 0x00, 0x20, 0x62,
+ 0x06, 0x14, 0x0E, 0x41, 0xE0,
+ 0x00, 0x00, 0x60, 0x00, 0x80, 0x00, 0x22, 0x13,
+ 0x46, 0x01, 0x92, 0xE5, 0x4A, 0x0E, 0x18, 0x52,
+ 0x7A, 0x96, 0x46, 0x10, 0xE0, 0xE4, 0x4A, 0x5D,
+ 0x00, 0x0F, 0x5C, 0x52, 0x5D, 0xBA, 0x1A, 0x52,
+ 0x1C, 0x02, 0x2A, 0x0D, 0xD8, 0xE0, 0x4A, 0x77,
+ 0x78, 0x52, 0x19, 0x52, 0x78, 0xBA, 0x1A, 0x52,
+ 0x1C, 0x02, 0x2A, 0x05, 0xD8, 0x5B, 0x1C, 0x73,
+ 0x45, 0xEC, 0xD3, 0x01, 0x9A, 0x00, 0x2A, 0x22,
+ 0xD0, 0xDA, 0x4B, 0x0A, 0x5C, 0x1B, 0x78, 0x5A,
+ 0x43, 0x73, 0x78, 0xD2, 0x18, 0xD8, 0x4B, 0x9B,
+ 0x56, 0x00, 0x9A, 0x93, 0x42, 0x17, 0xDA, 0x03,
+ 0x46, 0x82, 0x1C, 0x0F, 0xE0, 0x8D, 0x5C, 0xCD,
+ 0x54, 0x8D, 0x18, 0x6D, 0x78, 0xCE, 0x18, 0x75,
+ 0x70, 0x56, 0x08, 0x76, 0x00, 0x65, 0x46, 0xAD,
+ 0x5B, 0x5E, 0x08, 0x76, 0x00, 0x67, 0x46, 0x9B,
+ 0x1C, 0xBD, 0x53, 0x92, 0x1C, 0xA2, 0x42, 0xED,
+ 0xD3, 0xA4, 0x1E, 0xE4, 0xB2,
+ 0x00, 0x00, 0x61, 0x00, 0x80, 0x00, 0xE0, 0x80,
+ 0x1C, 0xA0, 0x42, 0xBB, 0xD3, 0x64, 0x08, 0x62,
+ 0x00, 0xC5, 0x48, 0x09, 0xF0, 0x47, 0xFC, 0x20,
+ 0x46, 0xFE, 0xBD, 0xFF, 0xB5, 0xC0, 0x4A, 0x99,
+ 0xB0, 0x00, 0x20, 0xD0, 0x70, 0x16, 0x90, 0x17,
+ 0x90, 0xC2, 0x48, 0x0E, 0x46, 0x00, 0x78, 0x40,
+ 0x1E, 0x14, 0x90, 0xBE, 0x48, 0x00, 0x78, 0x13,
+ 0x90, 0x10, 0x7A, 0x15, 0x90, 0xB2, 0xE0, 0x13,
+ 0x98, 0x1C, 0x99, 0x70, 0x43, 0x49, 0x1E, 0x47,
+ 0x18, 0x1C, 0x9D, 0xA3, 0xE0, 0xB8, 0x49, 0x7F,
+ 0x1C, 0xC8, 0x57, 0x15, 0x9A, 0x90, 0x42, 0x7E,
+ 0xDB, 0x13, 0x9A, 0x01, 0x21, 0x52, 0x1E, 0x04,
+ 0x46, 0x95, 0x42, 0x00, 0xD3, 0x00, 0x21, 0x14,
+ 0x9A, 0x96, 0x42, 0x1D, 0xD2, 0x13, 0x9A, 0xBB,
+ 0x18, 0x5B, 0x1C, 0x00, 0x29, 0x06, 0xD0, 0xAE,
+ 0x4A, 0xD2, 0x56, 0x90, 0x42, 0xEB, 0xDB, 0x00,
+ 0x2A, 0x00, 0xDD, 0x14, 0x19,
+ 0x00, 0x00, 0x62, 0x00, 0x80, 0xAA, 0x4A, 0x5B,
+ 0x1E, 0xD2, 0x56, 0x90, 0x42, 0x63, 0xDB, 0x00,
+ 0x2A, 0x00, 0xDD, 0x14, 0x19, 0x00, 0x2D, 0x07,
+ 0xD0, 0xA5, 0x4A, 0x5B, 0x1E, 0xD2, 0x56, 0x90,
+ 0x42, 0x77, 0xDB, 0x00, 0x2A, 0x00, 0xDD, 0x14,
+ 0x19, 0x00, 0x29, 0x08, 0xD0, 0xA0, 0x4A, 0xD3,
+ 0x19, 0x01, 0x22, 0x9A, 0x56, 0x90, 0x42, 0x6C,
+ 0xDB, 0x00, 0x2A, 0x00, 0xDD, 0x14, 0x19, 0x00,
+ 0x2D, 0x09, 0xD0, 0x9B, 0x4A, 0xD3, 0x19, 0x20,
+ 0x3B, 0x1F, 0x22, 0x9A, 0x56, 0x90, 0x42, 0x60,
+ 0xDD, 0x00, 0x2A, 0x00, 0xDD, 0x14, 0x19, 0x00,
+ 0x2E, 0x1D, 0xD0, 0x13, 0x9A, 0xBB, 0x1A, 0x5B,
+ 0x1C, 0x00, 0x29, 0x06, 0xD0, 0x92, 0x4A, 0xD2,
+ 0x56, 0x90, 0x42, 0x52, 0xDD, 0x00, 0x2A, 0x00,
+ 0xDD, 0x14, 0x19, 0x8F, 0x4A, 0x5B, 0x1E, 0xD2,
+ 0x56, 0x90, 0x42, 0x4A, 0xDD, 0x00, 0x2A, 0x00,
+ 0xDD, 0x14, 0x19, 0x00, 0x2D,
+ 0x00, 0x00, 0x63, 0x00, 0x80, 0x07, 0xD0, 0x8A,
+ 0x4A, 0x5B, 0x1E, 0xD2, 0x56, 0x90, 0x42, 0x40,
+ 0xDD, 0x00, 0x2A, 0x00, 0xDD, 0x14, 0x19, 0x01,
+ 0x20, 0x00, 0x2D, 0x02, 0xD0, 0x00, 0x29, 0x00,
+ 0xD0, 0x00, 0x20, 0x00, 0x2E, 0x02, 0xD0, 0x14,
+ 0x99, 0x8E, 0x42, 0x00, 0xD1, 0x40, 0x1C, 0x7C,
+ 0x4A, 0x15, 0x99, 0x52, 0x79, 0x91, 0x40, 0x01,
+ 0x41, 0xA1, 0x42, 0x2A, 0xDC, 0xFE, 0xF7, 0xC9,
+ 0xF9, 0x01, 0x28, 0x16, 0xD1, 0x7C, 0x48, 0x00,
+ 0x78, 0xC1, 0x07, 0x07, 0xD0, 0x7B, 0x49, 0x75,
+ 0x4A, 0x49, 0x57, 0x12, 0x89, 0x00, 0xE0, 0x1C,
+ 0xE0, 0x91, 0x42, 0x1A, 0xDB, 0x80, 0x07, 0x08,
+ 0xD5, 0x72, 0x48, 0x76, 0x49, 0x00, 0x78, 0x80,
+ 0x19, 0x08, 0x56, 0x6E, 0x49, 0x09, 0x89, 0x88,
+ 0x42, 0x0F, 0xDB, 0x6F, 0x48, 0x02, 0xAA, 0xC0,
+ 0x57, 0x21, 0x1A, 0x16, 0x98, 0x40, 0x00, 0x11,
+ 0x52, 0x0B, 0xA9, 0x0E, 0x54,
+ 0x00, 0x00, 0x64, 0x00, 0x80, 0x40, 0x18, 0x45,
+ 0x70, 0x16, 0x98, 0x40, 0x1C, 0x16, 0x90, 0x10,
+ 0x28, 0x0C, 0xD0, 0x6D, 0x1C, 0x22, 0x98, 0x85,
+ 0x42, 0x00, 0xD8, 0x57, 0xE7, 0x16, 0x98, 0x10,
+ 0x28, 0x04, 0xD0, 0x76, 0x1C, 0x1B, 0x98, 0x86,
+ 0x42, 0x00, 0xD8, 0x48, 0xE7, 0x5D, 0x4C, 0xE0,
+ 0x7F, 0x00, 0x28, 0x16, 0x98, 0x00, 0xD1, 0x05,
+ 0xE0, 0xC0, 0xB2, 0x02, 0xAA, 0x0B, 0xA9, 0xFF,
+ 0xF7, 0xC6, 0xFE, 0x16, 0x90, 0x00, 0x28, 0x7E,
+ 0xD0, 0x0B, 0xA9, 0xFF, 0xF7, 0xFE, 0xFD, 0x21,
+ 0x79, 0x00, 0x29, 0x07, 0xD0, 0x00, 0x28, 0x05,
+ 0xD1, 0x0B, 0xAA, 0x16, 0x99, 0x19, 0x98, 0xFF,
+ 0xF7, 0x7B, 0xFB, 0x23, 0xE0, 0x4E, 0x49, 0x00,
+ 0x20, 0x88, 0x72, 0xC8, 0x72, 0x16, 0x99, 0x0B,
+ 0x20, 0x0B, 0x29, 0x00, 0xD8, 0x08, 0x46, 0x00,
+ 0x22, 0x16, 0xE0, 0x11, 0x46, 0x0E, 0x26, 0x71,
+ 0x43, 0x49, 0x4E, 0x53, 0x00,
+ 0x00, 0x00, 0x65, 0x00, 0x80, 0x0B, 0xAD, 0xEC,
+ 0x5C, 0x0F, 0x46, 0x9A, 0x3E, 0x89, 0x19, 0x4C,
+ 0x80, 0x5B, 0x19, 0x5B, 0x78, 0x8B, 0x80, 0x20,
+ 0x23, 0xCB, 0x72, 0x00, 0x23, 0x0B, 0x73, 0xF2,
+ 0x53, 0xCB, 0x71, 0x0B, 0x72, 0x4B, 0x72, 0x52,
+ 0x1C, 0x82, 0x42, 0xE6, 0xD3, 0x3C, 0x4C, 0x3D,
+ 0x49, 0xA3, 0x78, 0x20, 0x31, 0x00, 0x22, 0x18,
+ 0x91, 0x00, 0x2B, 0x00, 0xD0, 0x8A, 0x78, 0x00,
+ 0x21, 0x06, 0xE0, 0x39, 0x4E, 0x0E, 0x25, 0x4D,
+ 0x43, 0x9A, 0x3E, 0xAD, 0x19, 0xAA, 0x72, 0x49,
+ 0x1C, 0x81, 0x42, 0xF6, 0xD3, 0xA1, 0x79, 0x00,
+ 0x29, 0x7D, 0xD0, 0x83, 0x42, 0x7B, 0xD0, 0x31,
+ 0x49, 0x40, 0x31, 0x89, 0x7B, 0x01, 0x91, 0x64,
+ 0x29, 0x01, 0xDD, 0x64, 0x21, 0x01, 0x91, 0x00,
+ 0x25, 0x6F, 0xE0, 0x2D, 0x4A, 0x0E, 0x21, 0x69,
+ 0x43, 0x9A, 0x3A, 0x51, 0x5A, 0x02, 0xAB, 0x49,
+ 0x00, 0x5F, 0x5E, 0x0B, 0xAC,
+ 0x00, 0x00, 0x66, 0x00, 0x80, 0x09, 0x19, 0x49,
+ 0x78, 0x0A, 0x91, 0x2E, 0x46, 0x00, 0x21, 0x18,
+ 0xE0, 0xA9, 0x42, 0x15, 0xD0, 0x24, 0x4B, 0x0E,
+ 0x22, 0x4A, 0x43, 0x9A, 0x3B, 0x9A, 0x5A, 0x54,
+ 0x00, 0x0B, 0xAA, 0xA2, 0x18, 0x53, 0x78, 0x0A,
+ 0x9A, 0xD2, 0x1A, 0x00, 0xD5, 0x52, 0x42, 0x04,
+ 0x2A, 0x06, 0xDA, 0x02, 0xAA, 0x12, 0x5F, 0xBA,
+ 0x42, 0x02, 0xDD, 0x17, 0x46, 0x0E, 0x46, 0x0A,
+ 0x93, 0x49, 0x1C, 0x81, 0x42, 0x00, 0xE0, 0x4C,
+ 0xE0, 0xE2, 0xD3, 0x00, 0x24, 0x3E, 0xE0, 0xB4,
+ 0x42, 0x3B, 0xD0, 0x21, 0x46, 0x0E, 0x22, 0x51,
+ 0x43, 0x13, 0x4A, 0x9A, 0x3A, 0x52, 0x5A, 0x53,
+ 0x00, 0x0B, 0xAA, 0x9A, 0x18, 0x9C, 0x46, 0x52,
+ 0x78, 0x0A, 0x9B, 0x9A, 0x1A, 0x00, 0xD5, 0x52,
+ 0x42, 0x04, 0x2A, 0x2A, 0xDA, 0x62, 0x46, 0x02,
+ 0xAB, 0x9A, 0x5E, 0x64, 0x23, 0x5A, 0x43, 0x01,
+ 0x9B, 0x7B, 0x43, 0x9A, 0x42,
+ 0x00, 0x00, 0x67, 0x00, 0x80, 0x1C, 0xDA, 0x01,
+ 0x46, 0x20, 0x46, 0xFE, 0xF7, 0x5B, 0xFB, 0xB4,
+ 0x42, 0x00, 0xD2, 0x76, 0x1E, 0xAC, 0x42, 0x00,
+ 0xD2, 0x6D, 0x1E, 0x64, 0x1E, 0x15, 0xE0, 0x1A,
+ 0xE0, 0x90, 0x00, 0x00, 0x20, 0x90, 0xDD, 0x00,
+ 0x00, 0xE6, 0x03, 0x00, 0x20, 0x6E, 0x01, 0x00,
+ 0x20, 0x64, 0x08, 0x00, 0x20, 0x6D, 0x01, 0x00,
+ 0x20, 0xC1, 0x01, 0x00, 0x20, 0x5E, 0x0A, 0x00,
+ 0x20, 0x18, 0x9A, 0x92, 0x7A, 0x20, 0x4B, 0xC9,
+ 0x18, 0x8A, 0x72, 0x64, 0x1C, 0x84, 0x42, 0xBE,
+ 0xD3, 0x6D, 0x1C, 0x85, 0x42, 0x8D, 0xD3, 0x0B,
+ 0xAA, 0x19, 0x9B, 0x16, 0x99, 0xFE, 0xF7, 0xAC,
+ 0xFE, 0x17, 0x90, 0x1A, 0x49, 0x16, 0x98, 0x48,
+ 0x72, 0x17, 0x98, 0x88, 0x70, 0x1D, 0xB0, 0xF0,
+ 0xBD, 0x08, 0xB5, 0x17, 0x49, 0x09, 0x78, 0x49,
+ 0x1E, 0xCA, 0xB2, 0x16, 0x49, 0x00, 0x92, 0x09,
+ 0x78, 0x49, 0x1E, 0xCA, 0xB2,
+ 0x00, 0x00, 0x68, 0x00, 0x80, 0x00, 0x21, 0x0B,
+ 0x46, 0xFF, 0xF7, 0x47, 0xFE, 0x08, 0xBD, 0x0F,
+ 0x49, 0x00, 0x28, 0x03, 0xD0, 0x03, 0x28, 0x02,
+ 0xD1, 0x0F, 0x48, 0x00, 0x7F, 0x88, 0x71, 0x70,
+ 0x47, 0x02, 0x46, 0x00, 0x20, 0x01, 0x21, 0xC9,
+ 0x03, 0x00, 0xE0, 0x49, 0x08, 0x91, 0x42, 0xFC,
+ 0xD8, 0x06, 0xE0, 0x40, 0x18, 0x03, 0x46, 0x43,
+ 0x43, 0x93, 0x42, 0x00, 0xD9, 0x40, 0x1A, 0x49,
+ 0x08, 0x00, 0x29, 0xF6, 0xD1, 0x70, 0x47, 0x00,
+ 0x00, 0x4C, 0x03, 0x00, 0x20, 0x90, 0x00, 0x00,
+ 0x20, 0x6E, 0x01, 0x00, 0x20, 0x6D, 0x01, 0x00,
+ 0x20, 0x90, 0xDD, 0x00, 0x00, 0xF8, 0xB5, 0x47,
+ 0x49, 0x0A, 0x78, 0x47, 0x48, 0x20, 0x25, 0x24,
+ 0x2A, 0x03, 0xD3, 0x4A, 0x78, 0xC2, 0x61, 0x89,
+ 0x78, 0x1C, 0xE0, 0xCA, 0x78, 0x24, 0x2A, 0x03,
+ 0xD3, 0x0A, 0x79, 0xC2, 0x61, 0x49, 0x79, 0x15,
+ 0xE0, 0x8A, 0x79, 0x24, 0x2A,
+ 0x00, 0x00, 0x69, 0x00, 0x80, 0x03, 0xD3, 0xCA,
+ 0x79, 0xC2, 0x61, 0x09, 0x7A, 0x0E, 0xE0, 0x4A,
+ 0x7A, 0x24, 0x2A, 0x03, 0xD3, 0x8A, 0x7A, 0xC2,
+ 0x61, 0xC9, 0x7A, 0x07, 0xE0, 0x0A, 0x7B, 0x00,
+ 0x2A, 0x02, 0xD0, 0x0A, 0x7B, 0xC2, 0x61, 0x00,
+ 0xE0, 0xC5, 0x61, 0x49, 0x7B, 0x01, 0x62, 0x01,
+ 0x26, 0x34, 0x4C, 0xB6, 0x04, 0x26, 0x60, 0x31,
+ 0x48, 0x20, 0x30, 0x40, 0x7C, 0x32, 0x4F, 0x78,
+ 0x60, 0x05, 0x20, 0x00, 0xF0, 0x75, 0xF8, 0x27,
+ 0x20, 0xB8, 0x60, 0x30, 0x48, 0x05, 0x60, 0x10,
+ 0x21, 0x81, 0x60, 0xC1, 0x60, 0x00, 0x06, 0xE0,
+ 0x60, 0x60, 0x60, 0x26, 0x60, 0x2C, 0x49, 0x40,
+ 0x1C, 0x08, 0x60, 0x2B, 0x49, 0x2B, 0x48, 0x40,
+ 0x31, 0x08, 0x60, 0xF8, 0xBD, 0xF8, 0xB5, 0x72,
+ 0xB6, 0x00, 0x24, 0x29, 0x4E, 0x06, 0x20, 0x60,
+ 0x43, 0x85, 0x19, 0x28, 0x46, 0x09, 0xF0, 0x73,
+ 0xFA, 0x69, 0x79, 0x2A, 0x79,
+ 0x00, 0x00, 0x6A, 0x00, 0x80, 0x09, 0x02, 0x11,
+ 0x43, 0x09, 0xF0, 0x69, 0xFA, 0x64, 0x1C, 0xE4,
+ 0xB2, 0x02, 0x2C, 0xEF, 0xD3, 0x20, 0x4F, 0x00,
+ 0x21, 0x3F, 0x1F, 0x0A, 0x46, 0x3D, 0x1F, 0x90,
+ 0x00, 0x3B, 0x58, 0x1E, 0x0A, 0xD8, 0xB2, 0x36,
+ 0x02, 0x05, 0xE0, 0x4B, 0x00, 0x5C, 0x19, 0xEB,
+ 0x5C, 0x64, 0x78, 0xF4, 0x54, 0x49, 0x1C, 0x03,
+ 0x46, 0x40, 0x1E, 0xC0, 0xB2, 0x00, 0x2B, 0xF4,
+ 0xD1, 0x52, 0x1C, 0xEC, 0xD0, 0x15, 0x48, 0x02,
+ 0x22, 0x02, 0x60, 0x15, 0x48, 0x30, 0x21, 0x01,
+ 0x60, 0x51, 0x03, 0x81, 0x60, 0x81, 0x15, 0xC1,
+ 0x60, 0x13, 0x48, 0x12, 0x49, 0x01, 0x60, 0x45,
+ 0x21, 0x49, 0x04, 0x41, 0x60, 0x11, 0x48, 0x01,
+ 0x78, 0x11, 0x43, 0x01, 0x70, 0x01, 0x78, 0x06,
+ 0x22, 0x11, 0x43, 0x01, 0x70, 0xFF, 0xF7, 0x72,
+ 0xFF, 0xF8, 0xBD, 0x00, 0x00, 0xC0, 0xF1, 0xFF,
+ 0x0F, 0x00, 0xFF, 0x00, 0x40,
+ 0x00, 0x00, 0x6B, 0x00, 0x80, 0x00, 0x00, 0x01,
+ 0x40, 0x00, 0xFF, 0x01, 0x40, 0x80, 0x02, 0x01,
+ 0x40, 0x00, 0x01, 0x01, 0x40, 0x32, 0x00, 0x00,
+ 0x80, 0x04, 0xCC, 0x00, 0x00, 0x00, 0x20, 0x14,
+ 0x40, 0x00, 0x00, 0x14, 0x40, 0x04, 0x00, 0x09,
+ 0x00, 0x00, 0x50, 0x13, 0x40, 0x00, 0x70, 0x13,
+ 0x40, 0x10, 0xB5, 0x2E, 0x49, 0x09, 0x78, 0x48,
+ 0x43, 0x06, 0xF0, 0x08, 0xFA, 0x10, 0xBD, 0x00,
+ 0xBE, 0x70, 0x47, 0x01, 0x22, 0x52, 0x07, 0x10,
+ 0x28, 0x00, 0xD3, 0x00, 0xBE, 0x83, 0x00, 0xD0,
+ 0x58, 0xD1, 0x50, 0x70, 0x47, 0x01, 0x22, 0x52,
+ 0x07, 0x10, 0x28, 0x00, 0xD3, 0x00, 0xBE, 0x80,
+ 0x00, 0x82, 0x18, 0x10, 0x6C, 0x11, 0x64, 0x70,
+ 0x47, 0x03, 0x29, 0x00, 0xD9, 0x00, 0xBE, 0x10,
+ 0x28, 0x00, 0xD3, 0x00, 0xBE, 0x82, 0x07, 0xD2,
+ 0x0E, 0x92, 0x1D, 0x91, 0x40, 0x80, 0x08, 0x1C,
+ 0x4A, 0x80, 0x00, 0x80, 0x18,
+ 0x00, 0x00, 0x6C, 0x00, 0x80, 0x01, 0x60, 0x70,
+ 0x47, 0x02, 0x07, 0x1A, 0x49, 0x12, 0x0F, 0x01,
+ 0x20, 0x90, 0x40, 0x08, 0x60, 0x70, 0x47, 0x17,
+ 0x49, 0x02, 0x07, 0x80, 0x31, 0x12, 0x0F, 0x01,
+ 0x20, 0x90, 0x40, 0x08, 0x60, 0x70, 0x47, 0x02,
+ 0x07, 0x13, 0x49, 0x12, 0x0F, 0x01, 0x20, 0x90,
+ 0x40, 0x08, 0x60, 0x70, 0x47, 0x12, 0x49, 0x11,
+ 0x48, 0xC8, 0x60, 0x70, 0x47, 0x70, 0xB5, 0x0B,
+ 0x4D, 0x00, 0x28, 0x00, 0xD1, 0x0F, 0x48, 0x10,
+ 0x49, 0x04, 0x46, 0x68, 0x60, 0x48, 0x1E, 0x20,
+ 0x18, 0x09, 0xF0, 0xD9, 0xF9, 0x7D, 0x21, 0x28,
+ 0x70, 0xC9, 0x00, 0x48, 0x1E, 0x20, 0x18, 0x09,
+ 0xF0, 0xD2, 0xF9, 0xA8, 0x60, 0xC0, 0x03, 0xE8,
+ 0x60, 0x70, 0xBD, 0x00, 0x00, 0xB8, 0x00, 0x00,
+ 0x20, 0x00, 0xE4, 0x00, 0xE0, 0x00, 0xE1, 0x00,
+ 0xE0, 0x80, 0xE2, 0x00, 0xE0, 0x04, 0x00, 0xFA,
+ 0x05, 0x00, 0xED, 0x00, 0xE0,
+ 0x00, 0x00, 0x6D, 0x00, 0x80, 0x00, 0x51, 0x25,
+ 0x02, 0x40, 0x42, 0x0F, 0x00, 0x10, 0xB5, 0xFF,
+ 0x20, 0xFF, 0xF7, 0x95, 0xFF, 0x10, 0xBD, 0x70,
+ 0xB5, 0x06, 0xF0, 0xA0, 0xF9, 0x0D, 0x4A, 0x11,
+ 0x68, 0x03, 0x23, 0x9B, 0x03, 0x01, 0x24, 0x99,
+ 0x43, 0xA4, 0x03, 0x0C, 0x43, 0x14, 0x60, 0x01,
+ 0x24, 0xE4, 0x03, 0x0C, 0x43, 0x14, 0x60, 0x09,
+ 0x4D, 0x07, 0x4C, 0x2C, 0x61, 0x08, 0x4D, 0x04,
+ 0x24, 0x2C, 0x60, 0x19, 0x43, 0x11, 0x60, 0x06,
+ 0xF0, 0x8D, 0xF9, 0x06, 0x49, 0x01, 0x20, 0x08,
+ 0x70, 0x70, 0xBD, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x40, 0x05, 0x01, 0x01, 0x00, 0x00, 0x04, 0x01,
+ 0x40, 0x80, 0xE2, 0x00, 0xE0, 0xCA, 0x00, 0x00,
+ 0x20, 0x70, 0xB5, 0x05, 0xF0, 0xF3, 0xFF, 0x01,
+ 0x25, 0x6D, 0x02, 0x28, 0x46, 0x06, 0xF0, 0x18,
+ 0xF8, 0x05, 0xF0, 0xE1, 0xFF, 0x03, 0x24, 0xA0,
+ 0xB2, 0x00, 0x21, 0x06, 0xF0,
+ 0x00, 0x00, 0x6E, 0x00, 0x80, 0x1E, 0xF8, 0x64,
+ 0x1C, 0xAC, 0x42, 0xF8, 0xD3, 0x40, 0x21, 0x02,
+ 0x20, 0x06, 0xF0, 0x17, 0xF8, 0xFF, 0x49, 0x00,
+ 0x20, 0x08, 0x70, 0x70, 0xBD, 0xFF, 0xB5, 0x87,
+ 0xB0, 0x13, 0xAB, 0x84, 0x46, 0x38, 0xCB, 0x00,
+ 0x20, 0x02, 0x46, 0x01, 0x90, 0xFA, 0x48, 0x06,
+ 0x90, 0xA0, 0xE0, 0x16, 0x98, 0x09, 0x99, 0x50,
+ 0x43, 0x40, 0x18, 0x80, 0xB2, 0x00, 0x90, 0x60,
+ 0x46, 0x03, 0x28, 0x02, 0xD1, 0x50, 0x08, 0xC0,
+ 0x18, 0x00, 0xE0, 0x98, 0x18, 0x16, 0x21, 0x48,
+ 0x43, 0xF2, 0x49, 0x0E, 0x5A, 0x40, 0x18, 0xF6,
+ 0xB2, 0x03, 0x96, 0x80, 0x78, 0x02, 0x90, 0x02,
+ 0x99, 0x01, 0x98, 0x40, 0x18, 0xC0, 0xB2, 0x01,
+ 0x90, 0x60, 0x46, 0x01, 0x28, 0x07, 0xD1, 0x06,
+ 0x98, 0x00, 0x6A, 0x03, 0x28, 0x03, 0xD1, 0x01,
+ 0x98, 0x40, 0x18, 0xC0, 0xB2, 0x01, 0x90, 0x00,
+ 0x21, 0x01, 0x20, 0x03, 0x9E,
+ 0x00, 0x00, 0x6F, 0x00, 0x80, 0x88, 0x40, 0x30,
+ 0x42, 0x6E, 0xD0, 0x60, 0x46, 0x00, 0x28, 0x0E,
+ 0xD1, 0x00, 0x98, 0xC6, 0x00, 0x80, 0x19, 0x40,
+ 0x19, 0x40, 0x18, 0x07, 0x7B, 0x16, 0x20, 0x16,
+ 0x46, 0x46, 0x43, 0xDE, 0x48, 0x30, 0x18, 0x40,
+ 0x18, 0x00, 0x79, 0x27, 0x54, 0x5C, 0xE0, 0x60,
+ 0x46, 0x01, 0x28, 0x3E, 0xD1, 0xD8, 0x48, 0x40,
+ 0x38, 0x86, 0x69, 0xC0, 0x69, 0x30, 0x18, 0xC0,
+ 0xB2, 0x86, 0x46, 0x06, 0x98, 0x00, 0x6A, 0x02,
+ 0x28, 0x03, 0xD0, 0x06, 0x98, 0x00, 0x6A, 0x03,
+ 0x28, 0x1E, 0xD1, 0x11, 0x98, 0x10, 0x18, 0xC6,
+ 0x00, 0x80, 0x19, 0x40, 0x19, 0x40, 0x18, 0x05,
+ 0x90, 0x06, 0x7B, 0x98, 0x18, 0x16, 0x27, 0x78,
+ 0x43, 0xCC, 0x4F, 0xC0, 0x19, 0x40, 0x18, 0x04,
+ 0x90, 0x00, 0x79, 0x77, 0x46, 0xC0, 0x1B, 0x26,
+ 0x54, 0x06, 0x98, 0x00, 0x6A, 0x03, 0x28, 0x33,
+ 0xD1, 0x05, 0x98, 0x46, 0x7D,
+ 0x00, 0x00, 0x70, 0x00, 0x80, 0x04, 0x98, 0x00,
+ 0x79, 0xC7, 0x1B, 0x02, 0x98, 0x38, 0x18, 0x2A,
+ 0xE0, 0x11, 0x98, 0x10, 0x18, 0xC6, 0x00, 0x80,
+ 0x19, 0x40, 0x19, 0x40, 0x18, 0x46, 0x7D, 0x98,
+ 0x18, 0x16, 0x27, 0x78, 0x43, 0xBD, 0x4F, 0xC0,
+ 0x19, 0x40, 0x18, 0x00, 0x79, 0x77, 0x46, 0xC0,
+ 0x1B, 0x19, 0xE0, 0x60, 0x46, 0x02, 0x28, 0x11,
+ 0x98, 0x07, 0xD1, 0x10, 0x18, 0xC6, 0x00, 0x80,
+ 0x19, 0x40, 0x19, 0x40, 0x18, 0x06, 0x7B, 0x9F,
+ 0x18, 0x07, 0xE0, 0x10, 0x18, 0xC6, 0x00, 0x80,
+ 0x19, 0x40, 0x19, 0x40, 0x18, 0x06, 0x7B, 0x50,
+ 0x08, 0xC7, 0x18, 0x16, 0x20, 0x47, 0x43, 0xAF,
+ 0x48, 0x38, 0x18, 0x40, 0x18, 0x00, 0x79, 0x26,
+ 0x54, 0x49, 0x1C, 0x89, 0xB2, 0x08, 0x29, 0x87,
+ 0xD3, 0x52, 0x1C, 0x92, 0xB2, 0x12, 0x98, 0x82,
+ 0x42, 0x00, 0xD2, 0x5A, 0xE7, 0x0A, 0x99, 0x10,
+ 0x98, 0x00, 0x25, 0x0E, 0x18,
+ 0x00, 0x00, 0x71, 0x00, 0x80, 0x14, 0xE0, 0x08,
+ 0x98, 0x0A, 0x99, 0x00, 0x88, 0x88, 0x42, 0x08,
+ 0xD3, 0xB0, 0x42, 0x06, 0xD2, 0x0A, 0x9A, 0x61,
+ 0x5D, 0x80, 0x1A, 0x08, 0x30, 0x80, 0xB2, 0x05,
+ 0xF0, 0x50, 0xFF, 0x08, 0x98, 0x08, 0x99, 0x00,
+ 0x88, 0x40, 0x1C, 0x6D, 0x1C, 0x08, 0x80, 0xAD,
+ 0xB2, 0x01, 0x98, 0x85, 0x42, 0xE7, 0xD3, 0x0B,
+ 0xB0, 0xF0, 0xBD, 0xF1, 0xB5, 0x9E, 0xB0, 0x00,
+ 0x20, 0x1D, 0x90, 0x1B, 0x90, 0x03, 0x20, 0x05,
+ 0xF0, 0x40, 0xFF, 0x04, 0x02, 0x04, 0x20, 0x05,
+ 0xF0, 0x3C, 0xFF, 0x04, 0x43, 0x05, 0x20, 0x05,
+ 0xF0, 0x38, 0xFF, 0x06, 0x02, 0x06, 0x20, 0x05,
+ 0xF0, 0x34, 0xFF, 0x06, 0x43, 0x1E, 0x98, 0x8E,
+ 0x4D, 0x04, 0x28, 0x03, 0xD1, 0x01, 0x21, 0x28,
+ 0x46, 0x89, 0x02, 0x04, 0xE0, 0x05, 0x28, 0x03,
+ 0xD1, 0x89, 0x48, 0x01, 0x21, 0xC9, 0x02, 0x45,
+ 0x18, 0xFF, 0x20, 0xF9, 0x30,
+ 0x00, 0x00, 0x72, 0x00, 0x80, 0x86, 0x42, 0x00,
+ 0xD8, 0x30, 0x46, 0x83, 0x4F, 0x1A, 0x90, 0xF8,
+ 0x69, 0x02, 0x28, 0x84, 0x48, 0x04, 0xD1, 0x00,
+ 0x78, 0xC0, 0x1C, 0x86, 0x08, 0xB6, 0x00, 0x00,
+ 0xE0, 0x06, 0x78, 0x00, 0x20, 0x1D, 0x90, 0x7C,
+ 0x48, 0x1E, 0x9B, 0x40, 0x38, 0x09, 0xF0, 0x55,
+ 0xF9, 0x06, 0x04, 0x2D, 0x57, 0x83, 0x04, 0x04,
+ 0x8B, 0xC0, 0x6A, 0x80, 0xB2, 0x19, 0x90, 0x00,
+ 0x20, 0x18, 0x90, 0x1C, 0x90, 0x00, 0x2C, 0x03,
+ 0xD1, 0xA9, 0x78, 0x08, 0x20, 0x05, 0xF0, 0xF9,
+ 0xFE, 0x10, 0xAB, 0x98, 0x8E, 0x40, 0x1C, 0x00,
+ 0x27, 0x1D, 0x90, 0x11, 0xE0, 0x0E, 0xA8, 0x04,
+ 0xA9, 0x61, 0xC1, 0x1C, 0x98, 0x18, 0x9A, 0x19,
+ 0x99, 0x01, 0xAB, 0x07, 0xC3, 0x1A, 0x9A, 0x00,
+ 0x92, 0x23, 0x46, 0x3A, 0x46, 0x1D, 0xA9, 0x00,
+ 0x20, 0xFF, 0xF7, 0xD0, 0xFE, 0x7F, 0x1C, 0xBF,
+ 0xB2, 0x68, 0x48, 0x00, 0x78,
+ 0x00, 0x00, 0x73, 0x00, 0x80, 0x87, 0x42, 0xE9,
+ 0xD3, 0x5F, 0xE0, 0x01, 0x6B, 0x42, 0x6B, 0x89,
+ 0x18, 0x89, 0xB2, 0x19, 0x91, 0x00, 0x21, 0x18,
+ 0x91, 0xC0, 0x6A, 0x70, 0x43, 0x87, 0xB2, 0x00,
+ 0x2C, 0x04, 0xD1, 0xE9, 0x78, 0x08, 0x20, 0x05,
+ 0xF0, 0xCC, 0xFE, 0x01, 0xE0, 0x01, 0x2C, 0x03,
+ 0xD8, 0x29, 0x79, 0x09, 0x20, 0x05, 0xF0, 0xC5,
+ 0xFE, 0x10, 0xAB, 0x98, 0x8E, 0x04, 0xA9, 0x80,
+ 0x1C, 0x1D, 0x90, 0x07, 0xA8, 0x61, 0xC1, 0x18,
+ 0x9A, 0x19, 0x99, 0x01, 0x97, 0x03, 0x92, 0x1A,
+ 0x9A, 0x00, 0x92, 0x02, 0x91, 0x00, 0x22, 0x23,
+ 0x46, 0x1D, 0xA9, 0x02, 0x20, 0x28, 0xE0, 0xC1,
+ 0x6B, 0x89, 0xB2, 0x19, 0x91, 0x00, 0x21, 0x18,
+ 0x91, 0xC1, 0x6A, 0x80, 0x6B, 0x71, 0x43, 0x08,
+ 0x18, 0x87, 0xB2, 0x00, 0x2C, 0x04, 0xD1, 0x69,
+ 0x79, 0x08, 0x20, 0x05, 0xF0, 0xA2, 0xFE, 0x01,
+ 0xE0, 0x01, 0x2C, 0x03, 0xD8,
+ 0x00, 0x00, 0x74, 0x00, 0x80, 0xA9, 0x79, 0x09,
+ 0x20, 0x05, 0xF0, 0x9B, 0xFE, 0x10, 0xAB, 0x98,
+ 0x8E, 0x04, 0xA9, 0x80, 0x1C, 0x1D, 0x90, 0x07,
+ 0xA8, 0x61, 0xC1, 0x18, 0x9A, 0x19, 0x99, 0x01,
+ 0x97, 0x03, 0x92, 0x1A, 0x9A, 0x02, 0x91, 0x00,
+ 0x92, 0x23, 0x46, 0x00, 0x22, 0x1D, 0xA9, 0x03,
+ 0x20, 0xFF, 0xF7, 0x74, 0xFE, 0x09, 0xE0, 0x01,
+ 0x21, 0x19, 0x91, 0x81, 0x6B, 0xC9, 0xB2, 0x18,
+ 0x91, 0x81, 0x6A, 0x00, 0x29, 0x19, 0xD1, 0x01,
+ 0x20, 0x1B, 0x90, 0x03, 0x20, 0x1B, 0x99, 0x05,
+ 0xF0, 0x78, 0xFE, 0x04, 0x20, 0x1E, 0x99, 0x05,
+ 0xF0, 0x74, 0xFE, 0x1A, 0x98, 0x01, 0x0A, 0x05,
+ 0x20, 0x05, 0xF0, 0x6F, 0xFE, 0x1A, 0x98, 0xC1,
+ 0xB2, 0x06, 0x20, 0x05, 0xF0, 0x6A, 0xFE, 0x09,
+ 0x21, 0x07, 0x20, 0x05, 0xF0, 0x66, 0xFE, 0x1F,
+ 0xB0, 0xF0, 0xBD, 0xC1, 0x6A, 0x82, 0x6B, 0x71,
+ 0x43, 0xC0, 0x6B, 0x89, 0x18,
+ 0x00, 0x00, 0x75, 0x00, 0x80, 0x08, 0x18, 0x80,
+ 0xB2, 0x1C, 0x90, 0x38, 0x6A, 0x02, 0x28, 0x02,
+ 0xD0, 0x38, 0x6A, 0x03, 0x28, 0x09, 0xD1, 0x00,
+ 0x2C, 0x03, 0xD1, 0xE9, 0x79, 0x08, 0x20, 0x05,
+ 0xF0, 0x50, 0xFE, 0x10, 0xAB, 0x98, 0x8E, 0x40,
+ 0x1C, 0x1D, 0x90, 0x38, 0x6A, 0x01, 0x28, 0x02,
+ 0xD0, 0x38, 0x6A, 0x03, 0x28, 0x0D, 0xD1, 0x10,
+ 0xAB, 0x98, 0x8E, 0xA0, 0x42, 0x05, 0xD3, 0x29,
+ 0x7A, 0x00, 0x1B, 0x08, 0x30, 0x80, 0xB2, 0x05,
+ 0xF0, 0x3C, 0xFE, 0x10, 0xAB, 0x98, 0x8E, 0x40,
+ 0x1C, 0x1D, 0x90, 0x07, 0xA8, 0x04, 0xA9, 0x61,
+ 0xC1, 0x1C, 0x98, 0x18, 0x9A, 0x19, 0x99, 0x01,
+ 0xAB, 0x07, 0xC3, 0x1A, 0x9A, 0x00, 0x92, 0x00,
+ 0x22, 0x23, 0x46, 0x1D, 0xA9, 0x01, 0x20, 0x9F,
+ 0xE7, 0xF0, 0xB5, 0x85, 0xB0, 0x03, 0x20, 0x05,
+ 0xF0, 0x39, 0xFE, 0x02, 0x90, 0x05, 0x20, 0x05,
+ 0xF0, 0x35, 0xFE, 0x01, 0x90,
+ 0x00, 0x00, 0x76, 0x00, 0x80, 0x07, 0x20, 0x05,
+ 0xF0, 0x20, 0xFE, 0x07, 0x4C, 0x05, 0x46, 0x21,
+ 0x46, 0xFF, 0x31, 0x0B, 0xE0, 0x3E, 0x01, 0x00,
+ 0x20, 0xC8, 0xDF, 0x00, 0x00, 0x2C, 0xE1, 0x00,
+ 0x00, 0x80, 0xE2, 0x00, 0x00, 0x6D, 0x01, 0x00,
+ 0x20, 0x48, 0xDE, 0x00, 0x00, 0x81, 0x31, 0xFF,
+ 0x34, 0x41, 0x34, 0x04, 0x91, 0x03, 0x28, 0x01,
+ 0xD2, 0x67, 0x6A, 0x07, 0xE0, 0x06, 0x2D, 0x01,
+ 0xD2, 0x27, 0x6A, 0x03, 0xE0, 0x09, 0x2D, 0x15,
+ 0xD2, 0x20, 0x6A, 0x47, 0x00, 0xF9, 0x48, 0xE9,
+ 0x00, 0x08, 0x18, 0x00, 0x79, 0x46, 0x07, 0x76,
+ 0x0F, 0xFF, 0x20, 0x31, 0x46, 0xF9, 0x30, 0x08,
+ 0xF0, 0x52, 0xFF, 0x01, 0x99, 0x81, 0x42, 0x00,
+ 0xD9, 0x01, 0x90, 0x02, 0x98, 0xB8, 0x42, 0x0D,
+ 0xD2, 0x38, 0x1A, 0x0C, 0xE0, 0x09, 0x2D, 0x07,
+ 0xD1, 0xA0, 0x6A, 0x87, 0x00, 0x08, 0x6A, 0x03,
+ 0x28, 0x00, 0xD1, 0x7F, 0x00,
+ 0x00, 0x00, 0x77, 0x00, 0x80, 0x02, 0x26, 0xE7,
+ 0xE7, 0x01, 0x21, 0xA2, 0xE0, 0x00, 0x20, 0x01,
+ 0x99, 0x81, 0x42, 0x00, 0xD9, 0x01, 0x90, 0x09,
+ 0x2D, 0x65, 0xD1, 0x08, 0x20, 0x00, 0x90, 0x05,
+ 0xF0, 0x07, 0xFF, 0x07, 0x46, 0x02, 0x98, 0x02,
+ 0x99, 0xC6, 0xB2, 0x01, 0x98, 0x08, 0x18, 0x03,
+ 0x90, 0x4D, 0xE0, 0xB0, 0x08, 0x00, 0x21, 0x82,
+ 0x00, 0xB2, 0x1A, 0xA3, 0x6A, 0x92, 0xB2, 0x83,
+ 0x42, 0x04, 0x9B, 0x1B, 0x6A, 0x25, 0xD9, 0x01,
+ 0x2B, 0x0C, 0xD0, 0x00, 0x2A, 0x05, 0xD0, 0x01,
+ 0x2A, 0x06, 0xD0, 0x02, 0x2A, 0x0C, 0xD1, 0xD8,
+ 0x49, 0x18, 0xE0, 0x40, 0x00, 0xD7, 0x49, 0x10,
+ 0xE0, 0xD7, 0x49, 0x13, 0xE0, 0x00, 0x2A, 0x0A,
+ 0xD0, 0x01, 0x2A, 0x0C, 0xD0, 0x02, 0x2A, 0x0C,
+ 0xD0, 0x03, 0x2A, 0x1E, 0xD1, 0x39, 0x46, 0xC1,
+ 0x40, 0xC9, 0x07, 0xC9, 0x0F, 0x19, 0xE0, 0xD1,
+ 0x49, 0x40, 0x00, 0x09, 0x5A,
+ 0x00, 0x00, 0x78, 0x00, 0x80, 0x15, 0xE0, 0xD0,
+ 0x49, 0x00, 0xE0, 0xD0, 0x49, 0x08, 0x56, 0x81,
+ 0xB2, 0x0F, 0xE0, 0x03, 0x2B, 0x0D, 0xD1, 0x00,
+ 0x2A, 0x1C, 0xD0, 0x01, 0x2A, 0x1D, 0xD0, 0x02,
+ 0x2A, 0x1E, 0xD0, 0x03, 0x2A, 0x05, 0xD1, 0xA1,
+ 0x6A, 0x41, 0x1A, 0x38, 0x46, 0xC8, 0x40, 0xC1,
+ 0x07, 0xC9, 0x0F, 0x08, 0x0A, 0x09, 0x02, 0x08,
+ 0x43, 0x81, 0xB2, 0x00, 0x98, 0x05, 0xF0, 0x8B,
+ 0xFD, 0x00, 0x98, 0x80, 0x1C, 0x80, 0xB2, 0x00,
+ 0x90, 0x76, 0x1C, 0x03, 0x98, 0xF6, 0xB2, 0xB0,
+ 0x42, 0xAF, 0xD8, 0x1C, 0xE0, 0xA1, 0x6A, 0x40,
+ 0x1A, 0xD1, 0xE7, 0xA1, 0x6A, 0x40, 0x1A, 0xD2,
+ 0xE7, 0xA1, 0x6A, 0x40, 0x1A, 0xD1, 0xE7, 0xB3,
+ 0x49, 0xE8, 0x00, 0x08, 0x58, 0x02, 0x99, 0x01,
+ 0x9F, 0x71, 0x43, 0x0C, 0x18, 0x77, 0x43, 0x00,
+ 0x26, 0x07, 0xE0, 0x30, 0x46, 0x08, 0x30, 0x21,
+ 0x78, 0x80, 0xB2, 0x05, 0xF0,
+ 0x00, 0x00, 0x79, 0x00, 0x80, 0x5E, 0xFD, 0x64,
+ 0x1C, 0x76, 0x1C, 0xBE, 0x42, 0xF5, 0xD3, 0xE9,
+ 0xB2, 0x04, 0x20, 0x05, 0xF0, 0x56, 0xFD, 0x01,
+ 0x98, 0x81, 0xB2, 0x05, 0x20, 0x05, 0xF0, 0x5B,
+ 0xFD, 0x09, 0x2D, 0x01, 0xD1, 0x32, 0x21, 0x10,
+ 0xE0, 0x03, 0x2D, 0x04, 0xD3, 0xA1, 0x48, 0xE9,
+ 0x00, 0x08, 0x18, 0x01, 0x79, 0x09, 0xE0, 0xA6,
+ 0x48, 0x40, 0x69, 0x01, 0x28, 0xF6, 0xD1, 0x9D,
+ 0x48, 0xE9, 0x00, 0x08, 0x18, 0x01, 0x79, 0x08,
+ 0x20, 0x01, 0x43, 0x07, 0x20, 0x05, 0xF0, 0x39,
+ 0xFD, 0x00, 0x21, 0x03, 0x20, 0x05, 0xF0, 0x35,
+ 0xFD, 0x05, 0xB0, 0xF0, 0xBD, 0xFE, 0xB5, 0x03,
+ 0x20, 0x05, 0xF0, 0x33, 0xFD, 0x06, 0x02, 0x04,
+ 0x20, 0x05, 0xF0, 0x2F, 0xFD, 0x06, 0x43, 0x05,
+ 0x20, 0x05, 0xF0, 0x2B, 0xFD, 0x04, 0x02, 0x06,
+ 0x20, 0x05, 0xF0, 0x27, 0xFD, 0x04, 0x43, 0x07,
+ 0x20, 0x05, 0xF0, 0x23, 0xFD,
+ 0x00, 0x00, 0x7A, 0x00, 0x80, 0x01, 0x90, 0x05,
+ 0xF0, 0xF7, 0xFB, 0x07, 0x46, 0x00, 0x20, 0x00,
+ 0x90, 0x01, 0x98, 0x0C, 0x37, 0x02, 0x28, 0x03,
+ 0xD0, 0x03, 0x28, 0x07, 0xD0, 0x04, 0x28, 0x29,
+ 0xD1, 0x1B, 0x2C, 0x00, 0xD9, 0x1B, 0x24, 0x00,
+ 0x25, 0x8A, 0x4F, 0x1B, 0xE0, 0xFF, 0x20, 0xF9,
+ 0x30, 0x84, 0x42, 0x00, 0xD9, 0x04, 0x46, 0x00,
+ 0x25, 0x08, 0xE0, 0x70, 0x19, 0x39, 0x5C, 0x28,
+ 0x46, 0x08, 0x30, 0x80, 0xB2, 0x05, 0xF0, 0xFD,
+ 0xFC, 0x6D, 0x1C, 0xAD, 0xB2, 0xA5, 0x42, 0xF4,
+ 0xD3, 0x12, 0xE0, 0x70, 0x19, 0x39, 0x5C, 0x28,
+ 0x46, 0x09, 0x30, 0x80, 0xB2, 0x05, 0xF0, 0xF1,
+ 0xFC, 0x6D, 0x1C, 0xAD, 0xB2, 0xAC, 0x42, 0xF4,
+ 0xD8, 0x7B, 0x48, 0x41, 0x78, 0x08, 0x20, 0x05,
+ 0xF0, 0xE8, 0xFC, 0x01, 0xE0, 0x01, 0x20, 0x00,
+ 0x90, 0x03, 0x20, 0x00, 0x99, 0x05, 0xF0, 0xE1,
+ 0xFC, 0x04, 0x20, 0x01, 0x99,
+ 0x00, 0x00, 0x7B, 0x00, 0x80, 0x05, 0xF0, 0xDD,
+ 0xFC, 0x21, 0x0A, 0x05, 0x20, 0x05, 0xF0, 0xD9,
+ 0xFC, 0xE1, 0xB2, 0x06, 0x20, 0x05, 0xF0, 0xD5,
+ 0xFC, 0xFE, 0xBD, 0xF8, 0xB5, 0x01, 0x24, 0x00,
+ 0x25, 0x03, 0x20, 0x05, 0xF0, 0xD2, 0xFC, 0x06,
+ 0x46, 0x04, 0x20, 0x05, 0xF0, 0xCE, 0xFC, 0x00,
+ 0x90, 0x6A, 0x48, 0x07, 0x88, 0x6A, 0x48, 0x01,
+ 0xF0, 0xD9, 0xFE, 0x30, 0x46, 0x66, 0x4E, 0x01,
+ 0x28, 0x08, 0xD0, 0x02, 0x28, 0x1E, 0xD0, 0x03,
+ 0x28, 0x11, 0xD0, 0x04, 0x28, 0x2A, 0xD1, 0x01,
+ 0xF0, 0xEB, 0xFC, 0x20, 0xE0, 0x5F, 0x48, 0x09,
+ 0x38, 0x01, 0xF0, 0x0B, 0xFE, 0x70, 0x70, 0xC0,
+ 0xB2, 0x00, 0x28, 0x02, 0xD0, 0x01, 0x21, 0x08,
+ 0x43, 0x70, 0x70, 0x00, 0x24, 0x1A, 0xE0, 0x59,
+ 0x48, 0x00, 0x99, 0x09, 0x38, 0x01, 0xF0, 0xBD,
+ 0xFD, 0x70, 0x70, 0xC0, 0xB2, 0x00, 0x28, 0xF4,
+ 0xD1, 0x01, 0x25, 0xF2, 0xE7,
+ 0x00, 0x00, 0x7C, 0x00, 0x80, 0x30, 0x78, 0x00,
+ 0x28, 0x07, 0xD0, 0x01, 0x28, 0x0A, 0xD1, 0x51,
+ 0x48, 0x09, 0x38, 0x01, 0xF0, 0x38, 0xFC, 0x70,
+ 0x70, 0xF2, 0xE7, 0x4E, 0x48, 0x09, 0x38, 0x01,
+ 0xF0, 0x8A, 0xFC, 0xF8, 0xE7, 0x38, 0x46, 0x01,
+ 0xF0, 0xA1, 0xFE, 0x21, 0x46, 0x03, 0x20, 0x05,
+ 0xF0, 0x88, 0xFC, 0x71, 0x78, 0x04, 0x20, 0x05,
+ 0xF0, 0x84, 0xFC, 0x29, 0x46, 0x05, 0x20, 0x05,
+ 0xF0, 0x80, 0xFC, 0xF8, 0xBD, 0xF0, 0xB5, 0xA3,
+ 0xB0, 0x03, 0x20, 0x05, 0xF0, 0x8F, 0xFC, 0x06,
+ 0x46, 0x05, 0x20, 0x05, 0xF0, 0x8B, 0xFC, 0x05,
+ 0x46, 0x07, 0x20, 0x05, 0xF0, 0x76, 0xFC, 0x21,
+ 0x90, 0x00, 0x28, 0x10, 0xD0, 0x01, 0x28, 0x1A,
+ 0xD0, 0x02, 0x28, 0x5D, 0xD1, 0x00, 0x2E, 0x5B,
+ 0xD1, 0x80, 0x2D, 0x59, 0xD8, 0x3B, 0x4F, 0x38,
+ 0x46, 0x40, 0x02, 0x00, 0x0C, 0x22, 0x90, 0x00,
+ 0x20, 0x04, 0x46, 0x00, 0x90,
+ 0x00, 0x00, 0x7D, 0x00, 0x80, 0x12, 0xE0, 0x38,
+ 0x48, 0x38, 0x49, 0xC0, 0x09, 0xC9, 0x09, 0x40,
+ 0x1A, 0xB0, 0x42, 0x49, 0xD9, 0x80, 0x2D, 0x47,
+ 0xD8, 0x34, 0x4F, 0x38, 0x46, 0xEC, 0xE7, 0x00,
+ 0x2E, 0x42, 0xD1, 0x80, 0x2D, 0x40, 0xD8, 0x30,
+ 0x4F, 0x38, 0x46, 0xE5, 0xE7, 0x28, 0x19, 0x08,
+ 0x30, 0x80, 0xB2, 0x05, 0xF0, 0x4A, 0xFC, 0x1F,
+ 0x49, 0x10, 0x39, 0x09, 0x5D, 0x88, 0x42, 0x01,
+ 0xD0, 0x01, 0x20, 0x00, 0x90, 0x64, 0x1C, 0xA4,
+ 0xB2, 0x08, 0x2C, 0xEF, 0xD3, 0x00, 0x98, 0x00,
+ 0x28, 0x2A, 0xD1, 0x00, 0x24, 0x08, 0xE0, 0x20,
+ 0x46, 0x08, 0x30, 0x80, 0xB2, 0x05, 0xF0, 0x35,
+ 0xFC, 0x01, 0xA9, 0x08, 0x55, 0x64, 0x1C, 0xA4,
+ 0xB2, 0xA5, 0x42, 0xF4, 0xD8, 0xF0, 0x01, 0xC0,
+ 0x19, 0x40, 0x19, 0x05, 0xE0, 0x01, 0x78, 0x01,
+ 0xAA, 0x11, 0x55, 0x40, 0x1C, 0x64, 0x1C, 0xA4,
+ 0xB2, 0x80, 0x2C, 0xF7, 0xD3,
+ 0x00, 0x00, 0x7E, 0x00, 0x80, 0x28, 0x46, 0x10,
+ 0x30, 0x80, 0xB2, 0x05, 0xF0, 0x1E, 0xFC, 0x04,
+ 0x02, 0x28, 0x46, 0x11, 0x30, 0x80, 0xB2, 0x05,
+ 0xF0, 0x18, 0xFC, 0x04, 0x43, 0x01, 0xA9, 0x28,
+ 0x46, 0x05, 0xF0, 0x64, 0xFD, 0x84, 0x42, 0x23,
+ 0xD0, 0x01, 0x21, 0x03, 0x20, 0x05, 0xF0, 0x09,
+ 0xFC, 0x23, 0xB0, 0xF0, 0xBD, 0x20, 0xCC, 0x00,
+ 0x00, 0x0C, 0x02, 0x00, 0x20, 0x1C, 0x02, 0x00,
+ 0x20, 0x14, 0x02, 0x00, 0x20, 0x24, 0x02, 0x00,
+ 0x20, 0x18, 0x02, 0x00, 0x20, 0x10, 0x02, 0x00,
+ 0x20, 0x90, 0xDD, 0x00, 0x00, 0x0F, 0x04, 0x00,
+ 0x20, 0xCB, 0x00, 0x00, 0x20, 0x48, 0x01, 0x00,
+ 0x20, 0x10, 0x27, 0x00, 0x00, 0x00, 0xE2, 0x00,
+ 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xDC, 0x00,
+ 0x00, 0x00, 0x2E, 0x07, 0xD1, 0x00, 0x20, 0x01,
+ 0xA9, 0x3A, 0x5C, 0x0A, 0x54, 0x40, 0x1C, 0x80,
+ 0xB2, 0x04, 0x28, 0xF9, 0xD3,
+ 0x00, 0x00, 0x7F, 0x00, 0x80, 0x22, 0x98, 0x01,
+ 0xA9, 0x80, 0x19, 0x80, 0xB2, 0x05, 0xF0, 0x72,
+ 0xFD, 0x00, 0x28, 0x01, 0xD1, 0x00, 0x21, 0x00,
+ 0xE0, 0x01, 0x21, 0x03, 0x20, 0x05, 0xF0, 0xD1,
+ 0xFB, 0x04, 0x20, 0x21, 0x99, 0x05, 0xF0, 0xCD,
+ 0xFB, 0x29, 0x46, 0x05, 0x20, 0x05, 0xF0, 0xD3,
+ 0xFB, 0x21, 0x98, 0x00, 0x28, 0xBC, 0xD1, 0xF9,
+ 0x49, 0x08, 0x70, 0xF9, 0x48, 0x01, 0x88, 0xC9,
+ 0x07, 0xC9, 0x0F, 0x01, 0x80, 0xB4, 0xE7, 0xFE,
+ 0xB5, 0x03, 0x20, 0x05, 0xF0, 0xCF, 0xFB, 0x04,
+ 0x46, 0x05, 0x20, 0x05, 0xF0, 0xCB, 0xFB, 0x05,
+ 0x46, 0x07, 0x20, 0x05, 0xF0, 0xB6, 0xFB, 0x00,
+ 0x90, 0x00, 0x28, 0x09, 0xD0, 0x01, 0x28, 0x12,
+ 0xD0, 0x02, 0x28, 0x1A, 0xD1, 0x00, 0x2C, 0x18,
+ 0xD1, 0x80, 0x2D, 0x16, 0xD8, 0xEB, 0x4E, 0x0F,
+ 0xE0, 0xEB, 0x48, 0xEC, 0x49, 0xC0, 0x09, 0xC9,
+ 0x09, 0x40, 0x1A, 0xA0, 0x42,
+ 0x00, 0x00, 0x80, 0x00, 0x80, 0x0D, 0xD9, 0x80,
+ 0x2D, 0x0B, 0xD8, 0xE8, 0x4E, 0x04, 0xE0, 0x00,
+ 0x2C, 0x07, 0xD1, 0x80, 0x2D, 0x05, 0xD8, 0xE4,
+ 0x4E, 0xE0, 0x01, 0x87, 0x19, 0x00, 0x24, 0x01,
+ 0x90, 0x0C, 0xE0, 0x01, 0x21, 0x03, 0x20, 0x05,
+ 0xF0, 0x8C, 0xFB, 0xFE, 0xBD, 0x20, 0x46, 0x08,
+ 0x30, 0x39, 0x5D, 0x80, 0xB2, 0x05, 0xF0, 0x85,
+ 0xFB, 0x64, 0x1C, 0xA4, 0xB2, 0xA5, 0x42, 0xF5,
+ 0xD8, 0x39, 0x46, 0x28, 0x46, 0x05, 0xF0, 0xD2,
+ 0xFC, 0x04, 0x46, 0x01, 0x0A, 0x28, 0x46, 0x08,
+ 0x30, 0x80, 0xB2, 0x05, 0xF0, 0x76, 0xFB, 0x28,
+ 0x46, 0x09, 0x30, 0xE1, 0xB2, 0x80, 0xB2, 0x05,
+ 0xF0, 0x70, 0xFB, 0x00, 0x21, 0x03, 0x20, 0x05,
+ 0xF0, 0x6C, 0xFB, 0x04, 0x20, 0x00, 0x99, 0x05,
+ 0xF0, 0x68, 0xFB, 0x00, 0x2D, 0x03, 0xD1, 0x71,
+ 0x88, 0x01, 0x98, 0x08, 0x1A, 0x85, 0xB2, 0x29,
+ 0x46, 0x05, 0x20, 0x05, 0xF0,
+ 0x00, 0x00, 0x81, 0x00, 0x80, 0x68, 0xFB, 0xFE,
+ 0xBD, 0xF8, 0xB5, 0x01, 0xF0, 0x9F, 0xFD, 0x02,
+ 0x20, 0x05, 0xF0, 0x5B, 0xFB, 0x05, 0x46, 0x40,
+ 0x06, 0x7A, 0xD4, 0x01, 0xE0, 0x01, 0xF0, 0xC2,
+ 0xFD, 0x05, 0xF0, 0x6D, 0xFB, 0x00, 0x28, 0xF9,
+ 0xD1, 0xAB, 0x06, 0x9B, 0x0E, 0xBB, 0x48, 0x0A,
+ 0x2B, 0x3D, 0xD0, 0x07, 0xDC, 0x08, 0xF0, 0x91,
+ 0xFD, 0x0A, 0xA4, 0xA2, 0x24, 0x29, 0x2C, 0xA2,
+ 0x2F, 0x32, 0x35, 0x38, 0xA2, 0x0F, 0x2B, 0x79,
+ 0xD0, 0x0A, 0xDC, 0x0B, 0x2B, 0x48, 0xD0, 0x0C,
+ 0x2B, 0x5F, 0xD0, 0xB7, 0x4E, 0x0D, 0x2B, 0x5F,
+ 0xD0, 0x0E, 0x2B, 0x6C, 0xD1, 0x00, 0x20, 0x67,
+ 0xE0, 0x10, 0x2B, 0x71, 0xD0, 0x11, 0x2B, 0x68,
+ 0xD0, 0x3F, 0x2B, 0xF6, 0xD1, 0x03, 0x20, 0x05,
+ 0xF0, 0x2C, 0xFB, 0xFE, 0x28, 0x7C, 0xD0, 0xFF,
+ 0x28, 0x7D, 0xD1, 0x00, 0xF0, 0x95, 0xF8, 0x7B,
+ 0xE0, 0x80, 0x21, 0x03, 0x20,
+ 0x00, 0x00, 0x82, 0x00, 0x80, 0x05, 0xF0, 0x27,
+ 0xFB, 0x7A, 0xE0, 0xFF, 0xF7, 0x5C, 0xFF, 0x77,
+ 0xE0, 0xFF, 0xF7, 0x98, 0xFE, 0x74, 0xE0, 0x00,
+ 0xF0, 0xAB, 0xF9, 0x71, 0xE0, 0xFF, 0xF7, 0x3D,
+ 0xFE, 0x6E, 0xE0, 0xFF, 0xF7, 0xDB, 0xFD, 0x6B,
+ 0xE0, 0x00, 0xF0, 0x76, 0xF9, 0x68, 0xE0, 0x00,
+ 0x78, 0x00, 0x28, 0x55, 0xD0, 0x03, 0x20, 0x05,
+ 0xF0, 0x08, 0xFB, 0x04, 0x46, 0xC0, 0x07, 0x01,
+ 0xD0, 0x03, 0xF0, 0x33, 0xFC, 0xA0, 0x07, 0x01,
+ 0xD5, 0x03, 0xF0, 0xD0, 0xFB, 0x60, 0x07, 0x01,
+ 0xD5, 0x03, 0xF0, 0xFD, 0xFB, 0x20, 0x07, 0x01,
+ 0xD5, 0x03, 0xF0, 0xDE, 0xFB, 0x00, 0x21, 0x40,
+ 0xE0, 0x00, 0x78, 0x00, 0x28, 0x3C, 0xD0, 0x01,
+ 0x20, 0x05, 0xF0, 0xBB, 0xF9, 0x01, 0xF0, 0x92,
+ 0xFC, 0x04, 0xF0, 0x3E, 0xF9, 0xC0, 0x07, 0xF9,
+ 0xD1, 0x62, 0xB6, 0x8E, 0x48, 0x80, 0x6A, 0x00,
+ 0x28, 0x3E, 0xD0, 0x01, 0xF0,
+ 0x00, 0x00, 0x83, 0x00, 0x80, 0x87, 0xFC, 0x08,
+ 0xF0, 0x64, 0xFA, 0x01, 0x28, 0xF9, 0xD0, 0x37,
+ 0xE0, 0x48, 0xE0, 0xFF, 0xF7, 0xAD, 0xFC, 0x33,
+ 0xE0, 0x00, 0x24, 0x67, 0x00, 0xF8, 0x1C, 0x80,
+ 0xB2, 0x05, 0xF0, 0xE4, 0xFA, 0x84, 0x49, 0x64,
+ 0x1C, 0xC8, 0x53, 0x19, 0x2C, 0xF5, 0xD3, 0x01,
+ 0x20, 0x30, 0x70, 0x25, 0xE0, 0x02, 0xE0, 0x21,
+ 0xE0, 0x06, 0xE0, 0x16, 0xE0, 0x03, 0x20, 0x05,
+ 0xF0, 0xC4, 0xFA, 0x7E, 0x49, 0x08, 0x70, 0xC9,
+ 0xE7, 0x07, 0x20, 0x05, 0xF0, 0xBE, 0xFA, 0x00,
+ 0x07, 0x00, 0x0F, 0x05, 0x28, 0x04, 0xD8, 0xFF,
+ 0xF7, 0x70, 0xFB, 0x11, 0xE0, 0x08, 0xE0, 0x0A,
+ 0xE0, 0x01, 0x21, 0x03, 0x20, 0x05, 0xF0, 0xAD,
+ 0xFA, 0x0A, 0xE0, 0x00, 0xF0, 0xCA, 0xF8, 0x07,
+ 0xE0, 0x00, 0xF0, 0x71, 0xF8, 0x00, 0xE0, 0x01,
+ 0x20, 0x00, 0x28, 0x01, 0xD0, 0xAD, 0x09, 0xAD,
+ 0x01, 0x6F, 0x48, 0x80, 0x22,
+ 0x00, 0x00, 0x84, 0x00, 0x80, 0x01, 0x78, 0x51,
+ 0x40, 0x01, 0x70, 0xC8, 0xB2, 0xC1, 0x09, 0xC9,
+ 0x01, 0x29, 0x43, 0x40, 0x20, 0x01, 0x43, 0x02,
+ 0x20, 0x05, 0xF0, 0x93, 0xFA, 0x01, 0xF0, 0xDE,
+ 0xF8, 0x01, 0xF0, 0x14, 0xF9, 0xF8, 0xBD, 0x70,
+ 0x47, 0xFE, 0xB5, 0x04, 0x20, 0x05, 0xF0, 0x8D,
+ 0xFA, 0x04, 0x46, 0x05, 0x20, 0x05, 0xF0, 0x89,
+ 0xFA, 0x00, 0x02, 0x24, 0x18, 0x06, 0x20, 0x05,
+ 0xF0, 0x84, 0xFA, 0x00, 0x04, 0x24, 0x18, 0x07,
+ 0x20, 0x05, 0xF0, 0x7F, 0xFA, 0x00, 0x06, 0x25,
+ 0x18, 0x08, 0x20, 0x05, 0xF0, 0x7A, 0xFA, 0x04,
+ 0x46, 0x09, 0x20, 0x05, 0xF0, 0x76, 0xFA, 0x00,
+ 0x02, 0xFF, 0x26, 0x20, 0x18, 0xEF, 0x36, 0xB0,
+ 0x42, 0x00, 0xD8, 0x06, 0x46, 0x00, 0x24, 0x20,
+ 0x46, 0x0A, 0x30, 0x07, 0x46, 0x80, 0xB2, 0x05,
+ 0xF0, 0x68, 0xFA, 0x69, 0x46, 0x08, 0x55, 0xB8,
+ 0xB2, 0x00, 0x21, 0x05, 0xF0,
+ 0x00, 0x00, 0x85, 0x00, 0x80, 0x5E, 0xFA, 0x64,
+ 0x1C, 0x08, 0x2C, 0xF0, 0xD3, 0x01, 0x21, 0x4D,
+ 0x4B, 0x00, 0x20, 0x6A, 0x46, 0x1C, 0x5C, 0x17,
+ 0x5C, 0xBC, 0x42, 0x00, 0xD0, 0x00, 0x21, 0x40,
+ 0x1C, 0x08, 0x28, 0xF7, 0xD3, 0x01, 0x29, 0x06,
+ 0xD1, 0x48, 0x07, 0x85, 0x42, 0x03, 0xD3, 0x46,
+ 0x49, 0xA8, 0x19, 0x88, 0x42, 0x01, 0xD9, 0x01,
+ 0x20, 0xFE, 0xBD, 0x00, 0x24, 0x07, 0xE0, 0x20,
+ 0x46, 0x12, 0x30, 0x80, 0xB2, 0x05, 0xF0, 0x41,
+ 0xFA, 0x28, 0x70, 0x6D, 0x1C, 0x64, 0x1C, 0xB4,
+ 0x42, 0xF5, 0xD3, 0x00, 0x20, 0xFE, 0xBD, 0xFE,
+ 0xB5, 0x04, 0x20, 0x05, 0xF0, 0x36, 0xFA, 0x04,
+ 0x46, 0x05, 0x20, 0x05, 0xF0, 0x32, 0xFA, 0x00,
+ 0x02, 0x24, 0x18, 0x06, 0x20, 0x05, 0xF0, 0x2D,
+ 0xFA, 0x00, 0x04, 0x24, 0x18, 0x07, 0x20, 0x05,
+ 0xF0, 0x28, 0xFA, 0x00, 0x06, 0x25, 0x18, 0x08,
+ 0x20, 0x05, 0xF0, 0x23, 0xFA,
+ 0x00, 0x00, 0x86, 0x00, 0x80, 0x04, 0x46, 0x09,
+ 0x20, 0x05, 0xF0, 0x1F, 0xFA, 0x00, 0x02, 0xFF,
+ 0x26, 0x20, 0x18, 0xFD, 0x36, 0xB0, 0x42, 0x00,
+ 0xD8, 0x06, 0x46, 0x00, 0x24, 0x20, 0x46, 0x0A,
+ 0x30, 0x07, 0x46, 0x80, 0xB2, 0x05, 0xF0, 0x11,
+ 0xFA, 0x69, 0x46, 0x08, 0x55, 0xB8, 0xB2, 0x00,
+ 0x21, 0x05, 0xF0, 0x07, 0xFA, 0x64, 0x1C, 0x08,
+ 0x2C, 0xF0, 0xD3, 0x01, 0x21, 0x21, 0x4B, 0x00,
+ 0x20, 0x6A, 0x46, 0x1C, 0x5C, 0x17, 0x5C, 0xBC,
+ 0x42, 0x00, 0xD0, 0x00, 0x21, 0x40, 0x1C, 0x08,
+ 0x28, 0xF7, 0xD3, 0x01, 0x29, 0x06, 0xD1, 0x48,
+ 0x07, 0x85, 0x42, 0x03, 0xD3, 0x1A, 0x49, 0xA8,
+ 0x19, 0x88, 0x42, 0x01, 0xD9, 0x01, 0x20, 0xFE,
+ 0xBD, 0x00, 0x24, 0x06, 0xE0, 0x29, 0x78, 0x20,
+ 0x1D, 0x6D, 0x1C, 0x80, 0xB2, 0x05, 0xF0, 0xE5,
+ 0xF9, 0x64, 0x1C, 0xB4, 0x42, 0xF6, 0xD3, 0x00,
+ 0x20, 0xFE, 0xBD, 0xF8, 0xB5,
+ 0x00, 0x00, 0x87, 0x00, 0x80, 0x03, 0x20, 0x05,
+ 0xF0, 0xE0, 0xF9, 0x00, 0x26, 0x00, 0x28, 0x1D,
+ 0xD0, 0x01, 0x28, 0x1D, 0xD0, 0x02, 0x28, 0x3C,
+ 0xD1, 0x02, 0x4C, 0x1A, 0xE0, 0x2A, 0x01, 0x00,
+ 0x20, 0x3C, 0x01, 0x00, 0x20, 0x00, 0xE2, 0x00,
+ 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xDC, 0x00,
+ 0x00, 0xD4, 0x00, 0x00, 0x20, 0x88, 0xDF, 0x00,
+ 0x00, 0xF4, 0x00, 0x00, 0x20, 0x3F, 0x01, 0x00,
+ 0x20, 0x3E, 0x01, 0x00, 0x20, 0x18, 0xCC, 0x00,
+ 0x00, 0x00, 0x20, 0x00, 0x20, 0x53, 0x4C, 0x00,
+ 0xE0, 0x53, 0x4C, 0x20, 0x88, 0x67, 0x88, 0x21,
+ 0x46, 0x05, 0xF0, 0x08, 0xFB, 0x05, 0x46, 0xE0,
+ 0x19, 0x04, 0x88, 0xA5, 0x42, 0x00, 0xD0, 0x01,
+ 0x26, 0x31, 0x46, 0x03, 0x20, 0x05, 0xF0, 0xA9,
+ 0xF9, 0x29, 0x0A, 0x04, 0x20, 0x05, 0xF0, 0xA5,
+ 0xF9, 0xE9, 0xB2, 0x05, 0x20, 0x05, 0xF0, 0xA1,
+ 0xF9, 0x21, 0x0A, 0x06, 0x20,
+ 0x00, 0x00, 0x88, 0x00, 0x80, 0x05, 0xF0, 0x9D,
+ 0xF9, 0xE1, 0xB2, 0x07, 0x20, 0x05, 0xF0, 0x99,
+ 0xF9, 0xF8, 0xBD, 0x01, 0x21, 0x03, 0x20, 0xF9,
+ 0xE7, 0x70, 0xB5, 0x42, 0x48, 0x00, 0x78, 0x00,
+ 0x28, 0x01, 0xD1, 0x01, 0x21, 0x20, 0xE0, 0x03,
+ 0x20, 0x05, 0xF0, 0x8F, 0xF9, 0x04, 0x46, 0x3E,
+ 0x48, 0x06, 0x88, 0x3E, 0x48, 0x01, 0xF0, 0x9A,
+ 0xFB, 0x00, 0x25, 0x00, 0x2C, 0x09, 0xD0, 0x01,
+ 0x2C, 0x09, 0xD0, 0x02, 0x2C, 0x09, 0xD0, 0x03,
+ 0x2C, 0x09, 0xD1, 0x84, 0x20, 0x03, 0xF0, 0xC6,
+ 0xFE, 0x06, 0xE0, 0x81, 0x20, 0xFA, 0xE7, 0x88,
+ 0x20, 0xF8, 0xE7, 0x82, 0x20, 0xF6, 0xE7, 0x01,
+ 0x25, 0x30, 0x46, 0x01, 0xF0, 0x83, 0xFB, 0x29,
+ 0x46, 0x03, 0x20, 0x05, 0xF0, 0x6A, 0xF9, 0x70,
+ 0xBD, 0xF8, 0xB5, 0x03, 0x20, 0x05, 0xF0, 0x69,
+ 0xF9, 0x06, 0x02, 0x04, 0x20, 0x05, 0xF0, 0x65,
+ 0xF9, 0x06, 0x43, 0x05, 0x20,
+ 0x00, 0x00, 0x89, 0x00, 0x80, 0x05, 0xF0, 0x61,
+ 0xF9, 0x05, 0x02, 0x06, 0x20, 0x05, 0xF0, 0x5D,
+ 0xF9, 0x05, 0x43, 0x07, 0x20, 0x05, 0xF0, 0x59,
+ 0xF9, 0x00, 0x27, 0x00, 0x90, 0x01, 0x28, 0x03,
+ 0xD0, 0x02, 0x28, 0x12, 0xD0, 0x03, 0x28, 0x26,
+ 0xD1, 0x09, 0x2D, 0x00, 0xD9, 0x09, 0x25, 0x00,
+ 0x24, 0x08, 0xE0, 0x20, 0x46, 0x08, 0x30, 0x05,
+ 0xF0, 0x48, 0xF9, 0x31, 0x19, 0x1C, 0x4A, 0x64,
+ 0x1C, 0x50, 0x54, 0xE4, 0xB2, 0xA5, 0x42, 0xF4,
+ 0xD8, 0x16, 0xE0, 0x09, 0x2D, 0x00, 0xD9, 0x09,
+ 0x25, 0x08, 0x20, 0x05, 0xF0, 0x3A, 0xF9, 0x17,
+ 0x49, 0x00, 0x24, 0x08, 0x70, 0x08, 0xE0, 0x20,
+ 0x46, 0x09, 0x30, 0x05, 0xF0, 0x32, 0xF9, 0x31,
+ 0x19, 0x11, 0x4A, 0x64, 0x1C, 0x50, 0x54, 0xE4,
+ 0xB2, 0xA5, 0x42, 0xF4, 0xD8, 0x00, 0xE0, 0x01,
+ 0x27, 0x39, 0x46, 0x03, 0x20, 0x05, 0xF0, 0x21,
+ 0xF9, 0x04, 0x20, 0x00, 0x99,
+ 0x00, 0x00, 0x8A, 0x00, 0x80, 0x05, 0xF0, 0x1D,
+ 0xF9, 0x29, 0x0A, 0x05, 0x20, 0x05, 0xF0, 0x19,
+ 0xF9, 0xE9, 0xB2, 0x06, 0x20, 0x05, 0xF0, 0x15,
+ 0xF9, 0xF8, 0xBD, 0x00, 0x00, 0x00, 0xDC, 0x00,
+ 0x00, 0x00, 0xFF, 0x00, 0x00, 0x2A, 0x01, 0x00,
+ 0x20, 0x48, 0x01, 0x00, 0x20, 0x10, 0x27, 0x00,
+ 0x00, 0x06, 0x04, 0x00, 0x20, 0xCB, 0x00, 0x00,
+ 0x20, 0x70, 0xB5, 0x05, 0xF0, 0xCB, 0xF8, 0x01,
+ 0x20, 0x05, 0xF0, 0xF2, 0xF8, 0x05, 0xF0, 0xBB,
+ 0xF8, 0x01, 0x24, 0x65, 0x02, 0xA0, 0xB2, 0x00,
+ 0x21, 0x05, 0xF0, 0xF7, 0xF8, 0x64, 0x1C, 0xAC,
+ 0x42, 0xF8, 0xD3, 0x64, 0x4D, 0x00, 0x24, 0x60,
+ 0x00, 0x41, 0x19, 0x49, 0x78, 0x28, 0x5C, 0x05,
+ 0xF0, 0xEC, 0xF8, 0x64, 0x1C, 0x32, 0x2C, 0xF6,
+ 0xD3, 0xFF, 0x24, 0x01, 0x34, 0xA1, 0x78, 0x1C,
+ 0x20, 0x05, 0xF0, 0xE3, 0xF8, 0xE1, 0x78, 0x1D,
+ 0x20, 0x05, 0xF0, 0xDF, 0xF8,
+ 0x00, 0x00, 0x8B, 0x00, 0x80, 0x5A, 0x48, 0x81,
+ 0x88, 0x1E, 0x20, 0x05, 0xF0, 0xE4, 0xF8, 0x58,
+ 0x4C, 0x23, 0x20, 0x20, 0x34, 0x21, 0x8B, 0x05,
+ 0xF0, 0xDE, 0xF8, 0xA1, 0x7E, 0x25, 0x20, 0x05,
+ 0xF0, 0xD0, 0xF8, 0xE1, 0x7E, 0x26, 0x20, 0x05,
+ 0xF0, 0xCC, 0xF8, 0x21, 0x7F, 0x27, 0x20, 0x05,
+ 0xF0, 0xC8, 0xF8, 0x61, 0x7F, 0x28, 0x20, 0x05,
+ 0xF0, 0xC4, 0xF8, 0xA1, 0x7F, 0x29, 0x20, 0x05,
+ 0xF0, 0xC0, 0xF8, 0xE1, 0x7F, 0x2A, 0x20, 0x05,
+ 0xF0, 0xBC, 0xF8, 0x4A, 0x4C, 0x60, 0x7A, 0x22,
+ 0x7A, 0x01, 0x02, 0x11, 0x43, 0x2D, 0x20, 0x05,
+ 0xF0, 0xBE, 0xF8, 0x47, 0x48, 0x01, 0x88, 0x32,
+ 0x20, 0x05, 0xF0, 0xB9, 0xF8, 0x60, 0x7B, 0x22,
+ 0x7B, 0x01, 0x02, 0x11, 0x43, 0x36, 0x20, 0x05,
+ 0xF0, 0xB2, 0xF8, 0xE0, 0x7B, 0xA2, 0x7B, 0x01,
+ 0x02, 0x11, 0x43, 0x38, 0x20, 0x05, 0xF0, 0xAB,
+ 0xF8, 0x3E, 0x4D, 0x68, 0x69,
+ 0x00, 0x00, 0x8C, 0x00, 0x80, 0x3E, 0x4C, 0x01,
+ 0x28, 0x06, 0xD1, 0xA0, 0x69, 0xC1, 0xB2, 0x34,
+ 0x20, 0x05, 0xF0, 0x97, 0xF8, 0xE0, 0x69, 0x05,
+ 0xE0, 0xE0, 0x69, 0xC1, 0xB2, 0x34, 0x20, 0x05,
+ 0xF0, 0x90, 0xF8, 0xA0, 0x69, 0xC1, 0xB2, 0x35,
+ 0x20, 0x05, 0xF0, 0x8B, 0xF8, 0xE8, 0x68, 0x81,
+ 0xB2, 0x3A, 0x20, 0x05, 0xF0, 0x90, 0xF8, 0x28,
+ 0x69, 0x81, 0xB2, 0x3C, 0x20, 0x05, 0xF0, 0x8B,
+ 0xF8, 0x30, 0x48, 0x01, 0x78, 0x40, 0x20, 0x05,
+ 0xF0, 0x7C, 0xF8, 0x00, 0xF0, 0x67, 0xF8, 0x2E,
+ 0x4D, 0x2E, 0x4E, 0x28, 0x78, 0xC1, 0x00, 0x40,
+ 0x18, 0x31, 0x88, 0x40, 0x18, 0x08, 0x38, 0x81,
+ 0xB2, 0x43, 0x20, 0x05, 0xF0, 0x78, 0xF8, 0xA0,
+ 0x6A, 0xC1, 0xB2, 0x45, 0x20, 0x05, 0xF0, 0x69,
+ 0xF8, 0x30, 0x88, 0xC1, 0xB2, 0x46, 0x20, 0x05,
+ 0xF0, 0x64, 0xF8, 0x1E, 0x48, 0x20, 0x30, 0xC0,
+ 0x7C, 0xC2, 0x07, 0x23, 0x48,
+ 0x00, 0x00, 0x8D, 0x00, 0x80, 0xD2, 0x0F, 0x00,
+ 0x88, 0x41, 0x06, 0xC9, 0x0F, 0x49, 0x00, 0x11,
+ 0x43, 0x02, 0x06, 0xD2, 0x0F, 0x92, 0x00, 0x80,
+ 0x06, 0x0A, 0x43, 0xC0, 0x0F, 0xC1, 0x00, 0x11,
+ 0x43, 0x47, 0x20, 0x05, 0xF0, 0x4E, 0xF8, 0x29,
+ 0x78, 0x48, 0x20, 0x05, 0xF0, 0x4A, 0xF8, 0x19,
+ 0x4D, 0x00, 0x24, 0x28, 0x19, 0x01, 0x79, 0x20,
+ 0x46, 0x61, 0x30, 0x80, 0xB2, 0x05, 0xF0, 0x41,
+ 0xF8, 0x64, 0x1C, 0x20, 0x2C, 0xF5, 0xD3, 0x14,
+ 0x4D, 0x00, 0x24, 0x28, 0x19, 0x01, 0x79, 0x20,
+ 0x46, 0x81, 0x30, 0x80, 0xB2, 0x05, 0xF0, 0x35,
+ 0xF8, 0x64, 0x1C, 0x40, 0x2C, 0xF5, 0xD3, 0x70,
+ 0xBD, 0x10, 0xB5, 0x01, 0xF0, 0x73, 0xFA, 0x10,
+ 0xBD, 0x70, 0x47, 0x00, 0x00, 0x68, 0xCC, 0x00,
+ 0x00, 0x40, 0xF1, 0xFF, 0x0F, 0x00, 0xDC, 0x00,
+ 0x00, 0x3C, 0x01, 0x00, 0x20, 0x90, 0xDD, 0x00,
+ 0x00, 0x88, 0xDF, 0x00, 0x00,
+ 0x00, 0x00, 0x8E, 0x00, 0x80, 0x89, 0x00, 0x00,
+ 0x20, 0x96, 0x02, 0x00, 0x20, 0xEA, 0x00, 0x00,
+ 0x20, 0x98, 0x02, 0x00, 0x20, 0x00, 0xE2, 0x00,
+ 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x48, 0x80,
+ 0x6A, 0x00, 0x28, 0x00, 0xD0, 0x01, 0x20, 0xFE,
+ 0x49, 0x0B, 0x30, 0x08, 0x83, 0xFD, 0x48, 0xC0,
+ 0x7C, 0xC0, 0x07, 0x00, 0xD0, 0x02, 0x20, 0x0A,
+ 0x8B, 0x80, 0x18, 0x48, 0x83, 0x70, 0x47, 0xF8,
+ 0xB5, 0xF7, 0x4D, 0x00, 0x26, 0xAE, 0x83, 0xFF,
+ 0xF7, 0xE9, 0xFF, 0x04, 0xF0, 0xC3, 0xFF, 0x08,
+ 0x20, 0x04, 0xF0, 0xEA, 0xFF, 0x04, 0xF0, 0xB3,
+ 0xFF, 0x20, 0x21, 0x0A, 0x20, 0x04, 0xF0, 0xF1,
+ 0xFF, 0x40, 0x21, 0x02, 0x20, 0x04, 0xF0, 0xED,
+ 0xFF, 0x00, 0x21, 0x03, 0x20, 0x04, 0xF0, 0xE9,
+ 0xFF, 0x00, 0x21, 0x04, 0x20, 0x04, 0xF0, 0xE5,
+ 0xFF, 0x00, 0x21, 0x05, 0x20, 0x04, 0xF0, 0xE1,
+ 0xFF, 0x00, 0x21, 0x06, 0x20,
+ 0x00, 0x00, 0x8F, 0x00, 0x80, 0x04, 0xF0, 0xDD,
+ 0xFF, 0x00, 0x21, 0x07, 0x20, 0x04, 0xF0, 0xD9,
+ 0xFF, 0x00, 0x21, 0x08, 0x20, 0x04, 0xF0, 0xD5,
+ 0xFF, 0x00, 0x21, 0x09, 0x20, 0x04, 0xF0, 0xD1,
+ 0xFF, 0x0B, 0x24, 0x01, 0x27, 0x7F, 0x02, 0xA0,
+ 0xB2, 0x00, 0x21, 0x04, 0xF0, 0xCA, 0xFF, 0x64,
+ 0x1C, 0xBC, 0x42, 0xF8, 0xD3, 0x01, 0xF0, 0xAA,
+ 0xFA, 0x6E, 0x74, 0x00, 0x20, 0xDA, 0x4B, 0xEE,
+ 0x73, 0x1F, 0x21, 0x0E, 0x22, 0x42, 0x43, 0xD2,
+ 0x18, 0x40, 0x1C, 0xC0, 0xB2, 0xD1, 0x72, 0x0B,
+ 0x28, 0xF7, 0xD3, 0xD6, 0x48, 0x00, 0x78, 0x00,
+ 0x28, 0x04, 0xD0, 0x03, 0xF0, 0x8A, 0xFC, 0x00,
+ 0x20, 0x04, 0xF0, 0x7F, 0xFE, 0xD2, 0x49, 0x68,
+ 0x7B, 0x08, 0x70, 0x6E, 0x71, 0x01, 0x20, 0x28,
+ 0x70, 0xD0, 0x48, 0xAE, 0x73, 0x06, 0x80, 0xD0,
+ 0x48, 0x06, 0x80, 0x00, 0xF0, 0x57, 0xFD, 0x02,
+ 0x20, 0xE8, 0x72, 0x01, 0xF0,
+ 0x00, 0x00, 0x90, 0x00, 0x80, 0x47, 0xF9, 0x28,
+ 0x62, 0xCC, 0x48, 0x40, 0x68, 0xCC, 0x49, 0x08,
+ 0x60, 0xE8, 0x8A, 0x01, 0xF0, 0xB3, 0xF9, 0xF8,
+ 0xBD, 0xCA, 0x49, 0x00, 0x20, 0x08, 0x70, 0x8E,
+ 0xE7, 0x70, 0xB5, 0x01, 0x25, 0x01, 0xF0, 0x36,
+ 0xF9, 0x06, 0x46, 0xC7, 0x48, 0x04, 0x78, 0xBB,
+ 0x48, 0x80, 0x6A, 0x00, 0x28, 0x06, 0xD0, 0x05,
+ 0xF0, 0xBB, 0xF8, 0x00, 0x28, 0x00, 0xD0, 0x01,
+ 0x20, 0x00, 0x19, 0xC4, 0xB2, 0xC1, 0x4A, 0xB6,
+ 0x49, 0x00, 0x2C, 0x02, 0xD1, 0x10, 0x78, 0x40,
+ 0x07, 0x00, 0xD4, 0x0E, 0x62, 0x88, 0x7A, 0x01,
+ 0x28, 0x05, 0xD1, 0x88, 0x7B, 0x04, 0x43, 0x21,
+ 0xD1, 0x00, 0xF0, 0x24, 0xFD, 0x1E, 0xE0, 0x02,
+ 0x28, 0x0E, 0xD1, 0x00, 0x2C, 0x11, 0xD1, 0x10,
+ 0x78, 0x40, 0x07, 0x17, 0xD5, 0x08, 0x6A, 0x4A,
+ 0x8A, 0x30, 0x1A, 0x90, 0x42, 0x12, 0xD9, 0x03,
+ 0x20, 0x88, 0x72, 0x88, 0x8A,
+ 0x00, 0x00, 0x91, 0x00, 0x80, 0xC8, 0x82, 0x0D,
+ 0xE0, 0x03, 0x28, 0x09, 0xD1, 0x48, 0x78, 0x04,
+ 0x43, 0x03, 0xD0, 0x00, 0x25, 0x00, 0xF0, 0x10,
+ 0xFD, 0x04, 0xE0, 0x10, 0x78, 0x40, 0x07, 0x01,
+ 0xD4, 0x00, 0x25, 0xDD, 0xE7, 0x28, 0x46, 0x70,
+ 0xBD, 0xF0, 0xB5, 0x9D, 0x4A, 0x89, 0xB0, 0x11,
+ 0x7A, 0xA7, 0x4F, 0x49, 0x43, 0x05, 0x91, 0x51,
+ 0x7A, 0x49, 0x43, 0x04, 0x91, 0x39, 0x78, 0x88,
+ 0x42, 0x00, 0xD9, 0x08, 0x46, 0x00, 0x25, 0x29,
+ 0x46, 0xFF, 0x22, 0x6B, 0x46, 0x5A, 0x54, 0x49,
+ 0x1C, 0xC9, 0xB2, 0x0E, 0x29, 0xFA, 0xD9, 0x00,
+ 0x21, 0x97, 0x4E, 0x0F, 0xE0, 0x0E, 0x22, 0x9D,
+ 0x4B, 0x4A, 0x43, 0xD2, 0x18, 0xD2, 0x7A, 0x01,
+ 0x23, 0xD2, 0x06, 0xD2, 0x0E, 0x93, 0x40, 0x34,
+ 0x88, 0x1D, 0x43, 0x1C, 0x43, 0x34, 0x80, 0x6C,
+ 0x46, 0xA1, 0x54, 0x49, 0x1C, 0x81, 0x42, 0xED,
+ 0xD3, 0x8C, 0x49, 0x32, 0x88,
+ 0x00, 0x00, 0x92, 0x00, 0x80, 0x08, 0x88, 0x10,
+ 0x40, 0x00, 0x24, 0x08, 0x80, 0x26, 0x46, 0x71,
+ 0xE0, 0x0E, 0x20, 0x85, 0x49, 0x70, 0x43, 0x41,
+ 0x18, 0xC8, 0x7A, 0xC3, 0x43, 0xDB, 0x06, 0x6D,
+ 0xD0, 0x42, 0x06, 0x92, 0x0F, 0x03, 0x2A, 0x5C,
+ 0xD0, 0xC7, 0x06, 0xFF, 0x0E, 0x01, 0x20, 0xB8,
+ 0x40, 0x85, 0x43, 0x08, 0x90, 0x68, 0x46, 0xC0,
+ 0x5D, 0xFF, 0x28, 0x15, 0xD1, 0xB4, 0x42, 0x06,
+ 0xD0, 0x79, 0x4A, 0x0E, 0x20, 0x60, 0x43, 0x80,
+ 0x18, 0x0E, 0x22, 0x07, 0xF0, 0xEB, 0xFF, 0x60,
+ 0x20, 0x07, 0x43, 0x0E, 0x20, 0x74, 0x49, 0x60,
+ 0x43, 0x40, 0x18, 0xC7, 0x72, 0x75, 0x48, 0x08,
+ 0x9A, 0x01, 0x88, 0x91, 0x43, 0x01, 0x80, 0x3A,
+ 0xE0, 0x0E, 0x22, 0x50, 0x43, 0x79, 0x4A, 0x83,
+ 0x18, 0x58, 0x88, 0x4A, 0x88, 0x9C, 0x46, 0x82,
+ 0x1A, 0x98, 0x88, 0x96, 0x46, 0x8A, 0x88, 0x68,
+ 0x4B, 0x80, 0x1A, 0x72, 0x46,
+ 0x00, 0x00, 0x93, 0x00, 0x80, 0x52, 0x43, 0x40,
+ 0x43, 0x10, 0x18, 0x86, 0x46, 0x9B, 0x8B, 0x08,
+ 0x9A, 0x04, 0x98, 0x1A, 0x42, 0x00, 0xD1, 0x05,
+ 0x98, 0x70, 0x45, 0x12, 0xD8, 0x0E, 0x20, 0x62,
+ 0x49, 0x60, 0x43, 0x40, 0x18, 0x0E, 0x22, 0x61,
+ 0x46, 0x07, 0x90, 0x07, 0xF0, 0xBB, 0xFF, 0x40,
+ 0x20, 0x07, 0x43, 0x07, 0x98, 0x5A, 0x49, 0xC7,
+ 0x72, 0x8A, 0x8B, 0x08, 0x98, 0x10, 0x43, 0x88,
+ 0x83, 0x0D, 0xE0, 0xB4, 0x42, 0x06, 0xD0, 0x58,
+ 0x4A, 0x0E, 0x20, 0x60, 0x43, 0x80, 0x18, 0x0E,
+ 0x22, 0x07, 0xF0, 0xA8, 0xFF, 0x0E, 0x20, 0x54,
+ 0x49, 0x60, 0x43, 0x40, 0x18, 0xC7, 0x72, 0x64,
+ 0x1C, 0x07, 0xE0, 0xC0, 0x06, 0xC0, 0x0E, 0x01,
+ 0x22, 0x52, 0x49, 0x82, 0x40, 0x08, 0x88, 0x90,
+ 0x43, 0x08, 0x80, 0x76, 0x1C, 0x56, 0x4A, 0x10,
+ 0x78, 0x86, 0x42, 0x89, 0xD3, 0x00, 0x26, 0x26,
+ 0xE0, 0xE8, 0x07, 0x21, 0xD0,
+ 0x00, 0x00, 0x94, 0x00, 0x80, 0x68, 0x46, 0x80,
+ 0x5D, 0x0E, 0x21, 0x48, 0x43, 0x51, 0x49, 0x01,
+ 0x23, 0x40, 0x18, 0x06, 0x90, 0x82, 0x88, 0x41,
+ 0x88, 0x30, 0x46, 0xFC, 0xF7, 0x09, 0xFD, 0x00,
+ 0x28, 0x12, 0xD1, 0x0E, 0x20, 0x40, 0x49, 0x60,
+ 0x43, 0x47, 0x18, 0x0E, 0x22, 0x38, 0x46, 0x06,
+ 0x99, 0x07, 0xF0, 0x78, 0xFF, 0x20, 0x20, 0x30,
+ 0x43, 0x39, 0x49, 0xF8, 0x72, 0x01, 0x22, 0x88,
+ 0x8B, 0xB2, 0x40, 0x90, 0x43, 0x88, 0x83, 0x64,
+ 0x1C, 0x76, 0x1C, 0xF6, 0xB2, 0x6D, 0x08, 0x00,
+ 0x2D, 0x03, 0xD0, 0x3F, 0x48, 0x00, 0x78, 0x84,
+ 0x42, 0xD2, 0xD3, 0x31, 0x48, 0x3C, 0x49, 0x04,
+ 0x74, 0x31, 0x4B, 0x1F, 0x20, 0x0A, 0x78, 0x04,
+ 0xE0, 0x0E, 0x21, 0x61, 0x43, 0xC9, 0x18, 0xC8,
+ 0x72, 0x64, 0x1C, 0x94, 0x42, 0xF8, 0xD3, 0x09,
+ 0xB0, 0xF0, 0xBD, 0xF1, 0xB5, 0x28, 0x4D, 0x82,
+ 0xB0, 0x28, 0x78, 0x00, 0x28,
+ 0x00, 0x00, 0x95, 0x00, 0x80, 0x02, 0xD0, 0x00,
+ 0x20, 0x28, 0x70, 0x01, 0x20, 0x01, 0x90, 0x2E,
+ 0x48, 0x04, 0x78, 0x2F, 0x48, 0x00, 0x78, 0x84,
+ 0x42, 0x00, 0xD9, 0x04, 0x46, 0x1F, 0x4E, 0xB0,
+ 0x6A, 0x2D, 0x4F, 0x00, 0x28, 0x1B, 0xD0, 0x04,
+ 0xF0, 0x83, 0xFF, 0xB2, 0x6A, 0x2B, 0x49, 0x91,
+ 0x40, 0x88, 0x43, 0xF0, 0x21, 0x01, 0x40, 0x00,
+ 0x90, 0x00, 0x07, 0x09, 0x01, 0x00, 0x0F, 0x08,
+ 0x18, 0x0C, 0x21, 0x01, 0x40, 0x03, 0x22, 0x10,
+ 0x40, 0x89, 0x00, 0x08, 0x18, 0x22, 0x21, 0x01,
+ 0x40, 0x11, 0x22, 0x49, 0x00, 0x10, 0x40, 0x08,
+ 0x18, 0x39, 0x68, 0xC8, 0x72, 0x01, 0xE0, 0x00,
+ 0x20, 0x00, 0x90, 0xE9, 0x78, 0x00, 0x98, 0x81,
+ 0x42, 0x01, 0xD0, 0x01, 0x20, 0x01, 0x90, 0x00,
+ 0x98, 0x1B, 0x4A, 0xE8, 0x70, 0x10, 0x78, 0x1B,
+ 0x49, 0x40, 0x06, 0x40, 0x0F, 0x02, 0x28, 0x03,
+ 0xD1, 0x0B, 0x88, 0x9B, 0x06,
+ 0x00, 0x00, 0x96, 0x00, 0x80, 0x00, 0xD4, 0x00,
+ 0x24, 0x04, 0x28, 0x03, 0xD1, 0x08, 0x88, 0x40,
+ 0x06, 0x00, 0xD4, 0x00, 0x24, 0xE0, 0xB2, 0xFF,
+ 0xF7, 0xC7, 0xFE, 0x25, 0xE0, 0x88, 0xDF, 0x00,
+ 0x00, 0xD0, 0x00, 0x00, 0x20, 0x20, 0xDC, 0x00,
+ 0x00, 0x2A, 0x04, 0x00, 0x20, 0x2A, 0x01, 0x00,
+ 0x20, 0x32, 0x02, 0x00, 0x20, 0x84, 0x00, 0x00,
+ 0x20, 0x86, 0x00, 0x00, 0x20, 0x00, 0x04, 0x01,
+ 0x40, 0x4C, 0x01, 0x00, 0x20, 0x3E, 0x01, 0x00,
+ 0x20, 0x92, 0x00, 0x00, 0x20, 0x40, 0x01, 0x00,
+ 0x20, 0x96, 0x02, 0x00, 0x20, 0x4C, 0x03, 0x00,
+ 0x20, 0x80, 0x02, 0x00, 0x20, 0xFF, 0xFF, 0x00,
+ 0x00, 0x31, 0x02, 0x00, 0x20, 0x98, 0x02, 0x00,
+ 0x20, 0xFE, 0x48, 0x02, 0x78, 0x50, 0x06, 0x40,
+ 0x0F, 0x05, 0xD1, 0xFD, 0x48, 0x00, 0x78, 0x00,
+ 0x28, 0x02, 0xD0, 0x01, 0x20, 0x00, 0xE0, 0x00,
+ 0x20, 0x29, 0x7C, 0x00, 0x28,
+ 0x00, 0x00, 0x97, 0x00, 0x80, 0x02, 0xD1, 0x52,
+ 0x00, 0x0A, 0x43, 0x09, 0xE0, 0x20, 0x22, 0x0A,
+ 0x43, 0xF6, 0x49, 0x49, 0x7F, 0xC9, 0x06, 0x89,
+ 0x0F, 0x03, 0x29, 0x01, 0xD1, 0x01, 0x21, 0x01,
+ 0x91, 0xA9, 0x78, 0x81, 0x42, 0x07, 0xD0, 0xF1,
+ 0x49, 0x49, 0x7F, 0xC9, 0x06, 0x89, 0x0F, 0x01,
+ 0xD0, 0x01, 0x21, 0x01, 0x91, 0xA8, 0x70, 0xD1,
+ 0xB2, 0x68, 0x8B, 0x00, 0xF0, 0x83, 0xFB, 0x68,
+ 0x8B, 0x40, 0x1C, 0x84, 0xB2, 0x28, 0x7C, 0xC1,
+ 0x00, 0x40, 0x18, 0xE9, 0x49, 0x00, 0x19, 0x09,
+ 0x38, 0x09, 0x68, 0x00, 0x27, 0x48, 0x72, 0x30,
+ 0xE0, 0x0E, 0x20, 0xE6, 0x49, 0x78, 0x43, 0x45,
+ 0x18, 0x69, 0x88, 0x20, 0x46, 0x00, 0xF0, 0x73,
+ 0xFB, 0xA0, 0x1C, 0xA9, 0x88, 0x80, 0xB2, 0x00,
+ 0xF0, 0x6E, 0xFB, 0x20, 0x1D, 0xA9, 0x79, 0x80,
+ 0xB2, 0x00, 0xF0, 0x64, 0xFB, 0xA0, 0x1D, 0xE9,
+ 0x79, 0x80, 0xB2, 0x00, 0xF0,
+ 0x00, 0x00, 0x98, 0x00, 0x80, 0x5F, 0xFB, 0xE0,
+ 0x1D, 0x29, 0x7A, 0x80, 0xB2, 0x00, 0xF0, 0x5A,
+ 0xFB, 0x20, 0x46, 0x08, 0x30, 0x69, 0x7A, 0x80,
+ 0xB2, 0x00, 0xF0, 0x54, 0xFB, 0xD4, 0x4A, 0x61,
+ 0x1D, 0x12, 0x68, 0x89, 0xB2, 0xE8, 0x7A, 0x51,
+ 0x18, 0x08, 0x70, 0x60, 0x21, 0x08, 0x42, 0x01,
+ 0xD0, 0x01, 0x20, 0x01, 0x90, 0x09, 0x34, 0xA4,
+ 0xB2, 0x7F, 0x1C, 0xCF, 0x48, 0x00, 0x7C, 0x87,
+ 0x42, 0xCA, 0xD3, 0xCE, 0x48, 0xCC, 0x4D, 0x00,
+ 0x78, 0x68, 0x74, 0x28, 0x7C, 0xE9, 0x7B, 0x88,
+ 0x42, 0x01, 0xD0, 0x01, 0x21, 0x01, 0x91, 0xE8,
+ 0x73, 0xC4, 0x48, 0x20, 0x30, 0xC0, 0x7C, 0xC0,
+ 0x07, 0x23, 0xD0, 0xC7, 0x48, 0x01, 0x78, 0x01,
+ 0x20, 0xCA, 0x08, 0x4B, 0x07, 0x5B, 0x0F, 0x98,
+ 0x40, 0xBE, 0x4B, 0xC0, 0xB2, 0x9A, 0x18, 0x20,
+ 0x32, 0x12, 0x7D, 0x02, 0x42, 0x28, 0x8B, 0x09,
+ 0xD1, 0x00, 0xF0, 0x20, 0xFB,
+ 0x00, 0x00, 0x99, 0x00, 0x80, 0x28, 0x8B, 0xBF,
+ 0x49, 0x40, 0x1C, 0x80, 0xB2, 0x09, 0x78, 0x00,
+ 0xF0, 0x19, 0xFB, 0x0A, 0xE0, 0xB6, 0x49, 0x0A,
+ 0x68, 0x10, 0x18, 0x00, 0x22, 0x02, 0x70, 0x28,
+ 0x8B, 0x09, 0x68, 0x40, 0x1C, 0x80, 0xB2, 0x08,
+ 0x18, 0x02, 0x70, 0xB0, 0x6A, 0x00, 0x28, 0x26,
+ 0xD0, 0xB5, 0x48, 0x29, 0x7C, 0x00, 0x78, 0x40,
+ 0x1A, 0xC1, 0x00, 0x40, 0x18, 0x00, 0x19, 0x00,
+ 0x21, 0x80, 0xB2, 0x01, 0x22, 0x18, 0xE0, 0x00,
+ 0x9B, 0x13, 0x42, 0x0C, 0xD0, 0xAF, 0x4B, 0x1B,
+ 0x6A, 0x01, 0x2B, 0x01, 0xD1, 0xAE, 0x4B, 0x00,
+ 0xE0, 0xAE, 0x4B, 0xA5, 0x4C, 0x5B, 0x5C, 0x24,
+ 0x68, 0x24, 0x18, 0x23, 0x70, 0x04, 0xE0, 0xA2,
+ 0x4B, 0x1B, 0x68, 0x1B, 0x18, 0x00, 0x24, 0x1C,
+ 0x70, 0x40, 0x1C, 0x49, 0x1C, 0x80, 0xB2, 0x52,
+ 0x00, 0xB3, 0x6A, 0x8B, 0x42, 0xE3, 0xD8, 0x9E,
+ 0x48, 0x00, 0x79, 0x00, 0x28,
+ 0x00, 0x00, 0x9A, 0x00, 0x80, 0x70, 0xD0, 0x01,
+ 0x20, 0x01, 0x90, 0xB1, 0x6A, 0x9A, 0x48, 0x40,
+ 0x8B, 0x09, 0x18, 0x9D, 0x48, 0x00, 0x78, 0xC2,
+ 0x00, 0x80, 0x18, 0x40, 0x1C, 0x08, 0x18, 0x85,
+ 0xB2, 0x00, 0x27, 0x95, 0x49, 0x78, 0x00, 0x24,
+ 0x31, 0x08, 0x5A, 0x9B, 0x49, 0x44, 0x05, 0x64,
+ 0x0D, 0x8C, 0x42, 0xE7, 0xD0, 0x03, 0x21, 0x89,
+ 0x03, 0x08, 0x40, 0x42, 0xD0, 0x01, 0x21, 0x89,
+ 0x03, 0x40, 0x1A, 0x52, 0xD0, 0x40, 0x1A, 0x70,
+ 0xD0, 0x40, 0x1A, 0x39, 0xD1, 0x30, 0x6A, 0xA0,
+ 0x42, 0x36, 0xD9, 0x92, 0x49, 0x60, 0x00, 0x09,
+ 0x5A, 0x28, 0x46, 0x00, 0xF0, 0xB8, 0xFA, 0x90,
+ 0x48, 0x00, 0x57, 0x81, 0xB2, 0x28, 0x46, 0x32,
+ 0x30, 0x80, 0xB2, 0x00, 0xF0, 0xB0, 0xFA, 0x8D,
+ 0x48, 0x00, 0x57, 0x81, 0xB2, 0x28, 0x46, 0x64,
+ 0x30, 0x80, 0xB2, 0x00, 0xF0, 0xA8, 0xFA, 0xAD,
+ 0x1C, 0x7F, 0x1C, 0xAD, 0xB2,
+ 0x00, 0x00, 0x9B, 0x00, 0x80, 0x19, 0x2F, 0x74,
+ 0xD2, 0xB0, 0x69, 0x84, 0x49, 0x00, 0x19, 0x40,
+ 0x00, 0x09, 0x5A, 0x28, 0x46, 0x00, 0xF0, 0x9B,
+ 0xFA, 0xB0, 0x69, 0x81, 0x49, 0x09, 0x19, 0x40,
+ 0x56, 0x81, 0xB2, 0x28, 0x46, 0x32, 0x30, 0x80,
+ 0xB2, 0x00, 0xF0, 0x91, 0xFA, 0xB0, 0x69, 0x7D,
+ 0x49, 0x09, 0x19, 0x40, 0x56, 0x81, 0xB2, 0x28,
+ 0x46, 0x64, 0x30, 0x80, 0xB2, 0x00, 0xF0, 0x87,
+ 0xFA, 0x57, 0xE0, 0x70, 0x6A, 0xA0, 0x42, 0x54,
+ 0xD9, 0x77, 0x48, 0x00, 0x57, 0x81, 0xB2, 0x28,
+ 0x46, 0x00, 0xF0, 0x7D, 0xFA, 0x75, 0x48, 0x00,
+ 0x57, 0x81, 0xB2, 0x28, 0x46, 0x32, 0x30, 0x80,
+ 0xB2, 0x00, 0xF0, 0x75, 0xFA, 0x72, 0x48, 0x1E,
+ 0xE0, 0x49, 0xE0, 0x20, 0x46, 0x03, 0x21, 0x49,
+ 0x02, 0x08, 0x40, 0x24, 0x07, 0xB1, 0x6A, 0x24,
+ 0x0F, 0xA1, 0x42, 0x3A, 0xD9, 0x00, 0x28, 0x15,
+ 0xD0, 0xFF, 0x38, 0xFF, 0x38,
+ 0x00, 0x00, 0x9C, 0x00, 0x80, 0x02, 0x38, 0x34,
+ 0xD1, 0x6A, 0x49, 0x60, 0x00, 0x09, 0x5A, 0x28,
+ 0x46, 0x00, 0xF0, 0x5D, 0xFA, 0x68, 0x48, 0x00,
+ 0x57, 0x81, 0xB2, 0x28, 0x46, 0x32, 0x30, 0x80,
+ 0xB2, 0x00, 0xF0, 0x55, 0xFA, 0x5B, 0x48, 0x00,
+ 0x57, 0xC4, 0xE7, 0x0F, 0xE0, 0x63, 0x49, 0x60,
+ 0x00, 0x09, 0x5A, 0x28, 0x46, 0x00, 0xF0, 0x4B,
+ 0xFA, 0x61, 0x48, 0x00, 0x57, 0x81, 0xB2, 0x28,
+ 0x46, 0x32, 0x30, 0x80, 0xB2, 0x00, 0xF0, 0x43,
+ 0xFA, 0x51, 0x48, 0xEC, 0xE7, 0x30, 0x6A, 0xA0,
+ 0x42, 0x0F, 0xD9, 0x5C, 0x49, 0x60, 0x00, 0x09,
+ 0x5A, 0x28, 0x46, 0x00, 0xF0, 0x38, 0xFA, 0x5A,
+ 0x48, 0x00, 0x57, 0x81, 0xB2, 0x28, 0x46, 0x32,
+ 0x30, 0x80, 0xB2, 0x00, 0xF0, 0x30, 0xFA, 0x57,
+ 0x48, 0xD9, 0xE7, 0xAD, 0x1C, 0x7F, 0x1C, 0xAD,
+ 0xB2, 0x19, 0x2F, 0x00, 0xD2, 0x51, 0xE7, 0x02,
+ 0x99, 0x00, 0x20, 0xC9, 0x06,
+ 0x00, 0x00, 0x9D, 0x00, 0x80, 0x00, 0xD5, 0x04,
+ 0x20, 0x02, 0x99, 0x89, 0x06, 0x00, 0xD5, 0x08,
+ 0x20, 0x02, 0x99, 0x49, 0x06, 0x00, 0xD5, 0x0C,
+ 0x20, 0x02, 0x99, 0x09, 0x06, 0x00, 0xD5, 0x10,
+ 0x20, 0x02, 0x99, 0xC9, 0x05, 0x01, 0xD5, 0x1C,
+ 0x20, 0x01, 0xE0, 0x1C, 0x28, 0x05, 0xD1, 0x32,
+ 0x49, 0x4A, 0x79, 0x00, 0x2A, 0x09, 0xD1, 0x01,
+ 0x22, 0x04, 0xE0, 0x2F, 0x49, 0x4A, 0x79, 0x01,
+ 0x2A, 0x03, 0xD1, 0x00, 0x22, 0x4A, 0x71, 0x01,
+ 0x21, 0x01, 0x91, 0x2B, 0x49, 0xE3, 0x23, 0x0A,
+ 0x7B, 0x1A, 0x40, 0x02, 0x43, 0x0A, 0x73, 0x01,
+ 0x98, 0x00, 0x28, 0x02, 0xD0, 0x08, 0x7B, 0x40,
+ 0x30, 0x08, 0x73, 0x08, 0x7B, 0xDC, 0x21, 0x08,
+ 0x40, 0x21, 0x49, 0x09, 0x68, 0x88, 0x72, 0x01,
+ 0x98, 0xFE, 0xBD, 0x10, 0xB5, 0x20, 0x49, 0x70,
+ 0x22, 0x48, 0x7B, 0x03, 0x46, 0x13, 0x40, 0x8F,
+ 0x22, 0x20, 0x2B, 0x01, 0xD9,
+ 0x00, 0x00, 0x9E, 0x00, 0x80, 0x10, 0x40, 0x48,
+ 0x73, 0x48, 0x7B, 0x03, 0x06, 0x08, 0xD5, 0x30,
+ 0x4B, 0x1B, 0x88, 0x1B, 0x06, 0x5B, 0x0F, 0x03,
+ 0xD1, 0x40, 0x06, 0x40, 0x0E, 0x10, 0x40, 0x48,
+ 0x73, 0x8A, 0x79, 0xFA, 0x20, 0xFA, 0x2A, 0x00,
+ 0xD9, 0x88, 0x71, 0xCA, 0x79, 0xFA, 0x2A, 0x00,
+ 0xD9, 0xC8, 0x71, 0x8A, 0x8A, 0x88, 0x79, 0x82,
+ 0x42, 0x00, 0xD2, 0x88, 0x82, 0x8A, 0x8A, 0xC8,
+ 0x79, 0x82, 0x42, 0x00, 0xD2, 0x88, 0x82, 0x8A,
+ 0x8A, 0x7D, 0x20, 0xC0, 0x00, 0x82, 0x42, 0x00,
+ 0xD9, 0x88, 0x82, 0x4A, 0x8A, 0x1F, 0x48, 0x82,
+ 0x42, 0x00, 0xD9, 0x48, 0x82, 0x00, 0xF0, 0x72,
+ 0xFF, 0x10, 0xBD, 0x00, 0x00, 0x31, 0x02, 0x00,
+ 0x20, 0x93, 0x00, 0x00, 0x20, 0x00, 0xDC, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x20, 0x2A, 0x04, 0x00,
+ 0x20, 0xD0, 0x00, 0x00, 0x20, 0x92, 0x00, 0x00,
+ 0x20, 0x84, 0x02, 0x00, 0x20,
+ 0x00, 0x00, 0x9F, 0x00, 0x80, 0xC9, 0x02, 0x00,
+ 0x20, 0x96, 0x02, 0x00, 0x20, 0xC8, 0xDF, 0x00,
+ 0x00, 0x10, 0x02, 0x00, 0x20, 0x0C, 0x02, 0x00,
+ 0x20, 0xFF, 0x07, 0x00, 0x00, 0xC0, 0x0C, 0x00,
+ 0x20, 0xCE, 0x0D, 0x00, 0x20, 0x74, 0x0D, 0x00,
+ 0x20, 0x74, 0x05, 0x00, 0x20, 0x8B, 0x0A, 0x00,
+ 0x20, 0x64, 0x08, 0x00, 0x20, 0x1C, 0x02, 0x00,
+ 0x20, 0x14, 0x02, 0x00, 0x20, 0x24, 0x02, 0x00,
+ 0x20, 0x18, 0x02, 0x00, 0x20, 0x6E, 0x07, 0x00,
+ 0x20, 0x85, 0x0C, 0x00, 0x20, 0x5E, 0x0A, 0x00,
+ 0x20, 0x98, 0x02, 0x00, 0x20, 0x60, 0xEA, 0x00,
+ 0x00, 0x70, 0xB5, 0x03, 0x20, 0x04, 0xF0, 0xB5,
+ 0xFB, 0x05, 0x46, 0x04, 0x20, 0x04, 0xF0, 0xB1,
+ 0xFB, 0x02, 0x46, 0x01, 0x24, 0xEA, 0x48, 0x00,
+ 0x21, 0xCB, 0x00, 0xC3, 0x5C, 0xAB, 0x42, 0x23,
+ 0xD1, 0xC9, 0x00, 0x08, 0x18, 0x45, 0x68, 0x40,
+ 0x78, 0x00, 0x24, 0x90, 0x42,
+ 0x00, 0x00, 0xA0, 0x00, 0x80, 0x1A, 0xD1, 0x01,
+ 0x2A, 0x0E, 0xD0, 0x02, 0x2A, 0x11, 0xD0, 0x04,
+ 0x2A, 0x14, 0xD1, 0x07, 0x20, 0x04, 0xF0, 0xAA,
+ 0xFB, 0x06, 0x46, 0x05, 0x20, 0x04, 0xF0, 0xA6,
+ 0xFB, 0x00, 0x04, 0x30, 0x18, 0x28, 0x60, 0x0F,
+ 0xE0, 0x05, 0x20, 0x04, 0xF0, 0x8E, 0xFB, 0x28,
+ 0x70, 0x0A, 0xE0, 0x05, 0x20, 0x04, 0xF0, 0x9A,
+ 0xFB, 0x28, 0x80, 0x05, 0xE0, 0x01, 0x24, 0x03,
+ 0xE0, 0x49, 0x1C, 0xC9, 0xB2, 0x09, 0x29, 0xD3,
+ 0xD9, 0xFF, 0xF7, 0x53, 0xFF, 0x00, 0x2C, 0x04,
+ 0xD0, 0x00, 0x21, 0x04, 0x20, 0x04, 0xF0, 0x75,
+ 0xFB, 0x70, 0xBD, 0xD0, 0x48, 0xD0, 0x49, 0x00,
+ 0x68, 0x09, 0x78, 0x00, 0x22, 0x40, 0x18, 0xCF,
+ 0x49, 0x20, 0x38, 0x40, 0x7F, 0x8A, 0x5E, 0xCE,
+ 0x49, 0x80, 0x18, 0x48, 0x60, 0xCD, 0x4A, 0x91,
+ 0x7A, 0xD0, 0x79, 0x01, 0x29, 0x01, 0xD1, 0x90,
+ 0x79, 0x02, 0xE0, 0x03, 0x29,
+ 0x00, 0x00, 0xA1, 0x00, 0x80, 0x00, 0xD1, 0x90,
+ 0x8A, 0xC9, 0x49, 0x09, 0x68, 0x88, 0x42, 0xE3,
+ 0xD0, 0x80, 0xB2, 0x00, 0xF0, 0x73, 0xFD, 0x70,
+ 0xBD, 0x70, 0xB5, 0x02, 0x20, 0x04, 0xF0, 0x55,
+ 0xFB, 0x04, 0x46, 0x40, 0x06, 0x58, 0xD4, 0x01,
+ 0xE0, 0x00, 0xF0, 0xBC, 0xFD, 0x04, 0xF0, 0x67,
+ 0xFB, 0x00, 0x28, 0xF9, 0xD1, 0xA0, 0x06, 0x80,
+ 0x0E, 0x03, 0x28, 0x2A, 0xD0, 0x06, 0xDC, 0x00,
+ 0x28, 0x3A, 0xD0, 0x02, 0x28, 0x36, 0xD1, 0x00,
+ 0xF0, 0x09, 0xF9, 0x35, 0xE0, 0x05, 0x28, 0x23,
+ 0xD0, 0x25, 0x28, 0x2F, 0xD1, 0x02, 0xF0, 0x18,
+ 0xF8, 0x01, 0x46, 0x03, 0x20, 0x04, 0xF0, 0x3B,
+ 0xFB, 0x02, 0xF0, 0x15, 0xF8, 0x01, 0x46, 0x05,
+ 0x20, 0x04, 0xF0, 0x2B, 0xFB, 0x02, 0xF0, 0x13,
+ 0xF8, 0x01, 0x46, 0x06, 0x20, 0x04, 0xF0, 0x25,
+ 0xFB, 0x02, 0xF0, 0x11, 0xF8, 0x01, 0x46, 0x07,
+ 0x20, 0x04, 0xF0, 0x1F, 0xFB,
+ 0x00, 0x00, 0xA2, 0x00, 0x80, 0x02, 0xF0, 0x14,
+ 0xF8, 0x01, 0x46, 0x08, 0x20, 0x04, 0xF0, 0x19,
+ 0xFB, 0x12, 0xE0, 0xFF, 0xF7, 0x61, 0xFF, 0x0F,
+ 0xE0, 0xA6, 0x49, 0xA7, 0x48, 0x04, 0xF0, 0x66,
+ 0xFC, 0x05, 0x46, 0x00, 0x21, 0x03, 0x20, 0x04,
+ 0xF0, 0x0C, 0xFB, 0x29, 0x46, 0x04, 0x20, 0x04,
+ 0xF0, 0x12, 0xFB, 0x01, 0xE0, 0xA4, 0x09, 0xA4,
+ 0x01, 0xA0, 0x48, 0x80, 0x22, 0x01, 0x78, 0x51,
+ 0x40, 0x01, 0x70, 0xC8, 0xB2, 0xC1, 0x09, 0xC9,
+ 0x01, 0x21, 0x43, 0x40, 0x20, 0x01, 0x43, 0x02,
+ 0x20, 0x04, 0xF0, 0xF7, 0xFA, 0x01, 0x20, 0x70,
+ 0xBD, 0x00, 0x20, 0x70, 0xBD, 0x70, 0xB5, 0x98,
+ 0x4D, 0x98, 0x4C, 0x28, 0x78, 0x80, 0x07, 0x15,
+ 0xD5, 0x20, 0x78, 0x00, 0x28, 0x01, 0xD0, 0x03,
+ 0xF0, 0x38, 0xF9, 0x00, 0xF0, 0x6F, 0xFD, 0x28,
+ 0x78, 0xFD, 0x21, 0x08, 0x40, 0x28, 0x70, 0xC1,
+ 0xB2, 0x00, 0x20, 0x04, 0xF0,
+ 0x00, 0x00, 0xA3, 0x00, 0x80, 0xDE, 0xFA, 0x20,
+ 0x78, 0x00, 0x28, 0x01, 0xD0, 0x03, 0xF0, 0xCC,
+ 0xF8, 0xFF, 0xF7, 0xD5, 0xFA, 0x8C, 0x4D, 0x28,
+ 0x78, 0xC0, 0x07, 0x01, 0xD0, 0x04, 0xF0, 0xBC,
+ 0xFA, 0x28, 0x78, 0x00, 0x28, 0x03, 0xD1, 0x00,
+ 0xF0, 0x51, 0xF9, 0x04, 0xF0, 0x07, 0xFA, 0x20,
+ 0x78, 0x7E, 0x4E, 0x00, 0x28, 0x04, 0xD0, 0x30,
+ 0x78, 0x00, 0x28, 0x01, 0xD1, 0x00, 0xF0, 0xC2,
+ 0xF8, 0xFF, 0xF7, 0x6A, 0xFF, 0x00, 0x28, 0x01,
+ 0xD0, 0x01, 0x20, 0xB0, 0x73, 0x28, 0x78, 0x00,
+ 0x07, 0x01, 0xD5, 0x04, 0xF0, 0xA1, 0xFA, 0xB0,
+ 0x7B, 0x00, 0x28, 0x04, 0xD0, 0x28, 0x78, 0x00,
+ 0x28, 0x01, 0xD1, 0x00, 0xF0, 0xFB, 0xF8, 0x04,
+ 0xF0, 0xE2, 0xFA, 0x78, 0x49, 0x08, 0x69, 0x04,
+ 0x22, 0x90, 0x43, 0x08, 0x61, 0x76, 0x48, 0x81,
+ 0x68, 0x89, 0x07, 0xFC, 0xD5, 0x20, 0x78, 0x00,
+ 0x28, 0x24, 0xD0, 0x72, 0xB6,
+ 0x00, 0x00, 0xA4, 0x00, 0x80, 0x00, 0xF0, 0x46,
+ 0xFC, 0x03, 0xF0, 0xF2, 0xF8, 0x84, 0xB2, 0xE0,
+ 0x07, 0x05, 0xD1, 0x62, 0xB6, 0x6F, 0x48, 0x80,
+ 0x6A, 0x00, 0x28, 0x0F, 0xD0, 0x06, 0xE0, 0xBF,
+ 0xF3, 0x50, 0x8F, 0xBF, 0xF3, 0x60, 0x8F, 0x30,
+ 0xBF, 0x62, 0xB6, 0xEA, 0xE7, 0x72, 0xB6, 0x00,
+ 0xF0, 0x31, 0xFC, 0x07, 0xF0, 0x0E, 0xFA, 0xC0,
+ 0x07, 0x30, 0xD1, 0x62, 0xB6, 0x28, 0x78, 0x80,
+ 0x07, 0x01, 0xD5, 0x04, 0xF0, 0x69, 0xFA, 0x20,
+ 0x46, 0xFF, 0xF7, 0x17, 0xFC, 0xB0, 0x73, 0x04,
+ 0xF0, 0xC6, 0xFA, 0x58, 0x48, 0x20, 0x30, 0x00,
+ 0x78, 0x7D, 0x21, 0xC9, 0x00, 0x48, 0x43, 0x00,
+ 0xF0, 0x88, 0xFD, 0x00, 0x28, 0x04, 0xD0, 0x28,
+ 0x78, 0x40, 0x07, 0x01, 0xD5, 0x04, 0xF0, 0x54,
+ 0xFA, 0xFF, 0xF7, 0xD6, 0xFA, 0x04, 0x46, 0x28,
+ 0x78, 0xC0, 0x09, 0x01, 0xD0, 0x04, 0xF0, 0x4C,
+ 0xFA, 0x00, 0x2C, 0x01, 0xD0,
+ 0x00, 0x00, 0xA5, 0x00, 0x80, 0x00, 0xF0, 0xA2,
+ 0xFC, 0xF0, 0x7A, 0xB1, 0x7A, 0x88, 0x42, 0x04,
+ 0xD0, 0xF0, 0x8A, 0x00, 0xF0, 0x73, 0xFC, 0xB0,
+ 0x7A, 0xF0, 0x72, 0x70, 0xBD, 0xBF, 0xF3, 0x50,
+ 0x8F, 0xBF, 0xF3, 0x60, 0x8F, 0x30, 0xBF, 0x62,
+ 0xB6, 0xC0, 0xE7, 0x70, 0x47, 0x3F, 0x48, 0x02,
+ 0x21, 0x81, 0x72, 0xC1, 0x79, 0xC1, 0x82, 0x70,
+ 0x47, 0x3C, 0x48, 0x01, 0x21, 0x81, 0x72, 0x81,
+ 0x79, 0xC1, 0x82, 0x70, 0x47, 0x44, 0x4A, 0x12,
+ 0x68, 0x10, 0x18, 0x01, 0x70, 0x70, 0x47, 0x42,
+ 0x4A, 0x12, 0x68, 0x10, 0x18, 0x0A, 0x0A, 0x02,
+ 0x70, 0x41, 0x70, 0x70, 0x47, 0x70, 0xB5, 0x03,
+ 0x20, 0x04, 0xF0, 0x33, 0xFA, 0x01, 0x23, 0x2C,
+ 0x4A, 0x00, 0x21, 0xCC, 0x00, 0x14, 0x5D, 0x84,
+ 0x42, 0x1D, 0xD1, 0xC8, 0x00, 0x80, 0x18, 0x45,
+ 0x78, 0x44, 0x68, 0x29, 0x46, 0x04, 0x20, 0x04,
+ 0xF0, 0x20, 0xFA, 0x01, 0x2D,
+ 0x00, 0x00, 0xA6, 0x00, 0x80, 0x0D, 0xD0, 0x02,
+ 0x2D, 0x0E, 0xD0, 0x04, 0x2D, 0x15, 0xD1, 0x24,
+ 0x68, 0x05, 0x20, 0x21, 0x0C, 0x04, 0xF0, 0x1F,
+ 0xFA, 0xA1, 0xB2, 0x07, 0x20, 0x04, 0xF0, 0x1B,
+ 0xFA, 0x70, 0xBD, 0x21, 0x78, 0x05, 0x20, 0x0A,
+ 0xE0, 0x21, 0x88, 0x05, 0x20, 0xF6, 0xE7, 0x49,
+ 0x1C, 0xC9, 0xB2, 0x09, 0x29, 0xD9, 0xD9, 0x00,
+ 0x2B, 0xF2, 0xD0, 0x00, 0x21, 0x04, 0x20, 0x04,
+ 0xF0, 0x00, 0xFA, 0x70, 0xBD, 0x70, 0xB5, 0x24,
+ 0x48, 0x62, 0x26, 0x05, 0x68, 0x17, 0x48, 0x01,
+ 0x79, 0x00, 0x29, 0x00, 0xD0, 0xF8, 0x26, 0x01,
+ 0x7B, 0x20, 0x20, 0x01, 0x43, 0x0A, 0x20, 0x04,
+ 0xF0, 0xF0, 0xF9, 0x01, 0xE0, 0x00, 0xF0, 0x5E,
+ 0xFC, 0x04, 0xF0, 0x09, 0xFA, 0x00, 0x28, 0xF9,
+ 0xD1, 0x0B, 0x24, 0x0B, 0x36, 0x05, 0xE0, 0x29,
+ 0x5D, 0x20, 0x46, 0x04, 0xF0, 0xE2, 0xF9, 0x64,
+ 0x1C, 0xA4, 0xB2, 0xB4, 0x42,
+ 0x00, 0x00, 0xA7, 0x00, 0x80, 0xF7, 0xD3, 0x69,
+ 0x7A, 0x09, 0x20, 0x04, 0xF0, 0xDA, 0xF9, 0xA9,
+ 0x7A, 0x0A, 0x20, 0x04, 0xF0, 0xD6, 0xF9, 0x70,
+ 0xBD, 0xCC, 0xCC, 0x00, 0x00, 0x68, 0x01, 0x00,
+ 0x20, 0x64, 0x01, 0x00, 0x20, 0x66, 0x01, 0x00,
+ 0x20, 0x00, 0xFF, 0x01, 0x40, 0xD0, 0x00, 0x00,
+ 0x20, 0x60, 0x01, 0x00, 0x20, 0x00, 0xDC, 0x00,
+ 0x00, 0xFC, 0x05, 0x00, 0x00, 0x3E, 0x01, 0x00,
+ 0x20, 0x40, 0x01, 0x00, 0x20, 0x2A, 0x01, 0x00,
+ 0x20, 0x3F, 0x01, 0x00, 0x20, 0x00, 0xED, 0x00,
+ 0xE0, 0x00, 0x00, 0x12, 0x40, 0x88, 0xDF, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x20, 0x70, 0xB5, 0x04,
+ 0xF0, 0xED, 0xF8, 0x00, 0x20, 0x04, 0xF0, 0xB1,
+ 0xF9, 0xC0, 0x09, 0xC0, 0x01, 0xFF, 0x4E, 0x70,
+ 0x70, 0x00, 0x20, 0x30, 0x70, 0xFE, 0x4C, 0x60,
+ 0x7F, 0x80, 0x07, 0x80, 0x0F, 0x01, 0x28, 0x1A,
+ 0xD0, 0x02, 0x28, 0x1D, 0xD1,
+ 0x00, 0x00, 0xA8, 0x00, 0x80, 0x04, 0xF0, 0x7F,
+ 0xF9, 0x30, 0x24, 0x0B, 0x25, 0x00, 0xF0, 0x0A,
+ 0xFC, 0x00, 0x20, 0x04, 0xF0, 0x9A, 0xF9, 0x01,
+ 0x46, 0xF2, 0x78, 0x21, 0x40, 0x91, 0x42, 0x07,
+ 0xD1, 0x01, 0x46, 0x29, 0x42, 0x04, 0xD1, 0xC0,
+ 0x09, 0x71, 0x78, 0xC0, 0x01, 0x88, 0x42, 0xED,
+ 0xD0, 0x04, 0xF0, 0xC4, 0xF8, 0x70, 0xBD, 0x01,
+ 0x20, 0x30, 0x70, 0x00, 0xF0, 0x2B, 0xFB, 0xF0,
+ 0x60, 0x04, 0xF0, 0x61, 0xF9, 0x20, 0x7F, 0x00,
+ 0xF0, 0xA3, 0xFC, 0xF1, 0xE7, 0xF8, 0xB5, 0xE7,
+ 0x4C, 0x20, 0x78, 0x00, 0x28, 0x20, 0xD0, 0xE6,
+ 0x48, 0xC1, 0x7F, 0x80, 0x7F, 0x0D, 0x02, 0x05,
+ 0x43, 0x30, 0x26, 0x0B, 0x27, 0x00, 0xF0, 0xDE,
+ 0xFB, 0x00, 0x20, 0x04, 0xF0, 0x6E, 0xF9, 0x01,
+ 0x46, 0xE2, 0x78, 0x31, 0x40, 0x91, 0x42, 0x0D,
+ 0xD1, 0x01, 0x46, 0x39, 0x42, 0x0A, 0xD1, 0xC0,
+ 0x09, 0x61, 0x78, 0xC0, 0x01,
+ 0x00, 0x00, 0xA9, 0x00, 0x80, 0x88, 0x42, 0x05,
+ 0xD1, 0x00, 0xF0, 0x04, 0xFB, 0xE1, 0x68, 0x40,
+ 0x1A, 0xA8, 0x42, 0xE7, 0xD9, 0x00, 0x20, 0x20,
+ 0x70, 0xF8, 0xBD, 0x10, 0xB5, 0x04, 0xF0, 0x2C,
+ 0xF8, 0xD4, 0x4B, 0x00, 0x21, 0xD3, 0x4A, 0x5C,
+ 0x33, 0x8C, 0x00, 0x04, 0x59, 0x10, 0xC2, 0x49,
+ 0x1C, 0x89, 0xB2, 0x9A, 0x42, 0xF8, 0xD3, 0xCF,
+ 0x4A, 0xCE, 0x4B, 0x64, 0x32, 0xE8, 0x33, 0x8C,
+ 0x00, 0x04, 0x59, 0x10, 0xC2, 0x49, 0x1C, 0x89,
+ 0xB2, 0x9A, 0x42, 0xF8, 0xD9, 0x8A, 0x00, 0xCA,
+ 0x4B, 0x82, 0x58, 0xDA, 0x60, 0x49, 0x1C, 0x89,
+ 0xB2, 0x8A, 0x00, 0x83, 0x58, 0xC7, 0x4A, 0x53,
+ 0x60, 0x49, 0x1C, 0x09, 0x04, 0x89, 0x0B, 0x40,
+ 0x58, 0xD0, 0x60, 0x10, 0xBD, 0xF8, 0xB5, 0x82,
+ 0x00, 0x0C, 0x46, 0xC3, 0x48, 0x00, 0x27, 0x1C,
+ 0x21, 0x15, 0x18, 0x29, 0x60, 0xC0, 0x4A, 0xA0,
+ 0x00, 0x86, 0x18, 0xFF, 0x2C,
+ 0x00, 0x00, 0xAA, 0x00, 0x80, 0x00, 0xD0, 0x31,
+ 0x60, 0x0A, 0x20, 0xFE, 0xF7, 0x51, 0xF8, 0x10,
+ 0x20, 0x28, 0x60, 0x23, 0x20, 0xFE, 0xF7, 0x4C,
+ 0xF8, 0xB6, 0x48, 0x01, 0x68, 0x02, 0x03, 0x11,
+ 0x43, 0x01, 0x60, 0xC1, 0x68, 0x09, 0x06, 0xFC,
+ 0xD5, 0x80, 0x21, 0xC1, 0x60, 0x00, 0x20, 0x28,
+ 0x60, 0xFF, 0x2C, 0x00, 0xD0, 0x30, 0x60, 0xAF,
+ 0x48, 0xC0, 0x30, 0xC0, 0x68, 0xAB, 0x49, 0xFF,
+ 0x38, 0x06, 0x22, 0xFF, 0x38, 0x8A, 0x5E, 0x02,
+ 0x38, 0x50, 0x43, 0x00, 0x28, 0x00, 0xDA, 0x40,
+ 0x42, 0x09, 0x69, 0x88, 0x42, 0x00, 0xD9, 0x01,
+ 0x27, 0x38, 0x46, 0xF8, 0xBD, 0x70, 0xB5, 0x03,
+ 0xF0, 0xCB, 0xFF, 0xA2, 0x4C, 0xA7, 0x4A, 0x21,
+ 0x89, 0x00, 0x20, 0x43, 0x00, 0xD3, 0x5A, 0x8B,
+ 0x42, 0x03, 0xD8, 0x40, 0x1C, 0xC0, 0xB2, 0x20,
+ 0x28, 0xF7, 0xD3, 0x20, 0x28, 0x01, 0xD1, 0x1F,
+ 0x20, 0x01, 0xE0, 0x00, 0x28,
+ 0x00, 0x00, 0xAB, 0x00, 0x80, 0x0C, 0xD0, 0x43,
+ 0x00, 0x9D, 0x18, 0x20, 0x3D, 0xED, 0x8B, 0xD3,
+ 0x5A, 0x4D, 0x1B, 0x59, 0x1A, 0xAD, 0xB2, 0x89,
+ 0xB2, 0x8D, 0x42, 0x01, 0xD2, 0x40, 0x1E, 0xC0,
+ 0xB2, 0x41, 0x00, 0x51, 0x5A, 0x21, 0x81, 0x53,
+ 0x21, 0x93, 0x4A, 0x49, 0x06, 0xD1, 0x60, 0x91,
+ 0x4D, 0x95, 0x49, 0x69, 0x61, 0x8F, 0x4A, 0x95,
+ 0x49, 0x40, 0x32, 0x51, 0x62, 0x01, 0x04, 0x94,
+ 0x48, 0x01, 0x43, 0x8C, 0x48, 0x80, 0x30, 0x81,
+ 0x63, 0x92, 0x49, 0xC1, 0x60, 0xC1, 0x6B, 0x89,
+ 0x09, 0x89, 0x01, 0xC1, 0x63, 0x87, 0x4E, 0x90,
+ 0x48, 0xC0, 0x36, 0x70, 0x60, 0x03, 0x20, 0xB0,
+ 0x60, 0x8E, 0x48, 0x30, 0x61, 0x8E, 0x48, 0x30,
+ 0x62, 0x00, 0x21, 0xB1, 0x61, 0x29, 0x61, 0x8D,
+ 0x48, 0x28, 0x60, 0x28, 0x68, 0x40, 0x00, 0xFC,
+ 0xD4, 0x01, 0x22, 0x80, 0x48, 0xD2, 0x07, 0x42,
+ 0x60, 0x89, 0x4A, 0xC2, 0x60,
+ 0x00, 0x00, 0xAC, 0x00, 0x80, 0x7E, 0x4B, 0x00,
+ 0x20, 0x82, 0x00, 0xD2, 0x18, 0x11, 0x60, 0x40,
+ 0x1C, 0xC0, 0xB2, 0x41, 0x28, 0xF8, 0xD3, 0x28,
+ 0x69, 0x80, 0x21, 0x88, 0x43, 0x28, 0x61, 0x70,
+ 0x68, 0x78, 0x49, 0x00, 0x07, 0xC0, 0x0E, 0x40,
+ 0x31, 0x08, 0x5E, 0x21, 0x89, 0x07, 0xF0, 0xF5,
+ 0xF9, 0xE0, 0x80, 0x70, 0xBD, 0x70, 0xB5, 0x03,
+ 0xF0, 0x5F, 0xFF, 0x6E, 0x4B, 0x00, 0x21, 0x6D,
+ 0x4A, 0x5C, 0x33, 0x10, 0xCA, 0x8D, 0x00, 0x49,
+ 0x1C, 0x44, 0x51, 0x89, 0xB2, 0x9A, 0x42, 0xF8,
+ 0xD3, 0x68, 0x4A, 0x68, 0x4B, 0x64, 0x32, 0xE8,
+ 0x33, 0x10, 0xCA, 0x8D, 0x00, 0x49, 0x1C, 0x44,
+ 0x51, 0x89, 0xB2, 0x9A, 0x42, 0xF8, 0xD9, 0x64,
+ 0x4A, 0xD2, 0x68, 0x8B, 0x00, 0xC2, 0x50, 0x63,
+ 0x4A, 0x49, 0x1C, 0x53, 0x68, 0x89, 0xB2, 0x8C,
+ 0x00, 0x03, 0x51, 0x49, 0x1C, 0xD2, 0x68, 0x09,
+ 0x04, 0x89, 0x0B, 0x42, 0x50,
+ 0x00, 0x00, 0xAD, 0x00, 0x80, 0x70, 0xBD, 0xF0,
+ 0xB5, 0x85, 0xB0, 0x00, 0x20, 0x02, 0x90, 0x58,
+ 0x48, 0x20, 0x30, 0xC1, 0x79, 0x83, 0x79, 0x0A,
+ 0x02, 0x54, 0x49, 0x1A, 0x43, 0x0A, 0x81, 0x42,
+ 0x79, 0x03, 0x79, 0x10, 0x02, 0x18, 0x43, 0x08,
+ 0x61, 0xFF, 0xF7, 0xC4, 0xFF, 0xFF, 0xF7, 0x56,
+ 0xFF, 0x00, 0x20, 0x01, 0x46, 0x5D, 0x4A, 0x11,
+ 0x54, 0x40, 0x1C, 0xC0, 0xB2, 0x09, 0x28, 0xF9,
+ 0xD3, 0x00, 0x25, 0x68, 0x1C, 0xC4, 0xB2, 0x03,
+ 0x90, 0x28, 0xE0, 0xEE, 0x08, 0xE7, 0x08, 0x6A,
+ 0x07, 0x01, 0x21, 0x52, 0x0F, 0x08, 0x46, 0x90,
+ 0x40, 0xC2, 0xB2, 0x60, 0x07, 0x40, 0x0F, 0x81,
+ 0x40, 0xC8, 0xB2, 0x53, 0x49, 0x01, 0x92, 0x00,
+ 0x90, 0x88, 0x5D, 0x10, 0x42, 0x14, 0xD0, 0xC8,
+ 0x5D, 0x00, 0x99, 0x08, 0x42, 0x10, 0xD0, 0x21,
+ 0x46, 0x28, 0x46, 0xFF, 0xF7, 0xF7, 0xFE, 0x00,
+ 0x28, 0x0A, 0xD0, 0x4A, 0x48,
+ 0x00, 0x00, 0xAE, 0x00, 0x80, 0x01, 0x9A, 0x81,
+ 0x5D, 0x11, 0x43, 0x81, 0x55, 0xC1, 0x5D, 0x00,
+ 0x9A, 0x11, 0x43, 0xC1, 0x55, 0x01, 0x20, 0x02,
+ 0x90, 0x64, 0x1C, 0xE4, 0xB2, 0x41, 0x2C, 0xD4,
+ 0xD3, 0x00, 0xF0, 0x80, 0xFA, 0x03, 0x98, 0xC5,
+ 0xB2, 0x41, 0x2D, 0xCA, 0xD3, 0xFF, 0xF7, 0xB5,
+ 0xFE, 0x02, 0x98, 0x05, 0xB0, 0xF0, 0xBD, 0xF8,
+ 0xB5, 0x2D, 0x48, 0x00, 0x26, 0x20, 0x30, 0x41,
+ 0x7A, 0x03, 0x7A, 0x0A, 0x02, 0x29, 0x49, 0x1A,
+ 0x43, 0x0A, 0x81, 0x42, 0x79, 0x03, 0x79, 0x10,
+ 0x02, 0x18, 0x43, 0x08, 0x61, 0xFF, 0xF7, 0x6E,
+ 0xFF, 0xFF, 0xF7, 0x00, 0xFF, 0x00, 0x20, 0x33,
+ 0x49, 0x02, 0x46, 0x0A, 0x54, 0x40, 0x1C, 0xC0,
+ 0xB2, 0x09, 0x28, 0xFA, 0xD3, 0x00, 0x24, 0xE5,
+ 0x08, 0x61, 0x07, 0x49, 0x0F, 0x01, 0x20, 0x88,
+ 0x40, 0xC7, 0xB2, 0x2D, 0x48, 0x40, 0x5D, 0x38,
+ 0x42, 0x0A, 0xD0, 0xFF, 0x21,
+ 0x00, 0x00, 0xAF, 0x00, 0x80, 0x20, 0x46, 0xFF,
+ 0xF7, 0xB1, 0xFE, 0x00, 0x28, 0x04, 0xD0, 0x27,
+ 0x48, 0x41, 0x5D, 0x39, 0x43, 0x41, 0x55, 0x01,
+ 0x26, 0x64, 0x1C, 0xE4, 0xB2, 0x41, 0x2C, 0xE6,
+ 0xD3, 0xFF, 0xF7, 0x7B, 0xFE, 0x30, 0x46, 0xF8,
+ 0xBD, 0xF8, 0xB5, 0x09, 0x21, 0x20, 0x48, 0x07,
+ 0xF0, 0x16, 0xF9, 0x00, 0x20, 0x1E, 0x4C, 0x1F,
+ 0x4F, 0x1F, 0x4E, 0x0A, 0xE0, 0x3A, 0x5C, 0xD1,
+ 0x08, 0x55, 0x07, 0x6D, 0x0F, 0x63, 0x5C, 0x01,
+ 0x22, 0xAA, 0x40, 0x13, 0x43, 0x40, 0x1C, 0x63,
+ 0x54, 0xC0, 0xB2, 0x31, 0x6A, 0x81, 0x42, 0xF1,
+ 0xD8, 0x15, 0x48, 0xFF, 0xF7, 0xAC, 0xFF, 0x13,
+ 0x4D, 0x06, 0x46, 0x00, 0x21, 0x68, 0x5C, 0x6A,
+ 0x18, 0x50, 0x72, 0x27, 0xE0, 0x28, 0x01, 0x00,
+ 0x20, 0x00, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x11,
+ 0x40, 0x00, 0x00, 0x01, 0x40, 0x00, 0x00, 0x03,
+ 0x40, 0x00, 0x04, 0x11, 0x40,
+ 0x00, 0x00, 0xB0, 0x00, 0x80, 0x1C, 0xCD, 0x00,
+ 0x00, 0xFF, 0x01, 0x3A, 0xC0, 0x3A, 0xA0, 0x00,
+ 0xF0, 0x40, 0x03, 0x00, 0x40, 0x01, 0x00, 0x03,
+ 0xC0, 0x72, 0x40, 0x00, 0x80, 0x10, 0x0D, 0xCA,
+ 0x98, 0x00, 0x02, 0x00, 0x80, 0x00, 0x03, 0x00,
+ 0xC0, 0x51, 0x08, 0x00, 0x00, 0x0F, 0x04, 0x00,
+ 0x20, 0x06, 0x04, 0x00, 0x20, 0xC0, 0xE0, 0x00,
+ 0x00, 0x88, 0xDF, 0x00, 0x00, 0x49, 0x1C, 0xC9,
+ 0xB2, 0x09, 0x29, 0xCF, 0xD3, 0x7B, 0x48, 0xFF,
+ 0xF7, 0x1E, 0xFF, 0x30, 0x43, 0x01, 0x46, 0x00,
+ 0x20, 0x2A, 0x5C, 0x2B, 0x18, 0x9A, 0x74, 0x22,
+ 0x5C, 0x2A, 0x54, 0x40, 0x1C, 0xC0, 0xB2, 0x09,
+ 0x28, 0xF6, 0xD3, 0x08, 0x46, 0xF8, 0xBD, 0x10,
+ 0xB5, 0x73, 0x48, 0x74, 0x4A, 0x01, 0x88, 0x10,
+ 0x46, 0x8B, 0x05, 0x80, 0x30, 0x00, 0x2B, 0x12,
+ 0xDB, 0xC3, 0x1D, 0xF9, 0x33, 0x1B, 0x69, 0x00,
+ 0x2B, 0x25, 0xD1, 0x53, 0x68,
+ 0x00, 0x00, 0xB1, 0x00, 0x80, 0x9B, 0x06, 0x22,
+ 0xD1, 0x93, 0x6D, 0x9B, 0x06, 0x1F, 0xD1, 0xC3,
+ 0x6A, 0x9B, 0x06, 0x1C, 0xD1, 0x13, 0x46, 0xC0,
+ 0x33, 0xDB, 0x6B, 0x9B, 0x06, 0x17, 0xD1, 0xC9,
+ 0x05, 0x17, 0xD4, 0xD3, 0x68, 0xF0, 0x21, 0x0B,
+ 0x40, 0x40, 0x2B, 0x10, 0xD8, 0x12, 0x6E, 0x0A,
+ 0x40, 0x40, 0x2A, 0x0C, 0xD8, 0x40, 0x6B, 0x08,
+ 0x40, 0x40, 0x28, 0x08, 0xD8, 0x60, 0x48, 0x40,
+ 0x68, 0x08, 0x40, 0x40, 0x28, 0x03, 0xD8, 0xFB,
+ 0xF7, 0x2C, 0xFE, 0x04, 0x28, 0x01, 0xD9, 0x01,
+ 0x20, 0x10, 0xBD, 0x00, 0x20, 0x10, 0xBD, 0x10,
+ 0xB5, 0x5A, 0x49, 0x5B, 0x48, 0x04, 0xF0, 0x86,
+ 0xF8, 0x5A, 0x49, 0x09, 0x88, 0x88, 0x42, 0x01,
+ 0xD0, 0x01, 0x20, 0x10, 0xBD, 0x00, 0x20, 0x10,
+ 0xBD, 0x10, 0xB5, 0x57, 0x48, 0x00, 0x24, 0x01,
+ 0x68, 0xEF, 0x22, 0x11, 0x40, 0x01, 0x29, 0x00,
+ 0xD1, 0x01, 0x24, 0xFF, 0x21,
+ 0x00, 0x00, 0xB2, 0x00, 0x80, 0x01, 0x60, 0x04,
+ 0xF0, 0x8F, 0xF8, 0xFF, 0xF7, 0xE4, 0xFF, 0x00,
+ 0x28, 0x11, 0xD1, 0x02, 0x20, 0x04, 0x43, 0xFF,
+ 0xF7, 0xA6, 0xFF, 0x00, 0x28, 0x0B, 0xD1, 0x01,
+ 0x20, 0x40, 0x02, 0x04, 0x43, 0xFF, 0xF7, 0x40,
+ 0xFF, 0x00, 0x28, 0x04, 0xD1, 0xFF, 0x21, 0x20,
+ 0x46, 0x05, 0x31, 0x08, 0x43, 0x10, 0xBD, 0x20,
+ 0x46, 0x10, 0xBD, 0xF0, 0xB5, 0x16, 0x26, 0x0F,
+ 0x46, 0x05, 0x46, 0x77, 0x43, 0x00, 0x20, 0xCE,
+ 0x00, 0x89, 0x19, 0x04, 0x46, 0x49, 0x19, 0x41,
+ 0x4D, 0xED, 0x5B, 0x01, 0x26, 0xA6, 0x40, 0x35,
+ 0x42, 0x07, 0xD0, 0x0D, 0x19, 0x2D, 0x7B, 0xAA,
+ 0x42, 0x01, 0xD3, 0xAB, 0x42, 0x01, 0xD9, 0x40,
+ 0x1C, 0x80, 0xB2, 0x64, 0x1C, 0x08, 0x2C, 0xEE,
+ 0xD3, 0xF0, 0xBD, 0xF8, 0xB5, 0x0D, 0x46, 0x00,
+ 0x26, 0x03, 0xF0, 0xBE, 0xFD, 0x01, 0x21, 0x89,
+ 0x02, 0x00, 0x90, 0x07, 0xF0,
+ 0x00, 0x00, 0xB3, 0x00, 0x80, 0x2C, 0xF8, 0x35,
+ 0x49, 0x33, 0x48, 0x08, 0x60, 0x00, 0x2D, 0x01,
+ 0xD0, 0x01, 0x23, 0x00, 0xE0, 0x00, 0x23, 0x2B,
+ 0x4C, 0x20, 0x34, 0x61, 0x7C, 0x20, 0x7C, 0x00,
+ 0x9A, 0x06, 0xF0, 0x3A, 0xFC, 0x00, 0x2D, 0x01,
+ 0xD0, 0x01, 0x23, 0x00, 0xE0, 0x00, 0x23, 0xE1,
+ 0x7B, 0xA0, 0x7B, 0x00, 0x9A, 0x06, 0xF0, 0x02,
+ 0xFB, 0x21, 0x4F, 0x00, 0x25, 0x40, 0x37, 0x08,
+ 0xE0, 0xA3, 0x7A, 0xE2, 0x7A, 0x29, 0x46, 0x00,
+ 0x98, 0xFF, 0xF7, 0xB7, 0xFF, 0x80, 0x19, 0x86,
+ 0xB2, 0x6D, 0x1C, 0xF8, 0x6A, 0xA8, 0x42, 0xF3,
+ 0xD8, 0xF8, 0x6A, 0xB9, 0x6B, 0x40, 0x18, 0xF9,
+ 0x6B, 0x23, 0x7B, 0x41, 0x18, 0x62, 0x7B, 0x00,
+ 0x98, 0xFF, 0xF7, 0xA7, 0xFF, 0x80, 0x19, 0xC0,
+ 0xB2, 0xF8, 0xBD, 0x70, 0xB5, 0x04, 0x46, 0x13,
+ 0x49, 0x13, 0x48, 0x03, 0xF0, 0xF7, 0xFF, 0x01,
+ 0x46, 0x05, 0x20, 0x03, 0xF0,
+ 0x00, 0x00, 0xB4, 0x00, 0x80, 0xA8, 0xFE, 0x11,
+ 0x48, 0x01, 0x88, 0x07, 0x20, 0x03, 0xF0, 0xA3,
+ 0xFE, 0x13, 0x4D, 0xA8, 0x78, 0x00, 0x28, 0x09,
+ 0xD0, 0x20, 0x46, 0xFF, 0xF7, 0x8C, 0xFE, 0x20,
+ 0x46, 0xFF, 0xF7, 0x31, 0xFE, 0x00, 0x21, 0x20,
+ 0x46, 0xFF, 0xF7, 0xA3, 0xFF, 0xA8, 0x88, 0xC0,
+ 0xB2, 0x70, 0xBD, 0x00, 0x00, 0x06, 0x04, 0x00,
+ 0x20, 0x98, 0x02, 0x00, 0x20, 0x48, 0xDE, 0x00,
+ 0x00, 0x48, 0xDF, 0x00, 0x00, 0x00, 0xDC, 0x00,
+ 0x00, 0xFC, 0x05, 0x00, 0x00, 0xFC, 0xE1, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x40, 0x2C, 0xE1, 0x00,
+ 0x00, 0x80, 0xE2, 0x00, 0x00, 0x3C, 0x03, 0x00,
+ 0x20, 0x28, 0x01, 0x00, 0x20, 0x70, 0xB5, 0xDF,
+ 0x4C, 0x25, 0x69, 0x61, 0x69, 0x40, 0x1B, 0x00,
+ 0x02, 0x0E, 0x46, 0x06, 0xF0, 0xC8, 0xFF, 0xFF,
+ 0x28, 0x09, 0xD9, 0x01, 0x0A, 0x0A, 0x46, 0x72,
+ 0x43, 0x52, 0x19, 0x22, 0x61,
+ 0x00, 0x00, 0xB5, 0x00, 0x80, 0xE2, 0x68, 0x09,
+ 0x02, 0x52, 0x18, 0x40, 0x1A, 0xE2, 0x60, 0xE1,
+ 0x68, 0x08, 0x18, 0x70, 0xBD, 0xD4, 0x48, 0x40,
+ 0x68, 0xE4, 0xE7, 0xF8, 0xB5, 0xD3, 0x4C, 0x21,
+ 0x88, 0xD0, 0x4D, 0x28, 0x88, 0x06, 0x46, 0x06,
+ 0xF0, 0xAE, 0xFF, 0x21, 0x88, 0x41, 0x43, 0xB1,
+ 0x42, 0x00, 0xD2, 0x40, 0x1C, 0x03, 0x28, 0x00,
+ 0xD2, 0x03, 0x20, 0x21, 0x88, 0x6A, 0x69, 0x51,
+ 0x43, 0x09, 0x0A, 0xCB, 0x4A, 0x49, 0x1E, 0x91,
+ 0x42, 0x00, 0xD9, 0x11, 0x46, 0x06, 0x04, 0x0E,
+ 0x43, 0x03, 0xF0, 0x84, 0xFF, 0xC7, 0x4B, 0x05,
+ 0x46, 0x19, 0x68, 0x03, 0x27, 0xBF, 0x03, 0x01,
+ 0x20, 0xB9, 0x43, 0x80, 0x03, 0x08, 0x43, 0x18,
+ 0x60, 0x01, 0x20, 0xC0, 0x03, 0x08, 0x43, 0x18,
+ 0x60, 0xBD, 0x4C, 0x20, 0x69, 0xFF, 0x22, 0x02,
+ 0x32, 0x90, 0x43, 0xBF, 0x4A, 0x10, 0x43, 0x20,
+ 0x61, 0xBE, 0x48, 0x22, 0x69,
+ 0x00, 0x00, 0xB6, 0x00, 0x80, 0x02, 0x42, 0xFC,
+ 0xD1, 0xBD, 0x4A, 0x04, 0x20, 0x10, 0x60, 0xA6,
+ 0x60, 0xBC, 0x48, 0xE0, 0x60, 0xBC, 0x48, 0x20,
+ 0x61, 0x46, 0x00, 0x20, 0x69, 0x32, 0x46, 0x82,
+ 0x43, 0xFB, 0xD1, 0x39, 0x43, 0x19, 0x60, 0xB9,
+ 0x49, 0x02, 0x20, 0xFD, 0xF7, 0x53, 0xFD, 0x03,
+ 0x21, 0x02, 0x20, 0xFD, 0xF7, 0x59, 0xFD, 0x02,
+ 0x20, 0xFD, 0xF7, 0x66, 0xFD, 0xB4, 0x49, 0x20,
+ 0x69, 0x08, 0x42, 0xFC, 0xD1, 0xB3, 0x49, 0x00,
+ 0x20, 0x08, 0x70, 0xE8, 0xB2, 0x03, 0xF0, 0x4A,
+ 0xFF, 0xF8, 0xBD, 0xA6, 0x49, 0x00, 0x28, 0x01,
+ 0xD1, 0x01, 0x20, 0x05, 0xE0, 0x4B, 0x22, 0x12,
+ 0x01, 0x90, 0x42, 0x01, 0xD9, 0x0A, 0x80, 0x00,
+ 0xE0, 0x08, 0x80, 0x96, 0xE7, 0xA0, 0x49, 0x9D,
+ 0x4A, 0x88, 0x42, 0x01, 0xD9, 0x11, 0x80, 0x00,
+ 0xE0, 0x10, 0x80, 0x8E, 0xE7, 0x10, 0xB5, 0x04,
+ 0x46, 0x40, 0x00, 0x20, 0x18,
+ 0x00, 0x00, 0xB7, 0x00, 0x80, 0xC8, 0x28, 0x00,
+ 0xD2, 0xC8, 0x20, 0xFF, 0xF7, 0xEF, 0xFF, 0x95,
+ 0x49, 0x20, 0x46, 0x8C, 0x61, 0xFF, 0xF7, 0xDD,
+ 0xFF, 0x10, 0xBD, 0x1C, 0xB5, 0x68, 0x46, 0x03,
+ 0xF0, 0xA0, 0xFF, 0x00, 0x28, 0xFA, 0xD1, 0x6B,
+ 0x46, 0x19, 0x79, 0x01, 0x20, 0x80, 0x07, 0x21,
+ 0x29, 0x02, 0xD3, 0x99, 0x49, 0x49, 0x8A, 0xC1,
+ 0x60, 0x01, 0x68, 0x49, 0x00, 0x49, 0x08, 0x01,
+ 0x60, 0x96, 0x48, 0x01, 0x69, 0x04, 0x22, 0x11,
+ 0x43, 0x01, 0x61, 0x1C, 0xBD, 0x10, 0xB5, 0x03,
+ 0xF0, 0xDB, 0xFD, 0x03, 0xF0, 0x89, 0xFC, 0xFF,
+ 0xF7, 0xE0, 0xFF, 0x72, 0xB6, 0x90, 0x48, 0x81,
+ 0x68, 0x89, 0x07, 0xFC, 0xD5, 0x62, 0xB6, 0x72,
+ 0xB6, 0x8A, 0x4C, 0x20, 0x78, 0x00, 0x28, 0x0B,
+ 0xD1, 0x06, 0xE0, 0xBF, 0xF3, 0x50, 0x8F, 0xBF,
+ 0xF3, 0x60, 0x8F, 0x30, 0xBF, 0x62, 0xB6, 0x72,
+ 0xB6, 0x20, 0x78, 0x00, 0x28,
+ 0x00, 0x00, 0xB8, 0x00, 0x80, 0xF5, 0xD0, 0x01,
+ 0xE0, 0xFF, 0xF7, 0x47, 0xFF, 0x00, 0x20, 0x20,
+ 0x70, 0x75, 0x48, 0x40, 0x68, 0x73, 0x49, 0x48,
+ 0x60, 0x62, 0xB6, 0x03, 0xF0, 0x69, 0xFC, 0x03,
+ 0xF0, 0xC7, 0xFD, 0x10, 0xBD, 0x70, 0xB5, 0x03,
+ 0xF0, 0xD9, 0xFE, 0x72, 0x4A, 0x11, 0x68, 0x03,
+ 0x23, 0x9B, 0x03, 0x01, 0x24, 0x99, 0x43, 0xA4,
+ 0x03, 0x0C, 0x43, 0x14, 0x60, 0x01, 0x24, 0xE4,
+ 0x03, 0x0C, 0x43, 0x14, 0x60, 0x68, 0x4D, 0x77,
+ 0x4C, 0x2C, 0x61, 0x19, 0x43, 0x11, 0x60, 0x03,
+ 0xF0, 0xC9, 0xFE, 0x70, 0xBD, 0x10, 0xB5, 0x72,
+ 0xB6, 0x7D, 0x20, 0xC0, 0x00, 0xFF, 0xF7, 0x79,
+ 0xFF, 0x00, 0xF0, 0xB1, 0xF8, 0x63, 0x4C, 0x06,
+ 0x20, 0x60, 0x60, 0x00, 0xF0, 0xA5, 0xF8, 0x6E,
+ 0x48, 0x40, 0x7F, 0x40, 0x06, 0x80, 0x0F, 0x01,
+ 0xD1, 0x02, 0x20, 0x04, 0xE0, 0x01, 0x28, 0x01,
+ 0xD1, 0x03, 0x20, 0x00, 0xE0,
+ 0x00, 0x00, 0xB9, 0x00, 0x80, 0x01, 0x20, 0x03,
+ 0xF0, 0xAB, 0xFD, 0xFF, 0xF7, 0x86, 0xFF, 0xBF,
+ 0xF3, 0x50, 0x8F, 0xBF, 0xF3, 0x60, 0x8F, 0x30,
+ 0xBF, 0x03, 0xF0, 0xE3, 0xFD, 0x00, 0xF0, 0x93,
+ 0xF8, 0x62, 0x48, 0x60, 0x60, 0x00, 0xF0, 0x88,
+ 0xF8, 0xFF, 0xF7, 0xBC, 0xFF, 0x62, 0xB6, 0x10,
+ 0xBD, 0x70, 0xB5, 0x03, 0xF0, 0x93, 0xFE, 0x4F,
+ 0x4C, 0x21, 0x68, 0x03, 0x25, 0xAD, 0x03, 0x01,
+ 0x22, 0xA9, 0x43, 0x92, 0x03, 0x0A, 0x43, 0x22,
+ 0x60, 0x01, 0x22, 0xD2, 0x03, 0x0A, 0x43, 0x22,
+ 0x60, 0x56, 0x4A, 0x62, 0x60, 0x44, 0x4A, 0xD3,
+ 0x68, 0x55, 0x4E, 0x33, 0x40, 0xD3, 0x60, 0x13,
+ 0x69, 0x05, 0x26, 0x36, 0x04, 0x33, 0x43, 0x13,
+ 0x61, 0x13, 0x69, 0x9B, 0x03, 0xFC, 0xD5, 0x29,
+ 0x43, 0x21, 0x60, 0x3C, 0x4C, 0x00, 0x21, 0xA1,
+ 0x60, 0xE1, 0x60, 0x51, 0x68, 0xC0, 0xB2, 0x21,
+ 0x61, 0x03, 0xF0, 0x70, 0xFE,
+ 0x00, 0x00, 0xBA, 0x00, 0x80, 0x01, 0x20, 0x40,
+ 0x03, 0x60, 0x61, 0x70, 0xBD, 0x70, 0xB5, 0x4A,
+ 0x4B, 0x48, 0x48, 0x58, 0x61, 0x05, 0x20, 0x18,
+ 0x61, 0x72, 0xB6, 0x33, 0x48, 0x41, 0x68, 0x42,
+ 0x68, 0x8A, 0x42, 0xFC, 0xD0, 0x00, 0x21, 0x99,
+ 0x61, 0x44, 0x68, 0x41, 0x68, 0xA1, 0x42, 0xFC,
+ 0xD0, 0x98, 0x69, 0x40, 0x49, 0x89, 0x1C, 0x0D,
+ 0x1A, 0x04, 0x20, 0x18, 0x61, 0x62, 0xB6, 0x20,
+ 0x46, 0xFF, 0xF7, 0x90, 0xFE, 0x27, 0x4E, 0x00,
+ 0x2D, 0xF0, 0x60, 0x34, 0x61, 0xB0, 0x60, 0x0D,
+ 0xD0, 0x3A, 0x48, 0x7D, 0x21, 0x00, 0x78, 0xC9,
+ 0x02, 0x48, 0x43, 0x29, 0x46, 0x06, 0xF0, 0x53,
+ 0xFE, 0x70, 0x61, 0x00, 0x28, 0x01, 0xD1, 0x01,
+ 0x20, 0x70, 0x61, 0x70, 0xBD, 0x01, 0x20, 0x40,
+ 0x03, 0xFA, 0xE7, 0x10, 0xB5, 0x04, 0x46, 0xFF,
+ 0xF7, 0x8D, 0xFE, 0x1A, 0x49, 0x89, 0x68, 0x40,
+ 0x1A, 0xA0, 0x42, 0x03, 0xD3,
+ 0x00, 0x00, 0xBB, 0x00, 0x80, 0xFF, 0xF7, 0xC2,
+ 0xFF, 0x01, 0x20, 0x10, 0xBD, 0x00, 0x20, 0x10,
+ 0xBD, 0x00, 0x28, 0x10, 0xD0, 0x2A, 0x49, 0x88,
+ 0x42, 0x00, 0xD9, 0x08, 0x46, 0x24, 0x21, 0x48,
+ 0x43, 0x25, 0x49, 0x48, 0x61, 0x05, 0x20, 0x08,
+ 0x61, 0x00, 0x20, 0x88, 0x61, 0x08, 0x69, 0xC0,
+ 0x03, 0xFC, 0xD5, 0x04, 0x20, 0x08, 0x61, 0x70,
+ 0x47, 0x0E, 0x49, 0x08, 0x68, 0x03, 0x22, 0x92,
+ 0x03, 0x10, 0x43, 0x08, 0x60, 0x70, 0x47, 0x0B,
+ 0x49, 0x08, 0x68, 0x03, 0x22, 0x92, 0x03, 0x90,
+ 0x43, 0x01, 0x22, 0x92, 0x03, 0x02, 0x43, 0x0A,
+ 0x60, 0x01, 0x22, 0xD2, 0x03, 0x10, 0x43, 0x08,
+ 0x60, 0x70, 0x47, 0x00, 0x00, 0x48, 0x01, 0x00,
+ 0x20, 0x00, 0x04, 0x01, 0x40, 0xC8, 0x00, 0x00,
+ 0x20, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x40, 0x0C, 0x0C, 0x04, 0x00, 0x0A, 0x0A, 0x00,
+ 0x00, 0x80, 0xE2, 0x00, 0xE0,
+ 0x00, 0x00, 0xBC, 0x00, 0x80, 0x0D, 0x02, 0x00,
+ 0x00, 0x01, 0x01, 0x01, 0x00, 0x93, 0x36, 0x00,
+ 0x00, 0x08, 0x08, 0x08, 0x00, 0xCA, 0x00, 0x00,
+ 0x20, 0x40, 0xF1, 0xFF, 0x0F, 0x00, 0xED, 0x00,
+ 0xE0, 0x00, 0x00, 0x12, 0x40, 0x01, 0x09, 0x01,
+ 0x00, 0x00, 0xDC, 0x00, 0x00, 0x06, 0x00, 0x00,
+ 0x80, 0xFF, 0xF7, 0xFE, 0x20, 0xFF, 0xFF, 0xFF,
+ 0x00, 0x00, 0xE0, 0x00, 0xE0, 0x64, 0x01, 0x00,
+ 0x20, 0x50, 0xC3, 0x00, 0x00, 0x10, 0xB5, 0x3A,
+ 0x4B, 0x02, 0x24, 0x18, 0x78, 0x59, 0x68, 0xC0,
+ 0x1E, 0xC0, 0xB2, 0x0A, 0x5C, 0x1C, 0x5F, 0x52,
+ 0x42, 0xA2, 0x42, 0x00, 0xDD, 0x5A, 0x80, 0x09,
+ 0x5C, 0xFF, 0x20, 0x40, 0x1A, 0x02, 0x21, 0x59,
+ 0x5E, 0x88, 0x42, 0x00, 0xDA, 0x58, 0x80, 0x10,
+ 0xBD, 0x30, 0x48, 0xC1, 0x7A, 0x24, 0x29, 0x01,
+ 0xD2, 0x24, 0x20, 0x70, 0x47, 0xC1, 0x7A, 0x30,
+ 0x29, 0x01, 0xD9, 0x30, 0x20,
+ 0x00, 0x00, 0xBD, 0x00, 0x80, 0x70, 0x47, 0xC0,
+ 0x7A, 0x70, 0x47, 0xF0, 0xB5, 0x2A, 0x4F, 0x00,
+ 0x21, 0x3A, 0x7B, 0x7B, 0x7B, 0x8C, 0x46, 0x0E,
+ 0x46, 0x14, 0x46, 0x1D, 0x46, 0x04, 0x21, 0x20,
+ 0x2A, 0x00, 0xD0, 0x01, 0x26, 0x20, 0x2B, 0x01,
+ 0xD0, 0x01, 0x22, 0x94, 0x46, 0x49, 0x1E, 0x0B,
+ 0xD4, 0x4A, 0x00, 0x21, 0x4B, 0x8A, 0x18, 0xD7,
+ 0x18, 0x7A, 0x78, 0xBB, 0x78, 0x3F, 0x78, 0x87,
+ 0x42, 0xED, 0xD3, 0x14, 0x46, 0x1D, 0x46, 0xEA,
+ 0xE7, 0x1C, 0x48, 0x00, 0x2E, 0x00, 0xD0, 0xC4,
+ 0x61, 0x61, 0x46, 0x00, 0x29, 0x00, 0xD0, 0x05,
+ 0x62, 0xF0, 0xBD, 0xF8, 0xB5, 0x04, 0x46, 0xC0,
+ 0x1E, 0xC5, 0xB2, 0x20, 0x46, 0x18, 0x38, 0xC6,
+ 0xB2, 0x15, 0x48, 0x11, 0x4F, 0x24, 0x2C, 0x0B,
+ 0xD2, 0x14, 0x49, 0x89, 0x5D, 0x06, 0x46, 0x81,
+ 0x60, 0x05, 0x20, 0x03, 0xF0, 0x67, 0xFD, 0x78,
+ 0x68, 0x40, 0x5D, 0x70, 0x60,
+ 0x00, 0x00, 0xBE, 0x00, 0x80, 0xF0, 0x20, 0x0A,
+ 0xE0, 0x79, 0x68, 0x49, 0x5D, 0x05, 0x46, 0x41,
+ 0x60, 0xF0, 0x20, 0x03, 0xF0, 0x5B, 0xFD, 0x0B,
+ 0x48, 0x80, 0x5D, 0xA8, 0x60, 0x05, 0x20, 0x03,
+ 0xF0, 0x55, 0xFD, 0x09, 0x49, 0x20, 0x46, 0x48,
+ 0x43, 0xFD, 0xF7, 0x88, 0xFB, 0xF8, 0xBD, 0x00,
+ 0x00, 0x64, 0x01, 0x00, 0x20, 0x00, 0xDC, 0x00,
+ 0x00, 0xC0, 0xF1, 0xFF, 0x0F, 0x00, 0xFF, 0x00,
+ 0x40, 0x00, 0xFF, 0x01, 0x40, 0x7C, 0xCD, 0x00,
+ 0x00, 0x40, 0x42, 0x0F, 0x00, 0x70, 0x47, 0xFE,
+ 0xB5, 0xFF, 0x4C, 0x25, 0x68, 0x03, 0x21, 0x09,
+ 0x02, 0x28, 0x46, 0x88, 0x43, 0x20, 0x60, 0xFC,
+ 0x48, 0x40, 0x30, 0x80, 0x68, 0x01, 0x90, 0xE0,
+ 0x6B, 0x00, 0x90, 0x01, 0x98, 0xF8, 0x4A, 0x06,
+ 0x0C, 0x00, 0x98, 0x36, 0x04, 0x07, 0x0C, 0xFF,
+ 0x36, 0x02, 0x36, 0x3F, 0x04, 0xFF, 0x37, 0xA0,
+ 0x03, 0x31, 0x46, 0x02, 0x37,
+ 0x00, 0x00, 0xBF, 0x00, 0x80, 0x41, 0x40, 0x40,
+ 0x32, 0x91, 0x60, 0x78, 0x40, 0xE0, 0x63, 0x01,
+ 0x20, 0xFD, 0xF7, 0x0E, 0xFB, 0xEE, 0x48, 0x40,
+ 0x30, 0x86, 0x60, 0xE7, 0x63, 0x01, 0x20, 0xFD,
+ 0xF7, 0x07, 0xFB, 0xEB, 0x49, 0x01, 0x98, 0x40,
+ 0x31, 0x88, 0x60, 0x00, 0x98, 0xE0, 0x63, 0x25,
+ 0x60, 0xFE, 0xBD, 0x10, 0xB5, 0xE7, 0x49, 0xC8,
+ 0x68, 0x4A, 0x02, 0x10, 0x43, 0xC8, 0x60, 0xE6,
+ 0x48, 0x81, 0x68, 0x05, 0x20, 0x28, 0x29, 0x03,
+ 0xD3, 0x06, 0x20, 0x30, 0x29, 0x00, 0xD3, 0x07,
+ 0x20, 0xE2, 0x49, 0x0A, 0x7B, 0x12, 0x09, 0x10,
+ 0x18, 0x42, 0x00, 0x08, 0x7B, 0x40, 0x07, 0x40,
+ 0x0F, 0x05, 0x28, 0x00, 0xD9, 0x00, 0x20, 0xDE,
+ 0x4B, 0x80, 0x00, 0x1B, 0x58, 0xD8, 0x48, 0x13,
+ 0x43, 0xC0, 0x30, 0x03, 0x61, 0x89, 0x7B, 0xDB,
+ 0x4A, 0x09, 0x07, 0x09, 0x0F, 0x89, 0x18, 0x41,
+ 0x60, 0x03, 0x21, 0x81, 0x60,
+ 0x00, 0x00, 0xC0, 0x00, 0x80, 0xD2, 0x49, 0x92,
+ 0x0C, 0x40, 0x31, 0x8A, 0x62, 0xD3, 0x4A, 0x60,
+ 0x3A, 0x52, 0x69, 0xCF, 0x4B, 0x80, 0x33, 0x9A,
+ 0x63, 0x01, 0x22, 0x12, 0x03, 0x02, 0x60, 0x09,
+ 0x20, 0x00, 0x07, 0x88, 0x61, 0xCA, 0x4C, 0x20,
+ 0x68, 0x49, 0x06, 0x08, 0x43, 0x20, 0x60, 0x05,
+ 0x20, 0xFD, 0xF7, 0xF9, 0xFA, 0x05, 0x20, 0xFD,
+ 0xF7, 0xE7, 0xFA, 0x20, 0x68, 0x00, 0x28, 0x01,
+ 0xD0, 0xFF, 0xF7, 0x85, 0xFF, 0x10, 0xBD, 0x70,
+ 0xB5, 0xC7, 0x48, 0xC1, 0x7E, 0x00, 0x29, 0x19,
+ 0xD0, 0xC6, 0x48, 0x41, 0x43, 0xC4, 0x48, 0x20,
+ 0x30, 0x00, 0x78, 0x00, 0x04, 0x06, 0xF0, 0xD3,
+ 0xFC, 0xBE, 0x4B, 0x00, 0x21, 0xC2, 0x4C, 0xC3,
+ 0x4D, 0x20, 0x3B, 0x9E, 0x69, 0x64, 0x22, 0x00,
+ 0x2E, 0x01, 0xD0, 0x0A, 0x19, 0x12, 0x78, 0x4E,
+ 0x00, 0x42, 0x43, 0x12, 0x12, 0x49, 0x1C, 0xAA,
+ 0x53, 0x08, 0x29, 0xF2, 0xD3,
+ 0x00, 0x00, 0xC1, 0x00, 0x80, 0x70, 0xBD, 0xF8,
+ 0xB5, 0x00, 0x21, 0x05, 0x20, 0xFD, 0xF7, 0xAC,
+ 0xFA, 0xB2, 0x4E, 0x20, 0x3E, 0xF0, 0x69, 0x02,
+ 0x28, 0x0E, 0xD1, 0xB7, 0x49, 0x0E, 0x20, 0xFD,
+ 0xF7, 0x90, 0xFA, 0xB6, 0x48, 0x02, 0x6A, 0x01,
+ 0x6A, 0xFF, 0x23, 0x1B, 0x04, 0x99, 0x43, 0x01,
+ 0x23, 0x9B, 0x05, 0x19, 0x43, 0x0A, 0x43, 0x02,
+ 0x62, 0xA8, 0x4F, 0x60, 0x3F, 0xB8, 0x69, 0xAA,
+ 0x4C, 0x60, 0x70, 0xF8, 0x69, 0xA0, 0x70, 0x60,
+ 0x78, 0xC1, 0x1C, 0x89, 0x08, 0xE1, 0x74, 0xC9,
+ 0xB2, 0x40, 0x1A, 0x40, 0x1C, 0x03, 0x21, 0x06,
+ 0xF0, 0xA0, 0xFC, 0x20, 0x75, 0x00, 0x21, 0x20,
+ 0x46, 0x20, 0x30, 0xA7, 0x4D, 0x41, 0x70, 0xE9,
+ 0x68, 0xF0, 0x22, 0x11, 0x40, 0xE1, 0x77, 0x29,
+ 0x6A, 0xE1, 0x75, 0xA9, 0x68, 0x61, 0x76, 0xA9,
+ 0x68, 0x09, 0x0A, 0xE1, 0x76, 0x31, 0x68, 0x01,
+ 0x70, 0xFF, 0xF7, 0xA1, 0xFF,
+ 0x00, 0x00, 0xC2, 0x00, 0x80, 0x68, 0x6F, 0x20,
+ 0x76, 0xE8, 0x6D, 0xA0, 0x76, 0xE8, 0x6D, 0x29,
+ 0x46, 0x00, 0x0A, 0x20, 0x77, 0x80, 0x31, 0x09,
+ 0x6B, 0xC0, 0xB2, 0x0D, 0x0A, 0x39, 0x46, 0x40,
+ 0x39, 0x09, 0x68, 0x09, 0x0A, 0x00, 0x91, 0xF9,
+ 0x68, 0x0F, 0x0A, 0x64, 0x21, 0x41, 0x43, 0x70,
+ 0x68, 0x80, 0x03, 0x06, 0xF0, 0x68, 0xFC, 0x20,
+ 0x85, 0x8C, 0x48, 0x29, 0x46, 0x41, 0x43, 0xB0,
+ 0x68, 0x00, 0x04, 0x06, 0xF0, 0x60, 0xFC, 0x05,
+ 0x46, 0x00, 0x99, 0x64, 0x20, 0x41, 0x43, 0xF0,
+ 0x68, 0x80, 0x03, 0x06, 0xF0, 0x58, 0xFC, 0xA0,
+ 0x85, 0x39, 0x46, 0x64, 0x20, 0x41, 0x43, 0xF0,
+ 0x68, 0x80, 0x03, 0x06, 0xF0, 0x50, 0xFC, 0xE0,
+ 0x85, 0xB1, 0x69, 0x82, 0x48, 0x10, 0x30, 0x00,
+ 0x29, 0x0B, 0xD0, 0x7F, 0x4A, 0x00, 0x21, 0x8B,
+ 0x18, 0x1B, 0x78, 0x4C, 0x00, 0x6B, 0x43, 0x1B,
+ 0x12, 0x49, 0x1C, 0x03, 0x53,
+ 0x00, 0x00, 0xC3, 0x00, 0x80, 0x08, 0x29, 0xF6,
+ 0xD3, 0x08, 0xE0, 0x19, 0x22, 0x92, 0x02, 0x55,
+ 0x43, 0x2A, 0x14, 0x4B, 0x00, 0x49, 0x1C, 0xC2,
+ 0x52, 0x08, 0x29, 0xFA, 0xD3, 0x6F, 0x48, 0xC0,
+ 0x79, 0xC0, 0x07, 0x02, 0xD0, 0x04, 0xF0, 0x4A,
+ 0xFC, 0xF8, 0xBD, 0x04, 0xF0, 0x4B, 0xFC, 0xF8,
+ 0xBD, 0x10, 0xB5, 0x6D, 0x4C, 0x20, 0x78, 0x00,
+ 0x28, 0x03, 0xD1, 0xFF, 0xF7, 0x64, 0xFF, 0x01,
+ 0x20, 0x20, 0x70, 0xFF, 0xF7, 0xF6, 0xFE, 0x10,
+ 0xBD, 0x61, 0x49, 0x6E, 0x48, 0x48, 0x61, 0x60,
+ 0x49, 0x6D, 0x48, 0x40, 0x31, 0x48, 0x62, 0x01,
+ 0x21, 0x5D, 0x48, 0xC9, 0x03, 0xC0, 0x30, 0x01,
+ 0x60, 0x41, 0x68, 0x49, 0x00, 0x49, 0x08, 0x41,
+ 0x60, 0x81, 0x68, 0x49, 0x08, 0x49, 0x00, 0x81,
+ 0x60, 0x01, 0x69, 0x01, 0x22, 0x89, 0x00, 0x89,
+ 0x08, 0x92, 0x07, 0x89, 0x18, 0x01, 0x61, 0x70,
+ 0x47, 0x10, 0xB5, 0x53, 0x48,
+ 0x00, 0x00, 0xC4, 0x00, 0x80, 0x01, 0x68, 0x49,
+ 0x00, 0x49, 0x08, 0x01, 0x60, 0x05, 0x20, 0xFD,
+ 0xF7, 0x02, 0xFA, 0x05, 0x20, 0xFD, 0xF7, 0x07,
+ 0xFA, 0x10, 0xBD, 0x5C, 0x48, 0x00, 0x88, 0xC0,
+ 0xB2, 0x70, 0x47, 0x02, 0x46, 0x00, 0x20, 0x01,
+ 0x2A, 0x09, 0xD0, 0x02, 0x2A, 0x07, 0xD0, 0x04,
+ 0x2A, 0x07, 0xD0, 0x08, 0x2A, 0x02, 0xD1, 0x49,
+ 0x48, 0x60, 0x38, 0x80, 0x6B, 0x70, 0x47, 0x08,
+ 0x46, 0x70, 0x47, 0x48, 0x08, 0x70, 0x47, 0x42,
+ 0x48, 0xC0, 0x30, 0x01, 0x69, 0x8A, 0x00, 0x92,
+ 0x08, 0x41, 0x06, 0x52, 0x18, 0x02, 0x61, 0x42,
+ 0x68, 0x0A, 0x43, 0x42, 0x60, 0x81, 0x68, 0x01,
+ 0x22, 0x11, 0x43, 0x81, 0x60, 0x70, 0x47, 0x70,
+ 0xB5, 0xFF, 0xF7, 0xED, 0xFF, 0x01, 0x24, 0x3E,
+ 0x4D, 0x00, 0x21, 0x2C, 0x73, 0x20, 0x46, 0xFF,
+ 0xF7, 0xD4, 0xFF, 0x28, 0x71, 0x04, 0xF0, 0xE6,
+ 0xFB, 0x00, 0x28, 0x01, 0xD0,
+ 0x00, 0x00, 0xC5, 0x00, 0x80, 0x42, 0x48, 0x04,
+ 0x70, 0x34, 0x4C, 0x20, 0x3C, 0xE0, 0x69, 0x02,
+ 0x28, 0x01, 0xD1, 0x40, 0x49, 0x00, 0xE0, 0x40,
+ 0x49, 0x05, 0x20, 0xFD, 0xF7, 0x9B, 0xF9, 0x00,
+ 0x20, 0x3E, 0x4E, 0x68, 0x71, 0x70, 0x69, 0x3E,
+ 0x49, 0x01, 0x22, 0x09, 0x78, 0x12, 0x03, 0x00,
+ 0x02, 0x89, 0x18, 0x08, 0x43, 0x26, 0x49, 0xC0,
+ 0x31, 0x08, 0x60, 0x00, 0x20, 0x39, 0x4A, 0x0F,
+ 0x21, 0x83, 0x00, 0x9B, 0x18, 0x19, 0x60, 0x40,
+ 0x1C, 0x41, 0x28, 0xF9, 0xD3, 0x2C, 0x49, 0x4A,
+ 0x68, 0x25, 0x48, 0x20, 0x30, 0x40, 0x78, 0x00,
+ 0x28, 0x05, 0xD0, 0x05, 0x20, 0x82, 0x43, 0xD0,
+ 0x06, 0x01, 0xD4, 0xC0, 0x20, 0x82, 0x43, 0xFF,
+ 0xF7, 0x98, 0xFF, 0x03, 0x09, 0x2E, 0x48, 0x03,
+ 0xD0, 0x1A, 0x4B, 0x9B, 0x79, 0x01, 0x2B, 0x03,
+ 0xD0, 0x23, 0x69, 0x5B, 0x07, 0x00, 0xD0, 0x00,
+ 0x20, 0x13, 0x4B, 0x82, 0x43,
+ 0x00, 0x00, 0xC6, 0x00, 0x80, 0x1A, 0x60, 0xE8,
+ 0x7E, 0x6A, 0x7E, 0x00, 0x02, 0x10, 0x43, 0x98,
+ 0x60, 0xC8, 0x68, 0xF0, 0x22, 0x90, 0x43, 0xEA,
+ 0x7F, 0x10, 0x43, 0x58, 0x61, 0x08, 0x69, 0x98,
+ 0x61, 0x48, 0x69, 0xD8, 0x61, 0x88, 0x69, 0x18,
+ 0x62, 0xC8, 0x69, 0x58, 0x62, 0x0A, 0x6A, 0x1F,
+ 0x48, 0x02, 0x40, 0xE8, 0x7D, 0x02, 0x43, 0x00,
+ 0x04, 0x02, 0x43, 0x9A, 0x62, 0x48, 0x6A, 0xD8,
+ 0x62, 0x88, 0x6A, 0x18, 0x63, 0xC8, 0x6A, 0x58,
+ 0x63, 0x08, 0x6B, 0x98, 0x63, 0x48, 0x6B, 0x2F,
+ 0xE0, 0x00, 0x00, 0x11, 0x40, 0x00, 0x00, 0x01,
+ 0x40, 0x00, 0xFF, 0x01, 0x40, 0xE8, 0xDF, 0x00,
+ 0x00, 0xD8, 0xCD, 0x00, 0x00, 0x40, 0x40, 0x00,
+ 0x80, 0x6C, 0x01, 0x00, 0x20, 0x71, 0x02, 0x00,
+ 0x00, 0x60, 0xF1, 0xFF, 0x0F, 0x54, 0x05, 0x00,
+ 0x20, 0x41, 0x9B, 0x00, 0x00, 0x00, 0xED, 0x00,
+ 0xE0, 0x48, 0xDE, 0x00, 0x00,
+ 0x00, 0x00, 0xC7, 0x00, 0x80, 0xFF, 0x00, 0xAF,
+ 0x40, 0x0A, 0xA0, 0x00, 0x00, 0x48, 0x02, 0x00,
+ 0x20, 0xA8, 0x02, 0x00, 0x20, 0xA5, 0x9E, 0x00,
+ 0x00, 0x77, 0x9C, 0x00, 0x00, 0x54, 0xE0, 0x00,
+ 0x00, 0x34, 0x03, 0x00, 0x20, 0x00, 0x04, 0x11,
+ 0x40, 0x00, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x00,
+ 0xFF, 0xD8, 0x63, 0x88, 0x6B, 0xFF, 0x4A, 0x10,
+ 0x60, 0xC8, 0x6B, 0x50, 0x60, 0x08, 0x6C, 0x90,
+ 0x60, 0x48, 0x6C, 0xD0, 0x60, 0x88, 0x6C, 0x10,
+ 0x61, 0xC8, 0x6C, 0x50, 0x61, 0x08, 0x6D, 0x50,
+ 0x62, 0xF9, 0x48, 0x00, 0x69, 0xF7, 0x49, 0x80,
+ 0x09, 0x80, 0x01, 0x40, 0x31, 0xC8, 0x63, 0x0F,
+ 0x20, 0x00, 0x07, 0x90, 0x61, 0x70, 0x6B, 0x08,
+ 0x61, 0xF4, 0x4D, 0x00, 0x20, 0x86, 0x00, 0xB6,
+ 0x18, 0xF5, 0x62, 0x40, 0x1C, 0x09, 0x28, 0xF9,
+ 0xD3, 0x20, 0x69, 0x00, 0x28, 0x03, 0xD1, 0xC8,
+ 0x68, 0x40, 0x00, 0x40, 0x08,
+ 0x00, 0x00, 0xC8, 0x00, 0x80, 0xC8, 0x60, 0xE0,
+ 0x69, 0x02, 0x28, 0x04, 0xD1, 0x58, 0x69, 0x01,
+ 0x21, 0xC9, 0x02, 0x08, 0x43, 0x58, 0x61, 0x70,
+ 0xBD, 0xF8, 0xB5, 0xFF, 0xF7, 0x14, 0xFF, 0x02,
+ 0x26, 0xE7, 0x4F, 0x00, 0x21, 0x3E, 0x73, 0x30,
+ 0x46, 0xFF, 0xF7, 0xFB, 0xFE, 0x38, 0x71, 0x04,
+ 0xF0, 0x0D, 0xFB, 0x00, 0x28, 0x02, 0xD0, 0xE3,
+ 0x48, 0x01, 0x21, 0x01, 0x70, 0xDE, 0x4C, 0x40,
+ 0x34, 0xE0, 0x69, 0x02, 0x28, 0x78, 0x78, 0x03,
+ 0xD1, 0xC0, 0x1C, 0x80, 0x08, 0x80, 0x00, 0xFF,
+ 0xE7, 0xD9, 0x4D, 0xE9, 0x6A, 0x41, 0x43, 0x79,
+ 0x71, 0xDB, 0x49, 0x05, 0x20, 0xFD, 0xF7, 0xBA,
+ 0xF8, 0xDA, 0x4B, 0x98, 0x69, 0x01, 0x21, 0x00,
+ 0x02, 0x09, 0x03, 0x08, 0x43, 0xD1, 0x49, 0x80,
+ 0x31, 0x08, 0x60, 0xD7, 0x4A, 0x00, 0x20, 0x81,
+ 0x00, 0x89, 0x18, 0x0E, 0x60, 0x40, 0x1C, 0x41,
+ 0x28, 0xF9, 0xD3, 0xD4, 0x4E,
+ 0x00, 0x00, 0xC9, 0x00, 0x80, 0xB1, 0x6D, 0xCE,
+ 0x48, 0x20, 0x30, 0x40, 0x78, 0x00, 0x28, 0x05,
+ 0xD0, 0x05, 0x20, 0x81, 0x43, 0xC8, 0x06, 0x01,
+ 0xD4, 0xC0, 0x20, 0x81, 0x43, 0xFF, 0xF7, 0xBD,
+ 0xFE, 0x02, 0x09, 0xCD, 0x48, 0x04, 0xD0, 0xC4,
+ 0x4A, 0x60, 0x32, 0x92, 0x79, 0x01, 0x2A, 0x03,
+ 0xD0, 0x22, 0x69, 0x52, 0x07, 0x00, 0xD0, 0x00,
+ 0x20, 0xBE, 0x4A, 0x81, 0x43, 0x40, 0x3A, 0x11,
+ 0x60, 0x38, 0x7F, 0xB9, 0x7E, 0x00, 0x02, 0x08,
+ 0x43, 0x90, 0x60, 0x30, 0x6E, 0x50, 0x61, 0x70,
+ 0x6E, 0x90, 0x61, 0xB0, 0x6E, 0xD0, 0x61, 0xF0,
+ 0x6E, 0x10, 0x62, 0x30, 0x6F, 0x50, 0x62, 0x71,
+ 0x6F, 0xBE, 0x48, 0x01, 0x40, 0x38, 0x7E, 0x01,
+ 0x43, 0x00, 0x04, 0x01, 0x43, 0x91, 0x62, 0xB0,
+ 0x6F, 0xD0, 0x62, 0xF0, 0x6F, 0x10, 0x63, 0xB7,
+ 0x48, 0x80, 0x30, 0x01, 0x68, 0x51, 0x63, 0x41,
+ 0x68, 0x91, 0x63, 0x81, 0x68,
+ 0x00, 0x00, 0xCA, 0x00, 0x80, 0xD1, 0x63, 0xC2,
+ 0x68, 0xAA, 0x49, 0x0A, 0x60, 0x02, 0x69, 0x4A,
+ 0x60, 0x42, 0x69, 0x8A, 0x60, 0x82, 0x69, 0xCA,
+ 0x60, 0xC2, 0x69, 0x0A, 0x61, 0x02, 0x6A, 0x4A,
+ 0x61, 0x40, 0x6A, 0x48, 0x62, 0x28, 0x69, 0xA3,
+ 0x4A, 0x40, 0x32, 0xD0, 0x63, 0x0D, 0x20, 0x00,
+ 0x07, 0x88, 0x61, 0x98, 0x6B, 0x10, 0x61, 0xA1,
+ 0x4B, 0x00, 0x20, 0x9B, 0x1C, 0x85, 0x00, 0x6D,
+ 0x18, 0xEB, 0x62, 0x40, 0x1C, 0x08, 0x28, 0xF9,
+ 0xD3, 0x9C, 0x48, 0xD0, 0x60, 0x20, 0x69, 0x00,
+ 0x28, 0x03, 0xD1, 0xD0, 0x68, 0x40, 0x00, 0x40,
+ 0x08, 0xD0, 0x60, 0xF8, 0xBD, 0x70, 0x47, 0x10,
+ 0xB5, 0xFF, 0xF7, 0x71, 0xFE, 0x00, 0x20, 0x9A,
+ 0x49, 0x0F, 0x22, 0x83, 0x00, 0x5B, 0x18, 0x1A,
+ 0x60, 0x40, 0x1C, 0x41, 0x28, 0xF9, 0xD3, 0x91,
+ 0x49, 0x8E, 0x4A, 0x00, 0x20, 0x83, 0x00, 0x9B,
+ 0x18, 0xD9, 0x62, 0x40, 0x1C,
+ 0x00, 0x00, 0xCB, 0x00, 0x80, 0x09, 0x28, 0xF9,
+ 0xD3, 0x8B, 0x48, 0x40, 0x38, 0x00, 0x68, 0x89,
+ 0x49, 0x40, 0x39, 0x88, 0x60, 0x88, 0x48, 0x00,
+ 0x69, 0x86, 0x49, 0x80, 0x09, 0x80, 0x01, 0x40,
+ 0x31, 0xC8, 0x63, 0x8A, 0x4A, 0x10, 0x6A, 0x8E,
+ 0x4B, 0x01, 0x24, 0x1B, 0x78, 0x24, 0x03, 0x00,
+ 0x02, 0x1B, 0x19, 0x18, 0x43, 0x7F, 0x4B, 0x80,
+ 0x33, 0x18, 0x60, 0x10, 0x6C, 0x08, 0x61, 0x10,
+ 0xBD, 0x10, 0xB5, 0xFF, 0xF7, 0x40, 0xFE, 0x00,
+ 0x20, 0x81, 0x4A, 0x02, 0x21, 0x83, 0x00, 0x9B,
+ 0x18, 0x19, 0x60, 0x40, 0x1C, 0x41, 0x28, 0xF9,
+ 0xD3, 0x78, 0x4A, 0x00, 0x20, 0x75, 0x49, 0x92,
+ 0x1C, 0x83, 0x00, 0x5B, 0x18, 0xDA, 0x62, 0x40,
+ 0x1C, 0x09, 0x28, 0xF9, 0xD3, 0x72, 0x4A, 0xD3,
+ 0x68, 0x70, 0x48, 0x40, 0x38, 0x83, 0x60, 0x12,
+ 0x69, 0x6E, 0x4B, 0x40, 0x33, 0xDA, 0x63, 0x4A,
+ 0x6A, 0x03, 0x24, 0x64, 0x02,
+ 0x00, 0x00, 0xCC, 0x00, 0x80, 0x22, 0x43, 0x4A,
+ 0x62, 0x81, 0x69, 0x01, 0x22, 0xC9, 0x0D, 0xC9,
+ 0x05, 0x92, 0x05, 0x89, 0x18, 0x81, 0x61, 0x41,
+ 0x69, 0x42, 0x15, 0x11, 0x43, 0x41, 0x61, 0x6B,
+ 0x48, 0x01, 0x6A, 0x70, 0x4A, 0x01, 0x24, 0x12,
+ 0x78, 0x24, 0x03, 0x09, 0x02, 0x12, 0x19, 0x11,
+ 0x43, 0x60, 0x4A, 0x80, 0x32, 0x11, 0x60, 0x40,
+ 0x6C, 0x18, 0x61, 0x10, 0xBD, 0xF8, 0xB5, 0x60,
+ 0x4D, 0x08, 0x20, 0x28, 0x73, 0x00, 0x21, 0xFF,
+ 0xF7, 0xEC, 0xFD, 0x5B, 0x4C, 0x28, 0x71, 0x40,
+ 0x3C, 0xA0, 0x69, 0x65, 0x49, 0xC6, 0xB2, 0x05,
+ 0x20, 0xFC, 0xF7, 0xBC, 0xFF, 0x20, 0x46, 0x40,
+ 0x38, 0xC1, 0x6B, 0x54, 0x48, 0x40, 0x38, 0x01,
+ 0x60, 0x61, 0x68, 0x41, 0x61, 0xA1, 0x68, 0x81,
+ 0x61, 0xE1, 0x68, 0xC1, 0x61, 0x21, 0x69, 0x01,
+ 0x62, 0x61, 0x69, 0x41, 0x62, 0xA1, 0x69, 0x57,
+ 0x4A, 0x11, 0x40, 0x31, 0x43,
+ 0x00, 0x00, 0xCD, 0x00, 0x80, 0x32, 0x04, 0x11,
+ 0x43, 0x81, 0x62, 0xE1, 0x69, 0xC1, 0x62, 0x21,
+ 0x6A, 0x01, 0x63, 0x61, 0x6A, 0x41, 0x63, 0xA1,
+ 0x6A, 0x81, 0x63, 0xE1, 0x6A, 0xC1, 0x63, 0x21,
+ 0x6B, 0x44, 0x48, 0x01, 0x60, 0x61, 0x6B, 0x41,
+ 0x60, 0xA1, 0x6B, 0x81, 0x60, 0xE1, 0x6B, 0xC1,
+ 0x60, 0x40, 0x34, 0x21, 0x68, 0x01, 0x61, 0x61,
+ 0x68, 0x41, 0x61, 0xA1, 0x68, 0x41, 0x62, 0x0D,
+ 0x21, 0x09, 0x07, 0x81, 0x61, 0x27, 0x46, 0x40,
+ 0x37, 0xF8, 0x69, 0x02, 0x28, 0x04, 0xD1, 0x68,
+ 0x78, 0xC0, 0x1C, 0x86, 0x08, 0xB6, 0x00, 0x00,
+ 0xE0, 0x6E, 0x78, 0x38, 0x6A, 0x01, 0x28, 0x02,
+ 0xD1, 0xFF, 0xF7, 0x6E, 0xFF, 0x01, 0xE0, 0xFF,
+ 0xF7, 0x3A, 0xFF, 0xE0, 0x6A, 0xA1, 0x6B, 0x70,
+ 0x43, 0x40, 0x18, 0xE1, 0x6B, 0x40, 0x18, 0x68,
+ 0x71, 0x38, 0x69, 0x02, 0x28, 0x05, 0xD0, 0x2D,
+ 0x48, 0x40, 0x30, 0xC1, 0x68,
+ 0x00, 0x00, 0xCE, 0x00, 0x80, 0x49, 0x00, 0x49,
+ 0x08, 0xC1, 0x60, 0xF8, 0xBD, 0x30, 0x4A, 0x00,
+ 0x21, 0x8B, 0x00, 0x9B, 0x18, 0x18, 0x60, 0x49,
+ 0x1C, 0xC9, 0xB2, 0x41, 0x29, 0xF8, 0xD3, 0x70,
+ 0x47, 0xF8, 0xB5, 0xFF, 0xF7, 0xA0, 0xFD, 0x26,
+ 0x4F, 0x22, 0x4D, 0xF8, 0x7E, 0x01, 0x24, 0x24,
+ 0x03, 0x40, 0x3D, 0x10, 0x28, 0x04, 0xD9, 0x27,
+ 0x48, 0x80, 0x68, 0xC0, 0xB2, 0x00, 0x19, 0xA8,
+ 0x60, 0x0F, 0x20, 0xFF, 0xF7, 0xE3, 0xFF, 0x00,
+ 0x26, 0x1D, 0x48, 0xBE, 0x75, 0x3E, 0x86, 0x20,
+ 0x30, 0x46, 0x71, 0x86, 0x71, 0x18, 0x48, 0xFE,
+ 0x64, 0x80, 0x6B, 0x38, 0x71, 0x10, 0x20, 0x38,
+ 0x73, 0x22, 0x49, 0x05, 0x20, 0xFC, 0xF7, 0x36,
+ 0xFF, 0x13, 0x48, 0x40, 0x30, 0x00, 0x69, 0x11,
+ 0x49, 0x40, 0x31, 0x02, 0x28, 0x03, 0xD0, 0xC8,
+ 0x68, 0x40, 0x00, 0x40, 0x08, 0xC8, 0x60, 0x00,
+ 0x20, 0x82, 0x00, 0x52, 0x18,
+ 0x00, 0x00, 0xCF, 0x00, 0x80, 0x56, 0x61, 0x40,
+ 0x1C, 0x09, 0x28, 0xF9, 0xD3, 0x09, 0x48, 0x80,
+ 0x30, 0x04, 0x60, 0xA9, 0x6A, 0x11, 0x4A, 0xD2,
+ 0x43, 0x11, 0x40, 0xA9, 0x62, 0x0D, 0x21, 0x05,
+ 0x4A, 0x09, 0x07, 0x91, 0x61, 0x04, 0x49, 0x60,
+ 0x31, 0x09, 0x7C, 0x00, 0x29, 0x28, 0xD0, 0x01,
+ 0x69, 0x0F, 0x4A, 0x1F, 0xE0, 0x40, 0x00, 0x11,
+ 0x40, 0x88, 0xDF, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0xC0, 0x6C, 0x01, 0x00, 0x20, 0xA8, 0x02, 0x00,
+ 0x20, 0x6B, 0xA2, 0x00, 0x00, 0x54, 0xE0, 0x00,
+ 0x00, 0x00, 0x04, 0x11, 0x40, 0x48, 0xDE, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0xFF, 0x00,
+ 0xFF, 0x39, 0x03, 0x00, 0x20, 0x3A, 0x03, 0x00,
+ 0x20, 0x6F, 0xA3, 0x00, 0x00, 0x45, 0xA4, 0x00,
+ 0x00, 0xFF, 0xE0, 0xE3, 0xF1, 0x11, 0x40, 0x01,
+ 0x61, 0x01, 0x69, 0xFA, 0x4A, 0x11, 0x43, 0x01,
+ 0x61, 0xF8, 0xBD, 0xF0, 0xB5,
+ 0x00, 0x00, 0xD0, 0x00, 0x80, 0x04, 0x46, 0x0F,
+ 0x20, 0xFF, 0xF7, 0x80, 0xFF, 0x21, 0x46, 0x02,
+ 0x20, 0xFF, 0xF7, 0x07, 0xFD, 0x16, 0x21, 0xF4,
+ 0x4D, 0x48, 0x43, 0x2A, 0x5A, 0xF3, 0x49, 0x44,
+ 0x19, 0x0A, 0x86, 0xA2, 0x78, 0x8A, 0x75, 0xF2,
+ 0x4E, 0xF2, 0x4F, 0x00, 0x21, 0x2A, 0x5A, 0x01,
+ 0x23, 0x8B, 0x40, 0x1A, 0x42, 0x06, 0xD0, 0x62,
+ 0x18, 0x53, 0x7B, 0x12, 0x79, 0xB2, 0x5C, 0x92,
+ 0x00, 0xD2, 0x19, 0x13, 0x60, 0x49, 0x1C, 0x08,
+ 0x29, 0xF0, 0xD3, 0xF0, 0xBD, 0x10, 0xB5, 0xE7,
+ 0x49, 0xEA, 0x4B, 0x49, 0x79, 0x09, 0x18, 0xCA,
+ 0x00, 0x89, 0x18, 0xE7, 0x4A, 0x00, 0x20, 0x12,
+ 0x68, 0x8A, 0x18, 0x11, 0x18, 0x09, 0x7B, 0x0C,
+ 0x02, 0x0C, 0x43, 0x81, 0x00, 0xC9, 0x18, 0x4C,
+ 0x61, 0x40, 0x1C, 0x09, 0x28, 0xF5, 0xD3, 0x10,
+ 0xBD, 0xF0, 0xB5, 0xE1, 0x4C, 0x62, 0x7C, 0xDB,
+ 0x4B, 0x00, 0x2A, 0x01, 0xD1,
+ 0x00, 0x00, 0xD1, 0x00, 0x80, 0x01, 0x22, 0x00,
+ 0xE0, 0x1A, 0x7D, 0x94, 0x46, 0x62, 0x7C, 0x00,
+ 0x2A, 0x01, 0xD1, 0xC2, 0x1C, 0x03, 0xE0, 0x5A,
+ 0x78, 0xDC, 0x7C, 0x12, 0x1B, 0x12, 0x18, 0xD2,
+ 0xB2, 0x96, 0x46, 0xD8, 0x4D, 0x00, 0x22, 0x0C,
+ 0x01, 0x66, 0x19, 0x9C, 0x78, 0x73, 0x46, 0x03,
+ 0x2A, 0x02, 0xD2, 0x63, 0x46, 0x53, 0x43, 0x1B,
+ 0x18, 0xDB, 0xB2, 0xFF, 0x29, 0x01, 0xD1, 0x0F,
+ 0x25, 0x01, 0xE0, 0x95, 0x00, 0x75, 0x59, 0xCA,
+ 0x4F, 0xE3, 0x18, 0xFB, 0x5C, 0xC9, 0x4F, 0x9B,
+ 0x00, 0xDB, 0x19, 0x1D, 0x60, 0x52, 0x1C, 0xD2,
+ 0xB2, 0x04, 0x2A, 0xE7, 0xD3, 0xF0, 0xBD, 0xF0,
+ 0xB5, 0xC7, 0x4A, 0xC9, 0x49, 0x60, 0x3A, 0x13,
+ 0x6A, 0xC1, 0x4A, 0x52, 0x1E, 0x9A, 0x5C, 0x93,
+ 0x00, 0xC0, 0x4A, 0x9A, 0x18, 0x13, 0x68, 0x96,
+ 0x46, 0x9C, 0x46, 0x0C, 0x23, 0x13, 0x60, 0xBF,
+ 0x4A, 0x80, 0x3A, 0x13, 0x68,
+ 0x00, 0x00, 0xD2, 0x00, 0x80, 0x97, 0x68, 0x94,
+ 0x6A, 0x15, 0x68, 0x01, 0x26, 0xB6, 0x02, 0xB5,
+ 0x43, 0x15, 0x60, 0xFF, 0x25, 0x02, 0x35, 0x95,
+ 0x60, 0x00, 0x28, 0x06, 0xD0, 0x95, 0x6A, 0xBB,
+ 0x4E, 0x35, 0x40, 0x05, 0x43, 0x00, 0x04, 0x05,
+ 0x43, 0x95, 0x62, 0x07, 0x20, 0xD0, 0x60, 0x15,
+ 0x68, 0x01, 0x26, 0xB6, 0x07, 0x35, 0x43, 0x15,
+ 0x60, 0xD5, 0x68, 0xED, 0x07, 0x01, 0xD1, 0x49,
+ 0x1E, 0xFA, 0xD2, 0xD0, 0x60, 0x60, 0x46, 0x71,
+ 0x46, 0x08, 0x60, 0x13, 0x60, 0x97, 0x60, 0x94,
+ 0x62, 0xF0, 0xBD, 0xF0, 0xB5, 0xD3, 0x00, 0xD2,
+ 0x18, 0xAD, 0x4B, 0xA5, 0x4E, 0xD4, 0x18, 0x02,
+ 0x25, 0xA4, 0x4F, 0x0D, 0xE0, 0xC2, 0x08, 0xA3,
+ 0x5C, 0x42, 0x07, 0x52, 0x0F, 0xD3, 0x40, 0x2A,
+ 0x46, 0xDB, 0x07, 0x00, 0xD1, 0x01, 0x22, 0x33,
+ 0x5C, 0x9B, 0x00, 0xDB, 0x19, 0x1A, 0x60, 0x40,
+ 0x1C, 0x88, 0x42, 0xEF, 0xD3,
+ 0x00, 0x00, 0xD3, 0x00, 0x80, 0xF0, 0xBD, 0xF8,
+ 0xB5, 0x98, 0x4B, 0x05, 0x46, 0x01, 0x46, 0x18,
+ 0x7B, 0xFF, 0xF7, 0x47, 0xFC, 0x04, 0x46, 0x18,
+ 0x7B, 0x02, 0x28, 0x00, 0xD0, 0x0F, 0x20, 0xFF,
+ 0xF7, 0xB5, 0xFE, 0x16, 0x20, 0x44, 0x43, 0x90,
+ 0x48, 0x00, 0x21, 0x91, 0x4F, 0x91, 0x4E, 0x20,
+ 0x18, 0x8D, 0x4A, 0x12, 0x5B, 0x01, 0x23, 0x8B,
+ 0x40, 0x1A, 0x42, 0x06, 0xD0, 0x42, 0x18, 0x53,
+ 0x7B, 0x12, 0x79, 0xBA, 0x5C, 0x92, 0x00, 0x92,
+ 0x19, 0x13, 0x60, 0x49, 0x1C, 0x08, 0x29, 0xEF,
+ 0xD3, 0x86, 0x49, 0x8B, 0x4C, 0x09, 0x7B, 0x60,
+ 0x3C, 0x02, 0x29, 0x01, 0xD1, 0xC0, 0x78, 0x03,
+ 0xE0, 0x04, 0x29, 0x18, 0xD1, 0x8B, 0x48, 0x40,
+ 0x5D, 0xFF, 0x28, 0x03, 0xD0, 0x0C, 0x22, 0x80,
+ 0x00, 0x80, 0x19, 0x02, 0x60, 0x04, 0x29, 0x0E,
+ 0xD1, 0x20, 0x6B, 0xEA, 0x07, 0x40, 0x00, 0xD2,
+ 0x0F, 0xA8, 0x42, 0x04, 0xD9,
+ 0x00, 0x00, 0xD4, 0x00, 0x80, 0xE0, 0x69, 0xA1,
+ 0x69, 0x41, 0x18, 0xE0, 0x69, 0x01, 0xE0, 0xE1,
+ 0x69, 0x00, 0x20, 0xFF, 0xF7, 0x9E, 0xFF, 0x75,
+ 0x48, 0x00, 0x7B, 0x08, 0x28, 0x0E, 0xD1, 0xE0,
+ 0x69, 0xA1, 0x69, 0x40, 0x18, 0xA1, 0x6A, 0x40,
+ 0x18, 0x75, 0x49, 0x20, 0x39, 0x09, 0x6A, 0x01,
+ 0x29, 0x04, 0xD0, 0x38, 0x5C, 0x01, 0x21, 0x80,
+ 0x00, 0x80, 0x19, 0x01, 0x60, 0xF8, 0xBD, 0xFE,
+ 0xB5, 0x6F, 0x4A, 0x14, 0x25, 0x60, 0x3A, 0xD0,
+ 0x6A, 0x01, 0x90, 0x68, 0x48, 0x00, 0x21, 0x44,
+ 0x78, 0x86, 0x78, 0x41, 0x73, 0x01, 0x72, 0x81,
+ 0x71, 0xC1, 0x71, 0xC1, 0x70, 0xC1, 0x73, 0x41,
+ 0x74, 0x63, 0x1E, 0x83, 0x74, 0x41, 0x75, 0xC1,
+ 0x72, 0x11, 0x6A, 0x49, 0x1E, 0x81, 0x72, 0x00,
+ 0x20, 0xFF, 0xF7, 0x89, 0xFF, 0x00, 0x20, 0xFF,
+ 0xF7, 0xE9, 0xFE, 0x03, 0xF0, 0xED, 0xFF, 0x00,
+ 0x20, 0x04, 0xF0, 0x14, 0xF8,
+ 0x00, 0x00, 0xD5, 0x00, 0x80, 0x04, 0xF0, 0x04,
+ 0xF8, 0x5D, 0x4F, 0x20, 0x3F, 0x38, 0x69, 0x00,
+ 0x28, 0x08, 0xD0, 0x56, 0x4A, 0x56, 0x49, 0x92,
+ 0x7A, 0x0C, 0x20, 0x89, 0x5C, 0x55, 0x4A, 0x89,
+ 0x00, 0x89, 0x18, 0x08, 0x60, 0xF8, 0x69, 0x02,
+ 0x28, 0x07, 0xD1, 0x00, 0x21, 0x08, 0x46, 0xFF,
+ 0xF7, 0xE3, 0xFE, 0xE4, 0x1C, 0xA4, 0x08, 0xA4,
+ 0x00, 0x06, 0xE0, 0x4D, 0x49, 0x4D, 0x4A, 0x89,
+ 0x5D, 0x01, 0x20, 0x89, 0x00, 0x89, 0x18, 0x08,
+ 0x60, 0x01, 0x98, 0x60, 0x43, 0x47, 0x4C, 0xA0,
+ 0x73, 0x4B, 0x48, 0xC0, 0x7B, 0xFF, 0xF7, 0x03,
+ 0xFF, 0x48, 0x48, 0x4F, 0x49, 0x80, 0x38, 0xC1,
+ 0x60, 0x02, 0xF0, 0x7C, 0xFF, 0x00, 0x90, 0x45,
+ 0x48, 0x80, 0x38, 0x00, 0x68, 0x03, 0x21, 0x49,
+ 0x07, 0x08, 0x43, 0x42, 0x49, 0x80, 0x39, 0x08,
+ 0x60, 0x40, 0x48, 0x80, 0x38, 0x00, 0x68, 0x80,
+ 0x00, 0x01, 0xD5, 0x6D, 0x1E,
+ 0x00, 0x00, 0xD6, 0x00, 0x80, 0xF8, 0xD2, 0xF8,
+ 0x69, 0x02, 0x28, 0x05, 0xD1, 0x01, 0x21, 0x00,
+ 0x20, 0xFF, 0xF7, 0xB2, 0xFE, 0x00, 0x20, 0x0C,
+ 0xE0, 0x35, 0x4A, 0x0F, 0x20, 0x91, 0x5D, 0x8B,
+ 0x00, 0x34, 0x49, 0x5B, 0x18, 0x18, 0x60, 0x92,
+ 0x19, 0x52, 0x78, 0x01, 0x20, 0x92, 0x00, 0x51,
+ 0x18, 0x08, 0x60, 0x60, 0x72, 0x01, 0x20, 0xFF,
+ 0xF7, 0x89, 0xFE, 0x30, 0x48, 0x80, 0x38, 0x01,
+ 0x68, 0x03, 0x22, 0x52, 0x07, 0x11, 0x43, 0x01,
+ 0x60, 0x01, 0x69, 0x02, 0x22, 0x11, 0x43, 0x01,
+ 0x61, 0x00, 0x98, 0x02, 0xF0, 0x47, 0xFF, 0xFE,
+ 0xBD, 0x10, 0xB5, 0x24, 0x4C, 0x00, 0x21, 0xE1,
+ 0x72, 0x61, 0x75, 0x2E, 0x49, 0x89, 0x69, 0x01,
+ 0x22, 0x12, 0x03, 0x09, 0x02, 0x80, 0x18, 0x01,
+ 0x43, 0x22, 0x48, 0x40, 0x30, 0x01, 0x60, 0x03,
+ 0xF0, 0x6F, 0xFF, 0xA0, 0x79, 0xFF, 0xF7, 0x03,
+ 0xFF, 0xA0, 0x79, 0xFF, 0xF7,
+ 0x00, 0x00, 0xD7, 0x00, 0x80, 0x63, 0xFE, 0xA0,
+ 0x79, 0x03, 0xF0, 0x90, 0xFF, 0x03, 0xF0, 0x80,
+ 0xFF, 0x1A, 0x4C, 0x80, 0x3C, 0x20, 0x68, 0x00,
+ 0x28, 0x02, 0xD0, 0x00, 0x20, 0xFF, 0xF7, 0x9F,
+ 0xFE, 0x1D, 0x48, 0xE0, 0x60, 0x02, 0xF0, 0x1A,
+ 0xFF, 0x21, 0x69, 0x02, 0x22, 0x11, 0x43, 0x21,
+ 0x61, 0x21, 0x68, 0x03, 0x22, 0x52, 0x07, 0x11,
+ 0x43, 0x21, 0x60, 0x02, 0xF0, 0x13, 0xFF, 0x10,
+ 0xBD, 0x17, 0x49, 0x02, 0x20, 0x08, 0x70, 0x0E,
+ 0x48, 0x60, 0x38, 0x41, 0x6B, 0x02, 0x6B, 0x8A,
+ 0x18, 0x06, 0x49, 0x8A, 0x73, 0x00, 0x6B, 0x88,
+ 0x71, 0xC0, 0xB2, 0x40, 0x1C, 0xC8, 0x71, 0x11,
+ 0x48, 0x00, 0x78, 0xB9, 0xE7, 0x00, 0x0F, 0x08,
+ 0x08, 0x2C, 0xE1, 0x00, 0x00, 0x6C, 0x01, 0x00,
+ 0x20, 0xC0, 0xE0, 0x00, 0x00, 0x00, 0x04, 0x11,
+ 0x40, 0x3C, 0x03, 0x00, 0x20, 0x80, 0x00, 0x11,
+ 0x40, 0xE8, 0xDF, 0x00, 0x00,
+ 0x00, 0x00, 0xD8, 0x00, 0x80, 0x98, 0xCD, 0x00,
+ 0x00, 0x88, 0x90, 0x00, 0x00, 0x00, 0xFF, 0x00,
+ 0xFF, 0x18, 0xE1, 0x00, 0x00, 0x04, 0xE1, 0x00,
+ 0x00, 0xFF, 0x03, 0x00, 0x00, 0x54, 0xE0, 0x00,
+ 0x00, 0xAC, 0x02, 0x00, 0x20, 0x36, 0x03, 0x00,
+ 0x20, 0xFD, 0x48, 0x01, 0x21, 0x01, 0x70, 0xFD,
+ 0x48, 0x02, 0x6B, 0xFD, 0x48, 0x82, 0x73, 0x00,
+ 0x22, 0x82, 0x71, 0xC1, 0x71, 0xFB, 0x48, 0x00,
+ 0x78, 0x8A, 0xE7, 0xFB, 0x49, 0x08, 0x70, 0xC1,
+ 0x07, 0x00, 0xD0, 0xED, 0xE7, 0x80, 0x07, 0x00,
+ 0xD5, 0xB6, 0xE7, 0x70, 0x47, 0x70, 0x47, 0xF0,
+ 0xB5, 0x00, 0x21, 0x08, 0x20, 0xFF, 0xF7, 0xE1,
+ 0xFA, 0xF4, 0x4C, 0x16, 0x22, 0x00, 0x21, 0xF4,
+ 0x4D, 0xF4, 0x4F, 0x50, 0x43, 0x06, 0x19, 0x22,
+ 0x5A, 0x01, 0x23, 0x8B, 0x40, 0x1A, 0x42, 0x06,
+ 0xD0, 0x72, 0x18, 0x53, 0x7B, 0x12, 0x79, 0xAA,
+ 0x5C, 0x92, 0x00, 0xD2, 0x19,
+ 0x00, 0x00, 0xD9, 0x00, 0x80, 0x13, 0x60, 0x49,
+ 0x1C, 0x08, 0x29, 0xF0, 0xD3, 0xE5, 0x48, 0x40,
+ 0x30, 0x00, 0x6A, 0x03, 0x28, 0x0A, 0xD1, 0xE3,
+ 0x48, 0xC1, 0x69, 0x82, 0x69, 0x80, 0x6A, 0x89,
+ 0x18, 0x08, 0x18, 0x28, 0x5C, 0x02, 0x21, 0x80,
+ 0x00, 0xC0, 0x19, 0x01, 0x60, 0xF0, 0xBD, 0x10,
+ 0xB5, 0xDD, 0x4C, 0x00, 0x20, 0x60, 0x75, 0xFF,
+ 0xF7, 0x83, 0xFC, 0xE0, 0x8D, 0x60, 0x85, 0xFF,
+ 0xF7, 0xCA, 0xFF, 0x01, 0x20, 0xFF, 0xF7, 0xC2,
+ 0xFD, 0xDD, 0x48, 0xA0, 0x63, 0xDE, 0x48, 0xDD,
+ 0x49, 0xC1, 0x60, 0x01, 0x68, 0x82, 0x03, 0x11,
+ 0x43, 0x01, 0x60, 0x01, 0x69, 0x02, 0x22, 0x11,
+ 0x43, 0x01, 0x61, 0x10, 0xBD, 0x10, 0xB5, 0xD0,
+ 0x4A, 0x00, 0x20, 0x50, 0x75, 0xCD, 0x49, 0xD0,
+ 0x72, 0x40, 0x31, 0x0B, 0x6A, 0x14, 0x46, 0x2C,
+ 0x20, 0x20, 0x5E, 0x03, 0x2B, 0x01, 0xD1, 0xD3,
+ 0x49, 0x03, 0xE0, 0x0B, 0x6A,
+ 0x00, 0x00, 0xDA, 0x00, 0x80, 0xCE, 0x49, 0x02,
+ 0x2B, 0x06, 0xD1, 0x91, 0x63, 0x50, 0x85, 0x00,
+ 0x20, 0xFF, 0xF7, 0x39, 0xFE, 0x00, 0x20, 0x05,
+ 0xE0, 0x91, 0x63, 0xD0, 0x8D, 0x50, 0x85, 0xFF,
+ 0xF7, 0x9A, 0xFF, 0x01, 0x20, 0xFF, 0xF7, 0x92,
+ 0xFD, 0x00, 0x21, 0x08, 0x20, 0xFF, 0xF7, 0x79,
+ 0xFA, 0x16, 0x21, 0x48, 0x43, 0xBF, 0x49, 0x08,
+ 0x5A, 0x02, 0x04, 0xC3, 0x48, 0x01, 0x68, 0xFF,
+ 0x23, 0x1B, 0x04, 0x99, 0x43, 0x0A, 0x43, 0x02,
+ 0x60, 0xBE, 0x49, 0xC1, 0x60, 0x01, 0x68, 0x82,
+ 0x03, 0x11, 0x43, 0x01, 0x60, 0x01, 0x69, 0x02,
+ 0x22, 0x11, 0x43, 0x01, 0x61, 0x10, 0xBD, 0x70,
+ 0xB5, 0x05, 0x46, 0xB0, 0x48, 0x02, 0x6B, 0xB0,
+ 0x49, 0x20, 0x31, 0x48, 0x79, 0x82, 0x42, 0x00,
+ 0xD8, 0x88, 0x79, 0xFF, 0xF7, 0x46, 0xFD, 0x03,
+ 0xF0, 0x6F, 0xFE, 0xAB, 0x4E, 0x30, 0x8E, 0x03,
+ 0xF0, 0x87, 0xFE, 0xB1, 0x4C,
+ 0x00, 0x00, 0xDB, 0x00, 0x80, 0x20, 0x68, 0x00,
+ 0x28, 0x02, 0xD0, 0x00, 0x20, 0xFF, 0xF7, 0xA7,
+ 0xFD, 0x03, 0xF0, 0x5C, 0xFE, 0x00, 0x21, 0x00,
+ 0x28, 0x03, 0xD0, 0xAD, 0x48, 0x00, 0x78, 0x01,
+ 0x28, 0x05, 0xD1, 0x71, 0x77, 0x71, 0x86, 0xB1,
+ 0x77, 0xAA, 0x48, 0xF1, 0x63, 0x01, 0x60, 0x00,
+ 0x2D, 0x0E, 0xD0, 0x71, 0x75, 0xF1, 0x72, 0xB5,
+ 0x73, 0xA2, 0x48, 0xE0, 0x60, 0x20, 0x68, 0x03,
+ 0x21, 0x49, 0x07, 0x08, 0x43, 0x20, 0x60, 0x20,
+ 0x69, 0x02, 0x21, 0x08, 0x43, 0x20, 0x61, 0x70,
+ 0xBD, 0x01, 0x20, 0x70, 0x75, 0x70, 0xBD, 0x10,
+ 0xB5, 0x9B, 0x48, 0x41, 0x68, 0x92, 0x4C, 0x09,
+ 0x07, 0x09, 0x0F, 0x01, 0x29, 0x04, 0xD0, 0x98,
+ 0x49, 0xC0, 0x31, 0x49, 0x68, 0xC9, 0x00, 0x0C,
+ 0xD4, 0x01, 0x69, 0x02, 0x22, 0x91, 0x43, 0x01,
+ 0x61, 0xD1, 0x1E, 0xC1, 0x60, 0x05, 0x20, 0xFC,
+ 0xF7, 0x12, 0xFC, 0x8F, 0x48,
+ 0x00, 0x00, 0xDC, 0x00, 0x80, 0x60, 0x63, 0x01,
+ 0x20, 0x10, 0xBD, 0x60, 0x7D, 0x10, 0xBD, 0xF3,
+ 0xB5, 0x8E, 0x46, 0x85, 0x48, 0x00, 0x21, 0x01,
+ 0x74, 0xFF, 0x21, 0xC1, 0x73, 0x81, 0x48, 0x00,
+ 0x22, 0x84, 0x46, 0x1E, 0xE0, 0x16, 0x21, 0x16,
+ 0x46, 0x4E, 0x43, 0x82, 0x49, 0x00, 0x20, 0x77,
+ 0x18, 0xD3, 0xB2, 0x3C, 0x18, 0x25, 0x79, 0x00,
+ 0x99, 0x8D, 0x42, 0x0E, 0xD3, 0x7D, 0x4D, 0x24,
+ 0x79, 0x74, 0x45, 0x0A, 0xD8, 0xAC, 0x5B, 0x01,
+ 0x25, 0x85, 0x40, 0x2C, 0x42, 0x05, 0xD0, 0x76,
+ 0x4C, 0xE5, 0x7B, 0xFF, 0x2D, 0x00, 0xD1, 0xE3,
+ 0x73, 0x23, 0x74, 0x40, 0x1C, 0x08, 0x28, 0xE8,
+ 0xD3, 0x52, 0x1C, 0x60, 0x46, 0xC0, 0x6A, 0x90,
+ 0x42, 0xDC, 0xD8, 0xFC, 0xBD, 0xFF, 0xB5, 0x6E,
+ 0x4D, 0x04, 0x46, 0xAF, 0x78, 0x87, 0xB0, 0x10,
+ 0x46, 0x3A, 0x19, 0x19, 0x46, 0x14, 0x26, 0x02,
+ 0x97, 0x01, 0x92, 0xFF, 0xF7,
+ 0x00, 0x00, 0xDD, 0x00, 0x80, 0xC4, 0xFF, 0x00,
+ 0x21, 0x69, 0x73, 0xE0, 0xB2, 0x06, 0x90, 0x28,
+ 0x72, 0xE8, 0x7B, 0xA8, 0x71, 0xE8, 0x71, 0xE9,
+ 0x70, 0x06, 0x98, 0x68, 0x74, 0x08, 0x98, 0xA8,
+ 0x74, 0x69, 0x75, 0xE9, 0x72, 0xA8, 0x79, 0xFF,
+ 0xF7, 0x6E, 0xFD, 0x68, 0x78, 0xE9, 0x7B, 0x48,
+ 0x43, 0x00, 0x19, 0x03, 0x90, 0xFF, 0xF7, 0xCA,
+ 0xFC, 0x03, 0xF0, 0xCE, 0xFD, 0x59, 0x4F, 0x40,
+ 0x37, 0x39, 0x69, 0x38, 0x46, 0x20, 0x30, 0x05,
+ 0x90, 0x00, 0x29, 0x1C, 0xD0, 0x68, 0x78, 0x40,
+ 0x08, 0xA0, 0x42, 0x0A, 0xD8, 0xF8, 0x69, 0x02,
+ 0x28, 0x0B, 0xD1, 0x05, 0x98, 0x40, 0x7C, 0x00,
+ 0x28, 0x07, 0xD0, 0xE8, 0x7C, 0x40, 0x08, 0xA0,
+ 0x42, 0x03, 0xD9, 0x4E, 0x48, 0x00, 0x6A, 0x40,
+ 0x1E, 0x00, 0xE0, 0x02, 0x98, 0xA8, 0x72, 0x50,
+ 0x49, 0xAA, 0x7A, 0x0C, 0x20, 0x89, 0x5C, 0x4F,
+ 0x4A, 0x89, 0x00, 0x89, 0x18,
+ 0x00, 0x00, 0xDE, 0x00, 0x80, 0x08, 0x60, 0xF8,
+ 0x69, 0x08, 0x99, 0x09, 0x1B, 0x04, 0x91, 0x02,
+ 0x28, 0x0E, 0xD1, 0xE0, 0xB2, 0x00, 0x21, 0xFF,
+ 0xF7, 0xAF, 0xFC, 0x04, 0x98, 0x29, 0x7C, 0x00,
+ 0x1D, 0xEA, 0x7B, 0x80, 0x08, 0x89, 0x1A, 0x80,
+ 0x00, 0x49, 0x1C, 0x41, 0x43, 0xA9, 0x73, 0x0F,
+ 0xE0, 0x41, 0x4A, 0x01, 0x98, 0x01, 0x21, 0x10,
+ 0x5C, 0x40, 0x4A, 0x80, 0x00, 0x80, 0x18, 0x01,
+ 0x60, 0x28, 0x7C, 0xE9, 0x7B, 0x40, 0x1A, 0x04,
+ 0x99, 0x40, 0x1C, 0x49, 0x1C, 0x48, 0x43, 0xA8,
+ 0x73, 0x05, 0x98, 0xC0, 0x7B, 0xFF, 0xF7, 0xC3,
+ 0xFC, 0x3B, 0x49, 0x3A, 0x48, 0xC8, 0x60, 0x02,
+ 0xF0, 0x3D, 0xFD, 0x00, 0x90, 0x38, 0x48, 0x00,
+ 0x68, 0x03, 0x21, 0x49, 0x07, 0x08, 0x43, 0x36,
+ 0x49, 0x08, 0x60, 0x35, 0x48, 0x00, 0x68, 0x80,
+ 0x00, 0x01, 0xD5, 0x76, 0x1E, 0xF9, 0xD2, 0x03,
+ 0x98, 0x40, 0x1C, 0xFF, 0xF7,
+ 0x00, 0x00, 0xDF, 0x00, 0x80, 0x63, 0xFC, 0xF8,
+ 0x69, 0x0F, 0x26, 0x02, 0x28, 0x06, 0xD1, 0xE0,
+ 0xB2, 0x01, 0x21, 0xFF, 0xF7, 0x71, 0xFC, 0x06,
+ 0x98, 0x68, 0x72, 0x0F, 0xE0, 0x26, 0x48, 0x01,
+ 0x99, 0x26, 0x4B, 0x41, 0x5C, 0x89, 0x00, 0xC9,
+ 0x18, 0x0E, 0x60, 0x01, 0x9A, 0x01, 0x21, 0x80,
+ 0x18, 0x40, 0x78, 0x80, 0x00, 0xC0, 0x18, 0x01,
+ 0x60, 0x64, 0x1C, 0x6C, 0x72, 0x38, 0x69, 0x00,
+ 0x28, 0x1E, 0xD0, 0x68, 0x78, 0x41, 0x08, 0x68,
+ 0x7A, 0x81, 0x42, 0x0A, 0xD0, 0xF9, 0x69, 0x02,
+ 0x29, 0x16, 0xD1, 0x05, 0x99, 0x49, 0x7C, 0x00,
+ 0x29, 0x12, 0xD0, 0xE9, 0x7C, 0x49, 0x08, 0x81,
+ 0x42, 0x0E, 0xD9, 0x15, 0x49, 0xA8, 0x7A, 0x15,
+ 0x4A, 0x08, 0x5C, 0x80, 0x00, 0x80, 0x18, 0x06,
+ 0x60, 0x02, 0x98, 0x0C, 0x23, 0xC0, 0xB2, 0xA8,
+ 0x72, 0x08, 0x5C, 0x80, 0x00, 0x80, 0x18, 0x03,
+ 0x60, 0x11, 0x48, 0x01, 0x68,
+ 0x00, 0x00, 0xE0, 0x00, 0x80, 0x03, 0x22, 0x52,
+ 0x07, 0x11, 0x43, 0x01, 0x60, 0x01, 0x69, 0x02,
+ 0x22, 0x11, 0x43, 0x01, 0x61, 0x00, 0x98, 0x02,
+ 0xF0, 0xE5, 0xFC, 0x0B, 0xB0, 0xF0, 0xBD, 0x00,
+ 0x00, 0xAC, 0x02, 0x00, 0x20, 0x88, 0xDF, 0x00,
+ 0x00, 0x6C, 0x01, 0x00, 0x20, 0x35, 0x03, 0x00,
+ 0x20, 0xAB, 0x02, 0x00, 0x20, 0x2C, 0xE1, 0x00,
+ 0x00, 0xC0, 0xE0, 0x00, 0x00, 0x00, 0x04, 0x11,
+ 0x40, 0x49, 0x5F, 0x00, 0x00, 0xFF, 0x03, 0x00,
+ 0x00, 0x00, 0x00, 0x11, 0x40, 0xAB, 0x6C, 0x00,
+ 0x00, 0xA8, 0x02, 0x00, 0x20, 0xB0, 0x02, 0x00,
+ 0x20, 0x84, 0x49, 0x00, 0x28, 0x00, 0xD1, 0x84,
+ 0x48, 0x48, 0x63, 0x70, 0x47, 0x00, 0x28, 0x01,
+ 0xD0, 0x80, 0x49, 0x08, 0x64, 0x70, 0x47, 0x00,
+ 0x28, 0x01, 0xD0, 0x7E, 0x49, 0x48, 0x64, 0x70,
+ 0x47, 0x00, 0x28, 0x01, 0xD0, 0x7B, 0x49, 0x88,
+ 0x64, 0x70, 0x47, 0x7A, 0x49,
+ 0x00, 0x00, 0xE1, 0x00, 0x80, 0xC8, 0x75, 0x08,
+ 0x76, 0x7A, 0x48, 0x02, 0x6A, 0x7A, 0x48, 0x02,
+ 0x40, 0xC8, 0x7D, 0x02, 0x43, 0x00, 0x04, 0x02,
+ 0x43, 0x78, 0x48, 0x82, 0x62, 0x70, 0x47, 0x73,
+ 0x49, 0x74, 0x4A, 0x48, 0x76, 0xD3, 0x6D, 0xDB,
+ 0xB2, 0x83, 0x42, 0x00, 0xD3, 0xD0, 0x6D, 0x88,
+ 0x76, 0x72, 0x48, 0x82, 0x68, 0x49, 0x7E, 0x12,
+ 0x0A, 0x12, 0x02, 0x0A, 0x43, 0x82, 0x60, 0x70,
+ 0x47, 0x10, 0xB5, 0x6A, 0x49, 0x6D, 0x4A, 0xC8,
+ 0x76, 0x90, 0x68, 0xFF, 0x23, 0xC9, 0x7E, 0x1B,
+ 0x02, 0x98, 0x43, 0x09, 0x02, 0x08, 0x43, 0x90,
+ 0x60, 0xFE, 0xF7, 0xB5, 0xFF, 0x10, 0xBD, 0x10,
+ 0xB5, 0x62, 0x4C, 0x66, 0x4A, 0x20, 0x77, 0x91,
+ 0x68, 0xFF, 0x23, 0x1B, 0x02, 0x99, 0x43, 0xC3,
+ 0xB2, 0x1B, 0x02, 0x19, 0x43, 0x91, 0x60, 0x64,
+ 0x21, 0x41, 0x43, 0x61, 0x48, 0x40, 0x68, 0x80,
+ 0x03, 0x05, 0xF0, 0x81, 0xFC,
+ 0x00, 0x00, 0xE2, 0x00, 0x80, 0x20, 0x85, 0x10,
+ 0xBD, 0x58, 0x48, 0x40, 0x7F, 0x70, 0x47, 0x57,
+ 0x48, 0x20, 0x30, 0x80, 0x78, 0x70, 0x47, 0x55,
+ 0x48, 0x20, 0x30, 0xC0, 0x78, 0x70, 0x47, 0x53,
+ 0x48, 0x20, 0x30, 0x00, 0x79, 0x70, 0x47, 0x51,
+ 0x48, 0x80, 0x7F, 0xC0, 0x07, 0xC0, 0x0F, 0x70,
+ 0x47, 0x4E, 0x48, 0x40, 0x8E, 0xC0, 0xB2, 0x70,
+ 0x47, 0x4C, 0x48, 0x02, 0x21, 0x80, 0x7F, 0x08,
+ 0x40, 0x70, 0x47, 0x10, 0xB5, 0x04, 0x00, 0x04,
+ 0xD0, 0x20, 0x78, 0xFF, 0xF7, 0xB9, 0xFF, 0x64,
+ 0x78, 0x0F, 0xE0, 0x48, 0x48, 0x80, 0x68, 0x00,
+ 0x04, 0x00, 0x0E, 0xFF, 0xF7, 0xB1, 0xFF, 0x48,
+ 0x48, 0x20, 0x30, 0xC0, 0x79, 0xC0, 0x07, 0x01,
+ 0xD0, 0x04, 0x24, 0x00, 0xE0, 0x00, 0x24, 0x02,
+ 0x20, 0x04, 0x43, 0x60, 0x07, 0x02, 0xD5, 0x03,
+ 0xF0, 0x61, 0xFC, 0x01, 0xE0, 0x03, 0xF0, 0x62,
+ 0xFC, 0x40, 0x48, 0xA1, 0x07,
+ 0x00, 0x00, 0xE3, 0x00, 0x80, 0x01, 0xD4, 0x01,
+ 0x21, 0x00, 0xE0, 0x00, 0x21, 0x41, 0x70, 0x10,
+ 0xBD, 0x70, 0xB5, 0x36, 0x4D, 0x04, 0x00, 0x0B,
+ 0xD0, 0x20, 0x78, 0xFF, 0xF7, 0x72, 0xFF, 0xA0,
+ 0x78, 0x00, 0x07, 0x00, 0x0E, 0xE8, 0x77, 0xE0,
+ 0x78, 0xFF, 0xF7, 0x79, 0xFF, 0x60, 0x78, 0x0F,
+ 0xE0, 0x30, 0x4B, 0x18, 0x6A, 0xC0, 0xB2, 0xFF,
+ 0xF7, 0x64, 0xFF, 0xD8, 0x68, 0xF0, 0x21, 0x08,
+ 0x40, 0xE8, 0x77, 0x98, 0x68, 0xC0, 0xB2, 0xFF,
+ 0xF7, 0x6A, 0xFF, 0x2D, 0x48, 0x00, 0x68, 0xC0,
+ 0xB2, 0x00, 0xF0, 0x46, 0xF8, 0x70, 0xBD, 0x2A,
+ 0x49, 0x10, 0xB5, 0x00, 0x22, 0x40, 0x39, 0xCB,
+ 0x6A, 0x83, 0x42, 0x01, 0xD9, 0x02, 0x46, 0x27,
+ 0xE0, 0xCB, 0x6A, 0x8C, 0x6B, 0x1B, 0x19, 0x83,
+ 0x42, 0x01, 0xD9, 0xC9, 0x6A, 0x1F, 0xE0, 0xCB,
+ 0x6A, 0x8C, 0x6B, 0x1B, 0x19, 0xCC, 0x6B, 0x1B,
+ 0x19, 0x83, 0x42, 0x05, 0xD9,
+ 0x00, 0x00, 0xE4, 0x00, 0x80, 0xCA, 0x6A, 0x89,
+ 0x6B, 0x80, 0x1A, 0x40, 0x1A, 0x42, 0x08, 0x13,
+ 0xE0, 0xCB, 0x6A, 0x8C, 0x6B, 0x1C, 0x19, 0xCB,
+ 0x6B, 0x5B, 0x1C, 0xE3, 0x18, 0x83, 0x42, 0x07,
+ 0xD8, 0xCB, 0x6A, 0x8C, 0x6B, 0x1C, 0x19, 0xCB,
+ 0x6B, 0x9B, 0x1C, 0xE3, 0x18, 0x83, 0x42, 0x03,
+ 0xD9, 0xCA, 0x6A, 0xC9, 0x6B, 0x80, 0x1A, 0x42,
+ 0x1A, 0x10, 0x46, 0x10, 0xBD, 0x0B, 0x49, 0x02,
+ 0x46, 0x09, 0x7B, 0x00, 0x20, 0x04, 0x29, 0x0A,
+ 0xD1, 0x0D, 0x49, 0x40, 0x39, 0xCB, 0x6A, 0xD2,
+ 0x1A, 0x8B, 0x6B, 0xD2, 0x1A, 0xD2, 0x07, 0x02,
+ 0xD0, 0xC8, 0x69, 0x89, 0x69, 0x40, 0x18, 0x70,
+ 0x47, 0x10, 0xB5, 0x08, 0x49, 0x08, 0x70, 0xFE,
+ 0xF7, 0xEE, 0xFE, 0x10, 0xBD, 0x6C, 0x01, 0x00,
+ 0x20, 0x49, 0x5F, 0x00, 0x00, 0x48, 0xDE, 0x00,
+ 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x11,
+ 0x40, 0xC8, 0xDF, 0x00, 0x00,
+ 0x00, 0x00, 0xE5, 0x00, 0x80, 0x8C, 0x01, 0x00,
+ 0x20, 0xF8, 0x48, 0x00, 0x7B, 0xF8, 0x49, 0x08,
+ 0x71, 0x70, 0x47, 0x00, 0xB5, 0xF6, 0x4A, 0x10,
+ 0x78, 0x00, 0x28, 0x03, 0xD1, 0xFF, 0xF7, 0xF4,
+ 0xFF, 0x01, 0x20, 0x10, 0x70, 0x00, 0xBD, 0xF2,
+ 0x49, 0x00, 0x28, 0x02, 0xD1, 0xEF, 0x48, 0x1C,
+ 0x38, 0x03, 0xE0, 0x02, 0x28, 0x03, 0xD1, 0xED,
+ 0x48, 0x10, 0x38, 0xC8, 0x63, 0x70, 0x47, 0x01,
+ 0x28, 0xFC, 0xD1, 0xEA, 0x48, 0x00, 0x1F, 0xF8,
+ 0xE7, 0xE8, 0x49, 0xE9, 0x4A, 0x00, 0x28, 0x01,
+ 0xD1, 0x08, 0x7B, 0x02, 0xE0, 0x02, 0x28, 0x01,
+ 0xD1, 0x48, 0x7C, 0x10, 0x71, 0x70, 0x47, 0xFF,
+ 0xB5, 0x8D, 0xB0, 0x00, 0x20, 0x06, 0x90, 0x05,
+ 0x90, 0x01, 0x20, 0xE1, 0x4C, 0x03, 0x90, 0xE0,
+ 0x6B, 0x06, 0x88, 0x1A, 0x99, 0x01, 0x29, 0x0F,
+ 0xD1, 0x03, 0xF0, 0xA8, 0xFB, 0x00, 0x28, 0x01,
+ 0xD0, 0x02, 0x20, 0x03, 0x90,
+ 0x00, 0x00, 0xE6, 0x00, 0x80, 0xE0, 0x6B, 0x01,
+ 0x79, 0x06, 0x91, 0x05, 0x21, 0x41, 0x56, 0x70,
+ 0x20, 0x06, 0x40, 0x36, 0x09, 0x05, 0x91, 0x16,
+ 0xE0, 0x02, 0x29, 0x09, 0xD1, 0x81, 0x79, 0x06,
+ 0x91, 0x07, 0x21, 0x41, 0x56, 0x07, 0x20, 0x00,
+ 0x02, 0x06, 0x40, 0x36, 0x0A, 0x05, 0x91, 0x0A,
+ 0xE0, 0x03, 0x29, 0x08, 0xD1, 0x01, 0x7A, 0x06,
+ 0x91, 0x09, 0x21, 0x41, 0x56, 0x07, 0x20, 0x00,
+ 0x03, 0x06, 0x40, 0x36, 0x0B, 0x05, 0x91, 0x00,
+ 0x20, 0xF9, 0xE0, 0x00, 0x20, 0x02, 0x90, 0x10,
+ 0x98, 0xED, 0xE0, 0xFF, 0xF7, 0x73, 0xFF, 0x01,
+ 0x90, 0x09, 0x98, 0xFF, 0xF7, 0x3C, 0xFF, 0x16,
+ 0x21, 0x48, 0x43, 0xC4, 0x49, 0x40, 0x18, 0x0A,
+ 0x90, 0x00, 0x20, 0x08, 0x90, 0x04, 0x46, 0x05,
+ 0x46, 0x07, 0x90, 0x0A, 0x98, 0x07, 0x88, 0x03,
+ 0xF0, 0x69, 0xFB, 0x00, 0x28, 0x07, 0xD0, 0x04,
+ 0x98, 0x00, 0x28, 0x02, 0xD1,
+ 0x00, 0x00, 0xE7, 0x00, 0x80, 0x3F, 0x07, 0x3F,
+ 0x0F, 0x01, 0xE0, 0xF0, 0x20, 0x07, 0x40, 0xF8,
+ 0xB2, 0x86, 0x46, 0x17, 0x98, 0x00, 0x28, 0x3E,
+ 0xD0, 0xF0, 0x07, 0x3C, 0xD0, 0x00, 0x20, 0xF9,
+ 0x07, 0x22, 0xD0, 0x0A, 0x99, 0x09, 0x18, 0x09,
+ 0x79, 0x01, 0x9A, 0x0E, 0x9B, 0x89, 0x18, 0x4A,
+ 0x00, 0x9A, 0x5E, 0x0F, 0x9B, 0x59, 0x56, 0x0D,
+ 0x9B, 0x51, 0x1A, 0x02, 0x9A, 0x82, 0x18, 0x52,
+ 0x00, 0x9A, 0x5E, 0x51, 0x1A, 0x0A, 0x1E, 0x00,
+ 0xDA, 0x4A, 0x42, 0x17, 0x9B, 0x9A, 0x42, 0x01,
+ 0xDB, 0xFF, 0x2B, 0x09, 0xD1, 0x08, 0x9A, 0x64,
+ 0x18, 0x52, 0x1C, 0x08, 0x92, 0x00, 0x29, 0x03,
+ 0xDA, 0x07, 0x9A, 0x52, 0x1C, 0x6D, 0x18, 0x07,
+ 0x92, 0x7F, 0x08, 0x40, 0x1C, 0x00, 0x2F, 0xD6,
+ 0xD1, 0x08, 0x98, 0x01, 0x28, 0x0F, 0xDD, 0xA0,
+ 0x49, 0x80, 0x00, 0x08, 0x58, 0x60, 0x43, 0x04,
+ 0x12, 0x07, 0x98, 0x80, 0x00,
+ 0x00, 0x00, 0xE8, 0x00, 0x80, 0x08, 0x58, 0x68,
+ 0x43, 0x05, 0x12, 0x00, 0x2C, 0x00, 0xDA, 0x64,
+ 0x1C, 0x00, 0x2D, 0x00, 0xDA, 0x6D, 0x1C, 0x00,
+ 0x20, 0x84, 0x46, 0x70, 0x46, 0xC0, 0x07, 0x76,
+ 0xD0, 0x0A, 0x99, 0x60, 0x46, 0x08, 0x18, 0x00,
+ 0x79, 0x01, 0x99, 0x43, 0x18, 0x1A, 0x98, 0x03,
+ 0x28, 0x04, 0xD1, 0x92, 0x48, 0xC1, 0x69, 0x80,
+ 0x69, 0x08, 0x18, 0x1B, 0x1A, 0x02, 0x99, 0x60,
+ 0x46, 0x40, 0x18, 0x0D, 0x99, 0x40, 0x00, 0x08,
+ 0x5E, 0x59, 0x00, 0x0E, 0x9A, 0x0C, 0x91, 0x51,
+ 0x5E, 0x0F, 0x9A, 0xF7, 0x07, 0xD2, 0x56, 0x0B,
+ 0x92, 0x15, 0xD0, 0x8A, 0x1A, 0x90, 0x42, 0x02,
+ 0xDB, 0x07, 0x1B, 0x97, 0x42, 0x04, 0xDB, 0x90,
+ 0x42, 0x04, 0xDC, 0x07, 0x1B, 0x97, 0x42, 0x01,
+ 0xDD, 0x10, 0x46, 0x08, 0xE0, 0x67, 0x1B, 0xFF,
+ 0x1C, 0x06, 0x2F, 0x03, 0xD9, 0x90, 0x42, 0x01,
+ 0xDC, 0x40, 0x1B, 0x00, 0xE0,
+ 0x00, 0x00, 0xE9, 0x00, 0x80, 0x00, 0x1B, 0x72,
+ 0x07, 0x10, 0xD5, 0x42, 0x1A, 0x88, 0x42, 0x00,
+ 0xDC, 0x0A, 0x1A, 0x05, 0x9F, 0xBA, 0x42, 0x09,
+ 0xDA, 0x06, 0x9A, 0x00, 0x2A, 0x02, 0xD1, 0x40,
+ 0x18, 0x40, 0x10, 0x03, 0xE0, 0x4A, 0x00, 0x8A,
+ 0x18, 0x10, 0x18, 0x80, 0x10, 0xB2, 0x07, 0x06,
+ 0xD5, 0x88, 0x42, 0x01, 0xDD, 0x40, 0x1E, 0x02,
+ 0xE0, 0x88, 0x42, 0x00, 0xDA, 0x40, 0x1C, 0x70,
+ 0x4A, 0x90, 0x42, 0x02, 0xDC, 0xD2, 0x43, 0x90,
+ 0x42, 0x00, 0xDA, 0x10, 0x46, 0x0B, 0x9A, 0x12,
+ 0x18, 0x52, 0x1A, 0x7F, 0x2A, 0x09, 0xDD, 0x0B,
+ 0x98, 0x0E, 0x9A, 0x08, 0x1A, 0x0C, 0x99, 0x7F,
+ 0x30, 0x50, 0x52, 0x0F, 0x99, 0x7F, 0x20, 0xC8,
+ 0x54, 0x11, 0xE0, 0x7F, 0x27, 0xFF, 0x43, 0xBA,
+ 0x42, 0x08, 0xDA, 0x0B, 0x98, 0x0E, 0x9A, 0x08,
+ 0x1A, 0x0C, 0x99, 0x80, 0x38, 0x50, 0x52, 0x0F,
+ 0x98, 0xC7, 0x54, 0x04, 0xE0,
+ 0x00, 0x00, 0xEA, 0x00, 0x80, 0x0E, 0x9F, 0x0C,
+ 0x99, 0x78, 0x52, 0x0F, 0x98, 0xC2, 0x54, 0x70,
+ 0x46, 0x40, 0x08, 0x86, 0x46, 0x60, 0x46, 0x40,
+ 0x1C, 0x84, 0x46, 0x70, 0x46, 0x00, 0x28, 0x00,
+ 0xD0, 0x7B, 0xE7, 0x02, 0x98, 0x08, 0x30, 0xC0,
+ 0xB2, 0x02, 0x90, 0x09, 0x98, 0x40, 0x1C, 0x16,
+ 0x99, 0x09, 0x90, 0x88, 0x42, 0x00, 0xD2, 0x0C,
+ 0xE7, 0x04, 0x98, 0x40, 0x1C, 0xC0, 0xB2, 0x03,
+ 0x99, 0x04, 0x90, 0x88, 0x42, 0x00, 0xD2, 0x00,
+ 0xE7, 0x11, 0xB0, 0xF0, 0xBD, 0xF0, 0xB5, 0x0E,
+ 0x46, 0x85, 0xB0, 0x4A, 0x49, 0x05, 0x46, 0x94,
+ 0x46, 0x0B, 0x9F, 0x0A, 0x98, 0xCA, 0x6A, 0x8C,
+ 0x6B, 0xC9, 0x6B, 0x12, 0x19, 0x54, 0x18, 0x03,
+ 0x22, 0x61, 0x1C, 0x01, 0x93, 0x04, 0x92, 0x00,
+ 0x91, 0x02, 0x90, 0x03, 0x97, 0x23, 0x46, 0x62,
+ 0x46, 0x31, 0x46, 0x28, 0x46, 0xFF, 0xF7, 0xAF,
+ 0xFE, 0x05, 0xB0, 0xF0, 0xBD,
+ 0x00, 0x00, 0xEB, 0x00, 0x80, 0x7C, 0xB5, 0x3D,
+ 0x4D, 0x06, 0x46, 0x40, 0x35, 0x28, 0x6A, 0x37,
+ 0x4C, 0x01, 0x28, 0x0A, 0xD1, 0x36, 0x4A, 0x58,
+ 0x32, 0x11, 0x46, 0x4E, 0x39, 0x01, 0x92, 0x00,
+ 0x91, 0xE3, 0x7E, 0x08, 0x3A, 0x5A, 0x31, 0x30,
+ 0x46, 0x19, 0xE0, 0x31, 0x4A, 0x54, 0x32, 0x11,
+ 0x46, 0x4C, 0x39, 0x01, 0x92, 0x00, 0x91, 0xA3,
+ 0x7E, 0x08, 0x3A, 0x54, 0x31, 0x30, 0x46, 0xFF,
+ 0xF7, 0xC5, 0xFF, 0x28, 0x6A, 0x03, 0x28, 0x0C,
+ 0xD1, 0x29, 0x4A, 0x58, 0x32, 0x11, 0x46, 0x4E,
+ 0x39, 0x01, 0x92, 0x00, 0x91, 0xE3, 0x7E, 0x30,
+ 0x46, 0x08, 0x3A, 0x5A, 0x31, 0x10, 0x30, 0xFF,
+ 0xF7, 0xB5, 0xFF, 0x7C, 0xBD, 0x70, 0x47, 0x70,
+ 0xB5, 0x0E, 0x46, 0x24, 0x49, 0x86, 0xB0, 0xCC,
+ 0x6A, 0x03, 0x28, 0x02, 0xD1, 0x23, 0x46, 0x88,
+ 0x6B, 0x07, 0xE0, 0x01, 0x28, 0x02, 0xD1, 0x23,
+ 0x46, 0x08, 0x6B, 0x02, 0xE0,
+ 0x00, 0x00, 0xEC, 0x00, 0x80, 0x08, 0x6B, 0x03,
+ 0x19, 0x48, 0x6B, 0x1E, 0x49, 0xC5, 0x18, 0x01,
+ 0x22, 0x08, 0x46, 0x2D, 0x30, 0x02, 0x90, 0x15,
+ 0x48, 0x04, 0x92, 0x03, 0x91, 0x02, 0x7E, 0x18,
+ 0x1B, 0x00, 0x01, 0x01, 0x92, 0x80, 0x19, 0x00,
+ 0x95, 0x17, 0x4A, 0x18, 0x49, 0xFF, 0xF7, 0x57,
+ 0xFE, 0x06, 0xB0, 0x70, 0xBD, 0xFF, 0xB5, 0x8D,
+ 0xB0, 0x03, 0xF0, 0x08, 0xFA, 0x00, 0x28, 0x01,
+ 0xD0, 0x02, 0x20, 0x00, 0xE0, 0x01, 0x20, 0x01,
+ 0x90, 0x09, 0x48, 0xC0, 0x6B, 0x01, 0x88, 0x49,
+ 0x07, 0x49, 0x0F, 0x05, 0x91, 0x81, 0x78, 0x04,
+ 0x91, 0x03, 0x21, 0x41, 0x56, 0x03, 0x48, 0x03,
+ 0x91, 0xC0, 0x7D, 0x07, 0x90, 0x00, 0x20, 0x0A,
+ 0xE1, 0x0F, 0x98, 0x00, 0xE1, 0x20, 0xDE, 0x00,
+ 0x00, 0xC0, 0x01, 0x00, 0x20, 0x2C, 0xE1, 0x00,
+ 0x00, 0xF8, 0xCD, 0x00, 0x00, 0x88, 0xDF, 0x00,
+ 0x00, 0xFF, 0x1F, 0x00, 0x00,
+ 0x00, 0x00, 0xED, 0x00, 0x80, 0x85, 0x0C, 0x00,
+ 0x20, 0x5E, 0x0A, 0x00, 0x20, 0x6E, 0x07, 0x00,
+ 0x20, 0xF8, 0x49, 0x0D, 0x98, 0x09, 0x78, 0x48,
+ 0x43, 0x08, 0x90, 0xF7, 0x49, 0x0B, 0x98, 0x09,
+ 0x78, 0x48, 0x43, 0x0D, 0x99, 0x40, 0x18, 0xC0,
+ 0x00, 0x09, 0x90, 0x0B, 0x98, 0xFF, 0xF7, 0x93,
+ 0xFD, 0x16, 0x21, 0x48, 0x43, 0xF1, 0x49, 0x40,
+ 0x18, 0x0C, 0x90, 0x0D, 0x98, 0xD0, 0xE0, 0x00,
+ 0x27, 0x0C, 0x98, 0x06, 0x97, 0x3C, 0x46, 0x3D,
+ 0x46, 0x06, 0x88, 0x03, 0xF0, 0xBF, 0xF9, 0x00,
+ 0x28, 0x07, 0xD0, 0x02, 0x98, 0x00, 0x28, 0x02,
+ 0xD1, 0x36, 0x07, 0x36, 0x0F, 0x01, 0xE0, 0xF0,
+ 0x20, 0x06, 0x40, 0xF0, 0xB2, 0x84, 0x46, 0x07,
+ 0x98, 0x00, 0x28, 0x38, 0xD0, 0x05, 0x98, 0xC0,
+ 0x07, 0x35, 0xD0, 0x00, 0x20, 0xF1, 0x07, 0x1C,
+ 0xD0, 0x0C, 0x99, 0x09, 0x18, 0x09, 0x79, 0x08,
+ 0x9A, 0xE0, 0x4B, 0x52, 0x18,
+ 0x00, 0x00, 0xEE, 0x00, 0x80, 0xDE, 0x49, 0x89,
+ 0x56, 0x9A, 0x56, 0x16, 0x9B, 0x89, 0x1A, 0x09,
+ 0x9A, 0x12, 0x18, 0x9A, 0x56, 0x51, 0x1A, 0x0A,
+ 0x1E, 0x00, 0xDA, 0x4A, 0x42, 0x07, 0x9B, 0x9A,
+ 0x42, 0x07, 0xDA, 0x7F, 0x1C, 0x64, 0x18, 0x00,
+ 0x29, 0x03, 0xDA, 0x06, 0x9A, 0x52, 0x1C, 0x6D,
+ 0x18, 0x06, 0x92, 0x76, 0x08, 0x40, 0x1C, 0x00,
+ 0x2E, 0xDC, 0xD1, 0x01, 0x2F, 0x0F, 0xDD, 0xD2,
+ 0x49, 0xB8, 0x00, 0x08, 0x58, 0x60, 0x43, 0x04,
+ 0x12, 0x06, 0x98, 0x80, 0x00, 0x08, 0x58, 0x68,
+ 0x43, 0x05, 0x12, 0x00, 0x2C, 0x00, 0xDA, 0x64,
+ 0x1C, 0x00, 0x2D, 0x00, 0xDA, 0x6D, 0x1C, 0x00,
+ 0x26, 0x60, 0x46, 0xC0, 0x07, 0x6C, 0xD0, 0x0C,
+ 0x98, 0x80, 0x19, 0x01, 0x79, 0x09, 0x98, 0x16,
+ 0x9A, 0x80, 0x19, 0x10, 0x56, 0x08, 0x9A, 0x05,
+ 0x9B, 0x52, 0x18, 0xC1, 0x49, 0xDB, 0x07, 0x89,
+ 0x56, 0x17, 0xD0, 0xC0, 0x4B,
+ 0x00, 0x00, 0xEF, 0x00, 0x80, 0x9B, 0x56, 0xCB,
+ 0x1A, 0x98, 0x42, 0x02, 0xDB, 0x07, 0x1B, 0x9F,
+ 0x42, 0x04, 0xDB, 0x98, 0x42, 0x04, 0xDC, 0x07,
+ 0x1B, 0x9F, 0x42, 0x01, 0xDD, 0x18, 0x46, 0x08,
+ 0xE0, 0x67, 0x1B, 0xFF, 0x1C, 0x06, 0x2F, 0x03,
+ 0xD9, 0x98, 0x42, 0x01, 0xDC, 0x40, 0x1B, 0x00,
+ 0xE0, 0x00, 0x1B, 0x05, 0x9B, 0x5B, 0x07, 0x10,
+ 0xD5, 0x43, 0x1A, 0x88, 0x42, 0x00, 0xDC, 0x0B,
+ 0x1A, 0x03, 0x9F, 0xBB, 0x42, 0x09, 0xD2, 0x04,
+ 0x9B, 0x00, 0x2B, 0x02, 0xD1, 0x40, 0x18, 0x40,
+ 0x10, 0x03, 0xE0, 0x4B, 0x00, 0xCB, 0x18, 0x18,
+ 0x18, 0x80, 0x10, 0x05, 0x9B, 0x9B, 0x07, 0x06,
+ 0xD5, 0x88, 0x42, 0x01, 0xDD, 0x40, 0x1E, 0x02,
+ 0xE0, 0x88, 0x42, 0x00, 0xDA, 0x40, 0x1C, 0x7F,
+ 0x28, 0x01, 0xDD, 0x7F, 0x20, 0x04, 0xE0, 0x7F,
+ 0x23, 0xDB, 0x43, 0x98, 0x42, 0x00, 0xDA, 0x18,
+ 0x46, 0xA0, 0x4B, 0x9B, 0x56,
+ 0x00, 0x00, 0xF0, 0x00, 0x80, 0x9E, 0x46, 0x1F,
+ 0x18, 0x7B, 0x1A, 0x7F, 0x2B, 0x07, 0xDD, 0x70,
+ 0x46, 0x08, 0x1A, 0x9B, 0x49, 0x7F, 0x30, 0x88,
+ 0x54, 0x9A, 0x4B, 0x7F, 0x20, 0x0A, 0xE0, 0x7F,
+ 0x27, 0xFF, 0x43, 0xBB, 0x42, 0x08, 0xDA, 0x70,
+ 0x46, 0x08, 0x1A, 0x95, 0x49, 0x80, 0x38, 0x95,
+ 0x4B, 0x88, 0x54, 0x38, 0x46, 0x98, 0x54, 0x03,
+ 0xE0, 0x91, 0x49, 0x88, 0x54, 0x91, 0x48, 0x83,
+ 0x54, 0x60, 0x46, 0x40, 0x08, 0x76, 0x1C, 0x84,
+ 0x46, 0x00, 0x28, 0x89, 0xD1, 0x09, 0x98, 0x89,
+ 0x49, 0x08, 0x30, 0x09, 0x90, 0x09, 0x78, 0x08,
+ 0x98, 0x40, 0x18, 0x08, 0x90, 0x0A, 0x98, 0x40,
+ 0x1C, 0x0E, 0x99, 0x0A, 0x90, 0x88, 0x42, 0x00,
+ 0xD8, 0x29, 0xE7, 0x0B, 0x98, 0x40, 0x1C, 0x0B,
+ 0x90, 0x10, 0x99, 0x88, 0x42, 0x00, 0xD8, 0x0B,
+ 0xE7, 0x02, 0x98, 0x40, 0x1C, 0xC0, 0xB2, 0x01,
+ 0x99, 0x02, 0x90, 0x88, 0x42,
+ 0x00, 0x00, 0xF1, 0x00, 0x80, 0x00, 0xD2, 0xEF,
+ 0xE6, 0x5E, 0xE6, 0x08, 0xB5, 0x00, 0x90, 0x7F,
+ 0x48, 0xC3, 0x6A, 0x79, 0x48, 0x00, 0x22, 0x01,
+ 0x78, 0x5B, 0x1E, 0x49, 0x1E, 0x10, 0x46, 0xFF,
+ 0xF7, 0xC9, 0xFE, 0x08, 0xBD, 0xF8, 0xB5, 0x04,
+ 0x46, 0x0D, 0x46, 0x10, 0x46, 0x19, 0x46, 0x06,
+ 0x9E, 0xFF, 0xF7, 0xAD, 0xFA, 0x76, 0x48, 0x00,
+ 0x96, 0x03, 0x78, 0x76, 0x48, 0x29, 0x46, 0x02,
+ 0x78, 0x20, 0x46, 0xFF, 0xF7, 0xB7, 0xFE, 0xF8,
+ 0xBD, 0x30, 0xB5, 0x70, 0x48, 0x80, 0x6A, 0x00,
+ 0x28, 0x0B, 0xD0, 0x71, 0x4A, 0x00, 0x21, 0x14,
+ 0x46, 0x13, 0x1D, 0x0C, 0x3C, 0x25, 0x1D, 0x40,
+ 0x1E, 0x11, 0x54, 0x19, 0x54, 0x21, 0x54, 0x29,
+ 0x54, 0xF9, 0xD1, 0x30, 0xBD, 0x70, 0xB5, 0x6A,
+ 0x4D, 0x6A, 0x48, 0x4C, 0x3D, 0xEC, 0x6B, 0xE8,
+ 0x63, 0xFE, 0xF7, 0xA0, 0xFE, 0xFF, 0xF7, 0xF2,
+ 0xF9, 0xFF, 0xF7, 0x69, 0xFA,
+ 0x00, 0x00, 0xF2, 0x00, 0x80, 0x00, 0x28, 0xFB,
+ 0xD0, 0x65, 0x48, 0x00, 0x68, 0xFF, 0xF7, 0x3A,
+ 0xFE, 0xEC, 0x63, 0xFF, 0xF7, 0xD9, 0xFF, 0x70,
+ 0xBD, 0x70, 0x47, 0x5C, 0x48, 0x00, 0x6A, 0x61,
+ 0x4A, 0x00, 0x21, 0x40, 0x1E, 0x11, 0x54, 0xFC,
+ 0xD1, 0x52, 0x48, 0x56, 0x4A, 0x00, 0x78, 0x4E,
+ 0x3A, 0x11, 0x54, 0x40, 0x1E, 0xFC, 0xD1, 0x50,
+ 0x48, 0x52, 0x4A, 0x00, 0x78, 0x27, 0x3A, 0x11,
+ 0x54, 0x40, 0x1E, 0xFC, 0xD1, 0x54, 0x48, 0x4C,
+ 0x38, 0x81, 0x70, 0xC1, 0x70, 0x70, 0x47, 0x70,
+ 0xB5, 0x51, 0x4D, 0x52, 0x48, 0x4C, 0x3D, 0xEC,
+ 0x6B, 0xE8, 0x63, 0xFE, 0xF7, 0x5D, 0xFD, 0x03,
+ 0x20, 0xFF, 0xF7, 0x6F, 0xF9, 0xFF, 0xF7, 0x37,
+ 0xFA, 0x00, 0x28, 0xFB, 0xD0, 0x4E, 0x48, 0x01,
+ 0x68, 0x03, 0x20, 0xFF, 0xF7, 0x38, 0xFE, 0xEC,
+ 0x63, 0xFF, 0xF7, 0xCF, 0xFF, 0x70, 0xBD, 0x43,
+ 0x48, 0x40, 0x6A, 0x40, 0x4A,
+ 0x00, 0x00, 0xF3, 0x00, 0x80, 0x00, 0x21, 0x40,
+ 0x1E, 0x11, 0x54, 0xFC, 0xD1, 0x39, 0x48, 0x3D,
+ 0x4A, 0x00, 0x78, 0x9C, 0x3A, 0x11, 0x54, 0x40,
+ 0x1E, 0xFC, 0xD1, 0x37, 0x48, 0x39, 0x4A, 0x00,
+ 0x78, 0x75, 0x3A, 0x11, 0x54, 0x40, 0x1E, 0xFC,
+ 0xD1, 0x70, 0x47, 0x70, 0xB5, 0x3A, 0x4D, 0x3B,
+ 0x48, 0x4C, 0x3D, 0xEC, 0x6B, 0xE8, 0x63, 0xFE,
+ 0xF7, 0x56, 0xFC, 0xFF, 0xF7, 0x40, 0xF8, 0xFF,
+ 0xF7, 0x0A, 0xFA, 0x00, 0x28, 0xFB, 0xD0, 0x39,
+ 0x48, 0x00, 0x68, 0xFF, 0xF7, 0x5E, 0xFF, 0xEC,
+ 0x63, 0xFF, 0xF7, 0xD5, 0xFF, 0x70, 0xBD, 0x70,
+ 0x47, 0xF0, 0xB5, 0x2C, 0x48, 0x8B, 0xB0, 0x80,
+ 0x6A, 0x0A, 0x90, 0x2E, 0x48, 0x00, 0x1D, 0xC5,
+ 0x7A, 0x01, 0x7C, 0x07, 0x91, 0x01, 0x7C, 0x06,
+ 0x91, 0x41, 0x7D, 0x4E, 0x07, 0x81, 0x7D, 0x76,
+ 0x0F, 0x4F, 0x07, 0x41, 0x7D, 0x7F, 0x0F, 0xC9,
+ 0x08, 0x05, 0x91, 0x81, 0x7D,
+ 0x00, 0x00, 0xF4, 0x00, 0x80, 0xC9, 0x08, 0x04,
+ 0x91, 0x31, 0x46, 0x39, 0x43, 0x0A, 0xD1, 0x41,
+ 0x7A, 0x49, 0x00, 0x09, 0x91, 0x40, 0x7A, 0x40,
+ 0x00, 0x08, 0x90, 0x00, 0x20, 0x03, 0x90, 0x02,
+ 0x90, 0x01, 0x90, 0x15, 0xE0, 0xA8, 0x19, 0x40,
+ 0x1C, 0x09, 0x90, 0xE8, 0x19, 0x40, 0x1C, 0x08,
+ 0x90, 0x15, 0x48, 0x08, 0x38, 0x81, 0x5D, 0x03,
+ 0x91, 0xC0, 0x5D, 0x02, 0x90, 0x12, 0x48, 0xB1,
+ 0x00, 0x09, 0x18, 0x49, 0x68, 0xC9, 0xB2, 0x01,
+ 0x91, 0xB9, 0x00, 0x08, 0x18, 0x40, 0x68, 0xC0,
+ 0xB2, 0x00, 0x90, 0x00, 0x20, 0x09, 0xE0, 0x10,
+ 0x4A, 0x0C, 0x3A, 0x11, 0x5C, 0x49, 0x1C, 0x11,
+ 0x54, 0x12, 0x1D, 0x11, 0x5C, 0x49, 0x1C, 0x11,
+ 0x54, 0x40, 0x1C, 0x0A, 0x99, 0x88, 0x42, 0xF2,
+ 0xD3, 0x00, 0x24, 0xB8, 0xE0, 0x6E, 0x01, 0x00,
+ 0x20, 0x6D, 0x01, 0x00, 0x20, 0x2C, 0xE1, 0x00,
+ 0x00, 0x74, 0x05, 0x00, 0x20,
+ 0x00, 0x00, 0xF5, 0x00, 0x80, 0x64, 0x08, 0x00,
+ 0x20, 0xF8, 0xCD, 0x00, 0x00, 0x88, 0xDF, 0x00,
+ 0x00, 0x7C, 0x01, 0x00, 0x20, 0x7B, 0x01, 0x00,
+ 0x20, 0x0C, 0x02, 0x00, 0x20, 0x1C, 0xDE, 0x00,
+ 0x00, 0xB4, 0x01, 0x00, 0x20, 0x5E, 0x0A, 0x00,
+ 0x20, 0xB0, 0x01, 0x00, 0x20, 0xAC, 0x01, 0x00,
+ 0x20, 0xFE, 0x48, 0x07, 0x99, 0x00, 0x57, 0x88,
+ 0x42, 0x0A, 0xDD, 0xF9, 0xF7, 0x4A, 0xFD, 0x00,
+ 0x28, 0x02, 0xD1, 0xFA, 0x49, 0x0C, 0x39, 0x02,
+ 0xE0, 0xF8, 0x49, 0x00, 0x20, 0x08, 0x39, 0x08,
+ 0x55, 0xF6, 0x48, 0x06, 0x99, 0x00, 0x1D, 0x00,
+ 0x57, 0x88, 0x42, 0x0A, 0xDD, 0xF9, 0xF7, 0x39,
+ 0xFD, 0x00, 0x28, 0x02, 0xD1, 0xF1, 0x49, 0x08,
+ 0x39, 0x02, 0xE0, 0xF0, 0x49, 0x00, 0x20, 0x0C,
+ 0x39, 0x08, 0x55, 0xEE, 0x48, 0x0C, 0x38, 0x00,
+ 0x5D, 0xA8, 0x42, 0x35, 0xD3, 0xA8, 0x42, 0x02,
+ 0xD1, 0xEA, 0x48, 0x00, 0x5D,
+ 0x00, 0x00, 0xF6, 0x00, 0x80, 0x20, 0xE0, 0x09,
+ 0x99, 0x88, 0x42, 0x21, 0xD2, 0x00, 0x2E, 0x2B,
+ 0xD0, 0xE6, 0x48, 0xE6, 0x49, 0x00, 0x57, 0x08,
+ 0x31, 0x0A, 0x57, 0x84, 0x46, 0x80, 0x1A, 0x01,
+ 0x1E, 0x00, 0xDA, 0x41, 0x42, 0x05, 0x9B, 0x99,
+ 0x42, 0x01, 0xDD, 0x1F, 0x2B, 0x08, 0xD1, 0x03,
+ 0x9B, 0xDE, 0x49, 0xC0, 0x18, 0x01, 0x9B, 0x08,
+ 0x31, 0x58, 0x43, 0x00, 0x12, 0x10, 0x18, 0x05,
+ 0xE0, 0xDA, 0x48, 0x0C, 0x38, 0x05, 0x55, 0x60,
+ 0x46, 0xD8, 0x49, 0x08, 0x31, 0x08, 0x55, 0x0B,
+ 0xE0, 0xD6, 0x49, 0x0B, 0x46, 0x08, 0x33, 0x08,
+ 0x5D, 0x1A, 0x5D, 0x80, 0x1A, 0x08, 0x55, 0x00,
+ 0x20, 0x0C, 0x39, 0x08, 0x55, 0x19, 0x46, 0xF1,
+ 0xE7, 0xD0, 0x48, 0x08, 0x38, 0x00, 0x5D, 0xA8,
+ 0x42, 0x38, 0xD3, 0xA8, 0x42, 0x03, 0xD1, 0xCD,
+ 0x48, 0x00, 0x1D, 0x00, 0x5D, 0x22, 0xE0, 0x08,
+ 0x99, 0x88, 0x42, 0x23, 0xD2,
+ 0x00, 0x00, 0xF7, 0x00, 0x80, 0x00, 0x2F, 0x2D,
+ 0xD0, 0xC8, 0x48, 0xC8, 0x49, 0x00, 0x1D, 0x00,
+ 0x57, 0x0C, 0x31, 0x0A, 0x57, 0x84, 0x46, 0x80,
+ 0x1A, 0x01, 0x1E, 0x00, 0xDA, 0x41, 0x42, 0x04,
+ 0x9B, 0x99, 0x42, 0x01, 0xDD, 0x1F, 0x2B, 0x09,
+ 0xD1, 0x02, 0x99, 0xC0, 0x4B, 0x40, 0x18, 0x00,
+ 0x99, 0x0C, 0x33, 0x48, 0x43, 0x00, 0x12, 0x10,
+ 0x18, 0x19, 0x46, 0x05, 0xE0, 0xBB, 0x48, 0x08,
+ 0x38, 0x05, 0x55, 0x60, 0x46, 0xB9, 0x49, 0x0C,
+ 0x31, 0x08, 0x55, 0x0B, 0xE0, 0xB7, 0x4A, 0x12,
+ 0x1D, 0x11, 0x46, 0x08, 0x31, 0x10, 0x5D, 0x0B,
+ 0x5D, 0xC0, 0x1A, 0x10, 0x55, 0x00, 0x20, 0x0C,
+ 0x3A, 0x10, 0x55, 0xF1, 0xE7, 0x64, 0x1C, 0x0A,
+ 0x98, 0x84, 0x42, 0x00, 0xD2, 0x60, 0xE7, 0x0B,
+ 0xB0, 0xF0, 0xBD, 0x70, 0x47, 0xF0, 0xB5, 0xAE,
+ 0x48, 0x8B, 0xB0, 0x00, 0x78, 0x08, 0x90, 0xAD,
+ 0x48, 0x00, 0x78, 0x07, 0x90,
+ 0x00, 0x00, 0xF8, 0x00, 0x80, 0xAC, 0x48, 0x46,
+ 0x7A, 0xAC, 0x49, 0x09, 0x89, 0x05, 0x91, 0x41,
+ 0x7B, 0x04, 0x91, 0xC1, 0x7C, 0x49, 0x07, 0x49,
+ 0x0F, 0x03, 0x91, 0xC1, 0x7C, 0xC9, 0x08, 0x02,
+ 0x91, 0x03, 0x99, 0x00, 0x29, 0x05, 0xD1, 0x40,
+ 0x7A, 0x40, 0x00, 0x06, 0x90, 0x00, 0x20, 0x01,
+ 0x90, 0x0B, 0xE0, 0x70, 0x18, 0x40, 0x1C, 0x06,
+ 0x90, 0xA1, 0x48, 0x40, 0x5C, 0x01, 0x90, 0xA0,
+ 0x48, 0x89, 0x00, 0x08, 0x30, 0x08, 0x18, 0x40,
+ 0x68, 0xC0, 0xB2, 0x98, 0x4A, 0x00, 0x90, 0x00,
+ 0x20, 0x4C, 0x3A, 0x90, 0x64, 0xD0, 0x70, 0x90,
+ 0x70, 0x51, 0x78, 0xC8, 0x07, 0x06, 0xD0, 0x99,
+ 0x4C, 0x08, 0x98, 0x23, 0x5C, 0x5B, 0x1C, 0x23,
+ 0x54, 0x40, 0x1E, 0xFA, 0xD1, 0x88, 0x07, 0x07,
+ 0xD5, 0x94, 0x4C, 0x07, 0x98, 0x27, 0x34, 0x23,
+ 0x5C, 0x5B, 0x1C, 0x23, 0x54, 0x40, 0x1E, 0xFA,
+ 0xD1, 0xC8, 0x07, 0x60, 0xD0,
+ 0x00, 0x00, 0xF9, 0x00, 0x80, 0x05, 0x98, 0x08,
+ 0x9C, 0x40, 0x42, 0x0A, 0x90, 0x8E, 0x48, 0x64,
+ 0x1E, 0x05, 0x57, 0x0A, 0x98, 0x85, 0x42, 0x03,
+ 0xDA, 0x84, 0x49, 0x01, 0x20, 0x4C, 0x39, 0x88,
+ 0x70, 0x05, 0x98, 0x85, 0x42, 0x03, 0xDD, 0x81,
+ 0x49, 0x01, 0x20, 0x4C, 0x39, 0xC8, 0x70, 0x04,
+ 0x98, 0x85, 0x42, 0x16, 0xDD, 0x7D, 0x4F, 0x28,
+ 0x1A, 0x4C, 0x3F, 0xB9, 0x6C, 0x40, 0x18, 0xB8,
+ 0x64, 0xF9, 0xF7, 0x47, 0xFC, 0x00, 0x28, 0x05,
+ 0xD1, 0x79, 0x6A, 0x08, 0x55, 0xB9, 0x6A, 0x08,
+ 0x55, 0xF9, 0x6A, 0x05, 0xE0, 0xF9, 0x68, 0x00,
+ 0x20, 0x08, 0x55, 0x39, 0x69, 0x08, 0x55, 0x79,
+ 0x69, 0x08, 0x55, 0x72, 0x48, 0x4C, 0x38, 0x41,
+ 0x6A, 0x08, 0x5D, 0xB0, 0x42, 0x29, 0xD3, 0xB0,
+ 0x42, 0x02, 0xD1, 0x76, 0x48, 0x05, 0x55, 0x24,
+ 0xE0, 0x06, 0x9A, 0x90, 0x42, 0x19, 0xD2, 0x03,
+ 0x98, 0x00, 0x28, 0x1E, 0xD0,
+ 0x00, 0x00, 0xFA, 0x00, 0x80, 0x71, 0x4B, 0x18,
+ 0x57, 0x84, 0x46, 0x28, 0x1A, 0x02, 0x1E, 0x00,
+ 0xDA, 0x42, 0x42, 0x02, 0x9F, 0xBA, 0x42, 0x01,
+ 0xDD, 0x1F, 0x2F, 0x07, 0xD1, 0x01, 0x9A, 0x80,
+ 0x18, 0x00, 0x9A, 0x50, 0x43, 0x00, 0x12, 0x60,
+ 0x44, 0x18, 0x55, 0x0A, 0xE0, 0x0E, 0x55, 0x1D,
+ 0x55, 0x07, 0xE0, 0x66, 0x4A, 0x64, 0x4B, 0x10,
+ 0x5D, 0x28, 0x1A, 0x18, 0x55, 0x00, 0x20, 0x08,
+ 0x55, 0x10, 0x55, 0x00, 0x2C, 0xA2, 0xD1, 0x59,
+ 0x48, 0x4C, 0x38, 0x41, 0x78, 0x89, 0x07, 0x66,
+ 0xD5, 0x05, 0x99, 0x07, 0x9C, 0x49, 0x42, 0x09,
+ 0x91, 0x08, 0x98, 0x64, 0x1E, 0x27, 0x18, 0x5A,
+ 0x48, 0xC5, 0x57, 0x09, 0x98, 0x85, 0x42, 0x03,
+ 0xDA, 0x50, 0x49, 0x01, 0x20, 0x4C, 0x39, 0x88,
+ 0x70, 0x05, 0x98, 0x85, 0x42, 0x03, 0xDD, 0x4D,
+ 0x49, 0x01, 0x20, 0x4C, 0x39, 0xC8, 0x70, 0x04,
+ 0x98, 0x85, 0x42, 0x1A, 0xDD,
+ 0x00, 0x00, 0xFB, 0x00, 0x80, 0x29, 0x1A, 0x49,
+ 0x48, 0x4C, 0x38, 0x82, 0x6C, 0x89, 0x18, 0x81,
+ 0x64, 0xF9, 0xF7, 0xDF, 0xFB, 0x00, 0x28, 0x07,
+ 0xD1, 0x44, 0x49, 0x4C, 0x39, 0x0A, 0x6B, 0x10,
+ 0x55, 0x4A, 0x6B, 0x10, 0x55, 0x89, 0x6B, 0x07,
+ 0xE0, 0x40, 0x49, 0x00, 0x20, 0x4C, 0x39, 0x8A,
+ 0x69, 0x10, 0x55, 0xCA, 0x69, 0x10, 0x55, 0x09,
+ 0x6A, 0x08, 0x55, 0x3C, 0x48, 0x4C, 0x38, 0x01,
+ 0x6B, 0x08, 0x5D, 0xB0, 0x42, 0x29, 0xD3, 0xB0,
+ 0x42, 0x02, 0xD1, 0x40, 0x48, 0xC5, 0x55, 0x24,
+ 0xE0, 0x06, 0x9A, 0x90, 0x42, 0x19, 0xD2, 0x03,
+ 0x98, 0x00, 0x28, 0x1E, 0xD0, 0x3B, 0x48, 0xC0,
+ 0x57, 0x84, 0x46, 0x28, 0x1A, 0x02, 0x1E, 0x00,
+ 0xDA, 0x42, 0x42, 0x02, 0x9B, 0x9A, 0x42, 0x01,
+ 0xDD, 0x1F, 0x2B, 0x08, 0xD1, 0x01, 0x9B, 0x35,
+ 0x4A, 0xC0, 0x18, 0x00, 0x9B, 0x58, 0x43, 0x00,
+ 0x12, 0x60, 0x44, 0xD0, 0x55,
+ 0x00, 0x00, 0xFC, 0x00, 0x80, 0x09, 0xE0, 0x0E,
+ 0x55, 0xDF, 0xE7, 0x30, 0x4A, 0x2E, 0x4B, 0xD0,
+ 0x5D, 0x28, 0x1A, 0xD8, 0x55, 0x00, 0x20, 0x08,
+ 0x55, 0xF3, 0xE7, 0x00, 0x2C, 0x9C, 0xD1, 0xE6,
+ 0xE6, 0xF0, 0xB5, 0x23, 0x48, 0x87, 0xB0, 0x05,
+ 0x78, 0x22, 0x48, 0x07, 0x78, 0x22, 0x48, 0x01,
+ 0x7A, 0x06, 0x91, 0x81, 0x7C, 0x49, 0x07, 0x49,
+ 0x0F, 0x04, 0x91, 0x81, 0x7C, 0xC9, 0x08, 0x03,
+ 0x91, 0x04, 0x99, 0x00, 0x29, 0x05, 0xD1, 0x00,
+ 0x7A, 0x40, 0x00, 0x05, 0x90, 0x00, 0x20, 0x02,
+ 0x90, 0x0D, 0xE0, 0x06, 0x98, 0x40, 0x18, 0x40,
+ 0x1C, 0x05, 0x90, 0x19, 0x49, 0x04, 0x98, 0x08,
+ 0x5C, 0x02, 0x90, 0x04, 0x98, 0x08, 0x31, 0x80,
+ 0x00, 0x40, 0x18, 0x40, 0x68, 0xC0, 0xB2, 0x01,
+ 0x90, 0x0E, 0x48, 0x00, 0x21, 0x4C, 0x38, 0xC1,
+ 0x80, 0x40, 0x78, 0x02, 0x28, 0x08, 0xD0, 0x11,
+ 0x48, 0x2C, 0x46, 0x4E, 0x38,
+ 0x00, 0x00, 0xFD, 0x00, 0x80, 0x01, 0x5D, 0x49,
+ 0x1C, 0x01, 0x55, 0x64, 0x1E, 0xFA, 0xD1, 0x07,
+ 0xE0, 0x0C, 0x48, 0x3C, 0x46, 0x27, 0x38, 0x01,
+ 0x5D, 0x49, 0x1C, 0x01, 0x55, 0x64, 0x1E, 0xFA,
+ 0xD1, 0x00, 0x26, 0xF9, 0xF7, 0x56, 0xFB, 0x00,
+ 0x28, 0x4F, 0xD1, 0x2E, 0xE0, 0x0C, 0x02, 0x00,
+ 0x20, 0x6E, 0x01, 0x00, 0x20, 0x6D, 0x01, 0x00,
+ 0x20, 0x20, 0xDE, 0x00, 0x00, 0x90, 0xDD, 0x00,
+ 0x00, 0xF0, 0xCD, 0x00, 0x00, 0x16, 0x08, 0x00,
+ 0x20, 0x5E, 0x0A, 0x00, 0x20, 0x85, 0x0C, 0x00,
+ 0x20, 0x00, 0x20, 0x17, 0xE0, 0x79, 0x49, 0x0A,
+ 0x57, 0x79, 0x49, 0x64, 0x1C, 0x0B, 0x79, 0x9A,
+ 0x42, 0x0F, 0xDD, 0xCA, 0x88, 0x52, 0x1C, 0xCA,
+ 0x80, 0xCB, 0x68, 0x00, 0x22, 0x1A, 0x54, 0x0B,
+ 0x69, 0x1A, 0x54, 0x4B, 0x69, 0x1A, 0x54, 0x8B,
+ 0x69, 0x9A, 0x55, 0xCB, 0x69, 0x9A, 0x55, 0x09,
+ 0x6A, 0x8A, 0x55, 0x40, 0x1C,
+ 0x00, 0x00, 0xFE, 0x00, 0x80, 0xA8, 0x42, 0xE5,
+ 0xD3, 0x76, 0x1C, 0xBE, 0x42, 0xE0, 0xD3, 0x1E,
+ 0xE0, 0x00, 0x20, 0x17, 0xE0, 0x69, 0x49, 0x0A,
+ 0x57, 0x69, 0x49, 0x64, 0x1C, 0x0B, 0x79, 0x9A,
+ 0x42, 0x0F, 0xDD, 0xCA, 0x88, 0x52, 0x1C, 0xCA,
+ 0x80, 0x4B, 0x6A, 0x00, 0x22, 0x1A, 0x54, 0x8B,
+ 0x6A, 0x1A, 0x54, 0xCB, 0x6A, 0x1A, 0x54, 0x0B,
+ 0x6B, 0x9A, 0x55, 0x4B, 0x6B, 0x9A, 0x55, 0x89,
+ 0x6B, 0x8A, 0x55, 0x40, 0x1C, 0xA8, 0x42, 0xE5,
+ 0xD3, 0x76, 0x1C, 0xBE, 0x42, 0xE0, 0xD3, 0x5C,
+ 0x48, 0x40, 0x78, 0x02, 0x28, 0x5A, 0xD1, 0x00,
+ 0x20, 0x54, 0xE0, 0x59, 0x49, 0x06, 0x9A, 0x89,
+ 0x69, 0x8E, 0x46, 0x09, 0x5C, 0x91, 0x42, 0x4C,
+ 0xD3, 0x91, 0x42, 0x0C, 0xD1, 0x01, 0x46, 0x69,
+ 0x43, 0x00, 0x22, 0x52, 0x4E, 0x53, 0x4C, 0x03,
+ 0xE0, 0x73, 0x5C, 0x63, 0x54, 0x49, 0x1C, 0x52,
+ 0x1C, 0xAA, 0x42, 0xF9, 0xD3,
+ 0x00, 0x00, 0xFF, 0x00, 0x80, 0x3D, 0xE0, 0x05,
+ 0x9A, 0x91, 0x42, 0x26, 0xD2, 0x04, 0x99, 0x00,
+ 0x29, 0x37, 0xD0, 0x01, 0x46, 0x69, 0x43, 0x00,
+ 0x22, 0x17, 0xE0, 0x4A, 0x4C, 0x47, 0x4B, 0x64,
+ 0x56, 0x5B, 0x56, 0xA4, 0x46, 0x1B, 0x1B, 0x1C,
+ 0x1E, 0x00, 0xDA, 0x64, 0x42, 0x03, 0x9E, 0xB4,
+ 0x42, 0x01, 0xDD, 0x1F, 0x2E, 0x0C, 0xD1, 0x02,
+ 0x9E, 0x42, 0x4C, 0x9B, 0x19, 0x01, 0x9E, 0x73,
+ 0x43, 0x1B, 0x12, 0x63, 0x44, 0x63, 0x54, 0x49,
+ 0x1C, 0x52, 0x1C, 0xAA, 0x42, 0xE5, 0xD3, 0x18,
+ 0xE0, 0x72, 0x46, 0x06, 0x99, 0x11, 0x54, 0x40,
+ 0x1E, 0x13, 0xE0, 0x01, 0x46, 0x69, 0x43, 0x00,
+ 0x22, 0x38, 0x4C, 0x09, 0xE0, 0x35, 0x4B, 0x66,
+ 0x5C, 0x5B, 0x5C, 0x9B, 0x1B, 0x33, 0x4E, 0x73,
+ 0x54, 0x00, 0x23, 0x63, 0x54, 0x49, 0x1C, 0x52,
+ 0x1C, 0xAA, 0x42, 0xF3, 0xD3, 0x00, 0x22, 0x71,
+ 0x46, 0x0A, 0x54, 0x40, 0x1C,
+ 0x00, 0x01, 0x00, 0x00, 0x80, 0xB8, 0x42, 0xA8,
+ 0xD3, 0x07, 0xB0, 0xF0, 0xBD, 0x00, 0x20, 0x51,
+ 0xE0, 0x2B, 0x49, 0x06, 0x9A, 0xC9, 0x68, 0x8E,
+ 0x46, 0x09, 0x5C, 0x91, 0x42, 0x49, 0xD3, 0x91,
+ 0x42, 0x0B, 0xD1, 0x01, 0x46, 0x00, 0x22, 0x25,
+ 0x4E, 0x26, 0x4C, 0x03, 0xE0, 0x73, 0x5C, 0x63,
+ 0x54, 0x49, 0x19, 0x52, 0x1C, 0xBA, 0x42, 0xF9,
+ 0xD3, 0x3B, 0xE0, 0x05, 0x9A, 0x91, 0x42, 0x25,
+ 0xD2, 0x04, 0x99, 0x00, 0x29, 0x35, 0xD0, 0x01,
+ 0x46, 0x00, 0x22, 0x17, 0xE0, 0x1D, 0x4C, 0x1B,
+ 0x4B, 0x64, 0x56, 0x5B, 0x56, 0xA4, 0x46, 0x1B,
+ 0x1B, 0x1C, 0x1E, 0x00, 0xDA, 0x64, 0x42, 0x03,
+ 0x9E, 0xB4, 0x42, 0x01, 0xDD, 0x1F, 0x2E, 0x0C,
+ 0xD1, 0x02, 0x9E, 0x16, 0x4C, 0x9B, 0x19, 0x01,
+ 0x9E, 0x73, 0x43, 0x1B, 0x12, 0x63, 0x44, 0x63,
+ 0x54, 0x49, 0x19, 0x52, 0x1C, 0xBA, 0x42, 0xE5,
+ 0xD3, 0x17, 0xE0, 0x72, 0x46,
+ 0x00, 0x01, 0x01, 0x00, 0x80, 0x06, 0x99, 0x11,
+ 0x54, 0x40, 0x1E, 0x12, 0xE0, 0x01, 0x46, 0x00,
+ 0x22, 0x0C, 0x4C, 0x09, 0xE0, 0x09, 0x4B, 0x66,
+ 0x5C, 0x5B, 0x5C, 0x9B, 0x1B, 0x07, 0x4E, 0x73,
+ 0x54, 0x00, 0x23, 0x63, 0x54, 0x49, 0x19, 0x52,
+ 0x1C, 0xBA, 0x42, 0xF3, 0xD3, 0x00, 0x22, 0x71,
+ 0x46, 0x0A, 0x54, 0x40, 0x1C, 0xA8, 0x42, 0xAB,
+ 0xD3, 0xA6, 0xE7, 0x00, 0x00, 0x64, 0x08, 0x00,
+ 0x20, 0xC0, 0x01, 0x00, 0x20, 0x8B, 0x0A, 0x00,
+ 0x20, 0x10, 0xB5, 0xF8, 0x48, 0x40, 0x69, 0xF8,
+ 0x49, 0x08, 0x70, 0xF8, 0x49, 0x00, 0x20, 0x88,
+ 0x70, 0xF4, 0x48, 0x40, 0x30, 0x40, 0x8B, 0x80,
+ 0x07, 0xC0, 0x0F, 0xC8, 0x70, 0xF4, 0x48, 0x80,
+ 0x6A, 0x00, 0x28, 0x01, 0xD0, 0x04, 0xF0, 0x4A,
+ 0xFA, 0x10, 0xBD, 0xF0, 0x49, 0x01, 0x20, 0x08,
+ 0x74, 0x70, 0x47, 0xF7, 0xB5, 0x0F, 0x46, 0x16,
+ 0x46, 0xEE, 0x4C, 0x03, 0x20,
+ 0x00, 0x01, 0x02, 0x00, 0x80, 0xF9, 0xF7, 0x06,
+ 0xFA, 0xFF, 0xF7, 0x1B, 0xF8, 0x00, 0x20, 0xFF,
+ 0xF7, 0x3F, 0xF8, 0xEC, 0x4D, 0xEA, 0x48, 0x28,
+ 0x60, 0x81, 0x78, 0xEB, 0x4A, 0x11, 0x70, 0xC1,
+ 0x78, 0xEA, 0x4A, 0x11, 0x70, 0x00, 0x79, 0xEA,
+ 0x49, 0x08, 0x70, 0xFF, 0xF7, 0x3E, 0xFC, 0xFF,
+ 0xF7, 0x0E, 0xFC, 0x03, 0x20, 0x00, 0x99, 0xF9,
+ 0xF7, 0xDE, 0xF9, 0xFF, 0xF7, 0x29, 0xF8, 0x01,
+ 0x21, 0x20, 0x46, 0x2F, 0x60, 0x03, 0xF0, 0x24,
+ 0xFF, 0xFE, 0xF7, 0x8D, 0xF8, 0xFE, 0xF7, 0x77,
+ 0xFC, 0xFE, 0xF7, 0x41, 0xFE, 0x00, 0x28, 0xFB,
+ 0xD0, 0xDE, 0x48, 0x00, 0x68, 0xFF, 0xF7, 0x95,
+ 0xFB, 0x01, 0x21, 0x20, 0x46, 0x03, 0xF0, 0x7D,
+ 0xFF, 0xFE, 0xF7, 0x56, 0xF9, 0x03, 0x20, 0xFE,
+ 0xF7, 0x68, 0xFD, 0xFE, 0xF7, 0x30, 0xFE, 0x00,
+ 0x28, 0xFB, 0xD0, 0xD7, 0x48, 0x01, 0x68, 0x03,
+ 0x20, 0xFF, 0xF7, 0x31, 0xFA,
+ 0x00, 0x01, 0x03, 0x00, 0x80, 0xCC, 0x4D, 0x69,
+ 0x6A, 0xD4, 0x48, 0x02, 0xE0, 0x49, 0x1E, 0x42,
+ 0x5C, 0x62, 0x54, 0x00, 0x29, 0xFA, 0xDC, 0x28,
+ 0x6A, 0xD1, 0x49, 0x05, 0xE0, 0x40, 0x1E, 0x23,
+ 0x18, 0xFF, 0x33, 0x0A, 0x5C, 0xE1, 0x33, 0x9A,
+ 0x76, 0x00, 0x28, 0xF7, 0xDC, 0x68, 0x6A, 0xF1,
+ 0x09, 0x7F, 0x30, 0xC2, 0x09, 0x20, 0x46, 0x01,
+ 0xF0, 0xB0, 0xF9, 0x30, 0x46, 0xFF, 0x30, 0xFB,
+ 0x30, 0xC1, 0x09, 0x28, 0x6A, 0xC7, 0x4A, 0xB2,
+ 0x18, 0x80, 0x18, 0xC0, 0x09, 0x42, 0x1A, 0x20,
+ 0x46, 0xFF, 0x30, 0x52, 0x1C, 0x81, 0x30, 0x01,
+ 0xF0, 0xA0, 0xF9, 0xFE, 0xBD, 0xF8, 0xB5, 0x05,
+ 0x46, 0xB2, 0x48, 0xC1, 0x6B, 0x01, 0x29, 0x04,
+ 0xD1, 0x00, 0x6C, 0x00, 0x28, 0x01, 0xD0, 0x01,
+ 0x27, 0x00, 0xE0, 0x00, 0x27, 0x28, 0x06, 0x01,
+ 0xD5, 0x00, 0x24, 0x06, 0xE0, 0x38, 0x46, 0x03,
+ 0xF0, 0x5A, 0xFC, 0x04, 0x07,
+ 0x00, 0x01, 0x04, 0x00, 0x80, 0x24, 0x0F, 0x0F,
+ 0x20, 0x44, 0x40, 0xAE, 0x49, 0x2C, 0x43, 0xAC,
+ 0x48, 0x08, 0x60, 0x00, 0x2F, 0x07, 0xD0, 0x03,
+ 0x20, 0xF9, 0xF7, 0x7C, 0xF9, 0xFE, 0xF7, 0x91,
+ 0xFF, 0x00, 0x20, 0xFE, 0xF7, 0xB5, 0xFF, 0xA0,
+ 0x07, 0x03, 0xD5, 0x01, 0x21, 0xA3, 0x48, 0x03,
+ 0xF0, 0x18, 0xFF, 0xE0, 0x07, 0x03, 0xD0, 0x01,
+ 0x21, 0xA0, 0x48, 0x03, 0xF0, 0xA9, 0xFE, 0x9E,
+ 0x48, 0x00, 0x90, 0x80, 0x6A, 0x00, 0x28, 0x05,
+ 0xD0, 0x20, 0x07, 0x03, 0xD5, 0x01, 0x21, 0x9B,
+ 0x48, 0x03, 0xF0, 0xC9, 0xFF, 0x01, 0x21, 0x9A,
+ 0x48, 0xC9, 0x02, 0x45, 0x18, 0x49, 0x10, 0x46,
+ 0x18, 0x00, 0x2F, 0x31, 0xD0, 0x00, 0x98, 0x80,
+ 0x6A, 0x00, 0x28, 0x0D, 0xD0, 0x20, 0x07, 0x0B,
+ 0xD5, 0x94, 0x48, 0x01, 0x21, 0x06, 0x60, 0x91,
+ 0x48, 0x03, 0xF0, 0xB5, 0xFF, 0x91, 0x48, 0x01,
+ 0x21, 0x05, 0x60, 0x8E, 0x48,
+ 0x00, 0x01, 0x05, 0x00, 0x80, 0x03, 0xF0, 0xAF,
+ 0xFF, 0xA0, 0x07, 0x1D, 0xD0, 0x89, 0x4C, 0x40,
+ 0x21, 0x20, 0x8B, 0x08, 0x43, 0x20, 0x83, 0x01,
+ 0x20, 0xFF, 0xF7, 0x05, 0xF8, 0x00, 0x20, 0xFF,
+ 0xF7, 0x13, 0xF8, 0x91, 0x4A, 0x31, 0x46, 0x00,
+ 0x20, 0xFF, 0xF7, 0x27, 0xFF, 0x8F, 0x4A, 0x29,
+ 0x46, 0x01, 0x20, 0xFF, 0xF7, 0x22, 0xFF, 0x00,
+ 0x20, 0xFE, 0xF7, 0xF5, 0xFF, 0x20, 0x8B, 0x40,
+ 0x21, 0x88, 0x43, 0x20, 0x83, 0xFD, 0xF7, 0x80,
+ 0xFF, 0x7D, 0x48, 0x82, 0x78, 0x79, 0x49, 0x1C,
+ 0x31, 0x0A, 0x70, 0xB2, 0x78, 0x4A, 0x70, 0xAA,
+ 0x78, 0x8A, 0x70, 0xC3, 0x78, 0xCA, 0x1C, 0x13,
+ 0x70, 0xF3, 0x78, 0x53, 0x70, 0xEB, 0x78, 0x93,
+ 0x70, 0x04, 0x79, 0x8B, 0x1D, 0x1C, 0x70, 0x34,
+ 0x79, 0x5C, 0x70, 0x2C, 0x79, 0x9C, 0x70, 0x74,
+ 0x4C, 0x09, 0x78, 0x21, 0x70, 0x11, 0x78, 0x73,
+ 0x4A, 0x00, 0x2F, 0x11, 0x70,
+ 0x00, 0x01, 0x06, 0x00, 0x80, 0x72, 0x4A, 0x19,
+ 0x78, 0x11, 0x70, 0x6E, 0x49, 0x08, 0x60, 0x05,
+ 0xD0, 0x00, 0x20, 0xFE, 0xF7, 0x3D, 0xFF, 0x00,
+ 0x20, 0xFE, 0xF7, 0x13, 0xFF, 0xFF, 0xF7, 0x45,
+ 0xFB, 0xFF, 0xF7, 0x15, 0xFB, 0xF8, 0xBD, 0x70,
+ 0x47, 0x70, 0xB5, 0x62, 0x4C, 0x01, 0x26, 0x20,
+ 0x78, 0x00, 0x28, 0x02, 0xD1, 0x26, 0x70, 0xFF,
+ 0xF7, 0xC7, 0xFE, 0x6D, 0x48, 0xFE, 0xF7, 0x8C,
+ 0xFE, 0x00, 0x25, 0x65, 0x63, 0xA5, 0x63, 0xE5,
+ 0x63, 0x03, 0xF0, 0x9B, 0xFB, 0xFD, 0xF7, 0x30,
+ 0xFF, 0xFE, 0xF7, 0x9F, 0xFF, 0xF9, 0xF7, 0x57,
+ 0xFB, 0x03, 0xF0, 0x04, 0xFA, 0x02, 0xF0, 0xCE,
+ 0xFB, 0x02, 0xF0, 0x08, 0xFF, 0x03, 0xF0, 0xF2,
+ 0xF9, 0xF9, 0xF7, 0xE8, 0xF8, 0x53, 0x48, 0x53,
+ 0x49, 0xA1, 0x64, 0xE0, 0x38, 0x60, 0x64, 0x70,
+ 0x39, 0xE1, 0x64, 0x5E, 0x49, 0x21, 0x65, 0xFE,
+ 0xF7, 0x76, 0xFE, 0xA0, 0x6C,
+ 0x00, 0x01, 0x07, 0x00, 0x80, 0xFE, 0xF7, 0x6E,
+ 0xFE, 0x60, 0x6C, 0xFE, 0xF7, 0x75, 0xFE, 0x00,
+ 0x20, 0xFF, 0xF7, 0x24, 0xFF, 0x45, 0x48, 0xA5,
+ 0x73, 0xC0, 0x6B, 0x01, 0x28, 0x11, 0xD1, 0x43,
+ 0x48, 0x40, 0x30, 0x40, 0x8B, 0xE1, 0x78, 0x88,
+ 0x43, 0xC0, 0x07, 0x0A, 0xD1, 0x01, 0xF0, 0xA6,
+ 0xF8, 0xFE, 0xF7, 0xB9, 0xFE, 0x00, 0x28, 0x03,
+ 0xD1, 0xFE, 0xF7, 0xBA, 0xFE, 0x00, 0x28, 0x00,
+ 0xD0, 0xA6, 0x73, 0x25, 0x64, 0xA5, 0x71, 0xE5,
+ 0x71, 0x65, 0x74, 0x65, 0x75, 0x25, 0x83, 0x65,
+ 0x83, 0x39, 0x48, 0x25, 0x71, 0x80, 0x6A, 0x00,
+ 0x28, 0x01, 0xD0, 0x04, 0xF0, 0xD4, 0xF8, 0x26,
+ 0x74, 0x70, 0xBD, 0x10, 0xB5, 0xFD, 0xF7, 0x0C,
+ 0xFF, 0x32, 0x49, 0x00, 0x20, 0x08, 0x71, 0x10,
+ 0xBD, 0xF8, 0xB5, 0x30, 0x4D, 0x00, 0x24, 0x06,
+ 0x46, 0x6C, 0x70, 0x01, 0xF0, 0xEF, 0xFA, 0x07,
+ 0x46, 0x62, 0xB6, 0x28, 0x79,
+ 0x00, 0x01, 0x08, 0x00, 0x80, 0x17, 0x28, 0x06,
+ 0xD2, 0x3B, 0x49, 0x80, 0x00, 0x09, 0x58, 0x30,
+ 0x46, 0x88, 0x47, 0x04, 0x46, 0x04, 0xE0, 0xFD,
+ 0xF7, 0xF3, 0xFE, 0x00, 0x20, 0x28, 0x71, 0x08,
+ 0x24, 0x72, 0xB6, 0xE0, 0x07, 0x05, 0xD0, 0xFE,
+ 0xF7, 0xD6, 0xFC, 0x01, 0x28, 0x01, 0xD1, 0xC0,
+ 0x07, 0x04, 0x43, 0x00, 0x2C, 0xE4, 0xDB, 0xF8,
+ 0xB2, 0x01, 0xF0, 0xD4, 0xFA, 0x1B, 0x48, 0x40,
+ 0x30, 0x00, 0x8B, 0x00, 0x28, 0x02, 0xD1, 0xF9,
+ 0xF7, 0x79, 0xF8, 0x10, 0xE0, 0xFE, 0xF7, 0x6B,
+ 0xFE, 0x00, 0x28, 0x03, 0xD0, 0xEE, 0x62, 0xF9,
+ 0xF7, 0x78, 0xF8, 0x08, 0xE0, 0x13, 0x4A, 0xE9,
+ 0x6A, 0x52, 0x6D, 0x28, 0x46, 0x71, 0x1A, 0x91,
+ 0x42, 0x01, 0xD9, 0xC6, 0x62, 0xEB, 0xE7, 0x69,
+ 0x8B, 0x20, 0x46, 0x08, 0x43, 0xF8, 0xBD, 0xF8,
+ 0xB5, 0x1B, 0x4B, 0x20, 0x4E, 0x20, 0x4C, 0x1B,
+ 0x4D, 0x0D, 0x4A, 0x00, 0x29,
+ 0x00, 0x01, 0x09, 0x00, 0x80, 0x77, 0xD0, 0x01,
+ 0x29, 0x03, 0xD0, 0x02, 0x29, 0x74, 0xD1, 0x00,
+ 0x20, 0x6C, 0xE0, 0x00, 0x28, 0x43, 0xD1, 0x04,
+ 0xE0, 0x31, 0x5C, 0x1D, 0x5C, 0x49, 0x19, 0x31,
+ 0x54, 0x40, 0x1C, 0x51, 0x6A, 0x81, 0x42, 0xF7,
+ 0xD8, 0x00, 0x20, 0x34, 0xE0, 0x78, 0xDC, 0x00,
+ 0x00, 0xC1, 0x01, 0x00, 0x20, 0x30, 0x02, 0x00,
+ 0x20, 0x88, 0xDF, 0x00, 0x00, 0x08, 0x0F, 0x00,
+ 0x20, 0x80, 0xE2, 0x00, 0x00, 0x3C, 0x03, 0x00,
+ 0x20, 0x34, 0x03, 0x00, 0x20, 0x35, 0x03, 0x00,
+ 0x20, 0x36, 0x03, 0x00, 0x20, 0xAC, 0x01, 0x00,
+ 0x20, 0xB0, 0x01, 0x00, 0x20, 0x64, 0x08, 0x00,
+ 0x20, 0x5E, 0x0A, 0x00, 0x20, 0x79, 0x02, 0x00,
+ 0x00, 0x00, 0xF6, 0x00, 0x00, 0x80, 0xFA, 0x00,
+ 0x00, 0x23, 0x83, 0x00, 0x00, 0xA8, 0x11, 0x00,
+ 0x20, 0x1C, 0xCE, 0x00, 0x00, 0x74, 0x05, 0x00,
+ 0x20, 0x6E, 0x07, 0x00, 0x20,
+ 0x00, 0x01, 0x0A, 0x00, 0x80, 0xFF, 0x27, 0x41,
+ 0x00, 0x1E, 0x18, 0xFB, 0x37, 0x65, 0x5A, 0xF7,
+ 0x57, 0xED, 0x19, 0x65, 0x52, 0x40, 0x1C, 0x11,
+ 0x6A, 0x81, 0x42, 0xF3, 0xD8, 0xF8, 0xBD, 0x00,
+ 0x20, 0x06, 0xE0, 0x19, 0x5C, 0x2F, 0x5C, 0xC9,
+ 0x1B, 0x37, 0x5C, 0xC9, 0x19, 0x31, 0x54, 0x40,
+ 0x1C, 0x51, 0x6A, 0x81, 0x42, 0xF5, 0xD8, 0x00,
+ 0x20, 0x0D, 0xE0, 0xFF, 0x21, 0x1E, 0x18, 0xFB,
+ 0x31, 0x71, 0x56, 0xFF, 0x27, 0x2E, 0x18, 0xFB,
+ 0x37, 0xF7, 0x57, 0xCE, 0x1B, 0x41, 0x00, 0x67,
+ 0x5A, 0xF6, 0x19, 0x66, 0x52, 0x40, 0x1C, 0x11,
+ 0x6A, 0x81, 0x42, 0xEE, 0xD8, 0xF8, 0xBD, 0x29,
+ 0x5C, 0x1F, 0x5C, 0xC9, 0x1B, 0x37, 0x5C, 0xC9,
+ 0x19, 0x31, 0x54, 0x40, 0x1C, 0x51, 0x6A, 0x81,
+ 0x42, 0xF5, 0xD8, 0x00, 0x20, 0x0F, 0xE0, 0x12,
+ 0xE0, 0x45, 0xE0, 0xFF, 0x21, 0x2E, 0x18, 0xFB,
+ 0x31, 0x71, 0x56, 0xFF, 0x27,
+ 0x00, 0x01, 0x0B, 0x00, 0x80, 0x1E, 0x18, 0xFB,
+ 0x37, 0xF7, 0x57, 0xCE, 0x1B, 0x41, 0x00, 0x67,
+ 0x5A, 0xF6, 0x19, 0x66, 0x52, 0x40, 0x1C, 0x11,
+ 0x6A, 0x81, 0x42, 0xEE, 0xD8, 0xF8, 0xBD, 0x01,
+ 0x28, 0x18, 0xD1, 0x00, 0x20, 0x04, 0xE0, 0x31,
+ 0x5C, 0x1D, 0x5C, 0x49, 0x1B, 0x31, 0x54, 0x40,
+ 0x1C, 0x51, 0x6A, 0x81, 0x42, 0xF7, 0xD8, 0x00,
+ 0x20, 0x08, 0xE0, 0xFF, 0x27, 0x41, 0x00, 0x1E,
+ 0x18, 0xFB, 0x37, 0x65, 0x5A, 0xF7, 0x57, 0xED,
+ 0x1B, 0x65, 0x52, 0x40, 0x1C, 0x11, 0x6A, 0x81,
+ 0x42, 0xF3, 0xD8, 0xF8, 0xBD, 0x00, 0x20, 0x04,
+ 0xE0, 0x31, 0x5C, 0x2B, 0x5C, 0xC9, 0x1A, 0x31,
+ 0x54, 0x40, 0x1C, 0x51, 0x6A, 0x81, 0x42, 0xF7,
+ 0xD8, 0x00, 0x20, 0x08, 0xE0, 0xFF, 0x27, 0x41,
+ 0x00, 0x2E, 0x18, 0xFB, 0x37, 0x63, 0x5A, 0xF7,
+ 0x57, 0xDB, 0x1B, 0x63, 0x52, 0x40, 0x1C, 0x11,
+ 0x6A, 0x81, 0x42, 0xF3, 0xD8,
+ 0x00, 0x01, 0x0C, 0x00, 0x80, 0xF8, 0xBD, 0xFE,
+ 0x4C, 0x00, 0x20, 0x60, 0x74, 0xFE, 0xF7, 0xC0,
+ 0xFD, 0x21, 0x46, 0x60, 0x7C, 0x1C, 0x31, 0xFB,
+ 0x4A, 0x09, 0x5C, 0x11, 0x70, 0x21, 0x46, 0x1F,
+ 0x31, 0xF9, 0x4A, 0x09, 0x5C, 0x11, 0x70, 0x21,
+ 0x46, 0x22, 0x31, 0xF8, 0x4A, 0x09, 0x5C, 0x11,
+ 0x70, 0xF7, 0x49, 0x80, 0x02, 0x40, 0x18, 0xF7,
+ 0x49, 0x08, 0x60, 0xFF, 0xF7, 0xB6, 0xF9, 0xFF,
+ 0xF7, 0x86, 0xF9, 0xF8, 0xBD, 0x70, 0xB5, 0xEE,
+ 0x4C, 0xF3, 0x4D, 0x21, 0x8B, 0x8A, 0x06, 0x03,
+ 0xD4, 0xCA, 0x06, 0x01, 0xD4, 0xC9, 0x05, 0x46,
+ 0xD5, 0xF0, 0x49, 0x09, 0x78, 0x00, 0x29, 0x42,
+ 0xD1, 0xA1, 0x6A, 0x88, 0x42, 0x3E, 0xD9, 0x69,
+ 0x6D, 0x08, 0x18, 0xA0, 0x62, 0x00, 0x20, 0xFE,
+ 0xF7, 0x68, 0xFD, 0x68, 0x6E, 0xC0, 0xB2, 0xFE,
+ 0xF7, 0x32, 0xFD, 0x00, 0x25, 0x65, 0x75, 0x60,
+ 0x7C, 0x00, 0x28, 0x1B, 0xD0,
+ 0x00, 0x01, 0x0D, 0x00, 0x80, 0x00, 0x20, 0xFE,
+ 0xF7, 0x83, 0xFD, 0x60, 0x7C, 0xA0, 0x74, 0xDC,
+ 0x48, 0x65, 0x74, 0x1C, 0x30, 0xDB, 0x4A, 0x00,
+ 0x78, 0x10, 0x70, 0xD9, 0x48, 0xDA, 0x4A, 0x1F,
+ 0x30, 0x00, 0x78, 0x10, 0x70, 0xD6, 0x48, 0xD9,
+ 0x4A, 0x22, 0x30, 0x00, 0x78, 0x10, 0x70, 0xD9,
+ 0x4A, 0xD7, 0x48, 0x10, 0x60, 0x29, 0x46, 0xA0,
+ 0x7C, 0xFF, 0xF7, 0xDD, 0xFE, 0x00, 0x20, 0xFE,
+ 0xF7, 0xF2, 0xFD, 0x00, 0x20, 0xFE, 0xF7, 0x00,
+ 0xFE, 0x00, 0x20, 0x02, 0xF0, 0x57, 0xFD, 0x00,
+ 0x20, 0xF9, 0xF7, 0x2A, 0xF9, 0x00, 0x20, 0xFA,
+ 0xF7, 0x9A, 0xFE, 0x20, 0x8B, 0xFF, 0x21, 0xF1,
+ 0x31, 0x88, 0x43, 0x20, 0x83, 0x70, 0xBD, 0x69,
+ 0x6D, 0x08, 0x18, 0xA0, 0x62, 0x70, 0xBD, 0x10,
+ 0xB5, 0xFF, 0xF7, 0xA8, 0xFF, 0xC2, 0x49, 0x08,
+ 0x8B, 0x48, 0x83, 0xC7, 0x48, 0x80, 0x69, 0x01,
+ 0x23, 0x01, 0x28, 0x0A, 0xD0,
+ 0x00, 0x01, 0x0E, 0x00, 0x80, 0x88, 0x78, 0xC6,
+ 0x4A, 0x40, 0x06, 0x40, 0x0F, 0x01, 0x28, 0x01,
+ 0xD0, 0x02, 0x28, 0x0C, 0xD1, 0x10, 0x79, 0x01,
+ 0x28, 0x01, 0xD1, 0x0B, 0x71, 0x10, 0xE0, 0x88,
+ 0x79, 0x00, 0x28, 0x01, 0xD0, 0x03, 0x20, 0x00,
+ 0xE0, 0x04, 0x20, 0x08, 0x71, 0x08, 0xE0, 0x10,
+ 0x79, 0x01, 0x28, 0x01, 0xD1, 0x0E, 0x20, 0x00,
+ 0xE0, 0x09, 0x20, 0x08, 0x71, 0x00, 0x20, 0x08,
+ 0x73, 0x01, 0x20, 0xC0, 0x07, 0x10, 0xBD, 0x70,
+ 0xB5, 0x05, 0x46, 0xFD, 0xF7, 0x65, 0xFE, 0xAC,
+ 0x4C, 0xB4, 0x48, 0x60, 0x64, 0xE0, 0x64, 0xFE,
+ 0xF7, 0x8A, 0xFC, 0xAF, 0x48, 0x41, 0x69, 0x03,
+ 0x29, 0x04, 0xD1, 0x03, 0x20, 0xFE, 0xF7, 0x6D,
+ 0xFA, 0x04, 0x20, 0x0A, 0xE0, 0x40, 0x69, 0x01,
+ 0x28, 0x03, 0xD1, 0xFE, 0xF7, 0x66, 0xFA, 0x01,
+ 0x20, 0x03, 0xE0, 0x02, 0x20, 0xFE, 0xF7, 0x61,
+ 0xFA, 0x02, 0x20, 0xE0, 0x73,
+ 0x00, 0x01, 0x0F, 0x00, 0x80, 0x05, 0x20, 0x65,
+ 0x63, 0x20, 0x71, 0x01, 0x20, 0x70, 0xBD, 0xF8,
+ 0xB5, 0x05, 0x46, 0x01, 0x24, 0xFE, 0xF7, 0x1F,
+ 0xFB, 0x01, 0x28, 0x3F, 0xD1, 0xFD, 0xF7, 0x14,
+ 0xFD, 0x97, 0x4E, 0xF0, 0x7B, 0x04, 0x28, 0x02,
+ 0xD1, 0x03, 0x20, 0xF1, 0x6C, 0x05, 0xE0, 0xF1,
+ 0x6C, 0xC0, 0x07, 0x01, 0xD0, 0x01, 0x20, 0x00,
+ 0xE0, 0x02, 0x20, 0xFE, 0xF7, 0x14, 0xFF, 0xFF,
+ 0xF7, 0x19, 0xFA, 0x99, 0x48, 0x04, 0x23, 0x01,
+ 0x68, 0x31, 0x63, 0xB0, 0x78, 0x42, 0x06, 0x57,
+ 0x0F, 0x03, 0x22, 0xD4, 0x07, 0x00, 0x2F, 0x22,
+ 0xD1, 0x8F, 0x48, 0x81, 0x69, 0x01, 0x29, 0x2A,
+ 0xD1, 0x92, 0x49, 0x09, 0x78, 0x01, 0x29, 0x32,
+ 0xD0, 0xB1, 0x79, 0x00, 0x29, 0x2F, 0xD1, 0x71,
+ 0x79, 0x01, 0x29, 0x2C, 0xD0, 0x8E, 0x49, 0x09,
+ 0x78, 0x01, 0x29, 0x1C, 0xD0, 0xB1, 0x6B, 0x80,
+ 0x68, 0x69, 0x1A, 0x81, 0x42,
+ 0x00, 0x01, 0x10, 0x00, 0x80, 0x17, 0xD8, 0x00,
+ 0x21, 0x31, 0x71, 0xF2, 0x79, 0x70, 0x78, 0x08,
+ 0x24, 0x82, 0x42, 0x01, 0xD0, 0xF0, 0x71, 0x0C,
+ 0x24, 0x80, 0x48, 0x01, 0x70, 0x43, 0xE0, 0x77,
+ 0x79, 0x01, 0x2F, 0x06, 0xD0, 0x7C, 0x4F, 0xBF,
+ 0x69, 0x00, 0x2F, 0x06, 0xD1, 0xB0, 0x79, 0x00,
+ 0x28, 0x01, 0xD1, 0x33, 0x71, 0x37, 0xE0, 0x32,
+ 0x71, 0x35, 0xE0, 0xC6, 0x09, 0x0C, 0xD0, 0x7B,
+ 0x4E, 0x36, 0x78, 0x01, 0x2E, 0x03, 0xD0, 0x6E,
+ 0x4E, 0xB6, 0x79, 0x00, 0x2E, 0x04, 0xD0, 0x28,
+ 0x46, 0x00, 0xF0, 0x75, 0xFE, 0x04, 0x46, 0x26,
+ 0xE0, 0x6F, 0x4E, 0x37, 0x69, 0x8F, 0x42, 0x05,
+ 0xD3, 0x67, 0x49, 0xF7, 0x68, 0xC9, 0x6B, 0x69,
+ 0x1A, 0xB9, 0x42, 0x02, 0xD9, 0x64, 0x48, 0x03,
+ 0x71, 0x19, 0xE0, 0x63, 0x49, 0xC0, 0x09, 0x0A,
+ 0xD0, 0x6D, 0x48, 0x00, 0x78, 0x01, 0x28, 0x04,
+ 0xD0, 0x88, 0x6B, 0xB3, 0x68,
+ 0x00, 0x01, 0x11, 0x00, 0x80, 0x28, 0x1A, 0x98,
+ 0x42, 0x01, 0xD9, 0x0A, 0x71, 0x0B, 0xE0, 0x00,
+ 0x22, 0x0A, 0x71, 0xCB, 0x79, 0x48, 0x78, 0x08,
+ 0x24, 0x83, 0x42, 0x01, 0xD0, 0xC8, 0x71, 0x0C,
+ 0x24, 0x5E, 0x48, 0x02, 0x70, 0x8A, 0x71, 0x20,
+ 0x46, 0xF8, 0xBD, 0x10, 0xB5, 0x61, 0x48, 0x42,
+ 0x78, 0x01, 0x78, 0x07, 0x20, 0x00, 0xF0, 0x48,
+ 0xFE, 0xFD, 0xF7, 0xD5, 0xFC, 0x59, 0x48, 0x50,
+ 0x4C, 0xE0, 0x30, 0xA0, 0x64, 0x20, 0x65, 0xFE,
+ 0xF7, 0xCD, 0xFB, 0xE3, 0x7A, 0xA2, 0x7A, 0x61,
+ 0x7A, 0x20, 0x7A, 0xFE, 0xF7, 0xCB, 0xFA, 0x06,
+ 0x20, 0x20, 0x71, 0x01, 0x20, 0x10, 0xBD, 0x70,
+ 0xB5, 0x05, 0x46, 0xFD, 0xF7, 0xC0, 0xFC, 0x4F,
+ 0x48, 0x45, 0x4C, 0xE0, 0x30, 0xA0, 0x64, 0x20,
+ 0x65, 0xFE, 0xF7, 0xB8, 0xFB, 0xFE, 0xF7, 0xA3,
+ 0xF8, 0x07, 0x20, 0xA5, 0x63, 0x20, 0x71, 0x01,
+ 0x20, 0x70, 0xBD, 0x10, 0xB5,
+ 0x00, 0x01, 0x12, 0x00, 0x80, 0x04, 0x46, 0xFD,
+ 0xF7, 0x29, 0xFE, 0x46, 0x48, 0xE0, 0x30, 0xFE,
+ 0xF7, 0xA9, 0xFB, 0xFE, 0xF7, 0x9F, 0xF9, 0x3A,
+ 0x48, 0x08, 0x21, 0xC4, 0x63, 0x01, 0x71, 0x01,
+ 0x20, 0x10, 0xBD, 0xF8, 0xB5, 0x00, 0x26, 0x00,
+ 0xF0, 0xE9, 0xFD, 0xFE, 0xF7, 0x01, 0xFC, 0x34,
+ 0x4D, 0x04, 0x46, 0xA8, 0x7B, 0x01, 0x28, 0x0C,
+ 0xD1, 0xFE, 0xF7, 0xFE, 0xFB, 0x00, 0x28, 0x08,
+ 0xD1, 0x00, 0x2C, 0x06, 0xD1, 0xA8, 0x73, 0xFF,
+ 0xF7, 0x02, 0xF8, 0xFF, 0xF7, 0x2E, 0xF8, 0xFE,
+ 0xF7, 0xE3, 0xFF, 0x28, 0x8B, 0x38, 0x49, 0x30,
+ 0x4F, 0xC2, 0x05, 0x06, 0xD5, 0xFA, 0x6C, 0x3B,
+ 0x6D, 0xD2, 0x1A, 0xA2, 0x42, 0x0E, 0xD9, 0x88,
+ 0x43, 0x28, 0x83, 0x68, 0x7D, 0x01, 0x28, 0x16,
+ 0xD1, 0x38, 0x6C, 0x00, 0x28, 0x13, 0xD1, 0xF8,
+ 0x6C, 0xA0, 0x42, 0x05, 0xD2, 0x28, 0x8B, 0x08,
+ 0x43, 0x28, 0x83, 0x1F, 0xE0,
+ 0x00, 0x01, 0x13, 0x00, 0x80, 0x01, 0x20, 0xF8,
+ 0xBD, 0xFE, 0xF7, 0xD6, 0xFB, 0x80, 0x21, 0x00,
+ 0x28, 0x28, 0x8B, 0x01, 0xD0, 0x08, 0x43, 0x00,
+ 0xE0, 0x88, 0x43, 0x28, 0x83, 0x13, 0xE0, 0xFE,
+ 0xF7, 0xCB, 0xFB, 0x00, 0x28, 0x09, 0xD1, 0xF8,
+ 0x6C, 0xA0, 0x42, 0x06, 0xD3, 0xFE, 0xF7, 0xBB,
+ 0xFB, 0x00, 0x28, 0x08, 0xD0, 0x28, 0x8B, 0xC0,
+ 0x06, 0x05, 0xD4, 0x00, 0x20, 0xE8, 0x74, 0x28,
+ 0x75, 0x01, 0x20, 0xA8, 0x75, 0x01, 0x26, 0x30,
+ 0x46, 0xF8, 0xBD, 0xFE, 0xB5, 0x01, 0x26, 0xFE,
+ 0xF7, 0x02, 0xFA, 0x01, 0x28, 0x72, 0xD1, 0xFD,
+ 0xF7, 0xF7, 0xFB, 0x0F, 0x48, 0xC0, 0x6B, 0xF6,
+ 0x07, 0x07, 0x4C, 0x01, 0x28, 0x2A, 0xD1, 0x0C,
+ 0x48, 0x40, 0x30, 0x40, 0x8B, 0xE1, 0x78, 0x88,
+ 0x43, 0xC0, 0x07, 0x23, 0xD1, 0xFF, 0xF7, 0x95,
+ 0xFF, 0x01, 0x28, 0x1F, 0xD1, 0x15, 0x20, 0x3E,
+ 0xE0, 0x30, 0x02, 0x00, 0x20,
+ 0x00, 0x01, 0x14, 0x00, 0x80, 0x34, 0x03, 0x00,
+ 0x20, 0x35, 0x03, 0x00, 0x20, 0x36, 0x03, 0x00,
+ 0x20, 0x80, 0xE2, 0x00, 0x00, 0x3C, 0x03, 0x00,
+ 0x20, 0x78, 0xDC, 0x00, 0x00, 0x92, 0x00, 0x00,
+ 0x20, 0x40, 0xDE, 0x00, 0x00, 0x28, 0x0E, 0x00,
+ 0x20, 0x08, 0x02, 0x00, 0x20, 0xC3, 0x01, 0x00,
+ 0x20, 0xC2, 0x01, 0x00, 0x20, 0x9C, 0x00, 0x00,
+ 0x20, 0x00, 0x01, 0x00, 0x00, 0x20, 0x8B, 0x60,
+ 0x83, 0x22, 0x6D, 0x00, 0x92, 0xE3, 0x7A, 0xA2,
+ 0x7A, 0x61, 0x7A, 0x20, 0x7A, 0xFE, 0xF7, 0x2A,
+ 0xFF, 0xFF, 0xF7, 0xE6, 0xF9, 0xE2, 0x7A, 0x00,
+ 0x92, 0xA3, 0x7A, 0x62, 0x7A, 0x21, 0x7A, 0xFD,
+ 0x48, 0x01, 0x90, 0xFA, 0xF7, 0x1A, 0xFB, 0xFC,
+ 0x4F, 0x38, 0x78, 0x01, 0x28, 0x06, 0xD8, 0x00,
+ 0x25, 0x01, 0x28, 0x06, 0xD1, 0xF9, 0x48, 0xC0,
+ 0x7A, 0xC0, 0x06, 0x04, 0xD5, 0x03, 0x20, 0x20,
+ 0x71, 0x1C, 0xE0, 0x00, 0x28,
+ 0x00, 0x01, 0x15, 0x00, 0x80, 0x00, 0xD0, 0x65,
+ 0x70, 0x01, 0x98, 0x02, 0xF0, 0x27, 0xFA, 0x02,
+ 0xF0, 0x97, 0xFB, 0x38, 0x78, 0x00, 0x28, 0x0B,
+ 0xD1, 0xA0, 0x79, 0x00, 0x28, 0x08, 0xD0, 0xA0,
+ 0x78, 0x40, 0x06, 0x40, 0x0F, 0x01, 0x28, 0x01,
+ 0xD0, 0x02, 0x28, 0x01, 0xD1, 0xFE, 0xF7, 0x93,
+ 0xFF, 0x60, 0x78, 0xE0, 0x71, 0x38, 0x78, 0xA0,
+ 0x71, 0x0C, 0x26, 0x25, 0x71, 0x30, 0x46, 0xFE,
+ 0xBD, 0xF8, 0xB5, 0xE7, 0x4D, 0x00, 0x21, 0x2A,
+ 0x7C, 0xE6, 0x4E, 0x0C, 0x46, 0x01, 0x2A, 0x08,
+ 0xD0, 0x2A, 0x6C, 0x33, 0x6A, 0x82, 0x1A, 0x9A,
+ 0x42, 0x70, 0xD9, 0xE3, 0x4A, 0x12, 0x78, 0x00,
+ 0x2A, 0x6C, 0xD1, 0x28, 0x64, 0x00, 0x20, 0x28,
+ 0x74, 0xE0, 0x4B, 0x09, 0xE0, 0xE0, 0x4A, 0xB7,
+ 0x6A, 0x12, 0x56, 0xBA, 0x42, 0x02, 0xDC, 0xF7,
+ 0x6A, 0xBA, 0x42, 0x00, 0xDA, 0x49, 0x1C, 0x40,
+ 0x1C, 0x5A, 0x6A, 0x82, 0x42,
+ 0x00, 0x01, 0x16, 0x00, 0x80, 0xF2, 0xD8, 0x00,
+ 0x20, 0x0A, 0xE0, 0xDA, 0x4A, 0x47, 0x00, 0xD2,
+ 0x5F, 0x77, 0x6B, 0xBA, 0x42, 0x02, 0xDC, 0xB7,
+ 0x6B, 0xBA, 0x42, 0x00, 0xDA, 0x64, 0x1C, 0x40,
+ 0x1C, 0x1A, 0x6A, 0x82, 0x42, 0xF1, 0xD8, 0xCF,
+ 0x48, 0x40, 0x6A, 0xCD, 0x4E, 0x1F, 0x36, 0x88,
+ 0x42, 0x5D, 0xD2, 0xFD, 0xF7, 0x98, 0xFB, 0xCB,
+ 0x49, 0xC8, 0x6B, 0x01, 0x28, 0x3F, 0xD1, 0x08,
+ 0x46, 0x40, 0x30, 0x40, 0x8B, 0xEA, 0x78, 0x90,
+ 0x43, 0xC0, 0x07, 0x38, 0xD1, 0x08, 0x6C, 0x00,
+ 0x28, 0x35, 0xD0, 0x03, 0x20, 0xF8, 0xF7, 0xDE,
+ 0xFC, 0xFE, 0xF7, 0xF3, 0xFA, 0x00, 0x27, 0x79,
+ 0x1E, 0x03, 0x20, 0xF8, 0xF7, 0xC8, 0xFC, 0xFE,
+ 0xF7, 0x13, 0xFB, 0x03, 0xF0, 0xE0, 0xFB, 0xBC,
+ 0x49, 0x1C, 0x31, 0xC8, 0x55, 0x03, 0xF0, 0xFB,
+ 0xFB, 0xF0, 0x55, 0x03, 0xF0, 0x14, 0xFC, 0xB8,
+ 0x49, 0x22, 0x31, 0xC8, 0x55,
+ 0x00, 0x01, 0x17, 0x00, 0x80, 0x7F, 0x1C, 0x03,
+ 0x2F, 0xE9, 0xD3, 0x28, 0x8B, 0x40, 0x06, 0x07,
+ 0xD5, 0x69, 0x7C, 0x03, 0x20, 0x49, 0x1E, 0xF8,
+ 0xF7, 0xAE, 0xFC, 0xFE, 0xF7, 0xF9, 0xFA, 0x1E,
+ 0xE0, 0x00, 0x20, 0xFE, 0xF7, 0xF5, 0xFA, 0x28,
+ 0x8B, 0x80, 0x06, 0x03, 0xD5, 0x02, 0x20, 0xF8,
+ 0xF7, 0xB1, 0xFC, 0x00, 0xE0, 0x00, 0x20, 0xFE,
+ 0xF7, 0xC4, 0xFA, 0x10, 0xE0, 0x66, 0xE0, 0x03,
+ 0xF0, 0xB6, 0xFB, 0xA7, 0x49, 0x6A, 0x7C, 0x1C,
+ 0x31, 0x88, 0x54, 0x03, 0xF0, 0xD0, 0xFB, 0x69,
+ 0x7C, 0x70, 0x54, 0x03, 0xF0, 0xE8, 0xFB, 0xA2,
+ 0x49, 0x6A, 0x7C, 0x22, 0x31, 0x88, 0x54, 0xA0,
+ 0x48, 0x69, 0x7C, 0x1C, 0x30, 0x40, 0x5C, 0xA4,
+ 0x49, 0x08, 0x70, 0xFE, 0xF7, 0xDE, 0xFE, 0x9D,
+ 0x48, 0x01, 0x6B, 0xA1, 0x42, 0x4A, 0xD2, 0xC1,
+ 0x6B, 0x00, 0x29, 0x32, 0xD0, 0x00, 0x6C, 0x00,
+ 0x28, 0x2F, 0xD0, 0x03, 0x20,
+ 0x00, 0x01, 0x18, 0x00, 0x80, 0xF8, 0xF7, 0x86,
+ 0xFC, 0xFE, 0xF7, 0x9B, 0xFA, 0x94, 0x4F, 0x00,
+ 0x24, 0x22, 0x37, 0x61, 0x1E, 0x03, 0x20, 0xF8,
+ 0xF7, 0x6E, 0xFC, 0xFE, 0xF7, 0xB9, 0xFA, 0x03,
+ 0xF0, 0xA6, 0xFB, 0x30, 0x55, 0x03, 0xF0, 0xBF,
+ 0xFB, 0x38, 0x55, 0x64, 0x1C, 0x03, 0x2C, 0xF0,
+ 0xD3, 0x28, 0x8B, 0x40, 0x06, 0x07, 0xD5, 0x69,
+ 0x7C, 0x03, 0x20, 0x49, 0x1E, 0xF8, 0xF7, 0x5B,
+ 0xFC, 0xFE, 0xF7, 0xA6, 0xFA, 0x17, 0xE0, 0x00,
+ 0x20, 0xFE, 0xF7, 0xA2, 0xFA, 0x28, 0x8B, 0x80,
+ 0x06, 0x03, 0xD5, 0x02, 0x20, 0xF8, 0xF7, 0x5E,
+ 0xFC, 0x00, 0xE0, 0x00, 0x20, 0xFE, 0xF7, 0x71,
+ 0xFA, 0x09, 0xE0, 0x03, 0xF0, 0x84, 0xFB, 0x69,
+ 0x7C, 0x70, 0x54, 0x03, 0xF0, 0x9C, 0xFB, 0x7C,
+ 0x49, 0x6A, 0x7C, 0x22, 0x31, 0x88, 0x54, 0x68,
+ 0x7C, 0x80, 0x4A, 0x31, 0x5C, 0x11, 0x70, 0x78,
+ 0x49, 0x22, 0x31, 0x08, 0x5C,
+ 0x00, 0x01, 0x19, 0x00, 0x80, 0x7E, 0x49, 0x08,
+ 0x70, 0xFE, 0xF7, 0x61, 0xFE, 0xF8, 0xBD, 0xF1,
+ 0xB5, 0x82, 0xB0, 0x01, 0x25, 0xFE, 0xF7, 0x9F,
+ 0xF8, 0x01, 0x28, 0x5C, 0xD1, 0xFD, 0xF7, 0x94,
+ 0xFA, 0x70, 0x4E, 0xF0, 0x6B, 0xED, 0x07, 0x6E,
+ 0x4C, 0x01, 0x28, 0x0D, 0xD1, 0x30, 0x46, 0x40,
+ 0x30, 0x40, 0x8B, 0xE1, 0x78, 0x88, 0x43, 0xC0,
+ 0x07, 0x06, 0xD1, 0xFF, 0xF7, 0x32, 0xFE, 0x01,
+ 0x28, 0x02, 0xD1, 0x15, 0x20, 0x20, 0x71, 0x46,
+ 0xE0, 0x20, 0x8B, 0x60, 0x83, 0x20, 0x6D, 0xFE,
+ 0xF7, 0xDC, 0xFD, 0xFF, 0xF7, 0xA5, 0xF8, 0x5F,
+ 0x48, 0x01, 0x90, 0xFA, 0xF7, 0x89, 0xFB, 0x5E,
+ 0x4F, 0x00, 0x25, 0x38, 0x78, 0x00, 0x28, 0x00,
+ 0xD0, 0x65, 0x70, 0x5F, 0x48, 0x00, 0x78, 0x00,
+ 0x28, 0x03, 0xD0, 0x60, 0x78, 0x80, 0x21, 0x08,
+ 0x43, 0x60, 0x70, 0x01, 0x98, 0x02, 0xF0, 0xEE,
+ 0xF8, 0x02, 0xF0, 0x5E, 0xFA,
+ 0x00, 0x01, 0x1A, 0x00, 0x80, 0x60, 0x78, 0xE0,
+ 0x71, 0x38, 0x78, 0x00, 0x28, 0x0E, 0xD1, 0x25,
+ 0x71, 0xA0, 0x79, 0x0C, 0x25, 0x00, 0x28, 0x14,
+ 0xD0, 0xA0, 0x78, 0x40, 0x06, 0x40, 0x0F, 0x01,
+ 0x28, 0x01, 0xD0, 0x02, 0x28, 0x0D, 0xD1, 0xFE,
+ 0xF7, 0x56, 0xFE, 0x0A, 0xE0, 0x55, 0x48, 0x00,
+ 0x79, 0x01, 0x28, 0x01, 0xD1, 0x0E, 0x20, 0x00,
+ 0xE0, 0x09, 0x20, 0x20, 0x71, 0x52, 0x4D, 0x01,
+ 0x20, 0x20, 0x73, 0x38, 0x78, 0xA0, 0x71, 0xF0,
+ 0x69, 0x01, 0x28, 0x04, 0xD1, 0x4F, 0x48, 0x20,
+ 0x65, 0x02, 0x98, 0xFF, 0xF7, 0xB5, 0xFE, 0x28,
+ 0x46, 0xFE, 0xBD, 0xF8, 0xB5, 0x07, 0x46, 0x01,
+ 0x26, 0xFE, 0xF7, 0x39, 0xF8, 0x01, 0x28, 0x51,
+ 0xD1, 0xFD, 0xF7, 0x2E, 0xFA, 0x47, 0x48, 0xFE,
+ 0xF7, 0x39, 0xFC, 0x44, 0x48, 0x00, 0x79, 0x3B,
+ 0x4E, 0x00, 0x25, 0x39, 0x4C, 0x01, 0x28, 0x05,
+ 0xD1, 0x30, 0x69, 0x21, 0x6B,
+ 0x00, 0x01, 0x1B, 0x00, 0x80, 0x88, 0x42, 0x01,
+ 0xD2, 0x41, 0x48, 0x05, 0x70, 0xFE, 0xF7, 0x31,
+ 0xFF, 0xA0, 0x78, 0x40, 0x06, 0x40, 0x0F, 0x01,
+ 0x28, 0x01, 0xD1, 0x20, 0x20, 0x00, 0xE0, 0x30,
+ 0x20, 0x02, 0xF0, 0xE1, 0xFC, 0x03, 0x21, 0x21,
+ 0x28, 0x01, 0xD0, 0x31, 0x28, 0x12, 0xD1, 0x01,
+ 0x22, 0x2A, 0x4B, 0x21, 0x28, 0xDA, 0x72, 0x01,
+ 0xD1, 0x20, 0x20, 0x00, 0xE0, 0x40, 0x20, 0x60,
+ 0x70, 0xE0, 0x71, 0xA0, 0x78, 0x0C, 0x26, 0xC0,
+ 0x09, 0x1F, 0xD0, 0x60, 0x79, 0x01, 0x28, 0x1C,
+ 0xD1, 0x21, 0x71, 0x1B, 0xE0, 0xA2, 0x78, 0xD2,
+ 0x09, 0x10, 0xD0, 0x01, 0x28, 0x0B, 0xD0, 0x60,
+ 0x79, 0x01, 0x28, 0x08, 0xD0, 0x2B, 0x48, 0x00,
+ 0x78, 0x01, 0x28, 0x04, 0xD0, 0xA0, 0x6B, 0xB2,
+ 0x68, 0x38, 0x1A, 0x90, 0x42, 0x02, 0xD9, 0x01,
+ 0x26, 0xF6, 0x07, 0xE9, 0xE7, 0xE1, 0x79, 0x60,
+ 0x78, 0x08, 0x26, 0x81, 0x42,
+ 0x00, 0x01, 0x1C, 0x00, 0x80, 0x01, 0xD0, 0x0C,
+ 0x26, 0xE0, 0x71, 0x25, 0x71, 0x30, 0x46, 0xF8,
+ 0xBD, 0x70, 0xB5, 0x05, 0x46, 0x13, 0x48, 0x80,
+ 0x69, 0x11, 0x4C, 0x01, 0x28, 0x05, 0xD1, 0x1B,
+ 0x48, 0xE0, 0x38, 0x60, 0x64, 0xE0, 0x64, 0xFE,
+ 0xF7, 0x22, 0xF9, 0x18, 0x48, 0xA0, 0x64, 0x09,
+ 0x48, 0x20, 0x65, 0xFD, 0xF7, 0x18, 0xFA, 0xA0,
+ 0x6C, 0xFE, 0xF7, 0x14, 0xF9, 0xFD, 0xF7, 0xFF,
+ 0xFD, 0x0A, 0x20, 0xA5, 0x63, 0x20, 0x71, 0x21,
+ 0x7B, 0x05, 0x20, 0x00, 0x29, 0x00, 0xD1, 0x01,
+ 0x20, 0x70, 0xBD, 0x00, 0x00, 0xA8, 0x11, 0x00,
+ 0x20, 0x92, 0x00, 0x00, 0x20, 0x4C, 0x03, 0x00,
+ 0x20, 0x30, 0x02, 0x00, 0x20, 0x78, 0xDC, 0x00,
+ 0x00, 0x93, 0x00, 0x00, 0x20, 0x88, 0xDF, 0x00,
+ 0x00, 0x74, 0x05, 0x00, 0x20, 0x6E, 0x07, 0x00,
+ 0x20, 0x34, 0x03, 0x00, 0x20, 0x35, 0x03, 0x00,
+ 0x20, 0x36, 0x03, 0x00, 0x20,
+ 0x00, 0x01, 0x1D, 0x00, 0x80, 0x40, 0xDE, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x80, 0x08, 0x0F, 0x00,
+ 0x20, 0x2C, 0x02, 0x00, 0x20, 0xC2, 0x01, 0x00,
+ 0x20, 0x10, 0xB5, 0xFD, 0xF7, 0x9C, 0xFF, 0x01,
+ 0x28, 0x19, 0xD1, 0xFD, 0xF7, 0x91, 0xF9, 0xF8,
+ 0x48, 0xC0, 0x6B, 0xF8, 0x4C, 0x01, 0x28, 0x0E,
+ 0xD1, 0xF5, 0x48, 0x40, 0x30, 0x40, 0x8B, 0xE1,
+ 0x78, 0x88, 0x43, 0xC0, 0x07, 0x07, 0xD1, 0xFF,
+ 0xF7, 0x30, 0xFD, 0x01, 0x28, 0x03, 0xD1, 0x15,
+ 0x20, 0x20, 0x71, 0xC0, 0x07, 0x10, 0xBD, 0x0B,
+ 0x20, 0x20, 0x71, 0x00, 0x20, 0x10, 0xBD, 0x01,
+ 0x20, 0x10, 0xBD, 0x10, 0xB5, 0xFD, 0xF7, 0xC3,
+ 0xF9, 0xEA, 0x48, 0x80, 0x6C, 0xFE, 0xF7, 0xBE,
+ 0xF8, 0xFD, 0xF7, 0xA9, 0xFD, 0x10, 0xBD, 0x70,
+ 0xB5, 0xE6, 0x4D, 0x04, 0x46, 0xA9, 0x6C, 0x28,
+ 0x6D, 0x29, 0x65, 0xA8, 0x64, 0xFE, 0xF7, 0xB2,
+ 0xF8, 0xE1, 0x4E, 0xB0, 0x69,
+ 0x00, 0x01, 0x1E, 0x00, 0x80, 0x01, 0x28, 0x0F,
+ 0xD1, 0x68, 0x6B, 0x71, 0x68, 0x20, 0x1A, 0x88,
+ 0x42, 0x0A, 0xD9, 0xDF, 0x48, 0xFE, 0xF7, 0xA0,
+ 0xF8, 0xFD, 0xF7, 0x7E, 0xFA, 0x70, 0x69, 0xFD,
+ 0xF7, 0x90, 0xFE, 0x16, 0x20, 0x6C, 0x63, 0x05,
+ 0xE0, 0xFD, 0xF7, 0x9D, 0xF9, 0xFD, 0xF7, 0x87,
+ 0xFD, 0x0C, 0x20, 0xAC, 0x63, 0x28, 0x71, 0x01,
+ 0x20, 0xC0, 0x07, 0x89, 0xE7, 0xF1, 0xB5, 0xD3,
+ 0x4C, 0x20, 0x6D, 0xFE, 0xF7, 0xA2, 0xFC, 0xFE,
+ 0xF7, 0x6B, 0xFF, 0x20, 0x6D, 0xFA, 0xF7, 0x50,
+ 0xFA, 0xD0, 0x4D, 0xD1, 0x49, 0x28, 0x78, 0x08,
+ 0x70, 0xD0, 0x49, 0x00, 0x27, 0x09, 0x78, 0x03,
+ 0x29, 0x01, 0xD1, 0x2F, 0x70, 0x02, 0xE0, 0x00,
+ 0x28, 0x00, 0xD0, 0x67, 0x70, 0xCC, 0x48, 0x00,
+ 0x78, 0x00, 0x28, 0x03, 0xD0, 0x60, 0x78, 0x80,
+ 0x21, 0x08, 0x43, 0x60, 0x70, 0x20, 0x6D, 0x01,
+ 0xF0, 0xAD, 0xFF, 0x02, 0xF0,
+ 0x00, 0x01, 0x1F, 0x00, 0x80, 0x1D, 0xF9, 0x60,
+ 0x78, 0xE0, 0x71, 0xBF, 0x48, 0x04, 0x26, 0x80,
+ 0x69, 0x0B, 0x21, 0x01, 0x28, 0x28, 0x78, 0x03,
+ 0xD1, 0x00, 0x28, 0x0E, 0xD1, 0x27, 0x71, 0x0D,
+ 0xE0, 0x00, 0x28, 0x0A, 0xD1, 0xA0, 0x78, 0x40,
+ 0x06, 0x40, 0x0F, 0x01, 0x28, 0x01, 0xD0, 0x02,
+ 0x28, 0x03, 0xD1, 0x27, 0x71, 0xFE, 0xF7, 0x0F,
+ 0xFD, 0x00, 0xE0, 0x21, 0x71, 0x28, 0x78, 0xA0,
+ 0x71, 0x20, 0x8B, 0x60, 0x83, 0xFD, 0xF7, 0x07,
+ 0xFF, 0x01, 0x25, 0x01, 0x28, 0x1F, 0xD1, 0xFD,
+ 0xF7, 0xFB, 0xF8, 0xAD, 0x4F, 0xF8, 0x6B, 0x01,
+ 0x28, 0x0F, 0xD1, 0x38, 0x46, 0x40, 0x30, 0x40,
+ 0x8B, 0xE1, 0x78, 0x88, 0x43, 0xC0, 0x07, 0x08,
+ 0xD1, 0xFF, 0xF7, 0x9B, 0xFC, 0x01, 0x28, 0x04,
+ 0xD1, 0x15, 0x20, 0x25, 0x73, 0x20, 0x71, 0xC6,
+ 0x07, 0x11, 0xE0, 0x00, 0x98, 0xFF, 0xF7, 0x22,
+ 0xFB, 0xF8, 0x69, 0x01, 0x28,
+ 0x00, 0x01, 0x20, 0x00, 0x80, 0x0B, 0xD1, 0x00,
+ 0x98, 0xFF, 0xF7, 0x5A, 0xFD, 0x07, 0xE0, 0x20,
+ 0x79, 0x05, 0x26, 0x00, 0x28, 0x00, 0xD0, 0x00,
+ 0x25, 0x65, 0x73, 0x0D, 0x20, 0x20, 0x71, 0x30,
+ 0x46, 0xF8, 0xBD, 0x70, 0xB5, 0x06, 0x46, 0xFD,
+ 0xF7, 0xD6, 0xFE, 0x01, 0x28, 0x29, 0xD1, 0xFD,
+ 0xF7, 0xCB, 0xF8, 0x95, 0x4D, 0xE8, 0x6B, 0x95,
+ 0x4C, 0x01, 0x28, 0x0E, 0xD1, 0x28, 0x46, 0x40,
+ 0x30, 0x40, 0x8B, 0xE1, 0x78, 0x88, 0x43, 0xC0,
+ 0x07, 0x07, 0xD1, 0xFF, 0xF7, 0x6A, 0xFC, 0x01,
+ 0x28, 0x03, 0xD1, 0x15, 0x20, 0x20, 0x71, 0xC0,
+ 0x07, 0xFA, 0xE6, 0x30, 0x46, 0xFF, 0xF7, 0xF2,
+ 0xFA, 0xE8, 0x69, 0x01, 0x28, 0x02, 0xD1, 0x30,
+ 0x46, 0xFF, 0xF7, 0x2A, 0xFD, 0x60, 0x7B, 0x01,
+ 0x28, 0x03, 0xD1, 0x00, 0x20, 0x20, 0x71, 0x08,
+ 0x20, 0xEA, 0xE6, 0x0B, 0x20, 0x20, 0x71, 0x00,
+ 0x20, 0xE6, 0xE6, 0x01, 0x20,
+ 0x00, 0x01, 0x21, 0x00, 0x80, 0xE4, 0xE6, 0x70,
+ 0xB5, 0x05, 0x46, 0x80, 0x4C, 0x85, 0x48, 0x60,
+ 0x64, 0x70, 0x30, 0xE0, 0x64, 0x70, 0x30, 0xA0,
+ 0x64, 0x83, 0x48, 0x20, 0x65, 0x7C, 0x48, 0xFD,
+ 0xF7, 0xDB, 0xFF, 0xFD, 0xF7, 0xB9, 0xF9, 0x60,
+ 0x6C, 0xFD, 0xF7, 0xE1, 0xFF, 0x76, 0x48, 0x41,
+ 0x69, 0x03, 0x29, 0x04, 0xD1, 0x03, 0x20, 0xFD,
+ 0xF7, 0xC4, 0xFD, 0x04, 0x20, 0x0A, 0xE0, 0x40,
+ 0x69, 0x01, 0x28, 0x03, 0xD1, 0xFD, 0xF7, 0xBD,
+ 0xFD, 0x01, 0x20, 0x03, 0xE0, 0x02, 0x20, 0xFD,
+ 0xF7, 0xB8, 0xFD, 0x02, 0x20, 0xE0, 0x73, 0x0F,
+ 0x20, 0x65, 0x63, 0x20, 0x71, 0x21, 0x7B, 0x05,
+ 0x20, 0x00, 0x29, 0x00, 0xD1, 0x01, 0x20, 0xB3,
+ 0xE6, 0x10, 0xB5, 0xFD, 0xF7, 0x74, 0xFE, 0x01,
+ 0x28, 0x1C, 0xD1, 0xFD, 0xF7, 0x69, 0xF8, 0x64,
+ 0x48, 0xC0, 0x6B, 0x64, 0x4C, 0x01, 0x28, 0x11,
+ 0xD1, 0x61, 0x48, 0x40, 0x30,
+ 0x00, 0x01, 0x22, 0x00, 0x80, 0x40, 0x8B, 0xE1,
+ 0x78, 0x88, 0x43, 0xC0, 0x07, 0x0A, 0xD1, 0xFF,
+ 0xF7, 0x08, 0xFC, 0x01, 0x28, 0x06, 0xD1, 0x65,
+ 0x48, 0xFD, 0xF7, 0x9E, 0xFF, 0x15, 0x20, 0x20,
+ 0x71, 0xC0, 0x07, 0x10, 0xBD, 0x10, 0x20, 0x20,
+ 0x71, 0x00, 0x20, 0x10, 0xBD, 0x01, 0x20, 0x10,
+ 0xBD, 0x70, 0xB5, 0x56, 0x4C, 0x05, 0x46, 0x61,
+ 0x6C, 0xE0, 0x6C, 0xE1, 0x64, 0x60, 0x64, 0xA1,
+ 0x6C, 0x20, 0x6D, 0x21, 0x65, 0xA0, 0x64, 0xFD,
+ 0xF7, 0x67, 0xF9, 0x60, 0x6C, 0xFD, 0xF7, 0x8F,
+ 0xFF, 0x4D, 0x48, 0x41, 0x69, 0x03, 0x29, 0x04,
+ 0xD1, 0x03, 0x20, 0xFD, 0xF7, 0x72, 0xFD, 0x04,
+ 0x20, 0x0A, 0xE0, 0x40, 0x69, 0x01, 0x28, 0x03,
+ 0xD1, 0xFD, 0xF7, 0x6B, 0xFD, 0x01, 0x20, 0x03,
+ 0xE0, 0x02, 0x20, 0xFD, 0xF7, 0x66, 0xFD, 0x02,
+ 0x20, 0xE0, 0x73, 0x11, 0x20, 0x65, 0x63, 0x20,
+ 0x71, 0xC0, 0x07, 0x65, 0xE6,
+ 0x00, 0x01, 0x23, 0x00, 0x80, 0xF1, 0xB5, 0x41,
+ 0x4C, 0xE0, 0x7B, 0x21, 0x46, 0xC9, 0x6C, 0x04,
+ 0x28, 0x01, 0xD1, 0x03, 0x20, 0x04, 0xE0, 0xC0,
+ 0x07, 0x01, 0xD0, 0x01, 0x20, 0x00, 0xE0, 0x02,
+ 0x20, 0xFE, 0xF7, 0x21, 0xFA, 0xFE, 0xF7, 0x26,
+ 0xFD, 0x20, 0x6D, 0xFE, 0xF7, 0x6E, 0xFB, 0xFE,
+ 0xF7, 0x37, 0xFE, 0x20, 0x6D, 0xFA, 0xF7, 0x1C,
+ 0xF9, 0x36, 0x4D, 0x37, 0x49, 0x28, 0x78, 0x08,
+ 0x70, 0x36, 0x49, 0x00, 0x27, 0x09, 0x78, 0x03,
+ 0x29, 0x01, 0xD1, 0x2F, 0x70, 0x02, 0xE0, 0x00,
+ 0x28, 0x00, 0xD0, 0x67, 0x70, 0x32, 0x48, 0x00,
+ 0x78, 0x00, 0x28, 0x03, 0xD0, 0x60, 0x78, 0x80,
+ 0x21, 0x08, 0x43, 0x60, 0x70, 0x20, 0x6D, 0x01,
+ 0xF0, 0x79, 0xFE, 0x01, 0xF0, 0xE9, 0xFF, 0x60,
+ 0x78, 0xE0, 0x71, 0x25, 0x48, 0x04, 0x26, 0x80,
+ 0x69, 0x10, 0x21, 0x01, 0x28, 0x28, 0x78, 0x03,
+ 0xD1, 0x00, 0x28, 0x0E, 0xD1,
+ 0x00, 0x01, 0x24, 0x00, 0x80, 0x27, 0x71, 0x0D,
+ 0xE0, 0x00, 0x28, 0x0A, 0xD1, 0xA0, 0x78, 0x40,
+ 0x06, 0x40, 0x0F, 0x01, 0x28, 0x01, 0xD0, 0x02,
+ 0x28, 0x03, 0xD1, 0x27, 0x71, 0xFE, 0xF7, 0xDB,
+ 0xFB, 0x00, 0xE0, 0x21, 0x71, 0x28, 0x78, 0xA0,
+ 0x71, 0x20, 0x8B, 0x60, 0x83, 0xFD, 0xF7, 0xD3,
+ 0xFD, 0x01, 0x25, 0x01, 0x28, 0x3C, 0xD1, 0xFC,
+ 0xF7, 0xC7, 0xFF, 0x13, 0x4F, 0xF8, 0x6B, 0x01,
+ 0x28, 0x12, 0xD1, 0x38, 0x46, 0x40, 0x30, 0x40,
+ 0x8B, 0xE1, 0x78, 0x88, 0x43, 0xC0, 0x07, 0x0B,
+ 0xD1, 0xFF, 0xF7, 0x67, 0xFB, 0x01, 0x28, 0x07,
+ 0xD1, 0x14, 0x48, 0xFD, 0xF7, 0xFD, 0xFE, 0x15,
+ 0x20, 0x25, 0x73, 0x20, 0x71, 0xC6, 0x07, 0x2B,
+ 0xE0, 0x00, 0x98, 0xFF, 0xF7, 0xEB, 0xF9, 0x20,
+ 0x79, 0x00, 0x28, 0x02, 0xD1, 0x0D, 0x48, 0xFD,
+ 0xF7, 0xEF, 0xFE, 0xF8, 0x69, 0x01, 0x28, 0x1F,
+ 0xD1, 0x00, 0x98, 0xFF, 0xF7,
+ 0x00, 0x01, 0x25, 0x00, 0x80, 0x1D, 0xFC, 0x1B,
+ 0xE0, 0x78, 0xDC, 0x00, 0x00, 0x30, 0x02, 0x00,
+ 0x20, 0xD7, 0x8E, 0x00, 0x00, 0x92, 0x00, 0x00,
+ 0x20, 0xD1, 0x00, 0x00, 0x20, 0xDA, 0x00, 0x00,
+ 0x20, 0x93, 0x00, 0x00, 0x20, 0x28, 0x0E, 0x00,
+ 0x20, 0xA8, 0x11, 0x00, 0x20, 0x23, 0x83, 0x00,
+ 0x00, 0x20, 0x79, 0x05, 0x26, 0x00, 0x28, 0x00,
+ 0xD0, 0x00, 0x25, 0x65, 0x73, 0x12, 0x20, 0x20,
+ 0x71, 0x30, 0x46, 0xF8, 0xBD, 0x70, 0xB5, 0x06,
+ 0x46, 0xFD, 0xF7, 0x85, 0xFD, 0x01, 0x28, 0x2F,
+ 0xD1, 0xFC, 0xF7, 0x7A, 0xFF, 0xAF, 0x4D, 0xE8,
+ 0x6B, 0xAF, 0x4C, 0x01, 0x28, 0x11, 0xD1, 0x28,
+ 0x46, 0x40, 0x30, 0x40, 0x8B, 0xE1, 0x78, 0x88,
+ 0x43, 0xC0, 0x07, 0x0A, 0xD1, 0xFF, 0xF7, 0x19,
+ 0xFB, 0x01, 0x28, 0x06, 0xD1, 0xA9, 0x48, 0xFD,
+ 0xF7, 0xAF, 0xFE, 0x15, 0x20, 0x20, 0x71, 0xC0,
+ 0x07, 0xA6, 0xE5, 0x30, 0x46,
+ 0x00, 0x01, 0x26, 0x00, 0x80, 0xFF, 0xF7, 0x9E,
+ 0xF9, 0xE8, 0x69, 0x01, 0x28, 0x02, 0xD1, 0x30,
+ 0x46, 0xFF, 0xF7, 0xD6, 0xFB, 0x60, 0x7B, 0x01,
+ 0x28, 0x06, 0xD1, 0x00, 0x20, 0x20, 0x71, 0x08,
+ 0x24, 0x9E, 0x48, 0xFD, 0xF7, 0x99, 0xFE, 0x04,
+ 0xE0, 0x10, 0x20, 0x20, 0x71, 0x00, 0x24, 0x00,
+ 0xE0, 0x01, 0x24, 0x20, 0x46, 0x8C, 0xE5, 0x10,
+ 0xB5, 0xFD, 0xF7, 0xF2, 0xF9, 0x95, 0x48, 0x40,
+ 0x6C, 0xC0, 0xB2, 0xFD, 0xF7, 0x0C, 0xFD, 0x94,
+ 0x48, 0x14, 0x21, 0x01, 0x71, 0x01, 0x7B, 0x01,
+ 0x29, 0x03, 0xD1, 0x00, 0x21, 0x01, 0x73, 0x05,
+ 0x20, 0x10, 0xBD, 0x01, 0x20, 0x10, 0xBD, 0x70,
+ 0xB5, 0xFD, 0xF7, 0x39, 0xFD, 0x01, 0x28, 0x3B,
+ 0xD1, 0xFC, 0xF7, 0x2E, 0xFF, 0xFD, 0xF7, 0xE0,
+ 0xFE, 0x06, 0x46, 0xFD, 0xF7, 0xE1, 0xFE, 0x87,
+ 0x4A, 0x87, 0x4D, 0x00, 0x24, 0x00, 0x28, 0x02,
+ 0xD1, 0xD0, 0x6C, 0xB0, 0x42,
+ 0x00, 0x01, 0x27, 0x00, 0x80, 0x1B, 0xD2, 0x29,
+ 0x8B, 0x15, 0x23, 0x8E, 0x06, 0xD8, 0x07, 0x00,
+ 0x2E, 0x0C, 0xDA, 0x16, 0x6C, 0x01, 0x2E, 0x10,
+ 0xD1, 0xEE, 0x7C, 0x02, 0x2E, 0x06, 0xD3, 0x96,
+ 0x6C, 0x2A, 0x7D, 0x96, 0x42, 0x04, 0xD9, 0xEC,
+ 0x74, 0x52, 0x1C, 0x2A, 0x75, 0x2B, 0x71, 0x4F,
+ 0xE5, 0xFF, 0x20, 0x01, 0x30, 0x01, 0x43, 0x29,
+ 0x83, 0x0F, 0xE0, 0x80, 0x20, 0xFA, 0xE7, 0xFD,
+ 0xF7, 0xB7, 0xFE, 0xA9, 0x7B, 0x01, 0x29, 0x08,
+ 0xD1, 0x00, 0x28, 0x06, 0xD1, 0xAC, 0x73, 0xFE,
+ 0xF7, 0xBE, 0xFA, 0xFE, 0xF7, 0xEA, 0xFA, 0xFE,
+ 0xF7, 0x9F, 0xFA, 0x2C, 0x71, 0x08, 0x20, 0x37,
+ 0xE5, 0x01, 0x20, 0x35, 0xE5, 0x70, 0xB5, 0x6C,
+ 0x4C, 0x00, 0x25, 0x20, 0x8B, 0xC1, 0x05, 0x00,
+ 0x29, 0x02, 0xDA, 0x25, 0x71, 0x08, 0x20, 0x2B,
+ 0xE5, 0xC0, 0x06, 0x0E, 0xD4, 0x02, 0x20, 0xFD,
+ 0xF7, 0x52, 0xFF, 0x02, 0x20,
+ 0x00, 0x01, 0x28, 0x00, 0x80, 0xFD, 0xF7, 0x60,
+ 0xFF, 0x02, 0x20, 0xF8, 0xF7, 0x8D, 0xFA, 0x01,
+ 0x20, 0x01, 0xF0, 0xB4, 0xFE, 0x20, 0x8B, 0x10,
+ 0x21, 0x4C, 0xE0, 0x60, 0x7D, 0x00, 0x28, 0x0F,
+ 0xD1, 0x02, 0x20, 0xF8, 0xF7, 0x77, 0xF8, 0xFD,
+ 0xF7, 0x8C, 0xFE, 0x5A, 0x48, 0x80, 0x6E, 0xC0,
+ 0xB2, 0xFD, 0xF7, 0x55, 0xFE, 0x01, 0x20, 0x60,
+ 0x75, 0x03, 0x20, 0xF9, 0xF7, 0xE8, 0xFF, 0x37,
+ 0xE0, 0x03, 0x20, 0xF8, 0xF7, 0x67, 0xF8, 0xFD,
+ 0xF7, 0x7C, 0xFE, 0x60, 0x7C, 0xA0, 0x74, 0x40,
+ 0x1C, 0xC0, 0xB2, 0x60, 0x74, 0x03, 0x28, 0x04,
+ 0xD3, 0xA0, 0x7D, 0x00, 0x28, 0x00, 0xD0, 0x01,
+ 0x20, 0x60, 0x74, 0x61, 0x7C, 0x03, 0x20, 0x49,
+ 0x1E, 0xF8, 0xF7, 0x45, 0xF8, 0xFD, 0xF7, 0x90,
+ 0xFE, 0x49, 0x48, 0x61, 0x7C, 0x1C, 0x30, 0x4A,
+ 0x4A, 0x40, 0x5C, 0x10, 0x70, 0x46, 0x48, 0x49,
+ 0x4A, 0x1F, 0x30, 0x40, 0x5C,
+ 0x00, 0x01, 0x29, 0x00, 0x80, 0x10, 0x70, 0x44,
+ 0x48, 0x47, 0x4A, 0x22, 0x30, 0x40, 0x5C, 0x10,
+ 0x70, 0x46, 0x4A, 0x88, 0x02, 0x80, 0x18, 0x46,
+ 0x4A, 0x10, 0x60, 0xA0, 0x7C, 0xFE, 0xF7, 0xEB,
+ 0xFF, 0xA5, 0x75, 0xE0, 0x7C, 0x40, 0x21, 0x40,
+ 0x1C, 0xE0, 0x74, 0x20, 0x8B, 0x08, 0x43, 0x20,
+ 0x83, 0x20, 0x8B, 0x20, 0x21, 0x08, 0x43, 0x20,
+ 0x83, 0x13, 0x20, 0x20, 0x71, 0xC0, 0x07, 0xC7,
+ 0xE4, 0x10, 0xB5, 0xFF, 0xF7, 0x3B, 0xFD, 0x04,
+ 0x46, 0x32, 0x48, 0x40, 0x69, 0x32, 0x49, 0xC9,
+ 0x6C, 0xFE, 0xF7, 0x89, 0xF8, 0xFE, 0xF7, 0x8E,
+ 0xFB, 0x30, 0x48, 0xFD, 0xF7, 0xBD, 0xFD, 0x20,
+ 0x46, 0x10, 0xBD, 0x2D, 0x49, 0x48, 0x71, 0x70,
+ 0x47, 0x10, 0xB5, 0xFC, 0xF7, 0x89, 0xFE, 0x10,
+ 0xBD, 0x10, 0xB5, 0xFC, 0xF7, 0x5D, 0xFE, 0x10,
+ 0xBD, 0x2E, 0x48, 0x70, 0x47, 0x10, 0xB5, 0xFD,
+ 0xF7, 0x0F, 0xF9, 0x24, 0x48,
+ 0x00, 0x01, 0x2A, 0x00, 0x80, 0x40, 0x6C, 0xC0,
+ 0xB2, 0xFD, 0xF7, 0x29, 0xFC, 0xFD, 0xF7, 0x63,
+ 0xFC, 0x01, 0x28, 0xFB, 0xD1, 0xFC, 0xF7, 0x58,
+ 0xFE, 0x10, 0xBD, 0x70, 0xB5, 0x05, 0x46, 0x0C,
+ 0x46, 0x56, 0x18, 0x09, 0xE0, 0xA0, 0xB2, 0x29,
+ 0x46, 0x00, 0xF0, 0xA4, 0xFA, 0x00, 0x28, 0x01,
+ 0xD0, 0x72, 0xB6, 0xFE, 0xE7, 0x80, 0x35, 0x64,
+ 0x1C, 0xA6, 0x42, 0xF3, 0xD8, 0x88, 0xE4, 0x16,
+ 0x49, 0x03, 0x20, 0x08, 0x71, 0xC0, 0x07, 0x70,
+ 0x47, 0x70, 0xB5, 0x40, 0x08, 0x00, 0x25, 0x12,
+ 0x4B, 0x90, 0x42, 0x01, 0xD3, 0x1D, 0x72, 0x01,
+ 0xE0, 0x14, 0x1A, 0x1C, 0x72, 0x16, 0x4C, 0xA6,
+ 0x69, 0x36, 0x1A, 0x76, 0x1E, 0x96, 0x42, 0x02,
+ 0xD8, 0xA2, 0x69, 0x52, 0x1E, 0x00, 0xE0, 0x82,
+ 0x18, 0x5A, 0x72, 0x88, 0x42, 0x01, 0xD3, 0x9D,
+ 0x72, 0x01, 0xE0, 0x0A, 0x1A, 0x9A, 0x72, 0xE2,
+ 0x69, 0x12, 0x1A, 0x52, 0x1E,
+ 0x00, 0x01, 0x2B, 0x00, 0x80, 0x8A, 0x42, 0x02,
+ 0xD8, 0xE0, 0x69, 0x40, 0x1E, 0x00, 0xE0, 0x40,
+ 0x18, 0xD8, 0x72, 0x5D, 0xE4, 0x78, 0xDC, 0x00,
+ 0x00, 0x30, 0x02, 0x00, 0x20, 0x23, 0x83, 0x00,
+ 0x00, 0x34, 0x03, 0x00, 0x20, 0x35, 0x03, 0x00,
+ 0x20, 0x36, 0x03, 0x00, 0x20, 0x80, 0xE2, 0x00,
+ 0x00, 0x3C, 0x03, 0x00, 0x20, 0x08, 0x0F, 0x00,
+ 0x20, 0x88, 0xDF, 0x00, 0x00, 0x10, 0xB5, 0xC2,
+ 0x48, 0x40, 0x7A, 0x00, 0x28, 0x01, 0xD1, 0x01,
+ 0x20, 0x00, 0xE0, 0x00, 0x20, 0x03, 0xF0, 0x1A,
+ 0xF9, 0x10, 0xBD, 0x10, 0xB5, 0x00, 0x20, 0x03,
+ 0xF0, 0x97, 0xF8, 0x03, 0xF0, 0x2A, 0xF9, 0x00,
+ 0x20, 0x03, 0xF0, 0x9B, 0xF8, 0x00, 0x20, 0x03,
+ 0xF0, 0xA1, 0xF8, 0xB8, 0x48, 0x00, 0x78, 0x01,
+ 0x07, 0xB5, 0x48, 0x0E, 0xD4, 0x40, 0x7A, 0x00,
+ 0x28, 0x04, 0xD1, 0x01, 0x20, 0x03, 0xF0, 0x0B,
+ 0xF9, 0x01, 0x20, 0x03, 0xE0,
+ 0x00, 0x01, 0x2C, 0x00, 0x80, 0x01, 0x20, 0x03,
+ 0xF0, 0x06, 0xF9, 0x00, 0x20, 0x03, 0xF0, 0xFA,
+ 0xF8, 0x10, 0xBD, 0x00, 0x7A, 0x03, 0xF0, 0xFF,
+ 0xF8, 0xFF, 0xF7, 0xD0, 0xFF, 0x10, 0xBD, 0xD8,
+ 0xE7, 0x30, 0xB5, 0x01, 0x23, 0xA8, 0x49, 0x24,
+ 0x20, 0x8B, 0x71, 0xC8, 0x71, 0xA7, 0x48, 0x02,
+ 0x78, 0x9A, 0x43, 0x02, 0x70, 0x02, 0x78, 0xFD,
+ 0x24, 0x22, 0x40, 0x02, 0x70, 0x5A, 0x02, 0x0A,
+ 0x80, 0x00, 0x22, 0x4A, 0x80, 0x8A, 0x80, 0x04,
+ 0x78, 0xF7, 0x25, 0x2C, 0x40, 0x04, 0x70, 0x02,
+ 0x24, 0x0C, 0x72, 0x4A, 0x72, 0x01, 0x78, 0xFB,
+ 0x22, 0x11, 0x40, 0x01, 0x70, 0x43, 0x70, 0x30,
+ 0xBD, 0x99, 0x49, 0x9B, 0x48, 0x4A, 0x88, 0x82,
+ 0x62, 0x89, 0x88, 0xC1, 0x62, 0x97, 0x49, 0x09,
+ 0x78, 0xC9, 0x07, 0x03, 0xD0, 0x41, 0x69, 0x08,
+ 0x22, 0x11, 0x43, 0x41, 0x61, 0x70, 0x47, 0x10,
+ 0xB5, 0x92, 0x48, 0x40, 0x78,
+ 0x00, 0x01, 0x2D, 0x00, 0x80, 0x00, 0x28, 0x0B,
+ 0xD1, 0x03, 0xF0, 0x92, 0xF8, 0xFF, 0xF7, 0xC8,
+ 0xFF, 0x03, 0x21, 0x00, 0x20, 0xF9, 0xF7, 0xA8,
+ 0xFF, 0x8E, 0x49, 0x00, 0x20, 0xF9, 0xF7, 0x9A,
+ 0xFF, 0x8B, 0x48, 0x40, 0x69, 0xC0, 0x07, 0x01,
+ 0xD0, 0x00, 0xF0, 0x05, 0xF9, 0xFF, 0xF7, 0xD8,
+ 0xFF, 0xFF, 0xF7, 0x8F, 0xFF, 0x10, 0xBD, 0x10,
+ 0xB5, 0x03, 0xF0, 0x42, 0xF8, 0x10, 0xBD, 0x84,
+ 0x48, 0x41, 0x69, 0x01, 0x22, 0x11, 0x43, 0x41,
+ 0x61, 0x80, 0x48, 0x01, 0x78, 0x04, 0x22, 0x11,
+ 0x43, 0x01, 0x70, 0x70, 0x47, 0x10, 0xB5, 0x00,
+ 0xF0, 0xEE, 0xF8, 0x7C, 0x48, 0x01, 0x78, 0xFB,
+ 0x22, 0x11, 0x40, 0x01, 0x70, 0x10, 0xBD, 0x30,
+ 0xB4, 0x78, 0x4A, 0x01, 0x28, 0x13, 0x78, 0x02,
+ 0xD1, 0xF7, 0x24, 0x23, 0x40, 0x01, 0xE0, 0x08,
+ 0x24, 0x23, 0x43, 0x13, 0x70, 0x72, 0x4A, 0x10,
+ 0x72, 0x51, 0x72, 0x30, 0xBC,
+ 0x00, 0x01, 0x2E, 0x00, 0x80, 0x65, 0xE7, 0x10,
+ 0xB5, 0x6F, 0x48, 0x40, 0x7A, 0x00, 0x28, 0x00,
+ 0xD0, 0x01, 0x20, 0x03, 0xF0, 0x77, 0xF8, 0x10,
+ 0xBD, 0x10, 0xB5, 0x03, 0xF0, 0x85, 0xF8, 0x01,
+ 0x21, 0x48, 0x40, 0x03, 0xF0, 0x6F, 0xF8, 0x10,
+ 0xBD, 0x68, 0x49, 0x0A, 0x78, 0x01, 0x23, 0x1A,
+ 0x43, 0x0A, 0x70, 0x69, 0x49, 0x64, 0x4A, 0x88,
+ 0x42, 0x01, 0xD9, 0x91, 0x80, 0x00, 0xE0, 0x90,
+ 0x80, 0x8E, 0xE7, 0x10, 0xB5, 0x03, 0xF0, 0x50,
+ 0xF8, 0x10, 0xBD, 0x64, 0x49, 0x80, 0x00, 0x40,
+ 0x18, 0x00, 0x68, 0xC0, 0xB2, 0x70, 0x47, 0x70,
+ 0xB5, 0x0C, 0x46, 0x05, 0x46, 0x09, 0x0A, 0x03,
+ 0xF0, 0x43, 0xF8, 0xE1, 0xB2, 0x68, 0x1C, 0x03,
+ 0xF0, 0x3F, 0xF8, 0x70, 0xBD, 0x81, 0x00, 0x5B,
+ 0x48, 0x08, 0x18, 0x01, 0x68, 0x40, 0x68, 0x09,
+ 0x02, 0x01, 0x43, 0x88, 0xB2, 0x70, 0x47, 0x54,
+ 0x48, 0x80, 0x69, 0x08, 0x21,
+ 0x00, 0x01, 0x2F, 0x00, 0x80, 0x08, 0x40, 0x70,
+ 0x47, 0x10, 0xB5, 0x51, 0x4C, 0x00, 0xF0, 0x26,
+ 0xF9, 0xA1, 0x69, 0x09, 0x07, 0x07, 0xD4, 0xA1,
+ 0x68, 0x01, 0x22, 0x11, 0x43, 0xA1, 0x60, 0xC0,
+ 0xB2, 0x00, 0xF0, 0x20, 0xF9, 0x10, 0xBD, 0xC0,
+ 0xB2, 0x00, 0xF0, 0x1C, 0xF9, 0xEE, 0xE7, 0xEB,
+ 0xE7, 0x10, 0xB5, 0x47, 0x4C, 0x00, 0xF0, 0x12,
+ 0xF9, 0xA1, 0x69, 0x09, 0x07, 0x07, 0xD4, 0xA1,
+ 0x68, 0x49, 0x08, 0x49, 0x00, 0xA1, 0x60, 0xC0,
+ 0xB2, 0x00, 0xF0, 0x0C, 0xF9, 0x03, 0xE0, 0xC0,
+ 0xB2, 0x00, 0xF0, 0x08, 0xF9, 0xEE, 0xE7, 0xA0,
+ 0x68, 0x80, 0x07, 0xFC, 0xD4, 0x10, 0xBD, 0xE7,
+ 0xE7, 0x70, 0xB5, 0x04, 0x46, 0x80, 0x07, 0x01,
+ 0xD1, 0x01, 0x20, 0x04, 0x43, 0x37, 0x4E, 0x3C,
+ 0x4D, 0xB4, 0x70, 0xE0, 0x07, 0x12, 0xD0, 0xFF,
+ 0xF7, 0xC7, 0xFF, 0x35, 0x49, 0x48, 0x69, 0x80,
+ 0x07, 0x01, 0xD5, 0x09, 0x20,
+ 0x00, 0x01, 0x30, 0x00, 0x80, 0x00, 0xE0, 0x03,
+ 0x20, 0x08, 0x61, 0xFF, 0x20, 0xC8, 0x60, 0x03,
+ 0x20, 0xF9, 0xF7, 0x09, 0xFF, 0x03, 0x20, 0xF9,
+ 0xF7, 0xF7, 0xFE, 0x0E, 0xE0, 0x00, 0xF0, 0x4B,
+ 0xF8, 0xA8, 0x68, 0xFF, 0x21, 0xC8, 0x31, 0xB0,
+ 0x60, 0x88, 0x43, 0x40, 0x1C, 0xA8, 0x60, 0x2D,
+ 0x49, 0x08, 0x68, 0x70, 0x60, 0x80, 0x08, 0x80,
+ 0x00, 0x08, 0x60, 0xA0, 0x07, 0x10, 0xD5, 0x03,
+ 0x20, 0x02, 0xF0, 0x62, 0xFF, 0x00, 0x20, 0x02,
+ 0xF0, 0x68, 0xFF, 0x00, 0x20, 0x02, 0xF0, 0x6E,
+ 0xFF, 0x10, 0x20, 0x28, 0x61, 0x00, 0x20, 0xF9,
+ 0xF7, 0xE6, 0xFE, 0x00, 0x20, 0xF9, 0xF7, 0xD4,
+ 0xFE, 0x70, 0xBD, 0x70, 0xB5, 0x19, 0x4C, 0x00,
+ 0x20, 0xA5, 0x78, 0xF9, 0xF7, 0xD4, 0xFE, 0x00,
+ 0x20, 0x02, 0xF0, 0x4A, 0xFF, 0x1A, 0x4E, 0x10,
+ 0x20, 0x30, 0x61, 0x00, 0x20, 0xF9, 0xF7, 0xD3,
+ 0xFE, 0xE8, 0x07, 0x0B, 0xD0,
+ 0x00, 0x01, 0x31, 0x00, 0x80, 0x12, 0x48, 0x00,
+ 0x21, 0x01, 0x61, 0xFF, 0x21, 0xC1, 0x60, 0x03,
+ 0x20, 0xF9, 0xF7, 0xC1, 0xFE, 0x03, 0x20, 0xF9,
+ 0xF7, 0xC6, 0xFE, 0x09, 0xE0, 0x11, 0x49, 0x60,
+ 0x68, 0x08, 0x60, 0xA0, 0x68, 0xB0, 0x60, 0x20,
+ 0x78, 0x40, 0x07, 0x01, 0xD5, 0xFF, 0xF7, 0x07,
+ 0xFF, 0xFF, 0xF7, 0x7E, 0xFF, 0x70, 0xBD, 0x06,
+ 0x48, 0x81, 0x69, 0x09, 0x07, 0xFC, 0xD4, 0x41,
+ 0x69, 0x49, 0x08, 0x49, 0x00, 0x41, 0x61, 0x70,
+ 0x47, 0x48, 0x14, 0x00, 0x20, 0x88, 0x02, 0x00,
+ 0x20, 0x00, 0x00, 0x12, 0x40, 0x1B, 0x96, 0x00,
+ 0x00, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x10, 0x12,
+ 0x40, 0x00, 0x00, 0x14, 0x40, 0x00, 0x20, 0x14,
+ 0x40, 0x33, 0x49, 0x00, 0x20, 0x08, 0x70, 0x70,
+ 0x47, 0xF0, 0xB5, 0x32, 0x48, 0x85, 0xB0, 0x80,
+ 0x6A, 0x00, 0x24, 0x01, 0x27, 0x04, 0x90, 0x52,
+ 0xE0, 0x2F, 0x49, 0x60, 0x00,
+ 0x00, 0x01, 0x32, 0x00, 0x80, 0x40, 0x18, 0x82,
+ 0x88, 0x0B, 0x7B, 0xD2, 0x18, 0x03, 0x92, 0x82,
+ 0x88, 0x0B, 0x7B, 0xD2, 0x1A, 0x02, 0x92, 0x02,
+ 0x8A, 0x0B, 0x7E, 0xD2, 0x18, 0x01, 0x92, 0x00,
+ 0x8A, 0x09, 0x7E, 0x40, 0x1A, 0x00, 0x90, 0x27,
+ 0x48, 0x05, 0x57, 0x27, 0x48, 0x06, 0x57, 0x23,
+ 0x48, 0x40, 0x30, 0x00, 0x6A, 0x01, 0x28, 0x0B,
+ 0xD1, 0x96, 0x42, 0x10, 0xDC, 0x00, 0x98, 0x86,
+ 0x42, 0x30, 0xDC, 0x1D, 0x49, 0x38, 0x46, 0x0A,
+ 0x78, 0xA0, 0x40, 0x82, 0x43, 0x0A, 0x70, 0x29,
+ 0xE0, 0xF7, 0xF7, 0xFF, 0xFD, 0x00, 0x28, 0x03,
+ 0x98, 0x0C, 0xD1, 0x85, 0x42, 0x06, 0xDD, 0x16,
+ 0x49, 0x38, 0x46, 0x0A, 0x78, 0xA0, 0x40, 0x10,
+ 0x43, 0x08, 0x70, 0x1B, 0xE0, 0x02, 0x98, 0x85,
+ 0x42, 0x18, 0xDC, 0x11, 0xE0, 0x85, 0x42, 0x09,
+ 0xDD, 0x01, 0x98, 0x86, 0x42, 0x06, 0xDD, 0x0E,
+ 0x48, 0x39, 0x46, 0x02, 0x78,
+ 0x00, 0x01, 0x33, 0x00, 0x80, 0xA1, 0x40, 0x11,
+ 0x43, 0x01, 0x70, 0x0B, 0xE0, 0x02, 0x98, 0x85,
+ 0x42, 0x08, 0xDC, 0x00, 0x98, 0x86, 0x42, 0x05,
+ 0xDC, 0x07, 0x4A, 0x38, 0x46, 0x11, 0x78, 0xA0,
+ 0x40, 0x81, 0x43, 0x11, 0x70, 0x64, 0x1C, 0x04,
+ 0x98, 0x84, 0x42, 0xA9, 0xD3, 0x05, 0xB0, 0xF0,
+ 0xBD, 0x01, 0x48, 0x00, 0x78, 0x70, 0x47, 0x00,
+ 0x00, 0x94, 0x02, 0x00, 0x20, 0x88, 0xDF, 0x00,
+ 0x00, 0xE4, 0xDD, 0x00, 0x00, 0x0C, 0x02, 0x00,
+ 0x20, 0x10, 0x02, 0x00, 0x20, 0x80, 0x1C, 0x80,
+ 0x08, 0x03, 0xD0, 0x00, 0xBF, 0x40, 0x1E, 0x00,
+ 0x46, 0xFC, 0xD1, 0x70, 0x47, 0xEF, 0xF3, 0x10,
+ 0x80, 0x72, 0xB6, 0x70, 0x47, 0x80, 0xF3, 0x10,
+ 0x88, 0x70, 0x47, 0x00, 0x00, 0x70, 0xB5, 0x05,
+ 0x46, 0x0B, 0x48, 0x00, 0x23, 0x0B, 0x4C, 0x10,
+ 0xE0, 0xCA, 0x5C, 0x12, 0x02, 0x50, 0x40, 0x08,
+ 0x22, 0x06, 0x04, 0x02, 0xD5,
+ 0x00, 0x01, 0x34, 0x00, 0x80, 0x40, 0x00, 0x60,
+ 0x40, 0x00, 0xE0, 0x40, 0x00, 0x52, 0x1E, 0x12,
+ 0x06, 0x80, 0xB2, 0x12, 0x0E, 0xF4, 0xD1, 0x5B,
+ 0x1C, 0x9B, 0xB2, 0xAB, 0x42, 0xEC, 0xD3, 0x70,
+ 0xBD, 0xFF, 0xFF, 0x00, 0x00, 0x21, 0x10, 0x00,
+ 0x00, 0x1C, 0xB5, 0x68, 0x46, 0x00, 0xF0, 0x59,
+ 0xF8, 0x00, 0x22, 0x0E, 0x49, 0x00, 0x28, 0x08,
+ 0xD1, 0x6B, 0x46, 0x58, 0x88, 0x90, 0x28, 0x04,
+ 0xD1, 0x18, 0x88, 0xC3, 0x1F, 0xF9, 0x3B, 0x5F,
+ 0x2B, 0x02, 0xD3, 0x0A, 0x70, 0x4A, 0x80, 0x1C,
+ 0xBD, 0x07, 0x4A, 0x40, 0x00, 0x80, 0x18, 0xFF,
+ 0x38, 0xFF, 0x38, 0x02, 0x38, 0x00, 0x88, 0x48,
+ 0x80, 0x80, 0xB2, 0xC0, 0x06, 0xC0, 0x0E, 0x08,
+ 0x70, 0x1C, 0xBD, 0x00, 0x00, 0x96, 0x02, 0x00,
+ 0x20, 0x78, 0xCE, 0x00, 0x00, 0x70, 0xB5, 0x01,
+ 0x23, 0x00, 0x22, 0x5B, 0x02, 0x98, 0x42, 0x1C,
+ 0xD2, 0x2B, 0x4B, 0x2A, 0x4C,
+ 0x00, 0x01, 0x35, 0x00, 0x80, 0x9C, 0x60, 0x00,
+ 0x25, 0xFF, 0x28, 0x00, 0xD9, 0x1D, 0x01, 0x29,
+ 0x4E, 0x35, 0x43, 0x25, 0x60, 0x7F, 0x25, 0x65,
+ 0x60, 0x8D, 0x5C, 0xA6, 0x18, 0x35, 0x72, 0x52,
+ 0x1C, 0xD2, 0xB2, 0x80, 0x2A, 0xF8, 0xD3, 0x24,
+ 0x49, 0x59, 0x60, 0x59, 0x68, 0x00, 0x29, 0xFC,
+ 0xDB, 0x9A, 0x68, 0x05, 0x21, 0x49, 0x07, 0x8A,
+ 0x42, 0x01, 0xD0, 0x09, 0x20, 0x70, 0xBD, 0x9C,
+ 0x60, 0x1E, 0x4A, 0x00, 0x04, 0x80, 0x18, 0x20,
+ 0x60, 0x1B, 0x48, 0x40, 0x1C, 0x58, 0x60, 0x58,
+ 0x68, 0x00, 0x28, 0xFC, 0xDB, 0x98, 0x68, 0x88,
+ 0x42, 0x01, 0xD1, 0x00, 0x20, 0x70, 0xBD, 0x98,
+ 0x68, 0x70, 0xBD, 0x70, 0xB5, 0x05, 0x46, 0x12,
+ 0x4E, 0x15, 0x48, 0xB0, 0x60, 0xFF, 0xF7, 0x76,
+ 0xFF, 0xF1, 0x02, 0x71, 0x60, 0x71, 0x68, 0x00,
+ 0x29, 0xFC, 0xDB, 0xB4, 0x68, 0x71, 0x68, 0xC0,
+ 0xB2, 0x0E, 0x05, 0x36, 0x0D,
+ 0x00, 0x01, 0x36, 0x00, 0x80, 0xFF, 0xF7, 0x6E,
+ 0xFF, 0x20, 0x0F, 0x0A, 0x28, 0x01, 0xD0, 0x01,
+ 0x20, 0x70, 0xBD, 0x2C, 0x80, 0x20, 0x0C, 0x28,
+ 0x71, 0x20, 0x02, 0x00, 0x0F, 0x68, 0x71, 0x20,
+ 0x03, 0x00, 0x0F, 0xA8, 0x71, 0x6E, 0x80, 0x00,
+ 0x20, 0x70, 0xBD, 0x00, 0x00, 0x54, 0x14, 0x00,
+ 0x20, 0x00, 0x00, 0x10, 0x40, 0xB6, 0xD7, 0x00,
+ 0x00, 0x04, 0x00, 0x00, 0x80, 0xB6, 0xD8, 0x00,
+ 0x00, 0xB6, 0xD3, 0x00, 0x00, 0xF8, 0xB5, 0xFF,
+ 0x4C, 0xFF, 0x49, 0xA0, 0x78, 0x09, 0x78, 0xFF,
+ 0x4A, 0x48, 0x43, 0x12, 0x68, 0xC0, 0x00, 0x85,
+ 0x18, 0xFD, 0x48, 0x42, 0x7C, 0x00, 0x2A, 0x01,
+ 0xD1, 0x01, 0x22, 0x01, 0xE0, 0xFB, 0x4A, 0x12,
+ 0x78, 0x40, 0x7C, 0x53, 0xB2, 0x62, 0x78, 0x00,
+ 0x28, 0x01, 0xD1, 0xD0, 0x1C, 0x03, 0xE0, 0xF8,
+ 0x48, 0x00, 0x78, 0x08, 0x1A, 0x80, 0x18, 0xC4,
+ 0xB2, 0x00, 0x20, 0x6E, 0x46,
+ 0x00, 0x01, 0x37, 0x00, 0x80, 0x21, 0x46, 0x03,
+ 0x28, 0x02, 0xD2, 0x01, 0x46, 0x59, 0x43, 0x89,
+ 0x18, 0x31, 0x54, 0x40, 0x1C, 0x04, 0x28, 0xF5,
+ 0xD3, 0xF0, 0x48, 0x00, 0x78, 0x58, 0xE0, 0xF0,
+ 0x49, 0x12, 0x22, 0x09, 0x78, 0x12, 0x27, 0x51,
+ 0x43, 0xEE, 0x4A, 0x36, 0x24, 0x89, 0x18, 0x42,
+ 0x00, 0x8E, 0x5E, 0x89, 0x18, 0xCF, 0x5F, 0x24,
+ 0x22, 0x8A, 0x5E, 0x0C, 0x5F, 0xF1, 0x19, 0x8C,
+ 0x46, 0x89, 0x18, 0x09, 0x1B, 0x7F, 0x23, 0x89,
+ 0x10, 0xDB, 0x43, 0x99, 0x42, 0x01, 0xDA, 0x19,
+ 0x46, 0x02, 0xE0, 0x7F, 0x29, 0x00, 0xDD, 0x7F,
+ 0x21, 0x6B, 0x46, 0x1B, 0x78, 0xDB, 0x00, 0x1B,
+ 0x18, 0xE9, 0x54, 0x61, 0x46, 0x09, 0x19, 0x89,
+ 0x1A, 0x7F, 0x23, 0x89, 0x10, 0xDB, 0x43, 0x99,
+ 0x42, 0x01, 0xDA, 0x19, 0x46, 0x02, 0xE0, 0x7F,
+ 0x29, 0x00, 0xDD, 0x7F, 0x21, 0x6B, 0x46, 0x5B,
+ 0x78, 0xDB, 0x00, 0x1B, 0x18,
+ 0x00, 0x01, 0x38, 0x00, 0x80, 0xE9, 0x54, 0xB1,
+ 0x18, 0x09, 0x19, 0xC9, 0x1B, 0x7F, 0x23, 0x89,
+ 0x10, 0xDB, 0x43, 0x99, 0x42, 0x01, 0xDA, 0x19,
+ 0x46, 0x02, 0xE0, 0x7F, 0x29, 0x00, 0xDD, 0x7F,
+ 0x21, 0x6B, 0x46, 0x9B, 0x78, 0xDB, 0x00, 0x1B,
+ 0x18, 0xE9, 0x54, 0xB9, 0x18, 0x09, 0x19, 0x89,
+ 0x1B, 0x7F, 0x22, 0x89, 0x10, 0xD2, 0x43, 0x91,
+ 0x42, 0x01, 0xDA, 0x11, 0x46, 0x02, 0xE0, 0x7F,
+ 0x29, 0x00, 0xDD, 0x7F, 0x21, 0x6B, 0x46, 0xDA,
+ 0x78, 0xD2, 0x00, 0x12, 0x18, 0xA9, 0x54, 0x40,
+ 0x1C, 0xC5, 0x49, 0x09, 0x78, 0x88, 0x42, 0xA2,
+ 0xD3, 0xC4, 0x48, 0xC5, 0x49, 0x00, 0x78, 0x09,
+ 0x78, 0x88, 0x42, 0x09, 0xD1, 0xC3, 0x49, 0x08,
+ 0x78, 0x00, 0x28, 0x05, 0xD0, 0x02, 0x28, 0x03,
+ 0xD2, 0x40, 0x1C, 0x08, 0x70, 0xFC, 0xF7, 0xE3,
+ 0xFE, 0xF8, 0xBD, 0xF8, 0xB5, 0x14, 0x26, 0xBE,
+ 0x49, 0x02, 0x20, 0xC8, 0x60,
+ 0x00, 0x01, 0x39, 0x00, 0x80, 0xB9, 0x49, 0xB2,
+ 0x4C, 0x08, 0x78, 0x40, 0x1C, 0x08, 0x70, 0xBB,
+ 0x48, 0xAD, 0x49, 0x00, 0x78, 0x09, 0x78, 0x48,
+ 0x43, 0xB9, 0x49, 0x09, 0x78, 0x40, 0x18, 0xAB,
+ 0x49, 0xC0, 0x00, 0x09, 0x68, 0x45, 0x18, 0x20,
+ 0x3C, 0x21, 0x69, 0xB6, 0x4F, 0xA8, 0x48, 0x00,
+ 0x90, 0x01, 0x29, 0x13, 0xD1, 0xFC, 0xF7, 0xB1,
+ 0xFA, 0x00, 0x09, 0x03, 0xD0, 0x00, 0x98, 0x80,
+ 0x79, 0x00, 0x28, 0x0B, 0xD1, 0x38, 0x6A, 0xB0,
+ 0x49, 0x00, 0xB2, 0x0A, 0x68, 0x12, 0x18, 0x0A,
+ 0x60, 0x61, 0x69, 0xAE, 0x4A, 0x50, 0x43, 0x41,
+ 0x43, 0x0A, 0x14, 0x00, 0xE0, 0x00, 0x22, 0x9F,
+ 0x48, 0xAB, 0x4F, 0x00, 0x78, 0x15, 0xE0, 0xA7,
+ 0x4B, 0x81, 0x00, 0xC9, 0x18, 0x09, 0x68, 0x0B,
+ 0xB2, 0x41, 0x00, 0x79, 0x5E, 0x9B, 0x1A, 0x4B,
+ 0x43, 0x99, 0x12, 0x7F, 0x23, 0x09, 0xB2, 0xDB,
+ 0x43, 0x99, 0x42, 0x01, 0xDA,
+ 0x00, 0x01, 0x3A, 0x00, 0x80, 0x2B, 0x54, 0x03,
+ 0xE0, 0x7F, 0x29, 0x00, 0xDD, 0x7F, 0x21, 0x29,
+ 0x54, 0x40, 0x1C, 0x95, 0x49, 0x09, 0x78, 0x88,
+ 0x42, 0xE5, 0xD3, 0x9E, 0x4D, 0x98, 0x48, 0x29,
+ 0x78, 0x01, 0x70, 0x9D, 0x48, 0x95, 0x49, 0x00,
+ 0x78, 0x08, 0x70, 0x86, 0x49, 0x09, 0x78, 0x01,
+ 0x29, 0x1A, 0xD1, 0x84, 0x49, 0x00, 0x22, 0x0A,
+ 0x70, 0x8F, 0x4F, 0x51, 0x1E, 0xF9, 0x60, 0x00,
+ 0xF0, 0xB5, 0xFE, 0x00, 0xF0, 0xA5, 0xFE, 0x00,
+ 0x98, 0xC0, 0x7B, 0xFC, 0xF7, 0xC8, 0xFD, 0x05,
+ 0x20, 0xF9, 0xF7, 0x69, 0xFC, 0x38, 0x68, 0x03,
+ 0x21, 0x49, 0x07, 0x08, 0x43, 0x38, 0x60, 0x38,
+ 0x68, 0x80, 0x00, 0x01, 0xD5, 0x76, 0x1E, 0xFA,
+ 0xD2, 0x80, 0x48, 0x81, 0x49, 0x00, 0x78, 0x09,
+ 0x78, 0x40, 0x1C, 0x0F, 0x26, 0x89, 0x4F, 0x88,
+ 0x42, 0x64, 0xD2, 0x89, 0x48, 0x89, 0x4A, 0x01,
+ 0x78, 0x28, 0x78, 0x09, 0x18,
+ 0x00, 0x01, 0x3B, 0x00, 0x80, 0x51, 0x5C, 0x88,
+ 0x4A, 0x89, 0x00, 0x89, 0x18, 0x0E, 0x60, 0x40,
+ 0x1C, 0xC0, 0xB2, 0x86, 0x49, 0x28, 0x70, 0x09,
+ 0x78, 0x88, 0x42, 0x0C, 0xD9, 0x84, 0x48, 0x7E,
+ 0x49, 0x00, 0x78, 0x28, 0x70, 0x08, 0x78, 0x40,
+ 0x1C, 0xC0, 0xB2, 0x08, 0x70, 0xFC, 0xF7, 0xEB,
+ 0xFD, 0x64, 0x49, 0x01, 0x20, 0x08, 0x70, 0x20,
+ 0x69, 0x00, 0x28, 0x26, 0xD0, 0x79, 0x4A, 0x38,
+ 0x78, 0x79, 0x4B, 0x10, 0x5C, 0x80, 0x00, 0xC0,
+ 0x18, 0x06, 0x60, 0x5F, 0x48, 0x00, 0x78, 0x41,
+ 0x08, 0x28, 0x78, 0x81, 0x42, 0x0B, 0xD8, 0xE1,
+ 0x69, 0x02, 0x29, 0x0D, 0xD1, 0x00, 0x99, 0x49,
+ 0x7C, 0x00, 0x29, 0x09, 0xD0, 0x5C, 0x49, 0x09,
+ 0x78, 0x49, 0x08, 0x81, 0x42, 0x04, 0xD9, 0x58,
+ 0x48, 0x60, 0x38, 0x00, 0x6A, 0x40, 0x1E, 0x01,
+ 0xE0, 0x69, 0x48, 0x00, 0x78, 0x38, 0x70, 0x39,
+ 0x78, 0x0C, 0x20, 0x51, 0x5C,
+ 0x00, 0x01, 0x3C, 0x00, 0x80, 0x8A, 0x00, 0xD1,
+ 0x18, 0x08, 0x60, 0x65, 0x48, 0x65, 0x4B, 0x02,
+ 0x78, 0x28, 0x78, 0x01, 0x21, 0x12, 0x18, 0x9A,
+ 0x5C, 0x63, 0x4B, 0x92, 0x00, 0xD2, 0x18, 0x11,
+ 0x60, 0x49, 0x49, 0x5D, 0x4A, 0x09, 0x78, 0x12,
+ 0x78, 0x51, 0x43, 0x08, 0x18, 0xFC, 0xF7, 0x0E,
+ 0xFD, 0x44, 0x48, 0x00, 0x78, 0x01, 0x28, 0x2C,
+ 0xD0, 0x4F, 0x48, 0x01, 0x68, 0x03, 0x22, 0x52,
+ 0x07, 0x11, 0x43, 0x01, 0x60, 0x49, 0x48, 0x4A,
+ 0x49, 0x00, 0x78, 0x09, 0x78, 0x88, 0x42, 0x25,
+ 0xD1, 0x53, 0x48, 0x29, 0x78, 0x00, 0x78, 0x53,
+ 0x4C, 0x40, 0x18, 0x20, 0x5C, 0x52, 0x4D, 0x80,
+ 0x00, 0x40, 0x19, 0x06, 0x60, 0x44, 0x49, 0x08,
+ 0x69, 0x02, 0x22, 0x90, 0x43, 0x08, 0x61, 0x05,
+ 0x20, 0xF9, 0xF7, 0xD9, 0xFB, 0x38, 0x78, 0x20,
+ 0x5C, 0x80, 0x00, 0x40, 0x19, 0x06, 0x60, 0x3D,
+ 0x49, 0x08, 0x78, 0x00, 0x28,
+ 0x00, 0x01, 0x3D, 0x00, 0x80, 0x06, 0xD0, 0x02,
+ 0x28, 0x04, 0xD2, 0x40, 0x1C, 0x08, 0x70, 0xFC,
+ 0xF7, 0xD6, 0xFD, 0xF8, 0xBD, 0x47, 0x49, 0x01,
+ 0x20, 0x08, 0x70, 0xF8, 0xBD, 0x36, 0x49, 0x08,
+ 0x68, 0x8A, 0x03, 0x10, 0x43, 0x08, 0x60, 0xF8,
+ 0xBD, 0xFE, 0xB5, 0x3A, 0x4D, 0x14, 0x26, 0x28,
+ 0x78, 0x01, 0x90, 0x31, 0x48, 0x02, 0x21, 0xC1,
+ 0x60, 0x2C, 0x48, 0x01, 0x78, 0x49, 0x1C, 0x01,
+ 0x70, 0x3D, 0x48, 0x12, 0x21, 0x00, 0x78, 0x48,
+ 0x43, 0x26, 0x49, 0x40, 0x18, 0x00, 0x90, 0x20,
+ 0x48, 0x20, 0x38, 0x02, 0x90, 0x00, 0x69, 0x2B,
+ 0x4F, 0x1D, 0x4C, 0x01, 0x28, 0x13, 0xD1, 0xFC,
+ 0xF7, 0x9C, 0xF9, 0x00, 0x09, 0x02, 0xD0, 0xA0,
+ 0x79, 0x00, 0x28, 0x0C, 0xD1, 0x38, 0x6A, 0x26,
+ 0x49, 0x00, 0xB2, 0x0A, 0x68, 0x12, 0x18, 0x0A,
+ 0x60, 0x02, 0x99, 0x49, 0x69, 0x23, 0x4A, 0x50,
+ 0x43, 0x41, 0x43, 0x09, 0x14,
+ 0x00, 0x01, 0x3E, 0x00, 0x80, 0x00, 0xE0, 0x00,
+ 0x21, 0x14, 0x48, 0x00, 0x78, 0x0D, 0xE0, 0x1D,
+ 0x4B, 0x82, 0x00, 0xD2, 0x18, 0x12, 0x68, 0x47,
+ 0x00, 0x13, 0xB2, 0x1D, 0x4A, 0x5B, 0x1A, 0xD2,
+ 0x5F, 0x53, 0x43, 0x9A, 0x12, 0x00, 0x9B, 0x40,
+ 0x1C, 0xDA, 0x53, 0x0F, 0x4A, 0x12, 0x78, 0x90,
+ 0x42, 0xED, 0xD3, 0x04, 0x4F, 0x38, 0x78, 0x01,
+ 0x28, 0x59, 0xD1, 0x00, 0x20, 0x38, 0x70, 0x40,
+ 0x1E, 0x0D, 0x49, 0x3B, 0xE0, 0x9C, 0x02, 0x00,
+ 0x20, 0x6D, 0x01, 0x00, 0x20, 0xAC, 0x01, 0x00,
+ 0x20, 0xE8, 0xDF, 0x00, 0x00, 0x80, 0x01, 0x00,
+ 0x20, 0x7F, 0x01, 0x00, 0x20, 0xA9, 0x02, 0x00,
+ 0x20, 0x6F, 0x01, 0x00, 0x20, 0xC4, 0x04, 0x00,
+ 0x20, 0xAA, 0x02, 0x00, 0x20, 0x77, 0x01, 0x00,
+ 0x20, 0x7A, 0x01, 0x00, 0x20, 0xA8, 0x02, 0x00,
+ 0x20, 0x00, 0x00, 0x11, 0x40, 0x72, 0x01, 0x00,
+ 0x20, 0x74, 0x01, 0x00, 0x20,
+ 0x00, 0x01, 0x3F, 0x00, 0x80, 0x00, 0x02, 0x11,
+ 0x40, 0xA8, 0x01, 0x00, 0x20, 0x3C, 0x0A, 0x00,
+ 0x00, 0x54, 0x05, 0x00, 0x20, 0x75, 0x01, 0x00,
+ 0x20, 0x73, 0x01, 0x00, 0x20, 0x76, 0x01, 0x00,
+ 0x20, 0x6E, 0x01, 0x00, 0x20, 0xC0, 0xE0, 0x00,
+ 0x00, 0x00, 0x04, 0x11, 0x40, 0x7E, 0x01, 0x00,
+ 0x20, 0x7D, 0x01, 0x00, 0x20, 0x81, 0x01, 0x00,
+ 0x20, 0x79, 0x01, 0x00, 0x20, 0xC8, 0x60, 0xFF,
+ 0x48, 0x00, 0x78, 0x00, 0xF0, 0x73, 0xFD, 0x00,
+ 0xF0, 0x63, 0xFD, 0xE0, 0x7B, 0xFC, 0xF7, 0x87,
+ 0xFC, 0x05, 0x20, 0xF9, 0xF7, 0x28, 0xFB, 0xFA,
+ 0x48, 0x00, 0x68, 0x03, 0x21, 0x49, 0x07, 0x08,
+ 0x43, 0xF7, 0x49, 0x08, 0x60, 0x08, 0x68, 0x80,
+ 0x00, 0x01, 0xD5, 0x76, 0x1E, 0xFA, 0xD2, 0x60,
+ 0x7C, 0x00, 0x28, 0xF4, 0x48, 0x00, 0x78, 0x08,
+ 0xD0, 0xF0, 0x49, 0xC0, 0x1C, 0x80, 0x08, 0x09,
+ 0x78, 0x80, 0x00, 0x48, 0x43,
+ 0x00, 0x01, 0x40, 0x00, 0x80, 0x29, 0x78, 0x89,
+ 0x00, 0x09, 0xE0, 0xEC, 0x49, 0xC0, 0x1C, 0x80,
+ 0x08, 0x09, 0x78, 0x80, 0x00, 0x48, 0x43, 0x29,
+ 0x78, 0xC9, 0x1C, 0x89, 0x08, 0x89, 0x00, 0x40,
+ 0x18, 0xF8, 0x70, 0xE9, 0x48, 0xE9, 0x4E, 0x03,
+ 0x78, 0x02, 0xF0, 0xD7, 0xFD, 0x08, 0x05, 0x0C,
+ 0x15, 0xA2, 0x05, 0x0C, 0x15, 0xC5, 0xEA, 0x02,
+ 0x21, 0x28, 0x78, 0xFC, 0xF7, 0x1D, 0xFC, 0xF8,
+ 0x78, 0x80, 0x1C, 0x05, 0xE0, 0x03, 0x21, 0x28,
+ 0x78, 0xFC, 0xF7, 0x16, 0xFC, 0xF8, 0x78, 0xC0,
+ 0x1C, 0xFC, 0xF7, 0xFC, 0xFB, 0x87, 0xE0, 0xDE,
+ 0x48, 0xDE, 0x49, 0x00, 0x78, 0x09, 0x78, 0x40,
+ 0x1C, 0x88, 0x42, 0xF7, 0xD2, 0x60, 0x7C, 0x00,
+ 0x28, 0x01, 0xD0, 0x01, 0x20, 0x00, 0xE0, 0x04,
+ 0x20, 0x31, 0x78, 0x40, 0x18, 0x28, 0x70, 0x60,
+ 0x7C, 0xD7, 0x4E, 0x00, 0x28, 0x03, 0xD0, 0x28,
+ 0x78, 0x31, 0x78, 0x88, 0x42,
+ 0x00, 0x01, 0x41, 0x00, 0x80, 0x07, 0xD2, 0x61,
+ 0x7C, 0xD4, 0x48, 0x00, 0x29, 0x10, 0xD1, 0x29,
+ 0x78, 0x02, 0x78, 0x91, 0x42, 0x0C, 0xD9, 0xD2,
+ 0x48, 0xC8, 0x49, 0x00, 0x78, 0x28, 0x70, 0x08,
+ 0x78, 0x40, 0x1C, 0xC0, 0xB2, 0x08, 0x70, 0xFC,
+ 0xF7, 0x6E, 0xFC, 0x01, 0x20, 0x38, 0x70, 0x09,
+ 0xE0, 0x61, 0x7C, 0x00, 0x29, 0x06, 0xD1, 0x29,
+ 0x78, 0x00, 0x78, 0xC9, 0x1C, 0x81, 0x42, 0x01,
+ 0xD9, 0xC0, 0x1E, 0x28, 0x70, 0xFF, 0x21, 0x01,
+ 0x98, 0xFC, 0xF7, 0xD6, 0xFB, 0x02, 0x98, 0x00,
+ 0x69, 0x00, 0x28, 0x27, 0xD0, 0xC4, 0x49, 0xC3,
+ 0x48, 0x0B, 0x78, 0x0F, 0x22, 0xC0, 0x5C, 0xC3,
+ 0x4B, 0x80, 0x00, 0xC0, 0x18, 0x02, 0x60, 0xB7,
+ 0x48, 0x00, 0x78, 0x42, 0x08, 0x28, 0x78, 0x82,
+ 0x42, 0x0A, 0xD8, 0x02, 0x9A, 0xD2, 0x69, 0x02,
+ 0x2A, 0x0A, 0xD1, 0x62, 0x7C, 0x00, 0x2A, 0x07,
+ 0xD0, 0x32, 0x78, 0x52, 0x08,
+ 0x00, 0x01, 0x42, 0x00, 0x80, 0x82, 0x42, 0x03,
+ 0xD9, 0xB9, 0x48, 0x00, 0x6A, 0x40, 0x1E, 0x01,
+ 0xE0, 0xB8, 0x48, 0x00, 0x78, 0x08, 0x70, 0xB3,
+ 0x4A, 0x09, 0x78, 0x0C, 0x20, 0x51, 0x5C, 0x89,
+ 0x00, 0xC9, 0x18, 0x08, 0x60, 0x00, 0x21, 0x28,
+ 0x78, 0xFC, 0xF7, 0xA6, 0xFB, 0x60, 0x7C, 0x00,
+ 0x28, 0xA4, 0x48, 0x00, 0x78, 0x09, 0xD0, 0xA1,
+ 0x49, 0xC0, 0x1C, 0x80, 0x08, 0x09, 0x78, 0x80,
+ 0x00, 0x48, 0x43, 0x29, 0x78, 0x89, 0x00, 0x40,
+ 0x18, 0x0A, 0xE0, 0xC0, 0x1C, 0x81, 0x08, 0x9B,
+ 0x48, 0x89, 0x00, 0x00, 0x78, 0x41, 0x43, 0x28,
+ 0x78, 0xC0, 0x1C, 0x80, 0x08, 0x80, 0x00, 0x08,
+ 0x18, 0xF8, 0x70, 0xC0, 0xB2, 0x74, 0xE7, 0x98,
+ 0x49, 0x08, 0x78, 0x40, 0x1C, 0x08, 0x70, 0x47,
+ 0xE0, 0x97, 0x48, 0x98, 0x49, 0x00, 0x78, 0x09,
+ 0x78, 0x40, 0x1C, 0x88, 0x42, 0x07, 0xD2, 0x01,
+ 0x21, 0x28, 0x78, 0xFC, 0xF7,
+ 0x00, 0x01, 0x43, 0x00, 0x80, 0x79, 0xFB, 0xF8,
+ 0x78, 0x40, 0x1C, 0xFC, 0xF7, 0x5F, 0xFB, 0x9A,
+ 0x49, 0x00, 0x20, 0x08, 0x70, 0x30, 0x78, 0x78,
+ 0x70, 0x98, 0x48, 0x01, 0x78, 0xB9, 0x70, 0x87,
+ 0x49, 0x09, 0x78, 0x01, 0x70, 0x28, 0x78, 0x96,
+ 0x49, 0x30, 0x70, 0x48, 0x68, 0x01, 0x22, 0x12,
+ 0x07, 0x10, 0x43, 0x48, 0x60, 0xD7, 0xE7, 0x86,
+ 0x48, 0x86, 0x49, 0x00, 0x78, 0x09, 0x78, 0x40,
+ 0x1C, 0x88, 0x42, 0x07, 0xD2, 0x01, 0x21, 0x28,
+ 0x78, 0xFC, 0xF7, 0x56, 0xFB, 0xF8, 0x78, 0x40,
+ 0x1C, 0xFC, 0xF7, 0x3C, 0xFB, 0x7C, 0x48, 0x00,
+ 0x21, 0x01, 0x70, 0x87, 0x49, 0x04, 0x20, 0x08,
+ 0x70, 0x30, 0x78, 0x78, 0x70, 0x85, 0x48, 0x01,
+ 0x78, 0xB9, 0x70, 0x74, 0x49, 0x09, 0x78, 0x01,
+ 0x70, 0x28, 0x78, 0x30, 0x70, 0x82, 0x48, 0x41,
+ 0x68, 0x01, 0x22, 0x12, 0x07, 0x11, 0x43, 0x41,
+ 0x60, 0x73, 0x48, 0x74, 0x49,
+ 0x00, 0x01, 0x44, 0x00, 0x80, 0x00, 0x78, 0x09,
+ 0x78, 0x42, 0x1C, 0x8A, 0x42, 0x08, 0xD2, 0x3A,
+ 0x78, 0x01, 0x2A, 0x25, 0xD0, 0x6A, 0x4B, 0x1A,
+ 0x68, 0x03, 0x24, 0x64, 0x07, 0x22, 0x43, 0x1A,
+ 0x60, 0x88, 0x42, 0x1E, 0xD1, 0xFF, 0x21, 0x01,
+ 0x98, 0xFC, 0xF7, 0x26, 0xFB, 0x6E, 0x49, 0x6D,
+ 0x4A, 0x09, 0x78, 0x0F, 0x20, 0x51, 0x5C, 0x6D,
+ 0x4A, 0x89, 0x00, 0x89, 0x18, 0x08, 0x60, 0x60,
+ 0x48, 0x01, 0x69, 0x02, 0x22, 0x91, 0x43, 0x01,
+ 0x61, 0x05, 0x20, 0xF9, 0xF7, 0xEC, 0xF9, 0x6D,
+ 0x48, 0x00, 0x78, 0x00, 0x28, 0x01, 0xD0, 0x02,
+ 0x28, 0x02, 0xD3, 0x6B, 0x49, 0x01, 0x20, 0x08,
+ 0x70, 0xFE, 0xBD, 0x57, 0x49, 0x08, 0x68, 0x8A,
+ 0x03, 0x10, 0x43, 0x08, 0x60, 0xFE, 0xBD, 0xF8,
+ 0xB5, 0x57, 0x49, 0x62, 0x4D, 0x08, 0x78, 0x5E,
+ 0x4F, 0x40, 0x1C, 0x08, 0x70, 0x63, 0x49, 0x28,
+ 0x78, 0x09, 0x68, 0x00, 0x01,
+ 0x00, 0x01, 0x45, 0x00, 0x80, 0x44, 0x18, 0x40,
+ 0x37, 0x38, 0x69, 0x61, 0x4E, 0x01, 0x28, 0x14,
+ 0xD1, 0xFB, 0xF7, 0xC3, 0xFF, 0x00, 0x09, 0x04,
+ 0xD0, 0x38, 0x46, 0x20, 0x30, 0x80, 0x79, 0x00,
+ 0x28, 0x0B, 0xD1, 0x30, 0x6A, 0x5B, 0x49, 0x00,
+ 0xB2, 0x0A, 0x68, 0x12, 0x18, 0x0A, 0x60, 0x79,
+ 0x69, 0x59, 0x4A, 0x50, 0x43, 0x41, 0x43, 0x09,
+ 0x14, 0x00, 0xE0, 0x00, 0x21, 0x57, 0x48, 0x58,
+ 0x4B, 0x00, 0x78, 0x0B, 0xE0, 0x82, 0x00, 0x92,
+ 0x19, 0x12, 0x68, 0x00, 0x27, 0x12, 0xB2, 0xDF,
+ 0x5F, 0x52, 0x1A, 0x7A, 0x43, 0x12, 0x13, 0x47,
+ 0x00, 0xE2, 0x53, 0x40, 0x1C, 0x51, 0x4A, 0x12,
+ 0x78, 0x90, 0x42, 0xEF, 0xD3, 0x28, 0x78, 0x00,
+ 0x21, 0x40, 0x1C, 0xC0, 0xB2, 0x34, 0x4C, 0x28,
+ 0x70, 0xC9, 0x43, 0xE1, 0x60, 0x37, 0x49, 0x09,
+ 0x78, 0x88, 0x42, 0x0F, 0xD2, 0x00, 0xF0, 0xD6,
+ 0xFB, 0x00, 0xF0, 0xC6, 0xFB,
+ 0x00, 0x01, 0x46, 0x00, 0x80, 0x28, 0x78, 0xFC,
+ 0xF7, 0x3E, 0xFB, 0x28, 0x78, 0xFC, 0xF7, 0x9E,
+ 0xFA, 0x20, 0x68, 0x03, 0x21, 0x49, 0x07, 0x08,
+ 0x43, 0x20, 0x60, 0xF8, 0xBD, 0x20, 0x69, 0x02,
+ 0x21, 0x88, 0x43, 0x20, 0x61, 0x05, 0x20, 0xF9,
+ 0xF7, 0x7E, 0xF9, 0x36, 0x49, 0x3E, 0x4B, 0x08,
+ 0x78, 0x00, 0x28, 0x0C, 0xD0, 0x02, 0x28, 0x0A,
+ 0xD2, 0x40, 0x1C, 0x08, 0x70, 0x18, 0x78, 0x01,
+ 0x28, 0x02, 0xD1, 0xFC, 0xF7, 0x71, 0xFC, 0xF8,
+ 0xBD, 0xFC, 0xF7, 0x3A, 0xFC, 0xF8, 0xBD, 0x37,
+ 0x4A, 0x14, 0x78, 0x01, 0x22, 0x03, 0x2C, 0x06,
+ 0xD1, 0x1B, 0x78, 0x01, 0x2B, 0x03, 0xD1, 0x00,
+ 0x28, 0xF2, 0xD0, 0x0A, 0x70, 0xF0, 0xE7, 0x28,
+ 0x48, 0x02, 0x70, 0x31, 0x48, 0x00, 0x68, 0x80,
+ 0x47, 0xF8, 0xBD, 0xF8, 0xB5, 0x12, 0x4C, 0x02,
+ 0x23, 0xE3, 0x60, 0x15, 0x49, 0x2D, 0x4D, 0x08,
+ 0x78, 0x2D, 0x68, 0x02, 0x01,
+ 0x00, 0x01, 0x47, 0x00, 0x80, 0x52, 0x19, 0x40,
+ 0x1C, 0x08, 0x70, 0x21, 0x4D, 0x2A, 0x4E, 0x00,
+ 0x20, 0x81, 0x00, 0x49, 0x19, 0x09, 0x68, 0x00,
+ 0x27, 0xF7, 0x5F, 0x09, 0xB2, 0x79, 0x43, 0x47,
+ 0x00, 0x09, 0x13, 0x40, 0x1C, 0xD1, 0x53, 0x08,
+ 0x28, 0xF2, 0xD3, 0x17, 0x49, 0x01, 0x20, 0x08,
+ 0x70, 0x20, 0x69, 0x98, 0x43, 0x20, 0x61, 0x05,
+ 0x20, 0x40, 0xE0, 0x00, 0x00, 0x73, 0x01, 0x00,
+ 0x20, 0x00, 0x00, 0x11, 0x40, 0x6D, 0x01, 0x00,
+ 0x20, 0x79, 0x01, 0x00, 0x20, 0x74, 0x01, 0x00,
+ 0x20, 0x77, 0x01, 0x00, 0x20, 0x7A, 0x01, 0x00,
+ 0x20, 0x7F, 0x01, 0x00, 0x20, 0x7E, 0x01, 0x00,
+ 0x20, 0x7D, 0x01, 0x00, 0x20, 0xC0, 0xE0, 0x00,
+ 0x00, 0x76, 0x01, 0x00, 0x20, 0x00, 0x04, 0x11,
+ 0x40, 0x88, 0xDF, 0x00, 0x00, 0x6E, 0x01, 0x00,
+ 0x20, 0x6F, 0x01, 0x00, 0x20, 0x72, 0x01, 0x00,
+ 0x20, 0x00, 0xED, 0x00, 0xE0,
+ 0x00, 0x01, 0x48, 0x00, 0x80, 0xA8, 0x02, 0x00,
+ 0x20, 0x81, 0x01, 0x00, 0x20, 0xB0, 0x01, 0x00,
+ 0x20, 0x00, 0x02, 0x11, 0x40, 0xA8, 0x01, 0x00,
+ 0x20, 0x3C, 0x0A, 0x00, 0x00, 0xA9, 0x02, 0x00,
+ 0x20, 0x94, 0x01, 0x00, 0x20, 0xAA, 0x02, 0x00,
+ 0x20, 0xAC, 0x02, 0x00, 0x20, 0xAB, 0x02, 0x00,
+ 0x20, 0xA0, 0x01, 0x00, 0x20, 0xB4, 0x01, 0x00,
+ 0x20, 0x96, 0x01, 0x00, 0x20, 0xF9, 0xF7, 0xF3,
+ 0xF8, 0xFF, 0x48, 0x00, 0x68, 0x80, 0x47, 0xF8,
+ 0xBD, 0xF0, 0xB5, 0xFE, 0x4A, 0x97, 0xB0, 0x02,
+ 0x20, 0xD0, 0x60, 0xFD, 0x49, 0x08, 0x78, 0x40,
+ 0x1C, 0xC0, 0xB2, 0x08, 0x70, 0x16, 0x90, 0xF9,
+ 0x48, 0x40, 0x30, 0x80, 0x69, 0x00, 0x01, 0x01,
+ 0xD5, 0xF8, 0x48, 0x00, 0xE0, 0xF8, 0x48, 0x0C,
+ 0x90, 0xF4, 0x48, 0x80, 0x68, 0xF9, 0x49, 0x00,
+ 0x0A, 0x0B, 0x90, 0xF6, 0x48, 0x05, 0x88, 0x00,
+ 0x20, 0x01, 0x90, 0xF5, 0x48,
+ 0x00, 0x01, 0x49, 0x00, 0x80, 0x00, 0x78, 0x15,
+ 0x90, 0x0F, 0x78, 0x01, 0x21, 0xB9, 0x40, 0x14,
+ 0x91, 0xF3, 0x49, 0x00, 0x28, 0x0E, 0x78, 0x0C,
+ 0xD0, 0x00, 0x24, 0x38, 0x46, 0x14, 0x99, 0x05,
+ 0xE0, 0x2A, 0x46, 0x0A, 0x42, 0x01, 0xD0, 0x64,
+ 0x1C, 0x49, 0x00, 0x40, 0x1C, 0xB0, 0x42, 0xF7,
+ 0xD3, 0x01, 0xE0, 0xEC, 0x48, 0x04, 0x78, 0xEC,
+ 0x48, 0x16, 0x99, 0x00, 0x78, 0x13, 0x90, 0xEB,
+ 0x48, 0x12, 0x90, 0x01, 0x29, 0x79, 0xD1, 0x00,
+ 0x20, 0x08, 0x90, 0x14, 0x98, 0x09, 0x90, 0x00,
+ 0x20, 0xBC, 0x46, 0x0E, 0x90, 0x25, 0xE0, 0x09,
+ 0x98, 0x05, 0x42, 0x1C, 0xD0, 0x00, 0x21, 0x08,
+ 0x46, 0x0C, 0xE0, 0x02, 0x46, 0x0E, 0x9B, 0x62,
+ 0x43, 0xD2, 0x18, 0x0C, 0x9B, 0x92, 0x00, 0x9A,
+ 0x58, 0x12, 0xB2, 0x00, 0x2A, 0x00, 0xDC, 0x52,
+ 0x42, 0x51, 0x18, 0x40, 0x1C, 0x0B, 0x9A, 0x90,
+ 0x42, 0xEF, 0xD3, 0x08, 0x98,
+ 0x00, 0x01, 0x4A, 0x00, 0x80, 0x88, 0x42, 0x03,
+ 0xDA, 0x08, 0x91, 0xD9, 0x49, 0x60, 0x46, 0x08,
+ 0x70, 0x0E, 0x98, 0x40, 0x1C, 0x0E, 0x90, 0x09,
+ 0x98, 0x40, 0x00, 0x09, 0x90, 0x60, 0x46, 0x40,
+ 0x1C, 0x84, 0x46, 0xB4, 0x45, 0xD7, 0xD3, 0x0B,
+ 0x99, 0x08, 0x98, 0x02, 0xF0, 0x6C, 0xFA, 0xD1,
+ 0x49, 0xC0, 0xB2, 0x08, 0x70, 0xD0, 0x49, 0x0A,
+ 0x68, 0xD0, 0x49, 0x09, 0x78, 0x8C, 0x46, 0xCB,
+ 0x49, 0x60, 0x39, 0x90, 0x42, 0x07, 0xDD, 0x0A,
+ 0x6B, 0x62, 0x45, 0x04, 0xD9, 0xCA, 0x4A, 0xCC,
+ 0x4B, 0x10, 0x60, 0x62, 0x46, 0x1A, 0x70, 0x62,
+ 0x46, 0xC8, 0x4B, 0x52, 0x1C, 0xD2, 0xB2, 0x1A,
+ 0x70, 0x0B, 0x6B, 0x93, 0x42, 0x05, 0xD9, 0xB7,
+ 0x48, 0x01, 0x69, 0x02, 0x22, 0x91, 0x43, 0x01,
+ 0x61, 0x0D, 0xE0, 0x0B, 0x6B, 0x93, 0x42, 0x10,
+ 0xD1, 0x09, 0x6B, 0xC1, 0x4A, 0x49, 0x1E, 0x12,
+ 0x78, 0x91, 0x42, 0x0A, 0xD0,
+ 0x00, 0x01, 0x4B, 0x00, 0x80, 0xAF, 0x49, 0x08,
+ 0x69, 0x02, 0x22, 0x90, 0x43, 0x08, 0x61, 0x05,
+ 0x20, 0xF9, 0xF7, 0x49, 0xF8, 0xB4, 0x48, 0x00,
+ 0x78, 0xA7, 0xE0, 0x12, 0x99, 0x8A, 0x88, 0xB9,
+ 0x4B, 0x82, 0x42, 0x19, 0x68, 0x7E, 0xD2, 0x88,
+ 0x42, 0x7C, 0xDD, 0x18, 0x60, 0xB6, 0x49, 0x01,
+ 0x20, 0x08, 0x70, 0x00, 0x20, 0x06, 0x90, 0x00,
+ 0x90, 0x72, 0xE0, 0xAF, 0xE0, 0x14, 0x98, 0x39,
+ 0x46, 0x84, 0x46, 0x00, 0x20, 0x07, 0x90, 0x0E,
+ 0x90, 0x0D, 0x98, 0x02, 0xAB, 0x60, 0x43, 0x11,
+ 0x90, 0x1A, 0xE0, 0x60, 0x46, 0x05, 0x42, 0x13,
+ 0xD0, 0x0E, 0x9A, 0x11, 0x98, 0x80, 0x18, 0x0C,
+ 0x9A, 0x80, 0x00, 0x10, 0x58, 0x4A, 0x00, 0x80,
+ 0x00, 0x00, 0xB2, 0x98, 0x52, 0x42, 0x42, 0x00,
+ 0x28, 0x00, 0xDB, 0x02, 0x46, 0x07, 0x98, 0x10,
+ 0x18, 0x07, 0x90, 0x0E, 0x98, 0x40, 0x1C, 0x0E,
+ 0x90, 0x60, 0x46, 0x40, 0x00,
+ 0x00, 0x01, 0x4C, 0x00, 0x80, 0x84, 0x46, 0x49,
+ 0x1C, 0xB1, 0x42, 0xE2, 0xD3, 0x9F, 0x49, 0xA0,
+ 0x00, 0x08, 0x58, 0x07, 0x99, 0x48, 0x43, 0x00,
+ 0x12, 0x07, 0x90, 0x00, 0x20, 0x07, 0x9A, 0x0A,
+ 0x90, 0x08, 0x90, 0x52, 0x42, 0x38, 0x46, 0x94,
+ 0x46, 0x14, 0x99, 0x13, 0xE0, 0x2A, 0x46, 0x0A,
+ 0x42, 0x0E, 0xD0, 0x42, 0x00, 0x02, 0xAB, 0x9A,
+ 0x5E, 0x62, 0x45, 0x09, 0xDB, 0x07, 0x9B, 0x9A,
+ 0x42, 0x06, 0xDC, 0x0A, 0x9B, 0xD2, 0x18, 0x12,
+ 0xB2, 0x0A, 0x92, 0x08, 0x9A, 0x52, 0x1C, 0x08,
+ 0x92, 0x49, 0x00, 0x40, 0x1C, 0xB0, 0x42, 0xE9,
+ 0xD3, 0x08, 0x98, 0x8C, 0x49, 0x80, 0x00, 0x08,
+ 0x58, 0x0A, 0x99, 0x02, 0xAA, 0x48, 0x43, 0x82,
+ 0x49, 0x00, 0x12, 0x09, 0x78, 0x49, 0x00, 0x51,
+ 0x5A, 0x08, 0x1A, 0x01, 0xB2, 0x48, 0x42, 0x00,
+ 0x29, 0x00, 0xDB, 0x08, 0x46, 0xFF, 0x22, 0x00,
+ 0xB2, 0xFD, 0x32, 0x90, 0x42,
+ 0x00, 0x01, 0x4D, 0x00, 0x80, 0x00, 0xD9, 0x10,
+ 0x46, 0x01, 0x9A, 0x82, 0x42, 0x00, 0xDA, 0x01,
+ 0x90, 0x00, 0x9A, 0x10, 0x18, 0x00, 0x90, 0x06,
+ 0x98, 0x40, 0x18, 0x06, 0x90, 0x0D, 0x98, 0x40,
+ 0x1C, 0x0D, 0x90, 0x00, 0xE0, 0x0E, 0xE0, 0x0B,
+ 0x99, 0x88, 0x42, 0x87, 0xD3, 0x78, 0x48, 0x01,
+ 0x99, 0x41, 0x60, 0x00, 0x99, 0x81, 0x60, 0x06,
+ 0x98, 0x00, 0x28, 0x00, 0xDA, 0x40, 0x42, 0x75,
+ 0x49, 0x08, 0x60, 0xFD, 0xE0, 0x5F, 0x4A, 0x10,
+ 0x69, 0x02, 0x23, 0x98, 0x43, 0x10, 0x61, 0x15,
+ 0x98, 0x61, 0x4A, 0x00, 0x28, 0x0C, 0xD0, 0x02,
+ 0x28, 0x0A, 0xD2, 0x40, 0x1C, 0x10, 0x70, 0x67,
+ 0x49, 0x00, 0x20, 0x08, 0x70, 0x64, 0x49, 0x08,
+ 0x60, 0x13, 0x98, 0xFC, 0xF7, 0x38, 0xFB, 0x6A,
+ 0xE1, 0x00, 0x29, 0x0F, 0xD1, 0x68, 0x49, 0x00,
+ 0x20, 0x08, 0x70, 0x68, 0x49, 0x64, 0x22, 0x08,
+ 0x70, 0x67, 0x49, 0x08, 0x70,
+ 0x00, 0x01, 0x4E, 0x00, 0x80, 0x0B, 0x99, 0x61,
+ 0x43, 0x66, 0x4C, 0x20, 0x88, 0x50, 0x43, 0x02,
+ 0xF0, 0x7A, 0xF9, 0x20, 0x80, 0x64, 0x49, 0x01,
+ 0x20, 0x08, 0x70, 0x54, 0xE1, 0x00, 0x20, 0x06,
+ 0x90, 0x00, 0x90, 0x79, 0xE0, 0x14, 0x98, 0x39,
+ 0x46, 0x84, 0x46, 0x00, 0x20, 0x07, 0x90, 0x0E,
+ 0x90, 0x26, 0xE0, 0x60, 0x46, 0x05, 0x42, 0x1F,
+ 0xD0, 0x0D, 0x98, 0x0E, 0x9A, 0x60, 0x43, 0x80,
+ 0x18, 0x0C, 0x9A, 0x80, 0x00, 0x10, 0x58, 0x59,
+ 0x4B, 0x80, 0x00, 0x00, 0xB2, 0x02, 0x46, 0xFF,
+ 0x32, 0x91, 0x32, 0x9A, 0x42, 0x03, 0xD3, 0x53,
+ 0x4B, 0x1A, 0x88, 0x52, 0x1C, 0x1A, 0x80, 0x4A,
+ 0x00, 0x02, 0xAB, 0x98, 0x52, 0x42, 0x42, 0x00,
+ 0x28, 0x00, 0xDB, 0x02, 0x46, 0x07, 0x98, 0x10,
+ 0x18, 0x07, 0x90, 0x0E, 0x98, 0x40, 0x1C, 0x0E,
+ 0x90, 0x60, 0x46, 0x40, 0x00, 0x84, 0x46, 0x49,
+ 0x1C, 0xB1, 0x42, 0xD6, 0xD3,
+ 0x00, 0x01, 0x4F, 0x00, 0x80, 0x41, 0x49, 0xA0,
+ 0x00, 0x08, 0x58, 0x07, 0x99, 0x48, 0x43, 0x00,
+ 0x12, 0x07, 0x90, 0x00, 0x20, 0x07, 0x9A, 0x0A,
+ 0x90, 0x08, 0x90, 0x52, 0x42, 0x38, 0x46, 0x94,
+ 0x46, 0x14, 0x99, 0x13, 0xE0, 0x2A, 0x46, 0x0A,
+ 0x42, 0x0E, 0xD0, 0x42, 0x00, 0x02, 0xAB, 0x9A,
+ 0x5E, 0x62, 0x45, 0x09, 0xDB, 0x07, 0x9B, 0x9A,
+ 0x42, 0x06, 0xDC, 0x0A, 0x9B, 0xD2, 0x18, 0x12,
+ 0xB2, 0x0A, 0x92, 0x08, 0x9A, 0x52, 0x1C, 0x08,
+ 0x92, 0x49, 0x00, 0x40, 0x1C, 0xB0, 0x42, 0xE9,
+ 0xD3, 0x08, 0x98, 0x2E, 0x49, 0x80, 0x00, 0x08,
+ 0x58, 0x0A, 0x99, 0x02, 0xAA, 0x48, 0x43, 0x24,
+ 0x49, 0x00, 0x12, 0x09, 0x78, 0x49, 0x00, 0x51,
+ 0x5A, 0x08, 0x1A, 0x01, 0xB2, 0x48, 0x42, 0x00,
+ 0x29, 0x00, 0xDB, 0x08, 0x46, 0xFF, 0x22, 0x00,
+ 0xB2, 0xFD, 0x32, 0x90, 0x42, 0x00, 0xD9, 0x10,
+ 0x46, 0x01, 0x9A, 0x82, 0x42,
+ 0x00, 0x01, 0x50, 0x00, 0x80, 0x00, 0xDA, 0x01,
+ 0x90, 0x06, 0x9A, 0x51, 0x18, 0x06, 0x91, 0x00,
+ 0x99, 0x08, 0x18, 0x00, 0x90, 0x0D, 0x98, 0x40,
+ 0x1C, 0x0B, 0x99, 0x0D, 0x90, 0x88, 0x42, 0x81,
+ 0xD3, 0x1B, 0x49, 0x01, 0x9A, 0x48, 0x68, 0x80,
+ 0x18, 0x48, 0x60, 0x10, 0x90, 0x88, 0x68, 0x00,
+ 0x9A, 0x86, 0x18, 0x8E, 0x60, 0x06, 0x98, 0x00,
+ 0x28, 0x00, 0xDA, 0x40, 0x42, 0x15, 0x49, 0x37,
+ 0xE0, 0xA4, 0x01, 0x00, 0x20, 0x00, 0x00, 0x11,
+ 0x40, 0x77, 0x01, 0x00, 0x20, 0x00, 0x12, 0x11,
+ 0x40, 0x00, 0x10, 0x11, 0x40, 0x9C, 0x01, 0x00,
+ 0x20, 0xA8, 0x02, 0x00, 0x20, 0xA9, 0x02, 0x00,
+ 0x20, 0xAA, 0x02, 0x00, 0x20, 0x82, 0x01, 0x00,
+ 0x20, 0x7A, 0x01, 0x00, 0x20, 0xE8, 0xDF, 0x00,
+ 0x00, 0xBC, 0x01, 0x00, 0x20, 0x89, 0x01, 0x00,
+ 0x20, 0xB8, 0x01, 0x00, 0x20, 0x91, 0x01, 0x00,
+ 0x20, 0x92, 0x01, 0x00, 0x20,
+ 0x00, 0x01, 0x51, 0x00, 0x80, 0xB0, 0x02, 0x00,
+ 0x20, 0x8A, 0x01, 0x00, 0x20, 0x38, 0xCF, 0x00,
+ 0x00, 0x9C, 0x02, 0x00, 0x20, 0xA8, 0x01, 0x00,
+ 0x20, 0x8E, 0x01, 0x00, 0x20, 0x8F, 0x01, 0x00,
+ 0x20, 0x90, 0x01, 0x00, 0x20, 0x9E, 0x01, 0x00,
+ 0x20, 0x81, 0x01, 0x00, 0x20, 0x21, 0x03, 0x00,
+ 0x00, 0x0A, 0x68, 0x87, 0x18, 0x0F, 0x60, 0x16,
+ 0x98, 0x13, 0x99, 0x40, 0x1C, 0x88, 0x42, 0x04,
+ 0xD2, 0x51, 0x49, 0x08, 0x68, 0x03, 0x22, 0x52,
+ 0x07, 0x7B, 0xE0, 0x16, 0x98, 0x88, 0x42, 0x75,
+ 0xD1, 0x01, 0x46, 0x10, 0x98, 0x02, 0xF0, 0xA1,
+ 0xF8, 0x80, 0x05, 0x05, 0x0E, 0x4B, 0x48, 0x05,
+ 0x70, 0x64, 0x20, 0x78, 0x43, 0x0F, 0x95, 0x0B,
+ 0x99, 0x02, 0xF0, 0x8D, 0xF8, 0x10, 0x99, 0x02,
+ 0xF0, 0x8A, 0xF8, 0xC0, 0xB2, 0x46, 0x49, 0x07,
+ 0x46, 0x08, 0x70, 0x30, 0x46, 0x64, 0x21, 0x48,
+ 0x43, 0x0B, 0x99, 0x02, 0xF0,
+ 0x00, 0x01, 0x52, 0x00, 0x80, 0x80, 0xF8, 0x10,
+ 0x99, 0x02, 0xF0, 0x7D, 0xF8, 0x41, 0x49, 0x2B,
+ 0x02, 0x08, 0x70, 0x05, 0x22, 0x40, 0x4D, 0x00,
+ 0x20, 0x12, 0x99, 0x09, 0x7A, 0x86, 0x00, 0xAE,
+ 0x59, 0x71, 0x43, 0x99, 0x42, 0x01, 0xD2, 0x02,
+ 0xB2, 0x02, 0xE0, 0x40, 0x1C, 0x05, 0x28, 0xF3,
+ 0xD3, 0x12, 0x98, 0x40, 0x7A, 0x91, 0x00, 0x38,
+ 0x4A, 0x38, 0x4E, 0x14, 0x32, 0x51, 0x58, 0x48,
+ 0x43, 0x00, 0x0A, 0x01, 0x25, 0x35, 0x70, 0x12,
+ 0x99, 0xC9, 0x7A, 0xCA, 0x07, 0x03, 0x21, 0x00,
+ 0x2A, 0x02, 0xD0, 0x87, 0x42, 0x0A, 0xD9, 0x08,
+ 0xE0, 0x12, 0x98, 0x40, 0x7A, 0xB8, 0x42, 0x05,
+ 0xD2, 0x12, 0x98, 0x00, 0x7A, 0x0F, 0x9A, 0x90,
+ 0x42, 0x00, 0xD2, 0x31, 0x70, 0x16, 0x99, 0x0B,
+ 0x98, 0x64, 0x22, 0x41, 0x43, 0x61, 0x43, 0x2A,
+ 0x4C, 0x20, 0x88, 0x50, 0x43, 0x02, 0xF0, 0x43,
+ 0xF8, 0x21, 0x4A, 0x20, 0x80,
+ 0x00, 0x01, 0x53, 0x00, 0x80, 0x11, 0x69, 0x02,
+ 0x20, 0x81, 0x43, 0x11, 0x61, 0x05, 0x20, 0xF8,
+ 0xF7, 0x4A, 0xFE, 0x30, 0x78, 0x80, 0x07, 0x0E,
+ 0xD4, 0x22, 0x49, 0x08, 0x78, 0x00, 0x28, 0x0A,
+ 0xD0, 0x02, 0x28, 0x08, 0xD2, 0x40, 0x1C, 0x08,
+ 0x70, 0x1F, 0x49, 0x00, 0x20, 0x08, 0x70, 0x1F,
+ 0x49, 0x08, 0x60, 0xEF, 0xE5, 0x02, 0xE0, 0x1E,
+ 0x48, 0x05, 0x70, 0x04, 0xE0, 0x12, 0x49, 0x08,
+ 0x68, 0x8A, 0x03, 0x10, 0x43, 0x08, 0x60, 0x1A,
+ 0x48, 0x00, 0x78, 0x01, 0x28, 0x19, 0xD1, 0x12,
+ 0x98, 0x00, 0x7C, 0x00, 0x28, 0x15, 0xD0, 0x12,
+ 0x98, 0x00, 0x7B, 0x40, 0x07, 0x40, 0x0F, 0x05,
+ 0x28, 0x00, 0xD9, 0x00, 0x20, 0x08, 0x49, 0xC0,
+ 0x31, 0x0A, 0x69, 0x12, 0x4B, 0x1A, 0x40, 0x0A,
+ 0x61, 0x0A, 0x69, 0x11, 0x4B, 0x80, 0x00, 0x18,
+ 0x58, 0x0E, 0x4B, 0xDB, 0x43, 0x18, 0x40, 0x02,
+ 0x43, 0x0A, 0x61, 0x17, 0xB0,
+ 0x00, 0x01, 0x54, 0x00, 0x80, 0xF0, 0xBD, 0x00,
+ 0x00, 0x00, 0x00, 0x11, 0x40, 0x8E, 0x01, 0x00,
+ 0x20, 0x8F, 0x01, 0x00, 0x20, 0x90, 0x01, 0x00,
+ 0x20, 0x5C, 0xCF, 0x00, 0x00, 0x8A, 0x01, 0x00,
+ 0x20, 0x9E, 0x01, 0x00, 0x20, 0xA8, 0x02, 0x00,
+ 0x20, 0x91, 0x01, 0x00, 0x20, 0xB8, 0x01, 0x00,
+ 0x20, 0x81, 0x01, 0x00, 0x20, 0xFF, 0xE0, 0xE3,
+ 0xF1, 0xD8, 0xCD, 0x00, 0x00, 0x27, 0x49, 0x01,
+ 0x20, 0x08, 0x70, 0x70, 0x47, 0x25, 0x49, 0x00,
+ 0x20, 0x08, 0x70, 0x70, 0x47, 0x23, 0x48, 0x00,
+ 0x78, 0x00, 0x28, 0x00, 0xD0, 0x01, 0x20, 0x70,
+ 0x47, 0x10, 0xB5, 0x20, 0x49, 0x00, 0x23, 0x08,
+ 0x78, 0x08, 0x22, 0x00, 0x28, 0x07, 0xD0, 0x04,
+ 0x24, 0x01, 0x28, 0x02, 0xD1, 0x4B, 0x70, 0x8C,
+ 0x70, 0x03, 0xE0, 0x4C, 0x70, 0x00, 0xE0, 0x4B,
+ 0x70, 0x8A, 0x70, 0x00, 0xF0, 0x23, 0xF8, 0x02,
+ 0x04, 0x17, 0x48, 0x01, 0x68,
+ 0x00, 0x01, 0x55, 0x00, 0x80, 0xFF, 0x23, 0x1B,
+ 0x04, 0x99, 0x43, 0x0A, 0x43, 0x02, 0x60, 0x10,
+ 0xBD, 0x10, 0xB5, 0x04, 0x46, 0x00, 0xF0, 0x16,
+ 0xF8, 0x20, 0x40, 0x02, 0x04, 0x10, 0x48, 0x01,
+ 0x68, 0xFF, 0x23, 0x1B, 0x04, 0x99, 0x43, 0x0A,
+ 0x43, 0x02, 0x60, 0x10, 0xBD, 0x10, 0xB5, 0x0D,
+ 0x49, 0x09, 0x78, 0x08, 0x18, 0x16, 0x21, 0x48,
+ 0x43, 0x0B, 0x49, 0x0C, 0x5A, 0x00, 0xF0, 0x02,
+ 0xF8, 0x20, 0x40, 0x10, 0xBD, 0x05, 0x48, 0x00,
+ 0x78, 0x00, 0x28, 0x05, 0xD0, 0x01, 0x28, 0x01,
+ 0xD1, 0x0F, 0x20, 0x70, 0x47, 0xF0, 0x20, 0x70,
+ 0x47, 0xFF, 0x20, 0x70, 0x47, 0xA8, 0x02, 0x00,
+ 0x20, 0x00, 0x00, 0x11, 0x40, 0x70, 0x01, 0x00,
+ 0x20, 0x2C, 0xE1, 0x00, 0x00, 0xF9, 0x49, 0x00,
+ 0x20, 0x88, 0x80, 0x08, 0x81, 0xC8, 0x80, 0x48,
+ 0x81, 0x88, 0x70, 0x70, 0x47, 0xF6, 0xE7, 0x10,
+ 0xB5, 0xF4, 0x4B, 0xD9, 0x88,
+ 0x00, 0x01, 0x56, 0x00, 0x80, 0x9A, 0x88, 0x11,
+ 0x43, 0x00, 0x20, 0xCC, 0x07, 0x05, 0xD1, 0x01,
+ 0x21, 0x81, 0x40, 0x11, 0x43, 0x99, 0x80, 0xC0,
+ 0xB2, 0x10, 0xBD, 0x40, 0x1C, 0x49, 0x08, 0x0E,
+ 0x28, 0xF3, 0xD9, 0x1E, 0x20, 0x10, 0xBD, 0xFF,
+ 0xB5, 0x87, 0xB0, 0x10, 0x9C, 0x22, 0x46, 0x79,
+ 0x32, 0x01, 0x92, 0x0B, 0x32, 0x94, 0x46, 0x01,
+ 0x28, 0x06, 0xD1, 0x01, 0x29, 0x04, 0xD1, 0x09,
+ 0x99, 0x00, 0x20, 0x08, 0x70, 0x0B, 0xB0, 0xF0,
+ 0xBD, 0x00, 0x22, 0x22, 0xE0, 0x04, 0x9B, 0x00,
+ 0x22, 0xE1, 0x4F, 0x9B, 0x00, 0x0A, 0xE0, 0x2C,
+ 0x26, 0x15, 0x46, 0x75, 0x43, 0x0A, 0x9E, 0xAD,
+ 0x19, 0xED, 0x58, 0xBD, 0x42, 0x00, 0xDA, 0x2F,
+ 0x46, 0x52, 0x1C, 0xD2, 0xB2, 0x82, 0x42, 0xF2,
+ 0xD3, 0x00, 0x22, 0x09, 0xE0, 0x2C, 0x26, 0x15,
+ 0x46, 0x75, 0x43, 0x0A, 0x9E, 0xAE, 0x19, 0xF5,
+ 0x58, 0xED, 0x1B, 0x52, 0x1C,
+ 0x00, 0x01, 0x57, 0x00, 0x80, 0xF5, 0x50, 0xD2,
+ 0xB2, 0x82, 0x42, 0xF3, 0xD3, 0x04, 0x9A, 0x52,
+ 0x1C, 0xD2, 0xB2, 0x04, 0x92, 0x8A, 0x42, 0xD9,
+ 0xD3, 0x00, 0x22, 0x34, 0xE0, 0x09, 0x9D, 0xFF,
+ 0x23, 0xAB, 0x54, 0x00, 0x23, 0x2B, 0xE0, 0x2C,
+ 0x25, 0x0A, 0x9E, 0x5D, 0x43, 0xAD, 0x19, 0x96,
+ 0x00, 0xAD, 0x59, 0x00, 0x2D, 0x1C, 0xD1, 0x0B,
+ 0x25, 0x5D, 0x43, 0x2D, 0x19, 0x00, 0x26, 0x06,
+ 0x95, 0xAE, 0x54, 0x35, 0x46, 0x01, 0x27, 0x06,
+ 0xE0, 0x09, 0x9E, 0x76, 0x57, 0x9E, 0x42, 0x00,
+ 0xD1, 0x00, 0x27, 0x6D, 0x1C, 0xED, 0xB2, 0x95,
+ 0x42, 0x02, 0xD2, 0x01, 0x2F, 0xF4, 0xD0, 0x0C,
+ 0xE0, 0x01, 0x2F, 0x0A, 0xD1, 0x09, 0x9D, 0xAB,
+ 0x54, 0x06, 0x9E, 0x01, 0x25, 0xB5, 0x54, 0x04,
+ 0xE0, 0x0B, 0x26, 0xFF, 0x25, 0x5E, 0x43, 0x36,
+ 0x19, 0xF8, 0xE7, 0x5B, 0x1C, 0xDB, 0xB2, 0x83,
+ 0x42, 0xD1, 0xD3, 0x52, 0x1C,
+ 0x00, 0x01, 0x58, 0x00, 0x80, 0xD2, 0xB2, 0x8A,
+ 0x42, 0xC8, 0xD3, 0x2D, 0xE1, 0x00, 0x22, 0x04,
+ 0xE0, 0x01, 0x9B, 0x00, 0x25, 0x9D, 0x54, 0x52,
+ 0x1C, 0xD2, 0xB2, 0x82, 0x42, 0xF8, 0xD3, 0x00,
+ 0x22, 0x08, 0xE0, 0x09, 0x9B, 0x9B, 0x56, 0x5B,
+ 0x1C, 0x00, 0xD0, 0x01, 0x23, 0x65, 0x46, 0xAB,
+ 0x54, 0x52, 0x1C, 0xD2, 0xB2, 0x8A, 0x42, 0xF4,
+ 0xD3, 0x00, 0x22, 0xA6, 0x4B, 0xD2, 0x43, 0x1A,
+ 0x70, 0xC9, 0xE0, 0x00, 0x22, 0x13, 0x46, 0xA3,
+ 0x4F, 0x00, 0x92, 0x1F, 0xE0, 0x01, 0x9A, 0xD2,
+ 0x5C, 0x01, 0x2A, 0x19, 0xD0, 0x0B, 0x26, 0x1D,
+ 0x46, 0x75, 0x43, 0x00, 0x22, 0x2D, 0x19, 0x5E,
+ 0xB2, 0x05, 0x95, 0x0F, 0xE0, 0x65, 0x46, 0xAD,
+ 0x5C, 0x01, 0x2D, 0x09, 0xD0, 0x05, 0x9D, 0xAD,
+ 0x5C, 0x00, 0x2D, 0x05, 0xD1, 0x01, 0x25, 0x00,
+ 0x95, 0x96, 0x4D, 0x3E, 0x70, 0x6D, 0x1C, 0x2A,
+ 0x70, 0x52, 0x1C, 0xD2, 0xB2,
+ 0x00, 0x01, 0x59, 0x00, 0x80, 0x8A, 0x42, 0xED,
+ 0xD3, 0x5B, 0x1C, 0xDB, 0xB2, 0x83, 0x42, 0xDD,
+ 0xD3, 0x00, 0x9A, 0x52, 0xB2, 0x02, 0x92, 0x00,
+ 0x2A, 0x62, 0xD1, 0x8F, 0x4A, 0x03, 0x92, 0x00,
+ 0x22, 0x1A, 0xE0, 0x01, 0x9A, 0xD2, 0x5D, 0x01,
+ 0x2A, 0x14, 0xD0, 0x3B, 0x46, 0x2C, 0x25, 0x6B,
+ 0x43, 0x0A, 0x9D, 0x00, 0x22, 0x5E, 0x19, 0x0B,
+ 0xE0, 0x63, 0x46, 0x9B, 0x5C, 0x01, 0x2B, 0x05,
+ 0xD0, 0x93, 0x00, 0xF3, 0x58, 0x03, 0x9D, 0xAB,
+ 0x42, 0x00, 0xDA, 0x03, 0x93, 0x52, 0x1C, 0xD2,
+ 0xB2, 0x8A, 0x42, 0xF1, 0xD3, 0x7A, 0x1C, 0xD2,
+ 0xB2, 0x17, 0x46, 0x82, 0x42, 0xE1, 0xD3, 0x00,
+ 0x23, 0x3B, 0xE0, 0x00, 0x22, 0x35, 0xE0, 0x65,
+ 0x46, 0xAD, 0x5C, 0x01, 0x2D, 0x15, 0xD1, 0x01,
+ 0x9D, 0xED, 0x5C, 0x01, 0x2D, 0x11, 0xD1, 0x2C,
+ 0x25, 0x0A, 0x9E, 0x5D, 0x43, 0xAE, 0x19, 0x95,
+ 0x00, 0xAE, 0x46, 0x37, 0x46,
+ 0x00, 0x01, 0x5A, 0x00, 0x80, 0x75, 0x59, 0x03,
+ 0x9E, 0xAD, 0x19, 0x3E, 0x46, 0x77, 0x46, 0xF5,
+ 0x51, 0x0B, 0x26, 0xFF, 0x25, 0x5E, 0x43, 0x36,
+ 0x19, 0xB5, 0x54, 0x65, 0x46, 0xAD, 0x5C, 0x00,
+ 0x2D, 0x15, 0xD1, 0x01, 0x9D, 0xED, 0x5C, 0x00,
+ 0x2D, 0x11, 0xD1, 0x2C, 0x25, 0x0A, 0x9E, 0x5D,
+ 0x43, 0xAE, 0x19, 0x95, 0x00, 0xAE, 0x46, 0x37,
+ 0x46, 0x75, 0x59, 0x03, 0x9E, 0xAD, 0x1B, 0x3E,
+ 0x46, 0x77, 0x46, 0xF5, 0x51, 0x03, 0xD1, 0x0B,
+ 0x26, 0x5E, 0x43, 0x36, 0x19, 0xB5, 0x54, 0x52,
+ 0x1C, 0xD2, 0xB2, 0x8A, 0x42, 0xC7, 0xD3, 0x5B,
+ 0x1C, 0xDB, 0xB2, 0x83, 0x42, 0xC1, 0xD3, 0x70,
+ 0xE7, 0x00, 0x22, 0x5C, 0x4E, 0x53, 0x1E, 0xB5,
+ 0x56, 0x0B, 0x26, 0x75, 0x43, 0x59, 0x4E, 0x2F,
+ 0x19, 0x76, 0x1C, 0xB5, 0x56, 0x0B, 0xE0, 0x66,
+ 0x46, 0xB6, 0x5C, 0x00, 0x2E, 0x05, 0xD0, 0xAA,
+ 0x42, 0x03, 0xD0, 0xBE, 0x5C,
+ 0x00, 0x01, 0x5B, 0x00, 0x80, 0x01, 0x2E, 0x00,
+ 0xD1, 0x53, 0xB2, 0x52, 0x1C, 0xD2, 0xB2, 0x8A,
+ 0x42, 0x02, 0xD2, 0x5E, 0x1C, 0xEF, 0xD0, 0x10,
+ 0xE0, 0x5A, 0x1C, 0x0E, 0xD1, 0x02, 0x9A, 0x01,
+ 0x2A, 0xDD, 0xD1, 0x4C, 0x4E, 0x00, 0x23, 0xF3,
+ 0x56, 0x0B, 0x25, 0x6B, 0x43, 0x02, 0x22, 0x1B,
+ 0x19, 0x01, 0x25, 0x75, 0x57, 0x5A, 0x55, 0x35,
+ 0x46, 0x0F, 0xE0, 0x02, 0x22, 0x7A, 0x55, 0x00,
+ 0x25, 0x62, 0x46, 0xD5, 0x54, 0x43, 0x4D, 0x00,
+ 0x26, 0xAE, 0x57, 0x01, 0x9A, 0x01, 0x23, 0x93,
+ 0x55, 0x9A, 0x1E, 0x2B, 0x46, 0x1A, 0x70, 0x5A,
+ 0x70, 0x33, 0xE7, 0x00, 0x22, 0xAA, 0x56, 0x0B,
+ 0x23, 0x5A, 0x43, 0x01, 0x23, 0xEB, 0x56, 0x12,
+ 0x19, 0xD6, 0x56, 0x02, 0x2E, 0x23, 0xD1, 0x00,
+ 0x27, 0x0E, 0xE0, 0x0B, 0x26, 0x7E, 0x43, 0x36,
+ 0x19, 0xF6, 0x5C, 0x01, 0x2E, 0x06, 0xD1, 0xD6,
+ 0x54, 0xAE, 0x57, 0x09, 0x9B,
+ 0x00, 0x01, 0x5C, 0x00, 0x80, 0x2A, 0x78, 0x9A,
+ 0x55, 0x2F, 0x70, 0x03, 0xE0, 0x7F, 0x1C, 0xFF,
+ 0xB2, 0x87, 0x42, 0xEE, 0xD3, 0x87, 0x42, 0xE0,
+ 0xD1, 0x2A, 0x46, 0x00, 0x25, 0x55, 0x57, 0x0B,
+ 0x26, 0x01, 0x23, 0x75, 0x43, 0xD6, 0x56, 0x2D,
+ 0x19, 0xAB, 0x55, 0x01, 0x26, 0x96, 0x57, 0x09,
+ 0x9D, 0x13, 0x78, 0xAB, 0x55, 0x18, 0xE0, 0x01,
+ 0x2E, 0xCF, 0xD1, 0x00, 0x26, 0x07, 0xE0, 0x97,
+ 0x5D, 0x02, 0x2F, 0x02, 0xD1, 0xD7, 0x54, 0x6E,
+ 0x70, 0x03, 0xE0, 0x76, 0x1C, 0xF6, 0xB2, 0x8E,
+ 0x42, 0xF5, 0xD3, 0x8E, 0x42, 0xC1, 0xD1, 0x00,
+ 0x22, 0xAA, 0x56, 0x0B, 0x26, 0x72, 0x43, 0x02,
+ 0x23, 0x12, 0x19, 0x01, 0x26, 0xAE, 0x57, 0x93,
+ 0x55, 0x00, 0x23, 0x1A, 0x46, 0x06, 0xE0, 0x09,
+ 0x9D, 0xAD, 0x56, 0x6D, 0x1C, 0x00, 0xD0, 0x5B,
+ 0x1C, 0x52, 0x1C, 0xD2, 0xB2, 0x8A, 0x42, 0xF6,
+ 0xD3, 0x8B, 0x42, 0x00, 0xD2,
+ 0x00, 0x01, 0x5D, 0x00, 0x80, 0xC2, 0xE6, 0x5D,
+ 0xE6, 0xFF, 0xB5, 0x8C, 0x46, 0x9E, 0x46, 0x00,
+ 0x25, 0x1C, 0xE0, 0x29, 0x46, 0x2C, 0x23, 0x59,
+ 0x43, 0x09, 0x9B, 0x00, 0x20, 0x74, 0x46, 0xCB,
+ 0x18, 0x0F, 0xE0, 0x51, 0x88, 0x66, 0x88, 0x97,
+ 0x88, 0x89, 0x1B, 0x0E, 0xB2, 0xA1, 0x88, 0x76,
+ 0x43, 0x79, 0x1A, 0x09, 0xB2, 0x49, 0x43, 0x71,
+ 0x18, 0x86, 0x00, 0x40, 0x1C, 0x99, 0x51, 0xC0,
+ 0xB2, 0x0E, 0x34, 0x84, 0x45, 0xED, 0xD8, 0x6D,
+ 0x1C, 0xED, 0xB2, 0x0E, 0x32, 0x00, 0x98, 0xA8,
+ 0x42, 0xDF, 0xD8, 0xFF, 0xBD, 0xB4, 0x02, 0x00,
+ 0x20, 0xFF, 0xFF, 0xFF, 0x7F, 0xF0, 0xB5, 0x05,
+ 0x46, 0x9F, 0x48, 0x89, 0xB0, 0x80, 0x68, 0x9F,
+ 0x4A, 0x02, 0x90, 0x9F, 0x4B, 0x11, 0x78, 0x98,
+ 0x78, 0x0C, 0x46, 0x04, 0x43, 0x7E, 0xD0, 0x2C,
+ 0x46, 0xFF, 0x34, 0xE5, 0x34, 0x26, 0x46, 0x0B,
+ 0x36, 0x05, 0x96, 0x0B, 0x36,
+ 0x00, 0x01, 0x5E, 0x00, 0x80, 0x03, 0x96, 0x00,
+ 0x26, 0x9E, 0x80, 0x1E, 0x81, 0x06, 0x91, 0x31,
+ 0x46, 0x0B, 0x27, 0x0E, 0x26, 0x0A, 0x46, 0x72,
+ 0x43, 0x94, 0x4E, 0x1E, 0x23, 0x92, 0x19, 0xD3,
+ 0x72, 0x05, 0x9A, 0x57, 0x54, 0x49, 0x1C, 0xC9,
+ 0xB2, 0x0B, 0x29, 0xF2, 0xD3, 0x01, 0x28, 0x06,
+ 0xD1, 0x06, 0x99, 0x01, 0x29, 0x05, 0xD1, 0x05,
+ 0x99, 0x00, 0x20, 0x08, 0x70, 0x37, 0xE0, 0x00,
+ 0x28, 0x35, 0xD0, 0x06, 0x99, 0x00, 0x29, 0x32,
+ 0xD0, 0x87, 0x4E, 0x81, 0x42, 0x00, 0x95, 0x18,
+ 0xD9, 0x01, 0x46, 0x86, 0x4A, 0x86, 0x4B, 0x06,
+ 0x98, 0xFF, 0xF7, 0x96, 0xFF, 0x03, 0x9A, 0x00,
+ 0x92, 0x2B, 0x46, 0x22, 0x46, 0xB1, 0x78, 0x06,
+ 0x98, 0xFF, 0xF7, 0xDD, 0xFD, 0x00, 0x20, 0xB1,
+ 0x78, 0x04, 0xE0, 0x05, 0x9B, 0x22, 0x5C, 0x1A,
+ 0x54, 0x40, 0x1C, 0xC0, 0xB2, 0x88, 0x42, 0xF8,
+ 0xD3, 0x15, 0xE0, 0x7B, 0x4A,
+ 0x00, 0x01, 0x5F, 0x00, 0x80, 0x79, 0x4B, 0xFF,
+ 0xF7, 0x7F, 0xFF, 0x03, 0x9A, 0x00, 0x92, 0x2B,
+ 0x46, 0x22, 0x46, 0xB0, 0x78, 0x06, 0x99, 0xFF,
+ 0xF7, 0xC6, 0xFD, 0x00, 0x20, 0x04, 0xE0, 0x22,
+ 0x56, 0x05, 0x99, 0x88, 0x54, 0x40, 0x1C, 0xC0,
+ 0xB2, 0x06, 0x99, 0x88, 0x42, 0xF7, 0xD3, 0x00,
+ 0x27, 0x6F, 0x4E, 0x38, 0x46, 0x34, 0x46, 0x07,
+ 0x97, 0x5A, 0xE0, 0x05, 0x9A, 0xE0, 0x7A, 0x51,
+ 0x5C, 0x0B, 0x29, 0x37, 0xD0, 0x0E, 0x22, 0x51,
+ 0x43, 0x68, 0x4A, 0xA3, 0x88, 0x8D, 0x18, 0x69,
+ 0x88, 0x62, 0x88, 0x89, 0x1A, 0xAA, 0x88, 0x49,
+ 0x43, 0xD2, 0x1A, 0x52, 0x43, 0x89, 0x18, 0x02,
+ 0x9A, 0x91, 0x42, 0x27, 0xD8, 0x0E, 0x28, 0x0B,
+ 0xD8, 0x5F, 0x4A, 0x01, 0x21, 0x93, 0x88, 0x81,
+ 0x40, 0x19, 0x43, 0x00, 0xE0, 0xB2, 0xE0, 0x91,
+ 0x80, 0x21, 0x88, 0x49, 0x1C, 0x29, 0x80, 0x07,
+ 0xE0, 0xA1, 0x7A, 0x00, 0x29,
+ 0x00, 0x01, 0x60, 0x00, 0x80, 0x0A, 0xD1, 0xFF,
+ 0xF7, 0x7A, 0xFD, 0x00, 0x21, 0x29, 0x80, 0xE0,
+ 0x72, 0xE8, 0x72, 0x53, 0x48, 0x00, 0x7B, 0xA8,
+ 0x72, 0x29, 0x46, 0x1E, 0xE0, 0x42, 0x06, 0x52,
+ 0x0E, 0x01, 0x21, 0x91, 0x40, 0x50, 0x4A, 0x13,
+ 0x89, 0x19, 0x43, 0x11, 0x81, 0xE8, 0x72, 0xA0,
+ 0x7A, 0xA8, 0x72, 0x18, 0xE0, 0x0E, 0x28, 0x16,
+ 0xD8, 0xA1, 0x7A, 0x00, 0x29, 0x13, 0xD0, 0x01,
+ 0x22, 0x82, 0x40, 0x49, 0x48, 0x49, 0x1E, 0x83,
+ 0x88, 0x1A, 0x43, 0x82, 0x80, 0x20, 0x88, 0x40,
+ 0x1C, 0x20, 0x80, 0xA1, 0x72, 0xB4, 0x42, 0x03,
+ 0xD0, 0x21, 0x46, 0x30, 0x46, 0xF6, 0xF7, 0xDD,
+ 0xFC, 0x7F, 0x1C, 0xFF, 0xB2, 0x0E, 0x36, 0x07,
+ 0x98, 0x40, 0x1C, 0xC0, 0xB2, 0x0E, 0x34, 0x07,
+ 0x90, 0x01, 0x46, 0x3D, 0x48, 0x80, 0x78, 0x81,
+ 0x42, 0x9F, 0xD3, 0x00, 0x20, 0x3D, 0x46, 0x3B,
+ 0x4C, 0x04, 0x96, 0x08, 0x90,
+ 0x00, 0x01, 0x61, 0x00, 0x80, 0x55, 0xE0, 0xE0,
+ 0x7A, 0x1E, 0x28, 0x3D, 0xD1, 0xA0, 0x7A, 0x84,
+ 0x46, 0x00, 0x28, 0x1C, 0xD1, 0x0B, 0x2D, 0x0A,
+ 0xD2, 0x04, 0x98, 0x86, 0x42, 0x02, 0xD0, 0x31,
+ 0x46, 0xF6, 0xF7, 0xBB, 0xFC, 0x04, 0x98, 0x6D,
+ 0x1C, 0x0E, 0x30, 0xED, 0xB2, 0x04, 0x90, 0xFF,
+ 0xF7, 0x26, 0xFD, 0xE0, 0x72, 0x00, 0x20, 0x20,
+ 0x80, 0x29, 0x48, 0x00, 0x7B, 0xA0, 0x72, 0x21,
+ 0x46, 0x30, 0x46, 0xF6, 0xF7, 0xAA, 0xFC, 0x7F,
+ 0x1C, 0xFF, 0xB2, 0x0E, 0x36, 0x2C, 0xE0, 0x0B,
+ 0x2D, 0x2A, 0xD2, 0x25, 0x48, 0x41, 0x89, 0x03,
+ 0x89, 0x19, 0x43, 0x00, 0x20, 0xCA, 0x07, 0x0B,
+ 0xD1, 0x80, 0x22, 0x01, 0x46, 0x91, 0x43, 0x01,
+ 0x22, 0x8A, 0x40, 0x1F, 0x49, 0x1A, 0x43, 0x0A,
+ 0x81, 0x80, 0x21, 0x08, 0x43, 0xC0, 0xB2, 0x04,
+ 0xE0, 0x40, 0x1C, 0x49, 0x08, 0x0E, 0x28, 0xED,
+ 0xD9, 0x1E, 0x20, 0xE0, 0x72,
+ 0x00, 0x01, 0x62, 0x00, 0x80, 0x60, 0x46, 0x04,
+ 0xE0, 0x00, 0x06, 0x0D, 0xD5, 0x0B, 0x2D, 0x0B,
+ 0xD2, 0xA0, 0x7A, 0x21, 0x46, 0x40, 0x1E, 0xA0,
+ 0x72, 0x04, 0x98, 0xF6, 0xF7, 0x7E, 0xFC, 0x6D,
+ 0x1C, 0x04, 0x98, 0xED, 0xB2, 0x0E, 0x30, 0x04,
+ 0x90, 0x08, 0x98, 0x40, 0x1C, 0xC0, 0xB2, 0x0E,
+ 0x34, 0x08, 0x90, 0x01, 0x46, 0x06, 0x98, 0x81,
+ 0x42, 0x01, 0xD2, 0x0B, 0x2F, 0xA3, 0xD3, 0x09,
+ 0x48, 0x09, 0x4C, 0x07, 0x70, 0xA5, 0x70, 0x02,
+ 0x78, 0x0E, 0x20, 0x42, 0x43, 0x08, 0x49, 0x07,
+ 0x48, 0x01, 0xF0, 0xE8, 0xFB, 0xA0, 0x88, 0xE0,
+ 0x80, 0x20, 0x89, 0x60, 0x81, 0x09, 0xB0, 0xF0,
+ 0xBD, 0x5C, 0xDD, 0x00, 0x00, 0x92, 0x00, 0x00,
+ 0x20, 0xB4, 0x02, 0x00, 0x20, 0x4C, 0x03, 0x00,
+ 0x20, 0xDC, 0x14, 0x00, 0x20, 0xF8, 0x49, 0x00,
+ 0x20, 0x08, 0x70, 0x70, 0x47, 0xF6, 0x49, 0x00,
+ 0x28, 0x01, 0xD1, 0xF6, 0x48,
+ 0x00, 0x01, 0x63, 0x00, 0x80, 0x03, 0xE0, 0x01,
+ 0x28, 0x02, 0xD1, 0xF4, 0x48, 0x10, 0x30, 0x48,
+ 0x60, 0x70, 0x47, 0x02, 0x46, 0x08, 0x46, 0x11,
+ 0x02, 0xF0, 0x4A, 0x10, 0xB5, 0x1C, 0x32, 0x94,
+ 0x79, 0x03, 0x46, 0xA3, 0x40, 0x1B, 0x1A, 0x59,
+ 0x18, 0x93, 0x79, 0xD9, 0x40, 0x0B, 0x1A, 0x81,
+ 0x42, 0x00, 0xD8, 0x43, 0x1A, 0xD2, 0x79, 0x1B,
+ 0x0A, 0x93, 0x42, 0x00, 0xD9, 0x08, 0x46, 0x10,
+ 0xBD, 0xF0, 0xB5, 0x9D, 0xB0, 0x00, 0x20, 0xE4,
+ 0x4A, 0x11, 0x90, 0x10, 0x90, 0x50, 0x68, 0x01,
+ 0x68, 0x0F, 0x91, 0x00, 0x21, 0x0D, 0x46, 0x0E,
+ 0x91, 0xE1, 0x49, 0x09, 0x68, 0x09, 0x02, 0x09,
+ 0x0C, 0x04, 0x91, 0xE0, 0x49, 0x09, 0x68, 0x09,
+ 0x02, 0x09, 0x0C, 0x03, 0x91, 0x01, 0x7B, 0x09,
+ 0x91, 0x41, 0x7B, 0x08, 0x91, 0x84, 0x7B, 0x20,
+ 0x23, 0x19, 0x46, 0xE1, 0x40, 0x07, 0x91, 0x40,
+ 0x68, 0x0F, 0x99, 0xC3, 0x40,
+ 0x00, 0x01, 0x64, 0x00, 0x80, 0xD8, 0x48, 0x06,
+ 0x93, 0x1C, 0x90, 0x00, 0x29, 0x02, 0xD1, 0x40,
+ 0x79, 0x80, 0x07, 0x7E, 0xD0, 0xD4, 0x48, 0x20,
+ 0x38, 0xC1, 0x68, 0x40, 0x39, 0x0D, 0x91, 0x01,
+ 0x69, 0x40, 0x39, 0x0C, 0x91, 0xC1, 0x68, 0x10,
+ 0x39, 0x0B, 0x91, 0x00, 0x69, 0x10, 0x38, 0x0A,
+ 0x90, 0xCA, 0x48, 0x1C, 0x30, 0x1B, 0x90, 0x0E,
+ 0x98, 0x13, 0xE0, 0x28, 0x46, 0x0E, 0x21, 0x48,
+ 0x43, 0xCA, 0x49, 0x02, 0x46, 0x44, 0x18, 0x0E,
+ 0x98, 0x0C, 0x26, 0x70, 0x43, 0xE3, 0x7A, 0xC8,
+ 0x4E, 0x1A, 0x90, 0x80, 0x19, 0x19, 0x90, 0xC0,
+ 0x7A, 0x83, 0x42, 0x0D, 0xD0, 0x0E, 0x98, 0x40,
+ 0x1C, 0x0E, 0x90, 0xBD, 0x49, 0x09, 0x78, 0x88,
+ 0x42, 0x03, 0xD2, 0xC2, 0x48, 0x00, 0x78, 0x85,
+ 0x42, 0xE3, 0xD3, 0xC0, 0x48, 0x02, 0x78, 0x3A,
+ 0xE2, 0x67, 0x88, 0xA0, 0x88, 0x17, 0x90, 0xA0,
+ 0x79, 0x16, 0x90, 0x1B, 0x98,
+ 0x00, 0x01, 0x65, 0x00, 0x80, 0x80, 0x7A, 0x01,
+ 0x28, 0x7E, 0xD1, 0x00, 0x26, 0x0E, 0x98, 0x00,
+ 0x96, 0x85, 0x42, 0x02, 0xD1, 0x88, 0x5A, 0x02,
+ 0x28, 0x08, 0xD2, 0xB5, 0x4A, 0x0C, 0x20, 0x00,
+ 0x21, 0x68, 0x43, 0x84, 0x32, 0x80, 0x18, 0x01,
+ 0x72, 0x41, 0x72, 0x81, 0x72, 0x04, 0x98, 0x40,
+ 0x00, 0xB8, 0x42, 0x05, 0xD8, 0xAC, 0x49, 0x20,
+ 0x39, 0xC9, 0x68, 0x08, 0x1A, 0xB8, 0x42, 0x22,
+ 0xD2, 0x20, 0x7B, 0x10, 0x28, 0x00, 0xD1, 0x01,
+ 0x26, 0x04, 0x98, 0x87, 0x42, 0x06, 0xD3, 0xA6,
+ 0x48, 0x20, 0x38, 0xC0, 0x68, 0x04, 0x99, 0x40,
+ 0x1A, 0xB8, 0x42, 0x14, 0xD2, 0xA2, 0x48, 0x01,
+ 0x26, 0x20, 0x38, 0x01, 0x69, 0x17, 0x9A, 0x49,
+ 0x08, 0x0A, 0x39, 0x91, 0x42, 0x0B, 0xD2, 0x00,
+ 0x69, 0x40, 0x08, 0x0A, 0x30, 0x90, 0x42, 0x06,
+ 0xD9, 0x9D, 0x4A, 0x0C, 0x20, 0x01, 0x21, 0x68,
+ 0x43, 0x84, 0x32, 0x80, 0x18,
+ 0x00, 0x01, 0x66, 0x00, 0x80, 0x41, 0x72, 0x03,
+ 0x98, 0x17, 0x99, 0x40, 0x00, 0x88, 0x42, 0x08,
+ 0xD8, 0x00, 0xE0, 0xF0, 0xE1, 0x94, 0x49, 0x20,
+ 0x39, 0x09, 0x69, 0x08, 0x1A, 0x17, 0x99, 0x88,
+ 0x42, 0x23, 0xD2, 0x20, 0x7B, 0x10, 0x28, 0x01,
+ 0xD1, 0x02, 0x20, 0x06, 0x43, 0x08, 0x46, 0x03,
+ 0x99, 0x88, 0x42, 0x06, 0xD3, 0x8C, 0x48, 0x20,
+ 0x38, 0x00, 0x69, 0x40, 0x1A, 0x17, 0x99, 0x88,
+ 0x42, 0x13, 0xD2, 0x02, 0x21, 0x88, 0x4A, 0x0E,
+ 0x43, 0x20, 0x3A, 0xD0, 0x68, 0x40, 0x08, 0x0A,
+ 0x38, 0xB8, 0x42, 0x0A, 0xD2, 0xD0, 0x68, 0x40,
+ 0x08, 0x0A, 0x30, 0xB8, 0x42, 0x05, 0xD9, 0x84,
+ 0x4A, 0x0C, 0x20, 0x68, 0x43, 0x84, 0x32, 0x80,
+ 0x18, 0x41, 0x72, 0x00, 0x2E, 0x12, 0xD0, 0x80,
+ 0x49, 0x0C, 0x20, 0x68, 0x43, 0x84, 0x31, 0x40,
+ 0x18, 0x18, 0x90, 0x40, 0x7A, 0x01, 0x46, 0x71,
+ 0x40, 0x03, 0x29, 0x07, 0xD0,
+ 0x00, 0x01, 0x67, 0x00, 0x80, 0x18, 0x99, 0x00,
+ 0xE0, 0x72, 0xE0, 0x89, 0x7A, 0x0A, 0x46, 0x72,
+ 0x40, 0x03, 0x2A, 0x09, 0xD1, 0x76, 0x4A, 0x0C,
+ 0x20, 0x00, 0x21, 0x68, 0x43, 0x84, 0x32, 0x80,
+ 0x18, 0x01, 0x72, 0x41, 0x72, 0x86, 0x72, 0x63,
+ 0xE0, 0x01, 0x22, 0x03, 0x29, 0x00, 0xD0, 0x00,
+ 0x22, 0x18, 0x99, 0x03, 0x2E, 0x8E, 0x72, 0x02,
+ 0xD1, 0x06, 0x46, 0x03, 0x20, 0x00, 0x90, 0x01,
+ 0x2E, 0x09, 0xD1, 0xB8, 0xB2, 0x02, 0x90, 0x6A,
+ 0x49, 0x1A, 0x98, 0x08, 0x5A, 0x41, 0x09, 0x17,
+ 0x98, 0x05, 0x90, 0x03, 0x98, 0x07, 0xE0, 0x17,
+ 0x98, 0x80, 0xB2, 0x02, 0x90, 0x19, 0x98, 0x40,
+ 0x88, 0x05, 0x97, 0x41, 0x09, 0x04, 0x98, 0x01,
+ 0x90, 0x01, 0x2A, 0x0A, 0xD1, 0x00, 0x20, 0x43,
+ 0x00, 0x18, 0x9A, 0x40, 0x1C, 0xC0, 0xB2, 0xD1,
+ 0x52, 0x04, 0x28, 0xF8, 0xD3, 0x18, 0x99, 0x0F,
+ 0x20, 0x08, 0x72, 0x01, 0x99,
+ 0x00, 0x01, 0x68, 0x00, 0x80, 0x05, 0x98, 0x01,
+ 0xF0, 0xFE, 0xFA, 0x01, 0x99, 0x48, 0x43, 0x05,
+ 0x99, 0x08, 0x1A, 0x80, 0x00, 0x01, 0x99, 0x01,
+ 0xF0, 0xF6, 0xFA, 0x00, 0x99, 0xC0, 0xB2, 0x00,
+ 0x29, 0x0A, 0xD1, 0x18, 0x9A, 0x43, 0x00, 0x02,
+ 0x99, 0xD1, 0x52, 0x18, 0x99, 0x01, 0x22, 0x09,
+ 0x7A, 0x82, 0x40, 0x18, 0x98, 0x11, 0x43, 0x01,
+ 0x72, 0x18, 0x99, 0x00, 0x23, 0x09, 0x7A, 0x18,
+ 0x46, 0x8C, 0x46, 0x01, 0x22, 0x61, 0x46, 0x82,
+ 0x40, 0x11, 0x42, 0x04, 0xD0, 0x18, 0x99, 0x42,
+ 0x00, 0x89, 0x5A, 0xCB, 0x18, 0x01, 0xE0, 0x02,
+ 0x99, 0x5B, 0x18, 0x40, 0x1C, 0xC0, 0xB2, 0x04,
+ 0x28, 0xEF, 0xD3, 0x98, 0x03, 0x00, 0x0C, 0x01,
+ 0x2E, 0x01, 0xD1, 0x07, 0x46, 0x00, 0xE0, 0x17,
+ 0x90, 0x3F, 0x48, 0x1A, 0x99, 0x40, 0x5A, 0x15,
+ 0x90, 0x19, 0x98, 0x41, 0x88, 0x14, 0x91, 0x80,
+ 0x88, 0x12, 0x90, 0x49, 0x09,
+ 0x00, 0x01, 0x69, 0x00, 0x80, 0x15, 0x98, 0x13,
+ 0x91, 0x0F, 0x99, 0x40, 0x09, 0x09, 0x06, 0x77,
+ 0xD5, 0xC1, 0x1B, 0xB8, 0x42, 0x00, 0xD8, 0x39,
+ 0x1A, 0x08, 0x98, 0x81, 0x42, 0x01, 0xD8, 0x06,
+ 0x98, 0x11, 0xE0, 0x09, 0x98, 0x81, 0x42, 0x01,
+ 0xD9, 0x07, 0x98, 0x0C, 0xE0, 0x08, 0x98, 0x06,
+ 0x9A, 0x08, 0x1A, 0x07, 0x99, 0x89, 0x1A, 0x48,
+ 0x43, 0x08, 0x9A, 0x09, 0x99, 0x89, 0x1A, 0x01,
+ 0xF0, 0xA2, 0xFA, 0x06, 0x99, 0x40, 0x18, 0x1B,
+ 0x99, 0x09, 0x79, 0x01, 0x29, 0x08, 0xD1, 0x2A,
+ 0x49, 0xC9, 0x6B, 0x01, 0x29, 0x04, 0xD1, 0x29,
+ 0x49, 0x09, 0x88, 0x89, 0x06, 0x00, 0xD5, 0x80,
+ 0x08, 0x15, 0x99, 0x15, 0x9A, 0x41, 0x43, 0x49,
+ 0x09, 0x47, 0x43, 0x51, 0x1A, 0xCE, 0x19, 0x13,
+ 0x99, 0x17, 0x98, 0x17, 0x9A, 0x08, 0x1A, 0x91,
+ 0x42, 0x00, 0xD8, 0x50, 0x1A, 0x08, 0x99, 0x88,
+ 0x42, 0x01, 0xD2, 0x06, 0x98,
+ 0x00, 0x01, 0x6A, 0x00, 0x80, 0x11, 0xE0, 0x09,
+ 0x99, 0x88, 0x42, 0x01, 0xD3, 0x07, 0x98, 0x0C,
+ 0xE0, 0x08, 0x99, 0x06, 0x9A, 0x40, 0x1A, 0x07,
+ 0x99, 0x89, 0x1A, 0x48, 0x43, 0x08, 0x9A, 0x09,
+ 0x99, 0x89, 0x1A, 0x01, 0xF0, 0x70, 0xFA, 0x06,
+ 0x99, 0x40, 0x18, 0x1B, 0x99, 0x09, 0x79, 0x01,
+ 0x29, 0x08, 0xD1, 0x11, 0x49, 0xC9, 0x6B, 0x01,
+ 0x29, 0x04, 0xD1, 0x10, 0x49, 0x09, 0x88, 0x89,
+ 0x06, 0x00, 0xD5, 0x80, 0x08, 0x14, 0x99, 0x14,
+ 0x9A, 0x41, 0x43, 0x49, 0x09, 0x52, 0x1A, 0x17,
+ 0x99, 0x41, 0x43, 0x57, 0x18, 0x17, 0xE0, 0x13,
+ 0xE0, 0xC0, 0x02, 0x00, 0x20, 0x2C, 0xDD, 0x00,
+ 0x00, 0xA0, 0x00, 0x00, 0x20, 0xA4, 0x00, 0x00,
+ 0x20, 0xB0, 0xDD, 0x00, 0x00, 0x4C, 0x03, 0x00,
+ 0x20, 0x76, 0x15, 0x00, 0x20, 0x92, 0x00, 0x00,
+ 0x20, 0x78, 0xDC, 0x00, 0x00, 0x48, 0x02, 0x00,
+ 0x20, 0x17, 0x98, 0x7E, 0x01,
+ 0x00, 0x01, 0x6B, 0x00, 0x80, 0x47, 0x01, 0x0F,
+ 0x98, 0x80, 0x06, 0x10, 0xD5, 0x5B, 0x48, 0x40,
+ 0x68, 0x80, 0x68, 0x01, 0x28, 0x04, 0xD1, 0x12,
+ 0x99, 0x16, 0x98, 0x40, 0x18, 0x40, 0x08, 0x05,
+ 0xE0, 0x12, 0x98, 0x41, 0x00, 0x41, 0x18, 0x16,
+ 0x98, 0x08, 0x18, 0x80, 0x08, 0x16, 0x90, 0x0F,
+ 0x98, 0x40, 0x06, 0x25, 0xD5, 0x15, 0x98, 0x86,
+ 0x42, 0x06, 0xD9, 0x0D, 0x98, 0x86, 0x42, 0x03,
+ 0xD8, 0x10, 0x2E, 0x01, 0xD9, 0x10, 0x3E, 0x08,
+ 0xE0, 0x15, 0x98, 0x86, 0x42, 0x05, 0xD2, 0x40,
+ 0x2E, 0x03, 0xD3, 0x0B, 0x98, 0x86, 0x42, 0x00,
+ 0xD2, 0x10, 0x36, 0x14, 0x98, 0x87, 0x42, 0x06,
+ 0xD9, 0x0C, 0x98, 0x87, 0x42, 0x03, 0xD8, 0x10,
+ 0x2F, 0x01, 0xD9, 0x10, 0x3F, 0x08, 0xE0, 0x14,
+ 0x98, 0x87, 0x42, 0x05, 0xD2, 0x40, 0x2F, 0x03,
+ 0xD3, 0x0A, 0x98, 0x86, 0x42, 0x00, 0xD2, 0x10,
+ 0x37, 0x0F, 0x98, 0xC0, 0x06,
+ 0x00, 0x01, 0x6C, 0x00, 0x80, 0x09, 0xD5, 0x12,
+ 0x99, 0x16, 0x98, 0x88, 0x42, 0x01, 0xD9, 0x40,
+ 0x1E, 0x02, 0xE0, 0x88, 0x42, 0x01, 0xD2, 0x40,
+ 0x1C, 0x16, 0x90, 0x1C, 0x98, 0x40, 0x79, 0xC0,
+ 0x07, 0x0B, 0xD0, 0x19, 0x98, 0xC1, 0x88, 0xE0,
+ 0x79, 0xFF, 0xF7, 0xB3, 0xFD, 0x11, 0x90, 0x19,
+ 0x98, 0x01, 0x89, 0x20, 0x7A, 0xFF, 0xF7, 0xAD,
+ 0xFD, 0x10, 0x90, 0x1C, 0x98, 0x40, 0x79, 0x80,
+ 0x07, 0x17, 0xD5, 0x19, 0x99, 0x0A, 0x20, 0x08,
+ 0x56, 0x1B, 0x99, 0x03, 0x46, 0x0A, 0x7A, 0x01,
+ 0x46, 0x91, 0x40, 0x09, 0x22, 0xA2, 0x56, 0x09,
+ 0x1A, 0x8A, 0x18, 0x1B, 0x99, 0x09, 0x7A, 0x0A,
+ 0x41, 0x62, 0x72, 0x10, 0x1A, 0x00, 0xD5, 0x40,
+ 0x42, 0x1B, 0x99, 0x49, 0x7A, 0x81, 0x42, 0x00,
+ 0xDD, 0x63, 0x72, 0x28, 0x46, 0x0C, 0x22, 0x50,
+ 0x43, 0x21, 0x4A, 0x03, 0x46, 0xE1, 0x7A, 0x80,
+ 0x18, 0xC1, 0x72, 0xF1, 0x02,
+ 0x00, 0x01, 0x6D, 0x00, 0x80, 0xD6, 0x52, 0x09,
+ 0x0C, 0x61, 0x80, 0xF9, 0x02, 0x47, 0x80, 0x09,
+ 0x0C, 0xA1, 0x80, 0x16, 0x99, 0x81, 0x80, 0x16,
+ 0x99, 0xA1, 0x71, 0x11, 0x99, 0xC1, 0x80, 0x11,
+ 0x99, 0x09, 0x0A, 0xE1, 0x71, 0x10, 0x99, 0x01,
+ 0x81, 0x10, 0x99, 0x09, 0x0A, 0x21, 0x72, 0x61,
+ 0x7A, 0x81, 0x72, 0x6D, 0x1C, 0xD2, 0xE5, 0x0E,
+ 0x20, 0x12, 0x49, 0x68, 0x43, 0x40, 0x18, 0x41,
+ 0x88, 0x0C, 0x24, 0x4B, 0x01, 0x29, 0x46, 0x61,
+ 0x43, 0x0D, 0x4C, 0x63, 0x52, 0x83, 0x88, 0x09,
+ 0x19, 0x5B, 0x01, 0x4B, 0x80, 0x83, 0x79, 0x8B,
+ 0x80, 0xC3, 0x7A, 0xCB, 0x72, 0xC3, 0x79, 0x1B,
+ 0x02, 0xCB, 0x80, 0x03, 0x7A, 0x1B, 0x02, 0x0B,
+ 0x81, 0x40, 0x7A, 0x88, 0x72, 0x6D, 0x1C, 0x95,
+ 0x42, 0xE1, 0xD3, 0x02, 0x48, 0x02, 0x70, 0x1D,
+ 0xB0, 0xF0, 0xBD, 0x00, 0x00, 0xC0, 0x02, 0x00,
+ 0x20, 0x76, 0x15, 0x00, 0x20,
+ 0x00, 0x01, 0x6E, 0x00, 0x80, 0x4C, 0x03, 0x00,
+ 0x20, 0x10, 0xB5, 0x00, 0x23, 0x14, 0x48, 0x14,
+ 0x4A, 0x83, 0x75, 0xFF, 0x21, 0xC3, 0x75, 0x5C,
+ 0x32, 0x01, 0x76, 0x14, 0x46, 0x18, 0x46, 0x08,
+ 0x34, 0x11, 0x54, 0x23, 0x54, 0x40, 0x1C, 0x08,
+ 0x28, 0xFA, 0xD3, 0x10, 0xBD, 0x0C, 0x49, 0x00,
+ 0x20, 0xC8, 0x64, 0xC8, 0x71, 0x08, 0x72, 0x08,
+ 0x65, 0x48, 0x72, 0x48, 0x65, 0x88, 0x72, 0xC8,
+ 0x72, 0xC8, 0x77, 0x88, 0x65, 0x08, 0x75, 0x48,
+ 0x75, 0x88, 0x71, 0xDD, 0xE7, 0x10, 0xB5, 0x04,
+ 0x4C, 0x20, 0x78, 0x00, 0x28, 0x03, 0xD1, 0xFF,
+ 0xF7, 0xE9, 0xFF, 0x01, 0x20, 0x20, 0x70, 0x10,
+ 0xBD, 0xC8, 0x02, 0x00, 0x20, 0x70, 0x47, 0xF0,
+ 0xB5, 0x00, 0x21, 0xB2, 0x4A, 0x99, 0xB0, 0x11,
+ 0x70, 0x20, 0x28, 0x47, 0xD1, 0xB0, 0x4E, 0x34,
+ 0x6A, 0xB0, 0x4D, 0x20, 0x46, 0x01, 0xAA, 0x40,
+ 0x1E, 0x2B, 0x56, 0x00, 0x2B,
+ 0x00, 0x01, 0x6F, 0x00, 0x80, 0x00, 0xDA, 0x5B,
+ 0x42, 0x01, 0x19, 0x69, 0x56, 0x00, 0x29, 0x00,
+ 0xDA, 0x49, 0x42, 0x8B, 0x42, 0x00, 0xDC, 0x0B,
+ 0x46, 0x41, 0x00, 0x53, 0x52, 0x00, 0x28, 0xEE,
+ 0xD1, 0xA7, 0x48, 0x00, 0x78, 0x18, 0x90, 0x40,
+ 0x1E, 0x41, 0x00, 0x51, 0x5E, 0x04, 0x46, 0x40,
+ 0x1E, 0x43, 0x00, 0xD3, 0x5E, 0x8B, 0x42, 0x01,
+ 0xDD, 0x19, 0x46, 0x04, 0x46, 0x00, 0x28, 0xF6,
+ 0xD1, 0xA0, 0x4B, 0xD8, 0x68, 0x88, 0x42, 0x17,
+ 0xDD, 0x58, 0x68, 0x88, 0x42, 0x1A, 0xDC, 0x30,
+ 0x6A, 0x40, 0x1E, 0x41, 0x00, 0x51, 0x5E, 0x05,
+ 0x46, 0x40, 0x1E, 0x42, 0x00, 0x01, 0xAF, 0xBA,
+ 0x5E, 0x8A, 0x42, 0x01, 0xDD, 0x11, 0x46, 0x05,
+ 0x46, 0xF2, 0x69, 0x82, 0x42, 0xF4, 0xD3, 0xF0,
+ 0x69, 0x2D, 0x1A, 0xD8, 0x68, 0x88, 0x42, 0x02,
+ 0xDC, 0x01, 0x20, 0x19, 0xB0, 0xF0, 0xBD, 0x58,
+ 0x68, 0x88, 0x42, 0x01, 0xDD,
+ 0x00, 0x01, 0x70, 0x00, 0x80, 0x00, 0x20, 0xF8,
+ 0xE7, 0xF0, 0x69, 0x40, 0x1E, 0x00, 0x2C, 0x2F,
+ 0xD0, 0x84, 0x42, 0x40, 0xD2, 0x01, 0x2C, 0x03,
+ 0xD1, 0x6B, 0x46, 0x0A, 0x20, 0x18, 0x5E, 0x15,
+ 0xE0, 0x41, 0x1E, 0x8C, 0x42, 0x06, 0xD1, 0x41,
+ 0x00, 0x01, 0xA8, 0x09, 0x18, 0x20, 0x39, 0x1A,
+ 0x20, 0x08, 0x5E, 0x0B, 0xE0, 0x61, 0x00, 0x01,
+ 0xA8, 0x09, 0x18, 0x0A, 0x46, 0x20, 0x3A, 0x1C,
+ 0x20, 0x10, 0x5E, 0x04, 0x22, 0x8A, 0x5E, 0x90,
+ 0x42, 0x00, 0xDC, 0x10, 0x46, 0x63, 0x00, 0x01,
+ 0xA9, 0x59, 0x18, 0x0F, 0x46, 0x20, 0x3F, 0x1E,
+ 0x23, 0xFB, 0x5E, 0x00, 0x22, 0x83, 0x42, 0x00,
+ 0xD9, 0x1A, 0x1A, 0x02, 0x27, 0xCF, 0x5F, 0x00,
+ 0x23, 0x87, 0x42, 0x28, 0xD9, 0x3B, 0x1A, 0x26,
+ 0xE0, 0x6B, 0x46, 0x04, 0x22, 0x06, 0x21, 0x08,
+ 0x20, 0x9A, 0x5E, 0x59, 0x5E, 0x18, 0x5E, 0x53,
+ 0x18, 0x00, 0x27, 0x3A, 0x46,
+ 0x00, 0x01, 0x71, 0x00, 0x80, 0x50, 0x2B, 0x01,
+ 0xD2, 0x50, 0x22, 0xD2, 0x1A, 0x3B, 0x46, 0x81,
+ 0x42, 0x15, 0xD9, 0x0B, 0x1A, 0x13, 0xE0, 0x42,
+ 0x00, 0x01, 0xAB, 0xD1, 0x18, 0x9A, 0x5E, 0x20,
+ 0x39, 0x1E, 0x23, 0x1C, 0x20, 0xCB, 0x5E, 0x08,
+ 0x5E, 0xD1, 0x18, 0x00, 0x27, 0x3A, 0x46, 0x83,
+ 0x42, 0x00, 0xD9, 0x1A, 0x1A, 0x3B, 0x46, 0x50,
+ 0x29, 0x01, 0xD2, 0x50, 0x23, 0x5B, 0x1A, 0x61,
+ 0x00, 0x01, 0xAF, 0x79, 0x5E, 0x08, 0x1A, 0x10,
+ 0x18, 0xC1, 0x18, 0x98, 0x1A, 0x00, 0x02, 0x01,
+ 0xF0, 0xA4, 0xF8, 0x00, 0x28, 0x06, 0xDB, 0x81,
+ 0x08, 0x5B, 0x4A, 0x89, 0x00, 0x51, 0x58, 0x80,
+ 0x30, 0x08, 0x18, 0x06, 0xE0, 0x41, 0x42, 0x89,
+ 0x08, 0x57, 0x4A, 0x89, 0x00, 0x51, 0x58, 0x40,
+ 0x1A, 0x80, 0x30, 0x00, 0x90, 0xB0, 0x69, 0x52,
+ 0x49, 0x01, 0xAA, 0x09, 0x78, 0x40, 0x1E, 0x49,
+ 0x00, 0x8A, 0x18, 0x00, 0x2D,
+ 0x00, 0x01, 0x72, 0x00, 0x80, 0x2E, 0xD0, 0x18,
+ 0x99, 0x85, 0x42, 0x3B, 0xD2, 0x69, 0x18, 0x01,
+ 0x2D, 0x02, 0xD1, 0x06, 0x20, 0x10, 0x5E, 0x14,
+ 0xE0, 0x40, 0x1E, 0x85, 0x42, 0x06, 0xD1, 0x30,
+ 0x6A, 0x40, 0x00, 0xC2, 0x19, 0x20, 0x3A, 0x18,
+ 0x20, 0x10, 0x5E, 0x0A, 0xE0, 0x48, 0x00, 0xC3,
+ 0x19, 0x1A, 0x46, 0x20, 0x3A, 0x1C, 0x20, 0x10,
+ 0x5E, 0x04, 0x22, 0x9A, 0x5E, 0x90, 0x42, 0x00,
+ 0xDC, 0x10, 0x46, 0x49, 0x00, 0xC9, 0x19, 0x0E,
+ 0x46, 0x20, 0x3E, 0x1E, 0x23, 0xF3, 0x5E, 0x00,
+ 0x22, 0x83, 0x42, 0x00, 0xD9, 0x1A, 0x1A, 0x02,
+ 0x23, 0xCB, 0x5E, 0x00, 0x26, 0x83, 0x42, 0x27,
+ 0xD9, 0x1E, 0x1A, 0x25, 0xE0, 0x7B, 0x5E, 0x02,
+ 0x21, 0x04, 0x20, 0x51, 0x5E, 0x00, 0x26, 0x10,
+ 0x5E, 0x5B, 0x18, 0x32, 0x46, 0x50, 0x2B, 0x01,
+ 0xD2, 0x50, 0x22, 0xD2, 0x1A, 0x81, 0x42, 0x17,
+ 0xD9, 0x0E, 0x1A, 0x15, 0xE0,
+ 0x00, 0x01, 0x73, 0x00, 0x80, 0x31, 0x48, 0x1C,
+ 0x23, 0x00, 0x78, 0x00, 0x26, 0x08, 0x18, 0x40,
+ 0x00, 0xC2, 0x19, 0x20, 0x3A, 0x1E, 0x21, 0x1A,
+ 0x20, 0x51, 0x5E, 0xD3, 0x5E, 0x10, 0x5E, 0xC9,
+ 0x18, 0x32, 0x46, 0x83, 0x42, 0x00, 0xD9, 0x1A,
+ 0x1A, 0x50, 0x29, 0x01, 0xD2, 0x50, 0x23, 0x5E,
+ 0x1A, 0x18, 0x99, 0x69, 0x18, 0x49, 0x00, 0x79,
+ 0x5E, 0x08, 0x1A, 0x10, 0x18, 0x81, 0x19, 0xB0,
+ 0x1A, 0x00, 0x02, 0x01, 0xF0, 0x2A, 0xF8, 0x00,
+ 0x28, 0x06, 0xDB, 0x81, 0x08, 0x1E, 0x4A, 0x89,
+ 0x00, 0x51, 0x58, 0x80, 0x30, 0x0A, 0x18, 0x06,
+ 0xE0, 0x41, 0x42, 0x89, 0x08, 0x1A, 0x4A, 0x89,
+ 0x00, 0x51, 0x58, 0x42, 0x1A, 0x80, 0x32, 0x1A,
+ 0x48, 0x46, 0x69, 0x1A, 0x48, 0x1A, 0x49, 0x00,
+ 0x68, 0x09, 0x68, 0x1A, 0x4B, 0x01, 0x2E, 0x09,
+ 0xD1, 0x00, 0x9E, 0x24, 0x02, 0xA4, 0x19, 0x44,
+ 0x43, 0x20, 0x0C, 0x2C, 0x02,
+ 0x00, 0x01, 0x74, 0x00, 0x80, 0xA2, 0x18, 0x4A,
+ 0x43, 0x11, 0x0C, 0x08, 0xE0, 0x26, 0x02, 0x00,
+ 0x9C, 0x34, 0x19, 0x4C, 0x43, 0x21, 0x0C, 0x2C,
+ 0x02, 0xA2, 0x18, 0x42, 0x43, 0x10, 0x0C, 0x98,
+ 0x80, 0x59, 0x80, 0x32, 0x20, 0x98, 0x71, 0x01,
+ 0x20, 0x02, 0x49, 0xD8, 0x72, 0x08, 0x70, 0x21,
+ 0x20, 0xE3, 0xE6, 0x00, 0x00, 0x92, 0x00, 0x00,
+ 0x20, 0x88, 0xDF, 0x00, 0x00, 0x74, 0x0D, 0x00,
+ 0x20, 0x6E, 0x01, 0x00, 0x20, 0x70, 0xDD, 0x00,
+ 0x00, 0x88, 0xCF, 0x00, 0x00, 0x6D, 0x01, 0x00,
+ 0x20, 0x90, 0xDD, 0x00, 0x00, 0xA4, 0x00, 0x00,
+ 0x20, 0xA0, 0x00, 0x00, 0x20, 0x4C, 0x03, 0x00,
+ 0x20, 0xFA, 0x49, 0x8A, 0x78, 0xFA, 0x48, 0x02,
+ 0x70, 0xCA, 0x78, 0x42, 0x70, 0x0A, 0x79, 0x82,
+ 0x70, 0x4A, 0x79, 0xC2, 0x70, 0x8A, 0x79, 0x02,
+ 0x71, 0xCA, 0x79, 0x42, 0x71, 0x09, 0x7A, 0x81,
+ 0x71, 0x70, 0x47, 0xED, 0xE7,
+ 0x00, 0x01, 0x75, 0x00, 0x80, 0xF0, 0xB5, 0x00,
+ 0x29, 0x0B, 0xD0, 0x00, 0x24, 0xEF, 0x4E, 0x0E,
+ 0xE0, 0x05, 0x19, 0xEF, 0x00, 0x00, 0x23, 0xED,
+ 0x19, 0xAD, 0x19, 0xEF, 0x18, 0x3F, 0x7B, 0x00,
+ 0x2F, 0x01, 0xD0, 0x10, 0x46, 0xF0, 0xBD, 0x5B,
+ 0x1C, 0x09, 0x2B, 0xF6, 0xD3, 0x64, 0x1C, 0x8C,
+ 0x42, 0xEE, 0xD3, 0x00, 0x20, 0xF0, 0xBD, 0xF8,
+ 0xB5, 0xE4, 0x4D, 0xE6, 0x4F, 0x06, 0x46, 0x00,
+ 0x24, 0xA9, 0x1C, 0x38, 0x46, 0xFD, 0xF7, 0x92,
+ 0xFF, 0x29, 0x88, 0x88, 0x42, 0x39, 0xD1, 0x00,
+ 0x2E, 0x11, 0xD0, 0xE1, 0x49, 0x38, 0x46, 0xFD,
+ 0xF7, 0x89, 0xFF, 0xDF, 0x49, 0x89, 0x1E, 0x09,
+ 0x88, 0x88, 0x42, 0x2E, 0xD1, 0xDD, 0x49, 0x38,
+ 0x46, 0xFD, 0xF7, 0x80, 0xFF, 0xDB, 0x49, 0x89,
+ 0x1E, 0x09, 0x88, 0x88, 0x42, 0x25, 0xD1, 0x00,
+ 0x25, 0x00, 0xF0, 0x94, 0xFC, 0xD8, 0x4C, 0xE1,
+ 0x6A, 0x06, 0x46, 0x4E, 0x43,
+ 0x00, 0x01, 0x76, 0x00, 0x80, 0x01, 0x22, 0x31,
+ 0x46, 0x28, 0x46, 0xFF, 0xF7, 0xBB, 0xFF, 0xA7,
+ 0x6B, 0x05, 0x46, 0x02, 0x22, 0x39, 0x46, 0x30,
+ 0x46, 0xFF, 0xF7, 0xB4, 0xFF, 0x05, 0x43, 0xF6,
+ 0x19, 0xE7, 0x6B, 0x04, 0x22, 0x39, 0x46, 0x30,
+ 0x46, 0xFF, 0xF7, 0xAC, 0xFF, 0x05, 0x43, 0xA1,
+ 0x6A, 0xF0, 0x19, 0x00, 0x29, 0x00, 0xD0, 0x01,
+ 0x21, 0x08, 0x22, 0xFF, 0xF7, 0xA3, 0xFF, 0x28,
+ 0x43, 0x04, 0x46, 0x20, 0x46, 0xF8, 0xBD, 0xF1,
+ 0xB5, 0xC7, 0x48, 0xC6, 0x4C, 0x01, 0x69, 0x82,
+ 0xB0, 0x07, 0x22, 0x52, 0x06, 0x00, 0x91, 0x91,
+ 0x43, 0x01, 0x22, 0x52, 0x06, 0x89, 0x18, 0x01,
+ 0x61, 0x00, 0x26, 0x35, 0x46, 0xFE, 0xF7, 0x72,
+ 0xFF, 0x00, 0x28, 0x01, 0xD0, 0x01, 0x26, 0x02,
+ 0x25, 0xF0, 0xB2, 0xBE, 0x49, 0x01, 0x90, 0x30,
+ 0xE0, 0xFE, 0xF7, 0x6E, 0xFF, 0x02, 0x98, 0xFE,
+ 0xF7, 0x87, 0xFF, 0xB7, 0x48,
+ 0x00, 0x01, 0x77, 0x00, 0x80, 0x60, 0x30, 0xC0,
+ 0x7B, 0xFA, 0xF7, 0xA9, 0xFE, 0xB6, 0x49, 0x07,
+ 0x22, 0xC0, 0x39, 0xCA, 0x60, 0x08, 0x68, 0x8B,
+ 0x03, 0x18, 0x43, 0x08, 0x60, 0xC8, 0x68, 0xC0,
+ 0x07, 0x01, 0xD1, 0x64, 0x1E, 0xFA, 0xD2, 0xCA,
+ 0x60, 0xB1, 0x48, 0x02, 0x99, 0x00, 0x78, 0xB2,
+ 0x4A, 0xC1, 0x40, 0xB0, 0x4B, 0x12, 0x78, 0x0B,
+ 0xE0, 0xCE, 0x07, 0x07, 0xD0, 0xAF, 0x4F, 0x86,
+ 0x00, 0xF6, 0x19, 0x36, 0x68, 0x36, 0x04, 0x76,
+ 0x14, 0x47, 0x00, 0xDE, 0x53, 0x49, 0x08, 0x40,
+ 0x1C, 0x90, 0x42, 0xF1, 0xD3, 0xA5, 0x49, 0x08,
+ 0x78, 0x40, 0x1C, 0x08, 0x70, 0xA3, 0x48, 0x00,
+ 0x78, 0xA8, 0x42, 0xC9, 0xD9, 0xA1, 0x49, 0x01,
+ 0x98, 0x08, 0x70, 0x9F, 0x49, 0x00, 0x98, 0x08,
+ 0x61, 0xFE, 0xBD, 0x70, 0xB5, 0x05, 0x46, 0x00,
+ 0x23, 0x9E, 0x4E, 0x18, 0x46, 0xD4, 0x07, 0x09,
+ 0xD0, 0x5C, 0x00, 0x34, 0x5F,
+ 0x00, 0x01, 0x78, 0x00, 0x80, 0x00, 0x29, 0x02,
+ 0xD0, 0xAC, 0x42, 0x03, 0xDD, 0x01, 0xE0, 0xAC,
+ 0x42, 0x00, 0xDA, 0x01, 0x20, 0x5B, 0x1C, 0x52,
+ 0x08, 0xF0, 0xD1, 0x70, 0xBD, 0xFF, 0xB5, 0x81,
+ 0xB0, 0xD0, 0xB2, 0x03, 0x90, 0x8E, 0x48, 0x1F,
+ 0x46, 0x60, 0x30, 0xC0, 0x7B, 0xFA, 0xF7, 0x57,
+ 0xFE, 0x00, 0x25, 0x80, 0x24, 0xFE, 0x26, 0x8C,
+ 0x49, 0x25, 0x43, 0x08, 0x68, 0xB0, 0x43, 0x28,
+ 0x43, 0x08, 0x60, 0x03, 0x98, 0xFF, 0xF7, 0x7F,
+ 0xFF, 0x01, 0xA8, 0x07, 0xC8, 0xB8, 0x47, 0x00,
+ 0x28, 0x00, 0xD0, 0xA5, 0x43, 0x64, 0x08, 0x34,
+ 0x40, 0xED, 0xD1, 0x28, 0x46, 0x05, 0xB0, 0xF0,
+ 0xBD, 0x70, 0xB5, 0x05, 0x46, 0x00, 0x23, 0x83,
+ 0x4E, 0x01, 0x20, 0xD4, 0x07, 0x09, 0xD0, 0x5C,
+ 0x00, 0x34, 0x5F, 0x00, 0x29, 0x02, 0xD0, 0xAC,
+ 0x42, 0x03, 0xDC, 0x01, 0xE0, 0xAC, 0x42, 0x00,
+ 0xDB, 0x00, 0x20, 0x5B, 0x1C,
+ 0x00, 0x01, 0x79, 0x00, 0x80, 0x52, 0x08, 0xF0,
+ 0xD1, 0x70, 0xBD, 0xFF, 0xB5, 0x81, 0xB0, 0x70,
+ 0x48, 0x0A, 0x9F, 0x01, 0x22, 0x81, 0x68, 0x92,
+ 0x02, 0x38, 0x46, 0x00, 0xF0, 0x43, 0xFE, 0x00,
+ 0x26, 0x4A, 0xE0, 0x28, 0x20, 0x0D, 0x99, 0x70,
+ 0x43, 0x44, 0x18, 0xA0, 0x68, 0x80, 0x47, 0x6E,
+ 0x48, 0xC0, 0x38, 0x81, 0x68, 0x01, 0x22, 0xC9,
+ 0xB2, 0xD2, 0x02, 0x89, 0x18, 0x81, 0x60, 0x03,
+ 0x98, 0x00, 0x28, 0x09, 0xD0, 0x68, 0x49, 0x80,
+ 0x39, 0x48, 0x6A, 0x03, 0x22, 0x12, 0x07, 0x90,
+ 0x43, 0x04, 0x9A, 0x12, 0x07, 0x10, 0x43, 0x48,
+ 0x62, 0x01, 0x98, 0x00, 0x28, 0x07, 0xD0, 0x62,
+ 0x48, 0x01, 0x68, 0x02, 0x9A, 0x09, 0x0A, 0x09,
+ 0x02, 0x11, 0x43, 0x01, 0x60, 0x02, 0xE0, 0x20,
+ 0x46, 0x00, 0xF0, 0xE1, 0xFB, 0x00, 0x25, 0x15,
+ 0xE0, 0xF9, 0xF7, 0x94, 0xFF, 0x21, 0x69, 0x28,
+ 0x46, 0x88, 0x47, 0xE1, 0x68,
+ 0x00, 0x01, 0x7A, 0x00, 0x80, 0x28, 0x46, 0x88,
+ 0x47, 0x02, 0x46, 0xE9, 0x00, 0x20, 0x6A, 0x69,
+ 0x18, 0x43, 0x18, 0x24, 0x20, 0x01, 0x57, 0x20,
+ 0x68, 0x00, 0xF0, 0x8F, 0xFB, 0x61, 0x69, 0x28,
+ 0x46, 0x88, 0x47, 0x6D, 0x1C, 0x60, 0x68, 0xA8,
+ 0x42, 0xE6, 0xD8, 0xA0, 0x69, 0x00, 0x28, 0x02,
+ 0xD0, 0xE1, 0x69, 0x09, 0x78, 0x01, 0x70, 0x76,
+ 0x1C, 0x0C, 0x98, 0x86, 0x42, 0xB1, 0xD3, 0x00,
+ 0x20, 0x4F, 0x4A, 0x0F, 0x21, 0x83, 0x00, 0x9B,
+ 0x18, 0x19, 0x60, 0x40, 0x1C, 0x41, 0x28, 0xF9,
+ 0xD3, 0x0B, 0x98, 0x00, 0x28, 0x82, 0xD0, 0xB9,
+ 0x1C, 0x3E, 0x48, 0xFD, 0xF7, 0x47, 0xFE, 0x38,
+ 0x80, 0x3B, 0x48, 0x80, 0x68, 0xC4, 0x09, 0x25,
+ 0x46, 0x08, 0x35, 0x05, 0xE0, 0xA0, 0xB2, 0x39,
+ 0x46, 0xFD, 0xF7, 0x80, 0xFE, 0x80, 0x37, 0x64,
+ 0x1C, 0xAC, 0x42, 0xF7, 0xD3, 0x6E, 0xE7, 0x70,
+ 0xB5, 0x05, 0x46, 0x0C, 0x46,
+ 0x00, 0x01, 0x7B, 0x00, 0x80, 0x00, 0xF0, 0x4E,
+ 0xFB, 0x06, 0x46, 0x01, 0x46, 0x28, 0x46, 0x00,
+ 0xF0, 0x3A, 0xFE, 0x20, 0x60, 0x70, 0x43, 0x28,
+ 0x1A, 0x81, 0x07, 0x89, 0x0F, 0x21, 0x61, 0x30,
+ 0x49, 0x60, 0x60, 0x40, 0x31, 0xC9, 0x69, 0x37,
+ 0x4A, 0x02, 0x29, 0x08, 0xD1, 0x11, 0x78, 0x8B,
+ 0x08, 0x9B, 0x00, 0x83, 0x42, 0x02, 0xD9, 0x80,
+ 0x08, 0x80, 0x00, 0x00, 0xE0, 0x08, 0x1F, 0x32,
+ 0x49, 0x09, 0x78, 0x43, 0x18, 0xA3, 0x60, 0x12,
+ 0x78, 0x52, 0x08, 0x82, 0x42, 0x04, 0xD9, 0x24,
+ 0x48, 0x00, 0x6A, 0x40, 0x1E, 0xE0, 0x60, 0x70,
+ 0xBD, 0xE1, 0x60, 0x70, 0xBD, 0x70, 0xB5, 0x86,
+ 0xB0, 0x01, 0xA9, 0xFF, 0xF7, 0xCC, 0xFF, 0x29,
+ 0x4E, 0x03, 0x98, 0x1D, 0x49, 0x80, 0x19, 0x40,
+ 0x31, 0xC9, 0x69, 0x0F, 0x24, 0x22, 0x4D, 0x02,
+ 0x29, 0x4C, 0xD1, 0x19, 0x49, 0x60, 0x31, 0x49,
+ 0x7C, 0x00, 0x29, 0x0A, 0xD0,
+ 0x00, 0x01, 0x7C, 0x00, 0x80, 0x20, 0x49, 0x03,
+ 0x98, 0x09, 0x78, 0x40, 0x1A, 0xC0, 0x1C, 0x80,
+ 0x05, 0x00, 0x0E, 0xFF, 0x21, 0xFA, 0xF7, 0x30,
+ 0xFD, 0x0F, 0xE0, 0x01, 0x78, 0x89, 0x00, 0x49,
+ 0x19, 0x0C, 0x60, 0x41, 0x78, 0x89, 0x00, 0x49,
+ 0x19, 0x0C, 0x60, 0x81, 0x78, 0x89, 0x00, 0x49,
+ 0x19, 0x0C, 0x60, 0xC0, 0x78, 0x80, 0x00, 0x40,
+ 0x19, 0x04, 0x60, 0x15, 0x48, 0x00, 0x78, 0x30,
+ 0x5C, 0x80, 0x00, 0x40, 0x19, 0x04, 0x60, 0x06,
+ 0xB0, 0x70, 0xBD, 0x00, 0x00, 0x80, 0xE2, 0x00,
+ 0x00, 0x34, 0x03, 0x00, 0x20, 0xCE, 0x03, 0x00,
+ 0x00, 0x82, 0xE6, 0x00, 0x00, 0x82, 0xEA, 0x00,
+ 0x00, 0x88, 0xDF, 0x00, 0x00, 0x88, 0x90, 0x00,
+ 0x00, 0xC0, 0x00, 0x11, 0x40, 0xA8, 0x02, 0x00,
+ 0x20, 0xA9, 0x02, 0x00, 0x20, 0xC4, 0x04, 0x00,
+ 0x20, 0xAA, 0x02, 0x00, 0x20, 0x00, 0x02, 0x11,
+ 0x40, 0x00, 0x04, 0x11, 0x40,
+ 0x00, 0x01, 0x7D, 0x00, 0x80, 0x6D, 0x01, 0x00,
+ 0x20, 0x6E, 0x01, 0x00, 0x20, 0xC0, 0xE0, 0x00,
+ 0x00, 0x76, 0x01, 0x00, 0x20, 0x00, 0x78, 0xCD,
+ 0xE7, 0x70, 0xB5, 0xFC, 0x4B, 0xFA, 0x4A, 0xDC,
+ 0x69, 0x12, 0x18, 0xFB, 0x4B, 0x02, 0x2C, 0x26,
+ 0xD1, 0xF8, 0x4C, 0x20, 0x34, 0x64, 0x7C, 0x00,
+ 0x2C, 0x09, 0xD0, 0xF8, 0x4A, 0xC9, 0xB2, 0x12,
+ 0x78, 0x80, 0x1A, 0xC0, 0x1C, 0x00, 0x06, 0x80,
+ 0x0E, 0xFA, 0xF7, 0xDA, 0xFC, 0xC0, 0xE7, 0x08,
+ 0x01, 0x15, 0x78, 0xF3, 0x49, 0xAD, 0x00, 0x0C,
+ 0x58, 0xED, 0x18, 0x2C, 0x60, 0x54, 0x78, 0x40,
+ 0x18, 0xA4, 0x00, 0xE4, 0x18, 0x41, 0x68, 0x21,
+ 0x60, 0x94, 0x78, 0x81, 0x68, 0xA4, 0x00, 0xE4,
+ 0x18, 0x21, 0x60, 0xC0, 0x68, 0xD1, 0x78, 0x89,
+ 0x00, 0xC9, 0x18, 0x08, 0x60, 0xA8, 0xE7, 0x01,
+ 0x20, 0x11, 0x78, 0xF8, 0xE7, 0x00, 0xB5, 0x85,
+ 0xB0, 0x69, 0x46, 0xFF, 0xF7,
+ 0x00, 0x01, 0x7E, 0x00, 0x80, 0x3C, 0xFF, 0x01,
+ 0x98, 0x00, 0x28, 0x02, 0xD1, 0x00, 0x98, 0xFA,
+ 0xF7, 0x3A, 0xFD, 0x03, 0x98, 0xE1, 0x49, 0xC0,
+ 0xB2, 0x08, 0x70, 0xDC, 0x49, 0x09, 0x69, 0x00,
+ 0x29, 0x06, 0xD0, 0xD9, 0x4A, 0x0C, 0x21, 0x10,
+ 0x5C, 0xD9, 0x4A, 0x80, 0x00, 0x80, 0x18, 0x01,
+ 0x60, 0x04, 0x99, 0x02, 0x98, 0xFF, 0xF7, 0xB0,
+ 0xFF, 0x05, 0xB0, 0x00, 0xBD, 0x00, 0xB5, 0x85,
+ 0xB0, 0x69, 0x46, 0xFF, 0xF7, 0x1C, 0xFF, 0x00,
+ 0x98, 0x16, 0x21, 0x48, 0x43, 0xD4, 0x49, 0x08,
+ 0x5A, 0xF2, 0xE7, 0x70, 0xB5, 0x04, 0x46, 0xD3,
+ 0x48, 0x0D, 0x46, 0x40, 0x6A, 0x20, 0x60, 0x00,
+ 0xF0, 0x61, 0xFA, 0xCA, 0x49, 0x40, 0x39, 0xC9,
+ 0x6A, 0x48, 0x43, 0x60, 0x60, 0xCE, 0x48, 0xA0,
+ 0x60, 0xCE, 0x48, 0xE0, 0x60, 0xCE, 0x48, 0x20,
+ 0x61, 0xCE, 0x48, 0x60, 0x61, 0xCE, 0x48, 0xA0,
+ 0x61, 0xA8, 0x1C, 0x0C, 0x35,
+ 0x00, 0x01, 0x7F, 0x00, 0x80, 0x25, 0x62, 0xE0,
+ 0x61, 0x01, 0x20, 0x20, 0x34, 0x20, 0x71, 0x5B,
+ 0xE7, 0x30, 0xB5, 0x0D, 0x46, 0x8F, 0xB0, 0x04,
+ 0x46, 0x01, 0x46, 0x05, 0xA8, 0xFF, 0xF7, 0xD9,
+ 0xFF, 0x05, 0xAA, 0x03, 0x92, 0x00, 0x22, 0x01,
+ 0x21, 0x02, 0x91, 0x01, 0x95, 0x00, 0x94, 0x11,
+ 0x46, 0x10, 0x46, 0x13, 0x46, 0xFF, 0xF7, 0x69,
+ 0xFE, 0x0F, 0xB0, 0x30, 0xBD, 0xF0, 0xB5, 0x8F,
+ 0xB0, 0x06, 0x46, 0x0C, 0x46, 0x15, 0x46, 0x1F,
+ 0x46, 0x11, 0x46, 0x05, 0xA8, 0xFF, 0xF7, 0xC1,
+ 0xFF, 0x05, 0xAA, 0x01, 0x21, 0x03, 0x92, 0x02,
+ 0x91, 0x0A, 0x46, 0x23, 0x46, 0x01, 0x97, 0x00,
+ 0x95, 0x31, 0x46, 0x01, 0x20, 0xFF, 0xF7, 0x51,
+ 0xFE, 0x0F, 0xB0, 0xF0, 0xBD, 0x30, 0xB5, 0xA9,
+ 0x48, 0xB2, 0x49, 0x00, 0x78, 0x09, 0x78, 0xA4,
+ 0x4A, 0x43, 0x18, 0x00, 0x20, 0x02, 0x21, 0xA4,
+ 0x4C, 0x04, 0xE0, 0x15, 0x5C,
+ 0x00, 0x01, 0x80, 0x00, 0x80, 0xAD, 0x00, 0x2D,
+ 0x19, 0x29, 0x60, 0x40, 0x1C, 0x83, 0x42, 0xF8,
+ 0xD8, 0x30, 0xBD, 0x9E, 0x49, 0x10, 0xB5, 0x40,
+ 0x39, 0x09, 0x6B, 0x08, 0x18, 0xFA, 0xF7, 0xB3,
+ 0xFC, 0x10, 0xBD, 0x10, 0xB5, 0x04, 0x46, 0x00,
+ 0x21, 0x02, 0x20, 0xFA, 0xF7, 0xFA, 0xF8, 0x01,
+ 0x19, 0x96, 0x48, 0x40, 0x38, 0x00, 0x6B, 0x08,
+ 0x18, 0x16, 0x21, 0x48, 0x43, 0x98, 0x49, 0x08,
+ 0x5A, 0x10, 0xBD, 0x10, 0xB5, 0xFA, 0xF7, 0x9F,
+ 0xFC, 0x10, 0xBD, 0x10, 0xB5, 0x04, 0x46, 0x00,
+ 0x21, 0x01, 0x20, 0xFA, 0xF7, 0xE6, 0xF8, 0x00,
+ 0x19, 0x16, 0x21, 0x48, 0x43, 0x90, 0x49, 0x08,
+ 0x5A, 0x10, 0xBD, 0xF3, 0xB5, 0x99, 0xB0, 0x04,
+ 0x46, 0x00, 0xF0, 0xDC, 0xF9, 0x87, 0x49, 0x40,
+ 0x39, 0xCA, 0x6A, 0x8C, 0x4D, 0x50, 0x43, 0xAA,
+ 0x6A, 0x05, 0x92, 0x0A, 0x6B, 0x06, 0x92, 0x91,
+ 0x4A, 0x08, 0x92, 0x91, 0x4A,
+ 0x00, 0x01, 0x81, 0x00, 0x80, 0x09, 0x92, 0x8C,
+ 0x4A, 0x8D, 0x4E, 0x52, 0x1C, 0x0B, 0x92, 0x07,
+ 0x96, 0xE2, 0x1C, 0x0C, 0x92, 0xC2, 0x00, 0x82,
+ 0x18, 0x12, 0x19, 0x0C, 0x32, 0x8B, 0x4F, 0x0D,
+ 0x92, 0x0A, 0x97, 0x00, 0x22, 0x08, 0xAB, 0x1A,
+ 0x76, 0xAB, 0x6A, 0x0F, 0x93, 0x4B, 0x6B, 0x10,
+ 0x93, 0x87, 0x4B, 0x12, 0x93, 0x87, 0x4B, 0x13,
+ 0x93, 0x7F, 0x4B, 0x11, 0x96, 0x9B, 0x1C, 0x15,
+ 0x93, 0x23, 0x1D, 0x14, 0x97, 0x16, 0x93, 0x09,
+ 0x6B, 0x18, 0xAB, 0x08, 0x18, 0xC1, 0x00, 0x40,
+ 0x18, 0x00, 0x19, 0x0C, 0x30, 0x17, 0x90, 0x1A,
+ 0x70, 0x1A, 0x98, 0x00, 0x94, 0x05, 0xAA, 0x02,
+ 0x21, 0x01, 0xAC, 0x07, 0xC4, 0x00, 0x22, 0x11,
+ 0x46, 0x10, 0x46, 0x13, 0x46, 0xFF, 0xF7, 0xCD,
+ 0xFD, 0x1B, 0xB0, 0xF0, 0xBD, 0x70, 0x47, 0x70,
+ 0x47, 0x10, 0xB5, 0x00, 0x21, 0x08, 0x20, 0xFA,
+ 0xF7, 0x90, 0xF8, 0x16, 0x21,
+ 0x00, 0x01, 0x82, 0x00, 0x80, 0x48, 0x43, 0x66,
+ 0x49, 0x08, 0x5A, 0x10, 0xBD, 0x10, 0xB5, 0xFA,
+ 0xF7, 0x95, 0xFA, 0xFA, 0xF7, 0x55, 0xFA, 0xFA,
+ 0xF7, 0x9E, 0xFD, 0x10, 0xBD, 0x10, 0xB5, 0xFA,
+ 0xF7, 0x8D, 0xFA, 0x00, 0x20, 0xFA, 0xF7, 0x2F,
+ 0xFC, 0x10, 0xBD, 0xF7, 0xB5, 0x57, 0x48, 0x0C,
+ 0x46, 0x05, 0x6A, 0x00, 0x26, 0x07, 0x46, 0x40,
+ 0x3F, 0xB8, 0x6A, 0x00, 0x28, 0x01, 0xD1, 0x01,
+ 0x20, 0xFE, 0xBD, 0x03, 0x2D, 0x04, 0xD0, 0x01,
+ 0x2D, 0x01, 0xD1, 0x02, 0x25, 0x00, 0xE0, 0x01,
+ 0x25, 0x00, 0xF0, 0x68, 0xF9, 0xF9, 0x6A, 0x48,
+ 0x43, 0xB9, 0x6B, 0x40, 0x18, 0xF9, 0x6B, 0x01,
+ 0x23, 0x41, 0x18, 0xE8, 0x07, 0x4F, 0x4F, 0x5C,
+ 0x4A, 0x00, 0x28, 0x18, 0xD0, 0x38, 0x6B, 0x63,
+ 0x60, 0x20, 0x60, 0x5A, 0x48, 0xE2, 0x60, 0xA0,
+ 0x60, 0x59, 0x48, 0x20, 0x61, 0x59, 0x48, 0x60,
+ 0x61, 0x4D, 0x48, 0x40, 0x1D,
+ 0x00, 0x01, 0x83, 0x00, 0x80, 0xA0, 0x61, 0x02,
+ 0x98, 0xC0, 0x1D, 0xE0, 0x61, 0xC8, 0x00, 0x02,
+ 0x9E, 0x08, 0x18, 0x80, 0x19, 0x0C, 0x30, 0x20,
+ 0x62, 0x24, 0x20, 0x03, 0x55, 0x01, 0x26, 0xA8,
+ 0x07, 0x1D, 0xD5, 0x3D, 0x6B, 0x30, 0x46, 0x28,
+ 0x27, 0x78, 0x43, 0x25, 0x50, 0x00, 0x19, 0x43,
+ 0x60, 0x4D, 0x4B, 0x83, 0x60, 0xC2, 0x60, 0x4A,
+ 0x4A, 0x02, 0x61, 0x4A, 0x4A, 0x42, 0x61, 0x3E,
+ 0x4A, 0x92, 0x1D, 0x82, 0x61, 0x02, 0x9A, 0x08,
+ 0x32, 0xC2, 0x61, 0xCA, 0x00, 0x8A, 0x18, 0x02,
+ 0x99, 0x51, 0x18, 0x15, 0x31, 0x01, 0x62, 0x00,
+ 0x21, 0x20, 0x30, 0x01, 0x71, 0x76, 0x1C, 0x00,
+ 0x98, 0x06, 0x60, 0x00, 0x20, 0xFE, 0xBD, 0x30,
+ 0xB5, 0x99, 0xB0, 0x04, 0x46, 0x0D, 0x46, 0x02,
+ 0x46, 0x05, 0xA9, 0x04, 0xA8, 0xFF, 0xF7, 0x99,
+ 0xFF, 0x00, 0x28, 0x0B, 0xD1, 0x05, 0xAA, 0x03,
+ 0x92, 0x00, 0x22, 0x04, 0x99,
+ 0x00, 0x01, 0x84, 0x00, 0x80, 0x02, 0x91, 0x01,
+ 0x95, 0x00, 0x94, 0x11, 0x46, 0x10, 0x46, 0x13,
+ 0x46, 0xFF, 0xF7, 0x3B, 0xFD, 0x19, 0xB0, 0x30,
+ 0xBD, 0xF0, 0xB5, 0x99, 0xB0, 0x05, 0x46, 0x0C,
+ 0x46, 0x16, 0x46, 0x1F, 0x46, 0x05, 0xA9, 0x04,
+ 0xA8, 0xFF, 0xF7, 0x7F, 0xFF, 0x00, 0x28, 0x0B,
+ 0xD1, 0x05, 0xAA, 0x04, 0x99, 0x03, 0x92, 0x02,
+ 0x91, 0x01, 0x22, 0x23, 0x46, 0x01, 0x97, 0x00,
+ 0x96, 0x29, 0x46, 0x10, 0x46, 0xFF, 0xF7, 0x21,
+ 0xFD, 0x19, 0xB0, 0xF0, 0xBD, 0xF0, 0xB5, 0x00,
+ 0x23, 0x8C, 0x46, 0x06, 0x46, 0x25, 0x49, 0x18,
+ 0x46, 0x1D, 0x46, 0x1C, 0x46, 0xD7, 0x07, 0x03,
+ 0xD0, 0x5F, 0x00, 0xCF, 0x5F, 0x7D, 0x19, 0x64,
+ 0x1C, 0x5B, 0x1C, 0x52, 0x08, 0xF6, 0xD1, 0x20,
+ 0x4A, 0xA1, 0x00, 0x51, 0x58, 0x62, 0x46, 0x69,
+ 0x43, 0x09, 0x12, 0x00, 0x2A, 0x3A, 0xD0, 0xB1,
+ 0x42, 0x00, 0xDD, 0x01, 0x20,
+ 0x00, 0x01, 0x85, 0x00, 0x80, 0xF0, 0xBD, 0x00,
+ 0x00, 0xC0, 0xE0, 0x00, 0x00, 0xC8, 0xDF, 0x00,
+ 0x00, 0x00, 0x04, 0x11, 0x40, 0x6E, 0x01, 0x00,
+ 0x20, 0x98, 0xCD, 0x00, 0x00, 0x76, 0x01, 0x00,
+ 0x20, 0x2C, 0xE1, 0x00, 0x00, 0x54, 0xE0, 0x00,
+ 0x00, 0x63, 0x62, 0x00, 0x00, 0x39, 0xBF, 0x00,
+ 0x00, 0xF9, 0xBE, 0x00, 0x00, 0xD9, 0xBD, 0x00,
+ 0x00, 0x34, 0x03, 0x00, 0x20, 0x6D, 0x01, 0x00,
+ 0x20, 0x15, 0x64, 0x00, 0x00, 0x47, 0xC0, 0x00,
+ 0x00, 0x3F, 0xC0, 0x00, 0x00, 0xE9, 0xBF, 0x00,
+ 0x00, 0x1F, 0xC0, 0x00, 0x00, 0x0F, 0xC0, 0x00,
+ 0x00, 0xF5, 0xC0, 0x00, 0x00, 0x19, 0xC1, 0x00,
+ 0x00, 0xF3, 0xC0, 0x00, 0x00, 0xF1, 0xC0, 0x00,
+ 0x00, 0x09, 0xC1, 0x00, 0x00, 0xC4, 0x04, 0x00,
+ 0x20, 0x38, 0xCF, 0x00, 0x00, 0xB1, 0x42, 0xC4,
+ 0xDB, 0xC4, 0xE7, 0x70, 0xB5, 0x0C, 0x46, 0x95,
+ 0x49, 0x15, 0x46, 0x8A, 0x68,
+ 0x00, 0x01, 0x86, 0x00, 0x80, 0x01, 0x23, 0xD2,
+ 0xB2, 0xDB, 0x02, 0xD2, 0x18, 0x8A, 0x60, 0x01,
+ 0x46, 0x91, 0x48, 0x00, 0x78, 0xF9, 0xF7, 0x85,
+ 0xFF, 0x16, 0x21, 0x48, 0x43, 0x8F, 0x49, 0x0A,
+ 0x5A, 0x21, 0x46, 0x28, 0x46, 0x8E, 0x4B, 0xFF,
+ 0xF7, 0x79, 0xFC, 0xC0, 0xB2, 0x8C, 0xE5, 0x70,
+ 0xB5, 0xF9, 0xF7, 0x99, 0xFF, 0x8B, 0x48, 0x00,
+ 0x25, 0x00, 0x78, 0x40, 0x08, 0x84, 0x08, 0xA4,
+ 0x00, 0x28, 0x46, 0xFA, 0xF7, 0x20, 0xFB, 0x20,
+ 0x46, 0xFA, 0xF7, 0x80, 0xFA, 0x86, 0x48, 0x01,
+ 0x78, 0x08, 0x19, 0x00, 0x21, 0xFF, 0xF7, 0xA0,
+ 0xFD, 0x84, 0x48, 0xC0, 0x7B, 0xFA, 0xF7, 0xBF,
+ 0xFA, 0x83, 0x48, 0x42, 0x6A, 0x01, 0x21, 0x28,
+ 0x46, 0xFF, 0xF7, 0xC7, 0xFF, 0x6C, 0xE5, 0x10,
+ 0xB5, 0xFA, 0xF7, 0x52, 0xF8, 0x7D, 0x48, 0x60,
+ 0x38, 0x00, 0x6B, 0x44, 0x08, 0x20, 0x46, 0xFA,
+ 0xF7, 0x65, 0xFA, 0x20, 0x46,
+ 0x00, 0x01, 0x87, 0x00, 0x80, 0xFA, 0xF7, 0xFF,
+ 0xFA, 0x72, 0x48, 0x00, 0x68, 0x00, 0x28, 0x03,
+ 0xD0, 0x76, 0x48, 0xC0, 0x7B, 0xFA, 0xF7, 0xA3,
+ 0xFA, 0x75, 0x48, 0x82, 0x6A, 0x00, 0x21, 0x20,
+ 0x46, 0xFF, 0xF7, 0xAB, 0xFF, 0x10, 0xBD, 0x10,
+ 0xB5, 0xFA, 0xF7, 0x36, 0xF8, 0x6F, 0x48, 0x60,
+ 0x38, 0x01, 0x6B, 0x40, 0x6B, 0x40, 0x08, 0x0C,
+ 0x18, 0x20, 0x46, 0xFA, 0xF7, 0x47, 0xFA, 0x20,
+ 0x46, 0xFA, 0xF7, 0xE1, 0xFA, 0x63, 0x48, 0x00,
+ 0x68, 0x00, 0x28, 0x03, 0xD0, 0x67, 0x48, 0xC0,
+ 0x7B, 0xFA, 0xF7, 0x85, 0xFA, 0x66, 0x48, 0x82,
+ 0x6A, 0x00, 0x21, 0x20, 0x46, 0xFF, 0xF7, 0x8D,
+ 0xFF, 0x10, 0xBD, 0x10, 0xB5, 0xFA, 0xF7, 0x2A,
+ 0xF9, 0x00, 0x20, 0xFA, 0xF7, 0x2F, 0xFA, 0x00,
+ 0x20, 0xFA, 0xF7, 0xC9, 0xFA, 0x5E, 0x48, 0x02,
+ 0x6B, 0x01, 0x21, 0x00, 0x20, 0xFF, 0xF7, 0x7D,
+ 0xFF, 0x10, 0xBD, 0x10, 0xB5,
+ 0x00, 0x01, 0x88, 0x00, 0x80, 0xFA, 0xF7, 0x1A,
+ 0xF9, 0xFA, 0xF7, 0xDA, 0xF8, 0xFA, 0xF7, 0x23,
+ 0xFC, 0x01, 0x20, 0xFA, 0xF7, 0x1B, 0xFA, 0x56,
+ 0x48, 0x02, 0x6B, 0x00, 0x21, 0x08, 0x46, 0xFF,
+ 0xF7, 0x6C, 0xFF, 0x10, 0xBD, 0x51, 0x49, 0x4F,
+ 0x48, 0x20, 0x39, 0x00, 0x78, 0xC9, 0x69, 0x02,
+ 0x29, 0x02, 0xD1, 0xC0, 0x1C, 0x80, 0x08, 0x80,
+ 0x00, 0x70, 0x47, 0xFF, 0xB5, 0x06, 0x46, 0x81,
+ 0xB0, 0xD0, 0xB2, 0x03, 0x90, 0x49, 0x48, 0x0F,
+ 0x46, 0x1D, 0x46, 0xC0, 0x7B, 0xFA, 0xF7, 0x47,
+ 0xFA, 0x00, 0x20, 0x01, 0x46, 0x29, 0x54, 0x40,
+ 0x1C, 0x09, 0x28, 0xFB, 0xD3, 0x3D, 0x48, 0x80,
+ 0x30, 0x41, 0x63, 0x10, 0x24, 0x3B, 0x4A, 0x00,
+ 0x20, 0x80, 0x32, 0x29, 0x5C, 0x21, 0x43, 0x0B,
+ 0x02, 0x0B, 0x43, 0x81, 0x00, 0x89, 0x18, 0x4B,
+ 0x61, 0x40, 0x1C, 0x08, 0x28, 0xF5, 0xD3, 0x03,
+ 0x98, 0xFF, 0xF7, 0x61, 0xFB,
+ 0x00, 0x01, 0x89, 0x00, 0x80, 0x00, 0x20, 0x3B,
+ 0x4B, 0x03, 0x99, 0x0F, 0xE0, 0xCA, 0x07, 0x0B,
+ 0xD0, 0x42, 0x00, 0x9A, 0x5E, 0x00, 0x2F, 0x02,
+ 0xD0, 0xB2, 0x42, 0x05, 0xDC, 0x01, 0xE0, 0xB2,
+ 0x42, 0x02, 0xDB, 0x2A, 0x5C, 0x22, 0x43, 0x2A,
+ 0x54, 0x49, 0x08, 0x40, 0x1C, 0x00, 0x29, 0xED,
+ 0xD1, 0x64, 0x08, 0xD7, 0xD1, 0x62, 0xE4, 0xFE,
+ 0xB5, 0x04, 0x46, 0x26, 0x4A, 0x00, 0x20, 0x2E,
+ 0x49, 0x80, 0x32, 0x83, 0x00, 0x9B, 0x18, 0x59,
+ 0x61, 0x40, 0x1C, 0x09, 0x28, 0xF9, 0xD3, 0x27,
+ 0x48, 0x20, 0x38, 0x00, 0x69, 0x01, 0x28, 0x01,
+ 0xD0, 0x00, 0x20, 0x50, 0x63, 0x00, 0x27, 0xFE,
+ 0x26, 0x20, 0x46, 0x20, 0x30, 0x3D, 0x46, 0x01,
+ 0x90, 0x22, 0xE0, 0xF9, 0xF7, 0x9B, 0xFB, 0x21,
+ 0x69, 0x28, 0x46, 0x88, 0x47, 0xE1, 0x68, 0x28,
+ 0x46, 0x88, 0x47, 0x00, 0x90, 0x01, 0x98, 0x04,
+ 0x21, 0x41, 0x56, 0x20, 0x68,
+ 0x00, 0x01, 0x8A, 0x00, 0x80, 0x1D, 0x4B, 0x00,
+ 0x9A, 0xFF, 0xF7, 0x88, 0xFB, 0xB8, 0x42, 0x00,
+ 0xD9, 0x07, 0x46, 0x01, 0x98, 0x04, 0x21, 0x41,
+ 0x56, 0x20, 0x68, 0x19, 0x4B, 0x00, 0x9A, 0xFF,
+ 0xF7, 0x7D, 0xFB, 0xB0, 0x42, 0x00, 0xD2, 0x06,
+ 0x46, 0x61, 0x69, 0x28, 0x46, 0x88, 0x47, 0x6D,
+ 0x1C, 0x60, 0x68, 0xA8, 0x42, 0xD9, 0xD8, 0xB8,
+ 0x19, 0x40, 0x08, 0xFE, 0x21, 0x08, 0x40, 0xE1,
+ 0x69, 0x08, 0x70, 0x04, 0x49, 0xC0, 0x31, 0x0A,
+ 0x68, 0x12, 0x0A, 0x12, 0x02, 0x02, 0x43, 0x0A,
+ 0x60, 0xFE, 0xBD, 0x00, 0x00, 0x00, 0x00, 0x11,
+ 0x40, 0x78, 0x01, 0x00, 0x20, 0x2C, 0xE1, 0x00,
+ 0x00, 0x49, 0xC2, 0x00, 0x00, 0x6D, 0x01, 0x00,
+ 0x20, 0x6E, 0x01, 0x00, 0x20, 0xE8, 0xDF, 0x00,
+ 0x00, 0x54, 0xE0, 0x00, 0x00, 0xC4, 0x04, 0x00,
+ 0x20, 0x0F, 0x0F, 0x00, 0x00, 0x5D, 0xBC, 0x00,
+ 0x00, 0xEF, 0xBB, 0x00, 0x00,
+ 0x00, 0x01, 0x8B, 0x00, 0x80, 0x70, 0x47, 0x10,
+ 0xB5, 0xFD, 0xF7, 0xAE, 0xF9, 0x56, 0x48, 0x00,
+ 0x68, 0xFA, 0xF7, 0x72, 0xFD, 0xFB, 0xF7, 0xAA,
+ 0xF9, 0x54, 0x49, 0x01, 0x20, 0x08, 0x70, 0x48,
+ 0x70, 0x10, 0xBD, 0xF8, 0xB5, 0x51, 0x4E, 0x07,
+ 0x46, 0x00, 0x24, 0x70, 0x78, 0x25, 0x46, 0x00,
+ 0x28, 0x09, 0xD1, 0x4F, 0x49, 0x70, 0x68, 0x09,
+ 0x6A, 0x38, 0x1A, 0x88, 0x42, 0x48, 0xD9, 0xFD,
+ 0xF7, 0xF7, 0xF9, 0x00, 0x28, 0x44, 0xD1, 0x00,
+ 0x20, 0x77, 0x60, 0x70, 0x70, 0x49, 0x48, 0x86,
+ 0x6A, 0x40, 0x30, 0x07, 0x6A, 0x02, 0x2F, 0x01,
+ 0xD0, 0x03, 0x2F, 0x1A, 0xD1, 0x44, 0x4A, 0x00,
+ 0x20, 0x40, 0x32, 0x0C, 0xE0, 0x44, 0x49, 0x43,
+ 0x00, 0xC9, 0x5E, 0x1C, 0x23, 0xD3, 0x5E, 0x99,
+ 0x42, 0x03, 0xDC, 0x1E, 0x23, 0xD3, 0x5E, 0x99,
+ 0x42, 0x00, 0xDA, 0x64, 0x1C, 0x40, 0x1C, 0xB0,
+ 0x42, 0xF0, 0xD3, 0x00, 0x2C,
+ 0x00, 0x01, 0x8C, 0x00, 0x80, 0x05, 0xD0, 0xFF,
+ 0xF7, 0xEC, 0xFE, 0x3C, 0x49, 0x08, 0x70, 0xFB,
+ 0xF7, 0x6D, 0xF9, 0x01, 0x2F, 0x01, 0xD0, 0x03,
+ 0x2F, 0x1A, 0xD1, 0x35, 0x4A, 0x00, 0x20, 0x38,
+ 0x4B, 0x60, 0x32, 0x0B, 0xE0, 0x41, 0x00, 0x00,
+ 0x24, 0x59, 0x5E, 0x14, 0x5F, 0xA1, 0x42, 0x03,
+ 0xDC, 0x02, 0x24, 0x14, 0x5F, 0xA1, 0x42, 0x00,
+ 0xDA, 0x6D, 0x1C, 0x40, 0x1C, 0xB0, 0x42, 0xF1,
+ 0xD3, 0x00, 0x2D, 0x05, 0xD0, 0xFF, 0xF7, 0xDD,
+ 0xFE, 0x2E, 0x49, 0x08, 0x70, 0xFB, 0xF7, 0x4E,
+ 0xF9, 0xF8, 0xBD, 0xF1, 0xB5, 0x82, 0xB0, 0xFD,
+ 0xF7, 0xC1, 0xF9, 0x23, 0x4E, 0x23, 0x4F, 0x01,
+ 0x25, 0x01, 0x90, 0x62, 0xB6, 0x38, 0x78, 0x01,
+ 0x28, 0x14, 0xD0, 0x02, 0x28, 0x1D, 0xD0, 0x03,
+ 0x28, 0x36, 0xD1, 0x30, 0x68, 0xFA, 0xF7, 0x86,
+ 0xFF, 0xFB, 0xF7, 0xAE, 0xF9, 0xFD, 0xF7, 0x38,
+ 0xF9, 0x1B, 0x48, 0x3D, 0x70,
+ 0x00, 0x01, 0x8D, 0x00, 0x80, 0xC0, 0x69, 0x01,
+ 0x28, 0x02, 0xD1, 0x02, 0x98, 0xFF, 0xF7, 0x89,
+ 0xFF, 0x00, 0x24, 0x14, 0xE0, 0x30, 0x68, 0xFA,
+ 0xF7, 0xEF, 0xFC, 0xF9, 0xF7, 0xCF, 0xFF, 0xFA,
+ 0xF7, 0x21, 0xFB, 0x02, 0x20, 0x38, 0x70, 0x2C,
+ 0x46, 0x09, 0xE0, 0x01, 0x24, 0xFA, 0xF7, 0x93,
+ 0xFB, 0x01, 0x28, 0x04, 0xD1, 0xF9, 0xF7, 0x88,
+ 0xFD, 0x03, 0x20, 0x38, 0x70, 0xC4, 0x07, 0x72,
+ 0xB6, 0xE0, 0x07, 0x05, 0xD0, 0xFA, 0xF7, 0x87,
+ 0xFB, 0x01, 0x28, 0x01, 0xD1, 0xC0, 0x07, 0x04,
+ 0x43, 0x00, 0x2C, 0xC6, 0xDB, 0x01, 0x98, 0xC0,
+ 0xB2, 0xFD, 0xF7, 0x84, 0xF9, 0x20, 0x46, 0xFE,
+ 0xBD, 0xF9, 0xF7, 0x8E, 0xFD, 0x3D, 0x70, 0xD3,
+ 0xE7, 0x7C, 0x02, 0x00, 0x20, 0x40, 0x03, 0x00,
+ 0x20, 0x78, 0xDC, 0x00, 0x00, 0x88, 0xDF, 0x00,
+ 0x00, 0x1C, 0x02, 0x00, 0x20, 0x39, 0x03, 0x00,
+ 0x20, 0x24, 0x02, 0x00, 0x20,
+ 0x00, 0x01, 0x8E, 0x00, 0x80, 0x3A, 0x03, 0x00,
+ 0x20, 0x0C, 0x49, 0xCA, 0x68, 0x03, 0x23, 0x1B,
+ 0x02, 0x9A, 0x43, 0x00, 0x02, 0x02, 0x43, 0xCA,
+ 0x60, 0x70, 0x47, 0x08, 0x49, 0x4A, 0x69, 0x0F,
+ 0x23, 0x1B, 0x04, 0x9A, 0x43, 0x00, 0x04, 0x02,
+ 0x43, 0x4A, 0x61, 0x70, 0x47, 0x03, 0x49, 0x8A,
+ 0x69, 0x10, 0x23, 0x9A, 0x43, 0x00, 0x01, 0x02,
+ 0x43, 0x8A, 0x61, 0x70, 0x47, 0x00, 0x00, 0x14,
+ 0x40, 0x10, 0xB5, 0x02, 0x78, 0x2B, 0x49, 0x2C,
+ 0x4C, 0x40, 0x78, 0x01, 0x2A, 0x18, 0xD1, 0x40,
+ 0x00, 0x08, 0x62, 0x48, 0x69, 0x30, 0x22, 0x90,
+ 0x43, 0x02, 0x22, 0x10, 0x43, 0x48, 0x61, 0x01,
+ 0x20, 0x00, 0xF0, 0xB6, 0xF8, 0x01, 0x20, 0x00,
+ 0xF0, 0x9F, 0xF8, 0x04, 0x20, 0x00, 0xF0, 0xB9,
+ 0xF8, 0x04, 0x20, 0x00, 0xF0, 0xA2, 0xF8, 0x20,
+ 0x68, 0x80, 0x08, 0x80, 0x00, 0x40, 0x1C, 0x15,
+ 0xE0, 0x4A, 0x69, 0x32, 0x23,
+ 0x00, 0x01, 0x8F, 0x00, 0x80, 0x9A, 0x43, 0x00,
+ 0x01, 0x02, 0x43, 0x4A, 0x61, 0x01, 0x20, 0x00,
+ 0xF0, 0xA8, 0xF8, 0x01, 0x20, 0x00, 0xF0, 0x91,
+ 0xF8, 0x06, 0x20, 0x00, 0xF0, 0xB7, 0xF8, 0x01,
+ 0x20, 0x00, 0xF0, 0xA8, 0xF8, 0x20, 0x68, 0x80,
+ 0x08, 0x80, 0x00, 0x80, 0x1C, 0x20, 0x60, 0x10,
+ 0xBD, 0x10, 0xB5, 0x10, 0x48, 0x41, 0x69, 0x41,
+ 0x61, 0x02, 0x21, 0x41, 0x62, 0x00, 0x21, 0xC1,
+ 0x62, 0x81, 0x62, 0xFF, 0x21, 0xC1, 0x60, 0x01,
+ 0x21, 0x01, 0x61, 0x03, 0x20, 0xF6, 0xF7, 0x23,
+ 0xFF, 0x03, 0x21, 0x08, 0x46, 0xF6, 0xF7, 0x08,
+ 0xFF, 0x08, 0x49, 0x03, 0x20, 0xF6, 0xF7, 0xFA,
+ 0xFE, 0x03, 0x20, 0xF6, 0xF7, 0x11, 0xFF, 0x10,
+ 0xBD, 0x05, 0x4A, 0x80, 0x00, 0x80, 0x18, 0x01,
+ 0x60, 0x70, 0x47, 0xFE, 0xE7, 0x00, 0x00, 0x12,
+ 0x40, 0x00, 0x20, 0x14, 0x40, 0x41, 0xC8, 0x00,
+ 0x00, 0x00, 0x10, 0x12, 0x40,
+ 0x00, 0x01, 0x90, 0x00, 0x80, 0x0E, 0x4A, 0x11,
+ 0x68, 0xEF, 0x23, 0xC0, 0x07, 0x19, 0x40, 0xC0,
+ 0x0E, 0x08, 0x43, 0x10, 0x60, 0x70, 0x47, 0x0A,
+ 0x49, 0x8A, 0x68, 0x07, 0x23, 0x1B, 0x03, 0x9A,
+ 0x43, 0x00, 0x03, 0x02, 0x43, 0x8A, 0x60, 0x70,
+ 0x47, 0x05, 0x48, 0x40, 0x68, 0xC0, 0x06, 0xC0,
+ 0x0F, 0x70, 0x47, 0x03, 0x49, 0x08, 0x69, 0x10,
+ 0x22, 0x10, 0x40, 0x08, 0x61, 0x00, 0x09, 0x70,
+ 0x47, 0x00, 0x00, 0x14, 0x40, 0x70, 0xB5, 0x15,
+ 0x49, 0xC8, 0x68, 0x15, 0x4D, 0xC8, 0x60, 0x09,
+ 0x69, 0x14, 0x4C, 0x01, 0x40, 0x29, 0x60, 0x88,
+ 0x07, 0x01, 0xD5, 0x20, 0x68, 0x80, 0x47, 0x28,
+ 0x68, 0x40, 0x07, 0x01, 0xD5, 0x60, 0x68, 0x80,
+ 0x47, 0x28, 0x68, 0x00, 0x07, 0x01, 0xD5, 0xA0,
+ 0x68, 0x80, 0x47, 0x28, 0x68, 0xC0, 0x06, 0x01,
+ 0xD5, 0xE0, 0x68, 0x80, 0x47, 0x28, 0x68, 0x80,
+ 0x06, 0x01, 0xD5, 0x20, 0x69,
+ 0x00, 0x01, 0x91, 0x00, 0x80, 0x80, 0x47, 0x28,
+ 0x68, 0x40, 0x06, 0x01, 0xD5, 0x60, 0x69, 0x80,
+ 0x47, 0x28, 0x68, 0x00, 0x06, 0x01, 0xD5, 0xA0,
+ 0x69, 0x80, 0x47, 0x70, 0xBD, 0x00, 0x00, 0x12,
+ 0x40, 0x48, 0x03, 0x00, 0x20, 0x0C, 0xD0, 0x00,
+ 0x00, 0x08, 0x4A, 0x11, 0x68, 0xFD, 0x23, 0xC0,
+ 0x07, 0x19, 0x40, 0x80, 0x0F, 0x08, 0x43, 0x10,
+ 0x60, 0x70, 0x47, 0x04, 0x49, 0x8A, 0x68, 0x38,
+ 0x23, 0x9A, 0x43, 0xC0, 0x00, 0x02, 0x43, 0x8A,
+ 0x60, 0x70, 0x47, 0x00, 0x00, 0x00, 0x00, 0x14,
+ 0x40, 0x07, 0x4A, 0x11, 0x68, 0xFE, 0x23, 0xC0,
+ 0x07, 0x19, 0x40, 0xC0, 0x0F, 0x08, 0x43, 0x10,
+ 0x60, 0x70, 0x47, 0x03, 0x49, 0x8A, 0x68, 0xD2,
+ 0x08, 0xD2, 0x00, 0x02, 0x43, 0x8A, 0x60, 0x70,
+ 0x47, 0x00, 0x00, 0x14, 0x40, 0x04, 0x49, 0x8A,
+ 0x68, 0x07, 0x23, 0x5B, 0x02, 0x9A, 0x43, 0x40,
+ 0x02, 0x02, 0x43, 0x8A, 0x60,
+ 0x00, 0x01, 0x92, 0x00, 0x80, 0x70, 0x47, 0x00,
+ 0x00, 0x00, 0x00, 0x14, 0x40, 0x04, 0x49, 0x8A,
+ 0x68, 0xFF, 0x23, 0xC1, 0x33, 0x9A, 0x43, 0x80,
+ 0x01, 0x02, 0x43, 0x8A, 0x60, 0x70, 0x47, 0x00,
+ 0x00, 0x00, 0x00, 0x14, 0x40, 0xF8, 0xB5, 0x04,
+ 0x2A, 0x2C, 0xD3, 0x83, 0x07, 0x12, 0xD0, 0x0B,
+ 0x78, 0x49, 0x1C, 0x03, 0x70, 0x40, 0x1C, 0x52,
+ 0x1E, 0x83, 0x07, 0x0B, 0xD0, 0x0B, 0x78, 0x49,
+ 0x1C, 0x03, 0x70, 0x40, 0x1C, 0x52, 0x1E, 0x83,
+ 0x07, 0x04, 0xD0, 0x0B, 0x78, 0x49, 0x1C, 0x03,
+ 0x70, 0x40, 0x1C, 0x52, 0x1E, 0x8B, 0x07, 0x9B,
+ 0x0F, 0x02, 0xD1, 0xF4, 0xF7, 0xED, 0xFC, 0xF8,
+ 0xBD, 0xC9, 0x1A, 0xDE, 0x00, 0x20, 0x23, 0x9D,
+ 0x1B, 0x08, 0xC9, 0x07, 0xE0, 0xF3, 0x40, 0x1C,
+ 0x46, 0x08, 0xC9, 0x1F, 0x46, 0xAF, 0x40, 0x27,
+ 0x43, 0x80, 0xC0, 0x12, 0x1F, 0x04, 0x2A, 0xF5,
+ 0xD2, 0xEB, 0x08, 0xC9, 0x1A,
+ 0x00, 0x01, 0x93, 0x00, 0x80, 0x52, 0x1E, 0xEA,
+ 0xD4, 0x0B, 0x78, 0x49, 0x1C, 0x03, 0x70, 0x40,
+ 0x1C, 0x52, 0x1E, 0xE4, 0xD4, 0x0B, 0x78, 0x49,
+ 0x1C, 0x03, 0x70, 0x40, 0x1C, 0x52, 0x1E, 0xDE,
+ 0xD4, 0x09, 0x78, 0x01, 0x70, 0xF8, 0xBD, 0x01,
+ 0xE0, 0x04, 0xC0, 0x09, 0x1F, 0x04, 0x29, 0xFB,
+ 0xD2, 0x8B, 0x07, 0x01, 0xD5, 0x02, 0x80, 0x80,
+ 0x1C, 0xC9, 0x07, 0x00, 0xD0, 0x02, 0x70, 0x70,
+ 0x47, 0x00, 0x29, 0x0B, 0xD0, 0xC3, 0x07, 0x02,
+ 0xD0, 0x02, 0x70, 0x40, 0x1C, 0x49, 0x1E, 0x02,
+ 0x29, 0x04, 0xD3, 0x83, 0x07, 0x02, 0xD5, 0x02,
+ 0x80, 0x80, 0x1C, 0x89, 0x1E, 0xE3, 0xE7, 0x00,
+ 0x22, 0xEE, 0xE7, 0x00, 0x22, 0xDF, 0xE7, 0x82,
+ 0x08, 0x81, 0x07, 0x92, 0x00, 0xC9, 0x0E, 0x0C,
+ 0xCA, 0xC0, 0x78, 0xCA, 0x40, 0x49, 0x42, 0x20,
+ 0x31, 0x8B, 0x40, 0x1A, 0x43, 0x11, 0x02, 0x09,
+ 0x0A, 0x00, 0x06, 0x08, 0x43,
+ 0x00, 0x01, 0x94, 0x00, 0x80, 0x70, 0x47, 0x00,
+ 0x22, 0x03, 0x09, 0x8B, 0x42, 0x2C, 0xD3, 0x03,
+ 0x0A, 0x8B, 0x42, 0x11, 0xD3, 0x00, 0x23, 0x9C,
+ 0x46, 0x4E, 0xE0, 0x03, 0x46, 0x0B, 0x43, 0x3C,
+ 0xD4, 0x00, 0x22, 0x43, 0x08, 0x8B, 0x42, 0x31,
+ 0xD3, 0x03, 0x09, 0x8B, 0x42, 0x1C, 0xD3, 0x03,
+ 0x0A, 0x8B, 0x42, 0x01, 0xD3, 0x94, 0x46, 0x3F,
+ 0xE0, 0xC3, 0x09, 0x8B, 0x42, 0x01, 0xD3, 0xCB,
+ 0x01, 0xC0, 0x1A, 0x52, 0x41, 0x83, 0x09, 0x8B,
+ 0x42, 0x01, 0xD3, 0x8B, 0x01, 0xC0, 0x1A, 0x52,
+ 0x41, 0x43, 0x09, 0x8B, 0x42, 0x01, 0xD3, 0x4B,
+ 0x01, 0xC0, 0x1A, 0x52, 0x41, 0x03, 0x09, 0x8B,
+ 0x42, 0x01, 0xD3, 0x0B, 0x01, 0xC0, 0x1A, 0x52,
+ 0x41, 0xC3, 0x08, 0x8B, 0x42, 0x01, 0xD3, 0xCB,
+ 0x00, 0xC0, 0x1A, 0x52, 0x41, 0x83, 0x08, 0x8B,
+ 0x42, 0x01, 0xD3, 0x8B, 0x00, 0xC0, 0x1A, 0x52,
+ 0x41, 0x43, 0x08, 0x8B, 0x42,
+ 0x00, 0x01, 0x95, 0x00, 0x80, 0x01, 0xD3, 0x4B,
+ 0x00, 0xC0, 0x1A, 0x52, 0x41, 0x41, 0x1A, 0x00,
+ 0xD2, 0x01, 0x46, 0x52, 0x41, 0x10, 0x46, 0x70,
+ 0x47, 0x5D, 0xE0, 0xCA, 0x0F, 0x00, 0xD0, 0x49,
+ 0x42, 0x03, 0x10, 0x00, 0xD3, 0x40, 0x42, 0x53,
+ 0x40, 0x00, 0x22, 0x9C, 0x46, 0x03, 0x09, 0x8B,
+ 0x42, 0x2D, 0xD3, 0x03, 0x0A, 0x8B, 0x42, 0x12,
+ 0xD3, 0xFC, 0x22, 0x89, 0x01, 0x12, 0xBA, 0x03,
+ 0x0A, 0x8B, 0x42, 0x0C, 0xD3, 0x89, 0x01, 0x92,
+ 0x11, 0x8B, 0x42, 0x08, 0xD3, 0x89, 0x01, 0x92,
+ 0x11, 0x8B, 0x42, 0x04, 0xD3, 0x89, 0x01, 0x3A,
+ 0xD0, 0x92, 0x11, 0x00, 0xE0, 0x89, 0x09, 0xC3,
+ 0x09, 0x8B, 0x42, 0x01, 0xD3, 0xCB, 0x01, 0xC0,
+ 0x1A, 0x52, 0x41, 0x83, 0x09, 0x8B, 0x42, 0x01,
+ 0xD3, 0x8B, 0x01, 0xC0, 0x1A, 0x52, 0x41, 0x43,
+ 0x09, 0x8B, 0x42, 0x01, 0xD3, 0x4B, 0x01, 0xC0,
+ 0x1A, 0x52, 0x41, 0x03, 0x09,
+ 0x00, 0x01, 0x96, 0x00, 0x80, 0x8B, 0x42, 0x01,
+ 0xD3, 0x0B, 0x01, 0xC0, 0x1A, 0x52, 0x41, 0xC3,
+ 0x08, 0x8B, 0x42, 0x01, 0xD3, 0xCB, 0x00, 0xC0,
+ 0x1A, 0x52, 0x41, 0x83, 0x08, 0x8B, 0x42, 0x01,
+ 0xD3, 0x8B, 0x00, 0xC0, 0x1A, 0x52, 0x41, 0xD9,
+ 0xD2, 0x43, 0x08, 0x8B, 0x42, 0x01, 0xD3, 0x4B,
+ 0x00, 0xC0, 0x1A, 0x52, 0x41, 0x41, 0x1A, 0x00,
+ 0xD2, 0x01, 0x46, 0x63, 0x46, 0x52, 0x41, 0x5B,
+ 0x10, 0x10, 0x46, 0x01, 0xD3, 0x40, 0x42, 0x00,
+ 0x2B, 0x00, 0xD5, 0x49, 0x42, 0x70, 0x47, 0x63,
+ 0x46, 0x5B, 0x10, 0x00, 0xD3, 0x40, 0x42, 0x01,
+ 0xB5, 0x00, 0x20, 0xC0, 0x46, 0xC0, 0x46, 0x02,
+ 0xBD, 0x04, 0x46, 0xC0, 0x46, 0xC0, 0x46, 0x20,
+ 0x46, 0xF4, 0xF7, 0xDA, 0xFB, 0x02, 0x48, 0x03,
+ 0x49, 0xAB, 0xBE, 0x70, 0x47, 0x0D, 0x00, 0x00,
+ 0x00, 0x18, 0x00, 0x00, 0x00, 0x26, 0x00, 0x02,
+ 0x00, 0x70, 0x47, 0x70, 0xB5,
+ 0x00, 0x01, 0x97, 0x00, 0x80, 0x8C, 0x18, 0x05,
+ 0x78, 0x40, 0x1C, 0x6B, 0x07, 0x5B, 0x0F, 0x01,
+ 0xD1, 0x03, 0x78, 0x40, 0x1C, 0x2A, 0x11, 0x06,
+ 0xD1, 0x02, 0x78, 0x40, 0x1C, 0x03, 0xE0, 0x06,
+ 0x78, 0x40, 0x1C, 0x0E, 0x70, 0x49, 0x1C, 0x5B,
+ 0x1E, 0xF9, 0xD1, 0x2B, 0x07, 0x06, 0xD4, 0x00,
+ 0x23, 0x01, 0xE0, 0x0B, 0x70, 0x49, 0x1C, 0x52,
+ 0x1E, 0xFB, 0xD5, 0x0A, 0xE0, 0x03, 0x78, 0x40,
+ 0x1C, 0xCB, 0x1A, 0x92, 0x1C, 0x03, 0xE0, 0x1D,
+ 0x78, 0x5B, 0x1C, 0x0D, 0x70, 0x49, 0x1C, 0x52,
+ 0x1E, 0xF9, 0xD5, 0xA1, 0x42, 0xD7, 0xD3, 0x00,
+ 0x20, 0x70, 0xBD, 0x30, 0xB4, 0x74, 0x46, 0x64,
+ 0x1E, 0x25, 0x78, 0x64, 0x1C, 0xAB, 0x42, 0x00,
+ 0xD2, 0x1D, 0x46, 0x63, 0x5D, 0x5B, 0x00, 0xE3,
+ 0x18, 0x30, 0xBC, 0x18, 0x47, 0xFF, 0xFB, 0xED,
+ 0xD5, 0xB5, 0x00, 0x31, 0x61, 0x8E, 0xB5, 0x00,
+ 0x00, 0x02, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x98, 0x00, 0x80, 0x01, 0x60, 0x13,
+ 0x40, 0x00, 0x30, 0x13, 0x40, 0x00, 0x04, 0x00,
+ 0x40, 0x13, 0x40, 0x00, 0x02, 0xA5, 0x01, 0x02,
+ 0x03, 0xFF, 0xFE, 0xFD, 0x5A, 0x54, 0x53, 0x47,
+ 0x34, 0x20, 0x44, 0x46, 0x54, 0x74, 0x05, 0x00,
+ 0x20, 0x31, 0x02, 0x00, 0x00, 0x8B, 0x0A, 0x00,
+ 0x20, 0x31, 0x02, 0x00, 0x00, 0x64, 0x08, 0x00,
+ 0x20, 0x31, 0x02, 0x00, 0x00, 0x6E, 0x07, 0x00,
+ 0x20, 0x32, 0x01, 0x00, 0x00, 0x85, 0x0C, 0x00,
+ 0x20, 0x31, 0x01, 0x00, 0x00, 0x5E, 0x0A, 0x00,
+ 0x20, 0x31, 0x01, 0x00, 0x00, 0xC0, 0x0C, 0x00,
+ 0x20, 0x32, 0x01, 0x00, 0x00, 0xCE, 0x0D, 0x00,
+ 0x20, 0x31, 0x01, 0x00, 0x00, 0x74, 0x0D, 0x00,
+ 0x20, 0x31, 0x01, 0x00, 0x00, 0x02, 0x00, 0x03,
+ 0xC1, 0x04, 0x00, 0x05, 0x10, 0x06, 0x00, 0x07,
+ 0x32, 0x08, 0x00, 0x09, 0x34, 0x0A, 0x00, 0x0B,
+ 0x41, 0x0C, 0x00, 0x0D, 0x61,
+ 0x00, 0x01, 0x99, 0x00, 0x80, 0x0E, 0x00, 0x0F,
+ 0x81, 0x10, 0x00, 0x11, 0x02, 0x12, 0x01, 0x13,
+ 0x01, 0x18, 0x00, 0x19, 0x05, 0x1A, 0x82, 0x1B,
+ 0x23, 0x22, 0x08, 0x2F, 0x02, 0x30, 0x03, 0x31,
+ 0x01, 0x3E, 0x00, 0x3F, 0xFF, 0x41, 0x02, 0x42,
+ 0x09, 0x49, 0x09, 0x4A, 0x00, 0x4B, 0x0E, 0x4C,
+ 0x02, 0x4D, 0x0E, 0x4E, 0x04, 0x4F, 0x08, 0x50,
+ 0x05, 0x51, 0x05, 0x52, 0xA5, 0x53, 0x02, 0x58,
+ 0x01, 0x59, 0x00, 0x5A, 0x08, 0x5B, 0x06, 0x5C,
+ 0x08, 0x5D, 0x07, 0x5E, 0x08, 0x5F, 0x08, 0x60,
+ 0x08, 0x4A, 0x01, 0x00, 0x00, 0xD8, 0x00, 0x00,
+ 0x20, 0x4B, 0x01, 0x00, 0x00, 0xDD, 0x00, 0x00,
+ 0x20, 0x4C, 0x02, 0x00, 0x00, 0xE4, 0x00, 0x00,
+ 0x20, 0x4D, 0x01, 0x00, 0x00, 0xD6, 0x00, 0x00,
+ 0x20, 0x4E, 0x02, 0x00, 0x00, 0xE2, 0x00, 0x00,
+ 0x20, 0x4F, 0x01, 0x00, 0x00, 0xD7, 0x00, 0x00,
+ 0x20, 0x50, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x9A, 0x00, 0x80, 0xD9, 0x00, 0x00,
+ 0x20, 0x51, 0x01, 0x00, 0x00, 0x33, 0x02, 0x00,
+ 0x20, 0x52, 0x02, 0x00, 0x00, 0x66, 0x01, 0x00,
+ 0x20, 0x80, 0x01, 0x00, 0x00, 0x90, 0x00, 0x00,
+ 0x20, 0x28, 0x00, 0x2C, 0x00, 0x30, 0x00, 0x34,
+ 0x00, 0x38, 0x00, 0x3C, 0x00, 0x40, 0x00, 0x44,
+ 0x00, 0x4C, 0x00, 0x54, 0x00, 0x5C, 0x00, 0x64,
+ 0x00, 0x70, 0x00, 0x7C, 0x00, 0x88, 0x00, 0x98,
+ 0x00, 0xA8, 0x00, 0xBC, 0x00, 0xD0, 0x00, 0xE8,
+ 0x00, 0x00, 0x01, 0x1C, 0x01, 0x3C, 0x01, 0x60,
+ 0x01, 0x88, 0x01, 0xB4, 0x01, 0xE8, 0x01, 0x20,
+ 0x02, 0x60, 0x02, 0xA8, 0x02, 0xF8, 0x02, 0x50,
+ 0x03, 0xC6, 0x08, 0x27, 0x09, 0x58, 0x09, 0x89,
+ 0x09, 0xEB, 0x09, 0x4C, 0x0A, 0xAE, 0x0A, 0x10,
+ 0x0B, 0x71, 0x0B, 0xD3, 0x0B, 0x35, 0x0C, 0x96,
+ 0x0C, 0xF8, 0x0C, 0x59, 0x0D, 0xBB, 0x0D, 0x1D,
+ 0x0E, 0x19, 0x1B, 0x1C, 0x1D,
+ 0x00, 0x01, 0x9B, 0x00, 0x80, 0x1E, 0x1F, 0x20,
+ 0x21, 0x22, 0x23, 0x25, 0x26, 0x27, 0x28, 0x29,
+ 0x2A, 0x2B, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33,
+ 0x34, 0x35, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x6F, 0x53,
+ 0xB2, 0x01, 0x6F, 0x57, 0xB2, 0x01, 0x6F, 0x4B,
+ 0xB2, 0x01, 0x6F, 0x4B, 0xB8, 0x01, 0x79, 0x43,
+ 0xB2, 0x01, 0x68, 0x43, 0xB2, 0x00, 0x01, 0x02,
+ 0x02, 0x03, 0x03, 0x04, 0x04, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x9C, 0x00, 0x80, 0x80, 0x00, 0x00,
+ 0x00, 0x55, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
+ 0x00, 0x33, 0x00, 0x00, 0x00, 0x2A, 0x00, 0x00,
+ 0x00, 0x24, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+ 0x00, 0xEB, 0x86, 0x00, 0x00, 0x43, 0x87, 0x00,
+ 0x00, 0xA7, 0x88, 0x00, 0x00, 0xDB, 0x88, 0x00,
+ 0x00, 0xFF, 0x88, 0x00, 0x00, 0x8B, 0x87, 0x00,
+ 0x00, 0xC7, 0x89, 0x00, 0x00, 0x8B, 0x8C, 0x00,
+ 0x00, 0x57, 0x8D, 0x00, 0x00, 0x0D, 0x8E, 0x00,
+ 0x00, 0x95, 0x8E, 0x00, 0x00, 0xEB, 0x8E, 0x00,
+ 0x00, 0x39, 0x8F, 0x00, 0x00, 0x1F, 0x90, 0x00,
+ 0x00, 0x83, 0x90, 0x00, 0x00, 0xE5, 0x90, 0x00,
+ 0x00, 0x2D, 0x91, 0x00, 0x00, 0x81, 0x91, 0x00,
+ 0x00, 0xC1, 0x92, 0x00, 0x00, 0x33, 0x93, 0x00,
+ 0x00, 0x5B, 0x93, 0x00, 0x00, 0xE1, 0x93, 0x00,
+ 0x00, 0xBD, 0x94, 0x00, 0x00, 0xEA, 0x03, 0xEA,
+ 0x03, 0xEA, 0x03, 0xEA, 0x03,
+ 0x00, 0x01, 0x9D, 0x00, 0x80, 0x6A, 0x03, 0x6A,
+ 0x03, 0x6A, 0x03, 0x6A, 0x03, 0x0A, 0x03, 0x00,
+ 0x00, 0x0A, 0x03, 0x00, 0x00, 0x0A, 0x01, 0x0A,
+ 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x00, 0x00,
+ 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x64, 0x03, 0x64,
+ 0x03, 0x64, 0x03, 0x64, 0x03, 0x04, 0x03, 0x04,
+ 0x03, 0x04, 0x03, 0x04, 0x03, 0x04, 0x01, 0x04,
+ 0x01, 0x04, 0x01, 0x04, 0x01, 0x04, 0x00, 0x04,
+ 0x00, 0x04, 0x00, 0x04, 0x00, 0x62, 0x03, 0x62,
+ 0x03, 0x62, 0x03, 0x62, 0x03, 0x02, 0x03, 0x02,
+ 0x03, 0x02, 0x03, 0x02, 0x03, 0x02, 0x01, 0x02,
+ 0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x00, 0x02,
+ 0x00, 0x02, 0x00, 0x02, 0x00, 0x0A, 0x03, 0x0A,
+ 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x03, 0x0A,
+ 0x00, 0x0A, 0x00, 0x0A, 0x03, 0x0A, 0x03, 0xEA,
+ 0x03, 0x0A, 0x03, 0x00, 0x00, 0x02, 0x00, 0x02,
+ 0x03, 0x6A, 0x03, 0x0A, 0x03,
+ 0x00, 0x01, 0x9E, 0x00, 0x80, 0x0A, 0x03, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6A,
+ 0x03, 0xEA, 0x03, 0xEA, 0x03, 0x02, 0x00, 0x04,
+ 0x00, 0x02, 0x00, 0x04, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x00, 0x00,
+ 0x00, 0x55, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
+ 0x00, 0x33, 0x00, 0x00, 0x00, 0x2A, 0x00, 0x00,
+ 0x00, 0x24, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0xB9, 0x00, 0x00,
+ 0x00, 0x86, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00,
+ 0x00, 0x26, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00,
+ 0x00, 0x27, 0x00, 0x00, 0x00, 0x37, 0x00, 0x00,
+ 0x00, 0x52, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x9F, 0x00, 0x80, 0x94, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00,
+ 0x00, 0x07, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00,
+ 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00,
+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00,
+ 0x00, 0x14, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+ 0x00, 0x17, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
+ 0x00, 0x18, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00,
+ 0x00, 0x19, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00,
+ 0x00, 0x19, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00,
+ 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
+ 0x00, 0x17, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00,
+ 0x00, 0x14, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00,
+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00,
+ 0x00, 0x0C, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00,
+ 0x00, 0x07, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xA0, 0x00, 0x80, 0x05, 0x00, 0x00,
+ 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xEF, 0xC7, 0x00, 0x00, 0xEF, 0xC7, 0x00,
+ 0x00, 0xEF, 0xC7, 0x00, 0x00, 0xEF, 0xC7, 0x00,
+ 0x00, 0xEF, 0xC7, 0x00, 0x00, 0xEF, 0xC7, 0x00,
+ 0x00, 0xEF, 0xC7, 0x00, 0x00, 0x58, 0xD0, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x80, 0x00, 0x00,
+ 0x00, 0xC4, 0x12, 0x00, 0x00, 0xD8, 0xD0, 0x00,
+ 0x00, 0x84, 0x00, 0x00, 0x20, 0xC8, 0x02, 0x00,
+ 0x00, 0x7E, 0xCB, 0x00, 0x00, 0x3C, 0xD1, 0x00,
+ 0x00, 0x4C, 0x03, 0x00, 0x20, 0x34, 0x13, 0x00,
+ 0x00, 0xE0, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xA1, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x03, 0x2B,
+ 0x01, 0x24, 0x39, 0x2C, 0x46, 0x51, 0x25, 0x02,
+ 0xA0, 0x8C, 0x6C, 0x50, 0x46, 0x01, 0x45, 0x01,
+ 0x23, 0x0B, 0x2E, 0xFF, 0x07, 0x02, 0x09, 0x21,
+ 0x54, 0x0A, 0x1C, 0xFF, 0xAC, 0x05, 0x34, 0xD0,
+ 0xF1, 0xFF, 0x0F, 0x4B, 0x49,
+ 0x00, 0x01, 0xA2, 0x00, 0x80, 0x5F, 0x04, 0x01,
+ 0x19, 0x99, 0xF1, 0x13, 0xC9, 0x07, 0x1B, 0x20,
+ 0xCA, 0x04, 0x1A, 0xC8, 0x04, 0x1A, 0xF0, 0x04,
+ 0x1A, 0xF1, 0x04, 0x1A, 0xEF, 0x04, 0x13, 0x17,
+ 0x08, 0x1B, 0x20, 0x18, 0x04, 0x1A, 0x16, 0x04,
+ 0x1A, 0x3E, 0x04, 0x1A, 0x3F, 0x04, 0x1A, 0x3D,
+ 0x04, 0x03, 0x5A, 0x04, 0xDE, 0x5A, 0xFF, 0x01,
+ 0x01, 0x64, 0x03, 0x76, 0x2C, 0xDD, 0xE3, 0x80,
+ 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xA3, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
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+ 0x00, 0x00, 0x00, 0x32, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x0B, 0x00, 0x00, 0x00, 0x19, 0x00, 0x19,
+ 0x00, 0x19, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x14, 0x00, 0x14, 0x00, 0x14, 0x00, 0x14,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
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+ 0x14, 0x00, 0x14, 0x00, 0x00, 0x37, 0x77, 0x00,
+ 0x28, 0x00, 0x0F, 0x01, 0x14, 0x01, 0x14, 0x00,
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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x02,
+ 0x14, 0x0B, 0x02, 0x02, 0x17, 0x02, 0x14, 0x50,
+ 0x50, 0x50, 0x50, 0x50, 0x0E, 0x0C, 0x0C, 0x0C,
+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xB4, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0xFF, 0x81, 0x03, 0x06, 0x00,
+ 0x00, 0xFF, 0x00, 0xAF, 0xC0, 0xFF, 0xFF, 0xB0,
+ 0x00, 0x22, 0x02, 0x7F, 0x81, 0x7F, 0x72, 0x01,
+ 0x80, 0x06, 0x01, 0x48, 0x04, 0x43, 0x28, 0x3C,
+ 0x28, 0x12, 0x01, 0x01, 0x00, 0x04, 0x01, 0x08,
+ 0x10, 0x01, 0x04, 0x00, 0x00, 0x44, 0x01, 0x02,
+ 0x80, 0x01, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0xBD, 0x00, 0x80, 0x80, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00,
+ 0x90, 0x80, 0x00, 0xFE, 0x0B, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x7A, 0xA0, 0x00,
+ 0xD0, 0x00, 0x00, 0x00, 0x00, 0x05, 0x04, 0xFF,
+ 0x81, 0x04, 0x0C, 0x00, 0x00, 0xFF, 0x02, 0xAF,
+ 0xC0, 0xFF, 0xFF, 0xD0, 0x00, 0x22, 0x02, 0x7F,
+ 0x81, 0x7F, 0x72, 0x01, 0x80, 0x01, 0x81, 0x40,
+ 0x04, 0x31, 0x0F, 0x31, 0x0F, 0x12, 0x01, 0x01,
+ 0x00, 0x04, 0x01, 0x08, 0x10, 0x01, 0x04, 0x00,
+ 0x00, 0x44, 0x01, 0x02, 0x80, 0x01, 0x01, 0x00,
+ 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x01, 0x00, 0x90, 0x80, 0x00, 0xFE,
+ 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3A, 0xA6, 0x00, 0xD0, 0x00, 0x00, 0x00,
+ 0x00, 0x05, 0x04, 0xFF, 0x80, 0x03, 0x20, 0x00,
+ 0x00, 0xAF, 0x08, 0xAF, 0xC0,
+ 0x00, 0x01, 0xBE, 0x00, 0x80, 0xFF, 0xFF, 0xB0,
+ 0x00, 0x22, 0x02, 0x7F, 0x81, 0x7F, 0x72, 0x01,
+ 0x80, 0x01, 0x81, 0x40, 0x04, 0x96, 0x0F, 0x96,
+ 0x0F, 0x12, 0x01, 0x01, 0x00, 0x04, 0x01, 0x08,
+ 0x10, 0x01, 0x04, 0x00, 0x00, 0x44, 0x01, 0x02,
+ 0x80, 0x01, 0x01, 0x00, 0x00, 0x80, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00,
+ 0x90, 0x80, 0x00, 0xFE, 0x0B, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x3A, 0xA0, 0x00,
+ 0xD0, 0x05, 0x04, 0xFF, 0x80, 0x03, 0x24, 0x00,
+ 0x00, 0xFF, 0x00, 0xAF, 0xC0, 0xFF, 0xFF, 0xB0,
+ 0x00, 0x22, 0x02, 0x7F, 0x81, 0x7F, 0x72, 0x01,
+ 0x80, 0x06, 0x01, 0x48, 0x04, 0x31, 0x23, 0x31,
+ 0x23, 0x12, 0x01, 0x01, 0x00, 0x04, 0x01, 0x08,
+ 0x10, 0x01, 0x04, 0x00, 0x00, 0x44, 0x01, 0x02,
+ 0x80, 0x01, 0x01, 0x00, 0x00, 0x80, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xBF, 0x00, 0x80, 0x01, 0x01, 0x00,
+ 0x90, 0x80, 0x00, 0xFE, 0x0B, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x7A, 0xA0, 0x00,
+ 0xD0, 0x03, 0x08, 0x00, 0x00, 0x00, 0x00, 0x30,
+ 0x30, 0x40, 0x03, 0x07, 0x40, 0x15, 0x00, 0x00,
+ 0x00, 0x0D, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
+ 0x00, 0x11, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
+ 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00,
+ 0x00, 0x0A, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x00,
+ 0x00, 0x64, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00,
+ 0x00, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x50, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
+ 0x00, 0x0F, 0x00, 0x01, 0x00, 0x0F, 0x0F, 0x32,
+ 0x00, 0x04, 0x00, 0x04, 0x02, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xC0, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x34, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xC1, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0xCE, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x12, 0x13,
+ 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x22, 0x23,
+ 0x24, 0x25, 0x38, 0x37, 0x36, 0x2D, 0x2C, 0x2B,
+ 0x2A, 0x29, 0x28, 0x27, 0x3B, 0x3A, 0x39, 0x01,
+ 0x02, 0x03, 0x04, 0x05, 0x0E, 0x0F, 0x10, 0x10,
+ 0x27, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xC2, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x38, 0x2B, 0x38, 0x2B, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x13, 0x13, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1F, 0x00,
+ 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC,
+ 0x03, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x7E, 0x00, 0x06, 0x10, 0x00, 0x00, 0x01,
+ 0x02, 0x03, 0x04, 0x05, 0x00, 0x00, 0x0F, 0x0B,
+ 0x0A, 0x09, 0x09, 0x0A, 0x0A, 0x0F, 0x0F, 0xBF,
+ 0x00, 0x07, 0x10, 0x07, 0x08, 0x09, 0x0A, 0x0B,
+ 0x0C, 0x00, 0x06, 0x00, 0x0B, 0x0B, 0x0B, 0x0A,
+ 0x0B, 0x0B, 0x0F, 0x0A, 0x0F, 0xFF, 0x00, 0x08,
+ 0x38, 0x21, 0x14, 0x13, 0x12, 0x1D, 0x1E, 0x1F,
+ 0x20, 0x00, 0x0B, 0x0B, 0x0B, 0x0B, 0x0A, 0x0A,
+ 0x09, 0x0A, 0x0F, 0x8F, 0x00, 0x05, 0x10, 0x15,
+ 0x19, 0x18, 0x17, 0x00, 0x00, 0x00, 0x16, 0x00,
+ 0x0B, 0x0B, 0x0B, 0x0B, 0x0F,
+ 0x00, 0x01, 0xC3, 0x00, 0x80, 0x0F, 0x0F, 0x0B,
+ 0x0F, 0xFF, 0x00, 0x08, 0x10, 0x0D, 0x1A, 0x1B,
+ 0x1C, 0x11, 0x10, 0x0F, 0x0E, 0x00, 0x0A, 0x0A,
+ 0x0A, 0x0A, 0x0B, 0x0B, 0x0A, 0x0A, 0x0F, 0x81,
+ 0x00, 0x02, 0x14, 0x22, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x23, 0x00, 0x0B, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x0B, 0x00, 0x11, 0x00, 0x02,
+ 0x14, 0x23, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00,
+ 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x09, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC4, 0x12, 0x00, 0x00,
+ 0x00, 0x01, 0xC4, 0x00, 0x80, 0x24, 0x00, 0x7E,
+ 0x00, 0x02, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x43, 0x59, 0x49, 0x4C, 0x06, 0x01, 0x00, 0x03,
+ 0x02, 0x0D, 0x15, 0x01, 0xE0, 0x03, 0x20, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFE, 0xE9,
+ 0x00, 0x01, 0xFF, 0x00, 0x80, 0x3C, 0x00, 0x3C,
+ 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0xCA, 0x95,
+ 0xA2, 0x81, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x48, 0xBF, 0x00, 0x00, 0x0B, 0x25, 0x13,
+ 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0xC0, 0xED,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+};
diff --git a/arch/arm/mach-exynos/cyttsp4_params.h b/arch/arm/mach-exynos/cyttsp4_params.h new file mode 100644 index 0000000..d9a20ce --- /dev/null +++ b/arch/arm/mach-exynos/cyttsp4_params.h @@ -0,0 +1,1529 @@ +//*****************************************************************************
+//*****************************************************************************
+// FILENAME: Driver.h
+// TrueTouch Host Emulator Version Information: 2.1.613
+// TrueTouch Firmware Version Information: 1.1.360995
+//
+// DESCRIPTION: This file contains configuration values.
+//-----------------------------------------------------------------------------
+// Copyright (c) Cypress Semiconductor 2012. All Rights Reserved.
+//*****************************************************************************
+//*****************************************************************************
+//-----------------------------------------------------------------------------
+/* Touchscreen Parameters Endianess (Endianess: 0:Little; 1:Big)*/
+static const uint8_t cyttsp4_param_endianess = 0; +
+/* Touchscreen Parameters */
+static const uint8_t cyttsp4_param_regs[] = {
+/* Value Name */
+ 0xFC, 0x05, /* CONFIG_DATA_SIZE */ + 0xFC, 0x05, /* CONFIG_DATA_MAX_SIZE */ + 0x4C, 0x00, 0x00, 0x00, /* SDK_CTRL_CFG_SIZE */ + 0x01, 0x00, /* CONFIG_VER */ + 0x01, /* PANELID_ENABLE */ + 0x30, /* IMO_FREQ_MHZ */ + 0xEC, 0x13, /* X_LEN_PHY */ + 0xB0, 0x1D, /* Y_LEN_PHY */ + 0x10, /* HST_MODE0 */ + 0x07, /* ACT_DIST0 */ + 0x00, /* SCAN_TYP0 */ + 0x0A, /* ACT_INTRVL0 */ + 0x03, /* ACT_LFT_INTRVL0 */ + 0x00, /* Reserved21 */ + 0x32, 0x00, /* LP_INTRVL0 */ + 0xB8, 0x0B, /* TCH_TMOUT0 */ + 0x01, /* PWR_CFG */ + 0x00, /* Reserved27 */ + 0x32, /* INT_PULSE_DATA */ + 0x08, /* OPMODE_CFG */ + 0xF4, 0x01, /* HANDSHAKE_TIMEOUT */ + 0xF4, 0x01, /* ESD_COUNTER_CFG */ + 0x1E, /* TIMER_CAL_INTERVAL */ + 0x00, /* Reserved35 */ + 0x00, 0x00, /* RP2P_MIN */ + 0x88, 0x13, /* ILEAK_MAX */ + 0x96, 0x00, /* RFB_P2P */ + 0x96, 0x00, /* RFB_EXT */ + 0x00, /* IDACOPEN_LOW */ + 0x00, /* IDACOPEN_HIGH */ + 0x00, /* IDACOPEN_BUTTON_LOW */ + 0x00, /* IDACOPEN_BUTTON_HIGH */ + 0x00, /* GIDAC_OPEN */ + 0x00, /* GAIN_OPEN */ + 0x00, /* GIDAC_BUTTON_OPEN */ + 0x00, /* GAIN_BUTTON_OPEN */ + 0x00, /* POST_CFG */ + 0x00, /* GESTURE_CFG */ + 0x00, /* GEST_EN0 */ + 0x00, /* GEST_EN1 */ + 0x00, /* GEST_EN2 */ + 0x00, /* GEST_EN3 */ + 0x00, /* GEST_EN4 */ + 0x00, /* GEST_EN5 */ + 0x00, /* GEST_EN6 */ + 0x00, /* GEST_EN7 */ + 0x00, /* GEST_EN8 */ + 0x00, /* GEST_EN9 */ + 0x00, /* GEST_EN10 */ + 0x00, /* GEST_EN11 */ + 0x00, /* GEST_EN12 */ + 0x00, /* GEST_EN13 */ + 0x00, /* GEST_EN14 */ + 0x00, /* GEST_EN15 */ + 0x00, /* GEST_EN16 */ + 0x00, /* GEST_EN17 */ + 0x00, /* GEST_EN18 */ + 0x00, /* GEST_EN19 */ + 0x00, /* GEST_EN20 */ + 0x00, /* GEST_EN21 */ + 0x00, /* GEST_EN22 */ + 0x00, /* GEST_EN23 */ + 0x00, /* GEST_EN24 */ + 0x00, /* GEST_EN25 */ + 0x00, /* GEST_EN26 */ + 0x00, /* GEST_EN27 */ + 0x00, /* GEST_EN28 */ + 0x00, /* GEST_EN29 */ + 0x00, /* GEST_EN30 */ + 0x00, /* GEST_EN31 */ + 0x01, /* ACT_DIST2 */ + 0x00, /* EXTERN_SYNC */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* Reserved88 */ + 0x18, 0x00, 0x00, 0x00, /* GRIP_CFG_SIZE */ + 0x00, 0x00, /* GRIP_XEDG_A */ + 0x00, 0x00, /* GRIP_XEDG_B */ + 0x00, 0x00, /* GRIP_XEXC_A */ + 0x00, 0x00, /* GRIP_XEXC_B */ + 0x00, 0x00, /* GRIP_YEDG_A */ + 0x00, 0x00, /* GRIP_YEDG_B */ + 0x00, 0x00, /* GRIP_YEXC_A */ + 0x00, 0x00, /* GRIP_YEXC_B */ + 0x00, /* GRIP_FIRST_EXC */ + 0x00, /* GRIP_EXC_EDGE_ORIGIN */ + 0x00, 0x00, /* Reserved118 */ + 0x70, 0x00, 0x00, 0x00, /* TRUETOUCH_CFG_SIZE */ + 0x64, 0x00, 0x00, 0x00, /* MAX_SELF_SCAN_INTERVAL */ + 0x64, 0x00, 0x00, 0x00, /* MAX_MUTUAL_SCAN_INTERVAL */ + 0x64, 0x00, 0x00, 0x00, /* MAX_BALANCED_SCAN_INTERVAL */ + 0x02, 0x00, 0x00, 0x00, /* SELF_Z_THRSH */ + 0x01, 0x00, 0x00, 0x00, /* SELF_Z_MODE */ + 0x00, 0x00, 0x00, 0x00, /* SMART_SCAN_ENABLE */ + 0x00, 0x00, 0x00, 0x00, /* T_COMP_ENABLE */ + 0xD0, 0x07, 0x00, 0x00, /* T_COMP_INTERVAL */ + 0x32, 0x00, 0x00, 0x00, /* T_COMP_RECAL_MUTUAL_SENSOR_LIMIT */ + 0x64, 0x00, 0x00, 0x00, /* T_COMP_RECAL_MUTUAL_HIGH */ + 0xD8, 0xFF, 0xFF, 0xFF, /* T_COMP_RECAL_MUTUAL_LOW */ + 0x0A, 0x00, 0x00, 0x00, /* T_COMP_RECAL_SELF_SENSOR_LIMIT */ + 0x8C, 0x00, 0x00, 0x00, /* T_COMP_RECAL_SELF_HIGH */ + 0xD8, 0xFF, 0xFF, 0xFF, /* T_COMP_RECAL_SELF_LOW */ + 0x01, 0x00, 0x00, 0x00, /* CHARGER_ARMOR_ENABLE */ + 0x00, 0x00, 0x00, 0x00, /* AFH_ENABLE */ + 0x08, 0x00, 0x00, 0x00, /* AFH_LISTENING_SCAN_COUNT */ + 0x06, 0x00, 0x00, 0x00, /* AFH_LISTEN_SCAN_CYCLE_REPEATS */ + 0xFA, 0x00, 0x00, 0x00, /* CA_BLOCK_NOISE_THRESHOLD */ + 0x03, 0x00, 0x00, 0x00, /* CA_BLOCK_NOISE_HYSTERESIS */ + 0xB8, 0x0B, 0x00, 0x00, /* CA_DEFAULT_REVERT_TIME */ + 0x00, 0x00, /* CA_SMART_H2O_REJECT */ + 0x00, 0x00, /* CA_HOST_CONTROLLED_CHARGER */ + 0xA0, 0x00, /* T_COMP_BUTTON_MUTUAL_HIGH */ + 0xC4, 0xFF, /* T_COMP_BUTTON_MUTUAL_LOW */ + 0xA0, 0x00, /* T_COMP_BUTTON_SELF_HIGH */ + 0xC4, 0xFF, /* T_COMP_BUTTON_SELF_LOW */ + 0x08, 0x00, 0x00, 0x00, /* CA_NUM_SUB_CONV_BASE_SELF */ + 0x10, 0x00, 0x00, 0x00, /* CA_ALT_NUM_SUB_CONV_SELF */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* Reserved228 */ + 0x0C, /* CA_ALT_NUM_SUB_CONV_MUTUAL */ + 0x02, /* CA_ALT_ACQUISITION_FLAGS */ + 0x45, /* AFH_ALT_TX_PERIOD1 */ + 0x2D, /* AFH_ALT_TX_PERIOD1_MUTUAL_SCALE_FACTOR */ + 0x0F, /* AFH_ALT_TX_PERIOD1_MUTUAL_TX_VOLTAGE */ + 0x02, /* AFH_ALT_TX_PULSES1 */ + 0x56, /* AFH_ALT_TX_PERIOD2 */ + 0x2D, /* AFH_ALT_TX_PERIOD2_MUTUAL_SCALE_FACTOR */ + 0x0F, /* AFH_ALT_TX_PERIOD2_MUTUAL_TX_VOLTAGE */ + 0x02, /* AFH_ALT_TX_PULSES2 */ + 0x00, 0x00, /* Reserved250 */ + 0x2A, /* GEST_CFG_SIZE */ + 0x01, /* PAN_ACT_DSTX */ + 0x12, /* PAN_ACT_DSTY */ + 0x12, /* ZOOM_ACT_DSTX */ + 0x12, /* ZOOM_ACT_DSTY */ + 0x23, /* FLICK_ACT_DISTX */ + 0x23, /* FLICK_ACT_DISTY */ + 0x50, /* FLICK_TIME */ + 0x02, /* ST_DEBOUNCE */ + 0x03, /* MT_DEBOUNCE_PAN */ + 0x02, /* MT_DEBOUNCE_ZOOM */ + 0x0A, /* MT_DEBOUNCE_P2Z */ + 0x14, /* ROT_DEBOUNCE */ + 0x02, /* COMPL_DEBOUNCE */ + 0x28, 0x00, /* MT_TIMEOUT */ + 0x32, /* ST_DBLCLK_RMAX */ + 0x1E, /* ST_CLICK_DISTX */ + 0x1E, /* ST_CLICK_DISTY */ + 0x00, /* Reserved271 */ + 0xC8, 0x00, /* MT_CLICK_TMAX */ + 0x14, 0x00, /* MT_CLICK_TMIN */ + 0xC8, 0x00, /* ST_CLICK_TMAX */ + 0x14, 0x00, /* ST_CLICK_TMIN */ + 0xC8, 0x00, /* ST_DBLCLK_TMAX */ + 0x14, 0x00, /* ST_DBLCLK_TMIN */ + 0xF0, /* GESTURE_GROUP_MASK */ + 0x28, /* GESTURE_GROUP1_START */ + 0x29, /* GESTURE_GROUP1_END */ + 0x30, /* GESTURE_GROUP2_START */ + 0x3F, /* GESTURE_GROUP2_END */ + 0x48, /* GESTURE_GROUP3_START */ + 0x49, /* GESTURE_GROUP3_END */ + 0x90, /* GESTURE_GROUP4_START */ + 0x9F, /* GESTURE_GROUP4_END */ + 0x00, 0x00, 0x00, /* Reserved293 */ + 0x1C, 0x00, 0x00, 0x00, /* XY_FILT_CFG_SIZE */ + 0xF0, 0x00, 0x00, 0x00, /* XY_FILTER_MASK */ + 0x01, 0x00, 0x00, 0x00, /* XY_FILT_IIR_COEFF */ + 0x01, 0x00, 0x00, 0x00, /* XY_FILT_Z_IIR_COEFF */ + 0x00, /* XY_FILT_XY_FAST_THR */ + 0x00, /* XY_FILT_XY_SLOW_THR */ + 0x01, /* XY_FILT_IIR_FAST_COEFF */ + 0x00, /* Reserved315 */ + 0xF0, 0x00, 0x00, 0x00, /* XY_FILTER_MASK_CA */ + 0x01, 0x00, 0x00, 0x00, /* XY_FILT_IIR_COEFF_CA */ + 0x02, 0x00, 0x00, 0x00, /* XY_FILT_Z_IIR_COEFF_CA */ + 0x00, /* XY_FILT_XY_FAST_THR_CA */ + 0x00, /* XY_FILT_XY_SLOW_THR_CA */ + 0x01, /* XY_FILT_IIR_FAST_COEFF_CA */ + 0x00, /* Reserved331 */ + 0x00, /* XY_FILT_ADAPTIVE_IIR_FILTER */ + 0x0C, /* XY_FILT_ADAPTIVE_IIR_FILTER_DISTANCE */ + 0x00, /* XY_FILT_TOUCH_SIZE_IIR_COEFF */ + 0x00, /* XY_FILT_TOUCH_SIZE_HYST */ + 0x00, /* XY_FILT_TOUCH_ORIENTATION_IIR_COEFF */ + 0x00, /* XY_FILT_TOUCH_ORIENTATION_HYST */ + 0x01, /* XY_FILT_TOUCH_SCALLOPING_ENABLE */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, /* Reserved339 */ + 0x08, 0x00, 0x00, 0x00, /* FINGER_ID_CFG_SIZE */ + 0x00, 0x00, 0x00, 0x00, /* Reserved352 */ + 0xA0, 0x86, 0x01, 0x00, /* FINGER_ID_MAX_FINGER_VELOCITY2 */ + 0x02, /* LIFTOFF_DEBOUNCE */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, /* Reserved361 */ + 0x18, 0x00, 0x00, 0x00, /* CENTROID_SH_CFG_SIZE */ + 0x14, 0x00, 0x00, 0x00, /* STYLUS_THRSH */ + 0x05, 0x00, 0x00, 0x00, /* STYLUS_HYST */ + 0xFF, 0x00, 0x00, 0x00, /* S2F_THRESHOLD */ + 0x00, 0x00, 0x00, 0x00, /* HOVER_THRSH */ + 0x00, 0x00, 0x00, 0x00, /* HOVER_HYST */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* Reserved392 */ + 0x20, 0x00, 0x00, 0x00, /* ID_COORDS_CFG_SIZE */ + 0x02, /* LRG_OBJ_CFG */ + 0x4B, /* MAX_FAT_FINGER_SIZE */ + 0x0F, /* MIN_FAT_FINGER_SIZE */ + 0x0D, /* FINGER_THRESH_MUTUAL */ + 0x0F, 0x00, /* FINGER_THRESH_SELF */ + 0x0F, /* INNER_EDGE_GAIN */ + 0x09, /* OUTER_EDGE_GAIN */ + 0xE0, 0x01, 0x00, 0x00, /* X_RESOLUTION */ + 0x20, 0x03, 0x00, 0x00, /* Y_RESOLUTION */ + 0x00, 0x00, 0x00, 0x00, /* SENSOR_ASSIGNMENT */ + 0x80, 0x00, 0x00, 0x00, /* Z_SCALING */ + 0x00, /* RX_LINE_FILTER */ + 0x01, /* BYPASS_THRESHOLD_GAIN */ + 0x01, /* BYPASS_THRESHOLD_EDGE_GAIN */ + 0x02, /* FINGER_THR_MUT_HYST */ + 0x03, /* MAX_FAT_FINGER_SIZE_HYST */ + 0x03, /* MIN_FAT_FINGER_SIZE_HYST */ + 0x0A, /* MULTI_TOUCH_DEBOUNCE */ + 0x19, /* CA_FINGER_THRESHOLD_MUTUAL */ + 0x20, /* FAT_FINGER_THRESHOLD_COEFF */ + 0x03, /* SIZE_ORIENTATION_ENABLE */ + 0x50, /* MAJOR_AXIS_OFFSET */ + 0x0E, /* MAJOR_AXIS_SCALE */ + 0x50, /* MINOR_AXIS_OFFSET */ + 0x0E, /* MINOR_AXIS_SCALE */ + 0x02, /* RX_LINE_FILTER_DEBOUNCE */ + 0x00, /* CLIPPING_X_LOW */ + 0x00, /* CLIPPING_X_HIGH */ + 0x00, /* CLIPPING_Y_LOW */ + 0x00, /* CLIPPING_Y_HIGH */ + 0x05, /* COEF_EDGE_ATTRACTION */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG1 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG2 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG3 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG4 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG5 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG6 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG7 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG8 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG9 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG10 */ + 0x00, 0x00, /* WIDTH_CORNER_DIAG11 */ + 0x00, 0x00, /* WIDTH_CORNER_PERP1 */ + 0x00, 0x00, /* WIDTH_CORNER_PERP2 */ + 0x00, 0x00, /* WIDTH_CORNER_PERP3 */ + 0x00, 0x00, /* WIDTH_CORNER_PERP4 */ + 0x32, /* RX_LINE_FILTER_THRESHOLD */ + 0x00, /* NOISE_REJECTION_3x3_FILTER_SCALE */ + 0x01, /* NOISE_REJECTION_3x3_FILTER_SCALE_CA */ + 0x00, /* DIRECT_XY_ENABLE */ + 0x00, 0x00, /* Reserved482 */ + 0x0B, 0x00, 0x00, 0x00, /* BTN_CFG_SIZE */ + 0x19, 0x00, /* BTN_THRSH_MUT_0 */ + 0x19, 0x00, /* BTN_THRSH_MUT_1 */ + 0x19, 0x00, /* BTN_THRSH_MUT_2 */ + 0x19, 0x00, /* BTN_THRSH_MUT_3 */ + 0x00, /* BTN_HYST_MUT */ + 0x00, /* Reserved497 */ + 0x00, /* Reserved498 */ + 0x00, /* Reserved499 */ + 0x14, 0x00, /* BTN_THRSH_SELF */ + 0x14, 0x00, /* BTN_THRSH_SELF_1 */ + 0x14, 0x00, /* BTN_THRSH_SELF_2 */ + 0x14, 0x00, /* BTN_THRSH_SELF_3 */ + 0x00, /* BTN_HYST_SELF */ + 0x00, /* Reserved509 */ + 0x00, /* Reserved510 */ + 0x00, /* Reserved511 */ + 0x1A, 0x00, 0x00, 0x00, /* RAW_PROC_CFG_SIZE */ + 0x37, 0x77, /* RAW_FILTER_MASK */ + 0x00, /* RAW_FILT_IIR_COEFF_MUTUAL */ + 0x05, /* RAW_FILT_IIR_THRESHOLD_MUTUAL */ + 0x00, /* RAW_FILT_IIR_COEFF_SELF */ + 0x05, /* RAW_FILT_IIR_THRESHOLD_SELF */ + 0x00, /* RAW_FILT_IIR_COEFF_BALANCED */ + 0x14, /* RAW_FILT_IIR_THRESHOLD_BALANCED */ + 0x00, /* RAW_FILT_IIR_COEFF_BUTTONS */ + 0x14, /* RAW_FILT_IIR_THRESHOLD_BUTTONS */ + 0x00, 0x00, /* Reserved526 */ + 0x37, 0x77, /* RAW_FILTER_MASK_CA */ + 0x00, /* RAW_FILT_IIR_COEFF_MUTUAL_CA */ + 0x28, /* RAW_FILT_IIR_THRESHOLD_MUTUAL_CA */ + 0x00, /* RAW_FILT_IIR_COEFF_SELF_CA */ + 0x0F, /* RAW_FILT_IIR_THRESHOLD_SELF_CA */ + 0x01, /* RAW_FILT_IIR_COEFF_BALANCED_CA */ + 0x14, /* RAW_FILT_IIR_THRESHOLD_BALANCED_CA */ + 0x01, /* RAW_FILT_IIR_COEFF_BUTTONS_CA */ + 0x14, /* RAW_FILT_IIR_THRESHOLD_BUTTONS_CA */ + 0x00, 0x00, /* Reserved538 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* Reserved540 */ + 0x02, /* BL_DELAY_MUT */ + 0x02, /* BL_DELAY_SELF */ + 0x02, /* BL_DELAY_BAL */ + 0x14, /* BL_DELAY_BTN */ + 0x0B, /* BL_THR_MUT */ + 0x02, /* BL_THR_SELF */ + 0x02, /* BL_THR_BAL */ + 0x17, /* BL_THR_BTN_MUT */ + 0x02, /* BL_THR_BTN_SELF */ + 0x14, /* BL_MUT_SIG_THRESHOLD_CA */ + 0x50, /* BL_FILT_MUT */ + 0x50, /* BL_FILT_SELF */ + 0x50, /* BL_FILT_BAL */ + 0x50, /* BL_FILT_BTN_MUT */ + 0x50, /* BL_FILT_BTN_SELF */ + 0x0E, /* CMF_THR_MUT */ + 0x0C, /* CMF_THR_SELF */ + 0x0C, /* CMF_THR_BAL */ + 0x0C, /* CMF_THR_BTN_MUT */ + 0x0C, /* CMF_THR_BTN_SELF */ + 0x00, 0x00, 0x00, 0x00, /* Reserved572 */ + 0x08, 0x00, 0x00, 0x00, /* H2OREJECTION_SIZE */ + 0x00, /* BL_H20_RJCT */ + 0x00, /* BL_H20_SNS_WIDTH */ + 0x00, 0x00, /* Reserved582 */ + 0xB4, 0x01, 0x00, 0x00, /* CDC_CFG_SIZE */ + 0x00, 0x00, 0xFF, 0x81, /* TSS_CONTROL_MUT */ + 0x03, 0x06, 0x00, 0x00, /* TSS_LENGTH_MUT */ + 0xFF, 0x00, 0xAF, 0xC0, /* TSS_TX_CONFIG_MUT */ + 0xFF, 0xFF, 0xB0, 0x00, /* TSS_TX_CONTROL_MUT */ + 0x22, 0x02, 0x7F, 0x81, /* TSS_SEQ_CONFIG1_MUT */ + 0x7F, 0x72, 0x01, 0x80, /* TSS_SEQ_CONFIG2_MUT */ + 0x06, 0x01, 0x48, 0x04, /* TSS_SEQ_CONFIG3_MUT */ + 0x43, 0x28, 0x3C, 0x28, /* TSS_SEQ_CONFIG4_MUT */ + 0x12, 0x01, 0x01, 0x00, /* TSS_SEQ_CONFIG5_MUT */ + 0x04, 0x01, 0x08, 0x10, /* TSS_SEQ_CONFIG6_MUT */ + 0x01, 0x04, 0x00, 0x00, /* TSS_SEQ_CONFIG7_MUT */ + 0x44, 0x01, 0x02, 0x80, /* TSS_SEQ_CONFIG8_MUT */ + 0x01, 0x01, 0x00, 0x00, /* TSS_EXT_CONFIG1_MUT */ + 0x80, 0x00, 0x01, 0x00, /* TSS_EXT_CONFIG2_MUT */ + 0x00, 0x00, 0x00, 0x00, /* TSS_EXT_INTERVAL_MUT */ + 0x01, 0x01, 0x00, 0x90, /* TSS_INT_CONFIG1_MUT */ + 0x80, 0x00, 0xFE, 0x0B, /* TSS_INT_CONFIG2_MUT */ + 0x00, 0x00, 0x00, 0x00, /* TSS_INT_INTERVAL_MUT */ + 0x00, 0x00, 0x00, 0x00, /* TSS_MCS_CONFIG_MUT */ + 0x7A, 0xA0, 0x00, 0xD0, /* TSS_RX_CONFIG_MUT */ + 0x00, 0x00, 0x00, 0x00, /* Reserved668 */ + 0x05, 0x04, 0xFF, 0x81, /* TSS_CONTROL_SELF */ + 0x04, 0x0C, 0x00, 0x00, /* TSS_LENGTH_SELF */ + 0xFF, 0x02, 0xAF, 0xC0, /* TSS_TX_CONFIG_SELF */ + 0xFF, 0xFF, 0xD0, 0x00, /* TSS_TX_CONTROL_SELF */ + 0x22, 0x02, 0x7F, 0x81, /* TSS_SEQ_CONFIG1_SELF */ + 0x7F, 0x72, 0x01, 0x80, /* TSS_SEQ_CONFIG2_SELF */ + 0x01, 0x81, 0x40, 0x04, /* TSS_SEQ_CONFIG3_SELF */ + 0x31, 0x0F, 0x31, 0x0F, /* TSS_SEQ_CONFIG4_SELF */ + 0x12, 0x01, 0x01, 0x00, /* TSS_SEQ_CONFIG5_SELF */ + 0x04, 0x01, 0x08, 0x10, /* TSS_SEQ_CONFIG6_SELF */ + 0x01, 0x04, 0x00, 0x00, /* TSS_SEQ_CONFIG7_SELF */ + 0x44, 0x01, 0x02, 0x80, /* TSS_SEQ_CONFIG8_SELF */ + 0x01, 0x01, 0x00, 0x00, /* TSS_EXT_CONFIG1_SELF */ + 0x80, 0x00, 0x01, 0x00, /* TSS_EXT_CONFIG2_SELF */ + 0x00, 0x00, 0x00, 0x00, /* TSS_EXT_INTERVAL_SELF */ + 0x01, 0x01, 0x00, 0x90, /* TSS_INT_CONFIG1_SELF */ + 0x80, 0x00, 0xFE, 0x0B, /* TSS_INT_CONFIG2_SELF */ + 0x00, 0x00, 0x00, 0x00, /* TSS_INT_INTERVAL_SELF */ + 0x00, 0x00, 0x00, 0x00, /* TSS_MCS_CONFIG_SELF */ + 0x3A, 0xA6, 0x00, 0xD0, /* TSS_RX_CONFIG_SELF */ + 0x00, 0x00, 0x00, 0x00, /* Reserved752 */ + 0x05, 0x04, 0xFF, 0x80, /* TSS_CONTROL_BAL */ + 0x03, 0x20, 0x00, 0x00, /* TSS_LENGTH_BAL */ + 0xAF, 0x08, 0xAF, 0xC0, /* TSS_TX_CONFIG_BAL */ + 0xFF, 0xFF, 0xB0, 0x00, /* TSS_TX_CONTROL_BAL */ + 0x22, 0x02, 0x7F, 0x81, /* TSS_SEQ_CONFIG1_BAL */ + 0x7F, 0x72, 0x01, 0x80, /* TSS_SEQ_CONFIG2_BAL */ + 0x01, 0x81, 0x40, 0x04, /* TSS_SEQ_CONFIG3_BAL */ + 0x96, 0x0F, 0x96, 0x0F, /* TSS_SEQ_CONFIG4_BAL */ + 0x12, 0x01, 0x01, 0x00, /* TSS_SEQ_CONFIG5_BAL */ + 0x04, 0x01, 0x08, 0x10, /* TSS_SEQ_CONFIG6_BAL */ + 0x01, 0x04, 0x00, 0x00, /* TSS_SEQ_CONFIG7_BAL */ + 0x44, 0x01, 0x02, 0x80, /* TSS_SEQ_CONFIG8_BAL */ + 0x01, 0x01, 0x00, 0x00, /* TSS_EXT_CONFIG1_BAL */ + 0x80, 0x00, 0x01, 0x00, /* TSS_EXT_CONFIG2_BAL */ + 0x00, 0x00, 0x00, 0x00, /* TSS_EXT_INTERVAL_BAL */ + 0x01, 0x01, 0x00, 0x90, /* TSS_INT_CONFIG1_BAL */ + 0x80, 0x00, 0xFE, 0x0B, /* TSS_INT_CONFIG2_BAL */ + 0x00, 0x00, 0x00, 0x00, /* TSS_INT_INTERVAL_BAL */ + 0x00, 0x00, 0x00, 0x00, /* TSS_MCS_CONFIG_BAL */ + 0x3A, 0xA0, 0x00, 0xD0, /* TSS_RX_CONFIG_BAL */ + 0x05, 0x04, 0xFF, 0x80, /* TSS_CONTROL_BTN */ + 0x03, 0x24, 0x00, 0x00, /* TSS_LENGTH_BTN_MUT */ + 0xFF, 0x00, 0xAF, 0xC0, /* TSS_TX_CONFIG_BTN */ + 0xFF, 0xFF, 0xB0, 0x00, /* TSS_TX_CONTROL_BTN */ + 0x22, 0x02, 0x7F, 0x81, /* TSS_SEQ_CONFIG1_BTN */ + 0x7F, 0x72, 0x01, 0x80, /* TSS_SEQ_CONFIG2_BTN */ + 0x06, 0x01, 0x48, 0x04, /* TSS_SEQ_CONFIG3_BTN */ + 0x31, 0x23, 0x31, 0x23, /* TSS_SEQ_CONFIG4_BTN */ + 0x12, 0x01, 0x01, 0x00, /* TSS_SEQ_CONFIG5_BTN */ + 0x04, 0x01, 0x08, 0x10, /* TSS_SEQ_CONFIG6_BTN */ + 0x01, 0x04, 0x00, 0x00, /* TSS_SEQ_CONFIG7_BTN */ + 0x44, 0x01, 0x02, 0x80, /* TSS_SEQ_CONFIG8_BTN */ + 0x01, 0x01, 0x00, 0x00, /* TSS_EXT_CONFIG1_BTN */ + 0x80, 0x00, 0x01, 0x00, /* TSS_EXT_CONFIG2_BTN */ + 0x00, 0x00, 0x00, 0x00, /* TSS_EXT_INTERVAL_BTN */ + 0x01, 0x01, 0x00, 0x90, /* TSS_INT_CONFIG1_BTN */ + 0x80, 0x00, 0xFE, 0x0B, /* TSS_INT_CONFIG2_BTN */ + 0x00, 0x00, 0x00, 0x00, /* TSS_INT_INTERVAL_BTN */ + 0x00, 0x00, 0x00, 0x00, /* TSS_MCS_CONFIG_BTN */ + 0x7A, 0xA0, 0x00, 0xD0, /* TSS_RX_CONFIG_BTN */ + 0x03, 0x08, 0x00, 0x00, /* TSS_LENGTH_BTN_SELF */ + 0x00, 0x00, 0x30, 0x30, /* TSS_RX_VREF */ + 0x40, 0x03, 0x07, 0x40, /* TSS_RX_LX_CONFIG */ + 0x15, 0x00, 0x00, 0x00, /* TX_NUM */ + 0x0D, 0x00, 0x00, 0x00, /* RX_NUM */ + 0x22, 0x00, 0x00, 0x00, /* SENS_NUM */ + 0x11, 0x01, 0x00, 0x00, /* CROSS_NUM */ + 0x02, 0x00, 0x00, 0x00, /* BUTTON_NUM */ + 0x02, 0x00, 0x00, 0x00, /* SLOTS_MUT */ + 0x02, 0x00, 0x00, 0x00, /* SLOTS_SELF_RX */ + 0x03, 0x00, 0x00, 0x00, /* SLOTS_SELF_TX */ + 0x05, 0x00, 0x00, 0x00, /* SLOTS_SELF */ + 0x0A, 0x00, 0x00, 0x00, /* SLOTS_BAL */ + 0x2D, 0x00, 0x00, 0x00, /* SCALE_MUT */ + 0x64, 0x00, 0x00, 0x00, /* SCALE_SELF */ + 0x64, 0x00, 0x00, 0x00, /* SCALE_BAL */ + 0x2D, 0x00, 0x00, 0x00, /* SCALE_BUTTON */ + 0x00, 0x00, 0x00, 0x00, /* LX_MODE */ + 0x50, 0x00, 0x00, 0x00, /* LX_SCALE */ + 0x01, 0x00, 0x00, 0x00, /* ABSOLUTE_CR_CORRECTION_ENABLE */ + 0x02, 0x00, 0x00, 0x00, /* SCANNING_MODE_MUTUAL */ + 0x02, 0x00, 0x00, 0x00, /* SCANNING_MODE_BUTTON */ + 0x0F, 0x00, /* DETECT_CHARGER_THRESHOLD */ + 0x01, /* CA_LX_SCAN_MODE */ + 0x00, /* SUB_SLOT_SCAN */ + 0x0F, /* NOISE_METRIC1_THRESHOLD */ + 0x0F, /* NOISE_METRIC2_THRESHOLD */ + 0x32, /* NOISE_METRIC3_THRESHOLD */ + 0x00, /* AFH_DYNAMIC_THRSH_ENABLE */ + 0x04, /* ADC_CONFIG */ + 0x00, /* Reserved1013 */ + 0x04, /* TSS_LDO_PROG */ + 0x02, /* TX_PERIOD_DUMMY_SCAN */ + 0x01, /* SINGLE_ENDED_LISTEN_SCAN */ + 0x01, /* SPREAD_MTX */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, /* Reserved1018 */ + 0x34, 0x00, 0x00, 0x00, /* CALIBRATION_PARAM_SIZE */ + 0x01, 0x00, 0x00, 0x00, /* Reserved1112 */ + 0x01, 0x00, 0x00, 0x00, /* Reserved1116 */ + 0x01, 0x00, 0x00, 0x00, /* Reserved1120 */ + 0x01, 0x00, 0x00, 0x00, /* Reserved1124 */ + 0x01, 0x00, 0x00, 0x00, /* GLOBAL_IDAC_LSB_MUTUAL */ + 0x01, 0x00, 0x00, 0x00, /* GLOBAL_IDAC_LSB_SELF */ + 0x01, 0x00, 0x00, 0x00, /* GLOBAL_IDAC_LSB_BALANCED */ + 0x01, 0x00, 0x00, 0x00, /* GLOBAL_IDAC_LSB_BUTTON */ + 0x00, 0x00, 0x00, 0x00, /* TARGET_LEVEL_MUTUAL */ + 0x00, 0x00, 0x00, 0x00, /* TARGET_LEVEL_SELF */ + 0x00, 0x00, 0x00, 0x00, /* TARGET_LEVEL_BALANCED */ + 0xCE, 0xFF, 0xFF, 0xFF, /* TARGET_LEVEL_BUTTON */ + 0x01, 0x00, 0x00, 0x00, /* GAIN_MUTUAL */ + 0x01, 0x00, 0x00, 0x00, /* GAIN_SELF */ + 0x01, 0x00, 0x00, 0x00, /* GAIN_BALANCED */ + 0x01, 0x00, 0x00, 0x00, /* GAIN_BTN_MUTUAL */ + 0x01, 0x00, 0x00, 0x00, /* GAIN_BTN_SELF */ + 0x00, 0x00, 0x00, 0x00, /* Reserved1180 */ + 0x08, 0x00, 0x00, 0x00, /* SPREADER_CFG_SIZE */ + 0x00, 0x00, 0x00, 0x00, /* CLK_IMO_SPREAD */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* Reserved1192 */ + 0x11, 0x12, 0x13, 0x14, + 0x15, 0x16, 0x17, 0x18, + 0x19, 0x22, 0x23, 0x24, + 0x25, 0x38, 0x37, 0x36, + 0x2D, 0x2C, 0x2B, 0x2A, + 0x29, 0x28, 0x27, 0x3B, + 0x3A, 0x39, 0x01, 0x02, + 0x03, 0x04, 0x05, 0x0E, + 0x0F, 0x10, 0x10, 0x27, + 0x26, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, /* CDC_PIN_INDEX_TABLE */ + 0x00, 0x00, 0x00, /* Reserved1281 */ + 0x38, 0x2B, 0x38, 0x2B, + 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x13, 0x13, + 0x00, 0x00, /* CDC_BALANCED_LX_TABLE */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, /* Reserved1298 */ + 0x80, 0x1F, 0x00, 0xFF, + 0x03, 0x00, 0x00, 0x00, + 0x00, 0x07, 0xFC, 0x03, + 0xE0, 0x03, 0x00, 0x00, + 0x00, 0x00, /* CDC_BALANCED_TX_PATTERNS */ + 0x00, 0x00, /* Reserved1322 */ + 0x7E, 0x00, 0x06, 0x10, + 0x00, 0x00, 0x01, 0x02, + 0x03, 0x04, 0x05, 0x00, + 0x00, 0x0F, 0x0B, 0x0A, + 0x09, 0x09, 0x0A, 0x0A, + 0x0F, 0x0F, 0xBF, 0x00, + 0x07, 0x10, 0x07, 0x08, + 0x09, 0x0A, 0x0B, 0x0C, + 0x00, 0x06, 0x00, 0x0B, + 0x0B, 0x0B, 0x0A, 0x0B, + 0x0B, 0x0F, 0x0A, 0x0F, + 0xFF, 0x00, 0x08, 0x38, + 0x21, 0x14, 0x13, 0x12, + 0x1D, 0x1E, 0x1F, 0x20, + 0x00, 0x0B, 0x0B, 0x0B, + 0x0B, 0x0A, 0x0A, 0x09, + 0x0A, 0x0F, 0x8F, 0x00, + 0x05, 0x10, 0x15, 0x19, + 0x18, 0x17, 0x00, 0x00, + 0x00, 0x16, 0x00, 0x0B, + 0x0B, 0x0B, 0x0B, 0x0F, + 0x0F, 0x0F, 0x0B, 0x0F, + 0xFF, 0x00, 0x08, 0x10, + 0x0D, 0x1A, 0x1B, 0x1C, + 0x11, 0x10, 0x0F, 0x0E, + 0x00, 0x0A, 0x0A, 0x0A, + 0x0A, 0x0B, 0x0B, 0x0A, + 0x0A, 0x0F, 0x81, 0x00, + 0x02, 0x14, 0x22, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x23, 0x00, 0x0B, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0B, 0x00, + 0x11, 0x00, 0x02, 0x14, + 0x23, 0x00, 0x00, 0x00, + 0x22, 0x00, 0x00, 0x00, + 0x00, 0x0B, 0x00, 0x00, + 0x00, 0x09, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* CDC_SLOT_TABLE */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* Reserved1500 */ + 0xC4, 0x12, /* CONFIG_CRC */ +};
+
+/* Touchscreen Parameters Field Sizes (Writable: 0:Readonly; 1:Writable) */
+static const uint16_t cyttsp4_param_size[] = {
+/* Size Name */
+ 2, /* CONFIG_DATA_SIZE */ + 2, /* CONFIG_DATA_MAX_SIZE */ + 4, /* SDK_CTRL_CFG_SIZE */ + 2, /* CONFIG_VER */ + 1, /* PANELID_ENABLE */ + 1, /* IMO_FREQ_MHZ */ + 2, /* X_LEN_PHY */ + 2, /* Y_LEN_PHY */ + 1, /* HST_MODE0 */ + 1, /* ACT_DIST0 */ + 1, /* SCAN_TYP0 */ + 1, /* ACT_INTRVL0 */ + 1, /* ACT_LFT_INTRVL0 */ + 1, /* Reserved21 */ + 2, /* LP_INTRVL0 */ + 2, /* TCH_TMOUT0 */ + 1, /* PWR_CFG */ + 1, /* Reserved27 */ + 1, /* INT_PULSE_DATA */ + 1, /* OPMODE_CFG */ + 2, /* HANDSHAKE_TIMEOUT */ + 2, /* ESD_COUNTER_CFG */ + 1, /* TIMER_CAL_INTERVAL */ + 1, /* Reserved35 */ + 2, /* RP2P_MIN */ + 2, /* ILEAK_MAX */ + 2, /* RFB_P2P */ + 2, /* RFB_EXT */ + 1, /* IDACOPEN_LOW */ + 1, /* IDACOPEN_HIGH */ + 1, /* IDACOPEN_BUTTON_LOW */ + 1, /* IDACOPEN_BUTTON_HIGH */ + 1, /* GIDAC_OPEN */ + 1, /* GAIN_OPEN */ + 1, /* GIDAC_BUTTON_OPEN */ + 1, /* GAIN_BUTTON_OPEN */ + 1, /* POST_CFG */ + 1, /* GESTURE_CFG */ + 1, /* GEST_EN0 */ + 1, /* GEST_EN1 */ + 1, /* GEST_EN2 */ + 1, /* GEST_EN3 */ + 1, /* GEST_EN4 */ + 1, /* GEST_EN5 */ + 1, /* GEST_EN6 */ + 1, /* GEST_EN7 */ + 1, /* GEST_EN8 */ + 1, /* GEST_EN9 */ + 1, /* GEST_EN10 */ + 1, /* GEST_EN11 */ + 1, /* GEST_EN12 */ + 1, /* GEST_EN13 */ + 1, /* GEST_EN14 */ + 1, /* GEST_EN15 */ + 1, /* GEST_EN16 */ + 1, /* GEST_EN17 */ + 1, /* GEST_EN18 */ + 1, /* GEST_EN19 */ + 1, /* GEST_EN20 */ + 1, /* GEST_EN21 */ + 1, /* GEST_EN22 */ + 1, /* GEST_EN23 */ + 1, /* GEST_EN24 */ + 1, /* GEST_EN25 */ + 1, /* GEST_EN26 */ + 1, /* GEST_EN27 */ + 1, /* GEST_EN28 */ + 1, /* GEST_EN29 */ + 1, /* GEST_EN30 */ + 1, /* GEST_EN31 */ + 1, /* ACT_DIST2 */ + 1, /* EXTERN_SYNC */ + 8, /* Reserved88 */ + 4, /* GRIP_CFG_SIZE */ + 2, /* GRIP_XEDG_A */ + 2, /* GRIP_XEDG_B */ + 2, /* GRIP_XEXC_A */ + 2, /* GRIP_XEXC_B */ + 2, /* GRIP_YEDG_A */ + 2, /* GRIP_YEDG_B */ + 2, /* GRIP_YEXC_A */ + 2, /* GRIP_YEXC_B */ + 1, /* GRIP_FIRST_EXC */ + 1, /* GRIP_EXC_EDGE_ORIGIN */ + 2, /* Reserved118 */ + 4, /* TRUETOUCH_CFG_SIZE */ + 4, /* MAX_SELF_SCAN_INTERVAL */ + 4, /* MAX_MUTUAL_SCAN_INTERVAL */ + 4, /* MAX_BALANCED_SCAN_INTERVAL */ + 4, /* SELF_Z_THRSH */ + 4, /* SELF_Z_MODE */ + 4, /* SMART_SCAN_ENABLE */ + 4, /* T_COMP_ENABLE */ + 4, /* T_COMP_INTERVAL */ + 4, /* T_COMP_RECAL_MUTUAL_SENSOR_LIMIT */ + 4, /* T_COMP_RECAL_MUTUAL_HIGH */ + 4, /* T_COMP_RECAL_MUTUAL_LOW */ + 4, /* T_COMP_RECAL_SELF_SENSOR_LIMIT */ + 4, /* T_COMP_RECAL_SELF_HIGH */ + 4, /* T_COMP_RECAL_SELF_LOW */ + 4, /* CHARGER_ARMOR_ENABLE */ + 4, /* AFH_ENABLE */ + 4, /* AFH_LISTENING_SCAN_COUNT */ + 4, /* AFH_LISTEN_SCAN_CYCLE_REPEATS */ + 4, /* CA_BLOCK_NOISE_THRESHOLD */ + 4, /* CA_BLOCK_NOISE_HYSTERESIS */ + 4, /* CA_DEFAULT_REVERT_TIME */ + 2, /* CA_SMART_H2O_REJECT */ + 2, /* CA_HOST_CONTROLLED_CHARGER */ + 2, /* T_COMP_BUTTON_MUTUAL_HIGH */ + 2, /* T_COMP_BUTTON_MUTUAL_LOW */ + 2, /* T_COMP_BUTTON_SELF_HIGH */ + 2, /* T_COMP_BUTTON_SELF_LOW */ + 4, /* CA_NUM_SUB_CONV_BASE_SELF */ + 4, /* CA_ALT_NUM_SUB_CONV_SELF */ + 12, /* Reserved228 */ + 1, /* CA_ALT_NUM_SUB_CONV_MUTUAL */ + 1, /* CA_ALT_ACQUISITION_FLAGS */ + 1, /* AFH_ALT_TX_PERIOD1 */ + 1, /* AFH_ALT_TX_PERIOD1_MUTUAL_SCALE_FACTOR */ + 1, /* AFH_ALT_TX_PERIOD1_MUTUAL_TX_VOLTAGE */ + 1, /* AFH_ALT_TX_PULSES1 */ + 1, /* AFH_ALT_TX_PERIOD2 */ + 1, /* AFH_ALT_TX_PERIOD2_MUTUAL_SCALE_FACTOR */ + 1, /* AFH_ALT_TX_PERIOD2_MUTUAL_TX_VOLTAGE */ + 1, /* AFH_ALT_TX_PULSES2 */ + 2, /* Reserved250 */ + 1, /* GEST_CFG_SIZE */ + 1, /* PAN_ACT_DSTX */ + 1, /* PAN_ACT_DSTY */ + 1, /* ZOOM_ACT_DSTX */ + 1, /* ZOOM_ACT_DSTY */ + 1, /* FLICK_ACT_DISTX */ + 1, /* FLICK_ACT_DISTY */ + 1, /* FLICK_TIME */ + 1, /* ST_DEBOUNCE */ + 1, /* MT_DEBOUNCE_PAN */ + 1, /* MT_DEBOUNCE_ZOOM */ + 1, /* MT_DEBOUNCE_P2Z */ + 1, /* ROT_DEBOUNCE */ + 1, /* COMPL_DEBOUNCE */ + 2, /* MT_TIMEOUT */ + 1, /* ST_DBLCLK_RMAX */ + 1, /* ST_CLICK_DISTX */ + 1, /* ST_CLICK_DISTY */ + 1, /* Reserved271 */ + 2, /* MT_CLICK_TMAX */ + 2, /* MT_CLICK_TMIN */ + 2, /* ST_CLICK_TMAX */ + 2, /* ST_CLICK_TMIN */ + 2, /* ST_DBLCLK_TMAX */ + 2, /* ST_DBLCLK_TMIN */ + 1, /* GESTURE_GROUP_MASK */ + 1, /* GESTURE_GROUP1_START */ + 1, /* GESTURE_GROUP1_END */ + 1, /* GESTURE_GROUP2_START */ + 1, /* GESTURE_GROUP2_END */ + 1, /* GESTURE_GROUP3_START */ + 1, /* GESTURE_GROUP3_END */ + 1, /* GESTURE_GROUP4_START */ + 1, /* GESTURE_GROUP4_END */ + 3, /* Reserved293 */ + 4, /* XY_FILT_CFG_SIZE */ + 4, /* XY_FILTER_MASK */ + 4, /* XY_FILT_IIR_COEFF */ + 4, /* XY_FILT_Z_IIR_COEFF */ + 1, /* XY_FILT_XY_FAST_THR */ + 1, /* XY_FILT_XY_SLOW_THR */ + 1, /* XY_FILT_IIR_FAST_COEFF */ + 1, /* Reserved315 */ + 4, /* XY_FILTER_MASK_CA */ + 4, /* XY_FILT_IIR_COEFF_CA */ + 4, /* XY_FILT_Z_IIR_COEFF_CA */ + 1, /* XY_FILT_XY_FAST_THR_CA */ + 1, /* XY_FILT_XY_SLOW_THR_CA */ + 1, /* XY_FILT_IIR_FAST_COEFF_CA */ + 1, /* Reserved331 */ + 1, /* XY_FILT_ADAPTIVE_IIR_FILTER */ + 1, /* XY_FILT_ADAPTIVE_IIR_FILTER_DISTANCE */ + 1, /* XY_FILT_TOUCH_SIZE_IIR_COEFF */ + 1, /* XY_FILT_TOUCH_SIZE_HYST */ + 1, /* XY_FILT_TOUCH_ORIENTATION_IIR_COEFF */ + 1, /* XY_FILT_TOUCH_ORIENTATION_HYST */ + 1, /* XY_FILT_TOUCH_SCALLOPING_ENABLE */ + 9, /* Reserved339 */ + 4, /* FINGER_ID_CFG_SIZE */ + 4, /* Reserved352 */ + 4, /* FINGER_ID_MAX_FINGER_VELOCITY2 */ + 1, /* LIFTOFF_DEBOUNCE */ + 7, /* Reserved361 */ + 4, /* CENTROID_SH_CFG_SIZE */ + 4, /* STYLUS_THRSH */ + 4, /* STYLUS_HYST */ + 4, /* S2F_THRESHOLD */ + 4, /* HOVER_THRSH */ + 4, /* HOVER_HYST */ + 8, /* Reserved392 */ + 4, /* ID_COORDS_CFG_SIZE */ + 1, /* LRG_OBJ_CFG */ + 1, /* MAX_FAT_FINGER_SIZE */ + 1, /* MIN_FAT_FINGER_SIZE */ + 1, /* FINGER_THRESH_MUTUAL */ + 2, /* FINGER_THRESH_SELF */ + 1, /* INNER_EDGE_GAIN */ + 1, /* OUTER_EDGE_GAIN */ + 4, /* X_RESOLUTION */ + 4, /* Y_RESOLUTION */ + 4, /* SENSOR_ASSIGNMENT */ + 4, /* Z_SCALING */ + 1, /* RX_LINE_FILTER */ + 1, /* BYPASS_THRESHOLD_GAIN */ + 1, /* BYPASS_THRESHOLD_EDGE_GAIN */ + 1, /* FINGER_THR_MUT_HYST */ + 1, /* MAX_FAT_FINGER_SIZE_HYST */ + 1, /* MIN_FAT_FINGER_SIZE_HYST */ + 1, /* MULTI_TOUCH_DEBOUNCE */ + 1, /* CA_FINGER_THRESHOLD_MUTUAL */ + 1, /* FAT_FINGER_THRESHOLD_COEFF */ + 1, /* SIZE_ORIENTATION_ENABLE */ + 1, /* MAJOR_AXIS_OFFSET */ + 1, /* MAJOR_AXIS_SCALE */ + 1, /* MINOR_AXIS_OFFSET */ + 1, /* MINOR_AXIS_SCALE */ + 1, /* RX_LINE_FILTER_DEBOUNCE */ + 1, /* CLIPPING_X_LOW */ + 1, /* CLIPPING_X_HIGH */ + 1, /* CLIPPING_Y_LOW */ + 1, /* CLIPPING_Y_HIGH */ + 1, /* COEF_EDGE_ATTRACTION */ + 2, /* WIDTH_CORNER_DIAG1 */ + 2, /* WIDTH_CORNER_DIAG2 */ + 2, /* WIDTH_CORNER_DIAG3 */ + 2, /* WIDTH_CORNER_DIAG4 */ + 2, /* WIDTH_CORNER_DIAG5 */ + 2, /* WIDTH_CORNER_DIAG6 */ + 2, /* WIDTH_CORNER_DIAG7 */ + 2, /* WIDTH_CORNER_DIAG8 */ + 2, /* WIDTH_CORNER_DIAG9 */ + 2, /* WIDTH_CORNER_DIAG10 */ + 2, /* WIDTH_CORNER_DIAG11 */ + 2, /* WIDTH_CORNER_PERP1 */ + 2, /* WIDTH_CORNER_PERP2 */ + 2, /* WIDTH_CORNER_PERP3 */ + 2, /* WIDTH_CORNER_PERP4 */ + 1, /* RX_LINE_FILTER_THRESHOLD */ + 1, /* NOISE_REJECTION_3x3_FILTER_SCALE */ + 1, /* NOISE_REJECTION_3x3_FILTER_SCALE_CA */ + 1, /* DIRECT_XY_ENABLE */ + 2, /* Reserved482 */ + 4, /* BTN_CFG_SIZE */ + 2, /* BTN_THRSH_MUT_0 */ + 2, /* BTN_THRSH_MUT_1 */ + 2, /* BTN_THRSH_MUT_2 */ + 2, /* BTN_THRSH_MUT_3 */ + 1, /* BTN_HYST_MUT */ + 1, /* Reserved497 */ + 1, /* Reserved498 */ + 1, /* Reserved499 */ + 2, /* BTN_THRSH_SELF */ + 2, /* BTN_THRSH_SELF_1 */ + 2, /* BTN_THRSH_SELF_2 */ + 2, /* BTN_THRSH_SELF_3 */ + 1, /* BTN_HYST_SELF */ + 1, /* Reserved509 */ + 1, /* Reserved510 */ + 1, /* Reserved511 */ + 4, /* RAW_PROC_CFG_SIZE */ + 2, /* RAW_FILTER_MASK */ + 1, /* RAW_FILT_IIR_COEFF_MUTUAL */ + 1, /* RAW_FILT_IIR_THRESHOLD_MUTUAL */ + 1, /* RAW_FILT_IIR_COEFF_SELF */ + 1, /* RAW_FILT_IIR_THRESHOLD_SELF */ + 1, /* RAW_FILT_IIR_COEFF_BALANCED */ + 1, /* RAW_FILT_IIR_THRESHOLD_BALANCED */ + 1, /* RAW_FILT_IIR_COEFF_BUTTONS */ + 1, /* RAW_FILT_IIR_THRESHOLD_BUTTONS */ + 2, /* Reserved526 */ + 2, /* RAW_FILTER_MASK_CA */ + 1, /* RAW_FILT_IIR_COEFF_MUTUAL_CA */ + 1, /* RAW_FILT_IIR_THRESHOLD_MUTUAL_CA */ + 1, /* RAW_FILT_IIR_COEFF_SELF_CA */ + 1, /* RAW_FILT_IIR_THRESHOLD_SELF_CA */ + 1, /* RAW_FILT_IIR_COEFF_BALANCED_CA */ + 1, /* RAW_FILT_IIR_THRESHOLD_BALANCED_CA */ + 1, /* RAW_FILT_IIR_COEFF_BUTTONS_CA */ + 1, /* RAW_FILT_IIR_THRESHOLD_BUTTONS_CA */ + 2, /* Reserved538 */ + 12, /* Reserved540 */ + 1, /* BL_DELAY_MUT */ + 1, /* BL_DELAY_SELF */ + 1, /* BL_DELAY_BAL */ + 1, /* BL_DELAY_BTN */ + 1, /* BL_THR_MUT */ + 1, /* BL_THR_SELF */ + 1, /* BL_THR_BAL */ + 1, /* BL_THR_BTN_MUT */ + 1, /* BL_THR_BTN_SELF */ + 1, /* BL_MUT_SIG_THRESHOLD_CA */ + 1, /* BL_FILT_MUT */ + 1, /* BL_FILT_SELF */ + 1, /* BL_FILT_BAL */ + 1, /* BL_FILT_BTN_MUT */ + 1, /* BL_FILT_BTN_SELF */ + 1, /* CMF_THR_MUT */ + 1, /* CMF_THR_SELF */ + 1, /* CMF_THR_BAL */ + 1, /* CMF_THR_BTN_MUT */ + 1, /* CMF_THR_BTN_SELF */ + 4, /* Reserved572 */ + 4, /* H2OREJECTION_SIZE */ + 1, /* BL_H20_RJCT */ + 1, /* BL_H20_SNS_WIDTH */ + 2, /* Reserved582 */ + 4, /* CDC_CFG_SIZE */ + 4, /* TSS_CONTROL_MUT */ + 4, /* TSS_LENGTH_MUT */ + 4, /* TSS_TX_CONFIG_MUT */ + 4, /* TSS_TX_CONTROL_MUT */ + 4, /* TSS_SEQ_CONFIG1_MUT */ + 4, /* TSS_SEQ_CONFIG2_MUT */ + 4, /* TSS_SEQ_CONFIG3_MUT */ + 4, /* TSS_SEQ_CONFIG4_MUT */ + 4, /* TSS_SEQ_CONFIG5_MUT */ + 4, /* TSS_SEQ_CONFIG6_MUT */ + 4, /* TSS_SEQ_CONFIG7_MUT */ + 4, /* TSS_SEQ_CONFIG8_MUT */ + 4, /* TSS_EXT_CONFIG1_MUT */ + 4, /* TSS_EXT_CONFIG2_MUT */ + 4, /* TSS_EXT_INTERVAL_MUT */ + 4, /* TSS_INT_CONFIG1_MUT */ + 4, /* TSS_INT_CONFIG2_MUT */ + 4, /* TSS_INT_INTERVAL_MUT */ + 4, /* TSS_MCS_CONFIG_MUT */ + 4, /* TSS_RX_CONFIG_MUT */ + 4, /* Reserved668 */ + 4, /* TSS_CONTROL_SELF */ + 4, /* TSS_LENGTH_SELF */ + 4, /* TSS_TX_CONFIG_SELF */ + 4, /* TSS_TX_CONTROL_SELF */ + 4, /* TSS_SEQ_CONFIG1_SELF */ + 4, /* TSS_SEQ_CONFIG2_SELF */ + 4, /* TSS_SEQ_CONFIG3_SELF */ + 4, /* TSS_SEQ_CONFIG4_SELF */ + 4, /* TSS_SEQ_CONFIG5_SELF */ + 4, /* TSS_SEQ_CONFIG6_SELF */ + 4, /* TSS_SEQ_CONFIG7_SELF */ + 4, /* TSS_SEQ_CONFIG8_SELF */ + 4, /* TSS_EXT_CONFIG1_SELF */ + 4, /* TSS_EXT_CONFIG2_SELF */ + 4, /* TSS_EXT_INTERVAL_SELF */ + 4, /* TSS_INT_CONFIG1_SELF */ + 4, /* TSS_INT_CONFIG2_SELF */ + 4, /* TSS_INT_INTERVAL_SELF */ + 4, /* TSS_MCS_CONFIG_SELF */ + 4, /* TSS_RX_CONFIG_SELF */ + 4, /* Reserved752 */ + 4, /* TSS_CONTROL_BAL */ + 4, /* TSS_LENGTH_BAL */ + 4, /* TSS_TX_CONFIG_BAL */ + 4, /* TSS_TX_CONTROL_BAL */ + 4, /* TSS_SEQ_CONFIG1_BAL */ + 4, /* TSS_SEQ_CONFIG2_BAL */ + 4, /* TSS_SEQ_CONFIG3_BAL */ + 4, /* TSS_SEQ_CONFIG4_BAL */ + 4, /* TSS_SEQ_CONFIG5_BAL */ + 4, /* TSS_SEQ_CONFIG6_BAL */ + 4, /* TSS_SEQ_CONFIG7_BAL */ + 4, /* TSS_SEQ_CONFIG8_BAL */ + 4, /* TSS_EXT_CONFIG1_BAL */ + 4, /* TSS_EXT_CONFIG2_BAL */ + 4, /* TSS_EXT_INTERVAL_BAL */ + 4, /* TSS_INT_CONFIG1_BAL */ + 4, /* TSS_INT_CONFIG2_BAL */ + 4, /* TSS_INT_INTERVAL_BAL */ + 4, /* TSS_MCS_CONFIG_BAL */ + 4, /* TSS_RX_CONFIG_BAL */ + 4, /* TSS_CONTROL_BTN */ + 4, /* TSS_LENGTH_BTN_MUT */ + 4, /* TSS_TX_CONFIG_BTN */ + 4, /* TSS_TX_CONTROL_BTN */ + 4, /* TSS_SEQ_CONFIG1_BTN */ + 4, /* TSS_SEQ_CONFIG2_BTN */ + 4, /* TSS_SEQ_CONFIG3_BTN */ + 4, /* TSS_SEQ_CONFIG4_BTN */ + 4, /* TSS_SEQ_CONFIG5_BTN */ + 4, /* TSS_SEQ_CONFIG6_BTN */ + 4, /* TSS_SEQ_CONFIG7_BTN */ + 4, /* TSS_SEQ_CONFIG8_BTN */ + 4, /* TSS_EXT_CONFIG1_BTN */ + 4, /* TSS_EXT_CONFIG2_BTN */ + 4, /* TSS_EXT_INTERVAL_BTN */ + 4, /* TSS_INT_CONFIG1_BTN */ + 4, /* TSS_INT_CONFIG2_BTN */ + 4, /* TSS_INT_INTERVAL_BTN */ + 4, /* TSS_MCS_CONFIG_BTN */ + 4, /* TSS_RX_CONFIG_BTN */ + 4, /* TSS_LENGTH_BTN_SELF */ + 4, /* TSS_RX_VREF */ + 4, /* TSS_RX_LX_CONFIG */ + 4, /* TX_NUM */ + 4, /* RX_NUM */ + 4, /* SENS_NUM */ + 4, /* CROSS_NUM */ + 4, /* BUTTON_NUM */ + 4, /* SLOTS_MUT */ + 4, /* SLOTS_SELF_RX */ + 4, /* SLOTS_SELF_TX */ + 4, /* SLOTS_SELF */ + 4, /* SLOTS_BAL */ + 4, /* SCALE_MUT */ + 4, /* SCALE_SELF */ + 4, /* SCALE_BAL */ + 4, /* SCALE_BUTTON */ + 4, /* LX_MODE */ + 4, /* LX_SCALE */ + 4, /* ABSOLUTE_CR_CORRECTION_ENABLE */ + 4, /* SCANNING_MODE_MUTUAL */ + 4, /* SCANNING_MODE_BUTTON */ + 2, /* DETECT_CHARGER_THRESHOLD */ + 1, /* CA_LX_SCAN_MODE */ + 1, /* SUB_SLOT_SCAN */ + 1, /* NOISE_METRIC1_THRESHOLD */ + 1, /* NOISE_METRIC2_THRESHOLD */ + 1, /* NOISE_METRIC3_THRESHOLD */ + 1, /* AFH_DYNAMIC_THRSH_ENABLE */ + 1, /* ADC_CONFIG */ + 1, /* Reserved1013 */ + 1, /* TSS_LDO_PROG */ + 1, /* TX_PERIOD_DUMMY_SCAN */ + 1, /* SINGLE_ENDED_LISTEN_SCAN */ + 1, /* SPREAD_MTX */ + 90, /* Reserved1018 */ + 4, /* CALIBRATION_PARAM_SIZE */ + 4, /* Reserved1112 */ + 4, /* Reserved1116 */ + 4, /* Reserved1120 */ + 4, /* Reserved1124 */ + 4, /* GLOBAL_IDAC_LSB_MUTUAL */ + 4, /* GLOBAL_IDAC_LSB_SELF */ + 4, /* GLOBAL_IDAC_LSB_BALANCED */ + 4, /* GLOBAL_IDAC_LSB_BUTTON */ + 4, /* TARGET_LEVEL_MUTUAL */ + 4, /* TARGET_LEVEL_SELF */ + 4, /* TARGET_LEVEL_BALANCED */ + 4, /* TARGET_LEVEL_BUTTON */ + 4, /* GAIN_MUTUAL */ + 4, /* GAIN_SELF */ + 4, /* GAIN_BALANCED */ + 4, /* GAIN_BTN_MUTUAL */ + 4, /* GAIN_BTN_SELF */ + 4, /* Reserved1180 */ + 4, /* SPREADER_CFG_SIZE */ + 4, /* CLK_IMO_SPREAD */ + 24, /* Reserved1192 */ + 65, /* CDC_PIN_INDEX_TABLE */ + 3, /* Reserved1281 */ + 14, /* CDC_BALANCED_LX_TABLE */ + 6, /* Reserved1298 */ + 18, /* CDC_BALANCED_TX_PATTERNS */ + 2, /* Reserved1322 */ + 176, /* CDC_SLOT_TABLE */ + 32, /* Reserved1500 */ + 2, /* CONFIG_CRC */ +};
+
+/* Touchscreen Parameters Field Address*/
+static const uint8_t cyttsp4_param_addr[] = {
+/* Address Name */
+ 0xDC, 0x00, /* CONFIG_DATA_SIZE */ + 0xDC, 0x02, /* CONFIG_DATA_MAX_SIZE */ + 0xDC, 0x04, /* SDK_CTRL_CFG_SIZE */ + 0xDC, 0x08, /* CONFIG_VER */ + 0xDC, 0x0A, /* PANELID_ENABLE */ + 0xDC, 0x0B, /* IMO_FREQ_MHZ */ + 0xDC, 0x0C, /* X_LEN_PHY */ + 0xDC, 0x0E, /* Y_LEN_PHY */ + 0xDC, 0x10, /* HST_MODE0 */ + 0xDC, 0x11, /* ACT_DIST0 */ + 0xDC, 0x12, /* SCAN_TYP0 */ + 0xDC, 0x13, /* ACT_INTRVL0 */ + 0xDC, 0x14, /* ACT_LFT_INTRVL0 */ + 0xDC, 0x15, /* Reserved21 */ + 0xDC, 0x16, /* LP_INTRVL0 */ + 0xDC, 0x18, /* TCH_TMOUT0 */ + 0xDC, 0x1A, /* PWR_CFG */ + 0xDC, 0x1B, /* Reserved27 */ + 0xDC, 0x1C, /* INT_PULSE_DATA */ + 0xDC, 0x1D, /* OPMODE_CFG */ + 0xDC, 0x1E, /* HANDSHAKE_TIMEOUT */ + 0xDC, 0x20, /* ESD_COUNTER_CFG */ + 0xDC, 0x22, /* TIMER_CAL_INTERVAL */ + 0xDC, 0x23, /* Reserved35 */ + 0xDC, 0x24, /* RP2P_MIN */ + 0xDC, 0x26, /* ILEAK_MAX */ + 0xDC, 0x28, /* RFB_P2P */ + 0xDC, 0x2A, /* RFB_EXT */ + 0xDC, 0x2C, /* IDACOPEN_LOW */ + 0xDC, 0x2D, /* IDACOPEN_HIGH */ + 0xDC, 0x2E, /* IDACOPEN_BUTTON_LOW */ + 0xDC, 0x2F, /* IDACOPEN_BUTTON_HIGH */ + 0xDC, 0x30, /* GIDAC_OPEN */ + 0xDC, 0x31, /* GAIN_OPEN */ + 0xDC, 0x32, /* GIDAC_BUTTON_OPEN */ + 0xDC, 0x33, /* GAIN_BUTTON_OPEN */ + 0xDC, 0x34, /* POST_CFG */ + 0xDC, 0x35, /* GESTURE_CFG */ + 0xDC, 0x36, /* GEST_EN0 */ + 0xDC, 0x37, /* GEST_EN1 */ + 0xDC, 0x38, /* GEST_EN2 */ + 0xDC, 0x39, /* GEST_EN3 */ + 0xDC, 0x3A, /* GEST_EN4 */ + 0xDC, 0x3B, /* GEST_EN5 */ + 0xDC, 0x3C, /* GEST_EN6 */ + 0xDC, 0x3D, /* GEST_EN7 */ + 0xDC, 0x3E, /* GEST_EN8 */ + 0xDC, 0x3F, /* GEST_EN9 */ + 0xDC, 0x40, /* GEST_EN10 */ + 0xDC, 0x41, /* GEST_EN11 */ + 0xDC, 0x42, /* GEST_EN12 */ + 0xDC, 0x43, /* GEST_EN13 */ + 0xDC, 0x44, /* GEST_EN14 */ + 0xDC, 0x45, /* GEST_EN15 */ + 0xDC, 0x46, /* GEST_EN16 */ + 0xDC, 0x47, /* GEST_EN17 */ + 0xDC, 0x48, /* GEST_EN18 */ + 0xDC, 0x49, /* GEST_EN19 */ + 0xDC, 0x4A, /* GEST_EN20 */ + 0xDC, 0x4B, /* GEST_EN21 */ + 0xDC, 0x4C, /* GEST_EN22 */ + 0xDC, 0x4D, /* GEST_EN23 */ + 0xDC, 0x4E, /* GEST_EN24 */ + 0xDC, 0x4F, /* GEST_EN25 */ + 0xDC, 0x50, /* GEST_EN26 */ + 0xDC, 0x51, /* GEST_EN27 */ + 0xDC, 0x52, /* GEST_EN28 */ + 0xDC, 0x53, /* GEST_EN29 */ + 0xDC, 0x54, /* GEST_EN30 */ + 0xDC, 0x55, /* GEST_EN31 */ + 0xDC, 0x56, /* ACT_DIST2 */ + 0xDC, 0x57, /* EXTERN_SYNC */ + 0xDC, 0x58, /* Reserved88 */ + 0xDC, 0x60, /* GRIP_CFG_SIZE */ + 0xDC, 0x64, /* GRIP_XEDG_A */ + 0xDC, 0x66, /* GRIP_XEDG_B */ + 0xDC, 0x68, /* GRIP_XEXC_A */ + 0xDC, 0x6A, /* GRIP_XEXC_B */ + 0xDC, 0x6C, /* GRIP_YEDG_A */ + 0xDC, 0x6E, /* GRIP_YEDG_B */ + 0xDC, 0x70, /* GRIP_YEXC_A */ + 0xDC, 0x72, /* GRIP_YEXC_B */ + 0xDC, 0x74, /* GRIP_FIRST_EXC */ + 0xDC, 0x75, /* GRIP_EXC_EDGE_ORIGIN */ + 0xDC, 0x76, /* Reserved118 */ + 0xDC, 0x78, /* TRUETOUCH_CFG_SIZE */ + 0xDC, 0x7C, /* MAX_SELF_SCAN_INTERVAL */ + 0xDC, 0x80, /* MAX_MUTUAL_SCAN_INTERVAL */ + 0xDC, 0x84, /* MAX_BALANCED_SCAN_INTERVAL */ + 0xDC, 0x88, /* SELF_Z_THRSH */ + 0xDC, 0x8C, /* SELF_Z_MODE */ + 0xDC, 0x90, /* SMART_SCAN_ENABLE */ + 0xDC, 0x94, /* T_COMP_ENABLE */ + 0xDC, 0x98, /* T_COMP_INTERVAL */ + 0xDC, 0x9C, /* T_COMP_RECAL_MUTUAL_SENSOR_LIMIT */ + 0xDC, 0xA0, /* T_COMP_RECAL_MUTUAL_HIGH */ + 0xDC, 0xA4, /* T_COMP_RECAL_MUTUAL_LOW */ + 0xDC, 0xA8, /* T_COMP_RECAL_SELF_SENSOR_LIMIT */ + 0xDC, 0xAC, /* T_COMP_RECAL_SELF_HIGH */ + 0xDC, 0xB0, /* T_COMP_RECAL_SELF_LOW */ + 0xDC, 0xB4, /* CHARGER_ARMOR_ENABLE */ + 0xDC, 0xB8, /* AFH_ENABLE */ + 0xDC, 0xBC, /* AFH_LISTENING_SCAN_COUNT */ + 0xDC, 0xC0, /* AFH_LISTEN_SCAN_CYCLE_REPEATS */ + 0xDC, 0xC4, /* CA_BLOCK_NOISE_THRESHOLD */ + 0xDC, 0xC8, /* CA_BLOCK_NOISE_HYSTERESIS */ + 0xDC, 0xCC, /* CA_DEFAULT_REVERT_TIME */ + 0xDC, 0xD0, /* CA_SMART_H2O_REJECT */ + 0xDC, 0xD2, /* CA_HOST_CONTROLLED_CHARGER */ + 0xDC, 0xD4, /* T_COMP_BUTTON_MUTUAL_HIGH */ + 0xDC, 0xD6, /* T_COMP_BUTTON_MUTUAL_LOW */ + 0xDC, 0xD8, /* T_COMP_BUTTON_SELF_HIGH */ + 0xDC, 0xDA, /* T_COMP_BUTTON_SELF_LOW */ + 0xDC, 0xDC, /* CA_NUM_SUB_CONV_BASE_SELF */ + 0xDC, 0xE0, /* CA_ALT_NUM_SUB_CONV_SELF */ + 0xDC, 0xE4, /* Reserved228 */ + 0xDC, 0xF0, /* CA_ALT_NUM_SUB_CONV_MUTUAL */ + 0xDC, 0xF1, /* CA_ALT_ACQUISITION_FLAGS */ + 0xDC, 0xF2, /* AFH_ALT_TX_PERIOD1 */ + 0xDC, 0xF3, /* AFH_ALT_TX_PERIOD1_MUTUAL_SCALE_FACTOR */ + 0xDC, 0xF4, /* AFH_ALT_TX_PERIOD1_MUTUAL_TX_VOLTAGE */ + 0xDC, 0xF5, /* AFH_ALT_TX_PULSES1 */ + 0xDC, 0xF6, /* AFH_ALT_TX_PERIOD2 */ + 0xDC, 0xF7, /* AFH_ALT_TX_PERIOD2_MUTUAL_SCALE_FACTOR */ + 0xDC, 0xF8, /* AFH_ALT_TX_PERIOD2_MUTUAL_TX_VOLTAGE */ + 0xDC, 0xF9, /* AFH_ALT_TX_PULSES2 */ + 0xDC, 0xFA, /* Reserved250 */ + 0xDC, 0xFC, /* GEST_CFG_SIZE */ + 0xDC, 0xFD, /* PAN_ACT_DSTX */ + 0xDC, 0xFE, /* PAN_ACT_DSTY */ + 0xDC, 0xFF, /* ZOOM_ACT_DSTX */ + 0xDD, 0x00, /* ZOOM_ACT_DSTY */ + 0xDD, 0x01, /* FLICK_ACT_DISTX */ + 0xDD, 0x02, /* FLICK_ACT_DISTY */ + 0xDD, 0x03, /* FLICK_TIME */ + 0xDD, 0x04, /* ST_DEBOUNCE */ + 0xDD, 0x05, /* MT_DEBOUNCE_PAN */ + 0xDD, 0x06, /* MT_DEBOUNCE_ZOOM */ + 0xDD, 0x07, /* MT_DEBOUNCE_P2Z */ + 0xDD, 0x08, /* ROT_DEBOUNCE */ + 0xDD, 0x09, /* COMPL_DEBOUNCE */ + 0xDD, 0x0A, /* MT_TIMEOUT */ + 0xDD, 0x0C, /* ST_DBLCLK_RMAX */ + 0xDD, 0x0D, /* ST_CLICK_DISTX */ + 0xDD, 0x0E, /* ST_CLICK_DISTY */ + 0xDD, 0x0F, /* Reserved271 */ + 0xDD, 0x10, /* MT_CLICK_TMAX */ + 0xDD, 0x12, /* MT_CLICK_TMIN */ + 0xDD, 0x14, /* ST_CLICK_TMAX */ + 0xDD, 0x16, /* ST_CLICK_TMIN */ + 0xDD, 0x18, /* ST_DBLCLK_TMAX */ + 0xDD, 0x1A, /* ST_DBLCLK_TMIN */ + 0xDD, 0x1C, /* GESTURE_GROUP_MASK */ + 0xDD, 0x1D, /* GESTURE_GROUP1_START */ + 0xDD, 0x1E, /* GESTURE_GROUP1_END */ + 0xDD, 0x1F, /* GESTURE_GROUP2_START */ + 0xDD, 0x20, /* GESTURE_GROUP2_END */ + 0xDD, 0x21, /* GESTURE_GROUP3_START */ + 0xDD, 0x22, /* GESTURE_GROUP3_END */ + 0xDD, 0x23, /* GESTURE_GROUP4_START */ + 0xDD, 0x24, /* GESTURE_GROUP4_END */ + 0xDD, 0x25, /* Reserved293 */ + 0xDD, 0x28, /* XY_FILT_CFG_SIZE */ + 0xDD, 0x2C, /* XY_FILTER_MASK */ + 0xDD, 0x30, /* XY_FILT_IIR_COEFF */ + 0xDD, 0x34, /* XY_FILT_Z_IIR_COEFF */ + 0xDD, 0x38, /* XY_FILT_XY_FAST_THR */ + 0xDD, 0x39, /* XY_FILT_XY_SLOW_THR */ + 0xDD, 0x3A, /* XY_FILT_IIR_FAST_COEFF */ + 0xDD, 0x3B, /* Reserved315 */ + 0xDD, 0x3C, /* XY_FILTER_MASK_CA */ + 0xDD, 0x40, /* XY_FILT_IIR_COEFF_CA */ + 0xDD, 0x44, /* XY_FILT_Z_IIR_COEFF_CA */ + 0xDD, 0x48, /* XY_FILT_XY_FAST_THR_CA */ + 0xDD, 0x49, /* XY_FILT_XY_SLOW_THR_CA */ + 0xDD, 0x4A, /* XY_FILT_IIR_FAST_COEFF_CA */ + 0xDD, 0x4B, /* Reserved331 */ + 0xDD, 0x4C, /* XY_FILT_ADAPTIVE_IIR_FILTER */ + 0xDD, 0x4D, /* XY_FILT_ADAPTIVE_IIR_FILTER_DISTANCE */ + 0xDD, 0x4E, /* XY_FILT_TOUCH_SIZE_IIR_COEFF */ + 0xDD, 0x4F, /* XY_FILT_TOUCH_SIZE_HYST */ + 0xDD, 0x50, /* XY_FILT_TOUCH_ORIENTATION_IIR_COEFF */ + 0xDD, 0x51, /* XY_FILT_TOUCH_ORIENTATION_HYST */ + 0xDD, 0x52, /* XY_FILT_TOUCH_SCALLOPING_ENABLE */ + 0xDD, 0x53, /* Reserved339 */ + 0xDD, 0x5C, /* FINGER_ID_CFG_SIZE */ + 0xDD, 0x60, /* Reserved352 */ + 0xDD, 0x64, /* FINGER_ID_MAX_FINGER_VELOCITY2 */ + 0xDD, 0x68, /* LIFTOFF_DEBOUNCE */ + 0xDD, 0x69, /* Reserved361 */ + 0xDD, 0x70, /* CENTROID_SH_CFG_SIZE */ + 0xDD, 0x74, /* STYLUS_THRSH */ + 0xDD, 0x78, /* STYLUS_HYST */ + 0xDD, 0x7C, /* S2F_THRESHOLD */ + 0xDD, 0x80, /* HOVER_THRSH */ + 0xDD, 0x84, /* HOVER_HYST */ + 0xDD, 0x88, /* Reserved392 */ + 0xDD, 0x90, /* ID_COORDS_CFG_SIZE */ + 0xDD, 0x94, /* LRG_OBJ_CFG */ + 0xDD, 0x95, /* MAX_FAT_FINGER_SIZE */ + 0xDD, 0x96, /* MIN_FAT_FINGER_SIZE */ + 0xDD, 0x97, /* FINGER_THRESH_MUTUAL */ + 0xDD, 0x98, /* FINGER_THRESH_SELF */ + 0xDD, 0x9A, /* INNER_EDGE_GAIN */ + 0xDD, 0x9B, /* OUTER_EDGE_GAIN */ + 0xDD, 0x9C, /* X_RESOLUTION */ + 0xDD, 0xA0, /* Y_RESOLUTION */ + 0xDD, 0xA4, /* SENSOR_ASSIGNMENT */ + 0xDD, 0xA8, /* Z_SCALING */ + 0xDD, 0xAC, /* RX_LINE_FILTER */ + 0xDD, 0xAD, /* BYPASS_THRESHOLD_GAIN */ + 0xDD, 0xAE, /* BYPASS_THRESHOLD_EDGE_GAIN */ + 0xDD, 0xAF, /* FINGER_THR_MUT_HYST */ + 0xDD, 0xB0, /* MAX_FAT_FINGER_SIZE_HYST */ + 0xDD, 0xB1, /* MIN_FAT_FINGER_SIZE_HYST */ + 0xDD, 0xB2, /* MULTI_TOUCH_DEBOUNCE */ + 0xDD, 0xB3, /* CA_FINGER_THRESHOLD_MUTUAL */ + 0xDD, 0xB4, /* FAT_FINGER_THRESHOLD_COEFF */ + 0xDD, 0xB5, /* SIZE_ORIENTATION_ENABLE */ + 0xDD, 0xB6, /* MAJOR_AXIS_OFFSET */ + 0xDD, 0xB7, /* MAJOR_AXIS_SCALE */ + 0xDD, 0xB8, /* MINOR_AXIS_OFFSET */ + 0xDD, 0xB9, /* MINOR_AXIS_SCALE */ + 0xDD, 0xBA, /* RX_LINE_FILTER_DEBOUNCE */ + 0xDD, 0xBB, /* CLIPPING_X_LOW */ + 0xDD, 0xBC, /* CLIPPING_X_HIGH */ + 0xDD, 0xBD, /* CLIPPING_Y_LOW */ + 0xDD, 0xBE, /* CLIPPING_Y_HIGH */ + 0xDD, 0xBF, /* COEF_EDGE_ATTRACTION */ + 0xDD, 0xC0, /* WIDTH_CORNER_DIAG1 */ + 0xDD, 0xC2, /* WIDTH_CORNER_DIAG2 */ + 0xDD, 0xC4, /* WIDTH_CORNER_DIAG3 */ + 0xDD, 0xC6, /* WIDTH_CORNER_DIAG4 */ + 0xDD, 0xC8, /* WIDTH_CORNER_DIAG5 */ + 0xDD, 0xCA, /* WIDTH_CORNER_DIAG6 */ + 0xDD, 0xCC, /* WIDTH_CORNER_DIAG7 */ + 0xDD, 0xCE, /* WIDTH_CORNER_DIAG8 */ + 0xDD, 0xD0, /* WIDTH_CORNER_DIAG9 */ + 0xDD, 0xD2, /* WIDTH_CORNER_DIAG10 */ + 0xDD, 0xD4, /* WIDTH_CORNER_DIAG11 */ + 0xDD, 0xD6, /* WIDTH_CORNER_PERP1 */ + 0xDD, 0xD8, /* WIDTH_CORNER_PERP2 */ + 0xDD, 0xDA, /* WIDTH_CORNER_PERP3 */ + 0xDD, 0xDC, /* WIDTH_CORNER_PERP4 */ + 0xDD, 0xDE, /* RX_LINE_FILTER_THRESHOLD */ + 0xDD, 0xDF, /* NOISE_REJECTION_3x3_FILTER_SCALE */ + 0xDD, 0xE0, /* NOISE_REJECTION_3x3_FILTER_SCALE_CA */ + 0xDD, 0xE1, /* DIRECT_XY_ENABLE */ + 0xDD, 0xE2, /* Reserved482 */ + 0xDD, 0xE4, /* BTN_CFG_SIZE */ + 0xDD, 0xE8, /* BTN_THRSH_MUT_0 */ + 0xDD, 0xEA, /* BTN_THRSH_MUT_1 */ + 0xDD, 0xEC, /* BTN_THRSH_MUT_2 */ + 0xDD, 0xEE, /* BTN_THRSH_MUT_3 */ + 0xDD, 0xF0, /* BTN_HYST_MUT */ + 0xDD, 0xF1, /* Reserved497 */ + 0xDD, 0xF2, /* Reserved498 */ + 0xDD, 0xF3, /* Reserved499 */ + 0xDD, 0xF4, /* BTN_THRSH_SELF */ + 0xDD, 0xF6, /* BTN_THRSH_SELF_1 */ + 0xDD, 0xF8, /* BTN_THRSH_SELF_2 */ + 0xDD, 0xFA, /* BTN_THRSH_SELF_3 */ + 0xDD, 0xFC, /* BTN_HYST_SELF */ + 0xDD, 0xFD, /* Reserved509 */ + 0xDD, 0xFE, /* Reserved510 */ + 0xDD, 0xFF, /* Reserved511 */ + 0xDE, 0x00, /* RAW_PROC_CFG_SIZE */ + 0xDE, 0x04, /* RAW_FILTER_MASK */ + 0xDE, 0x06, /* RAW_FILT_IIR_COEFF_MUTUAL */ + 0xDE, 0x07, /* RAW_FILT_IIR_THRESHOLD_MUTUAL */ + 0xDE, 0x08, /* RAW_FILT_IIR_COEFF_SELF */ + 0xDE, 0x09, /* RAW_FILT_IIR_THRESHOLD_SELF */ + 0xDE, 0x0A, /* RAW_FILT_IIR_COEFF_BALANCED */ + 0xDE, 0x0B, /* RAW_FILT_IIR_THRESHOLD_BALANCED */ + 0xDE, 0x0C, /* RAW_FILT_IIR_COEFF_BUTTONS */ + 0xDE, 0x0D, /* RAW_FILT_IIR_THRESHOLD_BUTTONS */ + 0xDE, 0x0E, /* Reserved526 */ + 0xDE, 0x10, /* RAW_FILTER_MASK_CA */ + 0xDE, 0x12, /* RAW_FILT_IIR_COEFF_MUTUAL_CA */ + 0xDE, 0x13, /* RAW_FILT_IIR_THRESHOLD_MUTUAL_CA */ + 0xDE, 0x14, /* RAW_FILT_IIR_COEFF_SELF_CA */ + 0xDE, 0x15, /* RAW_FILT_IIR_THRESHOLD_SELF_CA */ + 0xDE, 0x16, /* RAW_FILT_IIR_COEFF_BALANCED_CA */ + 0xDE, 0x17, /* RAW_FILT_IIR_THRESHOLD_BALANCED_CA */ + 0xDE, 0x18, /* RAW_FILT_IIR_COEFF_BUTTONS_CA */ + 0xDE, 0x19, /* RAW_FILT_IIR_THRESHOLD_BUTTONS_CA */ + 0xDE, 0x1A, /* Reserved538 */ + 0xDE, 0x1C, /* Reserved540 */ + 0xDE, 0x28, /* BL_DELAY_MUT */ + 0xDE, 0x29, /* BL_DELAY_SELF */ + 0xDE, 0x2A, /* BL_DELAY_BAL */ + 0xDE, 0x2B, /* BL_DELAY_BTN */ + 0xDE, 0x2C, /* BL_THR_MUT */ + 0xDE, 0x2D, /* BL_THR_SELF */ + 0xDE, 0x2E, /* BL_THR_BAL */ + 0xDE, 0x2F, /* BL_THR_BTN_MUT */ + 0xDE, 0x30, /* BL_THR_BTN_SELF */ + 0xDE, 0x31, /* BL_MUT_SIG_THRESHOLD_CA */ + 0xDE, 0x32, /* BL_FILT_MUT */ + 0xDE, 0x33, /* BL_FILT_SELF */ + 0xDE, 0x34, /* BL_FILT_BAL */ + 0xDE, 0x35, /* BL_FILT_BTN_MUT */ + 0xDE, 0x36, /* BL_FILT_BTN_SELF */ + 0xDE, 0x37, /* CMF_THR_MUT */ + 0xDE, 0x38, /* CMF_THR_SELF */ + 0xDE, 0x39, /* CMF_THR_BAL */ + 0xDE, 0x3A, /* CMF_THR_BTN_MUT */ + 0xDE, 0x3B, /* CMF_THR_BTN_SELF */ + 0xDE, 0x3C, /* Reserved572 */ + 0xDE, 0x40, /* H2OREJECTION_SIZE */ + 0xDE, 0x44, /* BL_H20_RJCT */ + 0xDE, 0x45, /* BL_H20_SNS_WIDTH */ + 0xDE, 0x46, /* Reserved582 */ + 0xDE, 0x48, /* CDC_CFG_SIZE */ + 0xDE, 0x4C, /* TSS_CONTROL_MUT */ + 0xDE, 0x50, /* TSS_LENGTH_MUT */ + 0xDE, 0x54, /* TSS_TX_CONFIG_MUT */ + 0xDE, 0x58, /* TSS_TX_CONTROL_MUT */ + 0xDE, 0x5C, /* TSS_SEQ_CONFIG1_MUT */ + 0xDE, 0x60, /* TSS_SEQ_CONFIG2_MUT */ + 0xDE, 0x64, /* TSS_SEQ_CONFIG3_MUT */ + 0xDE, 0x68, /* TSS_SEQ_CONFIG4_MUT */ + 0xDE, 0x6C, /* TSS_SEQ_CONFIG5_MUT */ + 0xDE, 0x70, /* TSS_SEQ_CONFIG6_MUT */ + 0xDE, 0x74, /* TSS_SEQ_CONFIG7_MUT */ + 0xDE, 0x78, /* TSS_SEQ_CONFIG8_MUT */ + 0xDE, 0x7C, /* TSS_EXT_CONFIG1_MUT */ + 0xDE, 0x80, /* TSS_EXT_CONFIG2_MUT */ + 0xDE, 0x84, /* TSS_EXT_INTERVAL_MUT */ + 0xDE, 0x88, /* TSS_INT_CONFIG1_MUT */ + 0xDE, 0x8C, /* TSS_INT_CONFIG2_MUT */ + 0xDE, 0x90, /* TSS_INT_INTERVAL_MUT */ + 0xDE, 0x94, /* TSS_MCS_CONFIG_MUT */ + 0xDE, 0x98, /* TSS_RX_CONFIG_MUT */ + 0xDE, 0x9C, /* Reserved668 */ + 0xDE, 0xA0, /* TSS_CONTROL_SELF */ + 0xDE, 0xA4, /* TSS_LENGTH_SELF */ + 0xDE, 0xA8, /* TSS_TX_CONFIG_SELF */ + 0xDE, 0xAC, /* TSS_TX_CONTROL_SELF */ + 0xDE, 0xB0, /* TSS_SEQ_CONFIG1_SELF */ + 0xDE, 0xB4, /* TSS_SEQ_CONFIG2_SELF */ + 0xDE, 0xB8, /* TSS_SEQ_CONFIG3_SELF */ + 0xDE, 0xBC, /* TSS_SEQ_CONFIG4_SELF */ + 0xDE, 0xC0, /* TSS_SEQ_CONFIG5_SELF */ + 0xDE, 0xC4, /* TSS_SEQ_CONFIG6_SELF */ + 0xDE, 0xC8, /* TSS_SEQ_CONFIG7_SELF */ + 0xDE, 0xCC, /* TSS_SEQ_CONFIG8_SELF */ + 0xDE, 0xD0, /* TSS_EXT_CONFIG1_SELF */ + 0xDE, 0xD4, /* TSS_EXT_CONFIG2_SELF */ + 0xDE, 0xD8, /* TSS_EXT_INTERVAL_SELF */ + 0xDE, 0xDC, /* TSS_INT_CONFIG1_SELF */ + 0xDE, 0xE0, /* TSS_INT_CONFIG2_SELF */ + 0xDE, 0xE4, /* TSS_INT_INTERVAL_SELF */ + 0xDE, 0xE8, /* TSS_MCS_CONFIG_SELF */ + 0xDE, 0xEC, /* TSS_RX_CONFIG_SELF */ + 0xDE, 0xF0, /* Reserved752 */ + 0xDE, 0xF4, /* TSS_CONTROL_BAL */ + 0xDE, 0xF8, /* TSS_LENGTH_BAL */ + 0xDE, 0xFC, /* TSS_TX_CONFIG_BAL */ + 0xDF, 0x00, /* TSS_TX_CONTROL_BAL */ + 0xDF, 0x04, /* TSS_SEQ_CONFIG1_BAL */ + 0xDF, 0x08, /* TSS_SEQ_CONFIG2_BAL */ + 0xDF, 0x0C, /* TSS_SEQ_CONFIG3_BAL */ + 0xDF, 0x10, /* TSS_SEQ_CONFIG4_BAL */ + 0xDF, 0x14, /* TSS_SEQ_CONFIG5_BAL */ + 0xDF, 0x18, /* TSS_SEQ_CONFIG6_BAL */ + 0xDF, 0x1C, /* TSS_SEQ_CONFIG7_BAL */ + 0xDF, 0x20, /* TSS_SEQ_CONFIG8_BAL */ + 0xDF, 0x24, /* TSS_EXT_CONFIG1_BAL */ + 0xDF, 0x28, /* TSS_EXT_CONFIG2_BAL */ + 0xDF, 0x2C, /* TSS_EXT_INTERVAL_BAL */ + 0xDF, 0x30, /* TSS_INT_CONFIG1_BAL */ + 0xDF, 0x34, /* TSS_INT_CONFIG2_BAL */ + 0xDF, 0x38, /* TSS_INT_INTERVAL_BAL */ + 0xDF, 0x3C, /* TSS_MCS_CONFIG_BAL */ + 0xDF, 0x40, /* TSS_RX_CONFIG_BAL */ + 0xDF, 0x44, /* TSS_CONTROL_BTN */ + 0xDF, 0x48, /* TSS_LENGTH_BTN_MUT */ + 0xDF, 0x4C, /* TSS_TX_CONFIG_BTN */ + 0xDF, 0x50, /* TSS_TX_CONTROL_BTN */ + 0xDF, 0x54, /* TSS_SEQ_CONFIG1_BTN */ + 0xDF, 0x58, /* TSS_SEQ_CONFIG2_BTN */ + 0xDF, 0x5C, /* TSS_SEQ_CONFIG3_BTN */ + 0xDF, 0x60, /* TSS_SEQ_CONFIG4_BTN */ + 0xDF, 0x64, /* TSS_SEQ_CONFIG5_BTN */ + 0xDF, 0x68, /* TSS_SEQ_CONFIG6_BTN */ + 0xDF, 0x6C, /* TSS_SEQ_CONFIG7_BTN */ + 0xDF, 0x70, /* TSS_SEQ_CONFIG8_BTN */ + 0xDF, 0x74, /* TSS_EXT_CONFIG1_BTN */ + 0xDF, 0x78, /* TSS_EXT_CONFIG2_BTN */ + 0xDF, 0x7C, /* TSS_EXT_INTERVAL_BTN */ + 0xDF, 0x80, /* TSS_INT_CONFIG1_BTN */ + 0xDF, 0x84, /* TSS_INT_CONFIG2_BTN */ + 0xDF, 0x88, /* TSS_INT_INTERVAL_BTN */ + 0xDF, 0x8C, /* TSS_MCS_CONFIG_BTN */ + 0xDF, 0x90, /* TSS_RX_CONFIG_BTN */ + 0xDF, 0x94, /* TSS_LENGTH_BTN_SELF */ + 0xDF, 0x98, /* TSS_RX_VREF */ + 0xDF, 0x9C, /* TSS_RX_LX_CONFIG */ + 0xDF, 0xA0, /* TX_NUM */ + 0xDF, 0xA4, /* RX_NUM */ + 0xDF, 0xA8, /* SENS_NUM */ + 0xDF, 0xAC, /* CROSS_NUM */ + 0xDF, 0xB0, /* BUTTON_NUM */ + 0xDF, 0xB4, /* SLOTS_MUT */ + 0xDF, 0xB8, /* SLOTS_SELF_RX */ + 0xDF, 0xBC, /* SLOTS_SELF_TX */ + 0xDF, 0xC0, /* SLOTS_SELF */ + 0xDF, 0xC4, /* SLOTS_BAL */ + 0xDF, 0xC8, /* SCALE_MUT */ + 0xDF, 0xCC, /* SCALE_SELF */ + 0xDF, 0xD0, /* SCALE_BAL */ + 0xDF, 0xD4, /* SCALE_BUTTON */ + 0xDF, 0xD8, /* LX_MODE */ + 0xDF, 0xDC, /* LX_SCALE */ + 0xDF, 0xE0, /* ABSOLUTE_CR_CORRECTION_ENABLE */ + 0xDF, 0xE4, /* SCANNING_MODE_MUTUAL */ + 0xDF, 0xE8, /* SCANNING_MODE_BUTTON */ + 0xDF, 0xEC, /* DETECT_CHARGER_THRESHOLD */ + 0xDF, 0xEE, /* CA_LX_SCAN_MODE */ + 0xDF, 0xEF, /* SUB_SLOT_SCAN */ + 0xDF, 0xF0, /* NOISE_METRIC1_THRESHOLD */ + 0xDF, 0xF1, /* NOISE_METRIC2_THRESHOLD */ + 0xDF, 0xF2, /* NOISE_METRIC3_THRESHOLD */ + 0xDF, 0xF3, /* AFH_DYNAMIC_THRSH_ENABLE */ + 0xDF, 0xF4, /* ADC_CONFIG */ + 0xDF, 0xF5, /* Reserved1013 */ + 0xDF, 0xF6, /* TSS_LDO_PROG */ + 0xDF, 0xF7, /* TX_PERIOD_DUMMY_SCAN */ + 0xDF, 0xF8, /* SINGLE_ENDED_LISTEN_SCAN */ + 0xDF, 0xF9, /* SPREAD_MTX */ + 0xDF, 0xFA, /* Reserved1018 */ + 0xE0, 0x54, /* CALIBRATION_PARAM_SIZE */ + 0xE0, 0x58, /* Reserved1112 */ + 0xE0, 0x5C, /* Reserved1116 */ + 0xE0, 0x60, /* Reserved1120 */ + 0xE0, 0x64, /* Reserved1124 */ + 0xE0, 0x68, /* GLOBAL_IDAC_LSB_MUTUAL */ + 0xE0, 0x6C, /* GLOBAL_IDAC_LSB_SELF */ + 0xE0, 0x70, /* GLOBAL_IDAC_LSB_BALANCED */ + 0xE0, 0x74, /* GLOBAL_IDAC_LSB_BUTTON */ + 0xE0, 0x78, /* TARGET_LEVEL_MUTUAL */ + 0xE0, 0x7C, /* TARGET_LEVEL_SELF */ + 0xE0, 0x80, /* TARGET_LEVEL_BALANCED */ + 0xE0, 0x84, /* TARGET_LEVEL_BUTTON */ + 0xE0, 0x88, /* GAIN_MUTUAL */ + 0xE0, 0x8C, /* GAIN_SELF */ + 0xE0, 0x90, /* GAIN_BALANCED */ + 0xE0, 0x94, /* GAIN_BTN_MUTUAL */ + 0xE0, 0x98, /* GAIN_BTN_SELF */ + 0xE0, 0x9C, /* Reserved1180 */ + 0xE0, 0xA0, /* SPREADER_CFG_SIZE */ + 0xE0, 0xA4, /* CLK_IMO_SPREAD */ + 0xE0, 0xA8, /* Reserved1192 */ + 0xE0, 0xC0, /* CDC_PIN_INDEX_TABLE */ + 0xE1, 0x01, /* Reserved1281 */ + 0xE1, 0x04, /* CDC_BALANCED_LX_TABLE */ + 0xE1, 0x12, /* Reserved1298 */ + 0xE1, 0x18, /* CDC_BALANCED_TX_PATTERNS */ + 0xE1, 0x2A, /* Reserved1322 */ + 0xE1, 0x2C, /* CDC_SLOT_TABLE */ + 0xE1, 0xDC, /* Reserved1500 */ + 0xE1, 0xFC, /* CONFIG_CRC */ +};
+
diff --git a/arch/arm/mach-exynos/dev-spi.c b/arch/arm/mach-exynos/dev-spi.c index 0807d3d..8ef032e 100644 --- a/arch/arm/mach-exynos/dev-spi.c +++ b/arch/arm/mach-exynos/dev-spi.c @@ -96,6 +96,9 @@ static int exynos_spi_cfg_gpio(struct platform_device *pdev) case 0: s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_cfgpin(EXYNOS4_GPB(2), S3C_GPIO_SFN(2)); +#ifdef CONFIG_SEC_MODEM_P8LTE + s3c_gpio_cfgpin(EXYNOS4_GPB(1), S3C_GPIO_SFN(2)); +#endif s3c_gpio_cfgpin(EXYNOS4_GPB(3), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); s3c_gpio_setpull(EXYNOS4_GPB(2), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-exynos/dispfreq_opp_exynos4.c b/arch/arm/mach-exynos/dispfreq_opp_exynos4.c new file mode 100644 index 0000000..fafdd62 --- /dev/null +++ b/arch/arm/mach-exynos/dispfreq_opp_exynos4.c @@ -0,0 +1,609 @@ +/* linux/arch/arm/mach-exynos/dispfreq_opp_exynos4.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4 - Display frequency scaling support with OPP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* This feature was derived from exynos4 display of devfreq + * which was made by Mr Myungjoo Ham. + */ + +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/opp.h> +#include <linux/mutex.h> +#include <linux/suspend.h> +#include <linux/notifier.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/pm_qos_params.h> +#include <linux/devfreq/exynos4_display.h> + + +#include <linux/list.h> +#include <linux/pm_qos_params.h> +#include <mach/cpufreq.h> +#include <mach/dev.h> +#include <linux/device.h> + +#define DEVFREQ_OPTION_FREQ_LUB 0x0 +#define DEVFREQ_OPTION_FREQ_GLB 0x1 + +#define EXYNOS4_DISPLAY_ON 1 +#define EXYNOS4_DISPLAY_OFF 0 + +#define DEFAULT_DELAY_TIME 1000 /* us (millisecond) */ + +enum exynos_display_type { + TYPE_DISPLAY_EXYNOS4210, + TYPE_DISPLAY_EXYNOS4x12, +}; + +/* Define opp table which include various frequency level */ +struct exynos4_dispfreq_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +struct exynos4_dispfreq_pm_qos_table { + unsigned long freq; /* 0 if this is the last element */ + s32 qos_value; +}; + +struct exynos4_dispfreq_data { + struct device *dev; + struct opp *curr_opp; + struct delayed_work wq_lowfreq; + struct notifier_block nb; + struct notifier_block nb_pm; + struct notifier_block nb_qos; + + unsigned long initial_freq; + int qos_type; + struct exynos4_dispfreq_pm_qos_table *qos_list; + + unsigned long previous_freq; + unsigned long min_freq; + unsigned long max_freq; + unsigned long qos_min_freq; + + enum exynos_display_type type; + unsigned int state; + struct mutex lock; +}; + +/* Define frequency level */ +enum exynos4_dispfreq_clk_level_idx { + LV_0 = 0, + LV_1, + _LV_END +}; + +static struct exynos4_dispfreq_opp_table exynos_dispfreq_clk_table[] = { + {LV_0, 40, 0 }, + {LV_1, 60, 0 }, + {0, 0, 0 }, +}; + +static struct pm_qos_request_list qos_wrapper[DVFS_LOCK_ID_END]; + +/* Wrappers for obsolete legacy kernel hack (busfreq_lock/lock_free) */ +int exynos4_busfreq_lock(unsigned int nId, enum busfreq_level_request lvl) +{ + s32 qos_value; + + if (WARN(nId >= DVFS_LOCK_ID_END, "incorrect nId.")) + return -EINVAL; + if (WARN(lvl >= BUS_LEVEL_END, "incorrect level.")) + return -EINVAL; + + switch (lvl) { + case BUS_L0: + qos_value = 400000; + break; + case BUS_L1: + qos_value = 267000; + break; + case BUS_L2: + qos_value = 133000; + break; + default: + qos_value = 0; + } + + if (qos_wrapper[nId].pm_qos_class == 0) { + pm_qos_add_request(&qos_wrapper[nId], + PM_QOS_BUS_QOS, qos_value); + } else { + pm_qos_update_request(&qos_wrapper[nId], qos_value); + } + + return 0; +} + +void exynos4_busfreq_lock_free(unsigned int nId) +{ + if (WARN(nId >= DVFS_LOCK_ID_END, "incorrect nId.")) + return; + + if (qos_wrapper[nId].pm_qos_class) + pm_qos_update_request(&qos_wrapper[nId], + PM_QOS_BUS_DMA_THROUGHPUT_DEFAULT_VALUE); +} + +/* + * The exynos-display driver send newly frequency to display client + * if it receive event from sender device. + * List of display client device + * - FIMD and so on + */ +static BLOCKING_NOTIFIER_HEAD(exynos4_display_notifier_client_list); + + +int exynos4_display_register_client(struct notifier_block *nb) +{ + return blocking_notifier_chain_register( + &exynos4_display_notifier_client_list, nb); +} +EXPORT_SYMBOL(exynos4_display_register_client); + +int exynos4_display_unregister_client(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister( + &exynos4_display_notifier_client_list, nb); +} +EXPORT_SYMBOL(exynos4_display_unregister_client); + +static int devfreq_powersave_func(struct exynos4_dispfreq_data *data, + unsigned long *freq) +{ + *freq = data->min_freq; + return 0; +} + + +static int exynos4_dispfreq_profile_target(struct device *dev, + unsigned long *_freq, u32 options); + +/** + * update_devfreq() - Reevaluate the device and configure frequency. + * @devfreq: the devfreq instance. + * + * Note: Lock devfreq->lock before calling update_devfreq + * This function is exported for governors. + */ +static int exynos4_dispfreq_update(struct exynos4_dispfreq_data *data) +{ + unsigned long freq; + int err = 0; + u32 options = 0; + + if (!mutex_is_locked(&data->lock)) { + WARN(true, "devfreq->lock must be locked by the caller.\n"); + return -EINVAL; + } + + /* Reevaluate the proper frequency */ + err = devfreq_powersave_func(data, &freq); + if (err) + return err; + + /* + * Adjust the freuqency with user freq and QoS. + * + * List from the highest proiority + * min_freq + * max_freq + * qos_min_freq + */ + + if (data->qos_min_freq && freq < data->qos_min_freq) { + freq = data->qos_min_freq; + options &= ~(1 << 0); + options |= DEVFREQ_OPTION_FREQ_LUB; + } + if (data->max_freq && freq > data->max_freq) { + freq = data->max_freq; + options &= ~(1 << 0); + options |= DEVFREQ_OPTION_FREQ_GLB; + } + if (data->min_freq && freq < data->min_freq) { + freq = data->min_freq; + options &= ~(1 << 0); + options |= DEVFREQ_OPTION_FREQ_LUB; + } + + err = exynos4_dispfreq_profile_target(data->dev, &freq, options); + if (err) + return err; + + data->previous_freq = freq; + return err; +} + +static int exynos4_dispfreq_send_event_to_display(unsigned long val, void *v) +{ + return blocking_notifier_call_chain( + &exynos4_display_notifier_client_list, val, v); +} + +static int exynos4_dispfreq_opp_notifier_call(struct notifier_block *nb, + unsigned long val, void *devp) +{ + struct exynos4_dispfreq_data *data = container_of(nb, + struct exynos4_dispfreq_data, nb); + int ret; + + mutex_lock(&data->lock); + ret = exynos4_dispfreq_update(data); + mutex_unlock(&data->lock); + + return ret; +} + +struct opp *devfreq_recommended_opp(struct device *dev, unsigned long *freq, + bool floor) +{ + struct opp *opp; + + if (floor) { + opp = opp_find_freq_floor(dev, freq); + + if (opp == ERR_PTR(-ENODEV)) + opp = opp_find_freq_ceil(dev, freq); + } else { + opp = opp_find_freq_ceil(dev, freq); + + if (opp == ERR_PTR(-ENODEV)) + opp = opp_find_freq_floor(dev, freq); + } + + return opp; +} + + +static int exynos4_dispfreq_profile_target(struct device *dev, + unsigned long *_freq, u32 options) +{ + /* Inform display client of new frequency */ + struct exynos4_dispfreq_data *data = dev_get_drvdata(dev); + struct opp *opp = devfreq_recommended_opp(dev, _freq, options & + DEVFREQ_OPTION_FREQ_GLB); + unsigned long old_freq = opp_get_freq(data->curr_opp); + unsigned long new_freq = opp_get_freq(opp); + + /* TODO: No longer use fb notifier to identify LCD on/off state and + have yet alternative feature of it. So, exynos4-display change + refresh rate of display clinet irrespective of LCD state until + proper feature will be implemented. */ + if (old_freq == new_freq) + return 0; + + opp = opp_find_freq_floor(dev, &new_freq); + data->curr_opp = opp; + + switch (new_freq) { + case EXYNOS4_DISPLAY_LV_HF: + if (delayed_work_pending(&data->wq_lowfreq)) + cancel_delayed_work(&data->wq_lowfreq); + + exynos4_dispfreq_send_event_to_display( + EXYNOS4_DISPLAY_LV_HF, NULL); + break; + case EXYNOS4_DISPLAY_LV_LF: + schedule_delayed_work(&data->wq_lowfreq, + msecs_to_jiffies(DEFAULT_DELAY_TIME)); + break; + } + + return 0; +} + +static int exynos4_dispfreq_qos_notifier_call(struct notifier_block *nb, + unsigned long value, void *devp) +{ + struct exynos4_dispfreq_data *data = container_of(nb, + struct exynos4_dispfreq_data, nb_qos); + int ret; + int i; + unsigned long default_value = 0; + struct exynos4_dispfreq_pm_qos_table *qos_list = data->qos_list; + bool qos_use_max = true; + + if (!qos_list) + return NOTIFY_DONE; + + mutex_lock(&data->lock); + + switch (data->qos_type) { + case PM_QOS_CPU_DMA_LATENCY: + default_value = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; + break; + case PM_QOS_NETWORK_LATENCY: + default_value = PM_QOS_NETWORK_LAT_DEFAULT_VALUE; + break; + case PM_QOS_NETWORK_THROUGHPUT: + default_value = PM_QOS_NETWORK_THROUGHPUT_DEFAULT_VALUE; + break; + case PM_QOS_BUS_DMA_THROUGHPUT: + default_value = PM_QOS_BUS_DMA_THROUGHPUT_DEFAULT_VALUE; + break; + case PM_QOS_DISPLAY_FREQUENCY: + default_value = PM_QOS_DISPLAY_FREQUENCY_DEFAULT_VALUE; + break; + default: + /* Won't do any check to detect "default" state */ + break; + } + + if (value == default_value) { + data->qos_min_freq = 0; + goto update; + } + + for (i = 0; qos_list[i].freq; i++) { + /* QoS Met */ + if ((qos_use_max && qos_list[i].qos_value >= value) || + (!qos_use_max && qos_list[i].qos_value <= value)) { + data->qos_min_freq = qos_list[i].freq; + goto update; + } + } + + /* Use the highest QoS freq */ + if (i > 0) + data->qos_min_freq = qos_list[i - 1].freq; + +update: + ret = exynos4_dispfreq_update(data); + mutex_unlock(&data->lock); + return ret; +} + +/* + * Register exynos-display as client to pm notifer + * - This callback gets called when something important happens in pm state. + */ +static int exynos4_dispfreq_pm_notifier_callback(struct notifier_block *this, + unsigned long event, void *_data) +{ + struct exynos4_dispfreq_data *data = container_of(this, + struct exynos4_dispfreq_data, nb_pm); + + if (data->state == EXYNOS4_DISPLAY_OFF) + return NOTIFY_OK; + + switch (event) { + case PM_SUSPEND_PREPARE: + mutex_lock(&data->lock); + data->state = EXYNOS4_DISPLAY_OFF; + mutex_unlock(&data->lock); + + if (delayed_work_pending(&data->wq_lowfreq)) + cancel_delayed_work(&data->wq_lowfreq); + + return NOTIFY_OK; + + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + mutex_lock(&data->lock); + data->state = EXYNOS4_DISPLAY_ON; + mutex_unlock(&data->lock); + + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +/* + * Enable/disable exynos-display operation + */ +static void exynos4_dispfreq_disable(struct exynos4_dispfreq_data *data) +{ + struct opp *opp; + unsigned long freq = EXYNOS4_DISPLAY_LV_DEFAULT; + + /* Cancel workqueue which set low frequency of display client + * if it is pending state before executing workqueue. */ + if (delayed_work_pending(&data->wq_lowfreq)) + cancel_delayed_work(&data->wq_lowfreq); + + /* Set high frequency(default) of display client */ + exynos4_dispfreq_send_event_to_display(freq, NULL); + + mutex_lock(&data->lock); + data->state = EXYNOS4_DISPLAY_OFF; + mutex_unlock(&data->lock); + + /* Find opp object with high frequency */ + opp = opp_find_freq_floor(data->dev, &freq); + if (IS_ERR(opp)) { + dev_err(data->dev, + "invalid initial frequency %lu kHz.\n", freq); + } else + data->curr_opp = opp; +} + +static void exynos4_display_enable(struct exynos4_dispfreq_data *data) +{ + data->state = EXYNOS4_DISPLAY_ON; +} + +/* + * Timer to set display with low frequency state after 1 second + */ +static void exynos4_dispfreq_set_lowfreq(struct work_struct *work) +{ + exynos4_dispfreq_send_event_to_display(EXYNOS4_DISPLAY_LV_LF, NULL); +} + +static __devinit int exynos4_dispfreq_probe(struct platform_device *pdev) +{ + struct exynos4_dispfreq_data *data; + struct device *dev = &pdev->dev; + struct opp *opp; + int ret = 0; + int i; + struct exynos4_dispfreq_pm_qos_table *qos_list; + struct srcu_notifier_head *nh; + + data = kzalloc(sizeof(struct exynos4_dispfreq_data), GFP_KERNEL); + if (!data) { + dev_err(dev, "cannot allocate memory.\n"); + return -ENOMEM; + } + data->dev = dev; + data->state = EXYNOS4_DISPLAY_ON; + data->initial_freq = EXYNOS4_DISPLAY_LV_DEFAULT; + mutex_init(&data->lock); + + /* Register OPP entries */ + for (i = 0 ; i < _LV_END ; i++) { + ret = opp_add(dev, exynos_dispfreq_clk_table[i].clk, + exynos_dispfreq_clk_table[i].volt); + if (ret) { + dev_err(dev, "cannot add opp entries.\n"); + goto err_alloc_mem; + } + } + + + /* Find opp object with init frequency */ + opp = opp_find_freq_floor(dev, &data->initial_freq); + if (IS_ERR(opp)) { + dev_err(dev, "invalid initial frequency %lu kHz.\n", + data->initial_freq); + ret = PTR_ERR(opp); + goto err_alloc_mem; + } + data->curr_opp = opp; + + /* Initialize QoS */ + qos_list = kzalloc( + (sizeof(struct exynos4_dispfreq_pm_qos_table) * _LV_END), + GFP_KERNEL); + if (!data) { + dev_err(dev, "cannot allocate memory.\n"); + goto err_alloc_mem; + } + for (i = 0 ; i < _LV_END ; i++) { + qos_list[i].freq = exynos_dispfreq_clk_table[i].clk; + qos_list[i].qos_value = exynos_dispfreq_clk_table[i].clk; + } + + /* Register exynos4_display as client to opp notifier */ + memset(&data->nb, 0, sizeof(data->nb)); + data->nb.notifier_call = exynos4_dispfreq_opp_notifier_call; + nh = opp_get_notifier(dev); + ret = srcu_notifier_chain_register(nh, &data->nb); + if (ret < 0) { + dev_err(dev, "failed to get pm notifier: %d\n", ret); + goto err_reg_pm_opp; + } + + data->qos_type = PM_QOS_DISPLAY_FREQUENCY; + data->qos_list = qos_list; + + /* Register exynos4_display as client to pm qos notifier */ + memset(&data->nb_qos, 0, sizeof(data->nb_qos)); + data->nb_qos.notifier_call = exynos4_dispfreq_qos_notifier_call; + ret = pm_qos_add_notifier(data->qos_type, &data->nb_qos); + if (ret < 0) { + dev_err(dev, "failed to get pm notifier: %d\n", ret); + goto err_reg_pm_qos; + } + + /* Register exynos4_display as client to pm notifier */ + memset(&data->nb_pm, 0, sizeof(data->nb_pm)); + data->nb_pm.notifier_call = exynos4_dispfreq_pm_notifier_callback; + ret = register_pm_notifier(&data->nb_pm); + if (ret < 0) { + dev_err(dev, "failed to get pm notifier: %d\n", ret); + goto err_reg_pm; + } + + INIT_DELAYED_WORK(&data->wq_lowfreq, exynos4_dispfreq_set_lowfreq); + + platform_set_drvdata(pdev, data); + + return 0; + +err_reg_pm: + pm_qos_remove_notifier(data->qos_type, &data->nb_qos); + +err_reg_pm_qos: + srcu_notifier_chain_unregister(nh, &data->nb); + +err_reg_pm_opp: + kfree(data->qos_list); + +err_alloc_mem: + kfree(data); + + return ret; +} + +static __devexit int exynos4_dispfreq_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos4_dispfreq_data *data = pdev->dev.platform_data; + struct srcu_notifier_head *nh = opp_get_notifier(dev); + + unregister_pm_notifier(&data->nb_pm); + exynos4_dispfreq_disable(data); + + pm_qos_remove_notifier(data->qos_type, &data->nb_qos); + srcu_notifier_chain_unregister(nh, &data->nb); + + kfree(data->qos_list); + kfree(data); + + return 0; +} + +static int exynos4_dispfreq_suspend(struct device *dev) +{ + /* TODO */ + return 0; +} + +static int exynos4_dispfreq_resume(struct device *dev) +{ + /* TODO */ + return 0; +} + +static const struct dev_pm_ops exynos4_dispfreq_pm = { + .suspend = exynos4_dispfreq_suspend, + .resume = exynos4_dispfreq_resume, +}; + +static struct platform_driver exynos4_dispfreq_driver = { + .probe = exynos4_dispfreq_probe, + .remove = __devexit_p(exynos4_dispfreq_remove), + .driver = { + .name = "exynos4-dispfreq", + .owner = THIS_MODULE, + .pm = &exynos4_dispfreq_pm, + }, +}; + +static int __init exynos4_dispfreq_init(void) +{ + return platform_driver_register(&exynos4_dispfreq_driver); +} +late_initcall(exynos4_dispfreq_init); + +static void __exit exynos4_dispfreq_exit(void) +{ + platform_driver_unregister(&exynos4_dispfreq_driver); +} +module_exit(exynos4_dispfreq_exit); diff --git a/arch/arm/mach-exynos/exynos_sound_platform_data.c b/arch/arm/mach-exynos/exynos_sound_platform_data.c new file mode 100644 index 0000000..3353f41 --- /dev/null +++ b/arch/arm/mach-exynos/exynos_sound_platform_data.c @@ -0,0 +1,29 @@ +#include <linux/module.h> +#include <linux/err.h> +#include <linux/exynos_audio.h> + +static const struct exynos_sound_platform_data *platform_data; + +int __init exynos_sound_set_platform_data( + const struct exynos_sound_platform_data *data) +{ + if (platform_data) + return -EBUSY; + if (!data) + return -EINVAL; + + platform_data = kmemdup(data, sizeof(*data), GFP_KERNEL); + if (!platform_data) + return -ENOMEM; + + return 0; +} + +const struct exynos_sound_platform_data *exynos_sound_get_platform_data(void) +{ + if (!platform_data) + return ERR_PTR(-ENODEV); + + return platform_data; +} +EXPORT_SYMBOL(exynos_sound_get_platform_data); diff --git a/arch/arm/mach-exynos/gc1-gpio.c b/arch/arm/mach-exynos/gc1-gpio.c index 674d293..b758b7f 100644 --- a/arch/arm/mach-exynos/gc1-gpio.c +++ b/arch/arm/mach-exynos/gc1-gpio.c @@ -33,6 +33,8 @@ struct gpio_init_data { */ static struct gpio_init_data m0_init_gpios[] = { + {EXYNOS4_GPD0(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VIB */ {EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -43,6 +45,8 @@ static struct gpio_init_data m0_init_gpios[] = { {EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */ + {EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */ {EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -94,6 +98,10 @@ static struct gpio_init_data m0_init_gpios[] = { S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -110,6 +118,10 @@ static struct gpio_init_data m0_init_gpios[] = { {EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ {EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */ @@ -174,7 +186,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPD0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* VIB */ {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -184,13 +196,13 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -199,17 +211,22 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#ifdef CONFIG_SEC_MODEM_M0 + /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#else {EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, @@ -337,9 +354,11 @@ static unsigned int m0_sleep_gpio_table[][3] = { /* Exynos4212 specific gpio */ {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* EAR_MICBIAS_EN */ + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -377,7 +396,12 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#ifdef CONFIG_SEC_MODEM_M0 + /* GPM3(3) M0, CP_RESET_REQ hold high */ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_DOWN}, /* NC */ +#else {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -439,6 +463,7 @@ static unsigned int m0_sleep_gpio_table_rev01[][3] = { {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*GYRO_INT*/ {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*POWER_LED*/ {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*GYRO_DE*/ + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /*TOP_PCB_PWREN*/ {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*MOT_EN*/ {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*SAMBAZ*/ }; @@ -447,6 +472,7 @@ static unsigned int m0_sleep_gpio_table_rev01[][3] = { * GC1 Rev0.2 (HW MAIN REV0.0) GPIO Sleep Table */ static unsigned int m0_sleep_gpio_table_rev02[][3] = { + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/ {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/ {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /*NC*/ diff --git a/arch/arm/mach-exynos/gc1-jack.c b/arch/arm/mach-exynos/gc1-jack.c new file mode 100644 index 0000000..5ef129f --- /dev/null +++ b/arch/arm/mach-exynos/gc1-jack.c @@ -0,0 +1,133 @@ +/* arch/arm/mach-exynos/gc1-jack.c + * + * Copyright (C) 2012 Samsung Electronics Co, Ltd + * + * Based on mach-exynos/mach-midas.c + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/gpio-midas.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/sec_jack.h> +#include <mach/gc1-jack.h> + +static void sec_set_jack_micbias(bool on) +{ + if ((system_rev == 3) || (system_rev == 4) || (system_rev == 5)) + set_wm1811_micbias2(on); + else + gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on); +} + +/* FIXME: these values are for GD as hw rev 6 */ +static struct sec_jack_zone sec_jack_zones[] = { + { + /* adc == 0, unstable zone, default to 3pole if it stays + * in this range for 300ms (15ms delays, 20 samples) + */ + .adc_high = 0, + .delay_ms = 15, + .check_count = 20, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 0 < adc <= 1200, unstable zone, default to 3pole if it stays + * in this range for 300ms (15ms delays, 20 samples) + */ + .adc_high = 1200, + .delay_ms = 10, + .check_count = 80, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 1200 < adc <= 2100, unstable zone, default to 3pole if it + * stays in this range for 800ms (10ms delays, 80 samples) + */ + .adc_high = 2100, + .delay_ms = 10, + .check_count = 10, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 2100 < adc <= 4100, 4 pole zone, default to 4pole if it + * stays in this range for 100ms (10ms delays, 10 samples) + */ + .adc_high = 4100, + .delay_ms = 10, + .check_count = 15, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* adc > 4100, unstable zone, default to 3pole if it stays + * in this range for two seconds (10ms delays, 200 samples) + */ + .adc_high = 0x7fffffff, + .delay_ms = 10, + .check_count = 200, + .jack_type = SEC_HEADSET_3POLE, + }, +}; + +/* To support 3-buttons earjack */ +static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = { + { + /* 0 <= adc <=350, stable zone */ + .code = KEY_MEDIA, + .adc_low = 0, + .adc_high = 350, + }, + { + /* 351 <= adc <= 920, stable zone */ + .code = KEY_VOLUMEUP, + .adc_low = 351, + .adc_high = 920, + }, + { + /* 921 <= adc <= 1700, stable zone */ + .code = KEY_VOLUMEDOWN, + .adc_low = 921, + .adc_high = 1700, + }, +}; +/* END FIXME: these values is for GD as hw rev 6 */ + +static struct sec_jack_platform_data sec_jack_data = { + .set_micbias_state = sec_set_jack_micbias, + .zones = sec_jack_zones, + .num_zones = ARRAY_SIZE(sec_jack_zones), + .buttons_zones = sec_jack_buttons_zones, + .num_buttons_zones = ARRAY_SIZE(sec_jack_buttons_zones), + .det_gpio = GPIO_DET_35, + .send_end_gpio = GPIO_EAR_SEND_END, +}; + +static struct platform_device sec_device_jack = { + .name = "sec_jack", + .id = 1, /* will be used also for gpio_event id */ + .dev.platform_data = &sec_jack_data, +}; +void __init gc1_jack_init(void) +{ + + /* Ear Microphone BIAS */ + int err; + err = gpio_request(GPIO_EAR_MIC_BIAS_EN, "EAR MIC"); + if (err) { + pr_err(KERN_ERR "GPIO_EAR_MIC_BIAS_EN GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_EAR_MIC_BIAS_EN, 1); + gpio_set_value(GPIO_EAR_MIC_BIAS_EN, 0); + gpio_free(GPIO_EAR_MIC_BIAS_EN); + + platform_device_register(&sec_device_jack); +} diff --git a/arch/arm/mach-exynos/gc1-power.c b/arch/arm/mach-exynos/gc1-power.c index 175a579..65a822d 100644 --- a/arch/arm/mach-exynos/gc1-power.c +++ b/arch/arm/mach-exynos/gc1-power.c @@ -370,7 +370,11 @@ struct max77686_platform_data exynos4_max77686_info = { void midas_power_set_muic_pdata(void *pdata, int gpio) { - gpio_request(gpio, "AP_PMIC_IRQ"); + int err; + + err = gpio_request(gpio, "AP_PMIC_IRQ"); + if (err) + pr_warn("failed to request AP_PMIC_IRQ\n"); s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); } @@ -490,6 +494,10 @@ static struct regulator_consumer_supply s5m_ldo14_supply[] = { REGULATOR_SUPPLY("vabb2_1.95v", NULL), }; +static struct regulator_consumer_supply s5m_ldo19_supply[] = { + REGULATOR_SUPPLY("lcd_io_1.8v", NULL), +}; + static struct regulator_consumer_supply s5m_ldo20_supply[] = { REGULATOR_SUPPLY("touch", NULL), }; @@ -509,6 +517,7 @@ static struct regulator_consumer_supply s5m_ldo23_supply[] = { static struct regulator_consumer_supply s5m_ldo24_supply[] = { REGULATOR_SUPPLY("led_3.3v", NULL), + REGULATOR_SUPPLY("vmotor", NULL), }; static struct regulator_consumer_supply s5m_ldo25_supply[] = { @@ -586,6 +595,8 @@ S5M_REGULATOR_INIT(s5m_ldo12, "VUOTG_3.0V", 3000000, 3000000, 1, REGULATOR_CHANGE_STATUS, 0); S5M_REGULATOR_INIT(s5m_ldo14, "VABB2_1.95V", 1950000, 1950000, 1, REGULATOR_CHANGE_STATUS, 1); +S5M_REGULATOR_INIT(s5m_ldo19, "LCD_IO_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); S5M_REGULATOR_INIT(s5m_ldo20, "TSP_AVDD_3.3V", 3300000, 3300000, 0, REGULATOR_CHANGE_STATUS, 1); S5M_REGULATOR_INIT(s5m_ldo21, "MOT_3.3V", 3300000, 3300000, 0, @@ -594,7 +605,7 @@ S5M_REGULATOR_INIT(s5m_ldo22, "CAM_SENSOR_2.8V", 2800000, 2800000, 0, REGULATOR_CHANGE_STATUS, 1); S5M_REGULATOR_INIT(s5m_ldo23, "VTF_2.8V", 2800000, 2800000, 0, REGULATOR_CHANGE_STATUS, 1); -S5M_REGULATOR_INIT(s5m_ldo24, "LED_3.3V", 3300000, 3300000, 0, +S5M_REGULATOR_INIT(s5m_ldo24, "LED_3.3V", 3000000, 3000000, 0, REGULATOR_CHANGE_STATUS, 1); S5M_REGULATOR_INIT(s5m_ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, REGULATOR_CHANGE_STATUS, 1); @@ -701,6 +712,7 @@ static struct s5m_regulator_data s5m8767_regulators[] = { {S5M8767_LDO11, &s5m_ldo11_init_data,}, {S5M8767_LDO12, &s5m_ldo12_init_data,}, {S5M8767_LDO14, &s5m_ldo14_init_data,}, + {S5M8767_LDO19, &s5m_ldo19_init_data,}, {S5M8767_LDO20, &s5m_ldo20_init_data,}, {S5M8767_LDO21, &s5m_ldo21_init_data,}, {S5M8767_LDO22, &s5m_ldo22_init_data,}, @@ -723,6 +735,7 @@ struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = { [S5M8767_LDO11] = {S5M8767_LDO11, S5M_OPMODE_STANDBY}, [S5M8767_LDO12] = {S5M8767_LDO12, S5M_OPMODE_STANDBY}, [S5M8767_LDO14] = {S5M8767_LDO14, S5M_OPMODE_STANDBY}, + [S5M8767_LDO19] = {S5M8767_LDO19, S5M_OPMODE_STANDBY}, }; struct s5m_platform_data exynos4_s5m8767_info = { @@ -777,6 +790,7 @@ struct s5m_platform_data exynos4_s5m8767_info = { .buck_ds[1] = EXYNOS4_GPF3(2), .buck_ds[2] = EXYNOS4_GPF3(3), + .buck1_init = 1000000, .buck2_init = 1100000, .buck3_init = 1000000, .buck4_init = 1000000, diff --git a/arch/arm/mach-exynos/grande-jack.c b/arch/arm/mach-exynos/grande-jack.c new file mode 100644 index 0000000..99cb0fe --- /dev/null +++ b/arch/arm/mach-exynos/grande-jack.c @@ -0,0 +1,51 @@ +/* arch/arm/mach-exynos/grande-jack.c + * + * Copyright (C) 2012 Samsung Electronics Co, Ltd + * + * Based on mach-exynos/mach-grande.c + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mach/gpio-midas.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/sec_jack.h> + +static void sec_set_jack_micbias(bool on) +{ + gpio_set_value(GPIO_MIC_BIAS_EN, on); +} + +static struct sec_jack_platform_data sec_jack_data = { + .set_micbias_state = sec_set_jack_micbias, +}; + +static struct platform_device sec_device_jack = { + .name = "sec_jack", + .id = 1, /* will be used also for gpio_event id */ + .dev.platform_data = &sec_jack_data, +}; +void __init grande_jack_init(void) +{ + /* Ear Microphone BIAS */ + int err; + err = gpio_request(GPIO_MIC_BIAS_EN, "EAR MIC"); + if (err) { + pr_err(KERN_ERR "GPIO_MIC_BIAS_EN GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_MIC_BIAS_EN, 1); + gpio_set_value(GPIO_MIC_BIAS_EN, 0); + gpio_free(GPIO_MIC_BIAS_EN); + + platform_device_register(&sec_device_jack); +} + diff --git a/arch/arm/mach-exynos/gsd4t.c b/arch/arm/mach-exynos/gsd4t.c new file mode 100644 index 0000000..c30fa20 --- /dev/null +++ b/arch/arm/mach-exynos/gsd4t.c @@ -0,0 +1,299 @@ +/* + * gsd4t.c (SiRFstarIV) + * GPS driver for SiRFstar based chip. + * + * Copyright (C) 2011 Samsung Electronics + * Minho Ban <mhban@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/mutex.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/rfkill.h> +#include <linux/regulator/machine.h> +#include <asm/mach-types.h> +#include <mach/gpio.h> +#include <plat/gpio-cfg.h> + +#include <mach/gsd4t.h> + +struct gsd4t_data { + struct gsd4t_platform_data *pdata; + struct rfkill *rfk; + bool in_use; + /* No need below if constraints is always_on */ + struct regulator *vdd_18; + struct regulator *rtc_xi; +}; + +static int gsd4t_set_block(void *data, bool blocked) +{ + struct gsd4t_data *bd = data; + struct gsd4t_platform_data *pdata = bd->pdata; + + if (!blocked) { + if (bd->in_use) + return 0; + + pr_info("gsd4t on\n"); + + regulator_enable(bd->vdd_18); + regulator_enable(bd->rtc_xi); + + /* + * CSR(SiRF) recommends, + * + * _|^^^|_100ms_|^^^^^^^^^^^^^^^ nrst + * _____________,___200ms___|^^^ onoff + * + */ + + gpio_set_value(pdata->nrst, 1); + gpio_set_value(pdata->onoff, 0); + /* + * But real boot sequence should be handled by user layer + * (including download firmware) so we don't need control pins + * here actually. + * + msleep(50); + gpio_set_value(pdata->nrst, 0); + msleep(100); + gpio_set_value(pdata->nrst, 1); + msleep(200); + gpio_set_value(pdata->onoff, 1); + */ + + bd->in_use = true; + } else { + if (!bd->in_use) + return 0; + + pr_info("gsd4t off\n"); + + gpio_set_value(pdata->nrst, 0); + + regulator_disable(bd->vdd_18); + regulator_disable(bd->rtc_xi); + + bd->in_use = false; + } + return 0; +} + +static const struct rfkill_ops gsd4t_rfkill_ops = { + .set_block = gsd4t_set_block, +}; + +static int __devinit gsd4t_probe(struct platform_device *dev) +{ + struct gsd4t_platform_data *pdata; + struct gsd4t_data *bd; + unsigned int gpio; + int ret = 0; + + pdata = dev->dev.platform_data; + if (!pdata) { + dev_err(&dev->dev, "No platform data.\n"); + return -EINVAL; + } + + bd = kzalloc(sizeof(struct gsd4t_data), GFP_KERNEL); + if (!bd) + return -ENOMEM; + + bd->pdata = pdata; + + if (gpio_is_valid(pdata->nrst)) { + gpio = pdata->nrst; + /* GPS_nRST is high */ + gpio_request(gpio, "GPS_nRST"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_direction_output(gpio, 0); + + gpio_export(gpio, 1); + gpio_export_link(&dev->dev, "reset", gpio); + } else { + dev_err(&dev->dev, "Invalid nRST pin\n"); + ret = -EINVAL; + goto err_invalid_pin1; + } + + + if (gpio_is_valid(pdata->onoff)) { + gpio = pdata->onoff; + /* GPS_EN is low */ + gpio_request(gpio, "GPS_EN"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_direction_output(gpio, 0); + + gpio_export(gpio, 1); + gpio_export_link(&dev->dev, "onoff", gpio); + } else { + dev_err(&dev->dev, "Invalid GPS_EN pin\n"); + ret = -EINVAL; + goto err_invalid_pin2; + } + + /* Optional aiding pin */ + if (gpio_is_valid(pdata->tsync)) { + gpio = pdata->tsync; + /* AP_AGPS_TSYNC is low */ + gpio_request(gpio, "AP_AGPS_TSYNC"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_direction_output(gpio, 0); + + gpio_export(gpio, 1); + gpio_export_link(&dev->dev, "tsync", gpio); + } + + /* input UART pin need to set pull-up to prevent floating */ + if (gpio_is_valid(pdata->uart_rxd)) + s3c_gpio_setpull(pdata->uart_rxd, S3C_GPIO_PULL_UP); + + /* + * Get regulators. + * If always_on power, can remove below. + */ + bd->rtc_xi = regulator_get(&dev->dev, "gps_clk"); + if (IS_ERR_OR_NULL(bd->rtc_xi)) { + dev_err(&dev->dev, "gps_clk regulator_get error\n"); + ret = -EINVAL; + goto err_regulator_1; + } + + bd->vdd_18 = regulator_get(&dev->dev, "v_gps_1.8v"); + if (IS_ERR_OR_NULL(bd->vdd_18)) { + dev_err(&dev->dev, "vdd_18 regulator_get error\n"); + ret = -EINVAL; + goto err_regulator_2; + } + + /* + * Actually, we don't need rfkill becasue most of power sequences to be + * done by user level. Just leave this to know user trggers onoff so we + * can set pins PDN mode at suspend/resume. + */ + bd->rfk = rfkill_alloc("gsd4t", &dev->dev, RFKILL_TYPE_GPS, + &gsd4t_rfkill_ops, bd); + if (!bd->rfk) { + ret = -ENOMEM; + goto err_rfk_alloc; + } + + /* + * rfkill.h + * block true : off + * block false : on + */ + rfkill_init_sw_state(bd->rfk, true); + bd->in_use = false; + + ret = rfkill_register(bd->rfk); + if (ret) + goto err_rfkill; + + platform_set_drvdata(dev, bd); + + dev_info(&dev->dev, "ready\n"); + + return 0; + +err_rfkill: + rfkill_destroy(bd->rfk); +err_rfk_alloc: + regulator_put(bd->vdd_18); +err_regulator_2: + regulator_put(bd->rtc_xi); +err_regulator_1: + gpio_unexport(pdata->tsync); + gpio_unexport(pdata->onoff); +err_invalid_pin2: + gpio_unexport(pdata->nrst); +err_invalid_pin1: + kfree(bd); + return ret; +} + +static int __devexit gsd4t_remove(struct platform_device *dev) +{ + struct gsd4t_data *bd = platform_get_drvdata(dev); + struct gsd4t_platform_data *pdata = bd->pdata; + + if (bd->in_use) + rfkill_init_sw_state(bd->rfk, true); + + rfkill_unregister(bd->rfk); + rfkill_destroy(bd->rfk); + gpio_unexport(pdata->onoff); + gpio_unexport(pdata->nrst); + gpio_unexport(pdata->tsync); + gpio_free(pdata->onoff); + gpio_free(pdata->nrst); + + regulator_put(bd->vdd_18); + regulator_put(bd->rtc_xi); + + kfree(bd); + platform_set_drvdata(dev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int gsd4t_suspend(struct platform_device *dev, pm_message_t stata) +{ + struct gsd4t_data *bd = platform_get_drvdata(dev); + struct gsd4t_platform_data *pdata = bd->pdata; + + if (bd->in_use) + s5p_gpio_set_pd_cfg(pdata->nrst, S5P_GPIO_PD_OUTPUT1); + else + s5p_gpio_set_pd_cfg(pdata->nrst, S5P_GPIO_PD_OUTPUT0); + + return 0; +} + +static int gsd4t_resume(struct platform_device *dev) +{ + return 0; +} +#else +#define gsd4t_suspend NULL +#define gsd4t_resume NULL +#endif + +static struct platform_driver gsd4t_driver = { + .probe = gsd4t_probe, + .remove = __devexit_p(gsd4t_remove), + .suspend = gsd4t_suspend, + .resume = gsd4t_resume, + .driver = { + .name = "gsd4t", + }, +}; + +static int __init gsd4t_init(void) +{ + return platform_driver_register(&gsd4t_driver); +} + +static void __exit gsd4t_exit(void) +{ + platform_driver_unregister(&gsd4t_driver); +} + +module_init(gsd4t_init); +module_exit(gsd4t_exit); + +MODULE_AUTHOR("Minho Ban <mhban@samsung.com>"); +MODULE_DESCRIPTION("GSD4T GPS driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-exynos/idle-exynos5.S b/arch/arm/mach-exynos/idle-exynos5.S deleted file mode 100644 index a3575ca..0000000 --- a/arch/arm/mach-exynos/idle-exynos5.S +++ /dev/null @@ -1,210 +0,0 @@ -/* linux/arch/arm/mach-exynos/idle-exynos5.S - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS5 AFTR/LPA idle support - * Based on S3C2410 sleep code by: - * Ben Dooks, (c) 2004 Simtec Electronics - * - * Based on PXA/SA1100 sleep code by: - * Nicolas Pitre, (c) 2002 Monta Vista Software Inc - * Cliff Brake, (c) 2001 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/memory.h> -#include <plat/map-base.h> -#include <plat/map-s5p.h> -#include <mach/smc.h> - - .text - - /* - * exynos5_enter_lp - * - * entry: - * r1 = v:p offset - */ - -ENTRY(exynos5_enter_lp) - stmfd sp!, { r3 - r12, lr } - - adr r0, sleep_save_misc - -#ifdef CONFIG_ARM_TRUSTZONE - mrc p15, 0, r2, c1, c0, 1 @ read aux control register - str r2, [r0], #4 -#endif - mrc p15, 1, r2, c9, c0, 2 @ read l2 control register - str r2, [r0], #4 - mrc p15, 1, r2, c15, c0, 3 @ read l2 prefetch register - str r2, [r0], #4 - - ldr r3, =resume_with_mmu - bl cpu_suspend - - bl exynos5_L1_dcache_flush - - adr r0, sys_pwr_conf_addr - ldr r1, [r0] - ldr r2, [r1] - bic r2, r2, #(1<<16) - str r2, [r1] - -#ifdef CONFIG_ARM_TRUSTZONE - ldr r0, =SMC_CMD_CPU0AFTR - mov r1, #0 - mov r2, #0 - mov r3, #0 - smc 0 -#else - dsb - wfi -#endif - - /* Restore original sp */ - mov r0, sp - add r0, r0, #4 - ldr sp, [r0] - - mov r0, #0 - b early_wakeup - -resume_with_mmu: - adr r4, sleep_save_misc - -#ifdef CONFIG_ARM_TRUSTZONE - mov r3, #0 - - ldr r0, =SMC_CMD_REG - ldr r1, =SMC_REG_ID_CP15(1, 0, 0, 1) @ aux control register - ldr r2, [r4], #4 - smc 0 - ldr r0, =SMC_CMD_REG - ldr r1, =SMC_REG_ID_CP15(9, 1, 0, 2) @ L2 control register - ldr r2, [r4], #4 - smc 0 - ldr r0, =SMC_CMD_REG - ldr r1, =SMC_REG_ID_CP15(15, 1, 0, 3) @ L2 prefetch register - ldr r2, [r4], #4 - smc 0 -#else - ldr r2, [r4], #4 - mcr p15, 1, r2, c9, c0, 2 @ L2 control register - ldr r2, [r4], #4 - mcr p15, 1, r2, c15, c0, 3 @ L2 prefetch register -#endif - mov r0, #1 -early_wakeup: - - ldmfd sp!, { r3 - r12, pc } - - .ltorg - - /* - * sleep magic, to allow the bootloader to check for an valid - * image to resume to. Must be the first word before the - * s3c_cpu_resume entry. - */ - - .word 0x2bedf00d - -sleep_save_misc: - .long 0 - .long 0 - .long 0 - - .global sys_pwr_conf_addr -sys_pwr_conf_addr: - .long 0 - - /* - * exynos5_L1_dcache_flush - * - * L1 only dcache flush function - * - * When enter lowpower cpuidle mode, It is need to L1 only flush function. - */ -ENTRY(exynos5_L1_dcache_flush) - dmb @ ensure ordering with previous memory accesses - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq skip @ if loc is 0, then no need to clean - mov r10, #0 @ start clean at cache level 0 -loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache level - mov r1, r0, lsr r2 @ extract cache type bits from clidr - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - isb @ isb to sych the new cssr&csidr - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the way size - clz r5, r4 @ find bit position of way size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop2: - mov r9, r4 @ create working copy of max way size -loop3: - ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 - THUMB( lsl r6, r9, r5 ) - THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 - ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 - THUMB( lsl r6, r7, r2 ) - THUMB( orr r11, r11, r6 ) @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge loop3 - subs r7, r7, #1 @ decrement the index - bge loop2 -skip: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - dsb - isb - mov pc, lr -ENDPROC(exynos5_L1_dcache_flush) - - /* - * exynos5_idle_resume - * - * resume code entry for IROM to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) - */ - -ENTRY(exynos5_idle_resume) - /* - * To use JTEG after wakeup from power mode - * Set DBGEN, NIDEN, SPIDEN, SPNIDEN on TZPC1 - */ - ldr r0, =0x10110810 - mov r1, #0xf - str r1, [r0] - dsb - isb - - b cpu_resume diff --git a/arch/arm/mach-exynos/include/mach/bcm4752.h b/arch/arm/mach-exynos/include/mach/bcm4752.h new file mode 100644 index 0000000..832b4d7 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/bcm4752.h @@ -0,0 +1,26 @@ +/* linux/arm/arch/mach-exynos/include/mach/bcm47511.h + * + * Platform data Header for BCM47511(GPS) driver. + * + * Copyright (c) 2011 Samsung Electronics + * Minho Ban <mhban@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _BCM4752_H +#define _BCM4752_H + +struct bcm4752_platform_data { + unsigned int regpu; /* Power */ + unsigned int uart_rxd; /* Start gpio number of uart */ + /* Below are machine dependant */ + unsigned int gps_cntl; /* Request 26MHz CP clock */ + const char *reg32khz; /* regulator id for 32KHz clk */ +}; + +#endif /* _BCM47511_H */ + + diff --git a/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h b/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h index fabd1e8..f8f377d 100644 --- a/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h +++ b/arch/arm/mach-exynos/include/mach/busfreq_exynos4.h @@ -24,6 +24,7 @@ #define TIMINGROW_OFFSET 0x34 +#define PRIME_DMC_MAX_THRESHOLD 30 #define EXYNOS4412_DMC_MAX_THRESHOLD 30 #define EXYNOS4212_DMC_MAX_THRESHOLD 30 diff --git a/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h b/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h deleted file mode 100644 index fe00bd1..0000000 --- a/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h +++ /dev/null @@ -1,93 +0,0 @@ -/* linux/arch/arm/mach-exynos/include/mach/busfreq_exynos5.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - BUSFreq support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_BUSFREQ_H -#define __ASM_ARCH_BUSFREQ_H __FILE__ - -#include <linux/notifier.h> -#include <linux/earlysuspend.h> - -#include <mach/ppmu.h> - -#define MAX_LOAD 100 -#define LOAD_HISTORY_SIZE 5 -#define DIVIDING_FACTOR 10000 - -#define TIMINGROW_OFFSET 0x34 - -enum busfreq_level_idx { - LV_0, - LV_1, - LV_2, - LV_3, - LV_INT_END, - LV_MIF_END = LV_3, -}; - -struct opp; -struct device; -struct busfreq_table; - -struct busfreq_data { - bool use; - struct device *dev[PPMU_TYPE_END]; - struct delayed_work worker; - unsigned long curr_freq[PPMU_TYPE_END]; - unsigned long max_freq[PPMU_TYPE_END]; - unsigned long min_freq[PPMU_TYPE_END]; - struct regulator *vdd_reg[PPMU_TYPE_END]; - unsigned int sampling_rate; - struct kobject *busfreq_kobject; - struct busfreq_table *table[PPMU_TYPE_END]; - unsigned long long time_in_state[PPMU_TYPE_END][LV_INT_END]; - unsigned long long last_time[PPMU_TYPE_END]; - unsigned int load_history[PPMU_END][LOAD_HISTORY_SIZE]; - int index; - - struct notifier_block exynos_buspm_notifier; - struct notifier_block exynos_reboot_notifier; - struct notifier_block exynos_request_notifier; - struct early_suspend busfreq_early_suspend_handler; - struct attribute_group busfreq_attr_group; - int (*init) (struct device *dev, struct busfreq_data *data); - void (*monitor) (struct busfreq_data *data, struct opp **mif_opp, - struct opp **int_opp); - void (*target) (struct busfreq_data *data, enum ppmu_type type, int index); - unsigned int (*get_int_volt) (unsigned long freq); - int (*get_table_index) (unsigned long freq, enum ppmu_type type); - void (*busfreq_prepare) (int index); - void (*busfreq_post) (int index); - void (*busfreq_suspend) (void); - void (*busfreq_resume) (void); - - /* Dividers calculated at boot/probe-time */ - unsigned int lex_divtable[LV_INT_END]; - unsigned int r0x_divtable[LV_INT_END]; - unsigned int r1x_divtable[LV_INT_END]; - unsigned int cdrex_divtable[LV_MIF_END]; - unsigned int cdrex2_divtable[LV_MIF_END]; -}; - -struct busfreq_table { - unsigned int idx; - unsigned int mem_clk; - unsigned int volt; - unsigned int clk_topdiv; - unsigned int clk_dmc0div; - unsigned int clk_dmc1div; -}; - -void exynos_request_apply(unsigned long freq); -unsigned long step_down(struct busfreq_data *data, enum ppmu_type type, int step); - -int exynos5250_init(struct device *dev, struct busfreq_data *data); -#endif /* __ASM_ARCH_BUSFREQ_H */ diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h index 9ef27df..a799365 100644 --- a/arch/arm/mach-exynos/include/mach/cpufreq.h +++ b/arch/arm/mach-exynos/include/mach/cpufreq.h @@ -23,9 +23,13 @@ enum cpufreq_level_index { }; enum busfreq_level_request { - BUS_L0, /* MEM 400MHz BUS 200MHz */ - BUS_L1, /* MEM 267MHz BUS 160MHz */ - BUS_L2, /* MEM 133MHz BUS 133MHz */ + BUS_L0, /* MEM 400MHz BUS 266MHz */ + BUS_L1, /* MEM 400MHz BUS 200MHz */ + BUS_L2, /* MEM 267MHz BUS 200MHz */ + BUS_L3, /* MEM 267MHz BUS 160MHz */ + BUS_L4, /* MEM 160MHz BUS 160MHz */ + BUS_L5, /* MEM 133MHz BUS 133MHz */ + BUS_L6, /* MEM 100MHz BUS 100MHz */ BUS_LEVEL_END, }; diff --git a/arch/arm/mach-exynos/include/mach/gc1-jack.h b/arch/arm/mach-exynos/include/mach/gc1-jack.h new file mode 100644 index 0000000..ce915fd --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gc1-jack.h @@ -0,0 +1,25 @@ +/* + * gc1-jack.h - Jack Management of GC1 Project + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __GC1_JACK_H__ +#define __GC1_JACK_H__ __FILE__ + +void gc1_jack_init(void); +extern void set_wm1811_micbias2(bool on); + +#endif /* __GC1_JACK_H__ */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-exynos4.h b/arch/arm/mach-exynos/include/mach/gpio-exynos4.h index 93b5b7b..3d7368d 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-exynos4.h +++ b/arch/arm/mach-exynos/include/mach/gpio-exynos4.h @@ -205,8 +205,9 @@ enum exynos4212_gpio_number { #include <asm-generic/gpio.h> #if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_MACH_SLP_MIDAS) \ - || defined(CONFIG_MACH_SLP_PQ) \ - || defined(CONFIG_MACH_SLP_PQ_LTE) + || defined(CONFIG_MACH_SLP_PQ) \ + || defined(CONFIG_MACH_SLP_PQ_LTE)\ + || defined(CONFIG_MACH_SLP_T0_LTE) #include "gpio-midas.h" #endif @@ -214,14 +215,10 @@ enum exynos4212_gpio_number { #include "gpio-naples.h" #endif -#if defined(CONFIG_MACH_U1) +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) #include "gpio-u1.h" #endif -#if defined(CONFIG_MACH_U1CAMERA_BD) -#include "gpio-u1camera.h" -#endif - #if defined(CONFIG_MACH_Q1_BD) #include "gpio-q1.h" #endif @@ -238,4 +235,7 @@ enum exynos4212_gpio_number { #include "gpio-p8.h" #endif +#if defined(CONFIG_MACH_P8LTE) +#include "gpio-p8lte.h" +#endif #endif /* __ASM_ARCH_GPIO_EXYNOS4_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1ctc.h b/arch/arm/mach-exynos/include/mach/gpio-iron.h index e7c17d0..a874815 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1ctc.h +++ b/arch/arm/mach-exynos/include/mach/gpio-iron.h @@ -10,20 +10,13 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BOOT_MODE EXYNOS4_GPX0(3) +#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) +#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) +#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) +#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) #define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) #define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) #define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) #define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) @@ -34,23 +27,33 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) +#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) +#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) #define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) +/* keys */ +#define GPIO_KBR_0 EXYNOS4_GPX2(2) +#define GPIO_KBR_1 EXYNOS4_GPX2(4) +#define GPIO_KBR_2 EXYNOS4_GPX3(0) +#define GPIO_KBR_3 EXYNOS4_GPX3(3) +#define GPIO_KBR_4 EXYNOS4_GPX3(4) + +#define GPIO_KBC_0 EXYNOS4_GPL2(3) +#define GPIO_KBC_1 EXYNOS4_GPL2(4) +#define GPIO_KBC_2 EXYNOS4_GPL2(5) +#define GPIO_KBC_3 EXYNOS4_GPL2(6) +#define GPIO_KBC_4 EXYNOS4_GPL2(7) + /* Sensors & NFC*/ #define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) +#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPF0(0) +#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPF0(1) #define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) #define GPIO_ACC_INT EXYNOS4_GPX0(0) - #define GPIO_GYRO_DE EXYNOS4_GPL2(0) #define GPIO_GPS_nRST EXYNOS4_GPL2(1) #define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) @@ -62,26 +65,16 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPM4(4) #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY0(1) -#define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) -#define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ -#define GPIO_DET_35 EXYNOS4_GPX0(1) +#define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(3) #define GPIO_PMU_RST EXYNOS4_GPX3(2) @@ -89,8 +82,12 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) #define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_EN EXYNOS4_GPL0(3) + #define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) #define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_HALL_SW EXYNOS4_GPX3(7) + #define GPIO_BT_EN EXYNOS4_GPL0(6) #define GPIO_BT_WAKE EXYNOS4_GPX3(1) @@ -129,17 +126,14 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) #define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) +#define GPIO_3_TOUCH_EN EXYNOS4_GPC1(0) #define GPIO_PWM0 EXYNOS4_GPD0(0) #define GPIO_PWM1 EXYNOS4_GPD0(1) #define GPIO_PWM2 EXYNOS4_GPD0(2) #define GPIO_PWM3 EXYNOS4_GPD0(3) -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - #define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) #define GPIO_WLAN_EN_AF 1 #define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) @@ -157,54 +151,47 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) #define GPIO_WLAN_SDIO_D3_AF 2 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) +#define GPIO_USB_SEL EXYNOS4212_GPJ1(4) -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) #define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - #define GPIO_OTG_EN EXYNOS4_GPF0(7) -#define GPIO_OLED_ID EXYNOS4_GPF1(0) #define GPIO_ISP_RESET EXYNOS4_GPF1(3) #define GPIO_FUEL_SCL EXYNOS4_GPF1(4) #define GPIO_FUEL_SDA EXYNOS4_GPF1(5) #define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#define GPIO_S_LED_I2C_SCL +#define GPIO_S_LED_I2C_SDA #define GPIO_OLED_DET EXYNOS4_GPF3(0) +#define GPIO_LCD_SEL EXYNOS4_GPF2(6) +#define GPIO_LCD_OE EXYNOS4_GPF2(7) +#define GPIO_TSP_SEL EXYNOS4_GPF2(7) + #define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) #define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#if defined(CONFIG_REGULATOR_LP8720) +#define GPIO_FOLDER_PMIC_EN EXYNOS4_GPL0(4) +#define GPIO_FOLDER_PMIC_SDA EXYNOS4_GPF0(4) +#define GPIO_FOLDER_PMIC_SCL EXYNOS4_GPF0(6) + +#if defined(CONFIG_MACH_GRANDE) +#define GPIO_SUB_PMIC_EN EXYNOS4_GPF0(2) +#define GPIO_SUB_PMIC_SDA EXYNOS4_GPF0(7) +#define GPIO_SUB_PMIC_SCL EXYNOS4_GPF1(0) +#endif +#endif + /* Definitions for Sii 9244B0 */ #define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) #define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) #define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) #define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) + #define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) #define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) @@ -212,26 +199,20 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) #define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - #define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) #define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - #define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_UP EXYNOS4_GPX1(3) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(5) +#define GPIO_HOLD EXYNOS4_GPX0(5) #define GPIO_OK_KEY EXYNOS4_GPX3(5) - +#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) /*system_rev == 11*/ +#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3) /*system_rev >= 15*/ #define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - #define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) #define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) #define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) @@ -239,10 +220,21 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_FM_INT EXYNOS4_GPX1(3) +/* Modem Interface GPIOs - M0 HSIC */ +#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_PHONE_ON EXYNOS4212_GPM1(1) +#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) +#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) +#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_CP_RST EXYNOS4_GPX3(2) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) +#if defined(CONFIG_GSM_MODEM_ESC6270) /* Definitions for DPRAM */ #define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) #define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) @@ -255,33 +247,18 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) #define GPIO_DPRAM_BUSY EXYNOS4_GPY1(2) -/* Definitions for CMC221 */ -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_AP_CP_INT EXYNOS4_GPF2(2) - -#define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) -#define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) -#define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) -#define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) -#define GPIO_USB_HUB_CONNECT EXYNOS4212_GPV3(5) -#define GPIO_USB_BOOT_EN EXYNOS4212_GPV3(7) - -#define GPIO_BOOT_SW_SEL EXYNOS4212_GPV3(6) - -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) - -#define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) - #define GPIO_CP_MSM_RST EXYNOS4_GPL2(4) -#define GPIO_CP_MSM_PMU_RST EXYNOS4_GPX3(2) -#define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) - -#define GPIO_MSM_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ - -#define GPIO_MSM_DPRAM_INT EXYNOS4_GPX2(0) -#define MSM_DPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ - +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(6) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(5) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(4) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(12) +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX1(7) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(15) +#endif + +/* DUMMY GPIOS */ +#define GPIO_HDMI_HPD EXYNOS4_GPA1(4) +#define GPIO_HDMI_EN EXYNOS4_GPA1(4) +#define GPIO_V_BUS_INT EXYNOS4_GPA1(4) #endif /* __MACH_GPIO_C1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-midas.h b/arch/arm/mach-exynos/include/mach/gpio-midas.h index 894c1cf..2ed73f2 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-midas.h +++ b/arch/arm/mach-exynos/include/mach/gpio-midas.h @@ -13,40 +13,43 @@ #ifndef __ASM_ARCH_GPIO_MIDAS_H #define __ASM_ARCH_GPIO_MIDAS_H __FILE__ -#if defined(CONFIG_MACH_MIDAS_01_BD) || defined(CONFIG_GPIO_MIDAS_01_BD) +/* MACH_MIDAS_01_BD nor MACH_MIDAS_01_BD nomore exists + but SLP use GPIO_MIDAS_01_BD, GPIO_MIDAS_02_BD */ +#if defined(CONFIG_GPIO_MIDAS_01_BD) #include "gpio-rev01-midas.h" -#elif defined(CONFIG_MACH_MIDAS_02_BD) || defined(CONFIG_GPIO_MIDAS_02_BD) +#elif defined(CONFIG_GPIO_MIDAS_02_BD) #include "gpio-rev02-midas.h" -#elif defined(CONFIG_MACH_M0_GRANDECTC) +#elif defined(CONFIG_MACH_IRON) +#include "gpio-iron.h" +#elif defined(CONFIG_MACH_GRANDE) #include "gpio-rev00-m0grandectc.h" #elif defined(CONFIG_MACH_M0_CTC) #include "gpio-rev00-m0ctc.h" #elif defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) #include "gpio-rev00-m0.h" -#elif defined(CONFIG_MACH_M3) -#include "gpio-rev00-m3.h" #elif defined(CONFIG_MACH_C1) && !defined(CONFIG_TARGET_LOCALE_KOR) #include "gpio-rev00-c1.h" -#elif defined(CONFIG_MACH_C1CTC) -#include "gpio-rev00-c1ctc.h" -#elif (defined(CONFIG_MACH_C1VZW) || defined(CONFIG_MACH_SLP_PQ_LTE)) && \ - !defined(CONFIG_TARGET_LOCALE_KOR) +#elif defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) +#include "gpio-rev03-c1kor.h" +#elif defined(CONFIG_MACH_SLP_PQ_LTE) && !defined(CONFIG_TARGET_LOCALE_KOR) #include "gpio-rev00-c1vzw.h" -#elif defined(CONFIG_MACH_JENGA) -#include "gpio-rev00-jenga.h" -#elif defined(CONFIG_MACH_S2PLUS) -#include "gpio-rev00-s2plus.h" +#elif defined(CONFIG_MACH_M3) +#include "gpio-rev00-m3.h" #elif defined(CONFIG_GPIO_NAPLES_00_BD) #include "gpio-rev00-naples.h" -#elif (defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW)) && \ - defined(CONFIG_TARGET_LOCALE_KOR) -#include "gpio-rev03-c1kor.h" #elif defined(CONFIG_MACH_P4NOTE) #include "gpio-rev00-p4notepq.h" #elif defined(CONFIG_MACH_GC1) #include "gpio-rev00-gc1.h" -#elif defined(CONFIG_MACH_T0) +#elif defined(CONFIG_MACH_T0_CHN_CTC) +#include "gpio-rev00-t0ctc.h" +#elif defined(CONFIG_MACH_T0_CHN_CU_DUOS) || \ + defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#include "gpio-rev00-t0cu-duos.h" +#elif defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_SLP_T0_LTE) #include "gpio-rev00-t0.h" +#elif defined(CONFIG_MACH_BAFFIN) +#include "gpio-rev00-baffin.h" #endif #endif /* __ASM_ARCH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-p2.h b/arch/arm/mach-exynos/include/mach/gpio-p2.h index 986bed3..ab65a4d 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-p2.h +++ b/arch/arm/mach-exynos/include/mach/gpio-p2.h @@ -129,6 +129,8 @@ #define IRQ_SUSPEND_REQUEST IRQ_EINT11 #define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 +#define GPIO_LCD_BACKLIGHT_PWM EXYNOS4_GPD0(1) + #define EXYNOS4_GPD_0_0_TOUT_0 (0x2 << 0) #if defined(CONFIG_FB_MDNIE_PWM) #define EXYNOS4_GPD_0_1_TOUT_1 (0x3 << 4) diff --git a/arch/arm/mach-exynos/include/mach/gpio-p8lte.h b/arch/arm/mach-exynos/include/mach/gpio-p8lte.h new file mode 100644 index 0000000..18458a1 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gpio-p8lte.h @@ -0,0 +1,265 @@ +#ifndef __MACH_GPIO_P8LTE_H +#define __MACH_GPIO_P8LTE_H __FILE__ + +#define GPIO_XMMC0_CDn EXYNOS4_GPK0(2) + +#define GPIO_PS_ALS_SDA EXYNOS4_GPK2(2) +#define GPIO_PS_ALS_SCL EXYNOS4_GPK3(2) + +#define GPIO_GYRO_INT EXYNOS4_GPX0(0) +#define GPIO_PS_VOUT EXYNOS4_GPL0(6) + +#define GPIO_BUCK1_EN_A EXYNOS4_GPX0(5) +#define GPIO_BUCK1_EN_B EXYNOS4_GPX0(6) +#define GPIO_BUCK2_EN EXYNOS4_GPL0(0) +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) + + +#define GPIO_VOL_UP EXYNOS4_GPX2(0) +#define GPIO_VOL_DOWN EXYNOS4_GPX2(1) + +#define GPIO_nPOWER EXYNOS4_GPX2(7) +/* +#define VT_CAM_SDA_18V EXYNOS4_GPC1(0) +#define VT_CAM_SCL_18V EXYNOS4_GPC1(2) + +#define GPIO_CAM_SENSOR_CORE EXYNOS4210_GPE2(5) +#define GPIO_VT_CAM_15V EXYNOS4210_GPE2(2) +#define GPIO_CAM_IO_EN EXYNOS4210_GPE2(1) +*/ +#define CODEC_VT_SDA_18V EXYNOS4_GPC1(3) +#define CODEC_VT_SCL_18V EXYNOS4_GPC1(4) + +/*#define GPIO_ISP_RESET EXYNOS4_GPY3(7)*/ +#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) +#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) + +#define GPIO_MASSMEM_EN_LEVEL 0 + +#define GPIO_CAM_MOVIE_EN EXYNOS4_GPL0(1) +#define GPIO_CAM_FLASH_EN EXYNOS4_GPL0(2) + +#define GPIO_TSP_LDO_ON EXYNOS4_GPY0(1) +/* +#define GPIO_CAM_FLASH_SET EXYNOS4210_GPE0(2) +#define GPIO_TSP_RST EXYNOS4_GPL0(5) +#define GPIO_TSP_INT EXYNOS4_GPX0(4) +*/ +#define GPIO_TSP_SDA EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL EXYNOS4_GPA1(3) +#define GPIO_TSP_VENDOR EXYNOS4_GPY5(6) +#define GPIO_TSP_INT_18V EXYNOS4_GPL2(5) + +#define GPIO_LCD_RST EXYNOS4_GPF0(1) +#define GPIO_LCD_EN EXYNOS4_GPL0(7) +#define GPIO_LCD_LDO_EN EXYNOS4_GPK1(1) +#define GPIO_UART_SEL1 EXYNOS4_GPY4(7) +#define GPIO_UART_SEL2 EXYNOS4_GPY0(0) +/* +#define GPIO_CAM_PCLK EXYNOS4210_GPJ0(0) +#define GPIO_CAM_VSYNC EXYNOS4210_GPJ0(1) +#define GPIO_CAM_HSYNC EXYNOS4210_GPJ0(2) +*/ +#define GPIO_CAM_MCLK EXYNOS4210_GPJ1(3) +/* +#define GPIO_CAM_AVDD_EN EXYNOS4210_GPJ1(4) + +#define GPIO_CAM_VGA_nSTBY EXYNOS4_GPL2(0) +#define GPIO_CAM_VGA_nRST EXYNOS4_GPL2(1) +*/ +#define GPIO_2M_nSTBY EXYNOS4_GPL2(0) +#define GPIO_2M_nRST EXYNOS4_GPL2(1) +#define GPIO_3M_nSTBY EXYNOS4_GPL2(2) +#define GPIO_3M_nRST EXYNOS4_GPL2(7) + +#define GPIO_DET_35 EXYNOS4_GPX3(2) +#define GPIO_DET_35_AF 0xF + +#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) +#define GPIO_EAR_SEND_END_AF 0xF + +#define GPIO_GPS_nRST EXYNOS4_GPY5(4) +#define GPIO_GPS_PWR_EN EXYNOS4_GPY5(5) + +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_RXD_AF 2 + +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_TXD_AF 2 + +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_CTS_AF 2 + +#define GPIO_BT_RTS EXYNOS4_GPA0(3) +#define GPIO_BT_RTS_AF 2 + +#define GPIO_GPS_RXD EXYNOS4_GPA0(4) +#define GPIO_GPS_RXD_AF 2 + +#define GPIO_GPS_TXD EXYNOS4_GPA0(5) +#define GPIO_GPS_TXD_AF 2 + +#define GPIO_GPS_CTS EXYNOS4_GPA0(6) +#define GPIO_GPS_CTS_AF 2 + +#define GPIO_GPS_RTS EXYNOS4_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +/*#define GPIO_ALC_nRST EXYNOS4_GPX1(7)*/ + +#define GPIO_DOUBLE_RR EXYNOS4_GPL2(3) +/*#define GPIO_2MIC_EN EXYNOS4_GPL2(5)*/ + +#define GPIO_CURR_ADJ EXYNOS4_GPY5(7) +#define GPIO_TA_EN EXYNOS4_GPY6(6) +#define GPIO_TA_nCHG EXYNOS4_GPX0(4) +#define GPIO_TA_nCONNECTED EXYNOS4_GPX0(1) +/* +//#define GPIO_CHG_SDA_28V EXYNOS4_GPB(2) +//#define GPIO_CHG_SCL_28V EXYNOS4_GPB(3) +*/ +#define GPIO_IPC_RXD EXYNOS4_GPA1(4) +#define GPIO_IPC_RXD_AF 2 + +#define GPIO_IPC_TXD EXYNOS4_GPA1(5) +#define GPIO_IPC_TXD_AF 2 + +/*dpram setting for VIA CP Modem*/ + +#define GPIO_PHONE_ON EXYNOS4_GPC1(1) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) + +#define GPIO_VIA_PS_HOLD_OFF EXYNOS4_GPX2(6) +#define GPIO_CP_AP_DPRAM_INT EXYNOS4_GPX3(5) +#define GPIO_VIA_DPRAM_INT_N EXYNOS4210_GPE0(3) +#define GPIO_CP_RST EXYNOS4_GPX2(5) + +/*#define GPIO_LVDS_NSHDN EXYNOS4_GPX1(5)*/ +#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) + +#define IRQ_PHONE_ACTIVE IRQ_EINT14 +#define IRQ_SUSPEND_REQUEST IRQ_EINT11 +#define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 + +#define EXYNOS4_GPD_0_0_TOUT_0 (0x2 << 0) +#define EXYNOS4_GPD_0_1_TOUT_1 (0x2 << 4) +#define EXYNOS4_GPD_0_2_TOUT_2 (0x2 << 8) +#define EXYNOS4_GPD_0_3_TOUT_3 (0x2 << 12) + +#define GPIO_WLAN_EN EXYNOS4_GPL1(2) +#define GPIO_WLAN_EN2 EXYNOS4_GPK1(0) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_nRST EXYNOS4_GPL0(4) + +/* CSR8811 Project(Alan.Ko) 2011.07.02 */ +/*#define GPIO_BT_EN EXYNOS4_GPL0(4)*/ +/* CSR8811 Project(Alan.Ko) end */ + +#define GPIO_BT_nRST EXYNOS4_GPY6(1) + +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX1(0) +#define GPIO_WLAN_HOST_WAKE_AF 0xF + +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX1(1) +#define GPIO_BT_HOST_WAKE_AF 0xF + +/* CSR8811 Project(Alan.Ko) 2011.07.02 */ +/*#define GPIO_BT_WAKE EXYNOS4_GPX3(1)*/ +/* CSR8811 Project(Alan.Ko) end */ + +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 + +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 + +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 + +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 + +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 + +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define GPIO_HW_REV0 EXYNOS4_GPY5(0) +#define GPIO_HW_REV1 EXYNOS4_GPY5(1) +#define GPIO_HW_REV2 EXYNOS4_GPY5(2) +#define GPIO_HW_REV3 EXYNOS4_GPY5(3) + +#define GPIO_HDMI_EN1 EXYNOS4_GPL1(1) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_MHL_WAKE_UP_AF S3C_GPIO_SFN(0xF) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + +/*IR*/ +#define GPIO_IRDA_EN EXYNOS4_GPX3(0) +#define GPIO_IRDA_nINT EXYNOS4_GPB(4) + +#define GPIO_SIM_DETECT EXYNOS4_GPX0(3) + +#define GPIO_MSENSE_INT EXYNOS4_GPX2(2) +#define GPIO_DOCK_INT EXYNOS4_GPX2(4) + +#define GPIO_USB_OTG_EN EXYNOS4_GPX3(3) +#define GPIO_USB_SEL1 EXYNOS4_GPY6(4) +#define GPIO_USB_SEL2 EXYNOS4_GPY4(6) +#define GPIO_USB_SEL3 EXYNOS4_GPY4(5) +#define GPIO_IF_CON_SENSE EXYNOS4_GPY3(3) +#define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) + +#define GPIO_MSENSOR_MHL_SDA_28V EXYNOS4_GPD0(2) +#define GPIO_MSENSOR_MHL_SDA_AF 0x3 +#define GPIO_MSENSOR_MHL_SCL_28V EXYNOS4_GPD0(3) +#define GPIO_MSENSOR_MHL_SCL_AF 0x3 +#define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) +#define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN +#define GPIO_USB_HUB_I2C_SDA EXYNOS4_GPY3(4) +#define GPIO_USB_HUB_I2C_SCL EXYNOS4_GPY3(5) +#define GPIO_USB_HUB_RST EXYNOS4_GPY3(6) +#endif + +#define GPIO_AP_HDMI_SDA GPIO_MSENSOR_MHL_SDA_28V +#define GPIO_AP_HDMI_SDA_AF GPIO_MSENSOR_MHL_SDA_AF +#define GPIO_AP_HDMI_SCL GPIO_MSENSOR_MHL_SCL_28V +#define GPIO_AP_HDMI_SCL_AF GPIO_MSENSOR_MHL_SCL_AF +#define GPIO_AP_SDA_18V GPIO_MHL_SDA_18V +#define GPIO_AP_SCL_18V GPIO_MHL_SCL_18V + +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +/*#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP)*/ + +#define GPIO_MIC_BIAS_EN EXYNOS4_GPY6(7) +#define GPIO_EAR_MIC_BIAS_EN EXYNOS4_GPL2(6) + +#define GPIO_REMOTE_SENSE_IRQ EXYNOS4_GPX0(2) + +#define GPIO_ACCESSORY_EN EXYNOS4_GPL1(0) +#define GPIO_ACCESSORY_INT EXYNOS4_GPX1(7) +#define GPIO_ACCESSORY_OUT_5V EXYNOS4_GPY3(1) + + +#define GPIO_220_PMIC_PWRON EXYNOS4_GPY6(2) +#define GPIO_LTE_PS_HOLD_OFF EXYNOS4_GPL0(5) +#define GPIO_CMC_RST EXYNOS4_GPY6(3) + +#define GPIO_LTE_ACTIVE EXYNOS4_GPX1(2) + +#define GPIO_LTE2AP_STATUS EXYNOS4_GPX1(4) +#define GPIO_AP2LTE_STATUS EXYNOS4_GPY4(3) +#define GPIO_LTE2AP_WAKEUP EXYNOS4_GPX1(3) +#define GPIO_AP2LTE_WAKEUP EXYNOS4_GPY4(4) + +#define IRQ_LTE_ACTIVE IRQ_EINT10 +#define IRQ_LTE2AP_WAKEUP IRQ_EINT11 + + +#endif /* __MACH_GPIO_P8LTE_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1vzw.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-baffin.h index 605b70c..15e3ff6 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1vzw.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-baffin.h @@ -1,5 +1,5 @@ -#ifndef __MACH_GPIO_C1VZW_H -#define __MACH_GPIO_C1VZW_H __FILE__ +#ifndef __MACH_GPIO_BAFFIN_H +#define __MACH_GPIO_BAFFIN_H __FILE__ #include <mach/gpio.h> @@ -15,17 +15,6 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FM_I2S_DI EXYNOS4_GPC0(3) #define GPIO_FM_I2S_DO EXYNOS4_GPC0(4) -#ifdef CONFIG_AUDIENCE_ES305 -#define GPIO_ES305_WAKEUP EXYNOS4_GPC0(4) -#define GPIO_ES305_RESET EXYNOS4_GPF2(5) -#endif - -#define GPIO_FM34_PWDN EXYNOS4_GPL0(3) -#define GPIO_FM34_RESET EXYNOS4_GPY1(3) -#define GPIO_FM34_BYPASS EXYNOS4_GPY1(2) -#define GPIO_FM34_SCL EXYNOS4212_GPM4(0) -#define GPIO_FM34_SDA EXYNOS4212_GPM4(1) - #define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) #define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) #define GPIO_PMIC_SDA EXYNOS4_GPB(2) @@ -43,16 +32,15 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) #define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM0(7) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) +#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) +#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) @@ -82,7 +70,8 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) #define GPIO_BARO_INT EXYNOS4_GPF0(5) -#define GPIO_TF_EN EXYNOS4_GPY0(1) +#define GPIO_TF_EN EXYNOS4_GPY2(0) + #define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) #define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) #define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) @@ -96,10 +85,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_DET_35 EXYNOS4_GPX0(1) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPC0(3) -#define GPIO_THIRD_MIC_BIAS_EN EXYNOS4_GPF2(0) - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) #define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) @@ -143,11 +129,25 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FLM_TXD EXYNOS4_GPA1(5) #define GPIO_FLM_TXD_AF 2 +#ifdef CONFIG_FM34_WE395 +#define GPIO_FM34_PWDN EXYNOS4_GPL0(3) +#define GPIO_FM34_RESET EXYNOS4_GPL0(1) +#define GPIO_FM34_BYPASS EXYNOS4_GPL0(2) +#define GPIO_FM34_RESET_05 EXYNOS4_GPY1(3) +#define GPIO_FM34_BYPASS_05 EXYNOS4_GPY1(2) +#define GPIO_FM34_SCL EXYNOS4212_GPM4(0) +#define GPIO_FM34_SDA EXYNOS4212_GPM4(1) +#endif + #define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) #define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) + + #define GPIO_HDMI_EN EXYNOS4_GPL0(4) + #define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) -#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(0) +#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(0) #define GPIO_PWM0 EXYNOS4_GPD0(0) #define GPIO_PWM1 EXYNOS4_GPD0(1) @@ -183,8 +183,6 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_TA_EN EXYNOS4_GPL2(2) -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - #define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) #define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) #define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) @@ -197,9 +195,12 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FUEL_SCL EXYNOS4_GPF1(4) #define GPIO_FUEL_SDA EXYNOS4_GPF1(5) +#define GPIO_LCD_BL_EN EXYNOS4_GPF0(5) #define GPIO_MLCD_RST EXYNOS4_GPF2(1) #define GPIO_UART_SEL EXYNOS4_GPF2(3) +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) #define GPIO_LTE_VIA_UART_SEL EXYNOS4212_GPJ0(6) +#endif #define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) #define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) #define GPIO_OLED_DET EXYNOS4_GPF3(0) @@ -235,16 +236,15 @@ extern void midas_config_sleep_gpio_table(void); #define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) #define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) #define GPIO_HDMI_HPD EXYNOS4_GPX3(7) #define GPIO_nPOWER EXYNOS4_GPX2(7) #define GPIO_OK_KEY EXYNOS4_GPX3(5) -#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) - -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) /* rev0.9 ~ */ -#define GPIO_WPC_INT EXYNOS4_GPX3(0) +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) #define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) @@ -279,8 +279,13 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_LTE_ACTIVE EXYNOS4_GPX1(6) #define LTE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) #define GPIO_CMC_IDPRAM_INT_00 EXYNOS4_GPX3(3) #define CMC_IDPRAM_INT_IRQ_00 IRQ_EINT(27) /* IRQ of GPX3[3] */ +#else +#define GPIO_CMC_IDPRAM_INT_00 EXYNOS4_GPX2(0) +#define CMC_IDPRAM_INT_IRQ_00 IRQ_EINT(16) /* IRQ of GPX2[0] */ +#endif #define GPIO_CMC_IDPRAM_INT_01 EXYNOS4_GPX2(0) #define CMC_IDPRAM_INT_IRQ_01 IRQ_EINT(16) /* IRQ of GPX2[0] */ @@ -291,17 +296,22 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_AP2CMC_INT2 EXYNOS4_GPX1(2) + /* Definitions for an USB HUB for CMC221 */ #define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) #define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) +/* Definitions for PDA_ACTIVE for CMC221 & CBP7.2 */ +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) + +#if defined(CONFIG_MACH_BAFFIN_KOR_LGT) /* Definitions for CBP7.2 */ #define GPIO_CBP_PMIC_PWRON EXYNOS4212_GPM0(6) #define GPIO_CBP_PS_HOLD_OFF EXYNOS4212_GPM1(0) #define GPIO_CBP_CP_RST EXYNOS4_GPF2(4) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) #define GPIO_CBP_PHONE_ACTIVE EXYNOS4_GPX1(3) #define CBP_PHONE_ACTIVE_IRQ IRQ_EINT(11) @@ -312,5 +322,17 @@ extern void midas_config_sleep_gpio_table(void); #define CBP_DPRAM_INT_IRQ_01 IRQ_EINT(29) /* IRQ of GPX3[5] */ #define GPIO_CBP_BOOT_SEL EXYNOS4212_GPM0(5) +#endif + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#define GPIO_TDMB_EN EXYNOS4_GPC0(0) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) +#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) +#define GPIO_TDMB_INT_AF 0xf +#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#endif -#endif /* __MACH_GPIO_C1VZW_H */ +#endif /* __MACH_GPIO_BAFFIN_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h index 827f1f9..fc4004c 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-c1.h @@ -36,17 +36,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) #define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) #define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPJ0(6) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) -#if 1 #define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) #define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#else -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) -#endif #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) @@ -76,7 +70,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) #define GPIO_BARO_INT EXYNOS4_GPF0(5) -#define GPIO_TF_EN EXYNOS4_GPY0(1) +#define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) #define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h index 04e3fb8..57f75a6 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-gc1.h @@ -66,21 +66,27 @@ extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); /* Sensors */ #define GPIO_ACC_INT EXYNOS4_GPX0(0) +#define GPIO_GYRO_INT EXYNOS4_GPF0(3) +#define GPIO_GYRO_DE EXYNOS4_GPL2(0) + #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) #define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPJ0(5) /* Sensors */ #define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_DET_35 EXYNOS4_GPX0(1) +#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) #define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) +#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPJ0(3) #define GPIO_PMU_RST EXYNOS4_GPX3(2) @@ -258,6 +264,8 @@ extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); #define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) #define GPIO_CP_RST EXYNOS4_GPX3(2) +#define GPIO_SIM_DETECT EXYNOS4_GPX3(5) + #define GPIO_FM_RST EXYNOS4_GPC1(1) #else @@ -299,8 +307,10 @@ extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); #define GPIO_PLAY_KEY EXYNOS4_GPX1(4) #define GPIO_S1_KEY EXYNOS4_GPX2(0) #define GPIO_S2_KEY EXYNOS4_GPX2(1) -#define GPIO_WIDE_KEY EXYNOS4_GPX2(2) -#define GPIO_TELE_KEY EXYNOS4_GPX3(3) +#define GPIO_TELE_KEY EXYNOS4_GPX2(2) +#define GPIO_WIDE_KEY EXYNOS4_GPX3(3) +#define GPIO_FAST_TELE_KEY EXYNOS4_GPX1(4) +#define GPIO_FAST_WIDE_KEY EXYNOS4_GPX0(4) #define GPIO_FM_INT_REV15 EXYNOS4_GPX1(4) #define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h deleted file mode 100644 index 42d1f08..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-jenga.h +++ /dev/null @@ -1,265 +0,0 @@ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) -#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) -#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) - -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) - -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) -#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) - -/* Sensors & NFC*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) - -#define GPIO_GYRO_INT EXYNOS4_GPF0(3) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY0(1) -#define GPIO_NFC_SCL_18V EXYNOS4_GPZ(6) -#define GPIO_NFC_SDA_18V EXYNOS4_GPZ(5) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ - -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM4(5) -#define GPIO_MIC_BIAS_EN_00 EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4212_GPM4(6) -#define GPIO_SUB_MIC_BIAS_EN_00 EXYNOS4_GPF2(0) -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPM4(7) -#define GPIO_EAR_MIC_BIAS_EN_00 EXYNOS4212_GPJ0(2) - - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) - -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) - -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - -#define GPIO_BT_EN EXYNOS4_GPL0(6) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) - -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) - -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) - -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) -#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) - -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) - - -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) - -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) - -/* Modem Interface GPIOs - M0 HSIC */ -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) -#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_CP_RST EXYNOS4_GPX3(2) - -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_INT EXYNOS4_GPX1(3) - -#endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h index 13fdb3d..cd778f2 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0.h @@ -20,8 +20,8 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_PMIC_SDA EXYNOS4_GPB(2) #define GPIO_PMIC_SCL EXYNOS4_GPB(3) -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) #define GPIO_ADC_INT EXYNOS4_GPX2(4) /* rev0.0, 0.1 */ #define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) @@ -71,6 +71,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4_GPC1(1) #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h index 2b36a60..e8cc1aa 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0ctc.h @@ -16,8 +16,8 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_PMIC_SDA EXYNOS4_GPB(2) #define GPIO_PMIC_SCL EXYNOS4_GPB(3) -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) #define GPIO_ADC_INT EXYNOS4_GPX2(4) #define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) @@ -52,8 +52,10 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ACC_INT EXYNOS4_GPX0(0) #define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#if !defined(CONFIG_MACH_M0_DUOSCTC) #define GPIO_GPS_nRST EXYNOS4_GPL2(1) #define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +#endif #define GPIO_GYRO_INT EXYNOS4_GPF0(3) #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) @@ -62,6 +64,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPM4(4) +#endif #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) @@ -83,7 +88,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) #define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) - +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(3) +#endif #define GPIO_PMU_RST EXYNOS4_GPX3(2) #define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) @@ -166,7 +173,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ISP_TXD EXYNOS4212_GPM4(5) #define GPIO_ISP_RXD EXYNOS4212_GPM4(6) +#if !defined(CONFIG_MACH_M0_DUOSCTC) #define GPIO_TA_EN EXYNOS4_GPL2(2) +#endif #define GPIO_MHL_SEL EXYNOS4_GPL0(3) @@ -183,7 +192,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FUEL_SDA EXYNOS4_GPF1(5) #define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#else #define GPIO_UART_SEL EXYNOS4_GPF2(3) +#endif #define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) #define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) #define GPIO_OLED_DET EXYNOS4_GPF3(0) @@ -241,11 +254,17 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) #define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) - +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_FM_RST EXYNOS4_GPC1(0) +#define GPIO_FM_INT_REV15 EXYNOS4_GPX0(4) +#define GPIO_FM_INT_REV07 EXYNOS4_GPX0(4) +#define GPIO_FM_INT EXYNOS4_GPX0(4) +#else #define GPIO_FM_RST EXYNOS4_GPC1(1) #define GPIO_FM_INT_REV15 EXYNOS4_GPX1(3) #define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) #define GPIO_FM_INT EXYNOS4_GPX1(3) +#endif #define GPIO_FM_MIC_SW EXYNOS4_GPL0(3) /* Definitions for DPRAM */ @@ -269,10 +288,16 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) + +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_USB_HUB_CONNECT EXYNOS4_GPF1(0) /* dummy */ +#define GPIO_USB_BOOT_EN EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL EXYNOS4_GPF1(1) +#else #define GPIO_USB_HUB_CONNECT EXYNOS4212_GPV3(5) #define GPIO_USB_BOOT_EN EXYNOS4212_GPV3(7) - #define GPIO_BOOT_SW_SEL EXYNOS4212_GPV3(6) +#endif /* for revesion 06 higher */ #define GPIO_USB_BOOT_EN_REV06 EXYNOS4_GPF2(2) @@ -280,6 +305,7 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) #define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) #define GPIO_CP_MSM_RST EXYNOS4_GPL2(4) @@ -287,10 +313,20 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) #define GPIO_MSM_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ +#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) #define GPIO_MSM_DPRAM_INT EXYNOS4_GPX2(0) -#define MSM_DPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ - +#define MSM_DPRAM_INT_IRQ IRQ_EINT(16) + +#if defined(CONFIG_MACH_M0_DUOSCTC) +#define GPIO_CP2_MSM_PWRON EXYNOS4_GPL2(2) +#define GPIO_CP2_MSM_RST EXYNOS4_GPL2(1) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) + +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(4) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(12) +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX3(5) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(29) +#endif #endif /* __MACH_GPIO_C1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h index e5c96b4..17d9586 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m0grandectc.h @@ -19,7 +19,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) #define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) +#if defined(CONFIG_MACH_GRANDE) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPJ0(1) +#else #define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) +#endif #define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) @@ -29,10 +33,28 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) -#define GPIO_ACC_INT EXYNOS4_GPX0(0) +/* keys */ +#define GPIO_KBR_0 EXYNOS4_GPX2(2) +#define GPIO_KBR_1 EXYNOS4_GPX2(4) +#define GPIO_KBR_2 EXYNOS4_GPX3(0) +#define GPIO_KBR_3 EXYNOS4_GPX3(3) +#define GPIO_KBR_4 EXYNOS4_GPX3(4) -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#define GPIO_KBC_0 EXYNOS4_GPL2(3) +#define GPIO_KBC_1 EXYNOS4_GPL2(4) +#define GPIO_KBC_2 EXYNOS4_GPL2(5) +#define GPIO_KBC_3 EXYNOS4_GPL2(6) +#define GPIO_KBC_4 EXYNOS4_GPL2(7) + + +/* Sensors & NFC*/ +#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) +#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPF0(0) +#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPF0(1) +#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) +#define GPIO_ACC_INT EXYNOS4_GPX0(0) +#define GPIO_GYRO_DE EXYNOS4_GPL2(0) #define GPIO_GYRO_INT EXYNOS4_GPF0(3) #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) #define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) @@ -40,14 +62,16 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) #define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) #define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#define GPIO_MSENSE_RST_N EXYNOS4212_GPM4(4) #define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) #define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) - +#define GPIO_3G_DET EXYNOS4_GPX0(6) #define GPIO_TF_EN EXYNOS4_GPY2(0) #define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) #define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(3) #define GPIO_PMU_RST EXYNOS4_GPX3(2) @@ -55,8 +79,12 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) #define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_EN EXYNOS4_GPL0(3) + #define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) #define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_HALL_SW EXYNOS4_GPX3(7) + #define GPIO_BT_EN EXYNOS4_GPL0(6) #define GPIO_BT_WAKE EXYNOS4_GPX3(1) @@ -93,6 +121,11 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_FLM_TXD EXYNOS4_GPA1(5) #define GPIO_FLM_TXD_AF 2 +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) +#define GPIO_3_TOUCH_EN EXYNOS4_GPC1(0) + #define GPIO_PWM0 EXYNOS4_GPD0(0) #define GPIO_PWM1 EXYNOS4_GPD0(1) #define GPIO_PWM2 EXYNOS4_GPD0(2) @@ -133,18 +166,29 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_LCD_SEL EXYNOS4_GPF2(6) #define GPIO_LCD_OE EXYNOS4_GPF2(7) +#define GPIO_TSP_SEL EXYNOS4_GPF2(7) #define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) #define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#if defined(CONFIG_REGULATOR_LP8720) +#define GPIO_FOLDER_PMIC_EN EXYNOS4_GPL0(4) +#define GPIO_FOLDER_PMIC_SDA EXYNOS4_GPF0(4) +#define GPIO_FOLDER_PMIC_SCL EXYNOS4_GPF0(6) + +#if defined(CONFIG_MACH_GRANDE) +#define GPIO_SUB_PMIC_EN EXYNOS4_GPF0(2) +#define GPIO_SUB_PMIC_SDA EXYNOS4_GPF0(7) +#define GPIO_SUB_PMIC_SCL EXYNOS4_GPF1(0) +#endif +#endif + /* Definitions for Sii 9244B0 */ #define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) #define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) #define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) #define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_VOL_UP EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) #define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) #define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) @@ -156,13 +200,14 @@ extern void midas_config_sleep_gpio_table(void); #define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) #define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_UP EXYNOS4_GPX1(3) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(5) +#define GPIO_HOLD EXYNOS4_GPX0(5) #define GPIO_OK_KEY EXYNOS4_GPX3(5) #define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) /*system_rev == 11*/ #define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3) /*system_rev >= 15*/ #define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - #define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) #define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) @@ -187,26 +232,27 @@ extern void midas_config_sleep_gpio_table(void); /* Definitions for CMC221 */ #define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) #define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_AP_CP_INT EXYNOS4_GPF2(2) +/* #define GPIO_AP_CP_INT EXYNOS4_GPF2(2) */ #define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) #define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) #define GPIO_USB_HUB_CONNECT EXYNOS4212_GPV3(5) -#define GPIO_USB_BOOT_EN EXYNOS4212_GPV3(7) +#define GPIO_USB_BOOT_EN EXYNOS4_GPF2(2) -#define GPIO_BOOT_SW_SEL EXYNOS4212_GPV3(6) +#define GPIO_BOOT_SW_SEL EXYNOS4_GPF2(5) /* for revesion 06 higher */ -#define GPIO_USB_BOOT_EN_REV06 EXYNOS4212_GPV3(7) -#define GPIO_BOOT_SW_SEL_REV06 EXYNOS4212_GPV3(6) +#define GPIO_USB_BOOT_EN_REV06 EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL_REV06 EXYNOS4_GPF2(5) #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) -#define GPIO_CP_MSM_RST EXYNOS4_GPL2(4) +#define GPIO_CP_MSM_PWRON EXYNOS4212_GPM1(1) +#define GPIO_CP_MSM_RST EXYNOS4_GPL2(1) #define GPIO_CP_MSM_PMU_RST EXYNOS4_GPX3(2) #define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) @@ -216,12 +262,28 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_MSM_DPRAM_INT EXYNOS4_GPX2(0) #define MSM_DPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ -#define GPIO_CP2_MSM_PWRON EXYNOS4_GPL2(1) -#define GPIO_CP2_MSM_RST EXYNOS4_GPL2(2) - -/* DUMP GPIOS */ +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(6) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(5) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(4) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(12) +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX1(7) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(15) + +#if defined(CONFIG_SIM_DETECT) +#define GPIO_CP_SIM_DETECT EXYNOS4_GPX0(1) +#define CP_SIM_DETECT_IRQ IRQ_EINT(1) +#define GPIO_ESC_SIM_DETECT EXYNOS4_GPX3(6) +#define ESC_SIM_DETECT_IRQ IRQ_EINT(30) +#endif + +/* DUMMY GPIOS */ #define GPIO_HDMI_HPD EXYNOS4_GPA1(4) #define GPIO_HDMI_EN EXYNOS4_GPA1(4) #define GPIO_V_BUS_INT EXYNOS4_GPA1(4) +#if defined(CONFIG_SIM_SLOT_SWITCH) +#define GPIO_UIM_SIM_SEL EXYNOS4212_GPM0(7) +#endif + #endif /* __MACH_GPIO_C1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h index cd3bc9c..1e7626c 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-m3.h @@ -1,291 +1,264 @@ -#ifndef __MACH_GPIO_M3_H -#define __MACH_GPIO_M3_H __FILE__ +#ifndef __MACH_GPIO_C2_H +#define __MACH_GPIO_C2_H __FILE__ + #include <mach/gpio.h> extern void midas_config_gpio_table(void); extern void midas_config_sleep_gpio_table(void); -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYNOS4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYNOS4_GPC0(2) -#define GPIO_FM_I2S_DI EXYNOS4_GPC0(3) -#define GPIO_FM_I2S_DO EXYNOS4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) - -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) - -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) -#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) - -/* Sensors & NFC*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) - -#define GPIO_GYRO_INT EXYNOS4_GPF0(3) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY0(1) -#define GPIO_NFC_SCL_18V EXYNOS4_GPD1(1) -#define GPIO_NFC_SDA_18V EXYNOS4_GPD1(0) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ - -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) - -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) - -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - -#define GPIO_BT_EN EXYNOS4_GPL0(6) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) - -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) - -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) -#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) -#define GPIO_OLED_DET EXYNOS4_GPF3(0) - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) - -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) - -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) - -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) - -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) - -/* Definitions for DPRAM */ -#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) -#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) -#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) -#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) -#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) - -/* Definitions for CMC221 */ -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_AP_CP_INT EXYNOS4_GPF2(2) -#define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) -#define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) -#define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) -#define CP_CMC221_CPU_RST EXYNOS4_GPL2(4) -#define CP_CMC221_PMIC_PWRON EXYNOS4_GPL2(5) -#define GPIO_CMC2AP_INT1_18V EXYNOS4_GPX0(5) -#define GPIO_AP2CMC_DP_INT3_18V EXYNOS4_GPX3(2) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) - -#define GPIO_LTE_ACTIVE EXYNOS4_GPX1(6) -#define LTE_ACTIVE_IRQ IRQ_EINT(14) /* IRQ of GPX1[6] */ - -#define GPIO_CMC_IDPRAM_INT EXYNOS4_GPX2(0) -#define CMC_IDPRAM_INT_IRQ IRQ_EINT(16) /* IRQ of GPX2[0] */ - -#define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) - -#define GPIO_CMC2AP_STATUS EXYNOS4_GPX0(5) -#define GPIO_AP2CMC_WAKEUP EXYNOS4_GPX1(2) - -#define ACTIVE_STATE_HSIC EXYNOS4_GPF1(1) -#define MDM_LTE_ACTIVE EXYNOS4_GPF2(0) -#define PDA_ACTIVE EXYNOS4_GPF1(6) -#define AP2MDM_PMIC_RESET_N EXYNOS4_GPL2(4) -#define MDM2AP_STATUS EXYNOS4212_GPM1(1) -#define AP2MDM_STATUS EXYNOS4212_GPM2(4) -#define MDM2AP_HSIC_READY EXYNOS4_GPX0(4) -#define AP2MDM_HSIC_READY EXYNOS4_GPX0(5) -#define AP2MDM_ERRFATAL EXYNOS4_GPX1(0) -#define MDM2AP_ERRFATAL EXYNOS4_GPX1(1) -#define MDM_DUMP_INT EXYNOS4_GPX1(2) - -#endif /* __MACH_GPIO_M3_H */ +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_RTS EXYNOS4_GPA0(3) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPA0(6) +#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPA0(7) +#else +#define GPIO_NFC_SDA_18V EXYNOS4_GPA0(6) +#define GPIO_NFC_SCL_18V EXYNOS4_GPA0(7) +#endif + +#define GPIO_AP_RXD_18V EXYNOS4_GPA1(0) +#define GPIO_AP_TXD_18V EXYNOS4_GPA1(1) +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) + +#define GPIO_CODEC_SDA_18V EXYNOS4_GPB(0) +#define GPIO_CODEC_SCL_18V EXYNOS4_GPB(1) +#define GPIO_MHL_DSDA_18V EXYNOS4_GPB(2) +#define GPIO_MHL_DSCL_18V EXYNOS4_GPB(3) +#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) +#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) +#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) +#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) + +#define GPIO_LCD_22V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 GPIO_LCD_22V_EN + +#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(0) +#define GPIO_MODEM_BOOT_MODE EXYNOS4_GPD0(1) +#define GPIO_PMIC_SDA EXYNOS4_GPD0(2) +#define GPIO_PMIC_SCL EXYNOS4_GPD0(3) + +#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(0) +#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(1) +#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) +#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) + +#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) +#define GPIO_GYRO_INT EXYNOS4_GPF0(3) +#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) +#define GPIO_BARO_INT EXYNOS4_GPF0(5) +#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) +#define GPIO_OTG_EN EXYNOS4_GPF0(7) + +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) + +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) + +#define GPIO_OLED_DET EXYNOS4_GPF3(0) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) + +#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) +#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) +#define GPIO_WM8994_LDO GPIO_CODEC_LDO_EN +#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) +#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) + +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) +#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) + +#define GPIO_NAND_CLK EXYNOS4_GPK0(0) +#define GPIO_NAND_CMD EXYNOS4_GPK0(1) +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) +#define GPIO_NAND_D0 EXYNOS4_GPK0(3) +#define GPIO_NAND_D1 EXYNOS4_GPK0(4) +#define GPIO_NAND_D2 EXYNOS4_GPK0(5) +#define GPIO_NAND_D3 EXYNOS4_GPK0(6) + +#define GPIO_NAND_D4 EXYNOS4_GPK1(3) +#define GPIO_NAND_D5 EXYNOS4_GPK1(4) +#define GPIO_NAND_D6 EXYNOS4_GPK1(5) +#define GPIO_NAND_D7 EXYNOS4_GPK1(6) + +#define GPIO_T_FLASH_CLK EXYNOS4_GPK2(0) +#define GPIO_T_FLASH_CMD EXYNOS4_GPK2(1) +#define GPIO_T_FLASH_D0 EXYNOS4_GPK2(3) +#define GPIO_T_FLASH_D1 EXYNOS4_GPK2(4) +#define GPIO_T_FLASH_D2 EXYNOS4_GPK2(5) +#define GPIO_T_FLASH_D3 EXYNOS4_GPK2(6) + +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) + +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#ifdef CONFIG_TARGET_LOCALE_EUR +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) +#endif +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_BT_EN EXYNOS4_GPL0(6) + +#define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_LED_VDD_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_EN GPIO_LED_VDD_EN +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) +#else +#define GPIO_LED_VDD_EN EXYNOS4212_GPM0(0) +#define GPIO_3_TOUCH_EN GPIO_LED_VDD_EN +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#endif + +#define GPIO_HW_REV0 EXYNOS4212_GPM1(2) +#define GPIO_HW_REV1 EXYNOS4212_GPM1(3) +#define GPIO_HW_REV2 EXYNOS4212_GPM1(4) +#define GPIO_HW_REV3 EXYNOS4212_GPM1(5) +#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) + +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) +#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) + +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) + +#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) +#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) + +#define GPIO_ACC_INT EXYNOS4_GPX0(0) +#define GPIO_OK_KEY EXYNOS4_GPX0(1) +#define GPIO_RGB_INT_N EXYNOS4_GPX0(2) +#define GPIO_PS_ALS_INT GPIO_RGB_INT_N +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) + +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) + +#define GPIO_VOL_UP EXYNOS4_GPX2(2) +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) +#else +#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) +#endif + +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) +#define GPIO_nPOWER EXYNOS4_GPX2(7) + +#define GPIO_WPC_INT EXYNOS4_GPX3(0) +#define GPIO_BT_WAKE EXYNOS4_GPX3(1) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) +#define GPIO_T_FLASH_DETECT EXYNOS4_GPX3(4) +#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + +#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY1(0) +#define GPIO_BENSE_SCL_18V EXYNOS4_GPY1(1) + +#define GPIO_TF_EN EXYNOS4_GPY2(0) +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4_GPY2(3) + +#if defined(CONFIG_MACH_M3_JPN_DCM) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) +#else +#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) +#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +#endif + +#define GPIO_MM_I2S_CLK EXYNOS5_GPZ(0) +#define GPIO_MM_I2S_SYNC EXYNOS5_GPZ(2) +#define GPIO_MM_I2S_DI EXYNOS5_GPZ(3) +#define GPIO_MM_I2S_DO EXYNOS5_GPZ(4) + + +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_HOST_WAKE_AF 0xF +#define GPIO_WLAN_SDIO_CLK_AF 2 +#define GPIO_WLAN_SDIO_CMD_AF 2 +#define GPIO_WLAN_SDIO_D0_AF 2 +#define GPIO_WLAN_SDIO_D1_AF 2 +#define GPIO_WLAN_SDIO_D2_AF 2 +#define GPIO_WLAN_SDIO_D3_AF 2 + +#define IRQ_BT_HOST_WAKE IRQ_EINT(22) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) + +#if defined(CONFIG_FELICA) +#define FELICA_GPIO_I2C_SDA EXYNOS4_GPY2(4) +#define FELICA_GPIO_I2C_SCL EXYNOS4_GPY2(5) +#define FELICA_UART3RX EXYNOS4_GPA1(4) +#define FELICA_GPIO_RFS EXYNOS4_GPL2(6) +#define FELICA_GPIO_PON EXYNOS4_GPL2(7) +#define FELICA_GPIO_INT EXYNOS4_GPX1(7) +#endif + +#if defined(CONFIG_ISDBT) +#define GPIO_ISDBT_RST_N EXYNOS4_GPC0(0) +#define GPIO_ISDBT_EN EXYNOS4_GPC0(2) +#define GPIO_ISDBT_INT EXYNOS4_GPC0(4) +#define GPIO_ISDBT_IRQ gpio_to_irq(GPIO_ISDBT_INT) +#define GPIO_ISDBT_INT_AF 0xf +#define GPIO_ISDBT_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_ISDBT_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_ISDBT_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_ISDBT_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +#endif /* __MACH_GPIO_C2_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h deleted file mode 100644 index b5dc8a7..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4note.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) -#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) -#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) - -#define GPIO_3M_nRST EXYNOS4_GPL1(1) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) -#define GPIO_3M_nSTBY EXYNOS4212_GPM0(6) -#define GPIO_2M_nRST EXYNOS4212_GPM1(6) - -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) - -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_2M_nSTBY EXYNOS4212_GPM4(3) -#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) - -/* 30pin Accessory */ -/* -#define GPIO_ACCESSORY_CHECK EXYNOS4_GPE0(4) -#define GPIO_ACCESSORY_EN EXYNOS4_GPL2(6) -#define GPIO_ACCESSORY_OUT_5V EXYNOS4_GPY4(4) -*/ -#define GPIO_ACCESSORY_INT EXYNOS4_GPX1(3) -#define GPIO_DOCK_INT EXYNOS4_GPX0(4) - -/* Sensors & NFC*/ -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPL0(2) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPL0(1) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) - -#define GPIO_GYRO_INT EXYNOS4_GPX0(6) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - -#define GPIO_MSENSOR_INT EXYNOS4212_GPM4(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) - -#define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_NFC_SCL_18V EXYNOS4_GPZ(6) -#define GPIO_NFC_SDA_18V EXYNOS4_GPZ(5) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(6) /*tmp*/ -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ - -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM0(0) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) -#define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) - -#define GPIO_PMU_RST EXYNOS4_GPX3(2) - -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) - -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) -#define GPIO_TSP_LDO_ON EXYNOS4_GPL0(3) -#define GPIO_TSP_RST EXYNOS4_GPL0(5) - -#define GPIO_PEN_PDCT_18V EXYNOS4_GPC1(0) -#define GPIO_PEN_LDO_EN EXYNOS4_GPC1(1) -#define GPIO_PEN_IRQ_18V EXYNOS4_GPC1(2) -#define GPIO_PEN_SDA_28V EXYNOS4_GPC1(3) -#define GPIO_PEN_SCL_28V EXYNOS4_GPC1(4 - -#define GPIO_BT_EN EXYNOS4_GPL0(6) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_3_TOUCH_SCL EXYNOS4212_GPM0(0) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL2(3) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4_GPC1(3) -#define GPIO_TOUCH_EN EXYNOS4212_GPJ0(3) - -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) - -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) - -#define GPIO_WLAN_EN EXYNOS4212_GPM3(5) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_USB_SEL0 EXYNOS4_GPY0(4) -#define GPIO_USB_SEL1 EXYNOS4_GPY0(5) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) - -/* charger */ -#define GPIO_CHG_SDA EXYNOS4212_GPM2(0) -#define GPIO_CHG_SCL EXYNOS4212_GPM2(1) -#define GPIO_TA_EN EXYNOS4_GPY1(3) -#define GPIO_TA_nCHG EXYNOS4_GPL2(1) -#define GPIO_TA_nCONNECTED EXYNOS4_GPX1(4) - -/* adc */ -#define GPIO_ADC_SCL EXYNOS4212_GPM4(0) -#define GPIO_ADC_SDA EXYNOS4212_GPM4(1) -#define GPIO_ADC_INT EXYNOS4_GPX0(1) - -/* fuelgauge */ -#define GPIO_FUEL_SCL EXYNOS4_GPY0(3) -#define GPIO_FUEL_SDA EXYNOS4_GPY0(2) -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_IF_CON_SENSE EXYNOS4_GPY4(3) - -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPL2(7) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) -#define GPIO_OLED_DET EXYNOS4_GPF3(0) - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPX2(4) -#define GPIO_BUCK3_SEL EXYNOS4_GPX2(0) -#define GPIO_BUCK4_SEL EXYNOS4_GPX2(1) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) - -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) /* rev0.9 ~ */ -#define GPIO_WPC_INT EXYNOS4_GPX3(0) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) - - -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPM4(4) -#define GPIO_WM8994_LDO EXYNOS4212_GPM4(4) - -/* Modem Interface GPIOs - M0 HSIC */ -#if !defined(CONFIG_SEC_MODEM_M0_TD) -#define GPIO_ACTIVE_STATE EXYNOS4_GPL0(0) -#define GPIO_PDA_ACTIVE EXYNOS4_GPL1(0) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) -#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_CP_RST EXYNOS4_GPX3(2) - -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#else - -/* Modem Interface GPIOs - M0 SPI */ -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_AP_CP_INT1 EXYNOS4_GPX0(5) -#define GPIO_AP_CP_INT2 EXYNOS4_GPX3(5) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_IPC_MRDY EXYNOS4_GPX0(4) -#define GPIO_IPC_SRDY EXYNOS4_GPX1(0) -#define GPIO_IPC_SUB_MRDY EXYNOS4_GPX3(2) -#define GPIO_IPC_SUB_SRDY EXYNOS4_GPX1(1) - -#define GPIO_CP_RST EXYNOS4_GPF1(1) -#define GPIO_CP_REQ_RESET EXYNOS4_GPF1(1) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_SUSPEND_REQUEST EXYNOS4_GPF1(1) -#define GPIO_ISP_INT EXYNOS4_GPF1(1) -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) - -#define GPIO_FM_RST EXYNOS4_GPC1(0) - -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_PHONE_ACTIVE IRQ_EINT14 -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_IPC_SUB_SRDY IRQ_EINT9 -#define IRQ_CP_DUMP_INT IRQ_EINT10 -#endif - -#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX1(3) - -#define GPIO_FM_INT_REV15 EXYNOS4_GPX1(4) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_MIC_SW EXYNOS4_GPL0(3) - -#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) -#define GPIO_TDMB_EN EXYNOS4_GPL0(0) -#define GPIO_TDMB_INT EXYNOS4_GPF0(2) -#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) -#define GPIO_TDMB_INT_AF 0xf -#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) -#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) -#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) -#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) -#endif - -#if defined(CONFIG_FB_S5P_S6C1372) -#define GPIO_LCD_EN EXYNOS4_GPC0(1) -#define GPIO_LED_BACKLIGHT_PWM EXYNOS4_GPD0(1) -#define GPIO_LED_BACKLIGHT_RESET EXYNOS4212_GPM0(1) -#define GPIO_LVDS_NSHDN EXYNOS4212_GPM0(5) -#endif - -#endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h index 3c62331..c44ac94 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-p4notepq.h @@ -74,8 +74,10 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_PS_ALS_SCL_28V EXYNOS4_GPL0(1) #define GPIO_GYRO_DE EXYNOS4_GPL2(0) +#if !defined(CONFIG_QC_MODEM) #define GPIO_GPS_nRST EXYNOS4_GPL2(1) #define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +#endif #define GPIO_GYRO_INT EXYNOS4_GPX0(6) #define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) @@ -147,13 +149,19 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) #define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) #define GPIO_TSP_LDO_ON EXYNOS4212_GPM4(5) -#define GPIO_TSP_RST EXYNOS4_GPL0(5) +#define GPIO_TSP_RST EXYNOS4212_GPM0(4) +#define GPIO_TSP_LDO_ON1 EXYNOS4_GPB(5) +#define GPIO_TSP_LDO_ON2 EXYNOS4_GPB(7) #define GPIO_PEN_PDCT_18V EXYNOS4_GPC1(0) #define GPIO_PEN_LDO_EN EXYNOS4_GPC1(1) #define GPIO_PEN_IRQ_18V EXYNOS4_GPC1(2) #define GPIO_PEN_SDA_28V EXYNOS4_GPC1(3) #define GPIO_PEN_SCL_28V EXYNOS4_GPC1(4) +#define GPIO_S_PEN_IRQ EXYNOS4_GPX1(5) +#if defined(CONFIG_QC_MODEM) +#define GPIO_PEN_FWE0 EXYNOS4_GPA0(5) +#endif #define GPIO_nPOWER EXYNOS4_GPX2(7) #define GPIO_VOL_DOWN EXYNOS4_GPX2(2) @@ -187,7 +195,14 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_ISP_TXD EXYNOS4212_GPM4(5) #define GPIO_ISP_RXD EXYNOS4212_GPM4(6) +#if defined(CONFIG_IR_REMOCON_GPIO) #define GPIO_IRDA_CONTROL EXYNOS4_GPL0(3) +#elif defined(CONFIG_IR_REMOCON_MC96) +#define GPIO_IRDA_WAKE EXYNOS4_GPL0(3) +#define GPIO_IRDA_IRQ EXYNOS4_GPM0(6) +#define GPIO_IRDA_SDA EXYNOS4_GPY0(0) +#define GPIO_IRDA_SCL EXYNOS4_GPY0(1) +#endif #define GPIO_MHL_SDA_1_8V EXYNOS4_GPY2(2) #define GPIO_MHL_SCL_1_8V EXYNOS4_GPY2(3) @@ -201,6 +216,9 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_USB_SEL1 EXYNOS4_GPY0(5) #define GPIO_USB_SEL_CP EXYNOS4212_GPM0(7) #define GPIO_UART_SEL EXYNOS4_GPL2(7) +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) +#define GPIO_UART_SEL2 EXYNOS4212_GPJ0(0) +#endif /* charger */ #define GPIO_CHG_SDA EXYNOS4212_GPM2(0) @@ -231,9 +249,15 @@ extern void midas_config_sleep_gpio_table(void); /* Definitions for Sii 9244B0 */ #define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#if !defined(CONFIG_QC_MODEM) #define GPIO_BUCK2_SEL EXYNOS4_GPX2(4) #define GPIO_BUCK3_SEL EXYNOS4_GPX2(0) #define GPIO_BUCK4_SEL EXYNOS4_GPX2(1) +#else +#define GPIO_BUCK2_SEL EXYNOS4_GPL2(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPL2(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPX2(4) +#endif #define GPIO_MHL_RST EXYNOS4_GPF3(4) #define GPIO_MHL_INT EXYNOS4_GPF3(5) #define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) @@ -333,4 +357,26 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_LVDS_NSHDN EXYNOS4212_GPM0(5) #endif +#if defined(CONFIG_QC_MODEM) +/* Modem Interface GPIOs - MDM */ +#define GPIO_MODEM_BOOT_MODE EXYNOS4_GPD0(1) +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPL0(0) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPL1(0) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPC0(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPC0(0) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPC0(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4_GPC0(3) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4212_GPM3(4) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX2(0) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX2(1) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ +#endif + #endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h deleted file mode 100644 index 3423451..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-s2plus.h +++ /dev/null @@ -1,715 +0,0 @@ -#if 1 -/* - * Gpio-rev00-s2plus.h - * - * 2011. 12.21 Sexykyu - * - * S2Plus H/W REV00 Board Gpio Setup - * - */ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_DUMMP EXYNOS4212_GPM3(4) - -/*********************** GPA0 Block *********/ - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - - -/*********************** GPA1 Block *********/ -#define GPIO_AP_RXD EXYNOS4_GPA1(0) -#define GPIO_AP_TXD EXYNOS4_GPA1(1) - -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - - -/*********************** GPB Block *********/ - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPB(1) - -#define GPIO_NFC_SDA_18V EXYNOS4_GPB(2) -#define GPIO_NFC_SCL_18V EXYNOS4_GPB(3) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - -/*********************** GPC0 Block *********/ - -#define GPIO_REC_PCM_CLK EXYNOS4_GPC0(0) -#define GPIO_REC_PCM_SYNC EXYNOS4_GPC0(2) -#define GPIO_REC_PCM_IN EXYNOS4_GPC0(3) -#define GPIO_REC_PCM_OUT EXYNOS4_GPC0(4) - - -/*********************** GPC1 Block *********/ - -#define GPIO_FM_I2S_CLK EXYNOS4_GPC1(0) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_I2S_SYNC EXYNOS4_GPC1(2) -#define GPIO_FM_I2S_DI EXYNOS4_GPC1(3) -#define GPIO_FM_I2S_DO EXYNOS4_GPC1(4) - - -/*********************** GPD0 Block *********/ - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(0) -#define GPIO_PMIC_SDA EXYNOS4_GPD0(2) -#define GPIO_PMIC_SCL EXYNOS4_GPD0(3) - - -/*********************** GPD1 Block *********/ - -#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - - -/*********************** GPF0 Block *********/ -#define GPIO_LCD_HYNC EXYNOS4_GPF0(0) -#define GPIO_LCD_VSYNC EXYNOS4_GPF0(1) -#define GPIO_LCD_DE EXYNOS4_GPF0(2) -#define GPIO_LCD_PCLK EXYNOS4_GPF0(3) -#define GPIO_LCD_D_0 EXYNOS4_GPF0(4) -#define GPIO_LCD_D_1 EXYNOS4_GPF0(5) -#define GPIO_LCD_D_2 EXYNOS4_GPF0(6) -#define GPIO_LCD_D_3 EXYNOS4_GPF0(7) - - -/*********************** GPF1 Block *********/ -#define GPIO_LCD_D_4 EXYNOS4_GPF1(0) -#define GPIO_LCD_D_5 EXYNOS4_GPF1(1) -#define GPIO_LCD_D_6 EXYNOS4_GPF1(2) -#define GPIO_LCD_D_7 EXYNOS4_GPF1(3) -#define GPIO_LCD_D_8 EXYNOS4_GPF1(4) -#define GPIO_LCD_D_9 EXYNOS4_GPF1(5) -#define GPIO_LCD_D_10 EXYNOS4_GPF1(6) -#define GPIO_LCD_D_11 EXYNOS4_GPF1(7) - -/*********************** GPF2 Block *********/ -#define GPIO_LCD_D_12 EXYNOS4_GPF2(0) -#define GPIO_LCD_D_13 EXYNOS4_GPF2(1) -#define GPIO_LCD_D_14 EXYNOS4_GPF2(2) -#define GPIO_LCD_D_15 EXYNOS4_GPF2(3) -#define GPIO_LCD_D_16 EXYNOS4_GPF2(4) -#define GPIO_LCD_D_17 EXYNOS4_GPF2(5) -#define GPIO_LCD_D_18 EXYNOS4_GPF2(6) -#define GPIO_LCD_D_19 EXYNOS4_GPF2(7) - - -/*********************** GPF3 Block *********/ -#define GPIO_LCD_D_20 EXYNOS4_GPF3(0) -#define GPIO_LCD_D_21 EXYNOS4_GPF3(1) -#define GPIO_LCD_D_22 EXYNOS4_GPF3(2) -#define GPIO_LCD_D_23 EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) - - -/*********************** GPJ0 Block *********/ -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPJ0(2) -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) /*old name*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) - -/*********************** GPJ1 Block *********/ -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - - -/*********************** GPK0 Block *********/ -#define GPIO_NAND_CLK EXYNOS4_GPK0(0) -#define GPIO_NAND_CMD EXYNOS4_GPK0(1) -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) -#define GPIO_NAND_D_0 EXYNOS4_GPK0(3) -#define GPIO_NAND_D_1 EXYNOS4_GPK0(4) -#define GPIO_NAND_D_2 EXYNOS4_GPK0(5) -#define GPIO_NAND_D_3 EXYNOS4_GPK0(6) - - -/*********************** GPK1 Block *********/ -#define GPIO_NAND_D_4 EXYNOS4_GPK1(3) -#define GPIO_NAND_D_5 EXYNOS4_GPK1(4) -#define GPIO_NAND_D_6 EXYNOS4_GPK1(5) -#define GPIO_NAND_D_7 EXYNOS4_GPK1(6) - - -/*********************** GPK2 Block *********/ -#define GPIO_T_FLASH_CLK EXYNOS4_GPK2(0) -#define GPIO_T_FLASH_CMD EXYNOS4_GPK2(1) - -#define GPIO_T_FLASH_D_0 EXYNOS4_GPK2(3) -#define GPIO_T_FLASH_D_1 EXYNOS4_GPK2(4) -#define GPIO_T_FLASH_D_2 EXYNOS4_GPK2(5) -#define GPIO_T_FLASH_D_3 EXYNOS4_GPK2(6) - -/*********************** GPK3 Block *********/ -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -/*********************** GPL0 Block *********/ -#define GPIO_BUCK2_SEL EXYNOS4_GPL0(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPL0(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPL0(3) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_BT_EN EXYNOS4_GPL0(6) - -/*********************** GPL1 Block *********/ -#define GPIO_PS_ALS_SCL_18V EXYNOS4_GPL1(0) -#define GPIO_PS_ALS_SDA_18V EXYNOS4_GPL1(1) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPL1(0) -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPL1(1) - -/*********************** GPL2 Block *********/ -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) -#define GPIO_WLAN_WAKE EXYNOS4_GPL2(3) -#define GPIO_CHG_EN EXYNOS4_GPL2(4) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) - - -/*********************** GPM0 Block *********/ -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_VT_nSTBY EXYNOS4212_GPM0(5) -#define GPIO_TA_nCONNECTED EXYNOS4212_GPM0(6) -#define GPIO_CHG_ING_N EXYNOS4212_GPM0(7) - - -/*********************** GPM1 Block *********/ -#define GPIO_HW_REV0 EXYNOS4212_GPM1(2) -#define GPIO_HW_REV1 EXYNOS4212_GPM1(3) -#define GPIO_HW_REV2 EXYNOS4212_GPM1(4) -#define GPIO_HW_REV3 EXYNOS4212_GPM1(5) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - - -/*********************** GPM2 Block *********/ - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_TP_VT_CAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) - - -/*********************** GPM3 Block *********/ -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) - - -/*********************** GPM4 Block *********/ -#define GPIO_3_TOUCH_SCL EXYNOS4212_GPM4(0) -#define GPIO_3_TOUCH_SDA EXYNOS4212_GPM4(1) -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM4(5) -#define GPIO_MIC_BIAS_EN_00 EXYNOS4212_GPM4(5) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4212_GPM4(6) -#define GPIO_SUB_MIC_BIAS_EN_00 EXYNOS4212_GPM4(6) - - -/*********************** GPX0 Block *********/ -#define GPIO_ACC_INT EXYNOS4_GPX0(0) -#define GPIO_DET_35 EXYNOS4_GPX0(1) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) -#define GPIO_GYRO_INT EXYNOS4_GPX0(4) -#define GPIO_OLED_DET EXYNOS4_GPX0(5) -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) - - -/*********************** GPX1 Block *********/ -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) /*old name*/ -#define GPIO_BARO_INT EXYNOS4_GPX1(4) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) - - -/*********************** GPX2 Block *********/ -#define GPIO_VOL_UP GPIO_DUMMP -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define GPIO_nPOWER EXYNOS4_GPX2(7) - - - -/*********************** GPX3 Block *********/ -#define GPIO_ISP_INT EXYNOS4_GPX3(0) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_CP_RST EXYNOS4_GPX3(2) -#define GPIO_VOL_DOWN GPIO_DUMMP -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) -#define GPIO_T_FLASH_DETECT EXYNOS4_GPX3(4) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) -#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -/*********************** GPY0 Block *********/ -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) - -/*********************** GPY2 Block *********/ -#define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BSENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - - -/*********************** GPY3 Block *********/ - -#define GPIO_MHL_SDA_1_8V EXYNOS4_GPY3(0) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_LCD_SCLK EXYNOS4_GPY3(1) -#define GPIO_MHL_SCL_1_8V EXYNOS4_GPY3(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) -#define GPIO_LCD_SDI EXYNOS4_GPY3(3) -#define GPIO_OLED_ID EXYNOS4_GPY3(4) -#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) -#define GPIO_ISP_RESET EXYNOS4_GPY3(7) - - -/*********************** GPY4 Block *********/ -#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) -#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) -#define GPIO_LCD_nCS EXYNOS4_GPY4(3) -#define GPIO_3_TOUCH_EN EXYNOS4_GPY4(4) -#define GPIO_MLCD_RST EXYNOS4_GPY4(5) -#define GPIO_MHL_SEL EXYNOS4_GPY4(6) -#define GPIO_UART_SEL EXYNOS4_GPY4(7) - - -/****************** DUMMP ********************/ -#define GPIO_MHL_DSDA_2_8V GPIO_DUMMP -#define GPIO_MHL_DSCL_2_8V GPIO_DUMMP -#define GPIO_WPC_INT GPIO_DUMMP -#define GPIO_OTG_EN GPIO_DUMMP /*don't used pin*/ -#define GPIO_CAM_IO_EN GPIO_DUMMP -#define GPIO_VTCAM_MCLK GPIO_DUMMP -#define GPIO_CAM_AF_EN GPIO_DUMMP -#define GPIO_FLM_RXD GPIO_DUMMP -#define GPIO_FLM_RXD_AF 2 -#define GPIO_FLM_TXD GPIO_DUMMP -#define GPIO_FLM_TXD_AF 2 -#define GPIO_GPS_CNTL GPIO_DUMMP -#define GPIO_PS_ALS_SDA_28V GPIO_DUMMP -#define GPIO_PS_ALS_SCL_28V GPIO_DUMMP -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - - - -#endif /* __MACH_GPIO_MIDAS_H */ - -#else - -/* linux/arch/arm/mach-exynos/include/mach/gpio-exynos4.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S2Plus GPIO common lib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef __MACH_GPIO_MIDAS_H -#define __MACH_GPIO_MIDAS_H __FILE__ - -#include <mach/gpio.h> - -extern void midas_config_gpio_table(void); -extern void midas_config_sleep_gpio_table(void); - -#define GPIO_DUMMP EXYNOS4212_GPM3(4) - - -#define GPIO_BT_RXD EXYNOS4_GPA0(0) -#define GPIO_BT_RXD_AF 2 - -#define GPIO_BT_TXD EXYNOS4_GPA0(1) -#define GPIO_BT_TXD_AF 2 - -#define GPIO_BT_CTS EXYNOS4_GPA0(2) -#define GPIO_BT_CTS_AF 2 - -#define GPIO_BT_RTS EXYNOS4_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD EXYNOS4_GPA0(4) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(5) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - - -#define GPIO_AP_RXD EXYNOS4_GPA1(0) -#define GPIO_AP_TXD EXYNOS4_GPA1(1) - -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) - - - -#define GPIO_CODEC_SDA_18V EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPB(1) - -#define GPIO_NFC_SDA_18V EXYNOS4_GPB(2) -#define GPIO_NFC_SCL_18V EXYNOS4_GPB(3) - -#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) -#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) -#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) -#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) - - -#define GPIO_REC_PCM_CLK EXYNOS4_GPC0(0) -#define GPIO_REC_PCM_SYNC EXYNOS4_GPC0(2) -#define GPIO_REC_PCM_IN EXYNOS4_GPC0(3) -#define GPIO_REC_PCM_OUT EXYNOS4_GPC0(4) - - - -#define GPIO_FM_I2S_CLK EXYNOS4_GPC1(0) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#define GPIO_FM_I2S_SYNC EXYNOS4_GPC1(2) -#define GPIO_FM_I2S_DI EXYNOS4_GPC1(3) -#define GPIO_FM_I2S_DO EXYNOS4_GPC1(4) - - - -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(0) -#define GPIO_PMIC_SDA EXYNOS4_GPD0(2) -#define GPIO_PMIC_SCL EXYNOS4_GPD0(3) - - - -#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) - - -#define GPIO_LCD_HYNC EXYNOS4_GPF0(0) -#define GPIO_LCD_VSYNC EXYNOS4_GPF0(1) -#define GPIO_LCD_DE EXYNOS4_GPF0(2) -#define GPIO_LCD_PCLK EXYNOS4_GPF0(3) -#define GPIO_LCD_D_0 EXYNOS4_GPF0(4) -#define GPIO_LCD_D_1 EXYNOS4_GPF0(5) -#define GPIO_LCD_D_2 EXYNOS4_GPF0(6) -#define GPIO_LCD_D_3 EXYNOS4_GPF0(7) - - -#define GPIO_LCD_D_4 EXYNOS4_GPF1(0) -#define GPIO_LCD_D_5 EXYNOS4_GPF1(1) -#define GPIO_LCD_D_6 EXYNOS4_GPF1(2) -#define GPIO_LCD_D_7 EXYNOS4_GPF1(3) -#define GPIO_LCD_D_8 EXYNOS4_GPF1(4) -#define GPIO_LCD_D_9 EXYNOS4_GPF1(5) -#define GPIO_LCD_D_10 EXYNOS4_GPF1(6) -#define GPIO_LCD_D_11 EXYNOS4_GPF1(7) - -#define GPIO_LCD_D_12 EXYNOS4_GPF2(0) -#define GPIO_LCD_D_13 EXYNOS4_GPF2(1) -#define GPIO_LCD_D_14 EXYNOS4_GPF2(2) -#define GPIO_LCD_D_15 EXYNOS4_GPF2(3) -#define GPIO_LCD_D_16 EXYNOS4_GPF2(4) -#define GPIO_LCD_D_17 EXYNOS4_GPF2(5) -#define GPIO_LCD_D_18 EXYNOS4_GPF2(6) -#define GPIO_LCD_D_19 EXYNOS4_GPF2(7) - - -#define GPIO_LCD_D_20 EXYNOS4_GPF3(0) -#define GPIO_LCD_D_21 EXYNOS4_GPF3(1) -#define GPIO_LCD_D_22 EXYNOS4_GPF3(2) -#define GPIO_LCD_D_23 EXYNOS4_GPF3(3) -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) - - -#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) -#define GPIO_WLAN_EN_AF 1 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4212_GPJ0(2) -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) -#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) - -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ1(0) -#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) -#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) - - -#define GPIO_NAND_CLK EXYNOS4_GPK0(0) -#define GPIO_NAND_CMD EXYNOS4_GPK0(1) -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) -#define GPIO_NAND_D_0 EXYNOS4_GPK0(3) -#define GPIO_NAND_D_1 EXYNOS4_GPK0(4) -#define GPIO_NAND_D_2 EXYNOS4_GPK0(5) -#define GPIO_NAND_D_3 EXYNOS4_GPK0(6) - - -#define GPIO_NAND_D_4 EXYNOS4_GPK1(3) -#define GPIO_NAND_D_5 EXYNOS4_GPK1(4) -#define GPIO_NAND_D_6 EXYNOS4_GPK1(5) -#define GPIO_NAND_D_7 EXYNOS4_GPK1(6) - - -#define GPIO_T_FLASH_CLK EXYNOS4_GPK2(0) -#define GPIO_T_FLASH_CMD EXYNOS4_GPK2(1) - -#define GPIO_T_FLASH_D_0 EXYNOS4_GPK2(3) -#define GPIO_T_FLASH_D_1 EXYNOS4_GPK2(4) -#define GPIO_T_FLASH_D_2 EXYNOS4_GPK2(5) -#define GPIO_T_FLASH_D_3 EXYNOS4_GPK2(6) - -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_BUCK2_SEL EXYNOS4_GPL0(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPL0(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPL0(3) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_BT_EN EXYNOS4_GPL0(6) - -#define GPIO_PS_ALS_SCL_18V EXYNOS4_GPL1(0) -#define GPIO_PS_ALS_SDA_18V EXYNOS4_GPL1(1) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPL1(0) -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPL1(1) - -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) -#define GPIO_WLAN_WAKE EXYNOS4_GPL2(3) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) - - -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_VT_nSTBY EXYNOS4212_GPM0(5) - - -#define GPIO_HW_REV0 EXYNOS4212_GPM1(2) -#define GPIO_HW_REV1 EXYNOS4212_GPM1(3) -#define GPIO_HW_REV2 EXYNOS4212_GPM1(4) -#define GPIO_HW_REV3 EXYNOS4212_GPM1(5) -#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) - - - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_TP_VT_CAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) - - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) - - -#define GPIO_3_TOUCH_SCL EXYNOS4212_GPM4(0) -#define GPIO_3_TOUCH_SDA EXYNOS4212_GPM4(1) -#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) -#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) - -#define GPIO_MIC_BIAS_EN EXYNOS4212_GPM4(5) -#define GPIO_MIC_BIAS_EN_00 EXYNOS4212_GPM4(5) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4212_GPM4(6) -#define GPIO_SUB_MIC_BIAS_EN_00 EXYNOS4212_GPM4(6) - - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) -#define GPIO_DET_35 EXYNOS4_GPX0(1) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) -#define GPIO_GYRO_INT EXYNOS4_GPX0(4) -#define GPIO_OLED_DET EXYNOS4_GPX0(5) -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) - - -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) -#define GPIO_BARO_INT EXYNOS4_GPX1(4) -#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) - - -#define GPIO_VOL_UP GPIO_DUMMP -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF -#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) -#define GPIO_nPOWER EXYNOS4_GPX2(7) - - - -#define GPIO_WPC_INT EXYNOS4_GPX3(0) -#define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_CP_RST EXYNOS4_GPX3(2) -#define GPIO_VOL_DOWN GPIO_DUMMP -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) -#define GPIO_T_FLASH_DETECT EXYNOS4_GPX3(4) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) -#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) - -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - - -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) - - -#define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) - - - -#define GPIO_MHL_SDA_1_8V GPIO_DUMMP -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPY3(0) -#define GPIO_LCD_SCLK EXYNOS4_GPY3(1) -#define GPIO_MHL_SCL_1_8V GPIO_DUMMP -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPY3(2) -#define GPIO_LCD_SDI EXYNOS4_GPY3(3) -#define GPIO_OLED_ID EXYNOS4_GPY3(4) -#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) -#define GPIO_ISP_RESET EXYNOS4_GPY3(7) - - -#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) -#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) -#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) -#define GPIO_LCD_nCS EXYNOS4_GPY4(3) -#define GPIO_3_TOUCH_EN EXYNOS4_GPY4(4) -#define GPIO_MLCD_RST EXYNOS4_GPY4(5) -#define GPIO_MHL_SEL EXYNOS4_GPY4(6) -#define GPIO_UART_SEL EXYNOS4_GPY4(7) - - - -#define GPIO_MHL_DSCL_2_8V GPIO_DUMMP -#define GPIO_MHL_DSDA_2_8V GPIO_DUMMP -#define GPIO_OTG_EN GPIO_DUMMP -#define GPIO_CAM_IO_EN GPIO_DUMMP -#define GPIO_VTCAM_MCLK GPIO_DUMMP -#define GPIO_CAM_AF_EN GPIO_DUMMP -#define GPIO_FLM_RXD GPIO_DUMMP -#define GPIO_FLM_RXD_AF 2 -#define GPIO_FLM_TXD GPIO_DUMMP -#define GPIO_FLM_TXD_AF 2 -#define GPIO_GPS_CNTL GPIO_DUMMP -#define GPIO_PS_ALS_SDA_28V GPIO_DUMMP -#define GPIO_PS_ALS_SCL_28V GPIO_DUMMP -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - - - -#endif /* __MACH_GPIO_MIDAS_H */ - -#endif diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h index 13fdb3d..2095f64 100644..100755 --- a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0.h @@ -6,102 +6,71 @@ extern void midas_config_gpio_table(void); extern void midas_config_sleep_gpio_table(void); -#define GPIO_eMMC_EN EXYNOS4_GPK0(2) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_FM_I2S_CLK EXYSNO4_GPC0(0) -#define GPIO_FM_I2S_SYNC EXYSNO4_GPC0(2) -#define GPIO_FM_I2S_DI EXYSNO4_GPC0(3) -#define GPIO_FM_I2S_DO EXYSNO4_GPC0(4) - -#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) -#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMIC_SDA EXYNOS4_GPB(2) -#define GPIO_PMIC_SCL EXYNOS4_GPB(3) +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); -#define GPIO_ADC_SCL EXYNOS4_GPY0(2) -#define GPIO_ADC_SDA EXYNOS4_GPY0(3) -#define GPIO_ADC_INT EXYNOS4_GPX2(4) /* rev0.0, 0.1 */ +/* Camera */ #define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) #define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) #define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) #define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) #define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) #define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) -#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(1) -#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(2) -#define GPIO_ISP_CORE_EN EXYNOS4212_GPM0(3) -#define GPIO_CAM_AF_EN EXYNOS4212_GPM0(4) +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) #define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#if 1 -#define GPIO_8M_CAM_SCL_18V EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4_GPD1(1) -#else -#define GPIO_8M_CAM_SCL_18V EXYNOS4212_GPM4(0) -#define GPIO_8M_CAM_SDA_18V EXYNOS4212_GPM4(1) -#define GPIO_8M_CAM_SCL_18V_00 EXYNOS4_GPD1(0) -#define GPIO_8M_CAM_SDA_18V_00 EXYNOS4_GPD1(1) -#endif - +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM4(1) #define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) #define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) #define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) -/* Sensors & NFC*/ -#define GPIO_PS_ALS_EN EXYNOS4212_GPJ0(5) -#define GPIO_PS_ALS_SDA_28V EXYNOS4_GPK1(1) -#define GPIO_PS_ALS_SCL_28V EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_ACC_INT EXYNOS4_GPX0(0) -#define GPIO_GYRO_DE EXYNOS4_GPL2(0) -#define GPIO_GPS_nRST EXYNOS4_GPL2(1) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +/* NFC */ +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) /* above rev0.1 */ +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) /* above rev0.1 */ -#define GPIO_GYRO_INT EXYNOS4_GPF0(3) -#define GPIO_GSENSE_SDA_18V EXYNOS4_GPD1(2) -#define GPIO_GSENSE_SCL_18V EXYNOS4_GPD1(3) -#define GPIO_MSENSOR_INT EXYNOS4212_GPJ0(7) -#define GPIO_MSENSOR_SDA_18V EXYNOS4_GPY2(4) -#define GPIO_MSENSOR_SCL_18V EXYNOS4_GPY2(5) +/* Sensor Hub */ +#define GPIO_MCU_AP_INT EXYNOS4_GPX0(0) +#define GPIO_AP_MCU_INT EXYNOS4_GPX0(2) +#define GPIO_MCU_AP_INT_2 EXYNOS4_GPX2(1) +#define GPIO_MCU_NRST EXYNOS4_GPY2(2) -#define GPIO_BENSE_SCL_18V EXYNOS4_GPY2(3) -#define GPIO_BSENSE_SDA_18V EXYNOS4_GPY2(2) -#define GPIO_BARO_INT EXYNOS4_GPF0(5) +/* PMIC */ +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) #define GPIO_TF_EN EXYNOS4_GPY2(0) -#define GPIO_NFC_SCL_18V EXYNOS4_GPZ(6) -#define GPIO_NFC_SDA_18V EXYNOS4_GPZ(5) -#define GPIO_NFC_SCL_18V_00 EXYNOS4_GPB(3) -#define GPIO_NFC_SDA_18V_00 EXYNOS4_GPB(2) -#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) -#define GPIO_NFC_CLK_REQ EXYNOS4212_GPM0(0) -/* Sensors & NFC*/ -#define GPIO_DET_35 EXYNOS4_GPX0(1) - -#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) -#define GPIO_THIRD_MIC_BIAS_EN EXYNOS4212_GPJ0(2) +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) -#define GPIO_PMU_RST EXYNOS4_GPX3(2) +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) #define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) #define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) -#define GPIO_TSP_INT EXYNOS4212_GPM2(3) -#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) -#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) + +/* BT */ #define GPIO_BT_EN EXYNOS4_GPL0(6) #define GPIO_BT_WAKE EXYNOS4_GPX3(1) #define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) @@ -119,37 +88,30 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_BT_RTS EXYNOS4_GPA0(3) #define GPIO_BT_RTS_AF 2 + +/* GPS */ #define GPIO_GPS_RXD EXYNOS4_GPA0(4) #define GPIO_GPS_RXD_AF 2 #define GPIO_GPS_TXD EXYNOS4_GPA0(5) #define GPIO_GPS_TXD_AF 2 +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_TARGET_LOCALE_CHN) #define GPIO_GPS_CTS EXYNOS4_GPA0(6) -#define GPIO_GPS_CTS_AF 2 - #define GPIO_GPS_RTS EXYNOS4_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 +#else +#define GPIO_GPS_CTS -1 +#define GPIO_GPS_RTS -1 +#endif -#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) -#define GPIO_HDMI_EN EXYNOS4_GPL0(4) -#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) -#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(0) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS_AF 2 -#define GPIO_PWM0 EXYNOS4_GPD0(0) -#define GPIO_PWM1 EXYNOS4_GPD0(1) -#define GPIO_PWM2 EXYNOS4_GPD0(2) -#define GPIO_PWM3 EXYNOS4_GPD0(3) +#define GPIO_GPS_nRST EXYNOS4_GPL2(1) +#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) -#define GPIO_VIBTONE_EN EXYNOS4212_GPJ0(6) +/* WIFI */ #define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) #define GPIO_WLAN_EN_AF 1 #define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) @@ -167,156 +129,245 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) #define GPIO_WLAN_SDIO_D3_AF 2 -#define GPIO_USB_SEL EXYNOS4212_GPJ0(1) - -#define GPIO_LCD_22V_EN EXYNOS4212_GPM4(4) -#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) - -#define GPIO_ISP_TXD EXYNOS4212_GPM4(5) -#define GPIO_ISP_RXD EXYNOS4212_GPM4(6) - -#define GPIO_TA_EN EXYNOS4_GPL2(2) - -#define GPIO_MHL_SEL EXYNOS4_GPL0(3) - +#ifdef CONFIG_SAMSUNG_MHL +/* Definitions for Sii 9244B0 */ #define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) #define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) -#define GPIO_MHL_SDA_1_8V_00 EXYNOS4_GPB(2) -#define GPIO_MHL_SCL_1_8V_00 EXYNOS4_GPB(3) - -#define GPIO_OTG_EN EXYNOS4_GPF0(7) - -#define GPIO_OLED_ID EXYNOS4_GPF1(0) -#define GPIO_ISP_RESET EXYNOS4_GPF1(3) -#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) -#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) - -#define GPIO_MLCD_RST EXYNOS4_GPF2(1) -#define GPIO_UART_SEL EXYNOS4_GPF2(3) -#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) -#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) -#define GPIO_OLED_DET EXYNOS4_GPF3(0) - -#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) -#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) - -/* Definitions for Sii 9244B0 */ -#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) -#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) -#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) -#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) #define GPIO_MHL_RST EXYNOS4_GPF3(4) #define GPIO_MHL_INT EXYNOS4_GPF3(5) #define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) #define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#endif +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) -#define GPIO_RGB_SDA_1_8V EXYNOS4_GPF0(0) -#define GPIO_RGB_SCL_1_8V EXYNOS4_GPF0(1) -#define GPIO_RGB_INT EXYNOS4_GPX2(2) -#define GPIO_VOL_UP EXYNOS4212_GPJ1(1) -#define GPIO_VOL_DOWN EXYNOS4212_GPJ1(2) -#define GPIO_VOL_UP_00 EXYNOS4_GPX2(2) -#define GPIO_VOL_DOWN_00 EXYNOS4_GPX3(3) - -#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) -#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) -#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +/* Touch key */ +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) -#define GPIO_MHL_DSCL_2_8V EXYNOS4_GPK1(0) -#define GPIO_MHL_DSDA_2_8V EXYNOS4_GPK1(2) -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +/* TSP */ +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_LDO_28V_EN EXYNOS4212_GPM4(0) -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) +/* Keys */ +#define GPIO_OK_KEY EXYNOS4_GPX0(1) /* above 0.1 */ +#define GPIO_VOL_UP EXYNOS4_GPX2(2) #define GPIO_nPOWER EXYNOS4_GPX2(7) -#define GPIO_OK_KEY EXYNOS4_GPX3(5) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) + +/* Pen */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_TARGET_LOCALE_CHN) +#define GPIO_PEN_SDA EXYNOS4_GPB(2) +#define GPIO_PEN_SCL EXYNOS4_GPB(3) +#else +#define GPIO_PEN_SDA EXYNOS4_GPA0(6) +#define GPIO_PEN_SCL EXYNOS4_GPA0(7) +#endif + +#define GPIO_WACOM_LDO_EN EXYNOS4_GPF2(5) +#define GPIO_PEN_IRQ EXYNOS4_GPX0(4) +#define GPIO_WACOM_SENSE EXYNOS4_GPX2(4) +#define GPIO_PEN_PDCT EXYNOS4_GPX3(5) +#define GPIO_PEN_SLP EXYNOS4_GPY1(3) +#define GPIO_PEN_FWE1 EXYNOS4_GPY1(3) +#define GPIO_PEN_RESET_N EXYNOS4_GPY2(1) + +/* battery */ #define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#if defined(CONFIG_TARGET_LOCALE_USA) +#define GPIO_BATT_PRESENT_N_INT EXYNOS4_GPX1(3) /* rev0.2 ~ */ +#endif +#if defined(CONFIG_BATTERY_WPC_CHARGER) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) /* rev0.2 ~ */ +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) /* rev0.2 ~ */ +#endif + +/* Others */ +#define GPIO_LCD_18V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) /* obsoleted */ + +#define GPIO_OTG_EN EXYNOS4_GPF0(7) -#define GPIO_V_BUS_INT EXYNOS4_GPX2(4) /* rev0.9 ~ */ -#define GPIO_WPC_INT EXYNOS4_GPX3(0) +#define GPIO_OLED_ID EXYNOS4_GPF1(0) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) -#define GPIO_VIBTONE_PWM EXYNOS4_GPD0(1) +#if defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(2) +#endif -#define GPIO_CODEC_SDA_18V EXYNOS4_GPD0(2) -#define GPIO_CODEC_SCL_18V EXYNOS4_GPD0(3) -#define GPIO_CODEC_SDA_18V_00 EXYNOS4_GPB(0) -#define GPIO_CODEC_SCL_18V_00 EXYNOS4_GPB(1) +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_AUDIO_PCM_SEL EXYNOS4212_GPM0(3) +#endif +#if defined(CONFIG_SWITCH_DUAL_MODEM) +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_UART_SEL EXYNOS4212_GPM3(6) +#define GPIO_USB_SEL EXYNOS4212_GPM4(0) +#define GPIO_CP_USB_ON EXYNOS4212_GPM0(2) +#endif +#endif -#define GPIO_CODEC_LDO_EN EXYNOS4212_GPJ0(4) +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_OLED_DET EXYNOS4_GPF3(0) #define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) +#define GPIO_ERR_FG EXYNOS4212_GPJ0(7) + +#define GPIO_G_DET_N EXYNOS4_GPX3(0) +#define GPIO_G_DET_N_REV03 EXYNOS4_GPX2(0) +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) + +#ifdef CONFIG_JACK_FET +#define GPIO_EAR_BIAS_DISCHARGE EXYNOS4_GPC1(0) +#endif + +/** Previous revision **/ +/* rev0.0 */ +#define GPIO_TSP_LDO_EN EXYNOS4212_GPJ0(6) +/* GPIO_MHL_SEL EXYNOS4212_GPJ0(5) */ +/* GPIO_LCD_22V_EN EXYNOS4_GPC0(1) */ + /* Modem Interface GPIOs - M0 HSIC */ -#if !defined(CONFIG_SEC_MODEM_M0_TD) #define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) #define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) #define GPIO_PHONE_ON EXYNOS4_GPL2(5) #define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) #define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) -#define GPIO_GPS_CNTL EXYNOS4212_GPM3(4) #define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) #define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) #define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) #define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) #define GPIO_CP_RST EXYNOS4_GPX3(2) -#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) -#define GPIO_FM_RST EXYNOS4_GPC1(1) -#else -/* Modem Interface GPIOs - M0 SPI */ -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) -#define GPIO_PHONE_ON EXYNOS4_GPL2(5) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) -#define GPIO_AP_CP_INT1 EXYNOS4_GPX0(5) -#define GPIO_AP_CP_INT2 EXYNOS4_GPX3(5) -#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) -#define GPIO_IPC_MRDY EXYNOS4_GPX0(4) -#define GPIO_IPC_SRDY EXYNOS4_GPX1(0) -#define GPIO_IPC_SUB_MRDY EXYNOS4_GPX3(2) -#define GPIO_IPC_SUB_SRDY EXYNOS4_GPX1(1) - -#define GPIO_CP_RST EXYNOS4_GPF1(1) -#define GPIO_CP_REQ_RESET EXYNOS4_GPF1(1) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX2(0) -#define GPIO_SUSPEND_REQUEST EXYNOS4_GPF1(1) -#define GPIO_ISP_INT EXYNOS4_GPF1(1) -#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +/* Modem Interface GPIOs - MDM */ +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4_GPY2(3) + +#if defined(CONFIG_MACH_T0_CHN_CMCC) +/* Modem Interface GPIOs - T0 SPI */ +#define GPIO_TD_PDA_ACTIVE EXYNOS4_GPF3(4) +#define GPIO_TD_PHONE_ON EXYNOS4212_GPM0(1) +#define GPIO_TD_PHONE_ACTIVE EXYNOS4_GPX1(3) +#define GPIO_AP_TD_INT1 EXYNOS4_GPF0(6) +#define GPIO_AP_TD_INT2 EXYNOS4_GPF0(4) +#define GPIO_TD_DUMP_INT EXYNOS4_GPX0(5) +#define GPIO_IPC_MRDY EXYNOS4_GPF2(4) +#define GPIO_IPC_SRDY EXYNOS4_GPX0(6) +#define GPIO_IPC_SUB_MRDY EXYNOS4_GPF2(2) +#define GPIO_IPC_SUB_SRDY EXYNOS4_GPX3(0) + +#define IRQ_PHONE_ACTIVE gpio_to_irq(GPIO_TD_PHONE_ACTIVE) +#define IRQ_IPC_SRDY gpio_to_irq(GPIO_IPC_SRDY) +#define IRQ_IPC_SUB_SRDY gpio_to_irq(GPIO_IPC_SUB_SRDY) +#define IRQ_TD_DUMP_INT gpio_to_irq(GPIO_TD_DUMP_INT) -#define GPIO_FM_RST EXYNOS4_GPC1(0) +#endif -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_PHONE_ACTIVE IRQ_EINT14 -#define IRQ_IPC_SRDY IRQ_EINT8 -#define IRQ_IPC_SUB_SRDY IRQ_EINT9 -#define IRQ_CP_DUMP_INT IRQ_EINT10 +#ifdef CONFIG_SEC_DUAL_MODEM_MODE +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_SIM_IO_SEL EXYNOS4_GPL2(0) +#define GPIO_CP_CTRL1 EXYNOS4_GPL2(3) +#define GPIO_CP_CTRL2 EXYNOS4_GPL2(4) +#endif #endif -#define GPIO_OK_KEY_ANDROID EXYNOS4_GPX0(1) /*system_rev == 11*/ -#define GPIO_OK_KEY_ANDROID_F EXYNOS4_GPX1(3) /*system_rev >= 15*/ -#define GPIO_FM_INT_REV15 EXYNOS4_GPX1(4) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX1(3) +#if !defined(CONFIG_MACH_T0_CHN_CMCC) +/* FM (Eur) */ #define GPIO_FM_INT EXYNOS4_GPX1(3) -#define GPIO_FM_MIC_SW EXYNOS4_GPL0(3) +#define GPIO_FM_RST EXYNOS4_GPX1(4) +#define GPIO_FM_RST_REV03 EXYNOS4_GPY0(1) +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) +#endif #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) -#define GPIO_TDMB_EN EXYNOS4_GPL0(0) -#define GPIO_TDMB_INT EXYNOS4_GPF0(2) +#define GPIO_TDMB_RST_N EXYNOS4_GPC0(0) +#define GPIO_TDMB_EN EXYNOS4_GPC0(2) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) #define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) -#define GPIO_TDMB_INT_AF 0xf #define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) #define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) #define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) #define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#if defined(CONFIG_TDMB_ANT_DET) +#define GPIO_TDMB_ANT_DET EXYNOS4_GPF2(0) +#define GPIO_TDMB_IRQ_ANT_DET gpio_to_irq(GPIO_TDMB_ANT_DET) +#define GPIO_TDMB_ANT_DET_REV08 EXYNOS4_GPX1(3) +#define GPIO_TDMB_IRQ_ANT_DET_REV08 gpio_to_irq(GPIO_TDMB_ANT_DET_REV08) +#endif + +#elif defined(CONFIG_ISDBT) +#define GPIO_ISDBT_RST_N EXYNOS4_GPC0(0) +#define GPIO_ISDBT_EN EXYNOS4_GPC0(2) +#define GPIO_ISDBT_INT EXYNOS4_GPC0(4) +#define GPIO_ISDBT_IRQ gpio_to_irq(GPIO_ISDBT_INT) +#define GPIO_ISDBT_INT_AF 0xf +#define GPIO_ISDBT_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_ISDBT_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_ISDBT_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_ISDBT_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +/*BARCODE_EMUL*/ +#if defined(CONFIG_BARCODE_EMUL_ICE4) +#define GPIO_BARCODE_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_BARCODE_SCL_1_8V EXYNOS4_GPF0(1) + +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) +#define GPIO_FPGA_CDONE EXYNOS4_GPF3(4) +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF3(5) +#else +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF0(2) +#define GPIO_FPGA_CDONE EXYNOS4_GPF0(3) +#endif + +#define GPIO_FPGA_RST_N EXYNOS4_GPF0(5) +#define GPIO_FPGA_SPI_CLK EXYNOS4212_GPM4(4) +#define GPIO_FPGA_SPI_SI EXYNOS4212_GPM4(6) +#define GPIO_FPGA_SPI_EN EXYNOS4212_GPM4(5) +#endif + +#if defined(CONFIG_FELICA) +#define FELICA_GPIO_I2C_SDA EXYNOS4_GPY2(4) +#define FELICA_GPIO_I2C_SCL EXYNOS4_GPY2(5) +#define FELICA_UART3RX EXYNOS4_GPA1(4) +#define FELICA_GPIO_RFS EXYNOS4_GPL2(6) +#define FELICA_GPIO_PON EXYNOS4_GPL2(7) +#define FELICA_GPIO_INT EXYNOS4_GPX1(7) #endif #endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0ctc.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0ctc.h new file mode 100644 index 0000000..61315f8 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0ctc.h @@ -0,0 +1,383 @@ +#ifndef __MACH_GPIO_T0CTC_H +#define __MACH_GPIO_T0CTC_H __FILE__ + +#include <mach/gpio.h> + +extern void midas_config_gpio_table(void); +extern void midas_config_sleep_gpio_table(void); + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + + +/* Camera */ +#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) +#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) +#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) +#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) + +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) +#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) + +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) +#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) + +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM4(1) +#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) +#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) +#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) + + +/* NFC */ +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) /* above rev0.1 */ +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) /* above rev0.1 */ + + +/* Sensor Hub */ +#define GPIO_MCU_AP_INT EXYNOS4_GPX0(0) +#define GPIO_AP_MCU_INT EXYNOS4_GPX0(2) +#define GPIO_MCU_AP_INT_2 EXYNOS4_GPX2(1) +#define GPIO_MCU_NRST EXYNOS4_GPY2(2) + + +/* PMIC */ +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) +#define GPIO_TF_EN EXYNOS4_GPY2(0) + +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) + +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) + +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) +#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) + +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) + + +/* BT */ +#define GPIO_BT_EN EXYNOS4_GPL0(6) +#define GPIO_BT_WAKE EXYNOS4_GPX3(1) +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) +#define IRQ_BT_HOST_WAKE IRQ_EINT(22) + +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_RXD_AF 2 + +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_TXD_AF 2 + +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_CTS_AF 2 + +#define GPIO_BT_RTS EXYNOS4_GPA0(3) +#define GPIO_BT_RTS_AF 2 + + +/* GPS */ +#define GPIO_GPS_RXD EXYNOS4_GPA0(4) +#define GPIO_GPS_RXD_AF 2 + +#define GPIO_GPS_TXD EXYNOS4_GPA0(5) +#define GPIO_GPS_TXD_AF 2 + +#if defined(CONFIG_MACH_T0_EUR_OPEN) +#define GPIO_GPS_CTS EXYNOS4_GPA0(6) +#define GPIO_GPS_RTS EXYNOS4_GPA0(7) +#else +#define GPIO_GPS_CTS -1 +#define GPIO_GPS_RTS -1 +#endif + +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS_AF 2 + +#if defined(CONFIG_MACH_T0_EUR_OPEN) +#define GPIO_GPS_nRST EXYNOS4_GPL2(1) +#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) +#else +#define GPIO_GPS_nRST -1 +#define GPIO_GPS_PWR_EN -1 +#endif + +/* WIFI */ +#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) +#define GPIO_WLAN_HOST_WAKE_AF 0xF +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + + +#ifdef CONFIG_SAMSUNG_MHL +/* Definitions for Sii 9244B0 */ +#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) +#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#endif + +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + +/* Touch key */ +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) + + +/* TSP */ +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) + + +/* Keys */ +#define GPIO_OK_KEY EXYNOS4_GPX0(1) /* above 0.1 */ +#define GPIO_VOL_UP EXYNOS4_GPX2(2) +#define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) + + +/* Pen */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) +#define GPIO_PEN_SDA EXYNOS4_GPB(2) +#define GPIO_PEN_SCL EXYNOS4_GPB(3) +#else +#define GPIO_PEN_SDA EXYNOS4_GPA0(6) +#define GPIO_PEN_SCL EXYNOS4_GPA0(7) +#endif + +#define GPIO_WACOM_LDO_EN EXYNOS4_GPF2(5) +#define GPIO_PEN_IRQ EXYNOS4_GPX0(4) +#define GPIO_WACOM_SENSE EXYNOS4_GPX2(4) +#define GPIO_PEN_PDCT EXYNOS4_GPX3(5) +#define GPIO_PEN_SLP EXYNOS4_GPY1(3) +#define GPIO_PEN_FWE1 EXYNOS4_GPY1(3) +#define GPIO_PEN_RESET_N EXYNOS4_GPY2(1) + +#if defined(CONFIG_BATTERY_WPC_CHARGER) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) /* rev0.2 ~ */ +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) /* rev0.2 ~ */ +#endif + +/* Others */ +#define GPIO_LCD_18V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) /* obsoleted */ + +#define GPIO_OTG_EN EXYNOS4_GPF0(7) + +#define GPIO_OLED_ID EXYNOS4_GPF1(0) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) + +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) + +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF1(1) + +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_OLED_DET EXYNOS4_GPF3(0) + +#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) +#define GPIO_ERR_FG EXYNOS4212_GPJ0(7) + +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#define GPIO_G_DET_N EXYNOS4_GPX3(0) +#define GPIO_G_DET_N_REV03 EXYNOS4_GPX2(0) +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) + +#ifdef CONFIG_JACK_FET +#define GPIO_EAR_BIAS_DISCHARGE EXYNOS4_GPC1(0) +#endif + +/** Previous revision **/ +/* rev0.0 */ +#define GPIO_TSP_LDO_EN EXYNOS4212_GPJ0(6) +/* GPIO_MHL_SEL EXYNOS4212_GPJ0(5) */ +/* GPIO_LCD_22V_EN EXYNOS4_GPC0(1) */ + + +#if !defined(CONFIG_MACH_T0_CHN_CTC) +/* Modem Interface GPIOs - M0 HSIC */ +#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) +#define GPIO_PHONE_ON EXYNOS4_GPL2(5) +#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) +#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_CP_RST EXYNOS4_GPX3(2) + + +/* Modem Interface GPIOs - MDM */ +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ +#define GPIO_AP2MDM_PMIC_RESET_N EXYNOS4_GPY2(3) + + +/* FM (Eur) */ +#define GPIO_FM_INT EXYNOS4_GPX1(3) +#define GPIO_FM_RST EXYNOS4_GPX1(4) +#define GPIO_FM_RST_REV03 EXYNOS4_GPY0(1) +#define GPIO_ADC_SCL EXYNOS4_GPY0(2) /* obsoleted */ +#define GPIO_ADC_SDA EXYNOS4_GPY0(3) /* obsoleted */ +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) +#endif + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#define GPIO_TDMB_RST_N EXYNOS4_GPC0(0) +#define GPIO_TDMB_EN EXYNOS4_GPC0(2) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) +#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) +#define GPIO_TDMB_INT_AF 0xf +#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +/*BARCODE_EMUL*/ +#if defined(CONFIG_BARCODE_EMUL_ICE4) +#define GPIO_BARCODE_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_BARCODE_SCL_1_8V EXYNOS4_GPF0(1) +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF0(2) +#define GPIO_FPGA_CDONE EXYNOS4_GPF0(3) +#define GPIO_FPGA_RST_N EXYNOS4_GPF0(5) +#define GPIO_FPGA_SPI_CLK EXYNOS4212_GPM4(4) +#define GPIO_FPGA_SPI_SI EXYNOS4212_GPM4(6) +#define GPIO_FPGA_SPI_EN EXYNOS4212_GPM4(5) +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define GPIO_FPGA1_CRESET EXYNOS4_GPF0(2) +#define GPIO_FPGA1_CDONE EXYNOS4_GPF0(3) +#define GPIO_FPGA1_RST_N EXYNOS4_GPF0(6) +#define GPIO_FPGA1_CS_N EXYNOS4_GPC1(2) + +#define GPIO_FPGA2_CRESET EXYNOS4_GPF0(0) +#define GPIO_FPGA2_CDONE EXYNOS4_GPF0(1) +#define GPIO_FPGA2_RST_N EXYNOS4_GPF2(3) +#define GPIO_FPGA2_CS_N EXYNOS4_GPC0(2) +#endif + +/* Definitions for DPRAM */ +#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) +#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) +#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) +#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) +#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) +#define GPIO_DPRAM_LBN EXYNOS4_GPY1(0) +#define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) +#define GPIO_DPRAM_BUSY EXYNOS4_GPY1(2) + + +/* Definitions for MDM6600 */ +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) + +#define GPIO_USB_HUB_RST EXYNOS4_GPL0(0) +#define GPIO_USB_HUB_SCL EXYNOS4_GPL1(0) +#define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) +#define GPIO_USB_HUB_INT EXYNOS4_GPX1(3) + +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#define GPIO_BOOT_SW_SEL_CP1 EXYNOS4_GPF3(4) +#define GPIO_USB_SEL EXYNOS4212_GPJ1(4) + +#define GPIO_USB_BOOT_EN EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL EXYNOS4_GPF3(4) + +/* for revesion 06 higher */ +#define GPIO_USB_BOOT_EN_REV06 EXYNOS4_GPF2(2) +#define GPIO_BOOT_SW_SEL_REV06 EXYNOS4_GPF3(4) + +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPC0(3) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPC0(0) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) + +#define GPIO_CP_MSM_PWRON EXYNOS4_GPL2(5) +#define GPIO_CP_MSM_RST EXYNOS4_GPL2(1) +#define GPIO_CP_MSM_PMU_RST EXYNOS4_GPC0(0) +#define GPIO_CP_MSM_DUMP EXYNOS4_GPX1(2) + +#define GPIO_MSM_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define MSM_PHONE_ACTIVE_IRQ IRQ_EINT(14) + +#define GPIO_MSM_DPRAM_INT EXYNOS4_GPX1(1) +#define MSM_DPRAM_INT_IRQ IRQ_EINT(9) + + +/* Definitions for ESC6270 */ +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(3) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(2) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) + +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX3(2) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(26) + +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX1(0) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(8) + +#if defined(CONFIG_SIM_SLOT_SWITCH) +#define GPIO_UIM_SIM_SEL EXYNOS4_GPL0(4) +#endif + +/* DUMMY GPIOS */ +#define GPIO_MHL_SEL EXYNOS4_GPC0(0) +#define GPIO_HDMI_HPD EXYNOS4_GPC0(0) +#define GPIO_HDMI_EN EXYNOS4_GPC0(0) +#define GPIO_USB_HUB_CONNECT EXYNOS4_GPC0(0) + +#endif /* __MACH_GPIO_T0CTC_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev00-t0cu-duos.h b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0cu-duos.h new file mode 100644 index 0000000..e477c7e --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gpio-rev00-t0cu-duos.h @@ -0,0 +1,354 @@ +#ifndef __MACH_GPIO_MIDAS_H +#define __MACH_GPIO_MIDAS_H __FILE__ + +#include <mach/gpio.h> + +extern void midas_config_gpio_table(void); +extern void midas_config_sleep_gpio_table(void); + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + + +/* Camera */ +#define GPIO_CAM_SPI_SCLK EXYNOS4_GPB(4) +#define GPIO_CAM_SPI_SSN EXYNOS4_GPB(5) +#define GPIO_CAM_SPI_MISO EXYNOS4_GPB(6) +#define GPIO_CAM_SPI_MOSI EXYNOS4_GPB(7) + +#define GPIO_CAM_SW_EN EXYNOS4212_GPJ1(0) +#define GPIO_TORCH_EN EXYNOS4212_GPJ1(1) +#define GPIO_TORCH_SET EXYNOS4212_GPJ1(2) +#define GPIO_CAM_MCLK EXYNOS4212_GPJ1(3) +#define GPIO_VTCAM_MCLK EXYNOS4212_GPM2(2) + +#define GPIO_ISP_STANDBY EXYNOS4212_GPM0(6) +#define GPIO_CAM_IO_EN EXYNOS4212_GPM0(7) +#define GPIO_ISP_CORE_EN EXYNOS4212_GPM1(0) +#define GPIO_CAM_AF_EN EXYNOS4212_GPM1(1) +#define GPIO_CAM_VT_nRST EXYNOS4212_GPM1(6) +#define GPIO_ISP_RESET EXYNOS4_GPF1(3) + +#define GPIO_CAM_SENSOR_CORE_EN EXYNOS4212_GPM4(1) +#define GPIO_VT_CAM_SCL_18V EXYNOS4212_GPM4(2) +#define GPIO_VT_CAM_SDA_18V EXYNOS4212_GPM4(3) +#define GPIO_VT_CAM_ID EXYNOS4_GPF1(2) + + +/* NFC */ +#define GPIO_NFC_EN EXYNOS4_GPL2(6) +#define GPIO_NFC_FIRMWARE EXYNOS4_GPL2(7) +#define GPIO_NFC_IRQ EXYNOS4_GPX1(7) +#define GPIO_NFC_SDA_18V EXYNOS4_GPY2(4) /* above rev0.1 */ +#define GPIO_NFC_SCL_18V EXYNOS4_GPY2(5) /* above rev0.1 */ + + +/* Sensor Hub */ +#define GPIO_MCU_AP_INT EXYNOS4_GPX0(0) +#define GPIO_AP_MCU_INT EXYNOS4_GPX0(2) +#define GPIO_MCU_AP_INT_2 EXYNOS4_GPX2(1) +#define GPIO_MCU_NRST EXYNOS4_GPY2(2) + + +/* PMIC */ +#define GPIO_eMMC_EN EXYNOS4_GPK0(2) +#define GPIO_TF_EN EXYNOS4_GPY2(0) + +#define GPIO_IF_PMIC_SDA EXYNOS4212_GPM2(0) +#define GPIO_IF_PMIC_SCL EXYNOS4212_GPM2(1) + +#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) + +#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) +#define GPIO_IF_PMIC_IRQ EXYNOS4_GPX1(5) + +#define GPIO_PMIC_DVS1 EXYNOS4212_GPM3(0) +#define GPIO_PMIC_DVS2 EXYNOS4212_GPM3(1) +#define GPIO_PMIC_DVS3 EXYNOS4212_GPM3(2) +#define GPIO_BUCK2_SEL EXYNOS4_GPF3(1) +#define GPIO_BUCK3_SEL EXYNOS4_GPF3(2) +#define GPIO_BUCK4_SEL EXYNOS4_GPF3(3) + + +/* BT */ +#define GPIO_BT_EN EXYNOS4_GPL0(6) +#define GPIO_BT_WAKE EXYNOS4_GPX3(1) +#define GPIO_BT_HOST_WAKE EXYNOS4_GPX2(6) +#define IRQ_BT_HOST_WAKE IRQ_EINT(22) + +#define GPIO_BT_RXD EXYNOS4_GPA0(0) +#define GPIO_BT_RXD_AF 2 + +#define GPIO_BT_TXD EXYNOS4_GPA0(1) +#define GPIO_BT_TXD_AF 2 + +#define GPIO_BT_CTS EXYNOS4_GPA0(2) +#define GPIO_BT_CTS_AF 2 + +#define GPIO_BT_RTS EXYNOS4_GPA0(3) +#define GPIO_BT_RTS_AF 2 + + +/* GPS */ +#define GPIO_GPS_RXD EXYNOS4_GPA0(4) +#define GPIO_GPS_RXD_AF 2 + +#define GPIO_GPS_TXD EXYNOS4_GPA0(5) +#define GPIO_GPS_TXD_AF 2 + +#define GPIO_GPS_CTS EXYNOS4_GPA0(6) +#define GPIO_GPS_RTS EXYNOS4_GPA0(7) + +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_RTS_AF 2 + +#define GPIO_GPS_nRST EXYNOS4_GPL2(1) +#define GPIO_GPS_PWR_EN EXYNOS4_GPL2(2) + + +/* WIFI */ +#define GPIO_WLAN_EN EXYNOS4212_GPJ0(0) +#define GPIO_WLAN_EN_AF 1 +#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) +#define GPIO_WLAN_HOST_WAKE_AF 0xF +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + + +/* Definitions for Sii 9244B0 */ +#ifdef CONFIG_SAMSUNG_MHL +#define GPIO_MHL_SDA_1_8V EXYNOS4_GPF0(4) +#define GPIO_MHL_SCL_1_8V EXYNOS4_GPF0(6) +#define GPIO_MHL_RST EXYNOS4_GPF3(4) +#define GPIO_MHL_INT EXYNOS4_GPF3(5) +#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) +#define GPIO_MHL_WAKE_UP EXYNOS4212_GPJ1(4) +#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) +#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) +#endif + +#define GPIO_HDMI_EN EXYNOS4_GPL0(4) +#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) + + +/* Touch key */ +#define GPIO_3_TOUCH_SCL EXYNOS4_GPL0(1) +#define GPIO_3_TOUCH_SDA EXYNOS4_GPL0(2) +#define GPIO_3_TOUCH_EN EXYNOS4212_GPM0(5) +#define GPIO_3_TOUCH_INT EXYNOS4212_GPJ0(3) + + +/* TSP */ +#define GPIO_TSP_SDA_18V EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL_18V EXYNOS4_GPA1(3) +#define GPIO_TSP_INT EXYNOS4212_GPM2(3) +#define GPIO_TSP_LDO_28V_EN EXYNOS4212_GPM4(0) + + +/* Keys */ +#define GPIO_OK_KEY EXYNOS4_GPX0(1) /* above 0.1 */ +#define GPIO_VOL_UP EXYNOS4_GPX2(2) +#define GPIO_nPOWER EXYNOS4_GPX2(7) +#define GPIO_VOL_DOWN EXYNOS4_GPX3(3) + + +/* Pen */ +#define GPIO_PEN_SDA EXYNOS4_GPB(2) +#define GPIO_PEN_SCL EXYNOS4_GPB(3) + +#define GPIO_WACOM_LDO_EN EXYNOS4_GPF2(5) +#define GPIO_PEN_IRQ EXYNOS4_GPX0(4) +#define GPIO_WACOM_SENSE EXYNOS4_GPX2(4) +#define GPIO_PEN_PDCT EXYNOS4_GPX3(5) +#define GPIO_PEN_SLP EXYNOS4_GPY1(3) +#define GPIO_PEN_FWE1 EXYNOS4_GPY1(3) +#define GPIO_PEN_RESET_N EXYNOS4_GPY2(1) + +/* battery */ +#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) +#if defined(CONFIG_TARGET_LOCALE_USA) +#define GPIO_BATT_PRESENT_N_INT EXYNOS4_GPX1(3) /* rev0.2 ~ */ +#endif +#if defined(CONFIG_BATTERY_WPC_CHARGER) +#define GPIO_WPC_INT EXYNOS4_GPX3(0) /* rev0.2 ~ */ +#define GPIO_V_BUS_INT EXYNOS4_GPX1(4) /* rev0.2 ~ */ +#endif + +/* Others */ +#define GPIO_LCD_18V_EN EXYNOS4_GPC0(1) +#define GPIO_LCD_22V_EN_00 EXYNOS4_GPC0(1) /* obsoleted */ + +#define GPIO_OTG_EN EXYNOS4_GPF0(7) + +#define GPIO_OLED_ID EXYNOS4_GPF1(0) +#define GPIO_FUEL_SCL EXYNOS4_GPF1(4) +#define GPIO_FUEL_SDA EXYNOS4_GPF1(5) + +#define GPIO_MIC_BIAS_EN EXYNOS4_GPF1(7) +#define GPIO_SUB_MIC_BIAS_EN EXYNOS4_GPF2(0) + + +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#define GPIO_AUDIO_PCM_SEL EXYNOS4_GPF2(2) +#endif + +#if defined(CONFIG_MACH_T0_CHN_CMCC) +#define GPIO_AUDIO_PCM_SEL EXYNOS4212_GPM0(3) +#endif + +#define GPIO_MLCD_RST EXYNOS4_GPF2(1) +#define GPIO_S_LED_I2C_SCL EXYNOS4_GPF2(6) +#define GPIO_S_LED_I2C_SDA EXYNOS4_GPF2(7) +#define GPIO_OLED_DET EXYNOS4_GPF3(0) + +#define GPIO_WM8994_LDO EXYNOS4212_GPJ0(4) +#define GPIO_ERR_FG EXYNOS4212_GPJ0(7) + +#define GPIO_G_DET_N EXYNOS4_GPX3(0) +#define GPIO_G_DET_N_REV03 EXYNOS4_GPX2(0) +#define GPIO_VPS_SOUND_EN EXYNOS4_GPL0(3) + +#ifdef CONFIG_JACK_FET +#define GPIO_EAR_BIAS_DISCHARGE EXYNOS4_GPC1(0) +#endif + +/** Previous revision **/ +/* rev0.0 */ +#define GPIO_TSP_LDO_EN EXYNOS4212_GPJ0(6) +/* GPIO_MHL_SEL EXYNOS4212_GPJ0(5) */ +/* GPIO_LCD_22V_EN EXYNOS4_GPC0(1) */ + + +/* Modem Interface GPIOs - M0 HSIC */ +#define GPIO_ACTIVE_STATE EXYNOS4_GPF1(1) +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) +#define GPIO_AP_DUMP_INT EXYNOS4212_GPJ0(1) +#define GPIO_PHONE_ON EXYNOS4_GPL2(5) +#define GPIO_SUSPEND_REQUEST EXYNOS4212_GPM2(4) +#define GPIO_CP_REQ_RESET EXYNOS4212_GPM3(3) +#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPX1(0) +#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPX1(1) +#define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) +#define GPIO_PHONE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_CP_RST EXYNOS4_GPX3(2) + + +/* Modem Interface GPIOs - MDM */ +#define GPIO_MDM2AP_HSIC_READY EXYNOS4_GPF1(1) +#define GPIO_AP2MDM_STATUS EXYNOS4_GPF1(6) +#define GPIO_MDM2AP_HSIC_PWR_ACTIVE EXYNOS4_GPF2(2) /* AP2MDM_IPC2 */ +#define GPIO_WCN_PRIORITY EXYNOS4_GPF2(3) +#define GPIO_MDM_LTE_FRAME_SYNC EXYNOS4_GPF2(4) +#define GPIO_AP2MDM_ERR_FATAL EXYNOS4212_GPJ0(1) +#define GPIO_AP2MDM_PON_RESET_N EXYNOS4_GPL2(5) +#define GPIO_AP2MDM_WAKEUP EXYNOS4212_GPM2(4) +#define GPIO_AP2MDM_SOFT_RESET EXYNOS4212_GPM3(3) +#define GPIO_MDM2AP_STATUS EXYNOS4_GPX0(5) +#define GPIO_MDM2AP_HSIC_RESUME_REQ EXYNOS4_GPX0(6) /* AP2MDM_IPC3 */ +#define GPIO_AP2MDM_VDDMIN EXYNOS4_GPX1(0) +#define GPIO_MDM2AP_VDDMIN EXYNOS4_GPX1(1) +#define GPIO_MDM2AP_ERR_FATAL EXYNOS4_GPX1(2) +#define GPIO_MDM_LTE_ACTIVE EXYNOS4_GPX1(6) +#define GPIO_AP2MDM_HSIC_PORT_ACTIVE EXYNOS4_GPX3(2) /* AP2MDM_IPC1 */ + + +/* FM (Eur) */ +#define GPIO_FM_INT EXYNOS4_GPX1(3) +#define GPIO_FM_RST EXYNOS4_GPX1(4) +#define GPIO_FM_RST_REV03 EXYNOS4_GPY0(1) +#define GPIO_ADC_SCL EXYNOS4_GPY0(2) /* obsoleted */ +#define GPIO_ADC_SDA EXYNOS4_GPY0(3) /* obsoleted */ +#define GPIO_FM_SCL EXYNOS4_GPY0(2) +#define GPIO_FM_SDA EXYNOS4_GPY0(3) + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#define GPIO_TDMB_RST_N EXYNOS4_GPC0(0) +#define GPIO_TDMB_EN EXYNOS4_GPC0(2) +#define GPIO_TDMB_INT EXYNOS4_GPC0(4) +#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) +#define GPIO_TDMB_INT_AF 0xf +#define GPIO_TDMB_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_TDMB_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_TDMB_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPC1(4) +#elif defined(CONFIG_ISDBT) +#define GPIO_ISDBT_RST_N EXYNOS4_GPC0(0) +#define GPIO_ISDBT_EN EXYNOS4_GPC0(2) +#define GPIO_ISDBT_INT EXYNOS4_GPC0(4) +#define GPIO_ISDBT_IRQ gpio_to_irq(GPIO_ISDBT_INT) +#define GPIO_ISDBT_INT_AF 0xf +#define GPIO_ISDBT_SPI_CLK EXYNOS4_GPC1(1) +#define GPIO_ISDBT_SPI_CS EXYNOS4_GPC1(2) +#define GPIO_ISDBT_SPI_MISO EXYNOS4_GPC1(3) +#define GPIO_ISDBT_SPI_MOSI EXYNOS4_GPC1(4) +#endif + +/*BARCODE_EMUL*/ +#if defined(CONFIG_BARCODE_EMUL_ICE4) +#define GPIO_BARCODE_SDA_1_8V EXYNOS4_GPF0(0) +#define GPIO_BARCODE_SCL_1_8V EXYNOS4_GPF0(1) + +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#define GPIO_FPGA_CDONE EXYNOS4_GPF3(4) +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF3(5) +#else +#define GPIO_FPGA_CRESET_B EXYNOS4_GPF0(2) +#define GPIO_FPGA_CDONE EXYNOS4_GPF0(3) +#endif + +#define GPIO_FPGA_RST_N EXYNOS4_GPF0(5) +#define GPIO_FPGA_SPI_CLK EXYNOS4212_GPM4(4) +#define GPIO_FPGA_SPI_SI EXYNOS4212_GPM4(6) +#define GPIO_FPGA_SPI_EN EXYNOS4212_GPM4(5) +#endif + +#if defined(CONFIG_LINK_DEVICE_PLD) +#define GPIO_FPGA1_CRESET EXYNOS4_GPF0(2) +#define GPIO_FPGA1_CDONE EXYNOS4_GPF0(3) +#define GPIO_FPGA1_RST_N EXYNOS4_GPF0(6) +#define GPIO_FPGA1_CS_N EXYNOS4_GPC1(2) +#endif + +/* Definitions for DPRAM */ +#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) +#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) +#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) +#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) +#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) +#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) +#define GPIO_DPRAM_LBN EXYNOS4_GPY1(0) +#define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) +#define GPIO_DPRAM_BUSY EXYNOS4_GPY1(2) + +#if defined(CONFIG_SWITCH_DUAL_MODEM) +#define GPIO_UART_SEL EXYNOS4212_GPJ0(2) +#define GPIO_USB_SEL EXYNOS4212_GPJ1(4) +#endif + +#if defined(CONFIG_GSM_MODEM_ESC6270) +/* Definitions for ESC6270 */ +#define GPIO_CP2_MSM_PWRON EXYNOS4212_GPM0(3) +#define GPIO_CP2_MSM_RST EXYNOS4212_GPM0(2) +#define GPIO_BOOT_SW_SEL_CP2 EXYNOS4_GPF2(4) + +#define GPIO_ESC_PHONE_ACTIVE EXYNOS4_GPX1(3) +#define ESC_PHONE_ACTIVE_IRQ IRQ_EINT(11) + +#define GPIO_ESC_DPRAM_INT EXYNOS4_GPX0(5) +#define ESC_DPRAM_INT_IRQ IRQ_EINT(5) +#endif + +#endif /* __MACH_GPIO_MIDAS_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h b/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h index 809b19d..5e020ad 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h +++ b/arch/arm/mach-exynos/include/mach/gpio-rev03-c1kor.h @@ -310,12 +310,14 @@ extern void midas_config_sleep_gpio_table(void); #define GPIO_USB_HUB_SDA EXYNOS4_GPL1(1) #define GPIO_USB_HUB_INT EXYNOS4_GPX2(1) +/* Definitions for PDA_ACTIVE for CMC221 & CBP7.2 */ +#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) + #if defined(CONFIG_MACH_C1_KOR_LGT) /* Definitions for CBP7.2 */ #define GPIO_CBP_PMIC_PWRON EXYNOS4212_GPM0(6) #define GPIO_CBP_PS_HOLD_OFF EXYNOS4212_GPM1(0) #define GPIO_CBP_CP_RST EXYNOS4_GPF2(4) -#define GPIO_PDA_ACTIVE EXYNOS4_GPF1(6) #define GPIO_CBP_PHONE_ACTIVE EXYNOS4_GPX1(3) #define CBP_PHONE_ACTIVE_IRQ IRQ_EINT(11) diff --git a/arch/arm/mach-exynos/include/mach/gpio-u1.h b/arch/arm/mach-exynos/include/mach/gpio-u1.h index a4b85ac..6b8abb2 100644 --- a/arch/arm/mach-exynos/include/mach/gpio-u1.h +++ b/arch/arm/mach-exynos/include/mach/gpio-u1.h @@ -55,6 +55,11 @@ #define GPIO_CAM_SENSOR_CORE EXYNOS4210_GPE2(5) #define GPIO_TSP_LDO_ON EXYNOS4_GPL0(3) +#ifdef CONFIG_MACH_TRATS +#define GPIO_TSP_SDA EXYNOS4_GPA1(2) +#define GPIO_TSP_SCL EXYNOS4_GPA1(3) +#endif + #define GPIO_USB_SEL EXYNOS4_GPL0(6) #if !defined(CONFIG_MACH_U1_KOR_LGT) #define GPIO_UART_SEL EXYNOS4_GPY4(7) @@ -162,11 +167,19 @@ #define GPIO_2MIC_SDA EXYNOS4_GPC1(2) #define GPIO_2MIC_SCL EXYNOS4_GPC1(0) +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#if defined(CONFIG_LEDS_GPIO) +/* GPIO's for SVC LED */ +#define GPIO_SVC_LED_BLUE EXYNOS4_GPA1(5) +#define GPIO_SVC_LED_RED EXYNOS4_GPB(1) +#endif +#else #define GPIO_FLM_RXD EXYNOS4_GPA1(4) #define GPIO_FLM_RXD_AF 2 #define GPIO_FLM_TXD EXYNOS4_GPA1(5) #define GPIO_FLM_TXD_AF 2 +#endif #if defined(CONFIG_MACH_U1_KOR_LGT) #define GPIO_DPRAM_INT_N EXYNOS4_GPX1(0) @@ -182,7 +195,11 @@ #define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) #define GPIO_CP_DUMP_INT EXYNOS4_GPX1(2) #else +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) +#else #define GPIO_PDA_ACTIVE EXYNOS4_GPX1(7) +#endif #define GPIO_CP_DUMP_INT DUMMY_GPIO #endif #define GPIO_CP_RST EXYNOS4_GPX1(4) @@ -208,6 +225,16 @@ #define IRQ_SUSPEND_REQUEST IRQ_EINT11 #define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 + +#ifdef CONFIG_USBHUB_USB3803 +#define GPIO_USB_RESET_N EXYNOS4210_GPE1(5) +#define GPIO_USB_BYPASS_N EXYNOS4_GPX1(7) +#define GPIO_USB_CLOCK_EN EXYNOS4_GPA1(4) +#define GPIO_USB_I2C_SDA EXYNOS4_GPY1(1) +#define GPIO_USB_I2C_SCL EXYNOS4_GPY1(0) +#endif /* CONFIG_USBHUB_USB3803 */ + + #define GPIO_WLAN_EN EXYNOS4_GPL1(2) #define GPIO_WLAN_EN_AF 1 @@ -223,22 +250,27 @@ #define GPIO_BT_WAKE EXYNOS4_GPX3(1) -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK2(0) +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK2(1) +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK2(3) +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK2(4) +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK2(5) +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK2(6) +#else +#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) +#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) +#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) +#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) +#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) +#endif -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) +#define GPIO_WLAN_SDIO_CLK_AF 2 #define GPIO_WLAN_SDIO_CMD_AF 2 - -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) #define GPIO_WLAN_SDIO_D0_AF 2 - -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) #define GPIO_WLAN_SDIO_D1_AF 2 - -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) #define GPIO_WLAN_SDIO_D2_AF 2 - -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) #define GPIO_WLAN_SDIO_D3_AF 2 #define GPIO_HW_REV0 EXYNOS4210_GPE1(0) @@ -272,9 +304,14 @@ #define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) #define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) #else +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) +#define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) +#else #define GPIO_MHL_SDA_18V EXYNOS4210_GPE1(6) #define GPIO_MHL_SCL_18V EXYNOS4210_GPE1(5) #endif +#endif #define GPIO_AP_HDMI_SDA GPIO_MSENSOR_MHL_SDA_28V #define GPIO_AP_HDMI_SDA_AF GPIO_MSENSOR_MHL_SDA_AF @@ -333,5 +370,24 @@ #define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) #endif +#if defined(CONFIG_TARGET_LOCALE_NA) && defined(CONFIG_WIMAX_CMC) +#define GPIO_WIMAX_USB_EN EXYNOS4_GPB(4) +#define GPIO_WIMAX_EN EXYNOS4210_GPE1(7) +#define GPIO_WIMAX_RESET_N EXYNOS4_GPA0(5) +#define GPIO_WIMAX_USB_EN EXYNOS4_GPB(4) +#define GPIO_WIMAX_WAKEUP EXYNOS4_GPX1(3) +#define GPIO_WIMAX_IF_MODE0 EXYNOS4_GPY3(5) +#define GPIO_WIMAX_IF_MODE1 EXYNOS4_GPY3(6) +#define GPIO_WIMAX_CON0 EXYNOS4_GPL2(6) +#define GPIO_WIMAX_CON1 EXYNOS4_GPL2(7) +#define GPIO_WIMAX_CON2 EXYNOS4210_GPE2(3) +#define GPIO_WIMAX_INT EXYNOS4_GPX1(1) +#define GPIO_WIMAX_I2C_CON EXYNOS4210_GPE1(6) +#define GPIO_WIMAX_DBGEN_28V EXYNOS4_GPA0(4) +#define GPIO_UART_SEL1 EXYNOS4_GPB(0) +#define GPIO_CMC_SCL_18V EXYNOS4_GPY0(0) +#define GPIO_CMC_SDA_18V EXYNOS4_GPY0(1) +#endif + #endif #endif /* __MACH_GPIO_U1_H */ diff --git a/arch/arm/mach-exynos/include/mach/gpio-u1camera.h b/arch/arm/mach-exynos/include/mach/gpio-u1camera.h deleted file mode 100644 index 5d7b8c5..0000000 --- a/arch/arm/mach-exynos/include/mach/gpio-u1camera.h +++ /dev/null @@ -1,296 +0,0 @@ -#ifndef __MACH_GPIO_U1CAMERA_H -#define __MACH_GPIO_U1CAMERA_H __FILE__ - -#ifdef CONFIG_MACH_U1_KOR_LGT -#define DUMMY_GPIO EXYNOS4_GPL2(2) -#endif -#if defined(CONFIG_MACH_U1CAMERA_BD) - -#define GPIO_XMMC0_CDn EXYNOS4_GPK0(2) - -#define GPIO_PS_ALS_SDA EXYNOS4_GPK2(2) -#define GPIO_PS_ALS_SCL EXYNOS4_GPK3(2) - -#define GPIO_GYRO_INT 0/*EXYNOS4_GPX0(0)*/ -#define GPIO_GYRO_FIFOP_INT 0/*EXYNOS4_GPX0(1)*/ -#define GPIO_PS_ALS_INT EXYNOS4_GPX0(2) - -#define GPIO_BUCK1_EN_A EXYNOS4_GPX0(5) -#define GPIO_BUCK1_EN_B EXYNOS4_GPX0(6) -#define GPIO_BUCK2_EN EXYNOS4_GPL0(0) -#define GPIO_PMIC_IRQ EXYNOS4_GPX0(7) - -#define GPIO_VOL_UP EXYNOS4_GPX2(0) -#define GPIO_VOL_DOWN EXYNOS4_GPX2(1) -#define GPIO_nPOWER EXYNOS4_GPX2(7) - -#define GPIO_OK_KEY EXYNOS4_GPX3(5) - -#define VT_CAM_SDA_18V EXYNOS4_GPC1(0) -#define VT_CAM_SCL_18V EXYNOS4_GPC1(2) - -#define CODEC_VT_SDA_18V EXYNOS4_GPC1(3) -#define CODEC_VT_SCL_18V EXYNOS4_GPC1(4) -#ifdef CONFIG_MACH_U1_KOR_LGT -#define GPIO_ISP_RESET EXYNOS4210_GPE0(4) -#else -#define GPIO_ISP_RESET EXYNOS4_GPY3(7) -#endif -#ifdef CONFIG_MACH_U1_KOR_LGT -#define GPIO_FUEL_SDA EXYNOS4210_GPE1(7) -#define GPIO_FUEL_SCL EXYNOS4210_GPE2(0) -#else -#define GPIO_FUEL_SDA EXYNOS4_GPY4(0) -#define GPIO_FUEL_SCL EXYNOS4_GPY4(1) -#endif -#define GPIO_FUEL_ALERT EXYNOS4_GPX2(3) - -#define GPIO_USB_SDA EXYNOS4210_GPE1(0) -#define GPIO_USB_SCL EXYNOS4210_GPE1(1) -#define GPIO_MASSMEM_EN EXYNOS4_GPL1(1) -#define GPIO_MASSMEM_EN_LEVEL 0 -#define GPIO_TSP_INT EXYNOS4_GPX0(4) - -#define GPIO_CAM_IO_EN EXYNOS4210_GPE2(1) -#define GPIO_CAM_SENSOR_CORE EXYNOS4210_GPE2(5) -#define GPIO_TSP_LDO_ON EXYNOS4_GPL0(3) - -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_UART_SEL EXYNOS4_GPY4(7) -#else -#define GPIO_UART_SEL EXYNOS4_GPL2(7) -#endif - -#define GPIO_3_TOUCH_SCL EXYNOS4_GPK1(0) -#define GPIO_8M_AF_EN EXYNOS4_GPK1(1) -#define GPIO_3_TOUCH_SDA EXYNOS4_GPK1(2) -#define GPIO_3_TOUCH_INT EXYNOS4_GPL0(5) - -#define GPIO_VT_CAM_15V EXYNOS4210_GPE2(2) - -#define GPIO_CAM_MCLK EXYNOS4210_GPJ1(3) - -#define GPIO_CAM_VGA_nSTBY EXYNOS4_GPL2(0) -#define GPIO_CAM_VGA_nRST EXYNOS4_GPL2(1) - -#define GPIO_DET_35 EXYNOS4_GPX3(2) -#define GPIO_DET_35_AF 0xF - -#define GPIO_EAR_SEND_END EXYNOS4_GPX3(6) -#define GPIO_EAR_SEND_END_AF 0xF - -#define GPIO_GPS_nRST EXYNOS4_GPL0(6) -#define GPIO_GPS_PWR_EN EXYNOS4_GPL0(7) - -#define GPIO_GPS_RXD EXYNOS4_GPA0(0) -#define GPIO_GPS_RXD_AF 2 - -#define GPIO_GPS_TXD EXYNOS4_GPA0(1) -#define GPIO_GPS_TXD_AF 2 - -#define GPIO_GPS_CTS EXYNOS4_GPA0(2) -#define GPIO_GPS_CTS_AF 2 - -#define GPIO_GPS_RTS EXYNOS4_GPA0(3) -#define GPIO_GPS_RTS_AF 2 - - -#if defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_BOOT_SW_SEL EXYNOS4_GPA0(6) -#define GPIO_USB_BOOT_EN EXYNOS4_GPA0(7) -#endif - -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_NFC_SCL EXYNOS4_GPY0(0) -#else -#define GPIO_NFC_SCL DUMMY_GPIO -#endif -#define GPIO_NFC_SDA EXYNOS4_GPY0(1) -#define GPIO_NFC_EN EXYNOS4_GPL2(6) -#define GPIO_NFC_FIRM EXYNOS4_GPL2(7) - -#define GPIO_2MIC_PWDN EXYNOS4_GPL2(3) -#define GPIO_2MIC_RST EXYNOS4_GPL2(4) -#define GPIO_2MIC_EN EXYNOS4_GPL2(5) - -#ifdef CONFIG_CHARGER_MAX8922_U1 /* sub-charger */ -#define GPIO_CHG_EN EXYNOS4_GPL2(2) -#define GPIO_CHG_ING_N EXYNOS4_GPL2(4) -#define GPIO_TA_nCONNECTED EXYNOS4_GPL2(5) -#endif - -#define GPIO_2MIC_SDA EXYNOS4_GPC1(2) -#define GPIO_2MIC_SCL EXYNOS4_GPC1(0) - -#define GPIO_FLM_RXD EXYNOS4_GPA1(4) -#define GPIO_FLM_RXD_AF 2 - -#define GPIO_FLM_TXD EXYNOS4_GPA1(5) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_PHONE_ON EXYNOS4_GPC1(1) - -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_PDA_ACTIVE EXYNOS4_GPY4(2) -#else -#define GPIO_CP_DUMP_INT DUMMY_GPIO -#endif -#if defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_CP_RST_MSM EXYNOS4_GPL2(6) -#endif -#define GPIO_CP_REQ_RESET EXYNOS4_GPY4(6) - -#define GPIO_S1_KEY EXYNOS4_GPX0(0) -#define GPIO_S2_KEY EXYNOS4_GPX0(1) - -#define GPIO_TELE_KEY EXYNOS4_GPX2(6) -#define GPIO_WIDE_KEY EXYNOS4_GPX3(1) -#define GPIO_RSERVED_KEY EXYNOS4_GPX1(0) -#define GPIO_PLAY_KEY EXYNOS4_GPX1(1) -#define GPIO_RECORD_KEY EXYNOS4_GPX1(2) -#define GPIO_MENU_KEY EXYNOS4_GPX1(3) -#define GPIO_ROTARY_PUSH EXYNOS4_GPX1(4) -#define GPIO_ISP_INT EXYNOS4_GPX1(5) -#define GPIO_HOME_KEY EXYNOS4_GPX1(6) -#define GPIO_BACK_KEY EXYNOS4_GPX1(7) -#define GPIO_NFC_IRQ EXYNOS4_GPL2(6) -#define GPIO_IPC_HOST_WAKEUP EXYNOS4_GPL2(6) -#define GPIO_IPC_SLAVE_WAKEUP EXYNOS4_GPL2(6) -#define GPIO_CP_RST EXYNOS4_GPL2(6) -#define GPIO_PHONE_ACTIVE EXYNOS4_GPL2(6) -#define GPIO_CP_DUMP_INT EXYNOS4_GPL2(6) - - -#define GPIO_ACTIVE_STATE EXYNOS4_GPY3(5) - -#define IRQ_PHONE_ACTIVE IRQ_EINT14 -#define IRQ_SUSPEND_REQUEST IRQ_EINT11 -#define IRQ_IPC_HOST_WAKEUP IRQ_EINT9 - -#define GPIO_WLAN_EN EXYNOS4_GPL1(2) -#define GPIO_WLAN_EN_AF 1 - -#define GPIO_BT_EN EXYNOS4_GPL0(4) -#define GPIO_BT_nRST EXYNOS4_GPL1(0) - -#define GPIO_WLAN_HOST_WAKE EXYNOS4_GPX2(5) -#define GPIO_WLAN_HOST_WAKE_AF 0xF - -#define GPIO_BT_HOST_WAKE 0/*EXYNOS4_GPX2(6)*/ -#define GPIO_BT_HOST_WAKE_AF 0xF -#define IRQ_BT_HOST_WAKE IRQ_EINT(22) - -#define GPIO_BT_WAKE 0/*EXYNOS4_GPX3(1)*/ - -#define GPIO_WLAN_SDIO_CLK EXYNOS4_GPK3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 - -#define GPIO_WLAN_SDIO_CMD EXYNOS4_GPK3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 - -#define GPIO_WLAN_SDIO_D0 EXYNOS4_GPK3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 - -#define GPIO_WLAN_SDIO_D1 EXYNOS4_GPK3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 - -#define GPIO_WLAN_SDIO_D2 EXYNOS4_GPK3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 - -#define GPIO_WLAN_SDIO_D3 EXYNOS4_GPK3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_HW_REV0 EXYNOS4210_GPE1(0) -#define GPIO_HW_REV1 EXYNOS4210_GPE1(1) -#define GPIO_HW_REV2 EXYNOS4210_GPE1(2) -#define GPIO_HW_REV3 EXYNOS4210_GPE1(3) - -#define GPIO_MHL_RST EXYNOS4_GPF3(4) -#define GPIO_MHL_INT EXYNOS4_GPF3(5) -#define GPIO_MHL_INT_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_WAKE_UP EXYNOS4210_GPJ1(4) -#define GPIO_MHL_WAKE_UP_AF S3C_GPIO_SFN(0xF) -#define GPIO_MHL_SEL EXYNOS4_GPL0(1) - -#define GPIO_BOOT_MODE EXYNOS4_GPX0(3) - -#define GPIO_MSENSE_INT EXYNOS4_GPX2(2) -#define GPIO_HDMI_EN EXYNOS4_GPX2(4) -#define GPIO_HDMI_EN_REV07 EXYNOS4_GPL1(1) -#define GPIO_HDMI_CEC EXYNOS4_GPX3(6) -#define GPIO_HDMI_HPD EXYNOS4_GPX3(7) - -#define GPIO_ACC_INT EXYNOS4_GPX3(0) -#define GPIO_USB_OTG_EN EXYNOS4_GPX3(3) - -#define GPIO_MSENSOR_MHL_SDA_28V EXYNOS4_GPD0(2) -#define GPIO_MSENSOR_MHL_SDA_AF 0x3 -#define GPIO_MSENSOR_MHL_SCL_28V EXYNOS4_GPD0(3) -#define GPIO_MSENSOR_MHL_SCL_AF 0x3 -#if !defined(CONFIG_MACH_U1_KOR_LGT) -#define GPIO_MHL_SDA_18V EXYNOS4_GPY3(0) -#define GPIO_MHL_SCL_18V EXYNOS4_GPY3(2) -#else -#define GPIO_MHL_SDA_18V EXYNOS4210_GPE1(6) -#define GPIO_MHL_SCL_18V EXYNOS4210_GPE1(5) -#endif - -#define GPIO_AP_HDMI_SDA GPIO_MSENSOR_MHL_SDA_28V -#define GPIO_AP_HDMI_SDA_AF GPIO_MSENSOR_MHL_SDA_AF -#define GPIO_AP_HDMI_SCL GPIO_MSENSOR_MHL_SCL_28V -#define GPIO_AP_HDMI_SCL_AF GPIO_MSENSOR_MHL_SCL_AF -#define GPIO_AP_SDA_18V GPIO_MHL_SDA_18V -#define GPIO_AP_SCL_18V GPIO_MHL_SCL_18V - -#define MHL_INT_IRQ gpio_to_irq(GPIO_MHL_INT) -#define MHL_WAKEUP_IRQ gpio_to_irq(GPIO_MHL_WAKE_UP) - -#define GPIO_MIC_BIAS_EN EXYNOS4210_GPE1(4) -#ifdef CONFIG_MACH_U1_KOR_LGT -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4210_GPE0(2) -#else -#define GPIO_SUB_MIC_BIAS_EN EXYNOS4210_GPE2(0) -#endif -#define GPIO_EAR_MIC_BIAS_EN EXYNOS4210_GPE2(4) - -#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) -#define GPIO_TDMB_EN EXYNOS4_GPC0(1) -#define GPIO_TDMB_RST_N EXYNOS4_GPB(5) -#define GPIO_TDMB_INT EXYNOS4_GPB(4) -#define GPIO_TDMB_IRQ gpio_to_irq(GPIO_TDMB_INT) -#define GPIO_TDMB_INT_AF 0xf -#define GPIO_TDMB_SPI_CLK EXYNOS4_GPB(0) -#define GPIO_TDMB_SPI_CS EXYNOS4_GPB(1) -#define GPIO_TDMB_SPI_MISO EXYNOS4_GPB(2) -#define GPIO_TDMB_SPI_MOSI EXYNOS4_GPB(3) -#endif -#ifdef CONFIG_FM_SI4709_MODULE -#define GPIO_FM_RST EXYNOS4_GPB(0) -#define GPIO_FM_INT EXYNOS4_GPB(1) -#define GPIO_FM_INT_REV07 EXYNOS4_GPX2(4) -#define GPIO_FM_SDA_28V EXYNOS4_GPB(2) -#define GPIO_FM_SCL_28V EXYNOS4_GPB(3) -#endif - -#ifdef CONFIG_ISDBT_FC8100 -#define GPIO_ISDBT_SCL_28V EXYNOS4210_GPE1(6) -#define GPIO_ISDBT_SDA_28V EXYNOS4210_GPE1(7) -#define GPIO_ISDBT_PWR_EN EXYNOS4_GPC0(1) -#define GPIO_ISDBT_RST EXYNOS4210_GPE1(5) -#endif - -#if defined(CONFIG_MACH_U1_KOR_LGT) -/* Definitions for DPRAM */ -#define GPIO_DPRAM_CSN EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN0 EXYNOS4_GPY0(0) -#define GPIO_DPRAM_CSN1 EXYNOS4_GPY0(1) -#define GPIO_DPRAM_CSN2 EXYNOS4_GPY0(2) -#define GPIO_DPRAM_CSN3 EXYNOS4_GPY0(3) -#define GPIO_DPRAM_REN EXYNOS4_GPY0(4) -#define GPIO_DPRAM_WEN EXYNOS4_GPY0(5) -#define GPIO_DPRAM_LBN EXYNOS4_GPY1(0) -#define GPIO_DPRAM_UBN EXYNOS4_GPY1(1) -#endif - -#endif -#endif /* __MACH_GPIO_U1CAMERA_H */ diff --git a/arch/arm/mach-exynos/include/mach/grande-jack.h b/arch/arm/mach-exynos/include/mach/grande-jack.h new file mode 100644 index 0000000..055bc49 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/grande-jack.h @@ -0,0 +1,25 @@ +/* + * grande-jack.h - Jack Management of GRANDE Project + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __GRANDE_H__ +#define __GRANDE_H__ __FILE__ + +void grande_jack_init(void); +void sec_set_jack_micbias(bool); + +#endif /* __GRANDE_JACK_H__ */ diff --git a/arch/arm/mach-exynos/include/mach/grande-power.h b/arch/arm/mach-exynos/include/mach/grande-power.h new file mode 100644 index 0000000..2512f4d --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/grande-power.h @@ -0,0 +1,39 @@ +/* + * grande-power.h - Power Management of MIDAS Project + * + * Copyright (C) 2011 Samsung Electrnoics + * Chiwoong Byun <woong.byun@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __GRANDE_POWER_H +#define __GRANDE_POWER_H __FILE__ + +#if defined(CONFIG_MFD_S5M_CORE) +extern struct s5m_platform_data exynos4_s5m8767_info; +#else +#ifdef CONFIG_REGULATOR_LP8720 +extern struct lp8720_platform_data folder_pmic_info; +extern struct lp8720_platform_data sub_pmic_info; +#endif +extern struct max77686_platform_data exynos4_max77686_info; +extern struct max8997_platform_data exynos4_max8997_info; +#endif + +void midas_power_init(void); +void midas_power_set_muic_pdata(void *, int); +void midas_power_gpio_init(void); +#endif /* __GRANDE_POWER_H */ diff --git a/arch/arm/mach-exynos/include/mach/gsd4t.h b/arch/arm/mach-exynos/include/mach/gsd4t.h new file mode 100644 index 0000000..d12d9f1 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/gsd4t.h @@ -0,0 +1,28 @@ +/* linux/arm/arch/mach-s5pv310/gsd4t.h + * + * GSD4T(GPS) platform driver data + * + * Copyright (c) 2011 Samsung Electronics + * Minho Ban <mhban@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _GSD4T_H +#define _GSD4T_H + +struct gsd4t_platform_data { + unsigned int onoff; + unsigned int nrst; + unsigned int tsync; + unsigned int uart_rxd; + unsigned int uart_txd; + unsigned int uart_cts; + unsigned int uart_rts; +}; + +#endif /* _GSD4T_H */ + + diff --git a/arch/arm/mach-exynos/include/mach/map-exynos4.h b/arch/arm/mach-exynos/include/mach/map-exynos4.h index 0a22891..666a824 100644..100755 --- a/arch/arm/mach-exynos/include/mach/map-exynos4.h +++ b/arch/arm/mach-exynos/include/mach/map-exynos4.h @@ -32,6 +32,10 @@ #define EXYNOS4212_PA_I2S1 0x13960000 #define EXYNOS4212_PA_I2S2 0x13970000 +/* NAND */ +#define EXYNOS4_PA_NAND (0x0CE00000) +#define S5P_PA_NAND EXYNOS4_PA_NAND + #define EXYNOS4_PA_PCM0 0x03840000 #define EXYNOS4_PA_PCM1 0x13980000 #define EXYNOS4_PA_PCM2 0x13990000 @@ -316,4 +320,9 @@ #define S5P_SZ_UART SZ_256 +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define EXYNOS4_PA_MODEMIF (0x13A00000) +#define S5P_PA_MODEMIF EXYNOS4_PA_MODEMIF +#endif + #endif /* __ASM_ARCH_MAP_EXYNOS4_H */ diff --git a/arch/arm/mach-exynos/include/mach/map-exynos5.h b/arch/arm/mach-exynos/include/mach/map-exynos5.h deleted file mode 100644 index 536356e..0000000 --- a/arch/arm/mach-exynos/include/mach/map-exynos5.h +++ /dev/null @@ -1,295 +0,0 @@ -/* linux/arch/arm/mach-exynos/include/mach/map-exynos5.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS5 - Memory map definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_MAP_EXYNOS5_H -#define __ASM_ARCH_MAP_EXYNOS5_H __FILE__ - -#define EXYNOS5_PA_SYSRAM 0x02020000 -#define EXYNOS5_PA_SYSRAM_NS 0x0204F000 - -#define EXYNOS5_PA_CHIPID 0x10000000 - -#define EXYNOS5_PA_CMU 0x10010000 - -#define EXYNOS5_PA_PMU 0x10040000 - -#define EXYNOS5_PA_HDMI_CEC 0x101B0000 -#define EXYNOS5_PA_SYSTIMER 0x101C0000 -#define EXYNOS5_PA_WATCHDOG 0x101D0000 -#define EXYNOS5_PA_RTC 0x101E0000 - -#define EXYNOS5_PA_COMBINER 0x10440000 - -#define EXYNOS5250_REV0_PA_GIC_CPU 0x10480000 -#define EXYNOS5250_REV0_PA_GIC_DIST 0x10490000 -#define EXYNOS5250_REV1_PA_GIC_CPU 0x10482000 -#define EXYNOS5250_REV1_PA_GIC_DIST 0x10481000 - -#define EXYNOS5_PA_SYSCON 0x10050000 -#define EXYNOS5_PA_TMU 0x10060000 -#define EXYNOS5_PA_ACE 0x10830000 - -#define EXYNOS5_PA_DMC_PHY0 0x10C00000 -#define EXYNOS5_PA_DMC_PHY1 0x10C10000 -#define EXYNOS5_PA_DMC 0x10DD0000 - -#define EXYNOS5_PA_PPMU_DDR_C 0x10C40000 -#define EXYNOS5_PA_PPMU_DDR_R1 0x10C50000 -#define EXYNOS5_PA_PPMU_CPU 0x10C60000 -#define EXYNOS5_PA_PPMU_DDR_L 0x10CB0000 -#define EXYNOS5_PA_PPMU_RIGHT0_BUS 0x13660000 - -#define EXYNOS5_PA_C2C 0x10E00000 -#define EXYNOS5_PA_C2C_CP 0x10E40000 - -#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000 -#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000 -#define EXYNOS5_PA_SYSMMU_2D 0x10A60000 -#define EXYNOS5_PA_SYSMMU_MFC_R 0x11200000 -#define EXYNOS5_PA_SYSMMU_MFC_L 0x11210000 -#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000 -#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000 -#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000 -#define EXYNOS5_PA_SYSMMU_IOP 0x12360000 -#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000 -#define EXYNOS5_PA_SYSMMU_GPS 0x12630000 -#define EXYNOS5_PA_SYSMMU_ISP 0x13260000 -#define EXYNOS5_PA_SYSMMU_DRC 0x13270000 -#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000 -#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000 -#define EXYNOS5_PA_SYSMMU_FD 0x132A0000 -#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000 -#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000 -#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000 -#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000 -#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000 -#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000 -#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000 -#define EXYNOS5_PA_SYSMMU_LITE2 0x13CA0000 -#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000 -#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000 -#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000 -#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000 -#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000 -#define EXYNOS5_PA_SYSMMU_TV 0x14650000 - -#define EXYNOS5_PA_FIMG2D 0x10850000 -#define EXYNOS5_PA_MFC 0x11000000 - -#define EXYNOS5_PA_GPIO1 0x11400000 -#define EXYNOS5_PA_GPIO2 0x13400000 -#define EXYNOS5_PA_GPIO3 0x10D10000 -#define EXYNOS5_PA_GPIO4 0x03860000 - -#define EXYNOS5_PA_G3D 0x11800000 - -#define EXYNOS5_PA_HSMMC(x) (0x12200000 + ((x) * 0x10000)) -#define EXYNOS5_PA_DWMCI 0x12240000 - -#define EXYNOS5_PA_SS_UDC 0x1200C100 -#define EXYNOS5_PA_SS_DRD 0x12000000 -#define EXYNOS5_PA_SS_PHY 0x12100000 -#define EXYNOS5_PA_EHCI 0x12110000 -#define EXYNOS5_PA_OHCI 0x12120000 -#define EXYNOS5_PA_HSPHY 0x12130000 -#define EXYNOS5_PA_HSOTG 0x12140000 - -#define EXYNOS5_PA_SATA_PHY_CTRL 0x12170000 -#define EXYNOS5_PA_SATA_PHY_I2C 0x121D0000 -#define EXYNOS5_PA_SATA_BASE 0x122F0000 - -#define EXYNOS5_PA_SROMC 0x12250000 -#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) - -#define EXYNOS5_PA_UART 0x12C00000 - -#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000)) -#define EXYNOS5_PA_IIC_HDMIPHY 0x12CE0000 - -#define EXYNOS5_PA_ADC 0x12D10000 - -#define EXYNOS5_PA_SPI0 0x12D20000 -#define EXYNOS5_PA_SPI1 0x12D30000 -#define EXYNOS5_PA_SPI2 0x12D40000 - -#define EXYNOS5_PA_TIMER 0x12DD0000 - -#define EXYNOS5_PA_FIMD0 0x13800000 -#define EXYNOS5_PA_FIMD1 0x14400000 -#define EXYNOS5_PA_MIXER 0x14450000 -#define EXYNOS5_PA_DSIM0 0x14500000 -#define EXYNOS5_PA_DP 0x145B0000 -#define EXYNOS5_PA_HDMI 0x14530000 - -#define EXYNOS5_PA_FIMC_IS 0x13000000 - -#define EXYNOS5_PA_FIMC_LITE0 0x13C00000 -#define EXYNOS5_PA_FIMC_LITE1 0x13C10000 -#define EXYNOS5_PA_FIMC_LITE2 0x13C90000 - -#define EXYNOS5_PA_MIPI_CSIS0 0x13C20000 -#define EXYNOS5_PA_MIPI_CSIS1 0x13C30000 - -#define EXYNOS5_PA_GSC0 0x13E00000 -#define EXYNOS5_PA_GSC1 0x13E10000 -#define EXYNOS5_PA_GSC2 0x13E20000 -#define EXYNOS5_PA_GSC3 0x13E30000 - -#define EXYNOS5_PA_ROTATOR 0x11c00000 - -#define EXYNOS5_PA_SDRAM 0x40000000 - -#define EXYNOS5_PA_NS_MDMA0 0x10800000 -#define EXYNOS5_PA_NS_MDMA1 0x11c10000 -#define EXYNOS5_PA_PDMA0 0x121a0000 -#define EXYNOS5_PA_PDMA1 0x121b0000 - -#define EXYNOS5_PA_AUDSS 0x03810000 -#define EXYNOS5_PA_I2S0 0x03830000 -#define EXYNOS5_PA_I2S1 0x12D60000 -#define EXYNOS5_PA_I2S2 0x12D70000 - -#define EXYNOS5_PA_PCM0 0x03840000 -#define EXYNOS5_PA_PCM1 0x12D80000 -#define EXYNOS5_PA_PCM2 0x12D90000 - -#define EXYNOS5_PA_AC97 0x12DA0000 - -#define EXYNOS5_PA_SPDIF 0x12DB0000 -#define EXYNOS4_PA_JPEG 0x11E00000 - -#define EXYNOS5_PA_BTS_CPU 0x10C80000 -#define EXYNOS5_PA_BTS_G3D_ACP 0x10EA0000 -#define EXYNOS5_PA_BTS_MFC0 0x11220000 -#define EXYNOS5_PA_BTS_MFC1 0x11230000 -#define EXYNOS5_PA_BTS_ROTATOR 0x11D60000 -#define EXYNOS5_PA_BTS_MDMA1 0x11D70000 -#define EXYNOS5_PA_BTS_JPEG 0x11F40000 -#define EXYNOS5_PA_BTS_GSCL0 0x13EC0000 -#define EXYNOS5_PA_BTS_GSCL1 0x13ED0000 -#define EXYNOS5_PA_BTS_GSCL2 0x13EE0000 -#define EXYNOS5_PA_BTS_GSCL3 0x13EF0000 -#define EXYNOS5_PA_BTS_DISP10 0x14660000 -#define EXYNOS5_PA_BTS_DISP11 0x14670000 -#define EXYNOS5_PA_BTS_TV0 0x14690000 -#define EXYNOS5_PA_BTS_TV1 0x146A0000 -#define EXYNOS5_PA_BTS_C2C 0x10c90000 -#define EXYNOS5_PA_FBM_DDR_R1 0x10c30000 -#define EXYNOS5_PA_FBM_DDR_R0 0x10dc0000 -#define EXYNOS5_PA_BTS_FIMC_ISP 0x13300000 -#define EXYNOS5_PA_BTS_FIMC_SCALER_C 0x13320000 -#define EXYNOS5_PA_BTS_FIMC_SCALER_P 0x13330000 -#define EXYNOS5_PA_BTS_FIMC_FD 0x13340000 -#define EXYNOS5_PA_BTS_FIMC_ODC 0x13370000 -#define EXYNOS5_PA_BTS_FIMC_DIS0 0x13380000 -#define EXYNOS5_PA_BTS_FIMC_DIS1 0x13390000 -#define EXYNOS5_PA_BTS_FIMC_3DNR 0x133A0000 - -/* Compatibiltiy Defines */ - -#define EXYNOS_PA_DWMCI EXYNOS5_PA_DWMCI - -#define EXYNOS_PA_SPI0 EXYNOS5_PA_SPI0 -#define EXYNOS_PA_SPI1 EXYNOS5_PA_SPI1 -#define EXYNOS_PA_SPI2 EXYNOS5_PA_SPI2 - -#define S5P_PA_HDMI_CEC EXYNOS5_PA_HDMI_CEC - -#define S3C_PA_HSMMC0 EXYNOS5_PA_HSMMC(0) -#define S3C_PA_HSMMC1 EXYNOS5_PA_HSMMC(1) -#define S3C_PA_HSMMC2 EXYNOS5_PA_HSMMC(2) -#define S3C_PA_HSMMC3 EXYNOS5_PA_HSMMC(3) - -#define EXYNOS_PA_AUDSS EXYNOS5_PA_AUDSS -#define EXYNOS_PA_I2S0 EXYNOS5_PA_I2S0 -#define EXYNOS_PA_I2S1 EXYNOS5_PA_I2S1 -#define EXYNOS_PA_I2S2 EXYNOS5_PA_I2S2 - -#define EXYNOS_PA_PCM0 EXYNOS5_PA_PCM0 -#define EXYNOS_PA_PCM1 EXYNOS5_PA_PCM1 -#define EXYNOS_PA_PCM2 EXYNOS5_PA_PCM2 - -#define EXYNOS_PA_AC97 EXYNOS5_PA_AC97 - -#define EXYNOS_PA_SPDIF EXYNOS5_PA_SPDIF - -#define EXYNOS_PA_FIMC_LITE0 EXYNOS5_PA_FIMC_LITE0 -#define EXYNOS_PA_FIMC_LITE1 EXYNOS5_PA_FIMC_LITE1 -#define EXYNOS_PA_FIMC_LITE2 EXYNOS5_PA_FIMC_LITE2 - -#define EXYNOS_PA_ROTATOR EXYNOS5_PA_ROTATOR - -#define EXYNOS_PA_C2C EXYNOS5_PA_C2C -#define EXYNOS_PA_C2C_CP EXYNOS5_PA_C2C_CP - -#define S3C_PA_IIC EXYNOS5_PA_IIC(0) -#define S3C_PA_IIC1 EXYNOS5_PA_IIC(1) -#define S3C_PA_IIC2 EXYNOS5_PA_IIC(2) -#define S3C_PA_IIC3 EXYNOS5_PA_IIC(3) -#define S3C_PA_IIC4 EXYNOS5_PA_IIC(4) -#define S3C_PA_IIC5 EXYNOS5_PA_IIC(5) -#define S3C_PA_IIC6 EXYNOS5_PA_IIC(6) -#define S3C_PA_IIC7 EXYNOS5_PA_IIC(7) -#define SAMSUNG_PA_ADC EXYNOS5_PA_ADC -#define S5P_PA_IIC_HDMIPHY EXYNOS5_PA_IIC_HDMIPHY -#define S3C_PA_WDT EXYNOS5_PA_WATCHDOG -#define S3C_PA_RTC EXYNOS5_PA_RTC -#define S5P_PA_CHIPID EXYNOS5_PA_CHIPID -#define S5P_PA_SYSCON EXYNOS5_PA_SYSCON -#define S5P_PA_SROMC EXYNOS5_PA_SROMC -#define S5P_PA_TIMER EXYNOS5_PA_TIMER -#define S5P_PA_HSOTG EXYNOS5_PA_HSOTG -#define S5P_PA_MFC EXYNOS5_PA_MFC -#define S5P_PA_HSPHY EXYNOS5_PA_HSPHY -#define S5P_PA_EHCI EXYNOS5_PA_EHCI -#define S5P_PA_OHCI EXYNOS5_PA_OHCI -#define S5P_PA_FIMD0 EXYNOS5_PA_FIMD0 -#define S5P_PA_FIMD1 EXYNOS5_PA_FIMD1 -#define S5P_PA_MIXER EXYNOS5_PA_MIXER -#define S5P_PA_DP EXYNOS5_PA_DP -#define S5P_PA_HDMI EXYNOS5_PA_HDMI -#define S5P_PA_SDRAM EXYNOS5_PA_SDRAM -#define S5P_PA_FIMG2D EXYNOS5_PA_FIMG2D - -#define S5P_PA_MDMA0 EXYNOS5_PA_NS_MDMA0 -#define S5P_PA_MDMA1 EXYNOS5_PA_NS_MDMA1 -#define S5P_PA_PDMA0 EXYNOS5_PA_PDMA0 -#define S5P_PA_PDMA1 EXYNOS5_PA_PDMA1 -#define S5P_PA_DSIM0 EXYNOS5_PA_DSIM0 -#define S5P_PA_JPEG EXYNOS4_PA_JPEG -#define S5P_PA_MIPI_CSIS0 EXYNOS5_PA_MIPI_CSIS0 -#define S5P_PA_MIPI_CSIS1 EXYNOS5_PA_MIPI_CSIS1 - -#define S5P_PA_ACE EXYNOS5_PA_ACE -#define S5P_PA_TMU EXYNOS5_PA_TMU -/* UART */ - -#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) - -#define S3C_PA_UART EXYNOS5_PA_UART - -#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) -#define S5P_PA_UART0 S5P_PA_UART(0) -#define S5P_PA_UART1 S5P_PA_UART(1) -#define S5P_PA_UART2 S5P_PA_UART(2) -#define S5P_PA_UART3 S5P_PA_UART(3) -#define S5P_PA_UART4 S5P_PA_UART(4) - -#define S5P_SZ_HDMI_CEC SZ_64K - -#define S5P_SZ_UART SZ_256 - -#define S5P_SZ_MIXER SZ_64K -#define S5P_SZ_HDMI SZ_1M -#define S5P_SZ_IIC_HDMIPHY SZ_64K - -#endif /* __ASM_ARCH_MAP_EXYNOS5_H */ diff --git a/arch/arm/mach-exynos/include/mach/mdm2.h b/arch/arm/mach-exynos/include/mach/mdm2.h index 78ca88f..61d875c 100644 --- a/arch/arm/mach-exynos/include/mach/mdm2.h +++ b/arch/arm/mach-exynos/include/mach/mdm2.h @@ -13,10 +13,34 @@ #ifndef _ARCH_ARM_MACH_MSM_MDM2_H #define _ARCH_ARM_MACH_MSM_MDM2_H +struct mdm_vddmin_resource { + int rpm_id; + int ap2mdm_vddmin_gpio; + unsigned int modes; + unsigned int drive_strength; + int mdm2ap_vddmin_gpio; +}; + struct mdm_platform_data { char *mdm_version; int ramdump_delay_ms; - struct platform_device *peripheral_platform_device; + int soft_reset_inverted; + int early_power_on; + int sfr_query; + int no_powerdown_after_ramdumps; + struct mdm_vddmin_resource *vddmin_resource; + struct platform_device *peripheral_platform_device_ehci; + struct platform_device *peripheral_platform_device_ohci; + const unsigned int ramdump_timeout_ms; +}; + +struct mdm_hsic_pm_platform_data { + /* cpu/bus frequency lock */ + atomic_t freqlock; + int (*freq_lock)(struct device *dev); + int (*freq_unlock)(struct device *dev); + + struct device *dev; }; #endif diff --git a/arch/arm/mach-exynos/include/mach/media.h b/arch/arm/mach-exynos/include/mach/media.h index ce0e53e..366d0fe 100644 --- a/arch/arm/mach-exynos/include/mach/media.h +++ b/arch/arm/mach-exynos/include/mach/media.h @@ -26,7 +26,7 @@ #define S5P_MDEV_TVOUT 9 -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) #define S5P_MDEV_PMEM 10 #endif diff --git a/arch/arm/mach-exynos/include/mach/midas-tsp.h b/arch/arm/mach-exynos/include/mach/midas-tsp.h index 4cbee4c..6e71902 100644 --- a/arch/arm/mach-exynos/include/mach/midas-tsp.h +++ b/arch/arm/mach-exynos/include/mach/midas-tsp.h @@ -13,6 +13,8 @@ #if defined(CONFIG_TOUCHSCREEN_MELFAS) #include <linux/platform_data/mms_ts.h> +#elif defined(CONFIG_TOUCHSCREEN_CYTTSP4) +#include <linux/platform_data/cypress_cyttsp4.h> #else #include <linux/melfas_ts.h> #endif @@ -20,7 +22,15 @@ extern int melfas_power(int on); void melfas_set_touch_i2c(void); void melfas_set_touch_i2c_to_gpio(void); +#if defined(CONFIG_TOUCHSCREEN_CYTTSP4) +int cyttsp4_hw_reset(void); +int cyttsp4_hw_power(int on); +int cyttsp4_hw_recov(int on); +int cyttsp4_irq_stat(void); +void midas_tsp_set_platdata(struct touch_platform_data *pdata); +#else void midas_tsp_set_platdata(struct melfas_tsi_platform_data *pdata); +#endif void midas_tsp_init(void); int is_melfas_vdd_on(void); int melfas_mux_fw_flash(bool to_gpios); diff --git a/arch/arm/mach-exynos/include/mach/midas-wacom.h b/arch/arm/mach-exynos/include/mach/midas-wacom.h new file mode 100644 index 0000000..24a0e1c --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/midas-wacom.h @@ -0,0 +1,24 @@ +/* + * linux/arch/arm/mach-exynos/include/mach/midas-wacom.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MIDAS_WACOM_H +#define __MIDAS_WACOM_H __FILE__ + +#include <linux/wacom_i2c.h> + +void midas_wacom_init(void); + +#ifdef CONFIG_CPU_FREQ_GOV_ONDEMAND_FLEXRATE +extern void midas_wacom_request_qos(void *data); +#else +#define midas_wacom_request_qos NULL +#endif + +#endif /* __MIDAS_WACOM_H */ diff --git a/arch/arm/mach-exynos/include/mach/mipi_ddi.h b/arch/arm/mach-exynos/include/mach/mipi_ddi.h index 17fae16..0b8deb1 100644 --- a/arch/arm/mach-exynos/include/mach/mipi_ddi.h +++ b/arch/arm/mach-exynos/include/mach/mipi_ddi.h @@ -58,6 +58,9 @@ struct mipi_ddi_platform_data { unsigned int reset_delay; unsigned int power_on_delay; unsigned int power_off_delay; +#if defined(CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD) + unsigned int lcd_sel_pin; +#endif /* CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD */ }; #endif /* _MIPI_DDI_H */ diff --git a/arch/arm/mach-exynos/include/mach/msm_smd.h b/arch/arm/mach-exynos/include/mach/msm_smd.h new file mode 100644 index 0000000..d896013 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/msm_smd.h @@ -0,0 +1,383 @@ +/* linux/include/asm-arm/arch-msm/msm_smd.h + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland <swetland@google.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MSM_SMD_H +#define __ASM_ARCH_MSM_SMD_H + +#include <linux/io.h> +#include <mach/msm_smsm.h> + +typedef struct smd_channel smd_channel_t; + +#define SMD_MAX_CH_NAME_LEN 20 /* includes null char at end */ + +#define SMD_EVENT_DATA 1 +#define SMD_EVENT_OPEN 2 +#define SMD_EVENT_CLOSE 3 +#define SMD_EVENT_STATUS 4 +#define SMD_EVENT_REOPEN_READY 5 + +/* + * SMD Processor ID's. + * + * For all processors that have both SMSM and SMD clients, + * the SMSM Processor ID and the SMD Processor ID will + * be the same. In cases where a processor only supports + * SMD, the entry will only exist in this enum. + */ +enum { + SMD_APPS = SMSM_APPS, + SMD_MODEM = SMSM_MODEM, + SMD_Q6 = SMSM_Q6, + SMD_WCNSS = SMSM_WCNSS, + SMD_DSPS = SMSM_DSPS, + SMD_MODEM_Q6_FW, + SMD_RPM, + NUM_SMD_SUBSYSTEMS, +}; + +enum { + SMD_APPS_MODEM = 0, + SMD_APPS_QDSP, + SMD_MODEM_QDSP, + SMD_APPS_DSPS, + SMD_MODEM_DSPS, + SMD_QDSP_DSPS, + SMD_APPS_WCNSS, + SMD_MODEM_WCNSS, + SMD_QDSP_WCNSS, + SMD_DSPS_WCNSS, + SMD_APPS_Q6FW, + SMD_MODEM_Q6FW, + SMD_QDSP_Q6FW, + SMD_DSPS_Q6FW, + SMD_WCNSS_Q6FW, + SMD_APPS_RPM, + SMD_MODEM_RPM, + SMD_QDSP_RPM, + SMD_WCNSS_RPM, + SMD_NUM_TYPE, + SMD_LOOPBACK_TYPE = 100, + +}; + +/* + * SMD IRQ Configuration + * + * Used to initialize IRQ configurations from platform data + * + * @irq_name: irq_name to query platform data + * @irq_id: initialized to -1 in platform data, stores actual irq id on + * successful registration + * @out_base: if not null then settings used for outgoing interrupt + * initialied from platform data + */ + +struct smd_irq_config { + /* incoming interrupt config */ + const char *irq_name; + unsigned long flags; + int irq_id; + const char *device_name; + const void *dev_id; + + /* outgoing interrupt config */ + uint32_t out_bit_pos; + void __iomem *out_base; + uint32_t out_offset; +}; + +/* + * SMD subsystem configurations + * + * SMD subsystems configurations for platform data. This contains the + * M2A and A2M interrupt configurations for both SMD and SMSM per + * subsystem. + * + * @subsys_name: name of subsystem passed to PIL + * @irq_config_id: unique id for each subsystem + * @edge: maps to actual remote subsystem edge + * + */ +struct smd_subsystem_config { + unsigned irq_config_id; + const char *subsys_name; + int edge; + + struct smd_irq_config smd_int; + struct smd_irq_config smsm_int; + +}; + +/* + * Subsystem Restart Configuration + * + * @disable_smsm_reset_handshake + */ +struct smd_subsystem_restart_config { + int disable_smsm_reset_handshake; +}; + +struct smd_platform { + uint32_t num_ss_configs; + struct smd_subsystem_config *smd_ss_configs; + struct smd_subsystem_restart_config *smd_ssr_config; +}; + +#ifdef CONFIG_MSM_SMD +/* warning: notify() may be called before open returns */ +int smd_open(const char *name, smd_channel_t **ch, void *priv, + void (*notify)(void *priv, unsigned event)); + +int smd_close(smd_channel_t *ch); + +/* passing a null pointer for data reads and discards */ +int smd_read(smd_channel_t *ch, void *data, int len); +int smd_read_from_cb(smd_channel_t *ch, void *data, int len); +/* Same as smd_read() but takes a data buffer from userspace + * The function might sleep. Only safe to call from user context + */ +int smd_read_user_buffer(smd_channel_t *ch, void *data, int len); + +/* Write to stream channels may do a partial write and return +** the length actually written. +** Write to packet channels will never do a partial write -- +** it will return the requested length written or an error. +*/ +int smd_write(smd_channel_t *ch, const void *data, int len); +/* Same as smd_write() but takes a data buffer from userspace + * The function might sleep. Only safe to call from user context + */ +int smd_write_user_buffer(smd_channel_t *ch, const void *data, int len); + +int smd_write_avail(smd_channel_t *ch); +int smd_read_avail(smd_channel_t *ch); + +/* Returns the total size of the current packet being read. +** Returns 0 if no packets available or a stream channel. +*/ +int smd_cur_packet_size(smd_channel_t *ch); + + +#if 0 +/* these are interruptable waits which will block you until the specified +** number of bytes are readable or writable. +*/ +int smd_wait_until_readable(smd_channel_t *ch, int bytes); +int smd_wait_until_writable(smd_channel_t *ch, int bytes); +#endif + +/* these are used to get and set the IF sigs of a channel. + * DTR and RTS can be set; DSR, CTS, CD and RI can be read. + */ +int smd_tiocmget(smd_channel_t *ch); +int smd_tiocmset(smd_channel_t *ch, unsigned int set, unsigned int clear); +int +smd_tiocmset_from_cb(smd_channel_t *ch, unsigned int set, unsigned int clear); +int smd_named_open_on_edge(const char *name, uint32_t edge, smd_channel_t **_ch, + void *priv, void (*notify)(void *, unsigned)); + +/* Tells the other end of the smd channel that this end wants to recieve + * interrupts when the written data is read. Read interrupts should only + * enabled when there is no space left in the buffer to write to, thus the + * interrupt acts as notification that space may be avaliable. If the + * other side does not support enabling/disabling interrupts on demand, + * then this function has no effect if called. + */ +void smd_enable_read_intr(smd_channel_t *ch); + +/* Tells the other end of the smd channel that this end does not want + * interrupts when written data is read. The interrupts should be + * disabled by default. If the other side does not support enabling/ + * disabling interrupts on demand, then this function has no effect if + * called. + */ +void smd_disable_read_intr(smd_channel_t *ch); + +/* Starts a packet transaction. The size of the packet may exceed the total + * size of the smd ring buffer. + * + * @ch: channel to write the packet to + * @len: total length of the packet + * + * Returns: + * 0 - success + * -ENODEV - invalid smd channel + * -EACCES - non-packet channel specified + * -EINVAL - invalid length + * -EBUSY - transaction already in progress + * -EAGAIN - no enough memory in ring buffer to start transaction + * -EPERM - unable to sucessfully start transaction due to write error + */ +int smd_write_start(smd_channel_t *ch, int len); + +/* Writes a segment of the packet for a packet transaction. + * + * @ch: channel to write packet to + * @data: buffer of data to write + * @len: length of data buffer + * @user_buf: (0) - buffer from kernelspace (1) - buffer from userspace + * + * Returns: + * number of bytes written + * -ENODEV - invalid smd channel + * -EINVAL - invalid length + * -ENOEXEC - transaction not started + */ +int smd_write_segment(smd_channel_t *ch, void *data, int len, int user_buf); + +/* Completes a packet transaction. Do not call from interrupt context. + * + * @ch: channel to complete transaction on + * + * Returns: + * 0 - success + * -ENODEV - invalid smd channel + * -E2BIG - some ammount of packet is not yet written + */ +int smd_write_end(smd_channel_t *ch); + +/* + * Returns a pointer to the subsystem name or NULL if no + * subsystem name is available. + * + * @type - Edge definition + */ +const char *smd_edge_to_subsystem(uint32_t type); + +/* + * Returns a pointer to the subsystem name given the + * remote processor ID. + * + * @pid Remote processor ID + * @returns Pointer to subsystem name or NULL if not found + */ +const char *smd_pid_to_subsystem(uint32_t pid); +#else + +static inline int smd_open(const char *name, smd_channel_t **ch, void *priv, + void (*notify)(void *priv, unsigned event)) +{ + return -ENODEV; +} + +static inline int smd_close(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_read(smd_channel_t *ch, void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_read_from_cb(smd_channel_t *ch, void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_read_user_buffer(smd_channel_t *ch, void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_write(smd_channel_t *ch, const void *data, int len) +{ + return -ENODEV; +} + +static inline int +smd_write_user_buffer(smd_channel_t *ch, const void *data, int len) +{ + return -ENODEV; +} + +static inline int smd_write_avail(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_read_avail(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_cur_packet_size(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int smd_tiocmget(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline int +smd_tiocmset(smd_channel_t *ch, unsigned int set, unsigned int clear) +{ + return -ENODEV; +} + +static inline int +smd_tiocmset_from_cb(smd_channel_t *ch, unsigned int set, unsigned int clear) +{ + return -ENODEV; +} + +static inline int +smd_named_open_on_edge(const char *name, uint32_t edge, smd_channel_t **_ch, + void *priv, void (*notify)(void *, unsigned)) +{ + return -ENODEV; +} + +static inline void smd_enable_read_intr(smd_channel_t *ch) +{ +} + +static inline void smd_disable_read_intr(smd_channel_t *ch) +{ +} + +static inline int smd_write_start(smd_channel_t *ch, int len) +{ + return -ENODEV; +} + +static inline int +smd_write_segment(smd_channel_t *ch, void *data, int len, int user_buf) +{ + return -ENODEV; +} + +static inline int smd_write_end(smd_channel_t *ch) +{ + return -ENODEV; +} + +static inline const char *smd_edge_to_subsystem(uint32_t type) +{ + return NULL; +} + +static inline const char *smd_pid_to_subsystem(uint32_t pid) +{ + return NULL; +} +#endif + +#endif diff --git a/arch/arm/mach-exynos/include/mach/msm_smsm.h b/arch/arm/mach-exynos/include/mach/msm_smsm.h new file mode 100644 index 0000000..5c3307e --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/msm_smsm.h @@ -0,0 +1,250 @@ +/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ARCH_ARM_MACH_MSM_SMSM_H_ +#define _ARCH_ARM_MACH_MSM_SMSM_H_ + +#include <linux/notifier.h> +#if defined(CONFIG_MSM_N_WAY_SMSM) +enum { + SMSM_APPS_STATE, + SMSM_MODEM_STATE, + SMSM_Q6_STATE, + SMSM_APPS_DEM, + SMSM_WCNSS_STATE = SMSM_APPS_DEM, + SMSM_MODEM_DEM, + SMSM_DSPS_STATE = SMSM_MODEM_DEM, + SMSM_Q6_DEM, + SMSM_POWER_MASTER_DEM, + SMSM_TIME_MASTER_DEM, +}; +extern uint32_t SMSM_NUM_ENTRIES; +#else +enum { + SMSM_APPS_STATE = 1, + SMSM_MODEM_STATE = 3, + SMSM_NUM_ENTRIES, +}; +#endif + +enum { + SMSM_APPS, + SMSM_MODEM, + SMSM_Q6, + SMSM_WCNSS, + SMSM_DSPS, +}; +extern uint32_t SMSM_NUM_HOSTS; + +#define SMSM_INIT 0x00000001 +#define SMSM_OSENTERED 0x00000002 +#define SMSM_SMDWAIT 0x00000004 +#define SMSM_SMDINIT 0x00000008 +#define SMSM_RPCWAIT 0x00000010 +#define SMSM_RPCINIT 0x00000020 +#define SMSM_RESET 0x00000040 +#define SMSM_RSA 0x00000080 +#define SMSM_RUN 0x00000100 +#define SMSM_PWRC 0x00000200 +#define SMSM_TIMEWAIT 0x00000400 +#define SMSM_TIMEINIT 0x00000800 +#define SMSM_PWRC_EARLY_EXIT 0x00001000 +#define SMSM_WFPI 0x00002000 +#define SMSM_SLEEP 0x00004000 +#define SMSM_SLEEPEXIT 0x00008000 +#define SMSM_OEMSBL_RELEASE 0x00010000 +#define SMSM_APPS_REBOOT 0x00020000 +#define SMSM_SYSTEM_POWER_DOWN 0x00040000 +#define SMSM_SYSTEM_REBOOT 0x00080000 +#define SMSM_SYSTEM_DOWNLOAD 0x00100000 +#define SMSM_PWRC_SUSPEND 0x00200000 +#define SMSM_APPS_SHUTDOWN 0x00400000 +#define SMSM_SMD_LOOPBACK 0x00800000 +#define SMSM_RUN_QUIET 0x01000000 +#define SMSM_MODEM_WAIT 0x02000000 +#define SMSM_MODEM_BREAK 0x04000000 +#define SMSM_MODEM_CONTINUE 0x08000000 +#define SMSM_SYSTEM_REBOOT_USR 0x20000000 +#define SMSM_SYSTEM_PWRDWN_USR 0x40000000 +#define SMSM_UNKNOWN 0x80000000 + +#define SMSM_WKUP_REASON_RPC 0x00000001 +#define SMSM_WKUP_REASON_INT 0x00000002 +#define SMSM_WKUP_REASON_GPIO 0x00000004 +#define SMSM_WKUP_REASON_TIMER 0x00000008 +#define SMSM_WKUP_REASON_ALARM 0x00000010 +#define SMSM_WKUP_REASON_RESET 0x00000020 +#define SMSM_A2_FORCE_SHUTDOWN 0x00002000 +#define SMSM_A2_RESET_BAM 0x00004000 + +#define SMSM_VENDOR 0x00020000 + +#define SMSM_A2_POWER_CONTROL 0x00000002 +#define SMSM_A2_POWER_CONTROL_ACK 0x00000800 + +#define SMSM_WLAN_TX_RINGS_EMPTY 0x00000200 +#define SMSM_WLAN_TX_ENABLE 0x00000400 + + +void *smem_alloc(unsigned id, unsigned size); +void *smem_alloc2(unsigned id, unsigned size_in); +void *smem_get_entry(unsigned id, unsigned *size); +int smsm_change_state(uint32_t smsm_entry, + uint32_t clear_mask, uint32_t set_mask); + +/* + * Changes the global interrupt mask. The set and clear masks are re-applied + * every time the global interrupt mask is updated for callback registration + * and de-registration. + * + * The clear mask is applied first, so if a bit is set to 1 in both the clear + * mask and the set mask, the result will be that the interrupt is set. + * + * @smsm_entry SMSM entry to change + * @clear_mask 1 = clear bit, 0 = no-op + * @set_mask 1 = set bit, 0 = no-op + * + * @returns 0 for success, < 0 for error + */ +int smsm_change_intr_mask(uint32_t smsm_entry, + uint32_t clear_mask, uint32_t set_mask); +int smsm_get_intr_mask(uint32_t smsm_entry, uint32_t *intr_mask); +uint32_t smsm_get_state(uint32_t smsm_entry); +int smsm_state_cb_register(uint32_t smsm_entry, uint32_t mask, + void (*notify)(void *, uint32_t old_state, uint32_t new_state), + void *data); +int smsm_state_cb_deregister(uint32_t smsm_entry, uint32_t mask, + void (*notify)(void *, uint32_t, uint32_t), void *data); +int smsm_driver_state_notifier_register(struct notifier_block *nb); +int smsm_driver_state_notifier_unregister(struct notifier_block *nb); +void smsm_print_sleep_info(uint32_t sleep_delay, uint32_t sleep_limit, + uint32_t irq_mask, uint32_t wakeup_reason, uint32_t pending_irqs); +void smsm_reset_modem(unsigned mode); +void smsm_reset_modem_cont(void); +void smd_sleep_exit(void); + +#define SMEM_NUM_SMD_STREAM_CHANNELS 64 +#define SMEM_NUM_SMD_BLOCK_CHANNELS 64 + +enum { + /* fixed items */ + SMEM_PROC_COMM = 0, + SMEM_HEAP_INFO, + SMEM_ALLOCATION_TABLE, + SMEM_VERSION_INFO, + SMEM_HW_RESET_DETECT, + SMEM_AARM_WARM_BOOT, + SMEM_DIAG_ERR_MESSAGE, + SMEM_SPINLOCK_ARRAY, + SMEM_MEMORY_BARRIER_LOCATION, + SMEM_FIXED_ITEM_LAST = SMEM_MEMORY_BARRIER_LOCATION, + + /* dynamic items */ + SMEM_AARM_PARTITION_TABLE, + SMEM_AARM_BAD_BLOCK_TABLE, + SMEM_RESERVE_BAD_BLOCKS, + SMEM_WM_UUID, + SMEM_CHANNEL_ALLOC_TBL, + SMEM_SMD_BASE_ID, + SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_STREAM_CHANNELS, + SMEM_SMEM_LOG_EVENTS, + SMEM_SMEM_STATIC_LOG_IDX, + SMEM_SMEM_STATIC_LOG_EVENTS, + SMEM_SMEM_SLOW_CLOCK_SYNC, + SMEM_SMEM_SLOW_CLOCK_VALUE, + SMEM_BIO_LED_BUF, + SMEM_SMSM_SHARED_STATE, + SMEM_SMSM_INT_INFO, + SMEM_SMSM_SLEEP_DELAY, + SMEM_SMSM_LIMIT_SLEEP, + SMEM_SLEEP_POWER_COLLAPSE_DISABLED, + SMEM_KEYPAD_KEYS_PRESSED, + SMEM_KEYPAD_STATE_UPDATED, + SMEM_KEYPAD_STATE_IDX, + SMEM_GPIO_INT, + SMEM_MDDI_LCD_IDX, + SMEM_MDDI_HOST_DRIVER_STATE, + SMEM_MDDI_LCD_DISP_STATE, + SMEM_LCD_CUR_PANEL, + SMEM_MARM_BOOT_SEGMENT_INFO, + SMEM_AARM_BOOT_SEGMENT_INFO, + SMEM_SLEEP_STATIC, + SMEM_SCORPION_FREQUENCY, + SMEM_SMD_PROFILES, + SMEM_TSSC_BUSY, + SMEM_HS_SUSPEND_FILTER_INFO, + SMEM_BATT_INFO, + SMEM_APPS_BOOT_MODE, + SMEM_VERSION_FIRST, + SMEM_VERSION_SMD = SMEM_VERSION_FIRST, + SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24, + SMEM_OSS_RRCASN1_BUF1, + SMEM_OSS_RRCASN1_BUF2, + SMEM_ID_VENDOR0, + SMEM_ID_VENDOR1, + SMEM_ID_VENDOR2, + SMEM_HW_SW_BUILD_ID, + SMEM_SMD_BLOCK_PORT_BASE_ID, + SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + + SMEM_NUM_SMD_BLOCK_CHANNELS, + SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + + SMEM_NUM_SMD_BLOCK_CHANNELS, + SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + + SMEM_NUM_SMD_BLOCK_CHANNELS, + SMEM_SCLK_CONVERSION, + SMEM_SMD_SMSM_INTR_MUX, + SMEM_SMSM_CPU_INTR_MASK, + SMEM_APPS_DEM_SLAVE_DATA, + SMEM_QDSP6_DEM_SLAVE_DATA, + SMEM_CLKREGIM_BSP, + SMEM_CLKREGIM_SOURCES, + SMEM_SMD_FIFO_BASE_ID, + SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + + SMEM_NUM_SMD_STREAM_CHANNELS, + SMEM_POWER_ON_STATUS_INFO, + SMEM_DAL_AREA, + SMEM_SMEM_LOG_POWER_IDX, + SMEM_SMEM_LOG_POWER_WRAP, + SMEM_SMEM_LOG_POWER_EVENTS, + SMEM_ERR_CRASH_LOG, + SMEM_ERR_F3_TRACE_LOG, + SMEM_SMD_BRIDGE_ALLOC_TABLE, + SMEM_SMDLITE_TABLE, + SMEM_SD_IMG_UPGRADE_STATUS, + SMEM_SEFS_INFO, + SMEM_RESET_LOG, + SMEM_RESET_LOG_SYMBOLS, + SMEM_MODEM_SW_BUILD_ID, + SMEM_SMEM_LOG_MPROC_WRAP, + SMEM_BOOT_INFO_FOR_APPS, + SMEM_SMSM_SIZE_INFO, + SMEM_SMD_LOOPBACK_REGISTER, + SMEM_SSR_REASON_MSS0, + SMEM_SSR_REASON_WCNSS0, + SMEM_SSR_REASON_LPASS0, + SMEM_SSR_REASON_DSPS0, + SMEM_SSR_REASON_VCODEC0, + SMEM_MEM_LAST = SMEM_SSR_REASON_VCODEC0, + SMEM_NUM_ITEMS, +}; + +enum { + SMEM_APPS_Q6_SMSM = 3, + SMEM_Q6_APPS_SMSM = 5, + SMSM_NUM_INTR_MUX = 8, +}; + +int smsm_check_for_modem_crash(void); +void *smem_find(unsigned id, unsigned size); +void *smem_get_entry(unsigned id, unsigned *size); + +#endif diff --git a/arch/arm/mach-exynos/include/mach/p4-input.h b/arch/arm/mach-exynos/include/mach/p4-input.h index b7ecddb..37c71c7 100644 --- a/arch/arm/mach-exynos/include/mach/p4-input.h +++ b/arch/arm/mach-exynos/include/mach/p4-input.h @@ -18,4 +18,8 @@ void p4_key_init(void); extern void synaptics_ts_charger_infom(bool en); #endif +#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S) +extern void ts_charger_infom(bool en); +#endif + #endif /* __P4_INPUT_H */ diff --git a/arch/arm/mach-exynos/include/mach/pld_pdata.h b/arch/arm/mach-exynos/include/mach/pld_pdata.h new file mode 100644 index 0000000..da0c064 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/pld_pdata.h @@ -0,0 +1,2015 @@ +unsigned char fpga_bin[] = { +0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, +0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x22, 0x11, 0x8B, 0x01, 0x06, 0x00}; diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index a0aab7c..a8ce9ff 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -148,6 +148,8 @@ #define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) #define EXYNOS4_CLKOUT_CMU_CPU EXYNOS_CLKREG(0x14A00) +#define EXYNOS4_EMA_CONF EXYNOS_CLKREG(0x15008) + #define EXYNOS4_PMREG(x) (S5P_VA_PMU + (x)) #define EXYNOS4_MIPI_CONTROL0 EXYNOS4_PMREG(0x0710) diff --git a/arch/arm/mach-exynos/include/mach/sec_debug.h b/arch/arm/mach-exynos/include/mach/sec_debug.h index 53ca0cb..1beb973 100644 --- a/arch/arm/mach-exynos/include/mach/sec_debug.h +++ b/arch/arm/mach-exynos/include/mach/sec_debug.h @@ -80,6 +80,8 @@ extern void __sec_debug_task_log(int cpu, struct task_struct *task); extern void __sec_debug_irq_log(unsigned int irq, void *fn, int en); extern void __sec_debug_work_log(struct worker *worker, struct work_struct *work, work_func_t f); +extern void __sec_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en); static inline void sec_debug_task_log(int cpu, struct task_struct *task) { @@ -100,18 +102,25 @@ static inline void sec_debug_work_log(struct worker *worker, __sec_debug_work_log(worker, work, f); } -#ifdef CONFIG_SEC_DEBUG_SOFTIRQ_LOG -static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en) +static inline void sec_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en) { +#ifdef CONFIG_SEC_DEBUG_HRTIMER_LOG if (unlikely(sec_debug_level.en.kernel_fault)) - __sec_debug_irq_log(irq, fn, en); + __sec_debug_hrtimer_log(timer, fn, en); +#endif } -#else + static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en) { -} +#ifdef CONFIG_SEC_DEBUG_SOFTIRQ_LOG + if (unlikely(sec_debug_level.en.kernel_fault)) + __sec_debug_irq_log(irq, fn, en); #endif +} + #else + static inline void sec_debug_task_log(int cpu, struct task_struct *task) { } @@ -125,6 +134,11 @@ static inline void sec_debug_work_log(struct worker *worker, { } +static inline void sec_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en) +{ +} + static inline void sec_debug_softirq_log(unsigned int irq, void *fn, int en) { } @@ -181,7 +195,6 @@ static inline void debug_rwsemaphore_up_log(struct rw_semaphore *sem) enum sec_debug_aux_log_idx { SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE, - SEC_DEBUG_AUXLOG_LOGBUF_LOCK_CHANGE, SEC_DEBUG_AUXLOG_ITEM_MAX, }; @@ -191,6 +204,10 @@ extern void sec_debug_aux_log(int idx, char *fmt, ...); #define sec_debug_aux_log(idx, ...) do { } while (0) #endif +#if defined(CONFIG_MACH_Q1_BD) +extern int sec_debug_panic_handler_safe(void *buf); +#endif + extern void read_lcd_register(void); #endif /* SEC_DEBUG_H */ diff --git a/arch/arm/mach-exynos/include/mach/sec_modem.h b/arch/arm/mach-exynos/include/mach/sec_modem.h index 097726b..4a7fbe8 100644 --- a/arch/arm/mach-exynos/include/mach/sec_modem.h +++ b/arch/arm/mach-exynos/include/mach/sec_modem.h @@ -5,14 +5,23 @@ enum hsic_lpa_states { STATE_HSIC_LPA_ENTER, STATE_HSIC_LPA_WAKE, STATE_HSIC_LPA_PHY_INIT, + STATE_HSIC_LPA_CHECK, }; #if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) void set_host_states(struct platform_device *pdev, int type); void set_hsic_lpa_states(int states); int get_cp_active_state(void); +#elif defined(CONFIG_MDM_HSIC_PM) +int set_hsic_lpa_states(int states); #else #define set_hsic_lpa_states(states) do {} while (0); #endif +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_BAFFIN) +bool modem_using_hub(void); +#else +static inline bool modem_using_hub(void) { return false; } +#endif + #endif diff --git a/arch/arm/mach-exynos/include/mach/secmem.h b/arch/arm/mach-exynos/include/mach/secmem.h index 42a8575..dfa86a4 100644 --- a/arch/arm/mach-exynos/include/mach/secmem.h +++ b/arch/arm/mach-exynos/include/mach/secmem.h @@ -40,7 +40,7 @@ struct secmem_crypto_driver_ftn { struct secmem_region { char *virt_addr; - unsigned long phys_addr; + dma_addr_t phys_addr; unsigned long len; }; diff --git a/arch/arm/mach-exynos/include/mach/sromc-exynos4.h b/arch/arm/mach-exynos/include/mach/sromc-exynos4.h new file mode 100644 index 0000000..69e2550 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/sromc-exynos4.h @@ -0,0 +1,253 @@ +/* + * arch/arm/mach-exynos/sromc.h + */ + +#ifndef __SROMC_H__ +#define __SROMC_H__ + +#include <linux/clk.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-srom.h> +#include <mach/gpio.h> +#include <mach/gpio-exynos4.h> +#include <mach/regs-mem.h> + +#define SROM_CS0_BASE 0x04000000 +#define SROM_CS1_BASE 0x05000000 +#define SROM_CS2_BASE 0x06000000 +#define SROM_CS3_BASE 0x07000000 +#define SROM_WIDTH 0x01000000 + +#define GPIO_SFN_SROMC S3C_GPIO_SFN(2) + +#define GPIO_SROMC_CSN EXYNOS4_GPY0(0) +#define GPIO_SROMC_CSN0 EXYNOS4_GPY0(0) +#define GPIO_SROMC_CSN1 EXYNOS4_GPY0(1) +#define GPIO_SROMC_CSN2 EXYNOS4_GPY0(2) +#define GPIO_SROMC_CSN3 EXYNOS4_GPY0(3) +#define GPIO_SROMC_REN EXYNOS4_GPY0(4) +#define GPIO_SROMC_WEN EXYNOS4_GPY0(5) +#define GPIO_SROMC_LBN EXYNOS4_GPY1(0) +#define GPIO_SROMC_UBN EXYNOS4_GPY1(1) +#define GPIO_SROMC_ADDR_BUS_L EXYNOS4_GPY3(0) +#define GPIO_SROMC_ADDR_BUS_H EXYNOS4_GPY4(0) +#define GPIO_SROMC_DATA_BUS_L EXYNOS4_GPY5(0) +#define GPIO_SROMC_DATA_BUS_H EXYNOS4_GPY6(0) + +/* SROMC configuration */ +struct sromc_bus_cfg { + unsigned addr_bits; /* Width of address bus in bits */ + unsigned data_bits; /* Width of data bus in bits */ + unsigned byte_acc; /* Byte access */ +}; + +/* SROMC bank attributes in BW (Bus width and Wait control) register */ +enum sromc_bank_attr { + SROMC_DATA_16 = 0x1, /* 16-bit data bus */ + SROMC_BYTE_ADDR = 0x2, /* Byte base address */ + SROMC_WAIT_EN = 0x4, /* Wait enabled */ + SROMC_BYTE_EN = 0x8, /* Byte access enabled */ + SROMC_ATTR_MASK = 0xF +}; + +/* SROMC bank configuration */ +struct sromc_bank_cfg { + unsigned csn; /* CSn # */ + unsigned attr; /* SROMC bank attributes */ + unsigned size; /* Size of a memory */ + unsigned addr; /* Start address (physical) */ +}; + +/* SROMC bank access timing configuration */ +struct sromc_timing_cfg { + u32 tacs; /* Address set-up before CSn */ + u32 tcos; /* Chip selection set-up before OEn */ + u32 tacc; /* Access cycle */ + u32 tcoh; /* Chip selection hold on OEn */ + u32 tcah; /* Address holding time after CSn */ + u32 tacp; /* Page mode access cycle at Page mode */ + u32 pmc; /* Page Mode config */ +}; + +static unsigned int sfn = GPIO_SFN_SROMC; + +/** + * sromc_enable + * + * Enables SROM controller (SROMC) block + * + */ +static int sromc_enable(void) +{ + struct clk *clk = NULL; + + /* SROMC clk enable */ + clk = clk_get(NULL, "sromc"); + if (!clk) { + pr_err("%s: ERR! SROMC clock gate fail\n", __func__); + return -EINVAL; + } + + clk_enable(clk); + return 0; +} + +/** + * sromc_config_demux_gpio + * @bc: pointer to an sromc_bus_cfg + * + * Configures GPIO pins for REn, WEn, LBn, UBn, address bus, and data bus + * as demux mode + * + * Returns 0 if there is no error + * + */ +static int sromc_config_demux_gpio(struct sromc_bus_cfg *bc) +{ + unsigned int addr_bits = bc->addr_bits; + unsigned int data_bits = bc->data_bits; + unsigned int byte_acc = bc->byte_acc; + unsigned int bits; + + pr_err("[SROMC] %s: addr_bits %d, data_bits %d, byte_acc %d\n", + __func__, addr_bits, data_bits, byte_acc); + + /* Configure address bus */ + switch (addr_bits) { + case 1 ... EXYNOS4_GPIO_Y3_NR: + bits = addr_bits; + s3c_gpio_cfgrange_nopull(GPIO_SROMC_ADDR_BUS_L, bits, sfn); + break; + + case (EXYNOS4_GPIO_Y3_NR + 1) ... 16: + bits = EXYNOS4_GPIO_Y3_NR; + s3c_gpio_cfgrange_nopull(GPIO_SROMC_ADDR_BUS_L, bits, sfn); + bits = (addr_bits - EXYNOS4_GPIO_Y3_NR); + s3c_gpio_cfgrange_nopull(GPIO_SROMC_ADDR_BUS_H, bits, sfn); + break; + + default: + pr_err("[SROMC] %s: ERR! invalid addr_bits %d\n", + __func__, addr_bits); + return -EINVAL; + } + + /* Configure data bus (8 or 16 bits) */ + switch (data_bits) { + case 8: + s3c_gpio_cfgrange_nopull(GPIO_SROMC_DATA_BUS_L, 8, sfn); + break; + + case 16: + s3c_gpio_cfgrange_nopull(GPIO_SROMC_DATA_BUS_L, 8, sfn); + s3c_gpio_cfgrange_nopull(GPIO_SROMC_DATA_BUS_H, 8, sfn); + break; + + default: + pr_err("[SROMC] %s: ERR! invalid data_bits %d\n", + __func__, data_bits); + return -EINVAL; + } + + /* Configure REn */ + s3c_gpio_cfgpin(GPIO_SROMC_REN, sfn); + s3c_gpio_setpull(GPIO_SROMC_REN, S3C_GPIO_PULL_NONE); + + /* Configure WEn */ + s3c_gpio_cfgpin(GPIO_SROMC_WEN, sfn); + s3c_gpio_setpull(GPIO_SROMC_WEN, S3C_GPIO_PULL_NONE); + + /* Configure LBn, UBn */ + if (byte_acc) { + s3c_gpio_cfgpin(GPIO_SROMC_LBN, sfn); + s3c_gpio_setpull(GPIO_SROMC_LBN, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_SROMC_UBN, sfn); + s3c_gpio_setpull(GPIO_SROMC_UBN, S3C_GPIO_PULL_NONE); + } + + return 0; +} + +/** + * sromc_config_csn_gpio + * @csn: CSn number (0 to 3) + * + * Configures GPIO pins for CSn + * + * Returns 0 if there is no error + * + */ +static int sromc_config_csn_gpio(unsigned int csn) +{ + unsigned int pin = GPIO_SROMC_CSN + csn; + + pr_err("[SROMC] %s: for CSn%d\n", __func__, csn); + + if (csn > 4) { + pr_err("[SROMC] %s: ERR! CSn%d invalid\n", __func__, csn); + return -EINVAL; + } + + /* Configure CSn GPIO pin */ + s3c_gpio_cfgpin(pin, sfn); + s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); + + return 0; +} + +/** + * sromc_config_access_attr + * @csn: CSn number + * @attr: SROMC attribute for this CSn + * + * Configures SROMC attribute for a CSn + * + */ +static void sromc_config_access_attr(unsigned int csn, unsigned int attr) +{ + unsigned int bw = 0; /* Bus width and Wait control */ + + pr_err("[SROMC] %s: for CSn%d\n", __func__, csn); + + bw = __raw_readl(S5P_SROM_BW); + pr_err("[SROMC] %s: old BW setting = 0x%08X\n", __func__, bw); + + /* Configure BW control field for the CSn */ + bw &= ~(SROMC_ATTR_MASK << (csn << 2)); + bw |= (attr << (csn << 2)); + writel(bw, S5P_SROM_BW); + + /* Verify SROMC settings */ + bw = __raw_readl(S5P_SROM_BW); + pr_err("[SROMC] %s: new BW setting = 0x%08X\n", __func__, bw); +} + +/** + * sromc_config_access_timing + * @csn: CSn number + * @tm_cfg: pointer to an sromc_timing_cfg + * + * Configures SROMC access timing register + * + */ +static void sromc_config_access_timing(unsigned int csn, + struct sromc_timing_cfg *tm_cfg) +{ + void __iomem *bank_sfr = S5P_SROM_BC0 + (4 * csn); + unsigned int bc = 0; /* Bank Control */ + + bc = __raw_readl(bank_sfr); + pr_err("[SROMC] %s: old BC%d setting = 0x%08X\n", __func__, csn, bc); + + /* Configure memory access timing for the CSn */ + bc = tm_cfg->tacs | tm_cfg->tcos | tm_cfg->tacc | + tm_cfg->tcoh | tm_cfg->tcah | tm_cfg->tacp | tm_cfg->pmc; + writel(bc, bank_sfr); + + /* Verify SROMC settings */ + bc = __raw_readl(bank_sfr); + pr_err("[SROMC] %s: new BC%d setting = 0x%08X\n", __func__, csn, bc); +} + +#endif + diff --git a/arch/arm/mach-exynos/include/mach/subsystem_restart.h b/arch/arm/mach-exynos/include/mach/subsystem_restart.h index f7becef..a72fa62 100644 --- a/arch/arm/mach-exynos/include/mach/subsystem_restart.h +++ b/arch/arm/mach-exynos/include/mach/subsystem_restart.h @@ -39,6 +39,7 @@ struct subsys_data { struct mutex shutdown_lock; struct mutex powerup_lock; + bool ongoing; void *restart_order; struct subsys_data *single_restart_list[1]; diff --git a/arch/arm/mach-exynos/include/mach/t0-power.h b/arch/arm/mach-exynos/include/mach/t0-power.h new file mode 100644 index 0000000..1bd3a53 --- /dev/null +++ b/arch/arm/mach-exynos/include/mach/t0-power.h @@ -0,0 +1,37 @@ +/* + * t0-power.h - Power Management of T0 Project + * + * Copyright (C) 2011 Samsung Electrnoics + * Chiwoong Byun <woong.byun@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MIDAS_POWER_H +#define __MIDAS_POWER_H __FILE__ + +#if defined(CONFIG_MFD_S5M_CORE) && defined(CONFIG_MFD_MAX77686) +extern struct s5m_platform_data exynos4_s5m8767_info; +extern struct max77686_platform_data exynos4_max77686_info; +#elif defined(CONFIG_MFD_S5M_CORE) +extern struct s5m_platform_data exynos4_s5m8767_info; +#else +extern struct max77686_platform_data exynos4_max77686_info; +#endif + +void midas_power_init(void); +void midas_power_set_muic_pdata(void *, int); +void midas_power_gpio_init(void); +#endif /* __MIDAS_POWER_H */ diff --git a/arch/arm/mach-exynos/include/mach/tdmb_pdata.h b/arch/arm/mach-exynos/include/mach/tdmb_pdata.h index ce8a986..eb5c162 100644 --- a/arch/arm/mach-exynos/include/mach/tdmb_pdata.h +++ b/arch/arm/mach-exynos/include/mach/tdmb_pdata.h @@ -25,7 +25,11 @@ struct tdmb_platform_data { void (*gpio_on) (void); void (*gpio_off)(void); - int irq; + unsigned int irq; +#if defined(CONFIG_TDMB_ANT_DET) + unsigned int gpio_ant_det; + unsigned int irq_ant_det; +#endif }; #endif #endif diff --git a/arch/arm/mach-exynos/include/mach/usb_switch.h b/arch/arm/mach-exynos/include/mach/usb_switch.h index de054b6..a5340e5 100644 --- a/arch/arm/mach-exynos/include/mach/usb_switch.h +++ b/arch/arm/mach-exynos/include/mach/usb_switch.h @@ -20,9 +20,14 @@ extern int usb_switch_lock(void); extern int usb_switch_trylock(void); extern void usb_switch_unlock(void); +extern enum usb_path_t usb_switch_get_path(void); extern void usb_switch_set_path(enum usb_path_t path); extern void usb_switch_clr_path(enum usb_path_t path); extern void set_usb_connection_state(bool connected); +#ifdef CONFIG_TARGET_LOCALE_KOR +extern int px_switch_get_usb_lock_state(void); +#endif + #endif diff --git a/arch/arm/mach-exynos/include/mach/usbdiag.h b/arch/arm/mach-exynos/include/mach/usbdiag.h index d1e3605..5f0cecf 100644 --- a/arch/arm/mach-exynos/include/mach/usbdiag.h +++ b/arch/arm/mach-exynos/include/mach/usbdiag.h @@ -28,6 +28,8 @@ #define USB_DIAG_DISCONNECT 1 #define USB_DIAG_WRITE_DONE 2 #define USB_DIAG_READ_DONE 3 +// zero_pky.patch by jagadish +#define USB_DIAG_QXDM_DISCONNECT 4 struct diag_request { char *buf; diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c index 1241dfc..f69edf1 100644 --- a/arch/arm/mach-exynos/irq-eint.c +++ b/arch/arm/mach-exynos/irq-eint.c @@ -99,6 +99,10 @@ static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type) newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; break; + case IRQ_TYPE_NONE: + printk(KERN_DEBUG "None irq type\n"); + break; + default: printk(KERN_ERR "No such irq type %d", type); return -EINVAL; diff --git a/arch/arm/mach-exynos/m3-gpio.c b/arch/arm/mach-exynos/m3-gpio.c new file mode 100644 index 0000000..f300b29 --- /dev/null +++ b/arch/arm/mach-exynos/m3-gpio.c @@ -0,0 +1,516 @@ +/* + * linux/arch/arm/mach-exynos/c2-gpio.c + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - GPIO setting in set board + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/serial_core.h> +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-serial.h> +#include <mach/gpio-midas.h> +#include <mach/pmu.h> + +extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +static struct gpio_init_data c2_init_gpios[] = { + {GPIO_GSENSE_SDA_18V, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_GSENSE_SCL_18V, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_NFC_SDA_18V, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_NFC_SCL_18V, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + + {GPIO_PMIC_SDA, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_PMIC_SCL, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_PMIC_DVS1, + S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_PMIC_IRQ, + S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_NFC_IRQ, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + + {GPIO_BT_WAKE, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_BT_HOST_WAKE, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_nPOWER, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + + {GPIO_BUCK2_SEL, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {GPIO_BUCK3_SEL, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {GPIO_BUCK4_SEL, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + + {GPIO_WLAN_EN, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + {GPIO_WLAN_HOST_WAKE, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {GPIO_WLAN_SDIO_CMD, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_WLAN_SDIO_D0, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_WLAN_SDIO_D1, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_WLAN_SDIO_D2, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {GPIO_WLAN_SDIO_D3, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + + {GPIO_FUEL_ALERT, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + + {GPIO_V_BUS_INT, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {GPIO_WPC_INT, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + + {GPIO_CAM_MCLK, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, + {GPIO_VTCAM_MCLK, + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, + + /* NC */ + {EXYNOS4_GPA0(4), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPA0(5), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPA1(4), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPA1(5), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + + {EXYNOS4_GPY0(0), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY0(1), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY0(2), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY0(3), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY0(4), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY0(5), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY1(2), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY1(3), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY2(1), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPY2(2), + S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* GPIO_AP2MDM_PMIC_RESET_N */ + {EXYNOS4_GPY2(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV4}, +}; + + +static unsigned int c2_sleep_gpio_table[][3] = { + {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* GPF1(6) T0 LTE prev level, if not mdm notice it as crash */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* GPX1(0) VDDMIN (pda active) set to low at Sleep */ + {EXYNOS4_GPX1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_DOWN}, + /* GPX3(2) T0 LTE HOST PORT PWR, hold previous level */ + {EXYNOS4_GPX3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#ifdef CONFIG_TARGET_LOCALE_EUR + {EXYNOS4_GPX1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */ +#endif + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + /* AP2MDM_PMIC_RESET_N */ + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_PREV, + S3C_GPIO_PULL_UP}, + {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + /* Exynos4212 specific gpio */ + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* GPM3(3) set to pull-down for reducing sleep current consumption */ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +}; + +static unsigned int c2_sleep_gpio_table_rev01[][3] = { + /* */ +}; + + +struct sleep_table { + unsigned int (*ptr)[3]; + unsigned int size; +}; + +#define GPIO_TABLE(_ptr) \ +{ \ + .ptr = _ptr, \ + .size = ARRAY_SIZE(_ptr) \ +} \ + +#define GPIO_TABLE_NULL \ +{ \ + .ptr = NULL, \ + .size = 0 \ +} \ + +static struct sleep_table c2_sleep_table[] = { + GPIO_TABLE(c2_sleep_gpio_table), /* Rev0.0(0x0) */ + GPIO_TABLE(c2_sleep_gpio_table_rev01), /* Rev0.0(0x1) */ +}; + + +static void config_sleep_gpio_table(unsigned int array_size, + unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +static void c2_config_sleep_gpio_table(void) +{ + int i; + int index = min(ARRAY_SIZE(c2_sleep_table), system_rev + 1); + + for (i = 0; i < index; i++) { + if (c2_sleep_table[i].ptr == NULL) + continue; + + config_sleep_gpio_table(c2_sleep_table[i].size, + c2_sleep_table[i].ptr); + } +} + + +/* To save power consumption, gpio pin set before enterling sleep */ +void midas_config_sleep_gpio_table(void) +{ + c2_config_sleep_gpio_table(); +} + +/* Intialize gpio set in midas board */ +void midas_config_gpio_table(void) +{ + u32 i, gpio; + + printk(KERN_DEBUG "%s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(c2_init_gpios); i++) { + gpio = c2_init_gpios[i].num; + if (gpio <= EXYNOS4212_GPV4(1)) { + s3c_gpio_cfgpin(gpio, c2_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, c2_init_gpios[i].pud); + + if (c2_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, c2_init_gpios[i].val); + + s5p_gpio_set_drvstr(gpio, c2_init_gpios[i].drv); + } + } +} diff --git a/arch/arm/mach-exynos/mach-midas.c b/arch/arm/mach-exynos/mach-midas.c index 4f21630..41ab1fd 100644 --- a/arch/arm/mach-exynos/mach-midas.c +++ b/arch/arm/mach-exynos/mach-midas.c @@ -36,11 +36,11 @@ #ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE #include <linux/battery/max17047_fuelgauge.h> #endif -#if defined(CONFIG_BATTERY_SAMSUNG) || defined(CONFIG_BATTERY_SAMSUNG_S2PLUS) +#if defined(CONFIG_BATTERY_SAMSUNG) #include <linux/power_supply.h> #include <linux/battery/samsung_battery.h> #endif -#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS) +#if defined(CONFIG_CHARGER_MAX8922_U1) #include <linux/power/max8922_charger_u1.h> #endif #ifdef CONFIG_STMPE811_ADC @@ -51,6 +51,10 @@ #include <linux/delay.h> #include <linux/bootmem.h> +#ifdef CONFIG_DMA_CMA +#include <linux/dma-contiguous.h> +#endif + #include <asm/mach/arch.h> #include <asm/mach-types.h> @@ -81,6 +85,8 @@ #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) #include <mach/tdmb_pdata.h> +#elif defined(CONFIG_ISDBT) +#include <media/isdbt_pdata.h> #endif #include <mach/map.h> @@ -122,8 +128,10 @@ struct s3cfb_extdsp_lcd { #include <mach/sec_debug.h> #include <mach/gpio-midas.h> -#ifdef CONFIG_MACH_GC1 +#if defined(CONFIG_MACH_GC1) #include <mach/gc1-power.h> +#elif defined(CONFIG_MACH_T0) +#include <mach/t0-power.h> #else #include <mach/midas-power.h> #endif @@ -137,19 +145,22 @@ struct s3cfb_extdsp_lcd { #include <mach/midas-lcd.h> #include <mach/midas-sound.h> -#ifdef CONFIG_USB_HOST_NOTIFY -#include <linux/host_notify.h> +#ifdef CONFIG_INPUT_WACOM +#include <mach/midas-wacom.h> #endif -#if defined(CONFIG_PHONE_IPC_SPI) -#include <linux/phone_svn/ipc_spi.h> -#include <linux/irq.h> +#ifdef CONFIG_USB_HOST_NOTIFY +#include <linux/host_notify.h> #endif #ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH #include <linux/i2c/touchkey_i2c.h> #endif +#if defined(CONFIG_MACH_GC1) +#include <mach/gc1-jack.h> +#endif + #include "board-mobile.h" /* Following are default values for UCON, ULCON and UFCON UART registers */ @@ -226,8 +237,9 @@ static struct spi_board_info spi1_board_info[] __initdata = { }; #endif -#if defined(CONFIG_PHONE_IPC_SPI) \ - || defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#if defined(CONFIG_LINK_DEVICE_SPI) \ + || defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) \ + || defined(CONFIG_ISDBT) || defined(CONFIG_LINK_DEVICE_PLD) static struct s3c64xx_spi_csinfo spi2_csi[] = { [0] = { .line = EXYNOS4_GPC1(2), @@ -246,9 +258,19 @@ static struct spi_board_info spi2_board_info[] __initdata = { .mode = SPI_MODE_0, .controller_data = &spi2_csi[0], }, +#elif defined(CONFIG_ISDBT) + { + .modalias = "fc8150_spi", + .platform_data = NULL, + .max_speed_hz = 5000000, + .bus_num = 2, + .chip_select = 0, + .mode = SPI_MODE_0, + .controller_data = &spi2_csi[0], + }, #else { - .modalias = "ipc_spi", + .modalias = "modem_if_spi", .platform_data = NULL, .bus_num = 2, .chip_select = 0, @@ -266,37 +288,39 @@ static struct i2c_board_info i2c_devs8_emul[]; #ifdef CONFIG_KEYBOARD_CYPRESS_TOUCH static void touchkey_init_hw(void) { -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW)\ -|| defined(CONFIG_MACH_C1) -#if defined(CONFIG_MACH_M0_CHNOPEN) || defined(CONFIG_MACH_M0_HKTW)\ -|| defined(CONFIG_TARGET_LOCALE_KOR) -/* do nothing */ +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) +#if defined(CONFIG_MACH_M0_CHNOPEN) || defined(CONFIG_MACH_M0_HKTW) || \ + defined(CONFIG_TARGET_LOCALE_KOR) + /* do nothing */ #elif defined(CONFIG_MACH_C1) #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) if (system_rev < 8) - return ; + return; #elif defined(CONFIG_MACH_C1_KOR_LGT) if (system_rev < 5) - return ; + return; #else if (system_rev < 7) - return ; -#endif + return; +#endif #else - /*rev 1.0*/ if (system_rev < 11) - return ; + return; /* rev 1.0 */ #endif #endif -#if defined(CONFIG_MACH_S2PLUS)\ -|| defined(CONFIG_TARGET_LOCALE_KOR)\ -|| defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW)\ -|| defined(CONFIG_MACH_C1) + +#if defined(CONFIG_TARGET_LOCALE_KOR) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_BAFFIN) gpio_request(GPIO_3_TOUCH_EN, "gpio_3_touch_en"); #if defined(CONFIG_MACH_C1_KOR_LGT) gpio_request(GPIO_3_TOUCH_LDO_EN, "gpio_3_touch_ldo_en"); #endif #endif + gpio_request(GPIO_3_TOUCH_INT, "3_TOUCH_INT"); s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE); s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT); @@ -308,7 +332,6 @@ static void touchkey_init_hw(void) s3c_gpio_setpull(GPIO_3_TOUCH_SCL, S3C_GPIO_PULL_DOWN); s3c_gpio_setpull(GPIO_3_TOUCH_SDA, S3C_GPIO_PULL_DOWN); - } static int touchkey_suspend(void) @@ -321,10 +344,10 @@ static int touchkey_suspend(void) if (regulator_is_enabled(regulator)) regulator_force_disable(regulator); - #if defined(CONFIG_MACH_C1_KOR_LGT) +#if defined(CONFIG_MACH_C1_KOR_LGT) gpio_request(GPIO_3_TOUCH_LDO_EN, "gpio_3_touch_ldo_en"); gpio_direction_output(GPIO_3_TOUCH_LDO_EN, 0); - #endif +#endif s3c_gpio_setpull(GPIO_3_TOUCH_SCL, S3C_GPIO_PULL_DOWN); s3c_gpio_setpull(GPIO_3_TOUCH_SDA, S3C_GPIO_PULL_DOWN); @@ -360,7 +383,8 @@ static int touchkey_power_on(bool on) if (on) { gpio_direction_output(GPIO_3_TOUCH_INT, 1); - irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), IRQF_TRIGGER_FALLING); + irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), + IRQF_TRIGGER_FALLING); s3c_gpio_cfgpin(GPIO_3_TOUCH_INT, S3C_GPIO_SFN(0xf)); s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE); } else @@ -421,8 +445,12 @@ static void tdmb_set_config_poweron(void) s3c_gpio_cfgpin(GPIO_TDMB_EN, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE); gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW); - - s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_SFN(GPIO_TDMB_INT_AF)); +#if defined(CONFIG_MACH_T0) + s3c_gpio_cfgpin(GPIO_TDMB_RST_N, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TDMB_RST_N, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW); +#endif + s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_SFN(0xf)); s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(GPIO_TDMB_SPI_CLK, S3C_GPIO_SFN(5)); @@ -438,6 +466,12 @@ static void tdmb_set_config_poweroff(void) s3c_gpio_setpull(GPIO_TDMB_EN, S3C_GPIO_PULL_NONE); gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW); +#if defined(CONFIG_MACH_T0) + s3c_gpio_cfgpin(GPIO_TDMB_RST_N, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TDMB_RST_N, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW); +#endif + s3c_gpio_cfgpin(GPIO_TDMB_INT, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_TDMB_INT, S3C_GPIO_PULL_NONE); gpio_set_value(GPIO_TDMB_INT, GPIO_LEVEL_LOW); @@ -452,6 +486,15 @@ static void tdmb_gpio_on(void) gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW); usleep_range(1000, 1000); gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_HIGH); + +#if defined(CONFIG_MACH_T0) + usleep_range(1000, 1000); + gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW); + usleep_range(2000, 2000); + gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_HIGH); + usleep_range(1000, 1000); +#endif + } static void tdmb_gpio_off(void) @@ -459,6 +502,10 @@ static void tdmb_gpio_off(void) printk(KERN_DEBUG "tdmb_gpio_off\n"); tdmb_set_config_poweroff(); +#if defined(CONFIG_MACH_T0) + gpio_set_value(GPIO_TDMB_RST_N, GPIO_LEVEL_LOW); + usleep_range(1000, 1000); +#endif gpio_set_value(GPIO_TDMB_EN, GPIO_LEVEL_LOW); } @@ -478,92 +525,123 @@ static struct platform_device tdmb_device = { static int __init tdmb_dev_init(void) { +#if defined(CONFIG_MACH_T0) && defined(CONFIG_TDMB_ANT_DET) + unsigned int tdmb_ant_det_gpio; + unsigned int tdmb_ant_det_irq; + if (system_rev >= 6) { + tdmb_ant_det_gpio = GPIO_TDMB_ANT_DET_REV08; + tdmb_ant_det_irq = GPIO_TDMB_IRQ_ANT_DET_REV08; + } else { + s5p_register_gpio_interrupt(GPIO_TDMB_ANT_DET); + tdmb_ant_det_gpio = GPIO_TDMB_ANT_DET; + tdmb_ant_det_irq = GPIO_TDMB_IRQ_ANT_DET; + } + s3c_gpio_cfgpin(tdmb_ant_det_gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(tdmb_ant_det_gpio, S3C_GPIO_PULL_NONE); + tdmb_pdata.gpio_ant_det = tdmb_ant_det_gpio; + tdmb_pdata.irq_ant_det = tdmb_ant_det_irq; +#endif tdmb_set_config_poweroff(); + s5p_register_gpio_interrupt(GPIO_TDMB_INT); tdmb_pdata.irq = GPIO_TDMB_IRQ; platform_device_register(&tdmb_device); return 0; } -#endif +#elif defined(CONFIG_ISDBT) +static void isdbt_set_config_poweron(void) +{ + s3c_gpio_cfgpin(GPIO_ISDBT_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_ISDBT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_ISDBT_EN, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_ISDBT_RST_N, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_ISDBT_RST_N, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_ISDBT_RST_N, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_ISDBT_INT, S3C_GPIO_SFN(GPIO_ISDBT_INT_AF)); + s3c_gpio_setpull(GPIO_ISDBT_INT, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_ISDBT_SPI_CLK, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(GPIO_ISDBT_SPI_MISO, S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin(GPIO_ISDBT_SPI_MOSI, S3C_GPIO_SFN(5)); + s3c_gpio_setpull(GPIO_ISDBT_SPI_CLK, S3C_GPIO_PULL_DOWN); + s3c_gpio_setpull(GPIO_ISDBT_SPI_MISO, S3C_GPIO_PULL_DOWN); + s3c_gpio_setpull(GPIO_ISDBT_SPI_MOSI, S3C_GPIO_PULL_DOWN); + + printk(KERN_DEBUG "isdbt_set_config_poweron\n"); -#if defined(CONFIG_PHONE_IPC_SPI) -static void ipc_spi_cfg_gpio(void); +} +static void isdbt_set_config_poweroff(void) +{ + s3c_gpio_cfgpin(GPIO_ISDBT_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_ISDBT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_ISDBT_EN, GPIO_LEVEL_LOW); -static struct ipc_spi_platform_data ipc_spi_data = { - .gpio_ipc_mrdy = GPIO_IPC_MRDY, - .gpio_ipc_srdy = GPIO_IPC_SRDY, - .gpio_ipc_sub_mrdy = GPIO_IPC_SUB_MRDY, - .gpio_ipc_sub_srdy = GPIO_IPC_SUB_SRDY, + s3c_gpio_cfgpin(GPIO_ISDBT_RST_N, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_ISDBT_RST_N, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_ISDBT_RST_N, GPIO_LEVEL_LOW); - .cfg_gpio = ipc_spi_cfg_gpio, -}; + s3c_gpio_cfgpin(GPIO_ISDBT_INT, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_ISDBT_INT, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_ISDBT_INT, GPIO_LEVEL_LOW); -static struct resource ipc_spi_res[] = { - [0] = { - .start = IRQ_IPC_SRDY, - .end = IRQ_IPC_SRDY, - .flags = IORESOURCE_IRQ, - }, -}; -static struct platform_device ipc_spi_device = { - .name = "onedram", - .id = -1, - .num_resources = ARRAY_SIZE(ipc_spi_res), - .resource = ipc_spi_res, - .dev = { - .platform_data = &ipc_spi_data, - }, -}; + printk(KERN_DEBUG "isdbt_set_config_poweroff\n"); +} -static void ipc_spi_cfg_gpio(void) +static void isdbt_gpio_on(void) { - int err = 0; + printk(KERN_DEBUG "isdbt_gpio_on\n"); - unsigned gpio_ipc_mrdy = ipc_spi_data.gpio_ipc_mrdy; - unsigned gpio_ipc_srdy = ipc_spi_data.gpio_ipc_srdy; - unsigned gpio_ipc_sub_mrdy = ipc_spi_data.gpio_ipc_sub_mrdy; - unsigned gpio_ipc_sub_srdy = ipc_spi_data.gpio_ipc_sub_srdy; + isdbt_set_config_poweron(); - err = gpio_request(gpio_ipc_mrdy, "IPC_MRDY"); - if (err) { - printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", - "IPC_MRDY", err); - } else { - gpio_direction_output(gpio_ipc_mrdy, 0); - } + gpio_set_value(GPIO_ISDBT_EN, GPIO_LEVEL_LOW); + usleep_range(1000, 1000); + gpio_set_value(GPIO_ISDBT_EN, GPIO_LEVEL_HIGH); - err = gpio_request(gpio_ipc_srdy, "IPC_SRDY"); - if (err) { - printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", - "IPC_SRDY", err); - } else { - gpio_direction_input(gpio_ipc_srdy); - s3c_gpio_cfgpin(gpio_ipc_srdy, S3C_GPIO_SFN(0xF)); - s3c_gpio_setpull(gpio_ipc_srdy, S3C_GPIO_PULL_DOWN); - } + usleep_range(1000, 1000); + gpio_set_value(GPIO_ISDBT_RST_N, GPIO_LEVEL_LOW); + usleep_range(2000, 2000); + gpio_set_value(GPIO_ISDBT_RST_N, GPIO_LEVEL_HIGH); + usleep_range(1000, 1000); - err = gpio_request(gpio_ipc_sub_mrdy, "IPC_SUB_MRDY"); - if (err) { - printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", - "IPC_SUB_MRDY", err); - } else { - gpio_direction_output(gpio_ipc_sub_mrdy, 0); - } +} - err = gpio_request(gpio_ipc_sub_srdy, "IPC_SUB_SRDY"); - if (err) { - printk(KERN_ERR "ipc_spi_cfg_gpio - fail to request gpio %s : %d\n", - "IPC_SUB_SRDY", err); - } else { - gpio_direction_input(gpio_ipc_sub_srdy); - s3c_gpio_cfgpin(gpio_ipc_sub_srdy, S3C_GPIO_SFN(0xF)); - s3c_gpio_setpull(gpio_ipc_sub_srdy, S3C_GPIO_PULL_DOWN); - } +static void isdbt_gpio_off(void) +{ + printk(KERN_DEBUG "isdbt_gpio_off\n"); - irq_set_irq_type(gpio_to_irq(GPIO_IPC_SRDY), IRQ_TYPE_EDGE_RISING); - irq_set_irq_type(gpio_to_irq(GPIO_IPC_SUB_SRDY), IRQ_TYPE_EDGE_RISING); + isdbt_set_config_poweroff(); + + gpio_set_value(GPIO_ISDBT_RST_N, GPIO_LEVEL_LOW); + usleep_range(1000, 1000); + + gpio_set_value(GPIO_ISDBT_EN, GPIO_LEVEL_LOW); +} + +static struct isdbt_platform_data isdbt_pdata = { + .gpio_on = isdbt_gpio_on, + .gpio_off = isdbt_gpio_off, +}; + +static struct platform_device isdbt_device = { + .name = "isdbt", + .id = -1, + .dev = { + .platform_data = &isdbt_pdata, + }, +}; + +static int __init isdbt_dev_init(void) +{ + isdbt_set_config_poweroff(); + s5p_register_gpio_interrupt(GPIO_ISDBT_INT); + isdbt_pdata.irq = GPIO_ISDBT_IRQ; + platform_device_register(&isdbt_device); + + printk(KERN_DEBUG "isdbt_dev_init\n"); + + return 0; } #endif @@ -747,7 +825,12 @@ static struct s3c_mshci_platdata exynos4_mshc_pdata __initdata = { .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50 | MMC_CAP_CMD23, - .host_caps2 = MMC_CAP2_PACKED_CMD, +#ifdef CONFIG_MMC_MSHCI_ENABLE_CACHE + .host_caps2 = MMC_CAP2_ADAPT_PACKED | MMC_CAP2_PACKED_CMD | + MMC_CAP2_CACHE_CTRL, +#else + .host_caps2 = MMC_CAP2_ADAPT_PACKED | MMC_CAP2_PACKED_CMD, +#endif #elif defined(CONFIG_EXYNOS4_MSHC_8BIT) .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, @@ -792,16 +875,20 @@ static void __init smdk4212_usbgadget_init(void) struct android_usb_platform_data *android_pdata = s3c_device_android_usb.dev.platform_data; if (android_pdata) { -#if defined(CONFIG_MACH_M0_CTC) - /*FOR CTC PC-MODEM START*/ - unsigned int newluns = 3; - /*FOR CTC PC-MODEM END*/ + unsigned int cdfs = 0; +#if defined(CONFIG_MACH_M0_CTC) || defined(CONFIG_MACH_T0_CHN_CTC) + unsigned int newluns = 1; + cdfs = 1; /* China CTC required CDFS */ +#elif defined(CONFIG_MACH_T0_USA_VZW) + unsigned int newluns = 0; + cdfs = 1; /* VZW required CDFS */ #else unsigned int newluns = 2; #endif printk(KERN_DEBUG "usb: %s: default luns=%d, new luns=%d\n", __func__, android_pdata->nluns, newluns); android_pdata->nluns = newluns; + android_pdata->cdfs_support = cdfs; } else { printk(KERN_DEBUG "usb: %s android_pdata is not available\n", __func__); @@ -810,7 +897,7 @@ static void __init smdk4212_usbgadget_init(void) s5p_usbgadget_set_platdata(pdata); #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ - defined(CONFIG_MACH_C1_KOR_LGT) + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_BAFFIN) pdata = s3c_device_usbgadget.dev.platform_data; if (pdata) { /* Squelch Threshold Tune [13:11] (111 : -20%) */ @@ -824,16 +911,58 @@ static void __init smdk4212_usbgadget_init(void) } #endif +#ifdef CONFIG_MACH_GC1 +static void motor_init_hw(void) +{ + if (gpio_request(EXYNOS4_GPD0(0), "VIBTONE_PWM") < 0) + printk(KERN_ERR "[VIB] gpio requst is failed\n"); + else { + gpio_direction_output(EXYNOS4_GPD0(0), 0); + printk(KERN_DEBUG "[VIB] gpio request is succeed\n"); + } +} + +static void motor_en(bool enable) +{ + gpio_direction_output(EXYNOS4_GPD0(0), enable); + printk(KERN_DEBUG "[VIB] motor_enabled GPIO GPD0(0) : %d\n", + gpio_get_value(EXYNOS4_GPD0(0))); +} +#endif +#ifdef CONFIG_MACH_BAFFIN +static void motor_en(bool enable) +{ + gpio_direction_output(EXYNOS4_GPD0(0), enable); + printk(KERN_DEBUG "[VIB] motor_enabled GPIO GPD0(0) : %d\n", + gpio_get_value(EXYNOS4_GPD0(0))); +} +#endif +#if defined(CONFIG_MACH_T0) && defined(CONFIG_TARGET_LOCALE_KOR) +static void motor_en(bool enable) +{ + gpio_direction_output(EXYNOS4_GPC0(3), enable); + printk(KERN_DEBUG "[VIB] motor_enabled GPIO GPC0(3) : %d\n", + gpio_get_value(EXYNOS4_GPC0(3))); +} +#endif + #ifdef CONFIG_MFD_MAX77693 #ifdef CONFIG_VIBETONZ static struct max77693_haptic_platform_data max77693_haptic_pdata = { - .max_timeout = 10000, - .duty = 37050, - .period = 38054, +#ifdef CONFIG_MACH_GC1 + .reg2 = MOTOR_ERM, + .pwm_id = 1, + .init_hw = motor_init_hw, + .motor_en = motor_en, +#else .reg2 = MOTOR_LRA | EXT_PWM | DIVIDER_128, + .pwm_id = 0, .init_hw = NULL, .motor_en = NULL, - .pwm_id = 0, +#endif + .max_timeout = 10000, + .duty = 35500, + .period = 37904, .regulator_name = "vmotor", }; #endif @@ -859,12 +988,12 @@ static struct max77693_led_platform_data max77693_led_pdata = { .leds[2].name = "torch-sec1", .leds[2].id = MAX77693_TORCH_LED_1, .leds[2].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB, - .leds[2].brightness = 0x0F, + .leds[2].brightness = 0x03, .leds[3].name = "torch-sec2", .leds[3].id = MAX77693_TORCH_LED_2, - .leds[3].cntrl_mode = MAX77693_LED_CTRL_BY_I2C, - .leds[3].brightness = 0x0F, + .leds[3].cntrl_mode = MAX77693_LED_CTRL_BY_FLASHSTB, + .leds[3].brightness = 0x04, }; #endif @@ -874,11 +1003,15 @@ static struct max77693_charger_platform_data max77693_charger_pdata = { #ifdef CONFIG_BATTERY_WPC_CHARGER .wpc_irq_gpio = GPIO_WPC_INT, #if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) || \ - defined(CONFIG_MACH_C1VZW) + defined(CONFIG_MACH_M3) || defined(CONFIG_MACH_T0) .vbus_irq_gpio = GPIO_V_BUS_INT, #endif +#if defined(CONFIG_MACH_T0) + .wc_pwr_det = true, +#else .wc_pwr_det = false, #endif +#endif }; #endif @@ -898,10 +1031,6 @@ static bool is_muic_default_uart_path_cp(void) if (system_rev == 4) return true; #endif -#ifdef CONFIG_MACH_S2PLUS - if (system_rev >= 2) - return true; -#endif return false; } @@ -925,7 +1054,7 @@ struct max77693_platform_data exynos4_max77693_info = { }; #endif -#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS) +#if defined(CONFIG_CHARGER_MAX8922_U1) static int max8922_cfg_gpio(void) { printk(KERN_INFO "[Battery] %s called.\n", __func__); @@ -955,7 +1084,7 @@ static struct platform_device max8922_device_charger = { .id = -1, .dev.platform_data = &max8922_pdata, }; -#endif /* CONFIG_CHARGER_MAX8922_U1 || CONFIG_CHARGER_MAX8922_S2PLUS */ +#endif /* CONFIG_CHARGER_MAX8922_U1 */ /* I2C0 */ static struct i2c_board_info i2c_devs0[] __initdata = { @@ -984,7 +1113,7 @@ static struct i2c_board_info i2c_devs5[] __initdata = { I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)), }, }; -#else +#elif !defined(CONFIG_MACH_T0_EUR_OPEN) || !defined(CONFIG_MACH_T0_CHN_OPEN) static struct i2c_board_info i2c_devs5[] __initdata = { #ifdef CONFIG_REGULATOR_MAX8997 { @@ -999,12 +1128,6 @@ static struct i2c_board_info i2c_devs5[] __initdata = { I2C_BOARD_INFO("max77686", (0x12 >> 1)), .platform_data = &exynos4_max77686_info, }, -#elif defined(CONFIG_REGULATOR_S5M8767) - /* s5m on i2c5 other than M1 board */ - { - I2C_BOARD_INFO("s5m87xx", (0x12 >> 1)), - .platform_data = &exynos4_s5m8767_info, - }, #endif }; #endif /* CONFIG_MACH_GC1 */ @@ -1040,6 +1163,26 @@ struct s3c2410_platform_i2c default_i2c5_data __initdata = { #endif +#ifdef CONFIG_S3C_DEV_I2C6 +static struct i2c_board_info i2c_devs6[] __initdata = { +}; +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) +static void i2c6_mhl_ddc_cfg_gpio(struct platform_device *dev) +{ + s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2, + S3C_GPIO_SFN(4), S3C_GPIO_PULL_NONE); +} +struct s3c2410_platform_i2c default_i2c6_data __initdata = { + .bus_num = 6, + .flags = 0, + .slave_addr = 0x10, + .frequency = 100*1000, + .sda_delay = 100, + .cfg_gpio = i2c6_mhl_ddc_cfg_gpio, +}; +#endif /* CONFIG_MACH_T0_EUR_OPEN */ +#endif /* CONFIG_S3C_DEV_I2C6 */ + #ifdef CONFIG_MACH_GC1 static struct i2c_board_info i2c_devs7[] __initdata = { { @@ -1055,9 +1198,10 @@ static struct i2c_board_info i2c_devs7_s5m[] __initdata = { }; #else static struct i2c_board_info i2c_devs7[] __initdata = { -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_BAFFIN) #if defined(CONFIG_REGULATOR_MAX77686) /* max77686 on i2c7 with M1 board */ { I2C_BOARD_INFO("max77686", (0x12 >> 1)), @@ -1084,7 +1228,6 @@ static struct platform_device bcm4334_bluetooth_device = { }; #endif -#if !defined(CONFIG_MACH_M0_GRANDECTC) static struct i2c_gpio_platform_data gpio_i2c_data8 = { .sda_pin = GPIO_3_TOUCH_SDA, .scl_pin = GPIO_3_TOUCH_SCL, @@ -1095,7 +1238,6 @@ struct platform_device s3c_device_i2c8 = { .id = 8, .dev.platform_data = &gpio_i2c_data8, }; -#endif /* I2C8 */ static struct i2c_board_info i2c_devs8_emul[] = { @@ -1120,29 +1262,12 @@ static struct i2c_board_info i2c_devs11_emul[] __initdata = { }; /* I2C12 */ -#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \ - && !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3) +#if defined(CONFIG_PN65N_NFC) && \ + !defined(CONFIG_MACH_C1) && !defined(CONFIG_MACH_BAFFIN) static struct i2c_board_info i2c_devs12_emul[] __initdata = { }; #endif -#if defined(CONFIG_MACH_S2PLUS) -static struct i2c_gpio_platform_data gpio_i2c_data13 = { - .sda_pin = GPIO_VT_CAM_SDA_18V, - .scl_pin = GPIO_VT_CAM_SCL_18V, -}; - -struct platform_device s3c_device_i2c13 = { - .name = "i2c-gpio", - .id = 13, - .dev.platform_data = &gpio_i2c_data13, -}; - -/* I2C13 */ -static struct i2c_board_info i2c_devs13_emul[] __initdata = { -}; -#endif - #ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE static struct i2c_gpio_platform_data gpio_i2c_data14 = { .sda_pin = GPIO_FUEL_SDA, @@ -1168,7 +1293,7 @@ static struct i2c_board_info i2c_devs14_emul[] __initdata = { }; #endif -#if !defined(CONFIG_MACH_M0_GRANDECTC) +#ifdef CONFIG_SAMSUNG_MHL /* I2C15 */ static struct i2c_gpio_platform_data gpio_i2c_data15 = { .sda_pin = GPIO_MHL_SDA_1_8V, @@ -1189,6 +1314,7 @@ static struct i2c_board_info i2c_devs15_emul[] __initdata = { }; /* I2C16 */ +#if !defined(CONFIG_MACH_T0) && !defined(CONFIG_MACH_M3) static struct i2c_gpio_platform_data gpio_i2c_data16 = { .sda_pin = GPIO_MHL_DSDA_2_8V, .scl_pin = GPIO_MHL_DSCL_2_8V, @@ -1199,15 +1325,17 @@ struct platform_device s3c_device_i2c16 = { .id = 16, .dev.platform_data = &gpio_i2c_data16, }; +#endif /* !defined(CONFIG_MACH_T0) */ static struct i2c_board_info i2c_devs16_emul[] __initdata = { }; #endif -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \ - defined(CONFIG_MACH_GC1) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_BAFFIN) static struct i2c_gpio_platform_data gpio_i2c_data17 = { .sda_pin = GPIO_IF_PMIC_SDA, .scl_pin = GPIO_IF_PMIC_SCL, @@ -1231,9 +1359,9 @@ static struct i2c_board_info i2c_devs17_emul[] __initdata = { #endif #if 0 -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) static struct i2c_gpio_platform_data i2c18_platdata = { .sda_pin = GPIO_8M_CAM_SDA_18V, .scl_pin = GPIO_8M_CAM_SCL_18V, @@ -1255,44 +1383,8 @@ static struct platform_device s3c_device_i2c18 = { #endif #endif -#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \ - || defined(CONFIG_FM_SI4705_MODULE) -static struct i2c_gpio_platform_data gpio_i2c_data19 = { - .sda_pin = GPIO_ADC_SDA, - .scl_pin = GPIO_ADC_SCL, -}; - -struct platform_device s3c_device_i2c19 = { - .name = "i2c-gpio", - .id = 19, - .dev.platform_data = &gpio_i2c_data19, -}; - - -/* I2C19 */ -static struct i2c_board_info i2c_devs19_emul[] __initdata = { -#if defined(CONFIG_STMPE811_ADC) - { - I2C_BOARD_INFO("stmpe811-adc", (0x82 >> 1)), - .platform_data = &stmpe811_pdata, - }, -#endif -#ifdef CONFIG_FM_SI4705_MODULE - { - I2C_BOARD_INFO("Si4709", (0x22 >> 1)), - }, -#endif -#ifdef CONFIG_FM_SI4709_MODULE - { - I2C_BOARD_INFO("Si4709", (0x20 >> 1)), - }, -#endif - -}; -#endif - /* I2C21 */ -#ifdef CONFIG_LEDS_AN30259A +#if defined(CONFIG_LEDS_AN30259A) || defined(CONFIG_LEDS_LP5521) static struct i2c_gpio_platform_data gpio_i2c_data21 = { .scl_pin = GPIO_S_LED_I2C_SCL, .sda_pin = GPIO_S_LED_I2C_SDA, @@ -1314,6 +1406,57 @@ static struct i2c_board_info i2c_devs21_emul[] __initdata = { }; #endif +/* I2C22 */ +#if defined (CONFIG_BARCODE_EMUL_ICE4) +static struct i2c_gpio_platform_data gpio_i2c_data22 = { + .scl_pin = GPIO_BARCODE_SCL_1_8V, + .sda_pin = GPIO_BARCODE_SDA_1_8V, +}; + +struct platform_device s3c_device_i2c22 = { + .name = "i2c-gpio", + .id = 22, + .dev.platform_data = &gpio_i2c_data22, +}; + +static struct i2c_board_info i2c_devs22_emul[] __initdata = { + { + I2C_BOARD_INFO("ice4", (0x6c)), + }, +}; +#endif + +#if defined(CONFIG_FELICA) + +#define FELICA_GPIO_RFS_NAME "FeliCa-RFS" +#define FELICA_GPIO_PON_NAME "FeliCa-PON" +#define FELICA_GPIO_INT_NAME "FeliCa-INT" +#define FELICA_GPIO_I2C_SDA_NAME "FeliCa-SDA" +#define FELICA_GPIO_I2C_SCL_NAME "FeliCa-SCL" + +static struct i2c_gpio_platform_data i2c30_gpio_platdata = { + .sda_pin = FELICA_GPIO_I2C_SDA, + .scl_pin = FELICA_GPIO_I2C_SCL, + .udelay = 0, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0 +}; + +static struct platform_device s3c_device_i2c30 = { + .name = "i2c-gpio", + .id = 30, /* adepter number */ + .dev.platform_data = &i2c30_gpio_platdata, +}; + +static struct i2c_board_info i2c_devs30[] __initdata = { + { + I2C_BOARD_INFO("felica_i2c", (0x56 >> 1)), + }, +}; + +#endif /* CONFIG_FELICA */ + #ifdef CONFIG_ANDROID_RAM_CONSOLE static struct resource ram_console_resource[] = { { @@ -1352,33 +1495,50 @@ static int __init setup_ram_console_mem(char *str) __setup("ram_console=", setup_ram_console_mem); #endif -#if defined(CONFIG_BATTERY_SAMSUNG) || defined(CONFIG_BATTERY_SAMSUNG_S2PLUS) +#if defined(CONFIG_BATTERY_SAMSUNG) static struct samsung_battery_platform_data samsung_battery_pdata = { .charger_name = "max77693-charger", .fuelgauge_name = "max17047-fuelgauge", -#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS) +#if defined(CONFIG_CHARGER_MAX8922_U1) .sub_charger_name = "max8922-charger", -#if defined(CONFIG_CHARGER_MAX8922_S2PLUS) - .use_sub_charger = true, #endif -#endif -#if defined(CONFIG_BATTERY_SAMSUNG_S2PLUS) +#if defined(CONFIG_MACH_GC1) .voltage_max = 4200000, #else .voltage_max = 4350000, #endif .voltage_min = 3400000, - .in_curr_limit = 1000, #if defined(CONFIG_MACH_GC1) + .in_curr_limit = 700, .chg_curr_ta = 700, + .chg_curr_dock = 700, + .chg_curr_siop_lv1 = 475, + .chg_curr_siop_lv2 = 475, + .chg_curr_siop_lv3 = 475, +#elif defined(CONFIG_MACH_T0) + .in_curr_limit = 1800, + .chg_curr_ta = 1700, + .chg_curr_dock = 1700, + .chg_curr_siop_lv1 = 1000, + .chg_curr_siop_lv2 = 475, + .chg_curr_siop_lv3 = 1, /* zero make charger off */ #else + .in_curr_limit = 1000, .chg_curr_ta = 1000, + .chg_curr_dock = 1000, + .chg_curr_siop_lv1 = 475, + .chg_curr_siop_lv2 = 475, + .chg_curr_siop_lv3 = 475, #endif + .chg_curr_usb = 475, .chg_curr_cdp = 1000, +#if defined(CONFIG_MACH_T0_USA_VZW) + .chg_curr_wpc = 650, +#else .chg_curr_wpc = 475, - .chg_curr_dock = 1000, +#endif .chg_curr_etc = 475, .chng_interval = 30, @@ -1388,13 +1548,16 @@ static struct samsung_battery_platform_data samsung_battery_pdata = { .emer_lv1_interval = 30, .emer_lv2_interval = 10, -#if defined(CONFIG_BATTERY_SAMSUNG_S2PLUS) +#if defined(CONFIG_MACH_GC1) .recharge_voltage = 4150000, #else - .recharge_voltage = 4300000, /* it will be cacaluated in probe */ + /* it will be cacaluated in probe */ + .recharge_voltage = 4300000, #endif -#if defined(CONFIG_TARGET_LOCALE_KOR) || defined(CONFIG_MACH_M0_CTC) +#if defined(CONFIG_TARGET_LOCALE_KOR) || defined(CONFIG_MACH_M0_CTC) || \ + defined(CONFIG_MACH_T0_USA_VZW) || defined(CONFIG_MACH_T0_USA_SPR) || \ + defined(CONFIG_MACH_T0_USA_USCC) .abstimer_charge_duration = 8 * 60 * 60, .abstimer_charge_duration_wpc = 8 * 60 * 60, .abstimer_recharge_duration = 2 * 60 * 60, @@ -1414,40 +1577,155 @@ static struct samsung_battery_platform_data samsung_battery_pdata = { #elif defined(CONFIG_MACH_C1_KOR_LGT) .overheat_stop_temp = 630, .overheat_recovery_temp = 430, - .freeze_stop_temp = -50, + .freeze_stop_temp = -70, .freeze_recovery_temp = 0, #elif defined(CONFIG_MACH_M0_KOR_SKT) || defined(CONFIG_MACH_M0_KOR_KT) .overheat_stop_temp = 710, .overheat_recovery_temp = 430, .freeze_stop_temp = -40, .freeze_recovery_temp = 30, +#elif defined(CONFIG_MACH_T0_KOR_SKT) || defined(CONFIG_MACH_T0_KOR_KT) || \ + defined(CONFIG_MACH_T0_KOR_LGT) + .overheat_stop_temp = 650, + .overheat_recovery_temp = 425, + .freeze_stop_temp = -45, + .freeze_recovery_temp = 3, #else .overheat_stop_temp = 600, .overheat_recovery_temp = 430, .freeze_stop_temp = -50, .freeze_recovery_temp = 0, #endif /* KOR model */ +#elif defined(CONFIG_TARGET_LOCALE_USA) +#if defined(CONFIG_MACH_C1_USA_ATT) + .overheat_stop_temp = 450, + .overheat_recovery_temp = 400, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#elif defined(CONFIG_MACH_M3_USA_VZW) + .overheat_stop_temp = 477, + .overheat_recovery_temp = 420, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#elif defined(CONFIG_MACH_T0_USA_ATT) + .overheat_stop_temp = 475, + .overheat_recovery_temp = 400, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#elif defined(CONFIG_MACH_T0_USA_VZW) + .overheat_stop_temp = 515, + .overheat_recovery_temp = 440, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#elif defined(CONFIG_MACH_T0_USA_SPR) + .overheat_stop_temp = 485, + .overheat_recovery_temp = 409, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#elif defined(CONFIG_MACH_T0_USA_USCC) + .overheat_stop_temp = 600, + .overheat_recovery_temp = 400, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#else + /* USA default */ + .overheat_stop_temp = 450, + .overheat_recovery_temp = 400, + .freeze_stop_temp = -50, + .freeze_recovery_temp = 0, +#endif #elif defined(CONFIG_MACH_M0_CTC) .overheat_stop_temp = 640, - .overheat_recovery_temp = 400, + .overheat_recovery_temp = 430, .freeze_stop_temp = -50, .freeze_recovery_temp = 30, +#elif defined(CONFIG_MACH_GC1) + .overheat_stop_temp = 600, + .overheat_recovery_temp = 400, + .freeze_stop_temp = -30, + .freeze_recovery_temp = 0, #else + /* M0 EUR */ .overheat_stop_temp = 600, .overheat_recovery_temp = 400, .freeze_stop_temp = -50, .freeze_recovery_temp = 0, #endif + /* CTIA spec */ +#if defined(CONFIG_TARGET_LOCALE_USA) && !defined(CONFIG_MACH_T0_USA_USCC) + .ctia_spec = true, +#else + .ctia_spec = false, +#endif + + /* CTIA temperature spec */ + .event_time = 10 * 60, +#if defined(CONFIG_MACH_C1_USA_ATT) + .event_overheat_stop_temp = 600, + .event_overheat_recovery_temp = 400, + .event_freeze_stop_temp = -50, + .event_freeze_recovery_temp = 0, + .lpm_overheat_stop_temp = 480, + .lpm_overheat_recovery_temp = 450, + .lpm_freeze_stop_temp = -50, + .lpm_freeze_recovery_temp = 0, +#elif defined(CONFIG_MACH_M3_USA_VZW) + .event_overheat_stop_temp = 600, + .event_overheat_recovery_temp = 400, + .event_freeze_stop_temp = -50, + .event_freeze_recovery_temp = 0, + .lpm_overheat_stop_temp = 480, + .lpm_overheat_recovery_temp = 450, + .lpm_freeze_stop_temp = -50, + .lpm_freeze_recovery_temp = 0, +#elif defined(CONFIG_MACH_T0_USA_VZW) + .event_overheat_stop_temp = 600, + .event_overheat_recovery_temp = 409, + .event_freeze_stop_temp = -50, + .event_freeze_recovery_temp = 0, + .lpm_overheat_stop_temp = 480, + .lpm_overheat_recovery_temp = 450, + .lpm_freeze_stop_temp = -50, + .lpm_freeze_recovery_temp = 0, +#else + /* USA default */ + .event_overheat_stop_temp = 600, + .event_overheat_recovery_temp = 400, + .event_freeze_stop_temp = -50, + .event_freeze_recovery_temp = 0, + .lpm_overheat_stop_temp = 480, + .lpm_overheat_recovery_temp = 450, + .lpm_freeze_stop_temp = -50, + .lpm_freeze_recovery_temp = 0, +#endif + .temper_src = TEMPER_AP_ADC, - .temper_ch = 2, + .temper_ch = 2, /* if src == TEMPER_AP_ADC */ #ifdef CONFIG_S3C_ADC - /* s3c adc driver does not convert raw adc data. + /* + * s3c adc driver does not convert raw adc data. * so, register convert function. */ .covert_adc = convert_adc, #endif +#if defined(CONFIG_MACH_M3_USA_VZW) + .vf_det_src = VF_DET_UNKNOWN, +#else +#if defined(CONFIG_MACH_T0) && defined(CONFIG_TARGET_LOCALE_USA) + .vf_det_src = VF_DET_GPIO, /* check H/W rev in battery probe */ +#else + .vf_det_src = VF_DET_CHARGER, +#endif +#endif + .vf_det_ch = 0, /* if src == VF_DET_ADC */ + .vf_det_th_l = 100, + .vf_det_th_h = 600, +#if defined(CONFIG_MACH_T0) && defined(CONFIG_TARGET_LOCALE_USA) + .batt_present_gpio = GPIO_BATT_PRESENT_N_INT, +#endif + .suspend_chging = true, .led_indicator = false, @@ -1478,18 +1756,6 @@ struct gpio_keys_button midas_buttons[] = { #if defined(CONFIG_MACH_GC1) GPIO_KEYS(KEY_POWER, GPIO_nPOWER, 1, 1, sec_debug_check_crash_key), - GPIO_KEYS(KEY_RECORD, GPIO_RECORD_KEY, - 1, 1, sec_debug_check_crash_key), -#if 0 - GPIO_KEYS(KEY_HOMEPAGE, GPIO_OK_KEY_ANDROID, - 1, 1, sec_debug_check_crash_key), - GPIO_KEYS(KEY_MENU, GPIO_MENU_KEY, - 1, 1, sec_debug_check_crash_key), - GPIO_KEYS(KEY_BACK, GPIO_BACK_KEY, - 1, 1, sec_debug_check_crash_key), -#endif - GPIO_KEYS(KEY_PLAY, GPIO_PLAY_KEY, - 1, 1, sec_debug_check_crash_key), GPIO_KEYS(KEY_CAMERA_FOCUS, GPIO_S1_KEY, 1, 1, sec_debug_check_crash_key), /*KEY_CAMERA_SHUTTER*/ @@ -1499,6 +1765,18 @@ struct gpio_keys_button midas_buttons[] = { 1, 1, sec_debug_check_crash_key), GPIO_KEYS(KEY_CAMERA_ZOOMOUT, GPIO_WIDE_KEY, 1, 1, sec_debug_check_crash_key), + GPIO_KEYS(0x221, GPIO_FAST_TELE_KEY, + 1, 1, sec_debug_check_crash_key), + GPIO_KEYS(0x222, GPIO_FAST_WIDE_KEY, + 1, 1, sec_debug_check_crash_key), +#if 0 + GPIO_KEYS(KEY_HOMEPAGE, GPIO_OK_KEY_ANDROID, + 1, 1, sec_debug_check_crash_key), + GPIO_KEYS(KEY_MENU, GPIO_MENU_KEY, + 1, 1, sec_debug_check_crash_key), + GPIO_KEYS(KEY_BACK, GPIO_BACK_KEY, + 1, 1, sec_debug_check_crash_key), +#endif #else GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP, 1, 0, sec_debug_check_crash_key), @@ -1509,6 +1787,7 @@ struct gpio_keys_button midas_buttons[] = { #endif }; +#if !defined(CONFIG_MACH_T0) && !defined(CONFIG_MACH_M3) struct gpio_keys_button m0_buttons[] = { GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP_00, 1, 0, sec_debug_check_crash_key), @@ -1516,13 +1795,10 @@ struct gpio_keys_button m0_buttons[] = { 1, 0, sec_debug_check_crash_key), GPIO_KEYS(KEY_POWER, GPIO_nPOWER, 1, 1, sec_debug_check_crash_key), -#if defined(CONFIG_MACH_S2PLUS) - GPIO_KEYS(KEY_HOME, GPIO_OK_KEY, - 1, 1, sec_debug_check_crash_key), -#endif }; +#endif -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW) || \ +#if defined(CONFIG_MACH_M0) || \ defined(CONFIG_MACH_C1_USA_ATT) struct gpio_keys_button m0_rev11_buttons[] = { GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP_00, @@ -1536,7 +1812,9 @@ struct gpio_keys_button m0_rev11_buttons[] = { }; #endif -#if defined(CONFIG_TARGET_LOCALE_KOR) +#if defined(CONFIG_TARGET_LOCALE_KOR) && \ + (defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) ||\ + defined(CONFIG_MACH_BAFFIN)) struct gpio_keys_button c1_rev04_buttons[] = { GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP_00, 1, 0, sec_debug_check_crash_key), @@ -1549,6 +1827,19 @@ struct gpio_keys_button c1_rev04_buttons[] = { }; #endif +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) +struct gpio_keys_button t0_buttons[] = { + GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP, + 1, 0, sec_debug_check_crash_key), + GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN, + 1, 0, sec_debug_check_crash_key), + GPIO_KEYS(KEY_POWER, GPIO_nPOWER, + 1, 1, sec_debug_check_crash_key), + GPIO_KEYS(KEY_HOMEPAGE, GPIO_OK_KEY, + 1, 1, sec_debug_check_crash_key), +}; +#endif + struct gpio_keys_platform_data midas_gpiokeys_platform_data = { midas_buttons, ARRAY_SIZE(midas_buttons), @@ -1561,6 +1852,8 @@ static struct platform_device midas_keypad = { }, }; + + #ifdef CONFIG_VIDEO_FIMG2D static struct fimg2d_platdata fimg2d_data __initdata = { .hw_ver = 0x41, @@ -1635,6 +1928,23 @@ static struct platform_device s3c_device_i2c10 = { }; #endif +#ifdef CONFIG_SENSORS_AK8963C +static struct i2c_gpio_platform_data i2c10_platdata = { + .sda_pin = GPIO_MSENSOR_SDA_18V, + .scl_pin = GPIO_MSENSOR_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device s3c_device_i2c10 = { + .name = "i2c-gpio", + .id = 10, + .dev.platform_data = &i2c10_platdata, +}; +#endif + #ifdef CONFIG_SENSORS_LPS331 static struct i2c_gpio_platform_data i2c11_platdata = { .sda_pin = GPIO_BSENSE_SDA_18V, @@ -1652,8 +1962,8 @@ static struct platform_device s3c_device_i2c11 = { }; #endif -#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \ - && !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3) +#if defined(CONFIG_PN65N_NFC) && \ + !defined(CONFIG_MACH_C1) && !defined(CONFIG_MACH_BAFFIN) static struct i2c_gpio_platform_data i2c12_platdata = { .sda_pin = GPIO_NFC_SDA_18V, .scl_pin = GPIO_NFC_SCL_18V, @@ -1674,11 +1984,14 @@ static struct platform_device s3c_device_i2c12 = { static void otg_accessory_power(int enable) { u8 on = (u8)!!enable; + int err; /* max77693 otg power control */ otg_control(enable); - gpio_request(GPIO_OTG_EN, "USB_OTG_EN"); + err = gpio_request(GPIO_OTG_EN, "USB_OTG_EN"); + if (err) + printk(KERN_ERR "failed to request USB_OTG_EN\n"); gpio_direction_output(GPIO_OTG_EN, on); gpio_free(GPIO_OTG_EN); pr_info("%s: otg accessory power = %d\n", __func__, on); @@ -1713,6 +2026,76 @@ static struct platform_device watchdog_reset_device = { }; #endif +#ifdef CONFIG_CORESIGHT_ETM + +#define CORESIGHT_PHYS_BASE 0x10880000 +#define CORESIGHT_ETB_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1000) +#define CORESIGHT_TPIU_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x3000) +#define CORESIGHT_FUNNEL_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x4000) +#define CORESIGHT_ETM_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1C000) + +static struct resource coresight_etb_resources[] = { + { + .start = CORESIGHT_ETB_PHYS_BASE, + .end = CORESIGHT_ETB_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_etb_device = { + .name = "coresight_etb", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_etb_resources), + .resource = coresight_etb_resources, +}; + +static struct resource coresight_tpiu_resources[] = { + { + .start = CORESIGHT_TPIU_PHYS_BASE, + .end = CORESIGHT_TPIU_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_tpiu_device = { + .name = "coresight_tpiu", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_tpiu_resources), + .resource = coresight_tpiu_resources, +}; + +static struct resource coresight_funnel_resources[] = { + { + .start = CORESIGHT_FUNNEL_PHYS_BASE, + .end = CORESIGHT_FUNNEL_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_funnel_device = { + .name = "coresight_funnel", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_funnel_resources), + .resource = coresight_funnel_resources, +}; + +static struct resource coresight_etm_resources[] = { + { + .start = CORESIGHT_ETM_PHYS_BASE, + .end = CORESIGHT_ETM_PHYS_BASE + (SZ_4K * 4) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_etm_device = { + .name = "coresight_etm", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_etm_resources), + .resource = coresight_etm_resources, +}; + +#endif + static struct platform_device *midas_devices[] __initdata = { #ifdef CONFIG_SEC_WATCHDOG_RESET &watchdog_reset_device, @@ -1759,57 +2142,76 @@ static struct platform_device *midas_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_i2c1, +#ifdef CONFIG_S3C_DEV_I2C2 + &s3c_device_i2c2, +#endif &s3c_device_i2c3, #ifdef CONFIG_S3C_DEV_I2C4 &s3c_device_i2c4, #endif /* &s3c_device_i2c5, */ -#ifdef CONFIG_AUDIENCE_ES305 +#if defined(CONFIG_AUDIENCE_ES305) || defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) &s3c_device_i2c6, #endif &s3c_device_i2c7, -#if !defined(CONFIG_MACH_M0_GRANDECTC) &s3c_device_i2c8, -#endif &s3c_device_i2c9, #ifdef CONFIG_SENSORS_AK8975C &s3c_device_i2c10, #endif +#ifdef CONFIG_SENSORS_AK8963C + &s3c_device_i2c10, +#endif + #ifdef CONFIG_SENSORS_LPS331 &s3c_device_i2c11, #endif /* &s3c_device_i2c12, */ -#if defined(CONFIG_MACH_S2PLUS) - &s3c_device_i2c13, -#endif #ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE &s3c_device_i2c14, /* max17047-fuelgauge */ #endif #ifdef CONFIG_SAMSUNG_MHL &s3c_device_i2c15, +#if !defined(CONFIG_MACH_T0) && !defined(CONFIG_MACH_M3) &s3c_device_i2c16, #endif -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \ - defined(CONFIG_MACH_GC1) +#endif /* CONFIG_SAMSUNG_MHL */ +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_BAFFIN) &s3c_device_i2c17, #if 0 &s3c_device_i2c18, #endif #endif -#ifdef CONFIG_LEDS_AN30259A +#if defined(CONFIG_LEDS_AN30259A) || defined(CONFIG_LEDS_LP5521) &s3c_device_i2c21, #endif +#if defined (CONFIG_BARCODE_EMUL_ICE4) + &s3c_device_i2c22, +#endif +#if defined(CONFIG_FELICA) + &s3c_device_i2c30, +#endif -#if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC +#if defined CONFIG_USB_EHCI_S5P +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) +#else &s5p_device_ehci, #endif -#if defined CONFIG_USB_OHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC +#endif + +#if defined CONFIG_USB_OHCI_S5P +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) +#else &s5p_device_ohci, #endif +#endif + #ifdef CONFIG_USB_GADGET &s3c_device_usbgadget, #endif @@ -1891,6 +2293,9 @@ static struct platform_device *midas_devices[] __initdata = { &SYSMMU_PLATDEV(fimc2), &SYSMMU_PLATDEV(fimc3), &SYSMMU_PLATDEV(jpeg), +#ifdef CONFIG_FB_S5P_SYSMMU + &SYSMMU_PLATDEV(fimd0), +#endif &SYSMMU_PLATDEV(mfc_l), &SYSMMU_PLATDEV(mfc_r), &SYSMMU_PLATDEV(tv), @@ -1919,7 +2324,7 @@ static struct platform_device *midas_devices[] __initdata = { #ifndef CONFIG_SND_SOC_SAMSUNG_USE_DMA_WRAPPER &samsung_asoc_idma, #endif -#if defined(CONFIG_CHARGER_MAX8922_U1) || defined(CONFIG_CHARGER_MAX8922_S2PLUS) +#if defined(CONFIG_CHARGER_MAX8922_U1) &max8922_device_charger, #endif #ifdef CONFIG_EXYNOS_C2C @@ -1929,14 +2334,16 @@ static struct platform_device *midas_devices[] __initdata = { #if defined(CONFIG_VIDEO_S5C73M3_SPI) &exynos_device_spi1, #endif -#if defined(CONFIG_PHONE_IPC_SPI) +#if defined(CONFIG_LINK_DEVICE_SPI) &exynos_device_spi2, - &ipc_spi_device, #elif defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) &exynos_device_spi2, +#elif defined(CONFIG_ISDBT) + &exynos_device_spi2, +#elif defined(CONFIG_LINK_DEVICE_PLD) + &exynos_device_spi2, #endif #endif - #ifdef CONFIG_BT_BCM4334 &bcm4334_bluetooth_device, #endif @@ -1950,6 +2357,13 @@ static struct platform_device *midas_devices[] __initdata = { #ifdef CONFIG_EXYNOS4_SETUP_THERMAL &s5p_device_tmu, #endif + +#ifdef CONFIG_CORESIGHT_ETM + &coresight_etb_device, + &coresight_tpiu_device, + &coresight_funnel_device, + &coresight_etm_device, +#endif }; #ifdef CONFIG_EXYNOS4_SETUP_THERMAL @@ -1979,20 +2393,25 @@ struct s5p_platform_tmu midas_tmu_data __initdata = { }; #endif -#if defined CONFIG_USB_OHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC +#if defined CONFIG_USB_OHCI_S5P +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) static int __init s5p_ohci_device_initcall(void) { return platform_device_register(&s5p_device_ohci); } late_initcall(s5p_ohci_device_initcall); #endif -#if defined CONFIG_USB_EHCI_S5P && defined CONFIG_LINK_DEVICE_HSIC +#endif + +#if defined CONFIG_USB_EHCI_S5P +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) static int __init s5p_ehci_device_initcall(void) { return platform_device_register(&s5p_device_ehci); } late_initcall(s5p_ehci_device_initcall); #endif +#endif #if defined(CONFIG_VIDEO_TVOUT) static struct s5p_platform_hpd hdmi_hpd_data __initdata = { @@ -2004,9 +2423,43 @@ static struct s5p_platform_hpd hdmi_hpd_data __initdata = { static struct s5p_platform_cec hdmi_cec_data __initdata = { }; + +#if defined(CONFIG_MACH_GC1) && defined(CONFIG_HDMI_TX_STRENGTH) +static u8 gc1_hdmi_tx_val[5] = {0x00, 0x1f, 0x00, 0x00, 0x00}; +static struct s5p_tx_tuning gc1_tx_tuning = { + /* tx_ch: bit4 - Pre-emp + * bit3 - Amp all + * bit2 - fine amp ch0 + * bit1 - fine amp ch1 + * bit0 - fine amp ch2 + */ + .tx_ch = 0x08, + .tx_val = &gc1_hdmi_tx_val[0], +}; +static struct s5p_platform_tvout hdmi_tvout_data __initdata = { + .tx_tune = &gc1_tx_tuning, +}; +#endif #endif #if defined(CONFIG_CMA) +static unsigned long fbmem_start; +static unsigned long fbmem_size; +static int __init early_fbmem(char *p) +{ + char *endp; + + if (!p) + return -EINVAL; + + fbmem_size = memparse(p, &endp); + if (*endp == '@') + fbmem_start = memparse(endp + 1, &endp); + + return endp > p ? 0 : -EINVAL; +} +early_param("fbmem", early_fbmem); + static void __init exynos4_reserve_mem(void) { static struct cma_region regions[] = { @@ -2101,12 +2554,18 @@ static void __init exynos4_reserve_mem(void) }, #endif #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 +#ifndef CONFIG_USE_FIMC_CMA { .name = "fimc1", .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K, +#if defined(CONFIG_MACH_GC1) + .start = 0x5ec00000, +#else .start = 0x65c00000, +#endif }, #endif +#endif #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 { .name = "mfc1", @@ -2114,14 +2573,22 @@ static void __init exynos4_reserve_mem(void) { .alignment = 1 << 26, }, +#if defined(CONFIG_MACH_GC1) + .start = 0x5e000000, +#else .start = 0x64000000, +#endif }, #endif #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL { .name = "mfc-normal", .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_NORMAL * SZ_1K, +#if defined(CONFIG_MACH_GC1) + .start = 0x5e000000, +#else .start = 0x64000000, +#endif }, #endif { @@ -2130,6 +2597,7 @@ static void __init exynos4_reserve_mem(void) }; #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION static struct cma_region regions_secure[] = { +#ifndef CONFIG_DMA_CMA #ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE { .name = "ion", @@ -2146,6 +2614,46 @@ static void __init exynos4_reserve_mem(void) .name = "sectbl", .size = SZ_1M, }, +#else +#if defined(CONFIG_USE_MFC_CMA) && defined(CONFIG_MACH_M0) +#ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE + { + .name = "ion", + .size = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K, + .start = 0x5F200000, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE + { + .name = "mfc-secure", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K, + .start = 0x5C100000, + }, +#endif + { + .name = "sectbl", + .size = SZ_1M, + .start = 0x5C000000, + }, +#else +#ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE + { + .name = "ion", + .size = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K, + }, +#endif +#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE + { + .name = "mfc-secure", + .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC_SECURE * SZ_1K, + }, +#endif + { + .name = "sectbl", + .size = SZ_1M, + }, +#endif +#endif { .size = 0 }, @@ -2188,7 +2696,20 @@ static void __init exynos4_reserve_mem(void) "s5p-smem/fimd=fimd;" "s5p-smem/fimc0=fimc0"; - s5p_cma_region_reserve(regions, regions_secure, 0, map); + int i; + + s5p_cma_region_reserve(regions, regions_secure, 0, map); + + if (!(fbmem_start && fbmem_size)) + return; + + for (i = 0; i < ARRAY_SIZE(regions); i++) { + if (regions[i].name && !strcmp(regions[i].name, "fimd")) { + memcpy(phys_to_virt(regions[i].start), phys_to_virt(fbmem_start), fbmem_size * SZ_1K); + printk(KERN_INFO "Bootloader sent 'fbmem' : %08X\n", (u32)fbmem_start); + break; + } + } } #else static inline void exynos4_reserve_mem(void) @@ -2258,6 +2779,9 @@ static void __init exynos_sysmmu_init(void) #ifdef CONFIG_VIDEO_JPEG_V2X sysmmu_set_owner(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev); #endif +#ifdef CONFIG_FB_S5P_SYSMMU + sysmmu_set_owner(&SYSMMU_PLATDEV(fimd0).dev, &s3c_device_fb.dev); +#endif #ifdef CONFIG_VIDEO_EXYNOS_FIMC_IS ASSIGN_SYSMMU_POWERDOMAIN(is_isp, &exynos4_device_pd[PD_ISP].dev); ASSIGN_SYSMMU_POWERDOMAIN(is_drc, &exynos4_device_pd[PD_ISP].dev); @@ -2316,16 +2840,50 @@ void __init s3cfb_extdsp_set_platdata(struct s3c_platform_fb *pd) static inline int need_i2c5(void) { -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0) return system_rev != 3; -#elif defined(CONFIG_MACH_JENGA) - return 0; #else return 1; #endif } +#if defined(CONFIG_FELICA) +static void felica_setup(void) +{ + /* I2C SDA GPY2[4] */ + gpio_request(FELICA_GPIO_I2C_SDA, FELICA_GPIO_I2C_SDA_NAME); + s3c_gpio_setpull(FELICA_GPIO_I2C_SDA, S3C_GPIO_PULL_DOWN); + gpio_free(FELICA_GPIO_I2C_SDA); + + /* I2C SCL GPY2[5] */ + gpio_request(FELICA_GPIO_I2C_SCL, FELICA_GPIO_I2C_SCL_NAME); + s3c_gpio_setpull(FELICA_GPIO_I2C_SCL, S3C_GPIO_PULL_DOWN); + gpio_free(FELICA_GPIO_I2C_SCL); + + /* PON GPL2[7] */ + gpio_request(FELICA_GPIO_PON, FELICA_GPIO_PON_NAME); + s3c_gpio_setpull(FELICA_GPIO_PON, S3C_GPIO_PULL_DOWN); + s3c_gpio_cfgpin(FELICA_GPIO_PON, S3C_GPIO_SFN(1)); /* OUTPUT */ + gpio_free(FELICA_GPIO_PON); + + /* RFS GPL2[6] */ + gpio_request(FELICA_GPIO_RFS, FELICA_GPIO_RFS_NAME); + s3c_gpio_setpull(FELICA_GPIO_RFS, S3C_GPIO_PULL_DOWN); + gpio_direction_input(FELICA_GPIO_RFS); + gpio_free(FELICA_GPIO_RFS); + + /* INT GPX1[7] = WAKEUP_INT1[7] */ + gpio_request(FELICA_GPIO_INT, FELICA_GPIO_INT_NAME); + s3c_gpio_setpull(FELICA_GPIO_INT, S3C_GPIO_PULL_DOWN); + s5p_register_gpio_interrupt(FELICA_GPIO_INT); + gpio_direction_input(FELICA_GPIO_INT); + irq_set_irq_type(gpio_to_irq(FELICA_GPIO_INT), IRQF_TRIGGER_FALLING); + s3c_gpio_cfgpin(FELICA_GPIO_INT, S3C_GPIO_SFN(0xF)); /* EINT */ + gpio_free(FELICA_GPIO_INT); +} +#endif + static void __init midas_machine_init(void) { struct clk *ppmu_clk = NULL; @@ -2337,8 +2895,9 @@ static void __init midas_machine_init(void) struct clk *prnt = NULL; struct device *spi1_dev = &exynos_device_spi1.dev; #endif -#if defined(CONFIG_PHONE_IPC_SPI) \ - || defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#if defined(CONFIG_LINK_DEVICE_SPI) \ + || defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) \ + || defined(CONFIG_ISDBT) || defined(CONFIG_LINK_DEVICE_PLD) struct device *spi2_dev = &exynos_device_spi2.dev; #endif #endif @@ -2361,23 +2920,28 @@ static void __init midas_machine_init(void) s3c_i2c1_set_platdata(NULL); i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); +#if defined(CONFIG_S3C_DEV_I2C2) \ + && !defined(CONFIG_MACH_T0_EUR_OPEN) \ + && !defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + && !defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) \ + && !defined(CONFIG_MACH_T0_CHN_CMCC) \ + && !defined(CONFIG_MACH_T0_CHN_OPEN) + s3c_i2c2_set_platdata(NULL); +#endif + s3c_i2c3_set_platdata(NULL); midas_tsp_init(); #ifndef CONFIG_TOUCHSCREEN_MELFAS_GC -#if !defined(CONFIG_MACH_M0_GRANDECTC) midas_tsp_set_lcdtype(lcdtype); #endif -#endif #ifdef CONFIG_LEDS_AAT1290A platform_device_register(&s3c_device_aat1290a_led); #endif #ifdef CONFIG_S3C_DEV_I2C4 -#ifdef CONFIG_MACH_MIDAS_02_BD +#if defined(CONFIG_MACH_T0) s3c_i2c4_set_platdata(NULL); - i2c_register_board_info(4, i2c_devs4_max77693, - ARRAY_SIZE(i2c_devs4_max77693)); #else s3c_i2c4_set_platdata(NULL); if (!(system_rev != 3 && system_rev >= 0)) { @@ -2385,16 +2949,31 @@ static void __init midas_machine_init(void) ARRAY_SIZE(i2c_devs4_max77693)); } #endif -#endif +#endif /* CONFIG_S3C_DEV_I2C4 */ midas_sound_init(); #ifdef CONFIG_S3C_DEV_I2C5 +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) + s3c_i2c5_set_platdata(NULL); +#else if (need_i2c5()) { s3c_i2c5_set_platdata(&default_i2c5_data); i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5)); } #endif +#endif + +#if defined(CONFIG_INPUT_WACOM) + midas_wacom_init(); +#endif + +#ifdef CONFIG_S3C_DEV_I2C6 +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) + s3c_i2c6_set_platdata(&default_i2c6_data); + i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6)); +#endif +#endif #ifdef CONFIG_MACH_GC1 s3c_i2c7_set_platdata(NULL); @@ -2413,7 +2992,7 @@ static void __init midas_machine_init(void) #endif i2c_register_board_info(8, i2c_devs8_emul, ARRAY_SIZE(i2c_devs8_emul)); -#ifndef CONFIG_LEDS_AAT1290A +#if !defined(CONFIG_MACH_GC1) && !defined(CONFIG_LEDS_AAT1290A) gpio_request(GPIO_3_TOUCH_INT, "3_TOUCH_INT"); s5p_register_gpio_interrupt(GPIO_3_TOUCH_INT); #endif @@ -2426,17 +3005,12 @@ static void __init midas_machine_init(void) i2c_register_board_info(11, i2c_devs11_emul, ARRAY_SIZE(i2c_devs11_emul)); -#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \ - && !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3) +#if defined(CONFIG_PN65N_NFC) && \ + !defined(CONFIG_MACH_C1) && !defined(CONFIG_MACH_BAFFIN) i2c_register_board_info(12, i2c_devs12_emul, ARRAY_SIZE(i2c_devs12_emul)); #endif -#if defined(CONFIG_MACH_S2PLUS) - i2c_register_board_info(13, i2c_devs13_emul, - ARRAY_SIZE(i2c_devs13_emul)); -#endif - #ifdef CONFIG_BATTERY_MAX17047_FUELGAUGE /* max17047 fuel gauge */ i2c_register_board_info(14, i2c_devs14_emul, @@ -2450,28 +3024,51 @@ static void __init midas_machine_init(void) i2c_register_board_info(16, i2c_devs16_emul, ARRAY_SIZE(i2c_devs16_emul)); #endif -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \ - defined(CONFIG_MACH_GC1) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) ||\ + defined(CONFIG_MACH_BAFFIN) +#if defined(CONFIG_MACH_T0) && defined(CONFIG_TARGET_LOCALE_KOR) + if (system_rev >= 9) + max77693_haptic_pdata.motor_en = motor_en; +#endif +#if defined(CONFIG_MACH_BAFFIN) + max77693_haptic_pdata.motor_en = motor_en; +#endif i2c_register_board_info(17, i2c_devs17_emul, ARRAY_SIZE(i2c_devs17_emul)); #endif -#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \ - || defined(CONFIG_FM_SI4705_MODULE) - i2c_register_board_info(19, i2c_devs19_emul, - ARRAY_SIZE(i2c_devs19_emul)); -#endif -#ifdef CONFIG_LEDS_AN30259A +#if defined(CONFIG_LEDS_AN30259A) || defined(CONFIG_LEDS_LP5521) i2c_register_board_info(21, i2c_devs21_emul, ARRAY_SIZE(i2c_devs21_emul)); #endif +#if defined (CONFIG_BARCODE_EMUL_ICE4) + i2c_register_board_info(22, i2c_devs22_emul, + ARRAY_SIZE(i2c_devs22_emul)); +#endif + +#if defined(CONFIG_FELICA) + i2c_register_board_info(30, i2c_devs30, ARRAY_SIZE(i2c_devs30)); +#endif #if defined(GPIO_OLED_DET) - gpio_request(GPIO_OLED_DET, "OLED_DET"); - s5p_register_gpio_interrupt(GPIO_OLED_DET); - gpio_free(GPIO_OLED_DET); + if (unlikely(gpio_request(GPIO_OLED_DET, "OLED_DET"))) + pr_err("Request GPIO_OLED_DET is failed\n"); + else { + s5p_register_gpio_interrupt(GPIO_OLED_DET); + gpio_free(GPIO_OLED_DET); + } +#endif + +#if defined(GPIO_ERR_FG) + if (unlikely(gpio_request(GPIO_ERR_FG, "OLED_DET"))) + pr_err("Request GPIO_ERR_FG is failed\n"); + else { + s5p_register_gpio_interrupt(GPIO_ERR_FG); + gpio_free(GPIO_ERR_FG); + } #endif #ifdef CONFIG_FB_S5P @@ -2530,9 +3127,16 @@ static void __init midas_machine_init(void) s3cfb_extdsp_set_platdata(&default_extdsp_data); #endif +#if defined(CONFIG_FELICA) + felica_setup(); +#endif /* CONFIG_FELICA */ + #if defined(CONFIG_VIDEO_TVOUT) s5p_hdmi_hpd_set_platdata(&hdmi_hpd_data); s5p_hdmi_cec_set_platdata(&hdmi_cec_data); +#if defined(CONFIG_MACH_GC1) && defined(CONFIG_HDMI_TX_STRENGTH) + s5p_hdmi_tvout_set_platdata(&hdmi_tvout_data); +#endif #ifdef CONFIG_EXYNOS_DEV_PD s5p_device_tvout.dev.parent = &exynos4_device_pd[PD_TV].dev; exynos4_device_pd[PD_TV].dev.parent = &exynos4_device_pd[PD_LCD0].dev; @@ -2580,18 +3184,19 @@ static void __init midas_machine_init(void) platform_add_devices(midas_devices, ARRAY_SIZE(midas_devices)); #ifdef CONFIG_S3C_ADC -#if defined(CONFIG_MACH_S2PLUS) +#if defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) platform_device_register(&s3c_device_adc); #else if (system_rev != 3) platform_device_register(&s3c_device_adc); #endif + +#if defined(CONFIG_MACH_GC1) + gc1_jack_init(); #endif -#if defined(CONFIG_STMPE811_ADC) || defined(CONFIG_FM_SI4709_MODULE) \ - || defined(CONFIG_FM_SI4705_MODULE) - platform_device_register(&s3c_device_i2c19); + #endif -#if defined(CONFIG_BATTERY_SAMSUNG) || defined(CONFIG_BATTERY_SAMSUNG_S2PLUS) +#if defined(CONFIG_BATTERY_SAMSUNG) platform_device_register(&samsung_device_battery); #endif #ifdef CONFIG_SEC_THERMISTOR @@ -2600,9 +3205,8 @@ static void __init midas_machine_init(void) #if defined(CONFIG_MACH_M0_CTC) midas_gpiokeys_platform_data.buttons = m0_buttons; midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(m0_buttons); -#elif defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) +#elif defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0) if (system_rev != 3 && system_rev >= 1) { midas_gpiokeys_platform_data.buttons = m0_buttons; midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(m0_buttons); @@ -2611,7 +3215,7 @@ static void __init midas_machine_init(void) /* Above logic is too complex. Let's override whatever the result is... */ -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_M0) #if defined(CONFIG_MACH_M0_CHNOPEN) || defined(CONFIG_MACH_M0_HKTW) { #else @@ -2622,7 +3226,8 @@ static void __init midas_machine_init(void) midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(m0_rev11_buttons); } -#elif defined(CONFIG_TARGET_LOCALE_KOR) +#elif defined(CONFIG_TARGET_LOCALE_KOR) && \ + (defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1)) s3c_gpio_setpull(GPIO_OK_KEY_ANDROID, S3C_GPIO_PULL_NONE); midas_gpiokeys_platform_data.buttons = c1_rev04_buttons; midas_gpiokeys_platform_data.nbuttons = @@ -2635,20 +3240,38 @@ static void __init midas_machine_init(void) midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(m0_rev11_buttons); } +#elif defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) + midas_gpiokeys_platform_data.buttons = t0_buttons; + midas_gpiokeys_platform_data.nbuttons = ARRAY_SIZE(t0_buttons); +#elif defined(CONFIG_MACH_BAFFIN) + s3c_gpio_setpull(GPIO_OK_KEY_ANDROID, S3C_GPIO_PULL_NONE); + midas_gpiokeys_platform_data.buttons = c1_rev04_buttons; + midas_gpiokeys_platform_data.nbuttons = + ARRAY_SIZE(c1_rev04_buttons); #endif - - platform_device_register(&midas_keypad); #ifdef CONFIG_MACH_GC1 - gpio_direction_output(GPIO_TOP_PCB_PWREN, 1); + /*for emul type*/ + if (system_rev < 2) { + printk(KERN_DEBUG"[KEYS] rev %x. switch wide/tele gpio\n", + system_rev); + gpio_direction_output(GPIO_TOP_PCB_PWREN, 1); + midas_buttons[3].gpio = GPIO_WIDE_KEY; + midas_buttons[4].gpio = GPIO_TELE_KEY; + midas_buttons[5].code = KEY_RECORD; + midas_buttons[5].gpio = GPIO_RECORD_KEY; + midas_buttons[6].code = KEY_PLAY; + midas_buttons[6].gpio = GPIO_PLAY_KEY; + } #endif + platform_device_register(&midas_keypad); #if defined(CONFIG_S3C_DEV_I2C5) if (need_i2c5()) platform_device_register(&s3c_device_i2c5); #endif -#if defined(CONFIG_PN65N_NFC) && !defined(CONFIG_MACH_C1) \ - && !defined(CONFIG_MACH_C1VZW) && !defined(CONFIG_MACH_M3) +#if defined(CONFIG_PN65N_NFC) && \ + !defined(CONFIG_MACH_C1) && !defined(CONFIG_MACH_BAFFIN) platform_device_register(&s3c_device_i2c12); #endif @@ -2664,7 +3287,8 @@ static void __init midas_machine_init(void) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", prnt->name, sclk->name); - clk_set_rate(sclk, 88 * 1000 * 1000); + clk_set_rate(sclk, 100 * 1000 * 1000); /*50MHz*/ + clk_put(sclk); clk_put(prnt); @@ -2682,8 +3306,9 @@ static void __init midas_machine_init(void) spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info)); #endif -#if defined(CONFIG_PHONE_IPC_SPI) \ - || defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) +#if defined(CONFIG_LINK_DEVICE_SPI) \ + || defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) \ + || defined(CONFIG_ISDBT) || defined(CONFIG_LINK_DEVICE_PLD) sclk = NULL; prnt = NULL; @@ -2715,6 +3340,8 @@ static void __init midas_machine_init(void) #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) tdmb_dev_init(); +#elif defined(CONFIG_ISDBT) + isdbt_dev_init(); #endif #endif @@ -2749,8 +3376,13 @@ static void __init midas_machine_init(void) /* 400 kHz for initialization of MMC Card */ __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0) | 0x9, EXYNOS4_CLKDIV_FSYS3); +#ifdef CONFIG_MACH_T0 + __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0) + | 0x90009, EXYNOS4_CLKDIV_FSYS2); +#else __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS2) & 0xfff0fff0) | 0x80008, EXYNOS4_CLKDIV_FSYS2); +#endif __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0) | 0x80008, EXYNOS4_CLKDIV_FSYS1); } @@ -2773,6 +3405,27 @@ static void __init exynos_c2c_reserve(void) } #endif +#ifdef CONFIG_DMA_CMA +static void __init exynos4_reserve(void) +{ + int ret = 0; + +#ifdef CONFIG_USE_FIMC_CMA + ret = dma_declare_contiguous(&s3c_device_fimc1.dev, + CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC1 * SZ_1K, 0x65800000, 0); + if (ret != 0) + panic("alloc failed for FIMC1\n"); +#endif + +#if defined(CONFIG_USE_MFC_CMA) && defined(CONFIG_MACH_M0) + ret = dma_declare_contiguous(&s5p_device_mfc.dev, + 0x02800000, 0x5C800000, 0); +#endif + if (ret != 0) + printk(KERN_ERR "%s Fail\n", __func__); +} +#endif + static void __init exynos_init_reserve(void) { sec_debug_magic_init(); @@ -2784,8 +3437,10 @@ MACHINE_START(SMDK4412, "SMDK4x12") .map_io = midas_map_io, .init_machine = midas_machine_init, .timer = &exynos4_timer, -#ifdef CONFIG_EXYNOS_C2C +#if defined(CONFIG_EXYNOS_C2C) .reserve = &exynos_c2c_reserve, +#elif defined(CONFIG_DMA_CMA) + .reserve = &exynos4_reserve, #endif .init_early = &exynos_init_reserve, MACHINE_END @@ -2796,8 +3451,10 @@ MACHINE_START(SMDK4212, "SMDK4x12") .map_io = midas_map_io, .init_machine = midas_machine_init, .timer = &exynos4_timer, -#ifdef CONFIG_EXYNOS_C2C +#if defined(CONFIG_EXYNOS_C2C) .reserve = &exynos_c2c_reserve, +#elif defined(CONFIG_DMA_CMA) + .reserve = &exynos4_reserve, #endif .init_early = &exynos_init_reserve, MACHINE_END diff --git a/arch/arm/mach-exynos/mach-p10.c b/arch/arm/mach-exynos/mach-p10.c deleted file mode 100644 index 5ee8289..0000000 --- a/arch/arm/mach-exynos/mach-p10.c +++ /dev/null @@ -1,3091 +0,0 @@ -/* linux/arch/arm/mach-exynos/mach-p10.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/platform_device.h> -#include <linux/serial_core.h> -#include <linux/spi/spi.h> -#include <linux/spi/spi_gpio.h> -#include <linux/clk.h> -#include <linux/gpio.h> -#include <linux/gpio_event.h> -#include <linux/gpio_keys.h> -#include <linux/i2c.h> -#include <linux/i2c-gpio.h> -#include <linux/pwm_backlight.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <linux/mmc/host.h> -#include <linux/memblock.h> -#include <linux/fb.h> -#include <linux/delay.h> -#include <linux/notifier.h> -#include <linux/reboot.h> - -#include <video/platform_lcd.h> -#include <video/s5p-dp.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <media/exynos_gscaler.h> -#include <media/exynos_flite.h> -#include <media/exynos_fimc_is.h> -#include <plat/gpio-cfg.h> -#include <plat/adc.h> -#include <plat/regs-serial.h> -#include <plat/exynos5.h> -#include <plat/cpu.h> -#include <plat/clock.h> -#include <plat/hwmon.h> -#include <plat/devs.h> -#include <plat/sdhci.h> - -#include <plat/fb.h> -#include <plat/fb-s5p.h> -#include <plat/fb-core.h> -#include <plat/regs-fb-v4.h> -#include <plat/iic.h> -#include <plat/pd.h> -#include <plat/ehci.h> -#include <plat/s5p-mfc.h> -#include <plat/dp.h> -#include <plat/backlight.h> -#include <plat/usbgadget.h> -#include <plat/fimg2d.h> -#include <plat/tv-core.h> -#include <plat/s3c64xx-spi.h> - -#include <plat/mipi_csis.h> -#include <mach/map.h> -#include <mach/exynos-ion.h> -#include <mach/sysmmu.h> -#include <mach/spi-clocks.h> -#include <mach/ppmu.h> -#include <mach/dev.h> -#include <mach/pmu.h> -#include <mach/regs-pmu.h> -#include <mach/dwmci.h> -#ifdef CONFIG_VIDEO_JPEG_V2X -#include <plat/jpeg.h> -#endif - -#ifdef CONFIG_EXYNOS_C2C -#include <mach/c2c.h> -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_TV -#include <plat/tvout.h> -#endif - -#ifdef CONFIG_MFD_MAX77686 -#include <linux/mfd/max77686.h> -#endif - -#ifdef CONFIG_SENSORS_BH1721FVC -#include <linux/bh1721fvc.h> -#endif - -#include <mach/gpio-p10.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu5.h> -#include <mach/midas-sound.h> - -#if defined(CONFIG_SEC_DEBUG) -#include <mach/sec_debug.h> -#endif - -#ifdef CONFIG_MPU_SENSORS_MPU6050 -#include <linux/mpu_411.h> -#endif - -#ifdef CONFIG_EXYNOS4_SETUP_THERMAL -#include <plat/s5p-tmu.h> -#include <mach/regs-tmu.h> -#endif -#include <plat/media.h> - -#ifdef CONFIG_BATTERY_SAMSUNG_P1X -#include <mach/p10-battery.h> -#endif - -#ifdef CONFIG_STMPE811_ADC -#include <linux/stmpe811-adc.h> -struct stmpe811_platform_data stmpe811_pdata; -#endif - -#include <mach/p10-input.h> -#ifdef CONFIG_LEDS_SPFCW043 -#include <linux/leds-spfcw043.h> -#endif - -#include "p10-wlan.h" - -#ifdef CONFIG_FB_S5P_EXTDSP -struct s3cfb_extdsp_lcd { - int width; - int height; - int bpp; -}; -#endif - -#ifdef CONFIG_MPU_SENSORS_MPU6050 - struct mpu_platform_data mpu6050_data = { - .int_config = 0x10, - .orientation = {0, 1, 0, - 1, 0, 0, - 0, 0, -1}, - .enable_irq_handler = NULL, - }; - -static struct ext_slave_platform_data mpu_ak8975_data = { - .bus = EXT_SLAVE_BUS_PRIMARY, - .adapt_num = 11, - .orientation = {1, 0, 0, - 0, 1, 0, - 0, 0, 1}, - .address = 0x0C, - .irq = IRQ_EINT(18), - }; - -static struct i2c_gpio_platform_data gpio_i2c_data11 = { - .sda_pin = GPIO_MSENSE_SDA, - .scl_pin = GPIO_MSENSE_SCL, -}; - -struct platform_device s3c_device_i2c11 = { - .name = "i2c-gpio", - .id = 11, - .dev.platform_data = &gpio_i2c_data11, -}; - -static struct i2c_board_info i2c_devs11[] __initdata = { - { - I2C_BOARD_INFO("ak8975_mod", 0x0C), - .irq = IRQ_EINT(18), - .platform_data = &mpu_ak8975_data, - }, -}; - -static struct i2c_board_info i2c_devs1[] __initdata = { - { - I2C_BOARD_INFO("mpu6050",0x68), - .irq = IRQ_EINT(12), - .platform_data = &mpu6050_data, - }, -/* - { - I2C_BOARD_INFO("ak8975_mod",0x0C), - .irq = IRQ_EINT(18), - .platform_data = &mpu_ak8975_data, - }, -*/ -}; - -void magnetic_init() -{ - pr_info("%s : AK8963C Init", __func__); - s3c_gpio_cfgpin(GPIO_MSENSE_RST, S3C_GPIO_SFN(S3C_GPIO_OUTPUT)); - s3c_gpio_setpull(GPIO_MSENSE_RST, S3C_GPIO_PULL_UP); - gpio_set_value(GPIO_MSENSE_RST, 0); - usleep_range(20, 20); - gpio_set_value(GPIO_MSENSE_RST, 1); -} - -#else -static struct i2c_board_info i2c_devs1[] __initdata = { - { - I2C_BOARD_INFO("dummy", (0x10)), - } -}; -#endif /* CONFIG_MPU_SENSORS_MPU6050 */ - - -#define REG_INFORM4 (S5P_INFORM4) - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define SMDK5250_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define SMDK5250_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define SMDK5250_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -#ifdef CONFIG_30PIN_CONN -#include <linux/30pin_con.h> -#endif - -#ifdef CONFIG_MOTOR_DRV_ISA1200 -#include <linux/isa1200_vibrator.h> -#endif - -static struct s3c2410_uartcfg smdk5250_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = SMDK5250_UCON_DEFAULT, - .ulcon = SMDK5250_ULCON_DEFAULT, - .ufcon = SMDK5250_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = SMDK5250_UCON_DEFAULT, - .ulcon = SMDK5250_ULCON_DEFAULT, - .ufcon = SMDK5250_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = SMDK5250_UCON_DEFAULT, - .ulcon = SMDK5250_ULCON_DEFAULT, - .ufcon = SMDK5250_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = SMDK5250_UCON_DEFAULT, - .ulcon = SMDK5250_ULCON_DEFAULT, - .ufcon = SMDK5250_UFCON_DEFAULT, - }, -}; - -#ifdef CONFIG_EXYNOS_MEDIA_DEVICE -struct platform_device exynos_device_md0 = { - .name = "exynos-mdev", - .id = 0, -}; - -struct platform_device exynos_device_md1 = { - .name = "exynos-mdev", - .id = 1, -}; -struct platform_device exynos_device_md2 = { - .name = "exynos-mdev", - .id = 2, -}; -#endif - -#if defined(CONFIG_DP_40HZ_P10) -#define FPS 40 -#elif defined(CONFIG_DP_60HZ_P10) -#define FPS 60 -#endif -#ifdef CONFIG_FB_S3C -#if defined(CONFIG_MACH_P10_DP_01) - -static struct s3c_fb_pd_win p10_fb_win0 = { - .win_mode = { - .refresh = FPS, - .left_margin = 80, - .right_margin = 48, - .upper_margin = 37, - .lower_margin = 3, - .hsync_len = 32, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - }, - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, -}; - -static struct s3c_fb_pd_win p10_fb_win1 = { - .win_mode = { - .refresh = FPS, - .left_margin = 80, - .right_margin = 48, - .upper_margin = 37, - .lower_margin = 3, - .hsync_len = 32, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - }, - - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, - -}; - -static struct s3c_fb_pd_win p10_fb_win2 = { - .win_mode = { - .refresh = FPS, - .left_margin = 80, - .right_margin = 48, - .upper_margin = 37, - .lower_margin = 3, - .hsync_len = 32, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - }, - - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, - -}; - -static struct s3c_fb_pd_win p10_fb_win3 = { - .win_mode = { - .refresh = FPS, - .left_margin = 80, - .right_margin = 48, - .upper_margin = 37, - .lower_margin = 3, - .hsync_len = 32, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - }, - - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, - -}; - -static struct s3c_fb_pd_win p10_fb_win4 = { - .win_mode = { - .refresh = FPS, - .left_margin = 80, - .right_margin = 48, - .upper_margin = 37, - .lower_margin = 3, - .hsync_len = 32, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - }, - - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, - -}; - -#elif defined(CONFIG_MACH_P10_DP_00) - -static struct s3c_fb_pd_win p10_fb_win0 = { - .win_mode = { - .refresh = 20, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 20, - .lower_margin = 3, - .hsync_len = 16, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - }, - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, -}; - -static struct s3c_fb_pd_win p10_fb_win1 = { - .win_mode = { - .refresh = 20, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 20, - .lower_margin = 3, - .hsync_len = 16, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - - }, - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, - -}; - -static struct s3c_fb_pd_win p10_fb_win2 = { - .win_mode = { - .refresh = 20, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 20, - .lower_margin = 3, - .hsync_len = 16, - .vsync_len = 6, - .xres = 2560, - .yres = 1600, - - }, - .virtual_x = 2560, - .virtual_y = 1640 * 2, - .max_bpp = 32, - .default_bpp = 24, - -}; -#endif -static void exynos_fimd_gpio_setup_24bpp(void) -{ - unsigned int reg = 0; - unsigned int uRead = 0; - -#if defined(CONFIG_S5P_DP) - /* Set Hotplug detect for DP */ - s3c_gpio_cfgpin(GPIO_DP_HPD, S3C_GPIO_SFN(3)); -#endif - /* - * Set DISP1BLK_CFG register for Display path selection - * - * FIMD of DISP1_BLK Bypass selection : DISP1BLK_CFG[15] - * --------------------- - * 0 | MIE/MDNIE - * 1 | FIMD : selected - */ - reg = __raw_readl(S3C_VA_SYS + 0x0214); - reg &= ~(1 << 15); /* To save other reset values */ - reg |= (1 << 15); - __raw_writel(reg, S3C_VA_SYS + 0x0214); -#if defined(CONFIG_S5P_DP) -#if defined(CONFIG_MACH_P10_DP_01) - // MPLL => FIMD Bus clock - uRead = __raw_readl(EXYNOS5_CLKSRC_TOP0); - uRead = (uRead & ~(0x3<<14)) | (0x0<<14); - __raw_writel(uRead, EXYNOS5_CLKSRC_TOP0); - - uRead = __raw_readl(EXYNOS5_CLKDIV_TOP0); - uRead = (uRead & ~(0x7<<28)) | (0x2<<28); - __raw_writel(uRead,EXYNOS5_CLKDIV_TOP0); - - /* Reference clcok selection for DPTX_PHY: pad_osc_clk_24M */ - reg = __raw_readl(S3C_VA_SYS + 0x04d4); - reg = (reg & ~(0x1 << 0)) | (0x0 << 0); - __raw_writel(reg, S3C_VA_SYS + 0x04d4); - - /* DPTX_PHY: XXTI */ - reg = __raw_readl(S3C_VA_SYS + 0x04d8); - reg = (reg & ~(0x1 << 3)) | (0x0 << 3); - __raw_writel(reg, S3C_VA_SYS + 0x04d8); -#elif defined(CONFIG_MACH_P10_DP_00) - - reg = __raw_readl(S3C_VA_SYS + 0x04d4); - reg |= (1 << 0); - __raw_writel(reg, S3C_VA_SYS + 0x04d4); - - /* DPTX_PHY: XXTI */ - reg = __raw_readl(S3C_VA_SYS + 0x04d8); - reg &= ~(1 << 3); - __raw_writel(reg, S3C_VA_SYS + 0x04d8); -#endif -#endif -} - -static struct s3c_fb_platdata p10_lcd1_pdata __initdata = { - .win[0] = &p10_fb_win0, - .win[1] = &p10_fb_win1, - .win[2] = &p10_fb_win2, - .win[3] = &p10_fb_win3, - .win[4] = &p10_fb_win4, - .default_win = 2, - .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, - .vidcon1 = 0, - .setup_gpio = exynos_fimd_gpio_setup_24bpp, -}; -#endif - -#if defined CONFIG_VIDEO_EXYNOS5_FIMC_IS -static struct exynos5_platform_fimc_is exynos5_fimc_is_data; - -#if defined CONFIG_VIDEO_S5K4E5 -static struct exynos5_fimc_is_sensor_info s5k4e5= { - .sensor_name = "S5K4E5", - .sensor_id = SENSOR_NAME_S5K4E5, -#if defined CONFIG_S5K4E5_POSITION_FRONT - .sensor_position = SENSOR_POSITION_FRONT, -#elif defined CONFIG_S5K4E5_POSITION_REAR - .sensor_position = SENSOR_POSITION_REAR, -#endif -#if defined CONFIG_S5K4E5_CSI_C - .csi_id = CSI_ID_A, - .flite_id = FLITE_ID_A, - .i2c_channel = SENSOR_CONTROL_I2C0, -#elif defined CONFIG_S5K4E5_CSI_D - .csi_id = CSI_ID_B, - .flite_id = FLITE_ID_B, - .i2c_channel = SENSOR_CONTROL_I2C1, -#endif - - .max_width = 2560, - .max_height = 1920, - .max_frame_rate = 30, - - .mipi_lanes = 2, - .mipi_settle = 12, - .mipi_align = 24, -}; -#endif - -#if defined CONFIG_VIDEO_S5K6A3 -static struct exynos5_fimc_is_sensor_info s5k6a3= { - .sensor_name = "S5K6A3", - .sensor_id = SENSOR_NAME_S5K6A3, -#if defined CONFIG_S5K6A3_POSITION_FRONT - .sensor_position = SENSOR_POSITION_FRONT, -#elif defined CONFIG_S5K6A3_POSITION_REAR - .sensor_position = SENSOR_POSITION_REAR, -#endif -#if defined CONFIG_S5K6A3_CSI_C - .csi_id = CSI_ID_A, - .flite_id = FLITE_ID_A, - .i2c_channel = SENSOR_CONTROL_I2C0, -#elif defined CONFIG_S5K6A3_CSI_D - .csi_id = CSI_ID_B, - .flite_id = FLITE_ID_B, - .i2c_channel = SENSOR_CONTROL_I2C1, -#endif - - .max_width = 1280, - .max_height = 720, - .max_frame_rate = 30, - - .mipi_lanes = 1, - .mipi_settle = 12, - .mipi_align = 24, -}; -#endif -#endif - -#ifdef CONFIG_S5P_DP -static void dp_lcd_set_power(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) { - - /* LCD_PWM_IN_2.8V, AH21, XPWMOUT_0 => LCD_B_PWM */ -#ifndef CONFIG_BACKLIGHT_PWM - gpio_request_one(GPIO_LCD_PWM_IN_18V, GPIOF_OUT_INIT_LOW, "GPB2"); -#endif - -#ifdef CONFIG_MACH_P10_00_BD - /* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */ - gpio_request_one(GPIO_LCD_APS_EN_18V, GPIOF_OUT_INIT_LOW, "GPG0"); -#endif - /* LCD_EN , XMMC2CDN => GPC2_2 */ - gpio_request_one(GPIO_LCD_EN, GPIOF_OUT_INIT_LOW, "GPC2"); - - /* LCD_EN , XMMC2CDN => GPC2_2 */ - gpio_set_value(GPIO_LCD_EN, 1); - -#ifdef CONFIG_MACH_P10_00_BD - /* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */ - gpio_set_value(GPIO_LCD_APS_EN_18V, 1); -#endif - - udelay(1000); - - /* LCD_PWM_IN_2.8V, AH21, XPWMOUT_0=> LCD_B_PWM */ -#ifndef CONFIG_BACKLIGHT_PWM - gpio_set_value(GPIO_LCD_PWM_IN_18V, 1); -#endif - } else { - /* LCD_PWM_IN_2.8V, AH21, XPWMOUT_0=> LCD_B_PWM */ -#ifndef CONFIG_BACKLIGHT_PWM - gpio_set_value(GPIO_LCD_PWM_IN_18V, 0); -#endif - -#ifdef CONFIG_MACH_P10_00_BD - /* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */ - gpio_set_value(GPIO_LCD_APS_EN_18V, 0); -#endif - - /* LCD_EN , XMMC2CDN => GPC2_2 */ - gpio_set_value(GPIO_LCD_EN, 0); - -#ifdef CONFIG_MACH_P10_00_BD - /* LCD_APS_EN_2.8V, R6, XCI1RGB_2 => GPG0_2 */ - gpio_free(GPIO_LCD_APS_EN_18V); -#endif - - /* LCD_EN , XMMC2CDN => GPC2_2 */ - gpio_free(GPIO_LCD_EN); - -#ifndef CONFIG_BACKLIGHT_PWM - gpio_free(GPIO_LCD_PWM_IN_18V); -#endif - } -} - -static struct plat_lcd_data p10_dp_lcd_data = { - .set_power = dp_lcd_set_power, -}; - -static struct platform_device p10_dp_lcd = { - .name = "platform-lcd", - .dev.parent = &s5p_device_fimd1.dev, - .dev.platform_data = &p10_dp_lcd_data, -}; - -static struct video_info p10_dp_config = { - .name = "for p10 TEST", -#if defined(CONFIG_MACH_P10_DP_01) - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - - .link_rate = LINK_RATE_2_70GBPS, - .lane_count = LANE_COUNT4, - -#elif defined(CONFIG_MACH_P10_DP_00) - - .h_sync_polarity = 0, - .v_sync_polarity = 0, - .interlaced = 0, - - .color_space = COLOR_RGB, - .dynamic_range = VESA, - .ycbcr_coeff = COLOR_YCBCR601, - .color_depth = COLOR_8, - - .link_rate = LINK_RATE_1_62GBPS, - .lane_count = LANE_COUNT4, -#endif -}; - -static void s5p_dp_backlight_on(void) -{ - /* LED_BACKLIGHT_RESET: XCI1RGB_5 => GPG0_5 */ - gpio_request_one(GPIO_LED_BACKLIGHT_RESET, GPIOF_OUT_INIT_LOW, "GPG0"); - - gpio_set_value(GPIO_LED_BACKLIGHT_RESET, 1); -} - -static void s5p_dp_backlight_off(void) -{ - /* LED_BACKLIGHT_RESET: XCI1RGB_5 => GPG0_5 */ - gpio_set_value(GPIO_LED_BACKLIGHT_RESET, 0); - - gpio_free(GPIO_LED_BACKLIGHT_RESET); - -} - -static struct s5p_dp_platdata p10_dp_data __initdata = { - .video_info = &p10_dp_config, - .phy_init = s5p_dp_phy_init, - .phy_exit = s5p_dp_phy_exit, - .backlight_on = s5p_dp_backlight_on, - .backlight_off = s5p_dp_backlight_off, -}; -#endif - -/* LCD Backlight data */ -#ifdef CONFIG_BACKLIGHT_PWM -static struct samsung_bl_gpio_info p10_bl_gpio_info = { - .no = GPIO_LCD_PWM_IN_18V, - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data p10_bl_data = { - .pwm_id = 0, - .pwm_period_ns = 10000, -}; -#endif - -#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) -static struct s5p_mfc_platdata smdk5250_mfc_pd = { - .clock_rate = 333000000, -}; -#endif - -#ifdef CONFIG_EXYNOS_C2C -struct exynos_c2c_platdata smdk5250_c2c_pdata = { - .setup_gpio = NULL, - .shdmem_addr = C2C_SHAREDMEM_BASE, - .shdmem_size = C2C_MEMSIZE_64, - .ap_sscm_addr = NULL, - .cp_sscm_addr = NULL, - .rx_width = C2C_BUSWIDTH_16, - .tx_width = C2C_BUSWIDTH_16, - .clk_opp100 = 400, - .clk_opp50 = 200, - .clk_opp25 = 100, - .default_opp_mode = C2C_OPP25, - .get_c2c_state = NULL, - .c2c_sysreg = S3C_VA_SYS + 0x0360, -}; -#endif - -static int exynos5_notifier_call(struct notifier_block *this, - unsigned long code, void *_cmd) -{ - int mode = 0; - - if ((code == SYS_RESTART) && _cmd) - if (!strcmp((char *)_cmd, "recovery")) - mode = 0xf; - - __raw_writel(mode, REG_INFORM4); - - return NOTIFY_DONE; -} - -static struct notifier_block exynos5_reboot_notifier = { - .notifier_call = exynos5_notifier_call, -}; - -#ifdef CONFIG_EXYNOS4_DEV_DWMCI -static void exynos_dwmci_cfg_gpio(int width) -{ - unsigned int gpio; - - for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); - } - - switch (width) { - case MMC_BUS_WIDTH_8: - for (gpio = EXYNOS5_GPC1(3); gpio <= EXYNOS5_GPC1(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); - } - case MMC_BUS_WIDTH_4: - for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); - } - break; - case MMC_BUS_WIDTH_1: - gpio = EXYNOS5_GPC0(3); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); - default: - break; - } -} - -static struct dw_mci_board exynos_dwmci_pdata __initdata = { - .num_slots = 1, - .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED, - .bus_hz = 66 * 1000 * 1000, - .caps = MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, - .fifo_depth = 0x80, - .detect_delay_ms = 200, - .hclk_name = "dwmci", - .cclk_name = "sclk_dwmci", - .cfg_gpio = exynos_dwmci_cfg_gpio, -}; -#endif - -static void exynos_dwmci0_cfg_gpio(int width) -{ - unsigned int gpio; - - for (gpio = EXYNOS5_GPC0(0); gpio < EXYNOS5_GPC0(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - - switch (width) { - case MMC_BUS_WIDTH_8: - for (gpio = EXYNOS5_GPC1(0); gpio <= EXYNOS5_GPC1(3); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - case MMC_BUS_WIDTH_4: - for (gpio = EXYNOS5_GPC0(3); gpio <= EXYNOS5_GPC0(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } - break; - case MMC_BUS_WIDTH_1: - gpio = EXYNOS5_GPC0(3); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - default: - break; - } -} - -static struct dw_mci_board exynos5_dwmci0_pdata __initdata = { - .num_slots = 1, - .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED, - .bus_hz = 100 * 1000 * 1000, - .caps = MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, - .fifo_depth = 0x80, - .detect_delay_ms = 200, - .hclk_name = "dwmci", - .cclk_name = "sclk_dwmci", - .cfg_gpio = exynos_dwmci0_cfg_gpio, -}; - -static void exynos_dwmci1_cfg_gpio(int width) -{ - unsigned int gpio; - for (gpio = EXYNOS5_GPC2(0); gpio < EXYNOS5_GPC2(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); - } - - switch (width) { - case MMC_BUS_WIDTH_4: - for (gpio = EXYNOS5_GPC2(3); gpio <= EXYNOS5_GPC2(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); - } - break; - case MMC_BUS_WIDTH_1: - gpio = EXYNOS5_GPC2(3); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); - default: - break; - } -} - -static void (*wlan_notify_func)(struct platform_device *dev, int state); -static DEFINE_MUTEX(wlan_mutex_lock); - -static int ext_cd_init_wlan(void (*notify_func)(struct platform_device *dev, int state)) -{ - mutex_lock(&wlan_mutex_lock); - WARN_ON(wlan_notify_func); - - wlan_notify_func = notify_func; - - if (wlan_notify_func) { - if (samsung_rev() >= EXYNOS5250_REV_1_0) - wlan_notify_func(&exynos_device_dwmci1, 1); - else - wlan_notify_func(&s3c_device_hsmmc3, 1); - } - - mutex_unlock(&wlan_mutex_lock); - - return 0; -} - -static int ext_cd_cleanup_wlan(void (*notify_func)(struct platform_device *dev, int state)) -{ - mutex_lock(&wlan_mutex_lock); - WARN_ON(wlan_notify_func); - - if (wlan_notify_func) { - if (samsung_rev() >= EXYNOS5250_REV_1_0) - wlan_notify_func(&exynos_device_dwmci1, 0); - else - wlan_notify_func(&s3c_device_hsmmc3, 0); - } - - wlan_notify_func = NULL; - - mutex_unlock(&wlan_mutex_lock); - - return 0; -} - -static struct dw_mci_board exynos5_dwmci1_pdata __initdata = { - .num_slots = 1, - .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION | DW_MCI_QUIRK_HIGHSPEED, - .bus_hz = 50 * 1000 * 1000, - .caps = MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23, - .fifo_depth = 0x80, - .detect_delay_ms = 200, - .hclk_name = "dwmci", - .cclk_name = "sclk_dwmci", - .cfg_gpio = exynos_dwmci1_cfg_gpio, - .ext_cd_init = ext_cd_init_wlan, - .ext_cd_cleanup = ext_cd_cleanup_wlan, - .cd_type = DW_MCI_CD_EXTERNAL, -}; - -void mmc_force_presence_change(struct platform_device *pdev) -{ - void (*notify_func)(struct platform_device *, int state) = NULL; - mutex_lock(&wlan_mutex_lock); - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - if (pdev == &exynos_device_dwmci1) - notify_func = wlan_notify_func; - } else { - if (pdev == &s3c_device_hsmmc3) - notify_func = wlan_notify_func; - } - - if (notify_func) - notify_func(pdev, 1); - else - pr_warn("%s: called for device with no notifier\n", __func__); - mutex_unlock(&wlan_mutex_lock); -} -EXPORT_SYMBOL_GPL(mmc_force_presence_change); - -static int smdk5250_dwmci_get_ro(u32 slot_id) -{ - /* smdk5250 rev1.0 did not support SD/MMC card write pritect. */ - return 0; -} - -static void exynos_dwmci2_cfg_gpio(int width) -{ - unsigned int gpio; - - for (gpio = EXYNOS5_GPC3(0); gpio <= EXYNOS5_GPC3(2); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); - } - - switch (width) { - case MMC_BUS_WIDTH_4: - for (gpio = EXYNOS5_GPC3(3); gpio <= EXYNOS5_GPC3(6); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); - } - break; - case MMC_BUS_WIDTH_1: - gpio = EXYNOS5_GPC3(3); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); - default: - break; - } -} - -static struct dw_mci_board exynos5_dwmci2_pdata __initdata = { - .num_slots = 1, - .quirks = DW_MCI_QUIRK_HIGHSPEED, - .bus_hz = 22 * 1000 * 1000, - .caps = MMC_CAP_CMD23, - .fifo_depth = 0x80, - .detect_delay_ms = 200, - .hclk_name = "dwmci", - .cclk_name = "sclk_dwmci", - .cfg_gpio = exynos_dwmci2_cfg_gpio, - .get_ro = smdk5250_dwmci_get_ro, -}; - -#ifdef CONFIG_VIDEO_FIMG2D -static struct fimg2d_platdata fimg2d_data __initdata = { - .hw_ver = 0x42, - .gate_clkname = "fimg2d", -}; -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC -static struct s3c_sdhci_platdata smdk5250_hsmmc0_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_PERMANENT, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC1 -static struct s3c_sdhci_platdata smdk5250_hsmmc1_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, -}; -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC2 -static struct s3c_sdhci_platdata smdk5250_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, - .ext_cd_gpio = GPIO_T_FLASH_DETECT, - .ext_cd_gpio_invert = true, -#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; -#endif - -struct class *camera_class; -EXPORT_SYMBOL(camera_class); - -#ifdef CONFIG_S3C_DEV_HSMMC3 -static struct s3c_sdhci_platdata smdk5250_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_EXTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, - .pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME, - /* ext_cd_xxx should be used in only .cd_type = S3C_SDHCI_CD_EXTERNAL */ - .ext_cd_init = ext_cd_init_wlan, - .ext_cd_cleanup = ext_cd_cleanup_wlan, -}; -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI -static struct s3c64xx_spi_csinfo spi1_csi[] = { - [0] = { - .line = GPIO_5M_SPI_CS, - .set_level = gpio_set_value, - .fb_delay = 0x2, - }, -}; - -static struct spi_board_info spi1_board_info[] __initdata = { - { - .modalias = "spidev", - .platform_data = NULL, - .max_speed_hz = 10*1000*1000, - .bus_num = 1, - .chip_select = 0, - .mode = SPI_MODE_0, - .controller_data = &spi1_csi[0], - } -}; -#endif - -#ifdef CONFIG_LEDS_SPFCW043 -static int spfcw043_setGpio(void) -{ - int err; - - err = gpio_request(GPIO_CAM_FLASH_EN, "TORCH_EN"); - if (err) { - printk(KERN_ERR "failed to request TORCH_EN\n"); - return -EPERM; - } - gpio_direction_output(GPIO_CAM_FLASH_EN, 1); - err = gpio_request(GPIO_CAM_FLASH_SET, "TORCH_SET"); - if (err) { - printk(KERN_ERR "failed to request TORCH_SET\n"); - gpio_free(GPIO_CAM_FLASH_EN); - return -EPERM; - } - gpio_direction_output(GPIO_CAM_FLASH_SET, 1); - gpio_set_value(GPIO_CAM_FLASH_EN, 0); - gpio_set_value(GPIO_CAM_FLASH_SET, 0); - - return 0; -} - -static int spfcw043_freeGpio(void) -{ - gpio_free(GPIO_CAM_FLASH_EN); - gpio_free(GPIO_CAM_FLASH_SET); - - return 0; -} - -static void spfcw043_torch_en(int onoff) -{ - gpio_set_value(GPIO_CAM_FLASH_EN, onoff); -} - -static void spfcw043_torch_set(int onoff) -{ - gpio_set_value(GPIO_CAM_FLASH_SET, onoff); -} - -static struct spfcw043_led_platform_data spfcw043_led_data = { - .brightness = TORCH_BRIGHTNESS_50, - .status = STATUS_UNAVAILABLE, - .setGpio = spfcw043_setGpio, - .freeGpio = spfcw043_freeGpio, - .torch_en = spfcw043_torch_en, - .torch_set = spfcw043_torch_set, -}; - -static struct platform_device s3c_device_spfcw043_led = { - .name = "spfcw043-led", - .id = -1, - .dev = { - .platform_data = &spfcw043_led_data, - }, -}; -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE -#if defined(CONFIG_ITU_A) -static int smdk5250_cam0_reset(int dummy) -{ - int err; - /* Camera A */ - err = gpio_request(EXYNOS5_GPX1(2), "GPX1"); - if (err) - printk(KERN_ERR "#### failed to request GPX1_2 ####\n"); - - s3c_gpio_setpull(EXYNOS5_GPX1(2), S3C_GPIO_PULL_NONE); - gpio_direction_output(EXYNOS5_GPX1(2), 0); - gpio_direction_output(EXYNOS5_GPX1(2), 1); - gpio_free(EXYNOS5_GPX1(2)); - - return 0; -} -#endif -#if defined(CONFIG_ITU_B) -static int smdk5250_cam1_reset(int dummy) -{ - int err; - /* Camera A */ - err = gpio_request(EXYNOS5_GPX1(0), "GPX1"); - if (err) - printk(KERN_ERR "#### failed to request GPX1_2 ####\n"); - - s3c_gpio_setpull(EXYNOS5_GPX1(0), S3C_GPIO_PULL_NONE); - gpio_direction_output(EXYNOS5_GPX1(0), 0); - gpio_direction_output(EXYNOS5_GPX1(0), 1); - gpio_free(EXYNOS5_GPX1(0)); - - return 0; -} -#endif - -#ifdef CONFIG_VIDEO_S5K4BA -static struct s5k4ba_mbus_platform_data s5k4ba_mbus_plat = { - .id = 0, - .fmt = { - .width = 1600, - .height = 1200, - /* .code = V4L2_MBUS_FMT_UYVY8_2X8, */ - .code = V4L2_MBUS_FMT_VYUY8_2X8, - }, - .clk_rate = 24000000UL, -#ifdef CONFIG_ITU_A - .set_power = smdk5250_cam0_reset, -#endif -#ifdef CONFIG_ITU_B - .set_power = smdk5250_cam1_reset, -#endif -}; - -static struct i2c_board_info s5k4ba_info = { - I2C_BOARD_INFO("S5K4BA", 0x2d), - .platform_data = &s5k4ba_mbus_plat, -}; -#endif - -/* 1 MIPI Cameras */ -#ifdef CONFIG_VIDEO_M5MOLS -static struct m5mols_platform_data m5mols_platdata = { -#ifdef CONFIG_CSI_C - .gpio_rst = EXYNOS5_GPX1(2), /* ISP_RESET */ -#endif -#ifdef CONFIG_CSI_D - .gpio_rst = EXYNOS5_GPX1(0), /* ISP_RESET */ -#endif - .enable_rst = true, /* positive reset */ - .irq = IRQ_EINT(22), -}; - -static struct i2c_board_info m5mols_board_info = { - I2C_BOARD_INFO("M5MOLS", 0x1F), - .platform_data = &m5mols_platdata, -}; -#endif -#endif /* CONFIG_VIDEO_EXYNOS_FIMC_LITE */ - -#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS -static struct regulator_consumer_supply mipi_csi_fixed_voltage_supplies[] = { - REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.0"), - REGULATOR_SUPPLY("mipi_csi", "s5p-mipi-csis.1"), -}; - -static struct regulator_init_data mipi_csi_fixed_voltage_init_data = { - .constraints = { - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(mipi_csi_fixed_voltage_supplies), - .consumer_supplies = mipi_csi_fixed_voltage_supplies, -}; - -static struct fixed_voltage_config mipi_csi_fixed_voltage_config = { - .supply_name = "DC_5V", - .microvolts = 5000000, - .gpio = -EINVAL, - .init_data = &mipi_csi_fixed_voltage_init_data, -}; - -static struct platform_device mipi_csi_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = 3, - .dev = { - .platform_data = &mipi_csi_fixed_voltage_config, - }, -}; -#endif - -#ifdef CONFIG_VIDEO_M5MOLS -static struct regulator_consumer_supply m5mols_fixed_voltage_supplies[] = { - REGULATOR_SUPPLY("core", NULL), - REGULATOR_SUPPLY("dig_18", NULL), - REGULATOR_SUPPLY("d_sensor", NULL), - REGULATOR_SUPPLY("dig_28", NULL), - REGULATOR_SUPPLY("a_sensor", NULL), - REGULATOR_SUPPLY("dig_12", NULL), -}; - -static struct regulator_init_data m5mols_fixed_voltage_init_data = { - .constraints = { - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(m5mols_fixed_voltage_supplies), - .consumer_supplies = m5mols_fixed_voltage_supplies, -}; - -static struct fixed_voltage_config m5mols_fixed_voltage_config = { - .supply_name = "CAM_SENSOR", - .microvolts = 1800000, - .gpio = -EINVAL, - .init_data = &m5mols_fixed_voltage_init_data, -}; - -static struct platform_device m5mols_fixed_voltage = { - .name = "reg-fixed-voltage", - .id = 4, - .dev = { - .platform_data = &m5mols_fixed_voltage_config, - }, -}; -#endif - -#if defined(CONFIG_REGULATOR_MAX77686) -/* max77686 */ -#ifdef CONFIG_SND_SOC_WM8994 -static struct regulator_consumer_supply ldo3_supply[] = { - REGULATOR_SUPPLY("vcc_1.8v", NULL), - REGULATOR_SUPPLY("AVDD2", NULL), - REGULATOR_SUPPLY("CPVDD", NULL), - REGULATOR_SUPPLY("DBVDD1", NULL), - REGULATOR_SUPPLY("DBVDD2", NULL), - REGULATOR_SUPPLY("DBVDD3", NULL) -}; -#else -static struct regulator_consumer_supply ldo3_supply[] = { - REGULATOR_SUPPLY("vcc_1.8v", NULL), -}; -#endif - -static struct regulator_consumer_supply ldo4_supply[] = { - REGULATOR_SUPPLY("vcc_2.8v", NULL), -}; - -static struct regulator_consumer_supply ldo5_supply[] = { - REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL), -}; - -static struct regulator_consumer_supply ldo8_supply[] = { - REGULATOR_SUPPLY("vmipi_1.0v", NULL), -}; - -static struct regulator_consumer_supply ldo9_supply[] = { - REGULATOR_SUPPLY("touch_vdd_1.8v", NULL), -}; - -static struct regulator_consumer_supply ldo10_supply[] = { - REGULATOR_SUPPLY("vmipi_1.8v", NULL), -}; - -static struct regulator_consumer_supply ldo11_supply[] = { - REGULATOR_SUPPLY("vabb1_1.9v", NULL), -}; - -static struct regulator_consumer_supply ldo12_supply[] = { - REGULATOR_SUPPLY("votg_3.0v", NULL), -}; - -static struct regulator_consumer_supply ldo14_supply[] = { - REGULATOR_SUPPLY("vabb02_1.8v", NULL), -}; - -static struct regulator_consumer_supply ldo15_supply[] = { - REGULATOR_SUPPLY("vhsic_1.0v", NULL), -}; - -static struct regulator_consumer_supply ldo16_supply[] = { - REGULATOR_SUPPLY("vhsic_1.8v", NULL), -}; - -#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \ - defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD) -static struct regulator_consumer_supply ldo17_supply[] = { - REGULATOR_SUPPLY("cam_core_1.8v", NULL), -}; -#endif -static struct regulator_consumer_supply ldo18_supply[] = { - REGULATOR_SUPPLY("cam_io_from_1.8v", NULL), -}; - -static struct regulator_consumer_supply ldo19_supply[] = { - REGULATOR_SUPPLY("vt_cam_1.8v", NULL), -}; - -static struct regulator_consumer_supply ldo20_supply[] = { - REGULATOR_SUPPLY("vmem_vdd_1.8v", NULL), -}; - -static struct regulator_consumer_supply ldo21_supply[] = { - REGULATOR_SUPPLY("vtf_2.8v", NULL), -}; - -#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \ - defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD) -static struct regulator_consumer_supply ldo22_supply[] = { - REGULATOR_SUPPLY("vcc_mmc_2.8v", NULL), -}; -#else -static struct regulator_consumer_supply ldo22_supply[] = { - REGULATOR_SUPPLY("cam_core_1.8v", NULL), -}; -#endif -static struct regulator_consumer_supply ldo23_supply[] = { - REGULATOR_SUPPLY("touch_avdd", NULL), -}; - -static struct regulator_consumer_supply ldo24_supply[] = { - REGULATOR_SUPPLY("cam_af_2.8v", NULL), -}; -static struct regulator_consumer_supply ldo25_supply[] = { - REGULATOR_SUPPLY("vadc_3.3v", NULL), -}; - -static struct regulator_consumer_supply ldo26_supply[] = { - REGULATOR_SUPPLY("irda_3.3v", NULL), -}; - -static struct regulator_consumer_supply max77686_buck1 = - REGULATOR_SUPPLY("vdd_mif", NULL); -static struct regulator_consumer_supply max77686_buck2 = - REGULATOR_SUPPLY("vdd_arm", NULL); - -static struct regulator_consumer_supply max77686_buck3 = - REGULATOR_SUPPLY("vdd_int", NULL); - -static struct regulator_consumer_supply max77686_buck4 = - REGULATOR_SUPPLY("vdd_g3d", NULL); - -static struct regulator_consumer_supply max77686_buck9 = - REGULATOR_SUPPLY("cam_isp_core", NULL); - -static struct regulator_consumer_supply max77686_enp32khz[] = { - REGULATOR_SUPPLY("lpo_in", "bcm47511"), - REGULATOR_SUPPLY("lpo", "bcm43241_bluetooth"), -}; - -#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask,\ - _disabled) \ -static struct regulator_init_data _ldo##_init_data = { \ - .constraints = { \ - .name = _name, \ - .min_uV = _min_uV, \ - .max_uV = _max_uV, \ - .always_on = _always_on, \ - .boot_on = _always_on, \ - .apply_uV = 1, \ - .valid_ops_mask = _ops_mask, \ - .state_mem = { \ - .disabled = _disabled, \ - .enabled = !(_disabled), \ - } \ - }, \ - .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ - .consumer_supplies = &_ldo##_supply[0], \ - }; - -REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, - 0, 0); -REGULATOR_INIT(ldo4, "VCC_2.8V_AP", 2800000, 2800000, 1, - 0, 0); -REGULATOR_INIT(ldo5, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo9, "TOUCH_VDD_1.8V", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo11, "VABB1_1.8V", 1800000, 1800000, 1, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo14, "VABB02_1.8V", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo15, "VHSIC_1.0V", 1000000, 1000000, 1, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo16, "VHSIC_1.8V", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \ - defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD) -REGULATOR_INIT(ldo17, "CAM_CORE_1.8v", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -#endif -REGULATOR_INIT(ldo18, "CAM_IO_FROM_1.8V", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo19, "VT_CAM_1.8V", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo20, "VMEM_VDD_1.8V", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0, - REGULATOR_CHANGE_STATUS, 1); -#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \ - defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD) -REGULATOR_INIT(ldo22, "VCC_MMC_2.8v", 2800000, 2800000, 0, - REGULATOR_CHANGE_STATUS, 1); -#else -REGULATOR_INIT(ldo22, "CAM_CORE_1.8v", 1800000, 1800000, 0, - REGULATOR_CHANGE_STATUS, 1); -#endif -REGULATOR_INIT(ldo23, "TSP_AVDD_2.8V", 2800000, 2800000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo24, "CAM_AF_2.8V", 2800000, 2800000, 0, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo25, "VADC_3.3V", 3300000, 3300000, 1, - REGULATOR_CHANGE_STATUS, 1); -REGULATOR_INIT(ldo26, "IRDA_3.3V", 3300000, 3300000, 0, - REGULATOR_CHANGE_STATUS, 1); - -static struct regulator_init_data max77686_buck1_data = { - .constraints = { - .name = "vdd_mif range", - .min_uV = 900000, - .max_uV = 1300000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max77686_buck1, -}; - -static struct regulator_init_data max77686_buck2_data = { - .constraints = { - .name = "vdd_arm range", - .min_uV = 800000, - .max_uV = 1500000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max77686_buck2, -}; - -static struct regulator_init_data max77686_buck3_data = { - .constraints = { - .name = "vdd_int range", - .min_uV = 900000, - .max_uV = 1300000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max77686_buck3, -}; - -static struct regulator_init_data max77686_buck4_data = { - .constraints = { - .name = "vdd_g3d range", - .min_uV = 700000, - .max_uV = 1300000, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max77686_buck4, -}; - -static struct regulator_init_data max77686_buck9_data = { - .constraints = { - .name = "cam_isp_core", - .min_uV = 1000000, - .max_uV = 1200000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max77686_buck9, -}; - -static struct regulator_init_data max77686_enp32khz_data = { - .constraints = { - .name = "32KHZ_PMIC", - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .state_mem = { - .enabled = 1, - .disabled = 0, - }, - }, - .num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz), - .consumer_supplies = max77686_enp32khz, -}; - -static struct max77686_regulator_data max77686_regulators[] = { - {MAX77686_BUCK1, &max77686_buck1_data,}, - {MAX77686_BUCK2, &max77686_buck2_data,}, - {MAX77686_BUCK3, &max77686_buck3_data,}, - {MAX77686_BUCK4, &max77686_buck4_data,}, - {MAX77686_BUCK9, &max77686_buck9_data,}, - {MAX77686_LDO3, &ldo3_init_data,}, - {MAX77686_LDO4, &ldo4_init_data,}, - {MAX77686_LDO5, &ldo5_init_data,}, - {MAX77686_LDO8, &ldo8_init_data,}, - {MAX77686_LDO9, &ldo9_init_data,}, - {MAX77686_LDO10, &ldo10_init_data,}, - {MAX77686_LDO11, &ldo11_init_data,}, - {MAX77686_LDO12, &ldo12_init_data,}, - {MAX77686_LDO14, &ldo14_init_data,}, - {MAX77686_LDO15, &ldo15_init_data,}, - {MAX77686_LDO16, &ldo16_init_data,}, -#if defined(CONFIG_MACH_P10_LUNGO_01_BD) || \ - defined(CONFIG_MACH_P10_LUNGO_WIFI_01_BD) - {MAX77686_LDO17, &ldo17_init_data,}, -#endif - {MAX77686_LDO18, &ldo18_init_data,}, - {MAX77686_LDO19, &ldo19_init_data,}, - {MAX77686_LDO20, &ldo20_init_data,}, - {MAX77686_LDO21, &ldo21_init_data,}, - {MAX77686_LDO22, &ldo22_init_data,}, - {MAX77686_LDO23, &ldo23_init_data,}, - {MAX77686_LDO24, &ldo24_init_data,}, - {MAX77686_LDO25, &ldo25_init_data,}, - {MAX77686_LDO26, &ldo26_init_data,}, - {MAX77686_P32KH, &max77686_enp32khz_data,}, -}; - -struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = { - [MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL}, - [MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY}, - [MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY}, - [MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY}, - [MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY}, - [MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY}, - [MAX77686_LDO15] = {MAX77686_LDO15, MAX77686_OPMODE_STANDBY}, - [MAX77686_LDO16] = {MAX77686_LDO16, MAX77686_OPMODE_STANDBY}, - [MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY}, - [MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY}, - [MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY}, - [MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY}, -}; - -static struct max77686_platform_data exynos4_max77686_info = { - .num_regulators = ARRAY_SIZE(max77686_regulators), - .regulators = max77686_regulators, - .irq_gpio = GPIO_PMIC_IRQ, - .irq_base = IRQ_BOARD_PMIC_START, - .wakeup = 1, - - .opmode_data = max77686_opmode_data, - .ramp_rate = MAX77686_RAMP_RATE_27MV, - .has_full_constraints = 1, - - .buck234_gpio_dvs = { - GPIO_PMIC_DVS1, - GPIO_PMIC_DVS2, - GPIO_PMIC_DVS3, - }, - .buck234_gpio_selb = { - GPIO_BUCK2_SEL, - GPIO_BUCK3_SEL, - GPIO_BUCK4_SEL, - }, - - /*for future work after DVS Table */ - .buck2_voltage[0] = 1100000, /* 1.1V */ - .buck2_voltage[1] = 1100000, /* 1.1V */ - .buck2_voltage[2] = 1100000, /* 1.1V */ - .buck2_voltage[3] = 1100000, /* 1.1V */ - .buck2_voltage[4] = 1100000, /* 1.1V */ - .buck2_voltage[5] = 1100000, /* 1.1V */ - .buck2_voltage[6] = 1100000, /* 1.1V */ - .buck2_voltage[7] = 1100000, /* 1.1V */ - - .buck3_voltage[0] = 1100000, /* 1.1V */ - .buck3_voltage[1] = 1100000, /* 1.1V */ - .buck3_voltage[2] = 1100000, /* 1.1V */ - .buck3_voltage[3] = 1100000, /* 1.1V */ - .buck3_voltage[4] = 1100000, /* 1.1V */ - .buck3_voltage[5] = 1100000, /* 1.1V */ - .buck3_voltage[6] = 1100000, /* 1.1V */ - .buck3_voltage[7] = 1100000, /* 1.1V */ - - .buck4_voltage[0] = 1100000, /* 1.1V */ - .buck4_voltage[1] = 1100000, /* 1.1V */ - .buck4_voltage[2] = 1100000, /* 1.1V */ - .buck4_voltage[3] = 1100000, /* 1.1V */ - .buck4_voltage[4] = 1100000, /* 1.1V */ - .buck4_voltage[5] = 1100000, /* 1.1V */ - .buck4_voltage[6] = 1100000, /* 1.1V */ - .buck4_voltage[7] = 1100000, /* 1.1V */ -}; -#endif /* CONFIG_REGULATOR_MAX77686 */ - -static struct i2c_board_info i2c_devs0[] __initdata = { -#ifdef CONFIG_VIDEO_EXYNOS_TV - { - I2C_BOARD_INFO("exynos_hdcp", (0x74 >> 1)), - } -#endif -}; - -#ifdef CONFIG_S3C_DEV_HWMON -static struct s3c_hwmon_pdata smdk5250_hwmon_pdata __initdata = { - /* Reference voltage (1.2V) */ - .in[0] = &(struct s3c_hwmon_chcfg) { - .name = "smdk:reference-voltage", - .mult = 3300, - .div = 4096, - }, -}; -#endif - -#if defined(CONFIG_REGULATOR_MAX77686) -static struct i2c_board_info i2c_devs5[] __initdata = { - { - I2C_BOARD_INFO("max77686", (0x12 >> 1)), - .platform_data = &exynos4_max77686_info, - } -}; -#endif - -#ifdef CONFIG_SENSORS_BH1721FVC - -static struct i2c_gpio_platform_data gpio_i2c_data12 = { - .sda_pin = GPIO_PS_ALS_SDA, - .scl_pin = GPIO_PS_ALS_SCL, -}; - -struct platform_device s3c_device_i2c12 = { - .name = "i2c-gpio", - .id = 12, - .dev.platform_data = &gpio_i2c_data12, -}; - -static int light_sensor_init(void) -{ - int err; - - printk(KERN_INFO"==============================\n"); - printk(KERN_INFO"== BH1721 Light Sensor Init ==\n"); - printk(KERN_INFO"==============================\n"); - printk("%d %d\n", GPIO_PS_ALS_SDA, GPIO_PS_ALS_SCL); - err = gpio_request(GPIO_PS_VOUT, "LIGHT_SENSOR_RESET"); - if (err) { - printk(KERN_INFO" bh1721fvc Failed to request the light " - " sensor gpio (%d)\n", err); - return err; - } - - s3c_gpio_cfgpin(GPIO_PS_VOUT, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_PS_VOUT, S3C_GPIO_PULL_NONE); - - err = gpio_direction_output(GPIO_PS_VOUT, 0); - udelay(2); - err = gpio_direction_output(GPIO_PS_VOUT, 1); - if (err) { - printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)" - " high (%d)\n", err); - return err; - } - - return 0; -} - -static int bh1721fvc_light_sensor_reset(void) -{ - int err; - - printk(KERN_INFO" bh1721fvc_light_sensor_reset\n"); - err = gpio_direction_output(GPIO_PS_VOUT, 0); - if (err) { - printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)" - " low (%d)\n", err); - return err; - } - - udelay(2); - - err = gpio_direction_output(GPIO_PS_VOUT, 1); - if (err) { - printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(reset)" - " high (%d)\n", err); - return err; - } - return 0; -} - -static int bh1721fvc_light_sensor_output(int value) -{ - int err; - int gpio_vout = GPIO_PS_VOUT; - - err = gpio_direction_output(GPIO_PS_VOUT, value); - if (err) { - printk(KERN_INFO" bh1721fvc Failed to make the light sensor gpio(dvi)" - " low (%d)\n", err); - return err; - } - return 0; -} - -static struct bh1721fvc_platform_data bh1721fvc_pdata = { - .reset = bh1721fvc_light_sensor_reset, - /* .output = bh1721fvc_light_sensor_output, */ -}; - -static struct i2c_board_info i2c_bh1721_emul[] __initdata = { - { - I2C_BOARD_INFO("bh1721fvc", 0x23), - .platform_data = &bh1721fvc_pdata, - }, -}; -#endif - -#ifdef CONFIG_SENSORS_SHT21 - -static struct i2c_gpio_platform_data gpio_i2c_data13 = { - .sda_pin = GPIO_HUM_SDA, - .scl_pin = GPIO_HUM_SCL, -}; - -struct platform_device s3c_device_i2c13 = { - .name = "i2c-gpio", - .id = 13, - .dev.platform_data = &gpio_i2c_data13, -}; - -static struct i2c_board_info i2c_devs13[] __initdata = { - { - I2C_BOARD_INFO("sht21", 0x40), - }, -}; - -#endif - -#if defined(CONFIG_SAMSUNG_MHL) -static struct i2c_board_info i2c_devs15_emul[] __initdata = { -}; - -/* i2c-gpio emulation platform_data */ -static struct i2c_gpio_platform_data i2c15_platdata = { - .sda_pin = GPIO_MHL_SDA_18V, - .scl_pin = GPIO_MHL_SCL_18V, - .udelay = 2, /* 250 kHz*/ - .sda_is_open_drain = 0, - .scl_is_open_drain = 0, - .scl_is_output_only = 0, -}; - -static struct platform_device s3c_device_i2c15 = { - .name = "i2c-gpio", - .id = 15, - .dev.platform_data = &i2c15_platdata, -}; - -#endif - -#ifdef CONFIG_MOTOR_DRV_ISA1200 - -static int isa1200_vdd_en(bool en) -{ - return gpio_direction_output(GPIO_MOTOR_EN, en); -} - -static struct i2c_gpio_platform_data gpio_i2c_data17 = { - .sda_pin = GPIO_MOTOR_SDA_18V, - .scl_pin = GPIO_MOTOR_SCL_18V, -}; - -struct platform_device s3c_device_i2c17 = { - .name = "i2c-gpio", - .id = 17, - .dev.platform_data = &gpio_i2c_data17, -}; - -static struct isa1200_vibrator_platform_data isa1200_vibrator_pdata = { - .gpio_en = isa1200_vdd_en, - .max_timeout = 10000, - .ctrl0 = CTL0_DIVIDER128 | CTL0_PWM_INPUT, - .ctrl1 = CTL1_DEFAULT, - .ctrl2 = 0, - .ctrl4 = 0, - .pll = 0, - .duty = 0, - .period = 0, - .get_clk = NULL, - .pwm_id = 1, - .pwm_duty = 37000, - .pwm_period = 38675,/*38109*/ -}; -static struct i2c_board_info i2c_devs17[] = { - { - I2C_BOARD_INFO("isa1200_vibrator", 0x48), - .platform_data = &isa1200_vibrator_pdata, - }, -}; - -static void isa1200_init(void) -{ - int gpio, ret; - - gpio = GPIO_MOTOR_EN; - gpio_request(gpio, "MOTOR_EN"); - gpio_direction_output(gpio, 1); - gpio_export(gpio, 0); -} -#endif /* CONFIG_MOTOR_DRV_ISA1200 */ - -#ifdef CONFIG_30PIN_CONN - -static void __init acc_con_gpio_init(void) -{ - s3c_gpio_cfgpin(GPIO_DOCK_INT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_DOCK_INT, S3C_GPIO_PULL_NONE); - - s3c_gpio_cfgpin(GPIO_ACCESSORY_INT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_ACCESSORY_INT, S3C_GPIO_PULL_NONE); -} - -static int acc_dock_con_state(void) -{ - /* From ACCESSROY_INT like desktop dock */ - - return gpio_get_value(GPIO_ACCESSORY_INT); -} - -static int acc_accessory_con_state(void) -{ - - /* From ACCESSORY_ID pin */ - return gpio_get_value(GPIO_DOCK_INT); -} - -struct acc_con_platform_data acc_con_pdata = { - /* - .otg_en = - .acc_power = - .usb_ldo_en = - */ - .get_dock_state = acc_dock_con_state, - .get_acc_state = acc_accessory_con_state, - .accessory_irq_gpio = GPIO_ACCESSORY_INT, - .dock_irq_gpio = GPIO_DOCK_INT, - .mhl_irq_gpio = GPIO_MHL_INT, - .hdmi_hpd_gpio = GPIO_HDMI_HPD, -}; -struct platform_device sec_device_connector = { - .name = "acc_con", - .id = -1, - .dev.platform_data = &acc_con_pdata, -}; -#endif - -#ifdef CONFIG_USB_EHCI_S5P -static struct s5p_ehci_platdata smdk5250_ehci_pdata; - -static void __init smdk5250_ehci_init(void) -{ - struct s5p_ehci_platdata *pdata = &smdk5250_ehci_pdata; - -#ifndef CONFIG_USB_EXYNOS_SWITCH - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH, - "HOST_VBUS_CONTROL")) - printk(KERN_ERR "failed to request gpio_host_vbus\n"); - else { - s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE); - gpio_free(EXYNOS5_GPX2(6)); - } - } -#endif - - s5p_ehci_set_platdata(pdata); -} -#endif - -#ifdef CONFIG_USB_OHCI_S5P -static struct s5p_ohci_platdata smdk5250_ohci_pdata; - -static void __init smdk5250_ohci_init(void) -{ - struct s5p_ohci_platdata *pdata = &smdk5250_ohci_pdata; - - s5p_ohci_set_platdata(pdata); -} -#endif - -#if defined(CONFIG_CPU_EXYNOS5250) -static void set_usb3_en(int enable) -{ - int err; - /* XMMC2CDN(USB3.0_EN) for P10 H/W */ - err = gpio_request(EXYNOS5_GPC2(2), "USB3_EN"); - if (err) - printk(KERN_ERR "usb: failed to request XMMC2CDN GPIO ####\n"); - - s3c_gpio_setpull(EXYNOS5_GPC2(2), S3C_GPIO_PULL_NONE); - gpio_direction_output(EXYNOS5_GPC2(2), enable); - gpio_free(EXYNOS5_GPC2(2)); - printk(KERN_INFO "usb: set usb3_en gpio (%d)\n", enable); -} -#endif - -/* USB GADGET */ -#ifdef CONFIG_USB_S3C_OTGD -static struct s5p_usbgadget_platdata smdk5250_usbgadget_pdata; - -static void __init smdk5250_usbgadget_init(void) -{ - struct s5p_usbgadget_platdata *pdata = &smdk5250_usbgadget_pdata; - - s5p_usbgadget_set_platdata(pdata); -} -#endif - -#ifdef CONFIG_EXYNOS_DEV_SS_UDC -static struct exynos_usb3_drd_pdata smdk5250_ss_udc_pdata; - -static void __init smdk5250_ss_udc_init(void) -{ - struct exynos_usb3_drd_pdata *pdata = &smdk5250_ss_udc_pdata; - - exynos_ss_udc_set_platdata(pdata); -} -#endif - -#ifdef CONFIG_USB_XHCI_EXYNOS -static struct exynos_usb3_drd_pdata smdk5250_xhci_pdata; - -static void __init smdk5250_xhci_init(void) -{ - struct exynos_usb3_drd_pdata *pdata = &smdk5250_xhci_pdata; - - exynos_xhci_set_platdata(pdata); -} -#endif - -#ifdef CONFIG_BATTERY_SAMSUNG -static struct platform_device samsung_device_battery = { - .name = "samsung-fake-battery", - .id = -1, -}; -#endif - -#if defined(CONFIG_STMPE811_ADC) -static struct i2c_gpio_platform_data gpio_i2c_data19 = { - .sda_pin = GPIO_ADC_SDA_18V, - .scl_pin = GPIO_ADC_SCL_18V, -}; - -struct platform_device s3c_device_i2c19 = { - .name = "i2c-gpio", - .id = 19, - .dev.platform_data = &gpio_i2c_data19, -}; - - -/* I2C19 */ -static struct i2c_board_info i2c_devs19_emul[] __initdata = { - { - I2C_BOARD_INFO("stmpe811-adc", (0x82 >> 1)), - .platform_data = &stmpe811_pdata, - }, -}; -#endif - -#ifdef CONFIG_BUSFREQ_OPP -/* BUSFREQ to control memory/bus*/ -static struct device_domain busfreq; - -static struct platform_device exynos5_busfreq = { - .id = -1, - .name = "exynos-busfreq", -}; -#endif - -/* Bluetooth */ -#ifdef CONFIG_BT_BCM43241 -static struct platform_device bcm43241_bluetooth_device = { - .name = "bcm43241_bluetooth", - .id = -1, -}; -#endif - -static struct platform_device *p10_devices[] __initdata = { - /* Samsung Power Domain */ -#ifdef CONFIG_EXYNOS_DEV_PD - &exynos5_device_pd[PD_MFC], - &exynos5_device_pd[PD_G3D], - &exynos5_device_pd[PD_ISP], - &exynos5_device_pd[PD_GSCL], - &exynos5_device_pd[PD_DISP1], -#endif - -#ifdef CONFIG_S5P_DP - &s5p_device_dp, -#endif - -#ifdef CONFIG_FB_S3C - &s5p_device_fimd1, -#endif - -#ifdef CONFIG_S5P_DP - &p10_dp_lcd, -#endif - -#ifdef CONFIG_FB_S5P_EXTDSP - &s3c_device_extdsp, -#endif - - &s3c_device_wdt, - -#ifdef CONFIG_S3C_DEV_HSMMC - &s3c_device_hsmmc0, -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC1 - &s3c_device_hsmmc1, -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC2 - &s3c_device_hsmmc2, -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC3 - &s3c_device_hsmmc3, -#endif - -#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC - &s5p_device_mfc, -#endif - -#ifdef CONFIG_VIDEO_JPEG_V2X - &s5p_device_jpeg, -#endif - -#ifdef CONFIG_EXYNOS4_DEV_DWMCI - &exynos_device_dwmci, -#endif - &exynos_device_dwmci0, - &exynos_device_dwmci1, - &exynos_device_dwmci2, -#ifdef CONFIG_ION_EXYNOS - &exynos_device_ion, -#endif - -#ifdef CONFIG_VIDEO_FIMG2D - &s5p_device_fimg2d, -#endif - -#ifdef CONFIG_EXYNOS_MEDIA_DEVICE - &exynos_device_md0, - &exynos_device_md1, - &exynos_device_md2, -#endif - -#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS - &exynos5_device_fimc_is, -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_GSCALER - &exynos5_device_gsc0, - &exynos5_device_gsc1, - &exynos5_device_gsc2, - &exynos5_device_gsc3, -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE - &exynos_device_flite0, - &exynos_device_flite1, - &exynos_device_flite2, -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS - &s5p_device_mipi_csis0, - &s5p_device_mipi_csis1, - &mipi_csi_fixed_voltage, -#endif - -#ifdef CONFIG_VIDEO_M5MOLS - &m5mols_fixed_voltage, -#endif - - &s3c_device_rtc, - -#ifdef CONFIG_HAVE_PWM - &s3c_device_timer[1], -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_TV -#ifdef CONFIG_VIDEO_EXYNOS_HDMI - &s5p_device_hdmi, -#endif -#ifdef CONFIG_VIDEO_EXYNOS_HDMIPHY - &s5p_device_i2c_hdmiphy, -#endif -#ifdef CONFIG_VIDEO_EXYNOS_MIXER - &s5p_device_mixer, -#endif -#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC - &s5p_device_cec, -#endif -#endif - &s3c_device_i2c0, -#ifdef CONFIG_MPU_SENSORS_MPU6050 - &s3c_device_i2c1, -#endif - &s3c_device_i2c3, - &s3c_device_i2c4, - &s3c_device_i2c5, - &s3c_device_i2c7, - -#ifdef CONFIG_USB_EHCI_S5P - &s5p_device_ehci, -#endif - -#ifdef CONFIG_USB_OHCI_S5P - &s5p_device_ohci, -#endif - -#ifdef CONFIG_USB_S3C_OTGD - &s3c_device_usbgadget, -#endif - -#ifdef CONFIG_EXYNOS_DEV_SS_UDC - &exynos_device_ss_udc, -#endif - -#ifdef CONFIG_USB_XHCI_EXYNOS - &exynos_device_xhci, -#endif - -#ifdef CONFIG_BATTERY_SAMSUNG - &samsung_device_battery, -#endif -#ifdef CONFIG_MOTOR_DRV_ISA1200 - &s3c_device_i2c17, -#endif -#if defined(CONFIG_STMPE811_ADC) - &s3c_device_i2c19, -#endif -#ifdef CONFIG_SND_SAMSUNG_I2S - &exynos_device_i2s0, -#endif - - &samsung_asoc_dma, - &samsung_asoc_idma, - -#ifdef CONFIG_SND_SAMSUNG_PCM - &exynos_device_pcm0, -#endif - -#if defined(CONFIG_SND_SAMSUNG_RP) || defined(CONFIG_SND_SAMSUNG_ALP) - &exynos_device_srp, -#endif - -#ifdef CONFIG_EXYNOS4_SETUP_THERMAL - &s5p_device_tmu, -#endif - -#ifdef CONFIG_S5P_DEV_ACE - &s5p_device_ace, -#endif - -#ifdef CONFIG_EXYNOS_C2C - &exynos_device_c2c, -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI - &exynos_device_spi1, -#endif - -#ifdef CONFIG_BUSFREQ_OPP - &exynos5_busfreq, -#endif - -#ifdef CONFIG_MPU_SENSORS_MPU6050 - &s3c_device_i2c11, -#endif -#ifdef CONFIG_SENSORS_BH1721FVC - &s3c_device_i2c12, -#endif - -#ifdef CONFIG_SENSORS_SHT21 - &s3c_device_i2c13, -#endif - -#if defined(CONFIG_SAMSUNG_MHL) - &s3c_device_i2c15, /* MHL */ -#endif - -#ifdef CONFIG_30PIN_CONN - &sec_device_connector, -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR - &exynos_device_rotator, -#endif -#ifdef CONFIG_BT_BCM43241 - &bcm43241_bluetooth_device, -#endif -}; - -#ifdef CONFIG_EXYNOS4_SETUP_THERMAL -/* below temperature base on the celcius degree */ -struct s5p_platform_tmu exynos_tmu_data __initdata = { - .ts = { - .stop_1st_throttle = 78, - .start_1st_throttle = 80, - .stop_2nd_throttle = 87, - .start_2nd_throttle = 103, - .start_tripping = 110, /* temp to do tripping */ - .start_emergency = 120, /* To protect chip,forcely kernel panic */ - .stop_mem_throttle = 80, - .start_mem_throttle = 85, - }, - .cpufreq = { - .limit_1st_throttle = 800000, /* 800MHz in KHz order */ - .limit_2nd_throttle = 200000, /* 200MHz in KHz order */ - }, -}; - -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC -static struct s5p_platform_cec hdmi_cec_data __initdata = { - -}; -#endif - -#if defined(CONFIG_CMA) -static void __init exynos_reserve_mem(void) -{ - static struct cma_region regions[] = { - { - .name = "ion", - .size = 256 * SZ_1M, - .start = 0 - }, -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0 - { - .name = "gsc0", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC0 * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1 - { - .name = "gsc1", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC1 * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2 - { - .name = "gsc2", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC2 * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3 - { - .name = "gsc3", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_GSC3 * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE0 - { - .name = "flite0", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE0 * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE1 - { - .name = "flite1", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FLITE1 * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD - { - .name = "fimd", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP - { - .name = "srp", - .size = CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP * SZ_1K, - .start = 0, - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC - { - .name = "fw", - .size = 2 << 20, - { .alignment = 128 << 10 }, - .start = 0x44000000, - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV - { - .name = "tv", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV * SZ_1K, - .start = 0 - }, -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT - { - .name = "rot", - .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_ROT * SZ_1K, - .start = 0, - }, -#endif -#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS - { - .name = "fimc_is", - .size = CONFIG_VIDEO_EXYNOS_MEMSIZE_FIMC_IS * SZ_1K, - { - .alignment = 1 << 26, - }, - .start = 0 - }, -#endif - { - .size = 0 - }, - }; - static const char map[] __initconst = -#ifdef CONFIG_EXYNOS_C2C - "samsung-c2c=c2c_shdmem;" -#endif - "s3cfb.0=fimd;" -#ifdef CONFIG_AUDIO_SAMSUNG_MEMSIZE_SRP - "samsung-rp=srp;" -#endif - "exynos-gsc.0=gsc0;exynos-gsc.1=gsc1;exynos-gsc.2=gsc2;exynos-gsc.3=gsc3;" - "exynos-fimc-lite.0=flite0;exynos-fimc-lite.1=flite1;" - "ion-exynos=ion,gsc0,gsc1,gsc2,gsc3,flite0,flite1,fimd,fw,rot;" - "exynos-rot=rot;" - "s5p-mfc-v6/f=fw;" - "s5p-mixer=tv;" - "exynos5-fimc-is=fimc_is;"; - - s5p_cma_region_reserve(regions, NULL, 0, map); -} -#else /* !CONFIG_CMA */ -static inline void exynos_reserve_mem(void) -{ -} -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE -static void __init smdk5250_camera_gpio_cfg(void) -{ - /* CAM A port(b0010) : PCLK, VSYNC, HREF, CLK_OUT */ - s3c_gpio_cfgrange_nopull(EXYNOS5_GPH0(0), 4, S3C_GPIO_SFN(2)); - /* CAM A port(b0010) : DATA[0-7] */ - s3c_gpio_cfgrange_nopull(EXYNOS5_GPH1(0), 8, S3C_GPIO_SFN(2)); - /* CAM B port(b0010) : PCLK, BAY_RGB[0-6] */ - s3c_gpio_cfgrange_nopull(EXYNOS5_GPG0(0), 8, S3C_GPIO_SFN(2)); - /* CAM B port(b0010) : BAY_Vsync, BAY_RGB[7-13] */ - s3c_gpio_cfgrange_nopull(EXYNOS5_GPG1(0), 8, S3C_GPIO_SFN(2)); - /* CAM B port(b0010) : BAY_Hsync, BAY_MCLK */ - s3c_gpio_cfgrange_nopull(EXYNOS5_GPG2(0), 2, S3C_GPIO_SFN(2)); - /* This is externel interrupt for m5mo */ -#ifdef CONFIG_VIDEO_M5MOLS - s3c_gpio_cfgpin(EXYNOS5_GPX2(6), S3C_GPIO_SFN(0xF)); - s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE); -#endif -} -#endif - -#if defined(CONFIG_VIDEO_EXYNOS_GSCALER) && defined(CONFIG_VIDEO_EXYNOS_FIMC_LITE) -#if defined(CONFIG_VIDEO_S5K4BA) -static struct exynos_isp_info s5k4ba = { - .board_info = &s5k4ba_info, - .cam_srclk_name = "xxti", - .clk_frequency = 24000000UL, - .bus_type = CAM_TYPE_ITU, -#ifdef CONFIG_ITU_A - .cam_clk_name = "sclk_cam0", - .i2c_bus_num = 4, - .cam_port = CAM_PORT_A, /* A-Port : 0, B-Port : 1 */ -#endif -#ifdef CONFIG_ITU_B - .cam_clk_name = "sclk_cam1", - .i2c_bus_num = 5, - .cam_port = CAM_PORT_B, /* A-Port : 0, B-Port : 1 */ -#endif - .flags = CAM_CLK_INV_VSYNC, -}; -/* This is for platdata of fimc-lite */ -static struct s3c_platform_camera flite_s5k4ba = { - .type = CAM_TYPE_MIPI, - .use_isp = true, - .inv_pclk = 1, - .inv_vsync = 1, - .inv_href = 0, - .inv_hsync = 0, -}; -#endif -#if defined(CONFIG_VIDEO_M5MOLS) -static struct exynos_isp_info m5mols = { - .board_info = &m5mols_board_info, - .cam_srclk_name = "xxti", - .clk_frequency = 24000000UL, - .bus_type = CAM_TYPE_MIPI, -#ifdef CONFIG_CSI_C - .cam_clk_name = "sclk_cam0", - .i2c_bus_num = 4, - .cam_port = CAM_PORT_A, /* A-Port : 0, B-Port : 1 */ -#endif -#ifdef CONFIG_CSI_D - .cam_clk_name = "sclk_cam1", - .i2c_bus_num = 5, - .cam_port = CAM_PORT_B, /* A-Port : 0, B-Port : 1 */ -#endif - .flags = CAM_CLK_INV_PCLK | CAM_CLK_INV_VSYNC, - .csi_data_align = 32, -}; -/* This is for platdata of fimc-lite */ -static struct s3c_platform_camera flite_m5mo = { - .type = CAM_TYPE_MIPI, - .use_isp = true, - .inv_pclk = 1, - .inv_vsync = 1, - .inv_href = 0, - .inv_hsync = 0, -}; -#endif - -static void __set_gsc_camera_config(struct exynos_platform_gscaler *data, - u32 active_index, u32 preview, - u32 camcording, u32 max_cam) -{ - data->active_cam_index = active_index; - data->cam_preview = preview; - data->cam_camcording = camcording; - data->num_clients = max_cam; -} - -static void __set_flite_camera_config(struct exynos_platform_flite *data, - u32 active_index, u32 max_cam) -{ - data->active_cam_index = active_index; - data->num_clients = max_cam; -} - -static void __init smdk5250_set_camera_platdata(void) -{ - int gsc_cam_index = 0; - int flite0_cam_index = 0; - int flite1_cam_index = 0; -#if defined(CONFIG_VIDEO_M5MOLS) - exynos_gsc0_default_data.isp_info[gsc_cam_index++] = &m5mols; -#if defined(CONFIG_CSI_C) - exynos_flite0_default_data.cam[flite0_cam_index] = &flite_m5mo; - exynos_flite0_default_data.isp_info[flite0_cam_index] = &m5mols; - flite0_cam_index++; -#endif -#if defined(CONFIG_CSI_D) - exynos_flite1_default_data.cam[flite1_cam_index] = &flite_m5mo; - exynos_flite1_default_data.isp_info[flite1_cam_index] = &m5mols; - flite1_cam_index++; -#endif -#endif - /* flite platdata register */ - __set_flite_camera_config(&exynos_flite0_default_data, 0, flite0_cam_index); - __set_flite_camera_config(&exynos_flite1_default_data, 0, flite1_cam_index); - - /* gscaler platdata register */ - /* GSC-0 */ - __set_gsc_camera_config(&exynos_gsc0_default_data, 0, 1, 0, gsc_cam_index); - - /* GSC-1 */ - /* GSC-2 */ - /* GSC-3 */ -} -#endif /* CONFIG_VIDEO_EXYNOS_GSCALER */ - -static void __init p10_map_io(void) -{ - s5p_init_io(NULL, 0, S5P_VA_CHIPID); - s3c24xx_init_clocks(24000000); - s3c24xx_init_uarts(smdk5250_uartcfgs, ARRAY_SIZE(smdk5250_uartcfgs)); - exynos_reserve_mem(); - -#if defined(CONFIG_SEC_DEBUG) - /* as soon as INFORM6 is visible, sec_debug is ready to run */ - sec_debug_init(); -#endif -} - -#ifdef CONFIG_EXYNOS_DEV_SYSMMU -static void __init exynos_sysmmu_init(void) -{ -#ifdef CONFIG_VIDEO_JPEG_V2X - platform_set_sysmmu(&SYSMMU_PLATDEV(jpeg).dev, &s5p_device_jpeg.dev); -#endif -#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MFC - platform_set_sysmmu(&SYSMMU_PLATDEV(mfc_lr).dev, &s5p_device_mfc.dev); -#endif -#ifdef CONFIG_VIDEO_EXYNOS_TV - platform_set_sysmmu(&SYSMMU_PLATDEV(tv).dev, &s5p_device_mixer.dev); -#endif -#ifdef CONFIG_VIDEO_EXYNOS_GSCALER - platform_set_sysmmu(&SYSMMU_PLATDEV(gsc0).dev, - &exynos5_device_gsc0.dev); - platform_set_sysmmu(&SYSMMU_PLATDEV(gsc1).dev, - &exynos5_device_gsc1.dev); - platform_set_sysmmu(&SYSMMU_PLATDEV(gsc2).dev, - &exynos5_device_gsc2.dev); - platform_set_sysmmu(&SYSMMU_PLATDEV(gsc3).dev, - &exynos5_device_gsc3.dev); -#endif -#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE - platform_set_sysmmu(&SYSMMU_PLATDEV(camif0).dev, - &exynos_device_flite0.dev); - platform_set_sysmmu(&SYSMMU_PLATDEV(camif1).dev, - &exynos_device_flite1.dev); -#endif -#ifdef CONFIG_VIDEO_EXYNOS_ROTATOR - platform_set_sysmmu(&SYSMMU_PLATDEV(rot).dev, - &exynos_device_rotator.dev); -#endif -#ifdef CONFIG_VIDEO_FIMG2D - platform_set_sysmmu(&SYSMMU_PLATDEV(2d).dev, &s5p_device_fimg2d.dev); -#endif -#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS - platform_set_sysmmu(&SYSMMU_PLATDEV(isp).dev, - &exynos5_device_fimc_is.dev); -#endif -} -#else /* !CONFIG_EXYNOS_DEV_SYSMMU */ -static inline void exynos_sysmmu_init(void) -{ -} -#endif - -static void p10_power_off(void) -{ - printk(KERN_EMERG "%s: set PS_HOLD low\n", __func__); - - writel(readl(EXYNOS5_PS_HOLD_CONTROL) & 0xFFFFFEFF, EXYNOS5_PS_HOLD_CONTROL); - printk(KERN_EMERG "%s: Should not reach here\n", __func__); -} - -#ifdef CONFIG_FB_S5P_EXTDSP -struct platform_device s3c_device_extdsp = { - .name = "s3cfb_extdsp", - .id = 0, -}; - -static struct s3cfb_extdsp_lcd dummy_buffer = { - .width = 1920, - .height = 1080, - .bpp = 16, -}; - -static struct s3c_platform_fb default_extdsp_data __initdata = { - .hw_ver = 0x70, - .nr_wins = 1, - .default_win = 0, - .swap = FB_SWAP_WORD | FB_SWAP_HWORD, - .lcd = &dummy_buffer -}; - -void __init s3cfb_extdsp_set_platdata(struct s3c_platform_fb *pd) -{ - struct s3c_platform_fb *npd; - int i; - - if (!pd) - pd = &default_extdsp_data; - - npd = kmemdup(pd, sizeof(struct s3c_platform_fb), GFP_KERNEL); - if (!npd) - printk(KERN_ERR "%s: no memory for platform data\n", __func__); - else { - for (i = 0; i < npd->nr_wins; i++) - npd->nr_buffers[i] = 1; - s3c_device_extdsp.dev.platform_data = npd; - } -} -#endif - -static void camera_init(void) -{ - camera_class = class_create(THIS_MODULE, "camera"); - - if (IS_ERR(camera_class)) - pr_err("Failed to create class(camera)!\n"); -} - -static void __init p10_machine_init(void) -{ -#ifdef CONFIG_S3C64XX_DEV_SPI - struct clk *sclk = NULL; - struct clk *prnt = NULL; - struct device *spi1_dev = &exynos_device_spi1.dev; -#endif - pm_power_off = p10_power_off; - - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - exynos_dwmci_set_platdata(&exynos5_dwmci0_pdata, 0); - dev_set_name(&exynos_device_dwmci0.dev, "s3c-sdhci.0"); - clk_add_alias("dwmci", "dw_mmc.0", "hsmmc", - &exynos_device_dwmci0.dev); - clk_add_alias("sclk_dwmci", "dw_mmc.0", "sclk_mmc", - &exynos_device_dwmci0.dev); - - exynos_dwmci_set_platdata(&exynos5_dwmci1_pdata, 1); - dev_set_name(&exynos_device_dwmci1.dev, "s3c-sdhci.1"); - clk_add_alias("dwmci", "dw_mmc.1", "hsmmc", - &exynos_device_dwmci1.dev); - clk_add_alias("sclk_dwmci", "dw_mmc.1", "sclk_mmc", - &exynos_device_dwmci1.dev); - - exynos_dwmci_set_platdata(&exynos5_dwmci2_pdata, 2); - dev_set_name(&exynos_device_dwmci2.dev, "s3c-sdhci.2"); - clk_add_alias("dwmci", "dw_mmc.2", "hsmmc", - &exynos_device_dwmci2.dev); - clk_add_alias("sclk_dwmci", "dw_mmc.2", "sclk_mmc", - &exynos_device_dwmci2.dev); - } else { -#ifdef CONFIG_EXYNOS4_DEV_DWMCI - exynos_dwmci_set_platdata(&exynos_dwmci_pdata, 0); -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC - s3c_sdhci0_set_platdata(&smdk5250_hsmmc0_pdata); -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC1 - s3c_sdhci1_set_platdata(&smdk5250_hsmmc1_pdata); -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC2 - s3c_sdhci2_set_platdata(&smdk5250_hsmmc2_pdata); -#endif - -#ifdef CONFIG_S3C_DEV_HSMMC3 - s3c_sdhci3_set_platdata(&smdk5250_hsmmc3_pdata); -#endif - } -#ifdef CONFIG_ION_EXYNOS - exynos_ion_set_platdata(); -#endif - -#ifdef CONFIG_LEDS_SPFCW043 - platform_device_register(&s3c_device_spfcw043_led); -#endif - -#ifdef CONFIG_FB_S3C - dev_set_name(&s5p_device_fimd1.dev, "s3cfb.1"); - clk_add_alias("lcd", "exynos5-fb.1", "lcd", &s5p_device_fimd1.dev); - clk_add_alias("sclk_fimd", "exynos5-fb.1", "sclk_fimd", - &s5p_device_fimd1.dev); - s5p_fb_setname(1, "exynos5-fb"); - - s5p_fimd1_set_platdata(&p10_lcd1_pdata); -#endif - -#ifdef CONFIG_FB_S5P_EXTDSP - s3cfb_extdsp_set_platdata(&default_extdsp_data); -#endif - -#ifdef CONFIG_BACKLIGHT_PWM - samsung_bl_set(&p10_bl_gpio_info, &p10_bl_data); -#endif - -#ifdef CONFIG_USB_EHCI_S5P - smdk5250_ehci_init(); -#endif - -#ifdef CONFIG_USB_OHCI_S5P - smdk5250_ohci_init(); -#endif - -#if defined(CONFIG_CPU_EXYNOS5250) - set_usb3_en(1); -#endif - -#ifdef CONFIG_USB_S3C_OTGD - smdk5250_usbgadget_init(); -#endif - -#ifdef CONFIG_EXYNOS_DEV_SS_UDC - smdk5250_ss_udc_init(); -#endif - -#ifdef CONFIG_USB_XHCI_EXYNOS - smdk5250_xhci_init(); -#endif - -#if defined(CONFIG_VIDEO_SAMSUNG_S5P_MFC) -#if defined(CONFIG_EXYNOS_DEV_PD) - s5p_device_mfc.dev.parent = &exynos5_device_pd[PD_MFC].dev; -#endif - s5p_mfc_set_platdata(&smdk5250_mfc_pd); - - dev_set_name(&s5p_device_mfc.dev, "s3c-mfc"); - clk_add_alias("mfc", "s5p-mfc-v6", "mfc", &s5p_device_mfc.dev); - s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc-v6"); -#endif - -#ifdef CONFIG_FB_S3C - s5p_device_fimd1.dev.parent = &exynos5_device_pd[PD_DISP1].dev; -#endif - -#ifdef CONFIG_S5P_DP - s5p_dp_set_platdata(&p10_dp_data); -#endif - -#ifdef CONFIG_S3C_ADC - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - platform_device_register(&s3c_device_adc); -#ifdef CONFIG_S3C_DEV_HWMON - platform_device_register(&s3c_device_hwmon); -#endif - } -#endif - -#ifdef CONFIG_S3C_DEV_HWMON - if (samsung_rev() >= EXYNOS5250_REV_1_0) - s3c_hwmon_set_platdata(&smdk5250_hwmon_pdata); -#endif - -#ifdef CONFIG_VIDEO_FIMG2D - s5p_fimg2d_set_platdata(&fimg2d_data); -#endif - - exynos_sysmmu_init(); - - p10_config_gpio_table(); - - exynos5_sleep_gpio_table_set = p10_config_sleep_gpio_table; - - s3c_i2c0_set_platdata(NULL); - i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); - -#ifdef CONFIG_MPU_SENSORS_MPU6050 - pr_info("MPU6050 I2C-1 Init\n"); - //magnetic_init(); - s3c_i2c1_set_platdata(NULL); - i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); -#endif - - p10_tsp_init(); - p10_key_init(); - - s3c_i2c5_set_platdata(NULL); - i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5)); - - midas_sound_init(); - -#ifdef CONFIG_MPU_SENSORS_MPU6050 - magnetic_init(); - i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11)); -#endif - -#ifdef CONFIG_SENSORS_BH1721FVC - light_sensor_init(); - i2c_register_board_info(12, i2c_bh1721_emul, ARRAY_SIZE(i2c_bh1721_emul)); -#endif - -#ifdef CONFIG_SENSORS_SHT21 - i2c_register_board_info(13, i2c_devs13, ARRAY_SIZE(i2c_devs13)); -#endif - -#if defined(CONFIG_SAMSUNG_MHL) - i2c_register_board_info(15, i2c_devs15_emul, - ARRAY_SIZE(i2c_devs15_emul)); -#endif - -#ifdef CONFIG_MOTOR_DRV_ISA1200 - isa1200_init(); - i2c_register_board_info(17, i2c_devs17, - ARRAY_SIZE(i2c_devs17)); -#endif - -#if defined(CONFIG_STMPE811_ADC) - i2c_register_board_info(19, i2c_devs19_emul, - ARRAY_SIZE(i2c_devs19_emul)); -#endif -#if defined(CONFIG_BATTERY_SAMSUNG_P1X) - p10_battery_init(); -#endif - - platform_device_register(&vbatt_device); - - platform_add_devices(p10_devices, ARRAY_SIZE(p10_devices)); - -#ifdef CONFIG_FB_S3C -#if defined(CONFIG_MACH_P10_DP_01) -#if defined(CONFIG_DP_40HZ_P10) - exynos4_fimd_setup_clock(&s5p_device_fimd1.dev, "sclk_fimd", "sclk_vpll", - 180 * MHZ); -#elif defined(CONFIG_DP_60HZ_P10) - exynos4_fimd_setup_clock(&s5p_device_fimd1.dev, "sclk_fimd", "sclk_vpll", - 270 * MHZ); -#endif -#endif -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS -#if defined(CONFIG_EXYNOS_DEV_PD) - s5p_device_mipi_csis0.dev.parent = &exynos5_device_pd[PD_GSCL].dev; - s5p_device_mipi_csis1.dev.parent = &exynos5_device_pd[PD_GSCL].dev; -#endif - s3c_set_platdata(&s5p_mipi_csis0_default_data, - sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0); - s3c_set_platdata(&s5p_mipi_csis1_default_data, - sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1); -#endif - -#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE -#if defined(CONFIG_EXYNOS_DEV_PD) - exynos_device_flite0.dev.parent = &exynos5_device_pd[PD_GSCL].dev; - exynos_device_flite1.dev.parent = &exynos5_device_pd[PD_GSCL].dev; - exynos_device_flite2.dev.parent = &exynos5_device_pd[PD_GSCL].dev; -#endif - smdk5250_camera_gpio_cfg(); - smdk5250_set_camera_platdata(); - s3c_set_platdata(&exynos_flite0_default_data, - sizeof(exynos_flite0_default_data), &exynos_device_flite0); - s3c_set_platdata(&exynos_flite1_default_data, - sizeof(exynos_flite1_default_data), &exynos_device_flite1); - s3c_set_platdata(&exynos_flite2_default_data, - sizeof(exynos_flite2_default_data), &exynos_device_flite2); - -/* In EVT0, for using camclk, gscaler clock should be enabled */ - if (samsung_rev() < EXYNOS5250_REV_1_0) { - dev_set_name(&exynos_device_flite0.dev, "exynos-gsc.0"); - clk_add_alias("gscl", "exynos-fimc-lite.0", "gscl", - &exynos_device_flite0.dev); - dev_set_name(&exynos_device_flite0.dev, "exynos-fimc-lite.0"); - - dev_set_name(&exynos_device_flite1.dev, "exynos-gsc.0"); - clk_add_alias("gscl", "exynos-fimc-lite.1", "gscl", - &exynos_device_flite1.dev); - dev_set_name(&exynos_device_flite1.dev, "exynos-fimc-lite.1"); - } -#endif - -#if defined CONFIG_VIDEO_EXYNOS5_FIMC_IS - dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0"); - clk_add_alias("gscl_wrap0", "exynos5-fimc-is", "gscl_wrap0", &exynos5_device_fimc_is.dev); - clk_add_alias("sclk_gscl_wrap0", "exynos5-fimc-is", "sclk_gscl_wrap0", &exynos5_device_fimc_is.dev); - dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1"); - clk_add_alias("gscl_wrap1", "exynos5-fimc-is", "gscl_wrap1", &exynos5_device_fimc_is.dev); - clk_add_alias("sclk_gscl_wrap1", "exynos5-fimc-is", "sclk_gscl_wrap1", &exynos5_device_fimc_is.dev); - dev_set_name(&exynos5_device_fimc_is.dev, "exynos-gsc.0"); - clk_add_alias("gscl", "exynos5-fimc-is", "gscl", &exynos5_device_fimc_is.dev); - dev_set_name(&exynos5_device_fimc_is.dev, "exynos5-fimc-is"); - -#if defined CONFIG_VIDEO_S5K6A3 - exynos5_fimc_is_data.sensor_info[s5k6a3.sensor_position] = &s5k6a3; - printk("add s5k6a3 sensor info(pos : %d)\n", s5k6a3.sensor_position); -#endif -#if defined CONFIG_VIDEO_S5K4E5 - exynos5_fimc_is_data.sensor_info[s5k4e5.sensor_position] = &s5k4e5; - printk("add s5k4e5 sensor info(pos : %d)\n", s5k4e5.sensor_position); -#endif - - exynos5_fimc_is_set_platdata(&exynos5_fimc_is_data); -#if defined(CONFIG_EXYNOS_DEV_PD) - exynos5_device_pd[PD_ISP].dev.parent = &exynos5_device_pd[PD_GSCL].dev; - exynos5_device_fimc_is.dev.parent = &exynos5_device_pd[PD_ISP].dev; -#endif -#endif -#ifdef CONFIG_EXYNOS4_SETUP_THERMAL - s5p_tmu_set_platdata(&exynos_tmu_data); -#endif -#ifdef CONFIG_VIDEO_EXYNOS_GSCALER -#if defined(CONFIG_EXYNOS_DEV_PD) - exynos5_device_gsc0.dev.parent = &exynos5_device_pd[PD_GSCL].dev; - exynos5_device_gsc1.dev.parent = &exynos5_device_pd[PD_GSCL].dev; - exynos5_device_gsc2.dev.parent = &exynos5_device_pd[PD_GSCL].dev; - exynos5_device_gsc3.dev.parent = &exynos5_device_pd[PD_GSCL].dev; -#endif - - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - exynos5_gsc_set_pdev_name(0, "exynos5250-gsc"); - exynos5_gsc_set_pdev_name(1, "exynos5250-gsc"); - exynos5_gsc_set_pdev_name(2, "exynos5250-gsc"); - exynos5_gsc_set_pdev_name(3, "exynos5250-gsc"); - } - - s3c_set_platdata(&exynos_gsc0_default_data, sizeof(exynos_gsc0_default_data), - &exynos5_device_gsc0); - s3c_set_platdata(&exynos_gsc1_default_data, sizeof(exynos_gsc1_default_data), - &exynos5_device_gsc1); - s3c_set_platdata(&exynos_gsc2_default_data, sizeof(exynos_gsc2_default_data), - &exynos5_device_gsc2); - s3c_set_platdata(&exynos_gsc3_default_data, sizeof(exynos_gsc3_default_data), - &exynos5_device_gsc3); - /* Gscaler can use MPLL(266MHz) or VPLL(300MHz). - In case of P10, Gscaler should use MPLL(266MHz) because FIMD uses VPLL(86MHz). - So mout_aclk_300_gscl_mid selects mout_mpll_user and then - mout_aclk_300_gscl_mid is set to 267MHz - even though the clock name(dout_aclk_300_gscl) implies and requires around 300MHz - */ - exynos5_gsc_set_parent_clock("mout_aclk_300_gscl_mid", "mout_mpll_user"); - exynos5_gsc_set_parent_clock("mout_aclk_300_gscl", "mout_aclk_300_gscl_mid"); - exynos5_gsc_set_parent_clock("aclk_300_gscl", "dout_aclk_300_gscl"); - exynos5_gsc_set_clock_rate("dout_aclk_300_gscl", 267000000); -#endif - -#ifdef CONFIG_EXYNOS_C2C - exynos_c2c_set_platdata(&smdk5250_c2c_pdata); -#endif - -#ifdef CONFIG_VIDEO_JPEG_V2X - exynos5_jpeg_setup_clock(&s5p_device_jpeg.dev, 150000000); -#endif - -#if defined(CONFIG_VIDEO_EXYNOS_TV) && defined(CONFIG_VIDEO_EXYNOS_HDMI) - dev_set_name(&s5p_device_hdmi.dev, "exynos5-hdmi"); - clk_add_alias("hdmi", "s5p-hdmi", "hdmi", &s5p_device_hdmi.dev); - clk_add_alias("hdmiphy", "s5p-hdmi", "hdmiphy", &s5p_device_hdmi.dev); - - s5p_tv_setup(); - -/* setup dependencies between TV devices */ - /* This will be added after power domain for exynos5 is developed */ - s5p_device_hdmi.dev.parent = &exynos5_device_pd[PD_DISP1].dev; - s5p_device_mixer.dev.parent = &exynos5_device_pd[PD_DISP1].dev; - - s5p_i2c_hdmiphy_set_platdata(NULL); -#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC - s5p_hdmi_cec_set_platdata(&hdmi_cec_data); -#endif -#endif - -#ifdef CONFIG_S3C64XX_DEV_SPI - sclk = clk_get(spi1_dev, "sclk_spi1"); - if (IS_ERR(sclk)) - dev_err(spi1_dev, "failed to get sclk for SPI-1\n"); - prnt = clk_get(spi1_dev, "mout_mpll_user"); - if (IS_ERR(prnt)) - dev_err(spi1_dev, "failed to get prnt\n"); - if (clk_set_parent(sclk, prnt)) - printk(KERN_ERR "Unable to set parent %s of clock %s.\n", - prnt->name, sclk->name); - - clk_set_rate(sclk, 800 * 1000 * 1000); - clk_put(sclk); - clk_put(prnt); - - if (!gpio_request(GPIO_5M_SPI_CS, "SPI_CS1")) { - gpio_direction_output(GPIO_5M_SPI_CS, 1); - s3c_gpio_cfgpin(GPIO_5M_SPI_CS, S3C_GPIO_SFN(1)); - s3c_gpio_setpull(GPIO_5M_SPI_CS, S3C_GPIO_PULL_UP); - exynos_spi_set_info(1, EXYNOS_SPI_SRCCLK_SCLK, - ARRAY_SIZE(spi1_csi)); - } - - spi_register_board_info(spi1_board_info, ARRAY_SIZE(spi1_board_info)); -#endif - -#ifdef CONFIG_BUSFREQ_OPP - dev_add(&busfreq, &exynos5_busfreq.dev); - ppmu_init(&exynos_ppmu[PPMU_CPU], &exynos5_busfreq.dev); - ppmu_init(&exynos_ppmu[PPMU_DDR_C], &exynos5_busfreq.dev); - ppmu_init(&exynos_ppmu[PPMU_DDR_R1], &exynos5_busfreq.dev); - ppmu_init(&exynos_ppmu[PPMU_DDR_L], &exynos5_busfreq.dev); - ppmu_init(&exynos_ppmu[PPMU_RIGHT0_BUS], &exynos5_busfreq.dev); -#endif -#ifdef CONFIG_30PIN_CONN - acc_con_gpio_init(); -#endif - - /* for BRCM Wi-Fi */ - brcm_wlan_init(); - - /* for camera*/ - camera_init(); - - register_reboot_notifier(&exynos5_reboot_notifier); -} - -#ifdef CONFIG_EXYNOS_C2C -static void __init exynos_c2c_reserve(void) -{ - static struct cma_region regions[] = { - { - .name = "c2c_shdmem", - .size = 64 * SZ_1M, - { .alignment = 64 * SZ_1M }, - .start = C2C_SHAREDMEM_BASE - }, { - .size = 0, - } - }; - - s5p_cma_region_reserve(regions, NULL, 0, map); -} -#endif - -#if defined(CONFIG_SEC_DEBUG) -static void __init exynos_init_reserve(void) -{ - sec_debug_magic_init(); -} -#endif - -MACHINE_START(SMDK5250, "SMDK5250") - .boot_params = S5P_PA_SDRAM + 0x100, - .init_irq = exynos5_init_irq, - .map_io = p10_map_io, - .init_machine = p10_machine_init, - .timer = &exynos4_timer, -#ifdef CONFIG_EXYNOS_C2C - .reserve = &exynos_c2c_reserve, -#endif -#if defined(CONFIG_SEC_DEBUG) - .init_early = &exynos_init_reserve, -#endif -MACHINE_END diff --git a/arch/arm/mach-exynos/mach-p4notepq.c b/arch/arm/mach-exynos/mach-p4notepq.c index fc349c1..8466afc 100644 --- a/arch/arm/mach-exynos/mach-p4notepq.c +++ b/arch/arm/mach-exynos/mach-p4notepq.c @@ -159,6 +159,10 @@ struct s3cfb_extdsp_lcd { #include "board-mobile.h" +#ifdef CONFIG_IR_REMOCON_MC96 +#include <linux/ir_remote_con_mc96.h> +#endif + extern int s6c1372_panel_gpio_init(void); /* cable state */ @@ -860,10 +864,13 @@ struct platform_device s3c_device_i2c14 = { static struct max17042_platform_data max17042_pdata = { .sdi_capacity = 0x3730, .sdi_vfcapacity = 0x4996, + .sdi_low_bat_comp_start_vol = 3600, .atl_capacity = 0x3022, .atl_vfcapacity = 0x4024, - .sdi_low_bat_comp_start_vol = 3600, .atl_low_bat_comp_start_vol = 3450, + .byd_capacity = 0x36B0, + .byd_vfcapacity = 0x48EA, + .byd_low_bat_comp_start_vol = 3600, .fuel_alert_line = GPIO_FUEL_ALERT, .check_jig_status = check_jig_on }; @@ -990,6 +997,83 @@ static struct i2c_board_info i2c_devs21_emul[] __initdata = { #endif }; + +/* I2C22 */ +#ifdef CONFIG_IR_REMOCON_MC96 +static void irda_wake_en(bool onoff) +{ + gpio_direction_output(GPIO_IRDA_WAKE, onoff); + printk(KERN_ERR "%s: irda_wake_en : %d\n", __func__, onoff); +} + +static void irda_device_init(void) +{ + int ret; + + printk(KERN_ERR "%s called!\n", __func__); + + ret = gpio_request(GPIO_IRDA_WAKE, "irda_wake"); + if (ret) { + printk(KERN_ERR "%s: gpio_request fail[%d], ret = %d\n", + __func__, GPIO_IRDA_WAKE, ret); + return; + } + gpio_direction_output(GPIO_IRDA_WAKE, 0); + + return; +} + +static int vled_ic_onoff; + +static void irda_vdd_onoff(bool onoff) +{ + int ret = 0; + static struct regulator *vled_ic; + + if (onoff) { + vled_ic = regulator_get(NULL, "vled_ic_1.9v"); + if (IS_ERR(vled_ic)) { + pr_err("could not get regulator vled_ic_1.9v\n"); + return; + } + regulator_enable(vled_ic); + vled_ic_onoff = 1; + } else if (vled_ic_onoff == 1) { + regulator_force_disable(vled_ic); + regulator_put(vled_ic); + vled_ic_onoff = 0; + } +} + +static struct i2c_gpio_platform_data gpio_i2c_data22 = { + .sda_pin = GPIO_IRDA_SDA, + .scl_pin = GPIO_IRDA_SCL, + .udelay = 2, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +struct platform_device s3c_device_i2c22 = { + .name = "i2c-gpio", + .id = 22, + .dev.platform_data = &gpio_i2c_data22, +}; + +static struct mc96_platform_data mc96_pdata = { + .ir_remote_init = irda_device_init, + .ir_wake_en = irda_wake_en, + .ir_vdd_onoff = irda_vdd_onoff, +}; + +static struct i2c_board_info i2c_devs22_emul[] __initdata = { + { + I2C_BOARD_INFO("mc96", (0XA0 >> 1)), + .platform_data = &mc96_pdata, + }, +}; +#endif + #ifdef CONFIG_I2C_GPIO #ifdef CONFIG_MOTOR_DRV_ISA1200 static void isa1200_init(void) @@ -1103,6 +1187,7 @@ static void sec_charger_cb(int set_cable_type) struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); bool cable_state_to_tsp; bool cable_state_to_usb; + enum usb_path_t usb_path; switch (set_cable_type) { case CHARGER_USB: @@ -1118,6 +1203,16 @@ static void sec_charger_cb(int set_cable_type) cable_state_to_usb = false; is_cable_attached = true; is_usb_lpm_enter = true; + + usb_path = usb_switch_get_path(); + if (usb_path != USB_PATH_AP) { + usb_switch_lock(); + usb_switch_set_path(USB_PATH_TA); + usb_switch_unlock(); + } else { + pr_info("%s: charger is detected and ap path\n", + __func__); + } break; case CHARGER_BATTERY: case CHARGER_DISCHARGE: @@ -1126,6 +1221,9 @@ static void sec_charger_cb(int set_cable_type) cable_state_to_usb = false; is_cable_attached = false; is_usb_lpm_enter = true; + usb_switch_lock(); + usb_switch_clr_path(USB_PATH_TA); + usb_switch_unlock(); break; } pr_info("%s:cable_type=%d,tsp(%d),usb(%d),attached(%d),usblpm(%d)\n", @@ -1136,9 +1234,20 @@ static void sec_charger_cb(int set_cable_type) synaptics_ts_charger_infom(is_cable_attached); #endif +#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S) + ts_charger_infom(is_cable_attached); +#endif + /* Send charger state to px-switch. px-switch needs cable type what USB or not */ set_usb_connection_state(!is_usb_lpm_enter); +#ifdef CONFIG_TARGET_LOCALE_KOR + if (px_switch_get_usb_lock_state()) { + pr_info("%s: usb locked by mdm\n", __func__); + return; + } +#endif + /* Send charger state to USB. USB needs cable type what USB data or not */ if (gadget) { if (cable_state_to_usb) @@ -1172,6 +1281,11 @@ static struct sec_battery_platform_data sec_battery_platform = { .temp_high_recovery = 42000, /* 42c */ .temp_low_recovery = 0, /* 0c */ .temp_low_threshold = -5000, /* -5c */ +#elif defined(CONFIG_TARGET_LOCALE_KOR) + .temp_high_threshold = 61400, /* 65c */ + .temp_high_recovery = 43500, /* 42c */ + .temp_low_recovery = 0, /* 0c */ + .temp_low_threshold = -5000, /* -5c */ #else .temp_high_threshold = 50000, /* 50c */ .temp_high_recovery = 42000, /* 42c */ @@ -1341,9 +1455,26 @@ static void check_uart_path(bool en) printk(KERN_DEBUG "[Keyboard] uart_sel2 : %d\n", gpio_get_value(gpio_uart_sel2)); #else +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + int gpio_uart_sel2; gpio_uart_sel = GPIO_UART_SEL; + gpio_uart_sel2 = GPIO_UART_SEL2; +#else + gpio_uart_sel = GPIO_UART_SEL; +#endif #endif +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + if (en) { + gpio_direction_output(gpio_uart_sel, 1); + gpio_direction_output(gpio_uart_sel2, 1); + printk(KERN_DEBUG "[Keyboard] uart_sel : 1, 1\n"); + } else { + gpio_direction_output(gpio_uart_sel, 0); + gpio_direction_output(gpio_uart_sel2, 0); + printk(KERN_DEBUG "[Keyboard] uart_sel : 0, 0\n"); + } +#else if (en) gpio_direction_output(gpio_uart_sel, 1); else @@ -1351,6 +1482,7 @@ static void check_uart_path(bool en) printk(KERN_DEBUG "[Keyboard] uart_sel : %d\n", gpio_get_value(gpio_uart_sel)); +#endif } static void sec_keyboard_register_cb(struct sec_keyboard_callbacks *cb) @@ -1398,6 +1530,8 @@ static void px_usb_otg_en(int active) usb_switch_set_path(USB_PATH_AP); px_usb_otg_power(1); + msleep(500); + host_notifier_pdata.ndev.mode = NOTIFY_HOST_MODE; if (host_notifier_pdata.usbhostd_start) host_notifier_pdata.usbhostd_start(); @@ -1478,7 +1612,7 @@ static struct platform_device exynos4_busfreq = { .name = "exynos-busfreq", }; -#if defined(CONFIG_SENSORS_BH1721) +#if defined(CONFIG_SENSORS_BH1721) || defined(CONFIG_SENSORS_AL3201) static struct i2c_gpio_platform_data i2c9_platdata = { .sda_pin = GPIO_PS_ALS_SDA_28V, .scl_pin = GPIO_PS_ALS_SCL_28V, @@ -1530,7 +1664,7 @@ static struct platform_device s3c_device_i2c11 = { #endif /* IR_LED */ -#ifdef CONFIG_IR_REMOCON +#ifdef CONFIG_IR_REMOCON_GPIO static struct platform_device ir_remote_device = { .name = "ir_rc", @@ -1549,7 +1683,87 @@ static void ir_rc_init_hw(void) #endif /* IR_LED */ +#ifdef CONFIG_SEC_WATCHDOG_RESET +static struct platform_device watchdog_reset_device = { + .name = "watchdog-reset", + .id = -1, +}; +#endif + +#ifdef CONFIG_CORESIGHT_ETM + +#define CORESIGHT_PHYS_BASE 0x10880000 +#define CORESIGHT_ETB_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1000) +#define CORESIGHT_TPIU_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x3000) +#define CORESIGHT_FUNNEL_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x4000) +#define CORESIGHT_ETM_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1C000) + +static struct resource coresight_etb_resources[] = { + { + .start = CORESIGHT_ETB_PHYS_BASE, + .end = CORESIGHT_ETB_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_etb_device = { + .name = "coresight_etb", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_etb_resources), + .resource = coresight_etb_resources, +}; + +static struct resource coresight_tpiu_resources[] = { + { + .start = CORESIGHT_TPIU_PHYS_BASE, + .end = CORESIGHT_TPIU_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_tpiu_device = { + .name = "coresight_tpiu", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_tpiu_resources), + .resource = coresight_tpiu_resources, +}; + +static struct resource coresight_funnel_resources[] = { + { + .start = CORESIGHT_FUNNEL_PHYS_BASE, + .end = CORESIGHT_FUNNEL_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_funnel_device = { + .name = "coresight_funnel", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_funnel_resources), + .resource = coresight_funnel_resources, +}; + +static struct resource coresight_etm_resources[] = { + { + .start = CORESIGHT_ETM_PHYS_BASE, + .end = CORESIGHT_ETM_PHYS_BASE + (SZ_4K * 4) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_etm_device = { + .name = "coresight_etm", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_etm_resources), + .resource = coresight_etm_resources, +}; + +#endif + static struct platform_device *midas_devices[] __initdata = { +#ifdef CONFIG_SEC_WATCHDOG_RESET + &watchdog_reset_device, +#endif #ifdef CONFIG_ANDROID_RAM_CONSOLE &ram_console_device, #endif @@ -1637,6 +1851,11 @@ static struct platform_device *midas_devices[] __initdata = { #ifdef CONFIG_LEDS_AN30259A &s3c_device_i2c21, #endif + +#ifdef CONFIG_IR_REMOCON_MC96 + &s3c_device_i2c22, +#endif + #if defined CONFIG_USB_EHCI_S5P && !defined CONFIG_LINK_DEVICE_HSIC &s5p_device_ehci, #endif @@ -1789,12 +2008,18 @@ static struct platform_device *midas_devices[] __initdata = { &sec_keyboard, #endif #endif -#if defined(CONFIG_IR_REMOCON) +#if defined(CONFIG_IR_REMOCON_GPIO) /* IR_LED */ &ir_remote_device, /* IR_LED */ #endif +#ifdef CONFIG_CORESIGHT_ETM + &coresight_etb_device, + &coresight_tpiu_device, + &coresight_funnel_device, + &coresight_etm_device, +#endif }; #ifdef CONFIG_EXYNOS4_SETUP_THERMAL @@ -1817,7 +2042,7 @@ struct s5p_platform_tmu midas_tmu_data __initdata = { .limit_2nd_throttle = 200000, /* 200MHz in KHz order */ }, .temp_compensate = { - .arm_volt = 900000, /* vdd_arm in uV for temp compensation */ + .arm_volt = 925000, /* vdd_arm in uV for temp compensation */ .bus_volt = 900000, /* vdd_bus in uV for temp compensation */ .g3d_volt = 900000, /* vdd_g3d in uV for temp compensation */ }, @@ -1866,6 +2091,9 @@ static void __init exynos4_reserve_mem(void) { .name = "fimd", .size = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMD * SZ_1K, + { + .alignment = 1 << 20, + }, .start = 0 }, #endif @@ -2266,6 +2494,11 @@ static void __init midas_machine_init(void) ARRAY_SIZE(i2c_devs21_emul)); #endif +#ifdef CONFIG_IR_REMOCON_MC96 + i2c_register_board_info(22, i2c_devs22_emul, + ARRAY_SIZE(i2c_devs22_emul)); +#endif + #if defined(GPIO_OLED_DET) gpio_request(GPIO_OLED_DET, "OLED_DET"); s5p_register_gpio_interrupt(GPIO_OLED_DET); @@ -2389,7 +2622,7 @@ static void __init midas_machine_init(void) platform_device_register(&s3c_device_i2c5); #endif -#if defined(CONFIG_SENSORS_BH1721) +#if defined(CONFIG_SENSORS_BH1721) || defined(CONFIG_SENSORS_AL3201) platform_device_register(&s3c_device_i2c9); #endif @@ -2506,7 +2739,7 @@ static void __init midas_machine_init(void) __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS1) & 0xfff0fff0) | 0x80008, EXYNOS4_CLKDIV_FSYS1); -#if defined(CONFIG_IR_REMOCON) +#if defined(CONFIG_IR_REMOCON_GPIO) /* IR_LED */ ir_rc_init_hw(); /* IR_LED */ diff --git a/arch/arm/mach-exynos/mach-px.c b/arch/arm/mach-exynos/mach-px.c index b4cc19c..c5c4cc8 100644 --- a/arch/arm/mach-exynos/mach-px.c +++ b/arch/arm/mach-exynos/mach-px.c @@ -222,6 +222,13 @@ static struct wacom_g5_callbacks *wacom_callbacks; #endif /* CONFIG_EPEN_WACOM_G5SP */ +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN +#include <linux/usb.h> +#include <linux/usb/hcd.h> +#include <linux/platform_data/usb3503_otg_conn.h> +#endif + + static struct charging_status_callbacks { void (*tsp_set_charging_cable) (int type); } charging_cbs; @@ -363,9 +370,13 @@ static struct tasklet_struct hostwake_task; static void wlan_hostwake_task(unsigned long data) { +#if defined(CONFIG_MACH_P8LTE) + printk(KERN_INFO "WLAN: wake lock timeout 1 sec...\n"); + wake_lock_timeout(&wsi->wake_lock, HZ); +#else printk(KERN_INFO "WLAN: wake lock timeout 0.5 sec...\n"); - wake_lock_timeout(&wsi->wake_lock, HZ / 2); +#endif } static irqreturn_t wlan_hostwake_isr(int irq, void *dev_id) @@ -6015,9 +6026,9 @@ static void __init smdkc210_usbgadget_init(void) pdata->phy_tune |= 0x1 << 11; #elif defined(CONFIG_TARGET_LOCALE_P2EUR_TEMP) /* P2 EUR OPEN */ - /*squelch threshold tune [13:11] (000 : +15%) */ + /*squelch threshold tune [13:11] (100 : -5%) */ pdata->phy_tune_mask |= 0x7 << 11; - pdata->phy_tune |= 0x0 << 11; + pdata->phy_tune |= 0x4 << 11; #endif printk(KERN_DEBUG "usb: %s tune_mask=0x%x, tune=0x%x\n", __func__, pdata->phy_tune_mask, pdata->phy_tune); @@ -6258,6 +6269,82 @@ static struct platform_device sec_battery_device = { }; #endif /* CONFIG_BATTERY_SEC_PX */ +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN +int usb3503_hw_config(void) +{ + s3c_gpio_cfgpin(GPIO_USB_HUB_RST, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_USB_HUB_RST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_USB_HUB_RST, S3C_GPIO_SETPIN_ZERO); + s5p_gpio_set_drvstr(GPIO_USB_HUB_RST, + S5P_GPIO_DRVSTR_LV1); /* need to check drvstr 1 or 2 */ + + return 0; +} + +int usb3503_reset_n(int val) +{ + gpio_set_value(GPIO_USB_HUB_RST, !!val); + + pr_info("Board : %s = %d\n", __func__, + gpio_get_value(GPIO_USB_HUB_RST)); + + return 0; +} + +static int host_port_enable(int port, int enable) +{ + int err; + + pr_info("port(%d) control(%d)\n", port, enable); + + if (enable) { + err = s5p_ehci_port_control(&s5p_device_ehci, port, 1); + if (err < 0) { + pr_err("ERR: port(%d) enable fail\n", port); + goto exit; + } + } else { + err = s5p_ehci_port_control(&s5p_device_ehci, port, 0); + if (err < 0) { + pr_err("ERR: port(%d) enable fail\n", port); + goto exit; + } + } + +exit: + return err; +} + +/* I2C17_EMUL */ +static struct i2c_gpio_platform_data i2c17_platdata = { + .sda_pin = GPIO_USB_HUB_I2C_SDA, + .scl_pin = GPIO_USB_HUB_I2C_SCL, +}; + +struct platform_device s3c_device_i2c17 = { + .name = "i2c-gpio", + .id = 17, + .dev.platform_data = &i2c17_platdata, +}; + +struct usb3503_platform_data usb3503_pdata = { + .init_needed = 1, + .es_ver = 1, + .inital_mode = USB_3503_MODE_STANDBY, + .hw_config = usb3503_hw_config, + .reset_n = usb3503_reset_n, + .port_enable = host_port_enable, +}; + +static struct i2c_board_info i2c_devs17_emul[] __initdata = { + { + I2C_BOARD_INFO(USB3503_I2C_NAME, 0x08), + .platform_data = &usb3503_pdata, + }, +}; +#endif + + #ifdef CONFIG_30PIN_CONN static void smdk_accessory_gpio_init(void) { @@ -6456,8 +6543,17 @@ struct platform_device host_notifier_device = { .dev.platform_data = &host_notifier_pdata, }; +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN +#define RETRY_CNT_LIMIT 100 +#endif + static void px_usb_otg_en(int active) { +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN + struct usb_hcd *ehci_hcd = platform_get_drvdata(&s5p_device_ehci); + int retry_cnt = 1; +#endif + pr_info("otg %s : %d\n", __func__, active); usb_switch_lock(); @@ -6484,6 +6580,16 @@ static void px_usb_otg_en(int active) #endif #ifdef CONFIG_USB_EHCI_S5P pm_runtime_put_sync(&s5p_device_ehci.dev); +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN + /* waiting for ehci root hub suspend is done */ + while (ehci_hcd->state != HC_STATE_SUSPENDED) { + msleep(50); + if (retry_cnt++ > RETRY_CNT_LIMIT) { + printk(KERN_ERR "ehci suspend not completed\n"); + break; + } + } +#endif #endif usb_switch_clr_path(USB_PATH_HOST); @@ -6494,6 +6600,23 @@ static void px_usb_otg_en(int active) } usb_switch_unlock(); + +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN + if (!active) { + host_port_enable(2, 0); + usb3503_set_mode(USB_3503_MODE_STANDBY); + } + + gpio_request(GPIO_USB_OTG_EN, "GPIO_USB_OTG_EN"); + gpio_direction_output(GPIO_USB_OTG_EN, active); + gpio_free(GPIO_USB_OTG_EN); + + if (active) { + usb3503_set_mode(USB_3503_MODE_HUB); + host_port_enable(2, 1); + } +#endif + } #endif @@ -6540,6 +6663,77 @@ static struct platform_device watchdog_reset_device = { .id = -1, }; #endif + +#ifdef CONFIG_CORESIGHT_ETM + +#define CORESIGHT_PHYS_BASE 0x10880000 +#define CORESIGHT_ETB_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1000) +#define CORESIGHT_TPIU_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x3000) +#define CORESIGHT_FUNNEL_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x4000) +#define CORESIGHT_ETM_PHYS_BASE (CORESIGHT_PHYS_BASE + 0x1C000) + +static struct resource coresight_etb_resources[] = { + { + .start = CORESIGHT_ETB_PHYS_BASE, + .end = CORESIGHT_ETB_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_etb_device = { + .name = "coresight_etb", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_etb_resources), + .resource = coresight_etb_resources, +}; + +static struct resource coresight_tpiu_resources[] = { + { + .start = CORESIGHT_TPIU_PHYS_BASE, + .end = CORESIGHT_TPIU_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_tpiu_device = { + .name = "coresight_tpiu", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_tpiu_resources), + .resource = coresight_tpiu_resources, +}; + +static struct resource coresight_funnel_resources[] = { + { + .start = CORESIGHT_FUNNEL_PHYS_BASE, + .end = CORESIGHT_FUNNEL_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_funnel_device = { + .name = "coresight_funnel", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_funnel_resources), + .resource = coresight_funnel_resources, +}; + +static struct resource coresight_etm_resources[] = { + { + .start = CORESIGHT_ETM_PHYS_BASE, + .end = CORESIGHT_ETM_PHYS_BASE + (SZ_4K * 2) - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device coresight_etm_device = { + .name = "coresight_etm", + .id = -1, + .num_resources = ARRAY_SIZE(coresight_etm_resources), + .resource = coresight_etm_resources, +}; + +#endif + static struct platform_device *smdkc210_devices[] __initdata = { #ifdef CONFIG_SEC_WATCHDOG_RESET &watchdog_reset_device, @@ -6622,6 +6816,9 @@ static struct platform_device *smdkc210_devices[] __initdata = { #ifdef CONFIG_S3C_DEV_I2C16_EMUL &s3c_device_i2c16, #endif +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN + &s3c_device_i2c17, /* USB HUB */ +#endif #endif /* consumer driver should resume after resuming i2c drivers */ @@ -6802,6 +6999,12 @@ static struct platform_device *smdkc210_devices[] __initdata = { &sec_keyboard, #endif #endif +#ifdef CONFIG_CORESIGHT_ETM + &coresight_etb_device, + &coresight_tpiu_device, + &coresight_funnel_device, + &coresight_etm_device, +#endif }; #ifdef CONFIG_EXYNOS4_SETUP_THERMAL @@ -7397,6 +7600,10 @@ static void __init smdkc210_machine_init(void) #ifdef CONFIG_S3C_DEV_I2C16_EMUL i2c_register_board_info(16, i2c_devs16, ARRAY_SIZE(i2c_devs16)); #endif +#ifdef CONFIG_USBHUB_USB3503_OTG_CONN + i2c_register_board_info(17, i2c_devs17_emul, + ARRAY_SIZE(i2c_devs17_emul)); +#endif #endif smdkc210_smsc911x_init(); diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c index 09f039d..97daba2 100644 --- a/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/arch/arm/mach-exynos/mach-smdk4x12.c @@ -4365,7 +4365,7 @@ static void __init exynos_c2c_reserve(void) } #endif -MACHINE_START(SMDK4212, "smdk4x12") +MACHINE_START(SMDK4212, "SMDK4X12") .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, @@ -4376,7 +4376,7 @@ MACHINE_START(SMDK4212, "smdk4x12") #endif MACHINE_END -MACHINE_START(SMDK4412, "smdk4x12") +MACHINE_START(SMDK4412, "SMDK4X12") .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, diff --git a/arch/arm/mach-exynos/mach-u1.c b/arch/arm/mach-exynos/mach-u1.c index e0871f6..7e1ef2f 100644 --- a/arch/arm/mach-exynos/mach-u1.c +++ b/arch/arm/mach-exynos/mach-u1.c @@ -127,6 +127,9 @@ #include <media/s5k5bafx_platform.h> #endif +#ifdef CONFIG_VIDEO_S5K5BBGX +#include <media/s5k5bbgx_platform.h> +#endif #if defined(CONFIG_EXYNOS4_SETUP_THERMAL) #include <plat/s5p-tmu.h> #include <mach/regs-tmu.h> @@ -136,6 +139,10 @@ #include <linux/sec_jack.h> #endif +#ifdef CONFIG_USBHUB_USB3803 +#include <linux/usb3803.h> +#endif + #ifdef CONFIG_BT_BCM4330 #include <mach/board-bluetooth-bcm.h> #endif @@ -208,6 +215,9 @@ static struct wacom_g5_callbacks *wacom_callbacks; #include <linux/phone_svn/ipc_spi.h> #include <linux/irq.h> #endif +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#include "../../../drivers/usb/gadget/s3c_udc.h" +#endif /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -289,6 +299,7 @@ static int m5mo_get_i2c_busnum(void) #endif } + static int m5mo_power_on(void) { struct regulator *regulator; @@ -1186,6 +1197,300 @@ static struct s3c_platform_camera s5k5bafx = { }; #endif +#ifdef CONFIG_VIDEO_S5K5BBGX +static int s5k5bbgx_get_i2c_busnum(void) +{ + return 12; +} + +static int s5k5bbgx_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + /* printk("%s: in\n", __func__); */ + + ret = gpio_request(GPIO_ISP_RESET, "GPY3"); + if (ret) { + printk(KERN_ERR "faile to request gpio(ISP_RESET)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_IO_EN, "GPE2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_IO_EN)\n"); + return ret; + } + ret = gpio_request(GPIO_VT_CAM_15V, "GPE2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); + return ret; + } + + s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_NONE); + + /* ISP_RESET low*/ + ret = gpio_direction_output(GPIO_ISP_RESET, 0); + CAM_CHECK_ERR_RET(ret, "output reset"); + udelay(100); + + /* CAM_ISP_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_isp_core"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable isp_core"); + udelay(10); + + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 1); + CAM_CHECK_ERR_RET(ret, "output io_en"); + udelay(300); /* don't change me */ + + /* VT_CORE_1.5V */ + ret = gpio_direction_output(GPIO_VT_CAM_15V, 1); + CAM_CHECK_ERR_RET(ret, "output vt_15v"); + udelay(100); + + /* CAM_ISP_1.8V */ + regulator = regulator_get(NULL, "cam_isp"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_isp"); + udelay(10); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable vt_1.8v"); + udelay(10); + + /* Mclk */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); + CAM_CHECK_ERR_RET(ret, "cfg mclk"); + udelay(10); + + /* CAM_VGA_nSTBY */ + ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + CAM_CHECK_ERR_RET(ret, "output VGA_nSTBY"); + udelay(50); + + /* CAM_VGA_nRST */ + ret = gpio_direction_output(GPIO_CAM_VGA_nRST, 1); + CAM_CHECK_ERR_RET(ret, "output VGA_nRST"); + udelay(100); + + gpio_free(GPIO_ISP_RESET); + gpio_free(GPIO_CAM_IO_EN); + gpio_free(GPIO_VT_CAM_15V); + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_CAM_VGA_nRST); + + return 0; +} + +static int s5k5bbgx_power_off(void) +{ + struct regulator *regulator; + int ret = 0; + + /* printk("n%s: in\n", __func__); */ + + ret = gpio_request(GPIO_CAM_VGA_nRST, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_VGA_nSTBY, "GPL2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nSTBY)\n"); + return ret; + } + ret = gpio_request(GPIO_VT_CAM_15V, "GPE2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_VT_CAM_15V)\n"); + return ret; + } + ret = gpio_request(GPIO_CAM_IO_EN, "GPE2"); + if (ret) { + printk(KERN_ERR "faile to request gpio(GPIO_CAM_IO_EN)\n"); + return ret; + } + + /* CAM_VGA_nRST */ + ret = gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + CAM_CHECK_ERR(ret, "output VGA_nRST"); + udelay(100); + + /* CAM_VGA_nSTBY */ + ret = gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + CAM_CHECK_ERR(ret, "output VGA_nSTBY"); + udelay(20); + + /* Mclk */ + ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); + CAM_CHECK_ERR(ret, "cfg mclk"); + udelay(20); + + /* VT_CAM_1.8V */ + regulator = regulator_get(NULL, "vt_cam_1.8v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable vt_1.8v"); + udelay(10); + + /* CAM_ISP_1.8V */ + regulator = regulator_get(NULL, "cam_isp"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable cam_isp"); + udelay(10); + + /* VT_CORE_1.5V */ + ret = gpio_direction_output(GPIO_VT_CAM_15V, 0); + CAM_CHECK_ERR(ret, "output vt_1.5v"); + udelay(10); + + /* CAM_SENSOR_A2.8V */ + ret = gpio_direction_output(GPIO_CAM_IO_EN, 0); + CAM_CHECK_ERR(ret, "output io_en"); + udelay(10); + + /* CAM_ISP_CORE_1.2V */ + regulator = regulator_get(NULL, "cam_isp_core"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable isp_core"); + + gpio_direction_input(VT_CAM_SDA_18V); + s3c_gpio_setpull(VT_CAM_SDA_18V, S3C_GPIO_PULL_DOWN); + gpio_direction_input(VT_CAM_SCL_18V); + s3c_gpio_setpull(VT_CAM_SCL_18V, S3C_GPIO_PULL_DOWN); + + gpio_free(GPIO_CAM_VGA_nRST); + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_VT_CAM_15V); + gpio_free(GPIO_CAM_IO_EN); + + return 0; +} + +static int s5k5bbgx_power(int onoff) +{ + int ret = 0; + + printk(KERN_INFO "%s(): %s\n", __func__, onoff ? "on" : "down"); + if (onoff) { +#if defined(CONFIG_TARGET_LOCALE_NA) + exynos_cpufreq_lock(DVFS_LOCK_ID_CAM, 1); + ret = s5k5bbgx_power_on(); + exynos_cpufreq_lock_free(DVFS_LOCK_ID_CAM); +#else + ret = s5k5bbgx_power_on(); +#endif + if (unlikely(ret)) + goto error_out; + } else { +#if defined(CONFIG_TARGET_LOCALE_NA) + exynos_cpufreq_lock(DVFS_LOCK_ID_CAM, 1); + ret = s5k5bbgx_power_off(); + exynos_cpufreq_lock_free(DVFS_LOCK_ID_CAM); +#else + ret = s5k5bbgx_power_off(); +#endif + /* s3c_i2c0_force_stop();*/ /* DSLIM. Should be implemented */ + } + + /* ret = s3c_csis_power(onoff); */ + +error_out: + return ret; +} + +static struct s5k5bbgx_platform_data s5k5bbgx_plat = { + .default_width = 640, + .default_height = 480, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 0, +}; + +static struct i2c_board_info s5k5bbgx_i2c_info = { + I2C_BOARD_INFO("S5K5BBGX", 0x5A >> 1), + .platform_data = &s5k5bbgx_plat, +}; + +static struct s3c_platform_camera s5k5bbgx = { +#if defined(CONFIG_VIDEO_S5K5BBGX_MIPI) + .id = CAMERA_CSI_D, + .type = CAM_TYPE_MIPI, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + + .mipi_lanes = 1, + .mipi_settle = 6, + .mipi_align = 32, +#else + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR, +#endif + .get_i2c_busnum = s5k5bbgx_get_i2c_busnum, + .info = &s5k5bbgx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam0", + .clk_rate = 24000000, + .line_length = 640, + .width = 640, + .height = 480, + .window = { + .left = 0, + .top = 0, + .width = 640, + .height = 480, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .reset_camera = 0, + .initialized = 0, + .cam_power = s5k5bbgx_power, +}; +#endif + + #ifdef WRITEBACK_ENABLED static int get_i2c_busnum_writeback(void) { @@ -1261,6 +1566,10 @@ static struct s3c_platform_fimc fimc_plat = { #ifdef CONFIG_VIDEO_M5MO &m5mo, #endif +#ifdef CONFIG_VIDEO_S5K5BBGX + &s5k5bbgx, +#endif + #ifdef CONFIG_VIDEO_S5K5BAFX &s5k5bafx, #endif @@ -1269,7 +1578,11 @@ static struct s3c_platform_fimc fimc_plat = { #endif }, .hw_ver = 0x51, +#if defined(CONFIG_VIDEO_S5K5BBGX) + .cfg_gpio = s3c_fimc0_cfg_gpio, +#else .cfg_gpio = cam_cfg_gpio, +#endif }; #endif /* CONFIG_VIDEO_FIMC */ @@ -1296,6 +1609,12 @@ static int ext_cd_cleanup_hsmmc##num(void (*notify_func)( \ return 0; \ } +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#ifdef CONFIG_S3C_DEV_HSMMC2 + DEFINE_MMC_CARD_NOTIFIER(2) +#endif +#endif + #ifdef CONFIG_S3C_DEV_HSMMC3 DEFINE_MMC_CARD_NOTIFIER(3) #endif @@ -1309,12 +1628,24 @@ void mmc_force_presence_change(struct platform_device *pdev) { void (*notify_func)(struct platform_device *, int state) = NULL; mutex_lock(¬ify_lock); +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#ifdef CONFIG_S3C_DEV_HSMMC2 + if (pdev == &s3c_device_hsmmc2) { + printk(KERN_INFO "Test logs pdev : %p s3c_device_hsmmc2 %p\n", + pdev, &s3c_device_hsmmc2); + notify_func = hsmmc2_notify_func; + printk(KERN_INFO "Test logs notify_func = hsmmc2_notify_func : %p\n", + notify_func); + } +#endif +#endif #ifdef CONFIG_S3C_DEV_HSMMC3 - printk("---------test logs pdev : %p s3c_device_hsmmc3 %p \n", - pdev, &s3c_device_hsmmc3); if (pdev == &s3c_device_hsmmc3) { + printk(KERN_INFO "Test logs pdev : %p s3c_device_hsmmc3 %p\n", + pdev, &s3c_device_hsmmc3); notify_func = hsmmc3_notify_func; - printk("---------test logs notify_func : %p \n", notify_func); + printk(KERN_INFO"Test logs notify_func = hsmmc3_notify_func: %p\n", + notify_func); } #endif @@ -1339,11 +1670,21 @@ static struct s3c_sdhci_platdata exynos4_hsmmc0_pdata __initdata = { #ifdef CONFIG_S3C_DEV_HSMMC2 static struct s3c_sdhci_platdata exynos4_hsmmc2_pdata __initdata = { +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) + .cd_type = S3C_SDHCI_CD_EXTERNAL, +#else .cd_type = S3C_SDHCI_CD_GPIO, .ext_cd_gpio = EXYNOS4_GPX3(4), + .vmmc_name = "vtf_2.8v", .ext_cd_gpio_invert = 1, +#endif .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, - .vmmc_name = "vtf_2.8v", +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +/* For Wi-Fi */ + .ext_cd_init = ext_cd_init_hsmmc2, + .ext_cd_cleanup = ext_cd_cleanup_hsmmc2, + .pm_flags = S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME, +#endif }; #endif @@ -2167,10 +2508,12 @@ static void __init ld9040_fb_init(void) lcdtype = max(ld9040_lcdtype, lcdtype); +#if !defined(CONFIG_PANEL_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) if (lcdtype == LCDTYPE_SM2_A2) ld9040_platform_data.pdata = &u1_panel_data_a2; else if (lcdtype == LCDTYPE_M2) ld9040_platform_data.pdata = &u1_panel_data_m2; +#endif pdata = ld9040_platform_data.pdata; pdata->ops = &ops; @@ -2636,7 +2979,7 @@ static struct regulator_consumer_supply led_movie_supply[] = { REGULATOR_SUPPLY("led_movie", NULL), }; -#if defined(CONFIG_MACH_Q1_BD) +#if defined(CONFIG_MACH_Q1_BD) || defined(CONFIG_LEDS_MAX8997) static struct regulator_consumer_supply led_torch_supply[] = { REGULATOR_SUPPLY("led_torch", NULL), }; @@ -2875,7 +3218,7 @@ static struct regulator_init_data led_movie_init_data = { .max_uA = 250000, .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS, -#if !defined(CONFIG_MACH_Q1_BD) +#if !defined(CONFIG_MACH_Q1_BD) && !defined(CONFIG_LEDS_MAX8997) .state_mem = { .disabled = 1, }, @@ -2885,7 +3228,7 @@ static struct regulator_init_data led_movie_init_data = { .consumer_supplies = &led_movie_supply[0], }; -#if defined(CONFIG_MACH_Q1_BD) +#if defined(CONFIG_MACH_Q1_BD) || defined(CONFIG_LEDS_MAX8997) static struct regulator_init_data led_torch_init_data = { .constraints = { .name = "FLASH_TORCH", @@ -2926,7 +3269,7 @@ static struct max8997_regulator_data max8997_regulators[] = { { MAX8997_ESAFEOUT2, &safeout2_init_data, NULL, }, { MAX8997_FLASH_CUR, &led_flash_init_data, NULL, }, { MAX8997_MOVIE_CUR, &led_movie_init_data, NULL, }, -#if defined CONFIG_MACH_Q1_BD +#if defined(CONFIG_MACH_Q1_BD) || defined(CONFIG_LEDS_MAX8997) { MAX8997_FLASH_TORCH, &led_torch_init_data, NULL, }, #endif /* CONFIG_MACH_Q1_BD */ }; @@ -3237,6 +3580,26 @@ static void max8997_muic_usb_cb(u8 usb_mode) } else pr_info("otg error s3c_udc is null.\n"); } +#elif defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +static void max8997_muic_usb_cb(u8 usb_mode) +{ + struct s3c_udc *udc_dev = platform_get_drvdata(&s3c_device_usbgadget); + int ret = 0; + + pr_info("%s: usb mode=%d\n", __func__, usb_mode); + if (udc_dev) { + switch (usb_mode) { + case USB_CABLE_DETACHED: + if (udc_dev->udc_enabled) + usb_gadget_vbus_disconnect(&udc_dev->gadget); + break; + case USB_CABLE_ATTACHED: + if (!udc_dev->udc_enabled) + usb_gadget_vbus_connect(&udc_dev->gadget); + break; + } + } +} #endif static void max8997_muic_mhl_cb(int attached) @@ -3318,7 +3681,7 @@ static void max8997_muic_jig_uart_cb(int path) gpio_set_value(GPIO_UART_SEL, val); pr_info("%s: val:%d\n", __func__, val); } - +#ifdef CONFIG_USB_HOST_NOTIFY static int max8997_muic_host_notify_cb(int enable) { struct host_notify_dev *ndev = &host_notifier_pdata.ndev; @@ -3334,6 +3697,7 @@ static int max8997_muic_host_notify_cb(int enable) return -1; } +#endif static struct max8997_muic_data max8997_muic = { .usb_cb = max8997_muic_usb_cb, @@ -3344,9 +3708,18 @@ static struct max8997_muic_data max8997_muic = { .init_cb = max8997_muic_init_cb, .deskdock_cb = max8997_muic_deskdock_cb, .cardock_cb = max8997_muic_cardock_cb, +#if !defined(CONFIG_MACH_U1_NA_USCC) .cfg_uart_gpio = max8997_muic_cfg_uart_gpio, +#endif .jig_uart_cb = max8997_muic_jig_uart_cb, +#ifdef CONFIG_USB_HOST_NOTIFY .host_notify_cb = max8997_muic_host_notify_cb, +#else + .host_notify_cb = NULL, +#endif +#if !defined(CONFIG_MACH_U1_NA_USCC) + .gpio_uart_sel = GPIO_UART_SEL, +#endif .gpio_usb_sel = GPIO_USB_SEL, }; @@ -3864,6 +4237,85 @@ static struct sec_bat_adc_table_data temper_table[] = { }; #else /* temperature table for ADC 6 */ +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +static struct sec_bat_adc_table_data temper_table[] = { + { 273, 670 }, + { 289, 660 }, + { 304, 650 }, + { 314, 640 }, + { 325, 630 }, + { 337, 620 }, + { 347, 610 }, + { 361, 600 }, + { 376, 590 }, + { 391, 580 }, + { 406, 570 }, + { 417, 560 }, + { 431, 550 }, + { 447, 540 }, + { 474, 530 }, + { 491, 520 }, + { 499, 510 }, + { 511, 500 }, + { 519, 490 }, + { 547, 480 }, + { 568, 470 }, + { 585, 460 }, + { 597, 450 }, + { 614, 440 }, + { 629, 430 }, + { 647, 420 }, + { 672, 410 }, + { 690, 400 }, + { 720, 390 }, + { 735, 380 }, + { 755, 370 }, + { 775, 360 }, + { 795, 350 }, + { 818, 340 }, + { 841, 330 }, + { 864, 320 }, + { 887, 310 }, + { 909, 300 }, + { 932, 290 }, + { 954, 280 }, + { 976, 270 }, + { 999, 260 }, + { 1021, 250 }, + { 1051, 240 }, + { 1077, 230 }, + { 1103, 220 }, + { 1129, 210 }, + { 1155, 200 }, + { 1177, 190 }, + { 1199, 180 }, + { 1220, 170 }, + { 1242, 160 }, + { 1263, 150 }, + { 1284, 140 }, + { 1306, 130 }, + { 1326, 120 }, + { 1349, 110 }, + { 1369, 100 }, + { 1390, 90 }, + { 1411, 80 }, + { 1433, 70 }, + { 1454, 60 }, + { 1474, 50 }, + { 1486, 40 }, + { 1499, 30 }, + { 1512, 20 }, + { 1531, 10 }, + { 1548, 0 }, + { 1570, -10 }, + { 1597, -20 }, + { 1624, -30 }, + { 1633, -40 }, + { 1643, -50 }, + { 1652, -60 }, + { 1663, -70 }, +}; +#else static struct sec_bat_adc_table_data temper_table[] = { { 165, 800 }, { 171, 790 }, @@ -3968,6 +4420,7 @@ static struct sec_bat_adc_table_data temper_table[] = { { 1815, -200 }, }; #endif +#endif #ifdef CONFIG_TARGET_LOCALE_NTT /* temperature table for ADC 7 */ static struct sec_bat_adc_table_data temper_table_ADC7[] = { @@ -4279,6 +4732,35 @@ static struct i2c_board_info i2c_devs19_emul[] = { #endif }; #endif +#ifdef CONFIG_LEDS_GPIO +struct gpio_led leds_gpio[] = { + { + .name = "red", + .default_trigger = NULL, + /* "default-on", // Turn ON RED LED at boot time ! */ + .gpio = GPIO_SVC_LED_RED, + .active_low = 0, + }, + { + .name = "blue", + .default_trigger = NULL, + /* "default-on", // Turn ON BLUE LED at boot time ! */ + .gpio = GPIO_SVC_LED_BLUE, + .active_low = 0, + } +}; + +struct gpio_led_platform_data leds_gpio_platform_data = { + .num_leds = ARRAY_SIZE(leds_gpio), + .leds = leds_gpio, +}; + +struct platform_device sec_device_leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { .platform_data = &leds_gpio_platform_data }, +}; +#endif /* CONFIG_LEDS_GPIO */ #if defined(CONFIG_SEC_THERMISTOR) #if defined(CONFIG_MACH_Q1_BD) @@ -4538,14 +5020,16 @@ struct gpio_keys_button u1_buttons[] = { .isr_hook = sec_debug_check_crash_key, .debounce_interval = 10, }, /* power key */ +#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) { - .code = KEY_HOME, + .code = KEY_HOMEPAGE, .gpio = GPIO_OK_KEY, .active_low = 1, .type = EV_KEY, .wakeup = 1, .debounce_interval = 10, }, /* ok key */ +#endif }; struct gpio_keys_platform_data u1_keypad_platform_data = { @@ -4606,13 +5090,8 @@ static struct sec_jack_zone sec_jack_zones[] = { * stays in this range for 100ms (10ms delays, 10 samples) */ .adc_high = 3800, -#if defined(CONFIG_MACH_Q1_BD) .delay_ms = 15, .check_count = 20, -#else - .delay_ms = 10, - .check_count = 5, -#endif .jack_type = SEC_HEADSET_4POLE, }, { @@ -4688,10 +5167,10 @@ static void mxt224_power_on(void) s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); gpio_set_value(GPIO_TSP_LDO_ON, 1); - mdelay(70); + msleep(70); s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); - mdelay(40); + msleep(40); } static void mxt224_power_off(void) @@ -4796,10 +5275,10 @@ static void mxt224_power_on(void) s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); gpio_set_value(GPIO_TSP_LDO_ON, 1); - mdelay(70); + msleep(70); s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); - mdelay(40); + msleep(40); /* printk("mxt224_power_on is finished\n"); */ } @@ -4822,7 +5301,11 @@ static void mxt224_power_off(void) #define MXT224_THRESHOLD_CHRG 70 #define MXT224_NOISE_THRESHOLD_BATT 30 #define MXT224_NOISE_THRESHOLD_CHRG 40 +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) +#define MXT224_MOVFILTER_BATT 47 +#else #define MXT224_MOVFILTER_BATT 11 +#endif #define MXT224_MOVFILTER_CHRG 47 #define MXT224_ATCHCALST 4 #define MXT224_ATCHCALTHR 35 @@ -4899,6 +5382,7 @@ static const u8 *mxt224_config[] = { #define MXT224E_NEXTTCHDI_CHRG 1 #else #define MXT224E_THRESHOLD_BATT 50 +#define MXT224E_T48_THRESHOLD_BATT 28 #define MXT224E_THRESHOLD_CHRG 40 #define MXT224E_CALCFG_BATT 0x42 #define MXT224E_CALCFG_CHRG 0x52 @@ -4909,12 +5393,14 @@ static const u8 *mxt224_config[] = { #define MXT224E_ATCHFRCCALTHR_NORMAL 40 #define MXT224E_ATCHFRCCALRATIO_NORMAL 55 #endif -#define MXT224E_GHRGTIME_BATT 27 +#define MXT224E_GHRGTIME_BATT 22 #define MXT224E_GHRGTIME_CHRG 22 #define MXT224E_ATCHCALST 4 #define MXT224E_ATCHCALTHR 35 #define MXT224E_BLEN_BATT 32 #define MXT224E_BLEN_CHRG 16 +#define MXT224E_T48_BLEN_BATT 0 +#define MXT224E_T48_BLEN_CHRG 0 #define MXT224E_MOVFILTER_BATT 13 #define MXT224E_MOVFILTER_CHRG 46 #define MXT224E_ACTVSYNCSPERX_NORMAL 32 @@ -5017,7 +5503,6 @@ static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8, /* MXT224E_0V5_CONFIG */ /* NEXTTCHDI added */ #ifdef CONFIG_TARGET_LOCALE_NA -#ifdef CONFIG_MACH_U1_NA_USCC_REV05 static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, 139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1, 10, @@ -5026,17 +5511,6 @@ static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, 223, 1, 10, 10, 10, 10, 143, 40, 143, 80, 18, 15, 50, 50, 0 }; - -#else -static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, - 139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1, - 10, - 10, /* MOVHYSTI */ - 1, MXT224E_MOVFILTER_BATT, MXT224_MAX_MT_FINGERS, 5, 40, 10, 31, 3, - 223, 1, 10, 10, 10, 10, 143, 40, 143, 80, - 18, 15, 50, 50, 2 -}; -#endif #else static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, 139, 0, 0, 19, 11, 0, MXT224E_BLEN_BATT, MXT224E_THRESHOLD_BATT, 2, 1, @@ -5064,15 +5538,9 @@ static u8 t25_config_e[] = { SPT_SELFTEST_T25, 0, 0, 0, 0, 0, 0, 0, 0 }; -#ifdef CONFIG_MACH_U1_NA_USCC_REV05 -static u8 t38_config_e[] = { SPT_USERDATA_T38, - 0, 1, 13, 19, 44, 0, 0, 0 -}; -#else static u8 t38_config_e[] = { SPT_USERDATA_T38, 0, 1, 14, 23, 44, 0, 0, 0 }; -#endif static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40, 0, 0, 0, 0, 0 @@ -5092,51 +5560,27 @@ static u8 t47_config_e[] = { PROCI_STYLUS_T47, /*MXT224E_0V5_CONFIG */ #ifdef CONFIG_TARGET_LOCALE_NA -#ifdef CONFIG_MACH_U1_NA_USCC_REV05 static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, 0x52, 0, 0, 0, 0, 0, 10, 15, + 3, 132, MXT224E_CALCFG_CHRG, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6, 0, 0, 64, 4, 64, - 10, 0, 10, 5, 0, 19, 0, 20, 0, 0, - 0, 0, 0, 0, 0, 40, 2, /*blen=0,threshold=50 */ + 10, 0, 9, 5, 0, 15, 0, 20, 0, 0, + 0, 0, 0, 0, MXT224E_T48_BLEN_CHRG, MXT224E_THRESHOLD_CHRG, 2, 10, /* MOVHYSTI */ 1, 47, - 10, 5, 40, 240, 245, 10, 10, 148, 50, 143, + MXT224_MAX_MT_FINGERS, 5, 40, 240, 245, 10, 10, 148, 50, 143, 80, 18, 10, 0 }; static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, - 3, 132, 0x40, 0, 0, 0, 0, 0, 10, 15, - 0, 0, 0, 6, 6, 0, 0, 64, 4, 64, - 10, 0, 20, 5, 0, 38, 0, 5, 0, 0, /*byte 27 original value 20 */ - 0, 0, 0, 0, 32, MXT224E_THRESHOLD, 2, - 10, - 1, 46, - MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143, - 80, 18, 15, 0 -}; -#else -static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, - 1, 4, 0x50, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 6, 6, 0, 0, 100, 4, 64, - 10, 0, 20, 5, 0, 38, 0, 20, 0, 0, - 0, 0, 0, 0, 0, 40, 2, /*blen=0,threshold=50 */ - 10, /* MOVHYSTI */ - 1, 15, - 10, 5, 40, 240, 245, 10, 10, 148, 50, 143, - 80, 18, 10, 2 -}; - -static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, - 1, 4, 0x40, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 6, 6, 0, 0, 100, 4, 64, - 10, 0, 20, 5, 0, 38, 0, 5, 0, 0, /*byte 27 original value 20 */ - 0, 0, 0, 0, 32, 50, 2, + 3, 132, MXT224E_CALCFG_BATT, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 6, 6, 0, 0, 48, 4, 48, + 10, 0, 10, 5, 0, 20, 0, 5, 0, 0, /*byte 27 original value 20 */ + 0, 0, 0, 0, MXT224E_T48_BLEN_BATT, MXT224E_T48_THRESHOLD_BATT, 2, 10, 1, 46, - MXT224_MAX_MT_FINGERS, 5, 40, 10, 0, 10, 10, 143, 40, 143, - 80, 18, 15, 2 + MXT224_MAX_MT_FINGERS, 5, 40, 240, 245, 10, 10, 148, 50, 143, + 80, 18, 15, MXT224E_NEXTTCHDI_NORMAL }; -#endif /*CONFIG_MACH_U1_NA_USCC_REV05 */ #else static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, 3, 132, MXT224E_CALCFG_CHRG, 0, 0, 0, 0, 0, 10, 15, @@ -5216,7 +5660,7 @@ static struct mxt224_platform_data mxt224_data = { .chrgtime_batt_e = MXT224E_GHRGTIME_BATT, .chrgtime_charging_e = MXT224E_GHRGTIME_CHRG, .blen_batt_e = MXT224E_BLEN_BATT, - .blen_charging_e = MXT224E_BLEN_CHRG, + .blen_charging_e = MXT224E_T48_BLEN_CHRG, .movfilter_batt_e = MXT224E_MOVFILTER_BATT, .movfilter_charging_e = MXT224E_MOVFILTER_CHRG, .actvsyncsperx_e = MXT224E_ACTVSYNCSPERX_NORMAL, @@ -5600,12 +6044,13 @@ static int touchkey_power_on(bool on) if (on) { gpio_direction_output(GPIO_3_TOUCH_INT, 1); - irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), IRQF_TRIGGER_FALLING); + irq_set_irq_type(gpio_to_irq(GPIO_3_TOUCH_INT), + IRQF_TRIGGER_FALLING); s3c_gpio_cfgpin(GPIO_3_TOUCH_INT, S3C_GPIO_SFN(0xf)); s3c_gpio_setpull(GPIO_3_TOUCH_INT, S3C_GPIO_PULL_NONE); - } - else + } else { gpio_direction_input(GPIO_3_TOUCH_INT); + } if (on) ret = touchkey_resume(); @@ -5618,11 +6063,10 @@ static int touchkey_power_on(bool on) static int touchkey_led_power_on(bool on) { #if defined(LED_LDO_WITH_EN_PIN) - if (on) { + if (on) gpio_direction_output(GPIO_3_TOUCH_EN, 1); - } else { + else gpio_direction_output(GPIO_3_TOUCH_EN, 0); - } #else struct regulator *regulator; @@ -5713,6 +6157,12 @@ static struct i2c_board_info i2c_devs3[] __initdata = { #ifdef CONFIG_S3C_DEV_I2C4 /* I2C4 */ static struct i2c_board_info i2c_devs4[] __initdata = { +#if defined(CONFIG_WIMAX_CMC) + { + I2C_BOARD_INFO("max8893_wmx", 0x3E), + .platform_data = NULL, + }, +#endif /* CONFIG_WIMAX_CMC */ }; #endif @@ -5986,6 +6436,43 @@ static int cm3663_ldo(bool on) return 0; } +#ifdef CONFIG_USBHUB_USB3803 +int usb3803_hw_config(void) +{ + int i; + int usb_gpio[] = {GPIO_USB_RESET_N, + GPIO_USB_BYPASS_N, + GPIO_USB_CLOCK_EN}; + + for (i = 0; i < 3; i++) { + s3c_gpio_cfgpin(usb_gpio[i], S3C_GPIO_OUTPUT); + s3c_gpio_setpull(usb_gpio[i], S3C_GPIO_PULL_NONE); + gpio_set_value(usb_gpio[i], S3C_GPIO_SETPIN_ZERO); + s5p_gpio_set_drvstr(usb_gpio[i], S5P_GPIO_DRVSTR_LV1); + /* need to check drvstr 1 or 2 */ + } + return 0; +} + +int usb3803_reset_n(int val) +{ + gpio_set_value(GPIO_USB_RESET_N, !!val); + return 0; +} + +int usb3803_bypass_n(int val) +{ + gpio_set_value(GPIO_USB_BYPASS_N, !!val); + return 0; +} + +int usb3803_clock_en(int val) +{ + gpio_set_value(GPIO_USB_CLOCK_EN, !!val); + return 0; +} +#endif /* CONFIG_USBHUB_USB3803 */ + static struct cm3663_platform_data cm3663_pdata = { .proximity_power = cm3663_ldo, }; @@ -6105,7 +6592,7 @@ void nfc_setup_gpio(void) } #endif -#if defined(CONFIG_VIDEO_S5K5BAFX) +#if defined(CONFIG_VIDEO_S5K5BAFX) || defined(CONFIG_VIDEO_S5K5BBGX) static struct i2c_gpio_platform_data i2c12_platdata = { .sda_pin = VT_CAM_SDA_18V, .scl_pin = VT_CAM_SCL_18V, @@ -6150,6 +6637,46 @@ static struct i2c_board_info i2c_devs16[] __initdata = { }; #endif + +#ifdef CONFIG_S3C_DEV_I2C17_EMUL +/* I2C17_EMUL */ +static struct i2c_gpio_platform_data i2c17_platdata = { + .sda_pin = GPIO_USB_I2C_SDA, + .scl_pin = GPIO_USB_I2C_SCL, +}; + +struct platform_device s3c_device_i2c17 = { + .name = "i2c-gpio", + .id = 17, + .dev.platform_data = &i2c17_platdata, +}; + + +#endif /* CONFIG_S3C_DEV_I2C17_EMUL */ + +#ifdef CONFIG_USBHUB_USB3803 +struct usb3803_platform_data usb3803_pdata = { + .init_needed = 1, + .es_ver = 1, + .inital_mode = USB_3803_MODE_STANDBY, + .hw_config = usb3803_hw_config, + .reset_n = usb3803_reset_n, + .bypass_n = usb3803_bypass_n, + .clock_en = usb3803_clock_en, +}; + +static struct i2c_board_info i2c_devs17_emul[] __initdata = { + { + I2C_BOARD_INFO(USB3803_I2C_NAME, 0x08), + .platform_data = &usb3803_pdata, + }, +}; +#endif /* CONFIG_USBHUB_USB3803 */ + + + + + #endif #ifdef CONFIG_TOUCHSCREEN_S3C2410 @@ -6260,11 +6787,11 @@ static int reset_lcd(void) } gpio_direction_output(EXYNOS4_GPY4(5), 1); - msleep(5); + usleep_range(5000, 5000); gpio_set_value(EXYNOS4_GPY4(5), 0); - msleep(5); + usleep_range(5000, 5000); gpio_set_value(EXYNOS4_GPY4(5), 1); - msleep(5); + usleep_range(5000, 5000); gpio_free(EXYNOS4_GPY4(5)); @@ -6565,6 +7092,10 @@ static struct platform_device *smdkc210_devices[] __initdata = { &exynos4_device_pd[PD_TV], &exynos4_device_pd[PD_GPS], +#if defined(CONFIG_WIMAX_CMC) + &s3c_device_cmc732, +#endif + #ifdef CONFIG_BATTERY_SAMSUNG &samsung_device_battery, #endif @@ -6610,7 +7141,7 @@ static struct platform_device *smdkc210_devices[] __initdata = { #if defined(CONFIG_S3C_DEV_I2C14_EMUL) &s3c_device_i2c14, #endif -#if defined(CONFIG_VIDEO_S5K5BAFX) +#if defined(CONFIG_VIDEO_S5K5BAFX) || defined(CONFIG_VIDEO_S5K5BBGX) &s3c_device_i2c12, #endif #ifdef CONFIG_SAMSUNG_MHL @@ -6625,6 +7156,9 @@ static struct platform_device *smdkc210_devices[] __initdata = { #if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER) &s3c_device_i2c19, /* SMB136, SMB328 */ #endif +#if defined(CONFIG_S3C_DEV_I2C17_EMUL) + &s3c_device_i2c17, /* USB HUB */ +#endif #endif /* consumer driver should resume after resuming i2c drivers */ @@ -6678,6 +7212,9 @@ static struct platform_device *smdkc210_devices[] __initdata = { #ifdef CONFIG_BATTERY_SEC_U1 &sec_device_battery, #endif +#ifdef CONFIG_LEDS_GPIO + &sec_device_leds_gpio, +#endif #ifdef CONFIG_LEDS_MAX8997 &sec_device_leds_max8997, #endif @@ -6806,7 +7343,9 @@ static struct platform_device *smdkc210_devices[] __initdata = { #ifdef CONFIG_USB_HOST_NOTIFY &host_notifier_device, #endif +#ifdef CONFIG_USB_HOST_NOTIFY &s3c_device_usb_otghcd, +#endif }; #ifdef CONFIG_EXYNOS4_SETUP_THERMAL @@ -6868,7 +7407,7 @@ static void __init exynos4_cma_region_reserve(struct cma_region *regions_normal, reg->reserved = 1; } else { paddr = __memblock_alloc_base(reg->size, reg->alignment, - MEMBLOCK_ALLOC_ACCESSIBLE); + MEMBLOCK_ALLOC_ACCESSIBLE); if (paddr) { reg->start = paddr; reg->reserved = 1; @@ -6956,10 +7495,10 @@ static void __init exynos4_reserve_mem(void) }, #endif #ifdef CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE - { - .name = "ion", - .size = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K, - }, + { + .name = "ion", + .size = CONFIG_ION_EXYNOS_CONTIGHEAP_SIZE * SZ_1K, + }, #endif #ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC1 { @@ -7028,9 +7567,10 @@ static void __init exynos4_reserve_mem(void) "android_pmem.0=pmem;android_pmem.1=pmem_gpu1;" "s3cfb.0=fimd;exynos4-fb.0=fimd;" "s3c-fimc.0=fimc0;s3c-fimc.1=fimc1;s3c-fimc.2=fimc2;" - "exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;exynos4210-fimc.2=fimc2;exynos4210-fimc3=fimc3;" + "exynos4210-fimc.0=fimc0;exynos4210-fimc.1=fimc1;" + "exynos4210-fimc.2=fimc2;exynos4210-fimc3=fimc3;" #ifdef CONFIG_ION_EXYNOS - "ion-exynos=ion;" + "ion-exynos=ion;" #endif #ifdef CONFIG_VIDEO_MFC5X "s3c-mfc/A=mfc0,mfc-secure;" @@ -7262,7 +7802,7 @@ static void __init smdkc210_machine_init(void) nfc_setup_gpio(); i2c_register_board_info(14, i2c_devs14, ARRAY_SIZE(i2c_devs14)); #endif -#if defined(CONFIG_VIDEO_S5K5BAFX) +#if defined(CONFIG_VIDEO_S5K5BAFX) || defined(CONFIG_VIDEO_S5K5BBGX) i2c_register_board_info(12, i2c_devs12_emul, ARRAY_SIZE(i2c_devs12_emul)); #endif @@ -7275,10 +7815,15 @@ static void __init smdkc210_machine_init(void) #if defined(CONFIG_SMB136_CHARGER_Q1) || defined(CONFIG_SMB328_CHARGER) i2c_register_board_info(19, i2c_devs19_emul, - ARRAY_SIZE(i2c_devs19_emul)); + ARRAY_SIZE(i2c_devs19_emul)); +#endif +#ifdef CONFIG_S3C_DEV_I2C17_EMUL + i2c_register_board_info(17, i2c_devs17_emul, + ARRAY_SIZE(i2c_devs17_emul)); #endif #endif + /* 400 kHz for initialization of MMC Card */ __raw_writel((__raw_readl(EXYNOS4_CLKDIV_FSYS3) & 0xfffffff0) | 0x9, EXYNOS4_CLKDIV_FSYS3); diff --git a/arch/arm/mach-exynos/mdm2.c b/arch/arm/mach-exynos/mdm2.c index 249b7cf..bb66e2e 100644 --- a/arch/arm/mach-exynos/mdm2.c +++ b/arch/arm/mach-exynos/mdm2.c @@ -36,7 +36,6 @@ #include <asm/uaccess.h> #include <mach/mdm2.h> #include <mach/restart.h> -#include <mach/subsystem_notif.h> #include <mach/subsystem_restart.h> #include <linux/msm_charm.h> #ifndef CONFIG_ARCH_EXYNOS @@ -47,119 +46,227 @@ #include "mdm_private.h" #include <linux/wakelock.h> -#define MDM_MODEM_TIMEOUT 6000 -#define MDM_HOLD_TIME 4000 -#define MDM_MODEM_DELTA 100 +#define MDM_PBLRDY_CNT 20 static int mdm_debug_on; static int power_on_count; +/* ehci driver already loaded by kernel init */ static int hsic_peripheral_status = 1; static DEFINE_MUTEX(hsic_status_lock); static void mdm_peripheral_connect(struct mdm_modem_drv *mdm_drv) { - pr_err("%s\n", __func__); + struct mdm_platform_data *pdata; + + pr_info("%s\n", __func__); + + if (!mdm_drv || !mdm_drv->pdata) + return; + + pdata = mdm_drv->pdata; + mutex_lock(&hsic_status_lock); if (hsic_peripheral_status) goto out; - if (mdm_drv->pdata->peripheral_platform_device) - platform_device_add(mdm_drv->pdata->peripheral_platform_device); + + /* exynos usb phy contgrol seq + * ehci on -> ohci on -> ohci off -> ehci on + */ + if (pdata->peripheral_platform_device_ehci) + platform_device_add(pdata->peripheral_platform_device_ehci); + + /* timing problem occurs when it is controlled after ohci on + * control ap2mdm_wake signal right after ehci host power on + */ + gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 1); + + if (pdata->peripheral_platform_device_ohci) + platform_device_add(pdata->peripheral_platform_device_ohci); + hsic_peripheral_status = 1; out: mutex_unlock(&hsic_status_lock); - pr_err("%s : ap2mdm_status = %d\n", __func__, - gpio_get_value(mdm_drv->ap2mdm_status_gpio)); } -static void mdm_peripheral_disconnect(struct mdm_modem_drv *mdm_drv) +void mdm_peripheral_disconnect(struct mdm_modem_drv *mdm_drv) { - pr_err("%s\n", __func__); + struct mdm_platform_data *pdata; + + pr_info("%s\n", __func__); + + if (!mdm_drv || !mdm_drv->pdata) + return; + + pdata = mdm_drv->pdata; + mutex_lock(&hsic_status_lock); if (!hsic_peripheral_status) goto out; - if (mdm_drv->pdata->peripheral_platform_device) - platform_device_del(mdm_drv->pdata->peripheral_platform_device); + + /* exynos usb phy contgrol seq + * ehci on -> ohci on -> ohci off -> ehci on + */ + if (pdata->peripheral_platform_device_ohci) + platform_device_del(pdata->peripheral_platform_device_ohci); + if (pdata->peripheral_platform_device_ehci) + platform_device_del(pdata->peripheral_platform_device_ehci); + hsic_peripheral_status = 0; out: mutex_unlock(&hsic_status_lock); - pr_err("%s : ap2mdm_status = %d\n", __func__, - gpio_get_value(mdm_drv->ap2mdm_status_gpio)); } -static void power_on_mdm(struct mdm_modem_drv *mdm_drv) +static void mdm_toggle_soft_reset(struct mdm_modem_drv *mdm_drv) { - power_on_count++; + int soft_reset_direction_assert = 0, + soft_reset_direction_de_assert = 1; - pr_err("%s: power count %d\n", __func__, power_on_count); - /* this gpio will be used to indicate apq readiness, - * de-assert it now so that it can asserted later - */ - gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 0); + if (mdm_drv->pdata->soft_reset_inverted) { + soft_reset_direction_assert = 1; + soft_reset_direction_de_assert = 0; + } + gpio_direction_output(mdm_drv->ap2mdm_soft_reset_gpio, + soft_reset_direction_assert); + usleep_range(5000, 10000); + gpio_direction_output(mdm_drv->ap2mdm_soft_reset_gpio, + soft_reset_direction_de_assert); + msleep(20); +} - /* The second attempt to power-on the mdm is the first attempt - * from user space, but we're already powered on. Ignore this. - * Subsequent attempts are from SSR or if something failed, in - * which case we must always reset the modem. - */ - if (power_on_count == 2) - return; +static void mdm_power_down_common(struct mdm_modem_drv *mdm_drv) +{ + int i; + int soft_reset_direction = + mdm_drv->pdata->soft_reset_inverted ? 1 : 0; + + pr_info("%s\n", __func__); + /* Wait for the modem to complete its power down actions. */ + for (i = 20; i > 0; i--) { + if (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0) + break; + msleep(100); + } + if (i == 0) { + pr_err("%s: MDM2AP_STATUS never went low. Doing a hard reset\n", + __func__); + gpio_direction_output(mdm_drv->ap2mdm_soft_reset_gpio, + soft_reset_direction); + /* + * Currently, there is a debounce timer on the charm PMIC. It is + * necessary to hold the PMIC RESET low for ~3.5 seconds + * for the reset to fully take place. Sleep here to ensure the + * reset has occured before the function exits. + */ + msleep(4000); + } mdm_peripheral_disconnect(mdm_drv); +} - /* Pull RESET gpio low and wait for it to settle. */ - pr_info("Pulling RESET gpio low\n"); - gpio_direction_output(mdm_drv->ap2mdm_pmic_reset_n_gpio, 0); - usleep_range(5000, 10000); +static void mdm_do_first_power_on(struct mdm_modem_drv *mdm_drv) +{ + int i; + int pblrdy; - /* Deassert RESET first and wait for ir to settle. */ - pr_info("%s: Pulling RESET gpio high\n", __func__); - gpio_direction_output(mdm_drv->ap2mdm_pmic_reset_n_gpio, 1); - msleep(20); + if (power_on_count != 1) { + pr_err("%s: Calling fn when power_on_count != 1\n", + __func__); + return; + } - /* Pull PWR gpio high and wait for it to settle, but only - * the first time the mdm is powered up. - * Some targets do not use ap2mdm_kpdpwr_n_gpio. + pr_err("%s: Powering on modem for the first time\n", __func__); + gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 0); + mdm_peripheral_disconnect(mdm_drv); + + /* If this is the first power-up after a panic, the modem may still + * be in a power-on state, in which case we need to toggle the gpio + * instead of just de-asserting it. No harm done if the modem was + * powered down. */ - if (power_on_count == 1) { - if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0) { - pr_debug("%s: Powering on mdm modem\n", __func__); - gpio_direction_output(mdm_drv->ap2mdm_kpdpwr_n_gpio, 1); - usleep_range(1000, 1000); - } + mdm_toggle_soft_reset(mdm_drv); + + /* If the device has a kpd pwr gpio then toggle it. */ + if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0) { + /* Pull AP2MDM_KPDPWR gpio high and wait for PS_HOLD to settle, + * then pull it back low. + */ + pr_debug("%s: Pulling AP2MDM_KPDPWR gpio high\n", __func__); + gpio_direction_output(mdm_drv->ap2mdm_kpdpwr_n_gpio, 1); + msleep(1000); + gpio_direction_output(mdm_drv->ap2mdm_kpdpwr_n_gpio, 0); } -#ifdef CONFIG_ARCH_EXYNOS + /* first power charged after 10ms */ + usleep_range(10000, 15000); gpio_direction_output(mdm_drv->ap2mdm_status_gpio, 1); -#endif - mdm_peripheral_connect(mdm_drv); + if (!mdm_drv->mdm2ap_pblrdy) + goto start_mdm_peripheral; + + for (i = 0; i < MDM_PBLRDY_CNT; i++) { + pblrdy = gpio_get_value(mdm_drv->mdm2ap_pblrdy); + if (pblrdy) + break; + usleep_range(5000, 5000); + } + + pr_debug("%s: i:%d\n", __func__, i); + +start_mdm_peripheral: + mdm_peripheral_connect(mdm_drv); msleep(200); } -static void power_down_mdm(struct mdm_modem_drv *mdm_drv) +static void mdm_do_soft_power_on(struct mdm_modem_drv *mdm_drv) { int i; + int pblrdy; - pr_err("%s\n", __func__); - for (i = MDM_MODEM_TIMEOUT; i > 0; i -= MDM_MODEM_DELTA) { - /* pet_watchdog(); */ - msleep(MDM_MODEM_DELTA); - if (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0) + pr_err("%s: soft resetting mdm modem\n", __func__); + mdm_peripheral_disconnect(mdm_drv); + mdm_toggle_soft_reset(mdm_drv); + + if (!mdm_drv->mdm2ap_pblrdy) + goto start_mdm_peripheral; + + for (i = 0; i < MDM_PBLRDY_CNT; i++) { + pblrdy = gpio_get_value(mdm_drv->mdm2ap_pblrdy); + if (pblrdy) break; + usleep_range(5000, 5000); } - if (i <= 0) { - pr_err("%s: MDM2AP_STATUS never went low.\n", - __func__); - gpio_direction_output(mdm_drv->ap2mdm_pmic_reset_n_gpio, 0); - - for (i = MDM_HOLD_TIME; i > 0; i -= MDM_MODEM_DELTA) { - /* pet_watchdog(); */ - msleep(MDM_MODEM_DELTA); - } - } - if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0) - gpio_direction_output(mdm_drv->ap2mdm_kpdpwr_n_gpio, 0); - mdm_peripheral_disconnect(mdm_drv); + + pr_debug("%s: i:%d\n", __func__, i); + +start_mdm_peripheral: + mdm_peripheral_connect(mdm_drv); + msleep(200); +} + +static void mdm_power_on_common(struct mdm_modem_drv *mdm_drv) +{ + power_on_count++; + + /* this gpio will be used to indicate apq readiness, + * de-assert it now so that it can be asserted later. + * May not be used. + */ + if (mdm_drv->ap2mdm_wakeup_gpio > 0) + gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 0); + + /* + * If we did an "early power on" then ignore the very next + * power-on request because it would the be first request from + * user space but we're already powered on. Ignore it. + */ + if (mdm_drv->pdata->early_power_on && + (power_on_count == 2)) + return; + + if (power_on_count == 1) + mdm_do_first_power_on(mdm_drv); + else + mdm_do_soft_power_on(mdm_drv); } #ifdef CONFIG_ARCH_EXYNOS @@ -179,18 +286,18 @@ static void mdm_status_changed(struct mdm_modem_drv *mdm_drv, int value) { pr_debug("%s: value:%d\n", __func__, value); - pr_err("%s: ap2mdm_status = %d\n", __func__, - gpio_get_value(mdm_drv->ap2mdm_status_gpio)); if (value) { mdm_peripheral_disconnect(mdm_drv); mdm_peripheral_connect(mdm_drv); - gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 1); + if (mdm_drv->ap2mdm_wakeup_gpio > 0) + gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 1); } } static struct mdm_ops mdm_cb = { - .power_on_mdm_cb = power_on_mdm, - .power_down_mdm_cb = power_down_mdm, + .power_on_mdm_cb = mdm_power_on_common, + .reset_mdm_cb = mdm_power_on_common, + .power_down_mdm_cb = mdm_power_down_common, .debug_state_changed_cb = debug_state_changed, .status_cb = mdm_status_changed, #ifdef CONFIG_ARCH_EXYNOS @@ -198,19 +305,9 @@ static struct mdm_ops mdm_cb = { #endif }; -/* temprary wakelock, remove when L3 state implemented */ -#ifdef CONFIG_ARCH_EXYNOS -static struct wake_lock mdm_wake; -#endif - static int __init mdm_modem_probe(struct platform_device *pdev) { - pr_err("%s\n", __func__); -/* temprary wakelock, remove when L3 state implemented */ -#ifdef CONFIG_ARCH_EXYNOS - wake_lock_init(&mdm_wake, WAKE_LOCK_SUSPEND, "mdm_wake"); - wake_lock(&mdm_wake); -#endif + pr_info("%s\n", __func__); return mdm_common_create(pdev, &mdm_cb); } @@ -226,7 +323,10 @@ static void mdm_modem_shutdown(struct platform_device *pdev) static struct platform_driver mdm_modem_driver = { .remove = mdm_modem_remove, - .shutdown = mdm_modem_shutdown, + /** + * shutdown has done at reboot notifier + *.shutdown = mdm_modem_shutdown, + */ .driver = { .name = "mdm2_modem", .owner = THIS_MODULE @@ -235,6 +335,9 @@ static struct platform_driver mdm_modem_driver = { static int __init mdm_modem_init(void) { + /* in lpm mode, do not load modem driver */ + if (lpcharge) + return 0; return platform_driver_probe(&mdm_modem_driver, mdm_modem_probe); } diff --git a/arch/arm/mach-exynos/mdm_common.c b/arch/arm/mach-exynos/mdm_common.c index 30b5f75..edd3418 100644 --- a/arch/arm/mach-exynos/mdm_common.c +++ b/arch/arm/mach-exynos/mdm_common.c @@ -36,7 +36,6 @@ #include <asm/uaccess.h> #include <mach/mdm2.h> #include <mach/restart.h> -#include <mach/subsystem_notif.h> #include <mach/subsystem_restart.h> #include <linux/msm_charm.h> #ifndef CONFIG_ARCH_EXYNOS @@ -44,29 +43,161 @@ #endif #include "mdm_private.h" +#ifdef CONFIG_MDM_HSIC_PM +#include <linux/mdm_hsic_pm.h> +static const char rmnet_pm_dev[] = "mdm_hsic_pm0"; +#endif + #ifdef CONFIG_ARCH_EXYNOS #include <linux/interrupt.h> #include <plat/gpio-cfg.h> +#include <mach/gpio.h> #endif #define MDM_MODEM_TIMEOUT 6000 #define MDM_MODEM_DELTA 100 #define MDM_BOOT_TIMEOUT 60000L -#define MDM_RDUMP_TIMEOUT 60000L +#define MDM_RDUMP_TIMEOUT 120000L +#define MDM2AP_STATUS_TIMEOUT_MS 300000L +/* declare as module param controled by cmdline parameter + * this value makes force ramdump even mdm gives silent reset + * usage : add cmdline ' mdm_common.force_dump=1 ' + */ +static int force_dump; +module_param(force_dump, int, S_IRUGO | S_IWUSR); static int mdm_debug_on; static struct workqueue_struct *mdm_queue; +static struct workqueue_struct *mdm_sfr_queue; +static unsigned int dump_timeout_ms; #define EXTERNAL_MODEM "external_modem" static struct mdm_modem_drv *mdm_drv; +static unsigned char *mdm_read_err_report(void); +static void mdm_disable_irqs(void); + DECLARE_COMPLETION(mdm_needs_reload); DECLARE_COMPLETION(mdm_boot); DECLARE_COMPLETION(mdm_ram_dumps); static int first_boot = 1; +#define RD_BUF_SIZE 100 +#define SFR_MAX_RETRIES 10 +#define SFR_RETRY_INTERVAL 1000 + +#ifndef CONFIG_ARCH_EXYNOS +static irqreturn_t mdm_vddmin_change(int irq, void *dev_id) +{ + int value = gpio_get_value( + mdm_drv->pdata->vddmin_resource->mdm2ap_vddmin_gpio); + + if (value == 0) + pr_info("External Modem entered Vddmin\n"); + else + pr_info("External Modem exited Vddmin\n"); + + return IRQ_HANDLED; +} +#endif + +static void mdm_setup_vddmin_gpios(void) +{ +#ifdef CONFIG_ARCH_EXYNOS + return; +#else + struct msm_rpm_iv_pair req; + struct mdm_vddmin_resource *vddmin_res; + int irq, ret; + + /* This resource may not be supported by some platforms. */ + vddmin_res = mdm_drv->pdata->vddmin_resource; + if (!vddmin_res) + return; + + req.id = vddmin_res->rpm_id; + req.value = ((uint32_t)vddmin_res->ap2mdm_vddmin_gpio & 0x0000FFFF) + << 16; + req.value |= ((uint32_t)vddmin_res->modes & 0x000000FF) << 8; + req.value |= (uint32_t)vddmin_res->drive_strength & 0x000000FF; + + msm_rpm_set(MSM_RPM_CTX_SET_0, &req, 1); + + /* Monitor low power gpio from mdm */ + irq = MSM_GPIO_TO_INT(vddmin_res->mdm2ap_vddmin_gpio); + if (irq < 0) { + pr_err("%s: could not get LPM POWER IRQ resource.\n", + __func__); + goto error_end; + } + + ret = request_threaded_irq(irq, NULL, mdm_vddmin_change, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "mdm lpm", NULL); + + if (ret < 0) + pr_err("%s: MDM LPM IRQ#%d request failed with error=%d", + __func__, irq, ret); +error_end: + return; +#endif +} + +static void mdm_restart_reason_fn(struct work_struct *work) +{ +#ifndef CONFIG_ARCH_EXYNOS + int ret, ntries = 0; + char sfr_buf[RD_BUF_SIZE]; + do { + msleep(SFR_RETRY_INTERVAL); + ret = sysmon_get_reason(SYSMON_SS_EXT_MODEM, + sfr_buf, sizeof(sfr_buf)); + if (ret) { + /* + * The sysmon device may not have been probed as yet + * after the restart. + */ + pr_err("%s: Error retrieving mdm restart reason, ret = %d, " + "%d/%d tries\n", __func__, ret, + ntries + 1, SFR_MAX_RETRIES); + } else { + pr_err("mdm restart reason: %s\n", sfr_buf); + break; + } + } while (++ntries < SFR_MAX_RETRIES); +#endif +} + +static DECLARE_WORK(sfr_reason_work, mdm_restart_reason_fn); + +void mdm_set_chip_configuration(bool dload) +{ + if (mdm_drv) { + pr_info("mdm9x15 boot protocol = %s\n", + dload ? "DLOAD" : "SAHARA"); + mdm_drv->proto_is_dload = dload; + } +} + +static void mdm2ap_status_check(struct work_struct *work) +{ + /* + * If the mdm modem did not pull the MDM2AP_STATUS gpio + * high then call subsystem_restart. + */ + if (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0) { + pr_err("%s: MDM2AP_STATUS gpio did not go high\n", + __func__); + mdm_drv->mdm_ready = 0; + notify_modem_fatal(); + subsystem_restart(EXTERNAL_MODEM); + } +} + +static DECLARE_DELAYED_WORK(mdm2ap_status_check_work, mdm2ap_status_check); + long mdm_modem_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { @@ -81,6 +212,9 @@ long mdm_modem_ioctl(struct file *filp, unsigned int cmd, switch (cmd) { case WAKE_CHARM: pr_info("%s: Powering on mdm\n", __func__); +#ifdef CONFIG_MDM_HSIC_PM + request_boot_lock_set(rmnet_pm_dev); +#endif mdm_drv->ops->power_on_mdm_cb(mdm_drv); break; case CHECK_FOR_BOOT: @@ -108,6 +242,13 @@ long mdm_modem_ioctl(struct file *filp, unsigned int cmd, complete(&mdm_boot); else first_boot = 0; + + /* If bootup succeeded, start a timer to check that the + * mdm2ap_status gpio goes high. + */ + if (!status && gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0) + schedule_delayed_work(&mdm2ap_status_check_work, + msecs_to_jiffies(MDM2AP_STATUS_TIMEOUT_MS)); break; case RAM_DUMP_DONE: pr_info("%s: mdm done collecting RAM dumps\n", __func__); @@ -117,9 +258,19 @@ long mdm_modem_ioctl(struct file *filp, unsigned int cmd, else { pr_info("%s: ramdump collection completed\n", __func__); mdm_drv->mdm_ram_dump_status = 0; + panic("CP Crash %s", mdm_read_err_report()); } complete(&mdm_ram_dumps); break; + + case WAIT_FOR_ERROR: + pr_debug("%s: wait for mdm error\n", __func__); + #if 0 + ret = wait_for_completion_interruptible(&mdm_error); + INIT_COMPLETION(mdm_error); + #endif + break; + case WAIT_FOR_RESTART: pr_info("%s: wait for mdm to need images reloaded\n", __func__); @@ -129,6 +280,29 @@ long mdm_modem_ioctl(struct file *filp, unsigned int cmd, (unsigned long __user *) arg); INIT_COMPLETION(mdm_needs_reload); break; + + case SILENT_RESET_CONTROL: + pr_info("%s: mdm doing silent reset\n", __func__); + mdm_drv->mdm_ram_dump_status = 0; + complete(&mdm_ram_dumps); + break; + + case AUTOPM_LOCK: + get_user(status, (unsigned long __user *) arg); + pr_info("%s: mdm autopm request[%s]\n", __func__, + status ? "lock" : "release"); + request_autopm_lock(status); + break; + + case GET_BOOT_PROTOCOL: + pr_info("%s: mdm get boot protocol %d\n", __func__, + mdm_drv->proto_is_dload); + return mdm_drv->proto_is_dload; + + case GET_FORCE_RAMDUMP: + pr_info("%s: mdm get dump mode = %d\n", __func__, force_dump); + return force_dump; + default: pr_err("%s: invalid ioctl cmd = %d\n", __func__, _IOC_NR(cmd)); ret = -EINVAL; @@ -138,9 +312,23 @@ long mdm_modem_ioctl(struct file *filp, unsigned int cmd, return ret; } +/* temporary implemented, it should be removed at mass production */ +/* simply declare this function as extern at test point, and call it */ +void mdm_force_fatal(void) +{ + pr_info("%s: Reseting the mdm due to AP request\n", __func__); + + force_dump = 1; + + notify_modem_fatal(); + subsystem_restart(EXTERNAL_MODEM); +} +EXPORT_SYMBOL(mdm_force_fatal); + static void mdm_fatal_fn(struct work_struct *work) { pr_info("%s: Reseting the mdm due to an errfatal\n", __func__); + notify_modem_fatal(); subsystem_restart(EXTERNAL_MODEM); } @@ -150,19 +338,15 @@ static void mdm_status_fn(struct work_struct *work) { int value = gpio_get_value(mdm_drv->mdm2ap_status_gpio); - if (!mdm_drv->mdm_ready) - return; - - mdm_drv->ops->status_cb(mdm_drv, value); - - pr_err("%s: status:%d\n", __func__, value); - - if ((value == 0)) { - pr_info("%s: unexpected reset external modem\n", __func__); - subsystem_restart(EXTERNAL_MODEM); - } else if (value == 1) { - pr_info("%s: status = 1: mdm is now ready\n", __func__); + pr_debug("%s: status:%d\n", __func__, value); + if (mdm_drv->mdm_ready && mdm_drv->ops->status_cb) + mdm_drv->ops->status_cb(mdm_drv, value); +#ifdef CONFIG_MDM_HSIC_PM + if (value) { + request_boot_lock_release(rmnet_pm_dev); + request_active_lock_set(rmnet_pm_dev); } +#endif } static DECLARE_WORK(mdm_status_work, mdm_status_fn); @@ -171,7 +355,6 @@ static void mdm_disable_irqs(void) { disable_irq_nosync(mdm_drv->mdm_errfatal_irq); disable_irq_nosync(mdm_drv->mdm_status_irq); - } static irqreturn_t mdm_errfatal(int irq, void *dev_id) @@ -179,12 +362,35 @@ static irqreturn_t mdm_errfatal(int irq, void *dev_id) pr_debug("%s: mdm got errfatal interrupt\n", __func__); if (mdm_drv->mdm_ready && (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 1)) { - pr_debug("%s: scheduling work now\n", __func__); + pr_info("%s: Reseting the mdm due to an errfatal\n", __func__); + mdm_drv->mdm_ready = 0; + /* subsystem_restart(EXTERNAL_MODEM); */ queue_work(mdm_queue, &mdm_fatal_work); } return IRQ_HANDLED; } +static unsigned char *mdm_read_err_report(void) +{ + /* Read CP error report from mdm_err.log in tombstones */ + static unsigned char buf[1000] = { 0, }; + struct file *filp; + mm_segment_t old_fs = get_fs(); + set_fs(KERNEL_DS); + do { + filp = filp_open("/tombstones/mdm/mdm_err.log", \ + O_RDWR, S_IRUSR|S_IWUSR); + if (IS_ERR(filp)) { + set_fs(old_fs); + return (unsigned char *) buf; + } + vfs_read(filp, buf, 1000, &filp->f_pos); + filp_close(filp, NULL); + set_fs(old_fs); + } while (0); + return (unsigned char *) buf; +} + static int mdm_modem_open(struct inode *inode, struct file *file) { return 0; @@ -219,21 +425,66 @@ static int mdm_panic_prep(struct notifier_block *this, if (gpio_get_value(mdm_drv->mdm2ap_status_gpio) == 0) break; } - if (i <= 0) + if (i <= 0) { pr_err("%s: MDM2AP_STATUS never went low\n", __func__); + /* Reset the modem so that it will go into download mode. */ + if (mdm_drv && mdm_drv->ops->reset_mdm_cb) + mdm_drv->ops->reset_mdm_cb(mdm_drv); + } return NOTIFY_DONE; } static struct notifier_block mdm_panic_blk = { .notifier_call = mdm_panic_prep, + .priority = 1, +}; + +static int mdm_reboot_notifier(struct notifier_block *this, + unsigned long event, void *ptr) +{ + int soft_reset_direction = + mdm_drv->pdata->soft_reset_inverted ? 1 : 0; + mdm_disable_irqs(); + notify_modem_fatal(); + gpio_direction_output(mdm_drv->ap2mdm_soft_reset_gpio, + soft_reset_direction); + if (mdm_drv->ap2mdm_pmic_pwr_en_gpio > 0) + gpio_direction_output(mdm_drv->ap2mdm_pmic_pwr_en_gpio, 0); + + /* give modem PMIC debounce time, spec is ~3.5 but 1s will be enough */ + msleep(1500); + + return NOTIFY_DONE; +} + +static struct notifier_block mdm_down_block = { + .notifier_call = mdm_reboot_notifier, + .priority = 1, }; static irqreturn_t mdm_status_change(int irq, void *dev_id) { int value = gpio_get_value(mdm_drv->mdm2ap_status_gpio); - pr_err("%s: mdm sent status change interrupt : %d\n", __func__, value); - queue_work(mdm_queue, &mdm_status_work); + pr_debug("%s: mdm sent status change interrupt\n", __func__); + if (value == 0 && mdm_drv->mdm_ready == 1) { + pr_info("%s: unexpected reset external modem\n", __func__); + mdm_drv->mdm_unexpected_reset_occurred = 1; + mdm_drv->mdm_ready = 0; + notify_modem_fatal(); + subsystem_restart(EXTERNAL_MODEM); + } else if (value == 1) { + cancel_delayed_work(&mdm2ap_status_check_work); + pr_info("%s: status = 1: mdm is now ready\n", __func__); + queue_work(mdm_queue, &mdm_status_work); + } + return IRQ_HANDLED; +} + +static irqreturn_t mdm_pblrdy_change(int irq, void *dev_id) +{ + pr_info("%s: pbl ready:%d\n", __func__, + gpio_get_value(mdm_drv->mdm2ap_pblrdy)); return IRQ_HANDLED; } @@ -241,7 +492,7 @@ static irqreturn_t mdm_status_change(int irq, void *dev_id) static int mdm_subsys_shutdown(const struct subsys_data *crashed_subsys) { pr_info("%s\n", __func__); - mdm_drv->mdm_ready = 0; + gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 1); if (mdm_drv->pdata->ramdump_delay_ms > 0) { /* Wait for the external modem to complete @@ -249,7 +500,13 @@ static int mdm_subsys_shutdown(const struct subsys_data *crashed_subsys) */ msleep(mdm_drv->pdata->ramdump_delay_ms); } - mdm_drv->ops->power_down_mdm_cb(mdm_drv); + #if 0 + if (!mdm_drv->mdm_unexpected_reset_occurred) + mdm_drv->ops->reset_mdm_cb(mdm_drv); + else + mdm_drv->mdm_unexpected_reset_occurred = 0; + + #endif return 0; } @@ -257,7 +514,7 @@ static int mdm_subsys_powerup(const struct subsys_data *crashed_subsys) { pr_info("%s\n", __func__); gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 0); - gpio_direction_output(mdm_drv->ap2mdm_status_gpio, 1); + gpio_direction_output(mdm_drv->ap2mdm_status_gpio, 0); mdm_drv->ops->power_on_mdm_cb(mdm_drv); mdm_drv->boot_type = CHARM_NORMAL_BOOT; complete(&mdm_needs_reload); @@ -265,8 +522,13 @@ static int mdm_subsys_powerup(const struct subsys_data *crashed_subsys) msecs_to_jiffies(MDM_BOOT_TIMEOUT))) { mdm_drv->mdm_boot_status = -ETIMEDOUT; pr_info("%s: mdm modem restart timed out.\n", __func__); - } else + } else { pr_info("%s: mdm modem has been restarted\n", __func__); + + /* Log the reason for the restart */ + if (mdm_drv->pdata->sfr_query) + queue_work(mdm_sfr_queue, &sfr_reason_work); + } INIT_COMPLETION(mdm_boot); return mdm_drv->mdm_boot_status; } @@ -274,22 +536,25 @@ static int mdm_subsys_powerup(const struct subsys_data *crashed_subsys) static int mdm_subsys_ramdumps(int want_dumps, const struct subsys_data *crashed_subsys) { - pr_info("%s\n", __func__); + pr_info("%s(dump = %d)\n", __func__, want_dumps); mdm_drv->mdm_ram_dump_status = 0; if (want_dumps) { mdm_drv->boot_type = CHARM_RAM_DUMPS; complete(&mdm_needs_reload); + pr_info("%s: waiting ramdump ...\n", __func__); if (!wait_for_completion_timeout(&mdm_ram_dumps, - msecs_to_jiffies(MDM_RDUMP_TIMEOUT))) { + msecs_to_jiffies(dump_timeout_ms))) { mdm_drv->mdm_ram_dump_status = -ETIMEDOUT; pr_info("%s: mdm modem ramdumps timed out.\n", __func__); - } else + } else { pr_info("%s: mdm modem ramdumps completed.\n", __func__); + mdm_drv->mdm_ram_dump_status = 0; + } INIT_COMPLETION(mdm_ram_dumps); - gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 1); - mdm_drv->ops->power_down_mdm_cb(mdm_drv); + if (!mdm_drv->pdata->no_powerdown_after_ramdumps) + mdm_drv->ops->power_down_mdm_cb(mdm_drv); } return mdm_drv->mdm_ram_dump_status; } @@ -319,6 +584,7 @@ DEFINE_SIMPLE_ATTRIBUTE(mdm_debug_on_fops, mdm_debug_on_get, mdm_debug_on_set, "%llu\n"); +#ifndef CONFIG_ARCH_EXYNOS static int mdm_debugfs_init(void) { struct dentry *dent; @@ -331,6 +597,8 @@ static int mdm_debugfs_init(void) &mdm_debug_on_fops); return 0; } +#endif + static void mdm_modem_initialize_data(struct platform_device *pdev, struct mdm_ops *mdm_ops) @@ -373,11 +641,11 @@ static void mdm_modem_initialize_data(struct platform_device *pdev, if (pres) mdm_drv->ap2mdm_wakeup_gpio = pres->start; - /* AP2MDM_PMIC_RESET_N */ + /* AP2MDM_SOFT_RESET */ pres = platform_get_resource_byname(pdev, IORESOURCE_IO, - "AP2MDM_PMIC_RESET_N"); + "AP2MDM_SOFT_RESET"); if (pres) - mdm_drv->ap2mdm_pmic_reset_n_gpio = pres->start; + mdm_drv->ap2mdm_soft_reset_gpio = pres->start; /* AP2MDM_KPDPWR_N */ pres = platform_get_resource_byname(pdev, IORESOURCE_IO, @@ -385,10 +653,24 @@ static void mdm_modem_initialize_data(struct platform_device *pdev, if (pres) mdm_drv->ap2mdm_kpdpwr_n_gpio = pres->start; + /* AP2MDM_PMIC_PWR_EN */ + pres = platform_get_resource_byname(pdev, IORESOURCE_IO, + "AP2MDM_PMIC_PWR_EN"); + if (pres) + mdm_drv->ap2mdm_pmic_pwr_en_gpio = pres->start; + + /* MDM2AP_PBLRDY */ + pres = platform_get_resource_byname(pdev, IORESOURCE_IO, + "MDM2AP_PBLRDY"); + if (pres) + mdm_drv->mdm2ap_pblrdy = pres->start; + mdm_drv->boot_type = CHARM_NORMAL_BOOT; mdm_drv->ops = mdm_ops; mdm_drv->pdata = pdev->dev.platform_data; + dump_timeout_ms = mdm_drv->pdata->ramdump_timeout_ms > 0 ? + mdm_drv->pdata->ramdump_timeout_ms : MDM_RDUMP_TIMEOUT; } int mdm_common_create(struct platform_device *pdev, @@ -409,31 +691,52 @@ int mdm_common_create(struct platform_device *pdev, gpio_request(mdm_drv->ap2mdm_status_gpio, "AP2MDM_STATUS"); gpio_request(mdm_drv->ap2mdm_errfatal_gpio, "AP2MDM_ERRFATAL"); - gpio_request(mdm_drv->ap2mdm_kpdpwr_n_gpio, "AP2MDM_KPDPWR_N"); - gpio_request(mdm_drv->ap2mdm_pmic_reset_n_gpio, "AP2MDM_PMIC_RESET_N"); + if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0) + gpio_request(mdm_drv->ap2mdm_kpdpwr_n_gpio, "AP2MDM_KPDPWR_N"); gpio_request(mdm_drv->mdm2ap_status_gpio, "MDM2AP_STATUS"); gpio_request(mdm_drv->mdm2ap_errfatal_gpio, "MDM2AP_ERRFATAL"); + if (mdm_drv->mdm2ap_pblrdy > 0) + gpio_request(mdm_drv->mdm2ap_pblrdy, "MDM2AP_PBLRDY"); - if (mdm_drv->ap2mdm_wakeup_gpio > 0) + if (mdm_drv->ap2mdm_pmic_pwr_en_gpio > 0) { + gpio_request(mdm_drv->ap2mdm_pmic_pwr_en_gpio, + "AP2MDM_PMIC_PWR_EN"); + gpio_set_value(mdm_drv->ap2mdm_pmic_pwr_en_gpio, 0); +#ifdef CONFIG_ARCH_EXYNOS + s3c_gpio_cfgpin(mdm_drv->ap2mdm_pmic_pwr_en_gpio, + S3C_GPIO_OUTPUT); + s3c_gpio_setpull(mdm_drv->ap2mdm_pmic_pwr_en_gpio, + S3C_GPIO_PULL_UP); + s5p_gpio_set_drvstr(mdm_drv->ap2mdm_pmic_pwr_en_gpio, + S5P_GPIO_DRVSTR_LV4); +#endif + } + if (mdm_drv->ap2mdm_soft_reset_gpio > 0) { + gpio_request(mdm_drv->ap2mdm_soft_reset_gpio, + "AP2MDM_SOFT_RESET"); + gpio_set_value(mdm_drv->ap2mdm_soft_reset_gpio, 0); +#ifdef CONFIG_ARCH_EXYNOS + s3c_gpio_cfgpin(mdm_drv->ap2mdm_soft_reset_gpio, + S3C_GPIO_OUTPUT); + s3c_gpio_setpull(mdm_drv->ap2mdm_soft_reset_gpio, + S3C_GPIO_PULL_UP); +#endif + } + if (mdm_drv->ap2mdm_wakeup_gpio > 0) { gpio_request(mdm_drv->ap2mdm_wakeup_gpio, "AP2MDM_WAKEUP"); - + gpio_set_value(mdm_drv->ap2mdm_wakeup_gpio, 0); #ifdef CONFIG_ARCH_EXYNOS - gpio_set_value(mdm_drv->ap2mdm_status_gpio, 1); - s3c_gpio_cfgpin(mdm_drv->ap2mdm_status_gpio, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(mdm_drv->ap2mdm_status_gpio, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(mdm_drv->ap2mdm_wakeup_gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(mdm_drv->ap2mdm_wakeup_gpio, + S3C_GPIO_PULL_NONE); #endif - gpio_direction_output(mdm_drv->ap2mdm_status_gpio, 1); - pr_err("%s> : right after ap2mdm_status = %d\n", __func__, - gpio_get_value(mdm_drv->ap2mdm_status_gpio)); + } + gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 0); #ifdef CONFIG_ARCH_EXYNOS - gpio_set_value(mdm_drv->ap2mdm_errfatal_gpio, 0); s3c_gpio_cfgpin(mdm_drv->ap2mdm_errfatal_gpio, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(mdm_drv->ap2mdm_errfatal_gpio, S3C_GPIO_PULL_DOWN); + s3c_gpio_setpull(mdm_drv->ap2mdm_errfatal_gpio, S3C_GPIO_PULL_NONE); #endif - gpio_direction_output(mdm_drv->ap2mdm_errfatal_gpio, 0); - pr_err("%s>> : right after ap2mdm_status = %d\n", __func__, - gpio_get_value(mdm_drv->ap2mdm_status_gpio)); if (mdm_drv->ap2mdm_wakeup_gpio > 0) gpio_direction_output(mdm_drv->ap2mdm_wakeup_gpio, 0); @@ -450,8 +753,24 @@ int mdm_common_create(struct platform_device *pdev, goto fatal_err; } +#ifndef CONFIG_ARCH_EXYNOS + mdm_sfr_queue = alloc_workqueue("mdm_sfr_queue", 0, 0); + if (!mdm_sfr_queue) { + pr_err("%s: could not create workqueue mdm_sfr_queue." + " All mdm functionality will be disabled\n", + __func__); + ret = -ENOMEM; + destroy_workqueue(mdm_queue); + goto fatal_err; + } +#endif + atomic_notifier_chain_register(&panic_notifier_list, &mdm_panic_blk); + register_reboot_notifier(&mdm_down_block); + +#ifndef CONFIG_ARCH_EXYNOS mdm_debugfs_init(); +#endif /* Register subsystem handlers */ ssr_register_subsystem(&mdm_subsystem); @@ -459,6 +778,8 @@ int mdm_common_create(struct platform_device *pdev, /* ERR_FATAL irq. */ #ifdef CONFIG_ARCH_EXYNOS irq = gpio_to_irq(mdm_drv->mdm2ap_errfatal_gpio); + s3c_gpio_cfgpin(mdm_drv->mdm2ap_errfatal_gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(mdm_drv->mdm2ap_errfatal_gpio, S3C_GPIO_PULL_NONE); #else irq = MSM_GPIO_TO_INT(mdm_drv->mdm2ap_errfatal_gpio); #endif @@ -478,14 +799,13 @@ int mdm_common_create(struct platform_device *pdev, goto errfatal_err; } mdm_drv->mdm_errfatal_irq = irq; + enable_irq_wake(irq); errfatal_err: - /* status irq */ #ifdef CONFIG_ARCH_EXYNOS - ret = s5p_register_gpio_interrupt(mdm_drv->mdm2ap_status_gpio); - if (ret) - pr_err("%s: register MDM2AP_STATUS ret = %d\n", __func__, ret); + s3c_gpio_cfgpin(mdm_drv->mdm2ap_status_gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(mdm_drv->mdm2ap_status_gpio, S3C_GPIO_PULL_NONE); irq = gpio_to_irq(mdm_drv->mdm2ap_status_gpio); #else irq = MSM_GPIO_TO_INT(mdm_drv->mdm2ap_status_gpio); @@ -508,14 +828,50 @@ errfatal_err: goto status_err; } mdm_drv->mdm_status_irq = irq; + enable_irq_wake(irq); status_err: + if (mdm_drv->mdm2ap_pblrdy > 0) { +#ifdef CONFIG_ARCH_EXYNOS + s3c_gpio_cfgpin(mdm_drv->mdm2ap_pblrdy, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(mdm_drv->mdm2ap_pblrdy, S3C_GPIO_PULL_NONE); + irq = gpio_to_irq(mdm_drv->mdm2ap_pblrdy); +#else + irq = MSM_GPIO_TO_INT(mdm_drv->mdm2ap_pblrdy); +#endif + if (irq < 0) { + pr_err("%s: could not get MDM2AP_PBLRDY IRQ resource", + __func__); + goto pblrdy_err; + } + + ret = request_threaded_irq(irq, NULL, mdm_pblrdy_change, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_SHARED, + "mdm pbl ready", mdm_drv); + + if (ret < 0) { + pr_err("%s: MDM2AP_PBL IRQ#%d request failed error=%d", + __func__, irq, ret); + goto pblrdy_err; + } + } + +pblrdy_err: + /* + * If AP2MDM_PMIC_PWR_EN gpio is used, pull it high. It remains + * high until the whole phone is shut down. + */ + if (mdm_drv->ap2mdm_pmic_pwr_en_gpio > 0) + gpio_direction_output(mdm_drv->ap2mdm_pmic_pwr_en_gpio, 1); + /* Register VDDmin gpios with RPM */ + mdm_setup_vddmin_gpios(); + /* Perform early powerup of the external modem in order to * allow tabla devices to be found. */ - mdm_drv->ops->power_on_mdm_cb(mdm_drv); - pr_err("%s : ap2mdm_status = %d\n", __func__, - gpio_get_value(mdm_drv->ap2mdm_status_gpio)); + if (mdm_drv->pdata->early_power_on) + mdm_drv->ops->power_on_mdm_cb(mdm_drv); pr_info("%s: Registering mdm modem\n", __func__); return misc_register(&mdm_modem_misc); @@ -523,10 +879,14 @@ status_err: fatal_err: gpio_free(mdm_drv->ap2mdm_status_gpio); gpio_free(mdm_drv->ap2mdm_errfatal_gpio); - gpio_free(mdm_drv->ap2mdm_kpdpwr_n_gpio); - gpio_free(mdm_drv->ap2mdm_pmic_reset_n_gpio); + if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0) + gpio_free(mdm_drv->ap2mdm_kpdpwr_n_gpio); + if (mdm_drv->ap2mdm_pmic_pwr_en_gpio > 0) + gpio_free(mdm_drv->ap2mdm_pmic_pwr_en_gpio); gpio_free(mdm_drv->mdm2ap_status_gpio); gpio_free(mdm_drv->mdm2ap_errfatal_gpio); + if (mdm_drv->ap2mdm_soft_reset_gpio > 0) + gpio_free(mdm_drv->ap2mdm_soft_reset_gpio); if (mdm_drv->ap2mdm_wakeup_gpio > 0) gpio_free(mdm_drv->ap2mdm_wakeup_gpio); @@ -544,10 +904,14 @@ int mdm_common_modem_remove(struct platform_device *pdev) gpio_free(mdm_drv->ap2mdm_status_gpio); gpio_free(mdm_drv->ap2mdm_errfatal_gpio); - gpio_free(mdm_drv->ap2mdm_kpdpwr_n_gpio); - gpio_free(mdm_drv->ap2mdm_pmic_reset_n_gpio); + if (mdm_drv->ap2mdm_kpdpwr_n_gpio > 0) + gpio_free(mdm_drv->ap2mdm_kpdpwr_n_gpio); + if (mdm_drv->ap2mdm_pmic_pwr_en_gpio > 0) + gpio_free(mdm_drv->ap2mdm_pmic_pwr_en_gpio); gpio_free(mdm_drv->mdm2ap_status_gpio); gpio_free(mdm_drv->mdm2ap_errfatal_gpio); + if (mdm_drv->ap2mdm_soft_reset_gpio > 0) + gpio_free(mdm_drv->ap2mdm_soft_reset_gpio); if (mdm_drv->ap2mdm_wakeup_gpio > 0) gpio_free(mdm_drv->ap2mdm_wakeup_gpio); @@ -563,5 +927,6 @@ void mdm_common_modem_shutdown(struct platform_device *pdev) mdm_disable_irqs(); mdm_drv->ops->power_down_mdm_cb(mdm_drv); + if (mdm_drv->ap2mdm_pmic_pwr_en_gpio > 0) + gpio_direction_output(mdm_drv->ap2mdm_pmic_pwr_en_gpio, 0); } - diff --git a/arch/arm/mach-exynos/mdm_device.c b/arch/arm/mach-exynos/mdm_device.c index 22be1d5..f5af03c 100644 --- a/arch/arm/mach-exynos/mdm_device.c +++ b/arch/arm/mach-exynos/mdm_device.c @@ -9,45 +9,181 @@ #include <mach/mdm2.h> #include "mdm_private.h" +#include <linux/cpufreq_pegasusq.h> +#include <mach/cpufreq.h> +#include <mach/dev.h> + static struct resource mdm_resources[] = { { - .start = MDM2AP_ERRFATAL, - .end = MDM2AP_ERRFATAL, + .start = GPIO_MDM2AP_ERR_FATAL, + .end = GPIO_MDM2AP_ERR_FATAL, .name = "MDM2AP_ERRFATAL", .flags = IORESOURCE_IO, }, { - .start = AP2MDM_ERRFATAL, - .end = AP2MDM_ERRFATAL, + .start = GPIO_AP2MDM_ERR_FATAL, + .end = GPIO_AP2MDM_ERR_FATAL, .name = "AP2MDM_ERRFATAL", .flags = IORESOURCE_IO, }, { - .start = MDM2AP_STATUS, - .end = MDM2AP_STATUS, + .start = GPIO_MDM2AP_STATUS, + .end = GPIO_MDM2AP_STATUS, .name = "MDM2AP_STATUS", .flags = IORESOURCE_IO, }, { - .start = AP2MDM_STATUS, - .end = AP2MDM_STATUS, + .start = GPIO_AP2MDM_STATUS, + .end = GPIO_AP2MDM_STATUS, .name = "AP2MDM_STATUS", .flags = IORESOURCE_IO, }, { - .start = AP2MDM_PMIC_RESET_N, - .end = AP2MDM_PMIC_RESET_N, - .name = "AP2MDM_PMIC_RESET_N", + .start = GPIO_AP2MDM_PON_RESET_N, + .end = GPIO_AP2MDM_PON_RESET_N, + .name = "AP2MDM_SOFT_RESET", + .flags = IORESOURCE_IO, + }, + { + .start = GPIO_AP2MDM_PMIC_RESET_N, + .end = GPIO_AP2MDM_PMIC_RESET_N, + .name = "AP2MDM_PMIC_PWR_EN", .flags = IORESOURCE_IO, }, + { + .start = GPIO_AP2MDM_WAKEUP, + .end = GPIO_AP2MDM_WAKEUP, + .name = "AP2MDM_WAKEUP", + .flags = IORESOURCE_IO, + }, +}; + +#ifdef CONFIG_MDM_HSIC_PM +static struct resource mdm_pm_resource[] = { + { + .start = GPIO_AP2MDM_HSIC_PORT_ACTIVE, + .end = GPIO_AP2MDM_HSIC_PORT_ACTIVE, + .name = "AP2MDM_HSIC_ACTIVE", + .flags = IORESOURCE_IO, + }, + { + .start = GPIO_MDM2AP_HSIC_PWR_ACTIVE, + .end = GPIO_MDM2AP_HSIC_PWR_ACTIVE, + .name = "MDM2AP_DEVICE_PWR_ACTIVE", + .flags = IORESOURCE_IO, + }, + { + .start = GPIO_MDM2AP_HSIC_RESUME_REQ, + .end = GPIO_MDM2AP_HSIC_RESUME_REQ, + .name = "MDM2AP_RESUME_REQ", + .flags = IORESOURCE_IO, + }, +}; + +static int exynos_frequency_lock(struct device *dev); +static int exynos_frequency_unlock(struct device *dev); + +static struct mdm_hsic_pm_platform_data mdm_hsic_pm_pdata = { + .freqlock = ATOMIC_INIT(0), + .freq_lock = exynos_frequency_lock, + .freq_unlock = exynos_frequency_unlock, }; +struct platform_device mdm_pm_device = { + .name = "mdm_hsic_pm0", + .id = -1, + .num_resources = ARRAY_SIZE(mdm_pm_resource), + .resource = mdm_pm_resource, +}; +#endif + static struct mdm_platform_data mdm_platform_data = { .mdm_version = "3.0", .ramdump_delay_ms = 2000, - .peripheral_platform_device = &s5p_device_ehci, + .early_power_on = 1, + .sfr_query = 0, + .vddmin_resource = NULL, +#ifdef CONFIG_USB_EHCI_S5P + .peripheral_platform_device_ehci = &s5p_device_ehci, +#endif +#ifdef CONFIG_USB_OHCI_S5P + .peripheral_platform_device_ohci = &s5p_device_ohci, +#endif + .ramdump_timeout_ms = 120000, }; +static int exynos_frequency_lock(struct device *dev) +{ + unsigned int level, cpufreq = 1400; /* 200 ~ 1400 */ + unsigned int busfreq = 400200; /* 100100 ~ 400200 */ + int ret = 0; + struct device *busdev = dev_get("exynos-busfreq"); + + if (atomic_read(&mdm_hsic_pm_pdata.freqlock) == 0) { + /* cpu frequency lock */ + ret = exynos_cpufreq_get_level(cpufreq * 1000, &level); + if (ret < 0) { + pr_err("ERR: exynos_cpufreq_get_level fail: %d\n", + ret); + goto exit; + } + + ret = exynos_cpufreq_lock(DVFS_LOCK_ID_USB_IF, level); + if (ret < 0) { + pr_err("ERR: exynos_cpufreq_lock fail: %d\n", ret); + goto exit; + } + + /* bus frequncy lock */ + if (!busdev) { + pr_err("ERR: busdev is not exist\n"); + ret = -ENODEV; + goto exit; + } + + ret = dev_lock(busdev, dev, busfreq); + if (ret < 0) { + pr_err("ERR: dev_lock error: %d\n", ret); + goto exit; + } + + /* lock minimum number of cpu cores */ + cpufreq_pegasusq_min_cpu_lock(2); + + atomic_set(&mdm_hsic_pm_pdata.freqlock, 1); + pr_debug("level=%d, cpufreq=%d MHz, busfreq=%06d\n", + level, cpufreq, busfreq); + } +exit: + return ret; +} + +static int exynos_frequency_unlock(struct device *dev) +{ + int ret = 0; + struct device *busdev = dev_get("exynos-busfreq"); + + if (atomic_read(&mdm_hsic_pm_pdata.freqlock) == 1) { + /* cpu frequency unlock */ + exynos_cpufreq_lock_free(DVFS_LOCK_ID_USB_IF); + + /* bus frequency unlock */ + ret = dev_unlock(busdev, dev); + if (ret < 0) { + pr_err("ERR: dev_unlock error: %d\n", ret); + goto exit; + } + + /* unlock minimum number of cpu cores */ + cpufreq_pegasusq_min_cpu_unlock(); + + atomic_set(&mdm_hsic_pm_pdata.freqlock, 0); + pr_debug("success\n"); + } +exit: + return ret; +} + struct platform_device mdm_device = { .name = "mdm2_modem", .id = -1, @@ -57,8 +193,28 @@ struct platform_device mdm_device = { static int __init init_mdm_modem(void) { - pr_err("%s !!! !!\n", __func__); + int ret; + pr_info("%s: registering modem dev, pm dev\n", __func__); + + mdm_pm_device.dev.platform_data = &mdm_hsic_pm_pdata; + ((struct mdm_hsic_pm_platform_data *) + mdm_pm_device.dev.platform_data)->dev = + &mdm_pm_device.dev; +#ifdef CONFIG_MDM_HSIC_PM + ret = platform_device_register(&mdm_pm_device); + if (ret < 0) { + pr_err("%s: fail to register mdm hsic pm dev(err:%d)\n", + __func__, ret); + return ret; + } +#endif mdm_device.dev.platform_data = &mdm_platform_data; - return platform_device_register(&mdm_device); + ret = platform_device_register(&mdm_device); + if (ret < 0) { + pr_err("%s: fail to register mdm modem dev(err:%d)\n", + __func__, ret); + return ret; + } + return 0; } module_init(init_mdm_modem); diff --git a/arch/arm/mach-exynos/mdm_hsic_pm.c b/arch/arm/mach-exynos/mdm_hsic_pm.c new file mode 100644 index 0000000..7d8ee80 --- /dev/null +++ b/arch/arm/mach-exynos/mdm_hsic_pm.c @@ -0,0 +1,1048 @@ +/* linux/arch/arm/mach-xxxx/mdm_hsic_pm.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/usb.h> +#include <linux/pm_runtime.h> +#include <plat/gpio-cfg.h> +#include <linux/mdm_hsic_pm.h> +#include <linux/suspend.h> +#include <linux/wakelock.h> +#include <mach/subsystem_restart.h> +#include <mach/sec_modem.h> +#include <linux/msm_charm.h> +#include "mdm_private.h" +#include <linux/wakelock.h> +#include <linux/usb.h> +#include <linux/usb/hcd.h> +#include <linux/usb/ehci_def.h> + +#include <linux/kernel.h> +#include <linux/netdevice.h> +#include <mach/mdm2.h> +#include <linux/usb/android_composite.h> + +#define EXTERNAL_MODEM "external_modem" +#define EHCI_REG_DUMP +#define DEFAULT_RAW_WAKE_TIME (6*HZ) + +BLOCKING_NOTIFIER_HEAD(mdm_reset_notifier_list); + +/** + * TODO: + * pm notifier register + * + * think the way to use notifier to register or unregister device + * + * disconnect also can be notified + * + * block request under kernel power off seq. + * + * in suspend function if busy has set, return + * + */ + +/** + * struct mdm_hsic_pm_data - hsic pm platform driver private data + * provide data and information for pm state transition + * + * @name: name of this pm driver + * @udev: usb driver for resuming device from device request + * @intf_cnt: count of registered interface driver + * @block_request: block and ignore requested resume interrupt + * @state_busy: it is not determined to use, it can be replaced to + * rpm status check + * @pm_notifier: notifier block to control block_request variable + * block_reqeust set to true at PM_SUSPEND_PREPARE and + * release at PM_POST_RESUME + * + */ +struct mdm_hsic_pm_data { + struct list_head list; + char name[32]; + + struct usb_device *udev; + int intf_cnt; + + /* control variables */ + struct notifier_block pm_notifier; + struct notifier_block netdev_notifier; + struct notifier_block usb_composite_notifier; + + bool block_request; + bool state_busy; + atomic_t pmlock_cnt; + bool shutdown; + + /* gpio-s and irq */ + int gpio_host_ready; + int gpio_device_ready; + int gpio_host_wake; + int irq; + + /* wakelock for L0 - L2 */ + struct wake_lock l2_wake; + + /* wakelock for boot */ + struct wake_lock boot_wake; + + /* wakelock for fast dormancy */ + struct wake_lock fd_wake; + long fd_wake_time; /* wake time for raw packet in jiffies */ + + /* workqueue, work for delayed autosuspend */ + struct workqueue_struct *wq; + struct delayed_work auto_rpm_start_work; + struct delayed_work auto_rpm_restart_work; + struct delayed_work request_resume_work; + struct delayed_work fast_dormancy_work; + + struct mdm_hsic_pm_platform_data *mdm_pdata; +}; + +/* indicate wakeup from lpa state */ +bool lpa_handling; + +#ifdef EHCI_REG_DUMP +struct dump_ehci_regs { + unsigned caps_hc_capbase; + unsigned caps_hcs_params; + unsigned caps_hcc_params; + unsigned reserved0; + struct ehci_regs regs; + unsigned port_usb; /*0x54*/ + unsigned port_hsic0; + unsigned port_hsic1; + unsigned reserved[12]; + unsigned insnreg00; /*0x90*/ + unsigned insnreg01; + unsigned insnreg02; + unsigned insnreg03; + unsigned insnreg04; + unsigned insnreg05; + unsigned insnreg06; + unsigned insnreg07; +}; + +struct s5p_ehci_hcd_stub { + struct device *dev; + struct usb_hcd *hcd; + struct clk *clk; + int power_on; +}; +/* for EHCI register dump */ +struct dump_ehci_regs sec_debug_ehci_regs; + +#define pr_hcd(s, r) printk(KERN_DEBUG "hcd reg(%s):\t 0x%08x\n", s, r) +static void print_ehci_regs(struct dump_ehci_regs *base) +{ + pr_hcd("HCCPBASE", base->caps_hc_capbase); + pr_hcd("HCSPARAMS", base->caps_hcs_params); + pr_hcd("HCCPARAMS", base->caps_hcc_params); + pr_hcd("USBCMD", base->regs.command); + pr_hcd("USBSTS", base->regs.status); + pr_hcd("USBINTR", base->regs.intr_enable); + pr_hcd("FRINDEX", base->regs.frame_index); + pr_hcd("CTRLDSSEGMENT", base->regs.segment); + pr_hcd("PERIODICLISTBASE", base->regs.frame_list); + pr_hcd("ASYNCLISTADDR", base->regs.async_next); + pr_hcd("CONFIGFLAG", base->regs.configured_flag); + pr_hcd("PORT0 Status/Control", base->port_usb); + pr_hcd("PORT1 Status/Control", base->port_hsic0); + pr_hcd("PORT2 Status/Control", base->port_hsic1); + pr_hcd("INSNREG00", base->insnreg00); + pr_hcd("INSNREG01", base->insnreg01); + pr_hcd("INSNREG02", base->insnreg02); + pr_hcd("INSNREG03", base->insnreg03); + pr_hcd("INSNREG04", base->insnreg04); + pr_hcd("INSNREG05", base->insnreg05); + pr_hcd("INSNREG06", base->insnreg06); + pr_hcd("INSNREG07", base->insnreg07); +} + +void debug_ehci_reg_dump(struct device *hdev) +{ + struct s5p_ehci_hcd_stub *s5p_ehci = dev_get_drvdata(hdev); + struct usb_hcd *hcd = s5p_ehci->hcd; + char *buf = (char *)&sec_debug_ehci_regs; + pr_info("%s\n", __func__); + pr_info("EHCI %s, %s\n", dev_driver_string(hdev), dev_name(hdev)); + + print_ehci_regs(hcd->regs); + + memcpy(buf, hcd->regs, 0xB); + memcpy(buf + 0x10, hcd->regs + 0x10, 0x1F); + memcpy(buf + 0x50, hcd->regs + 0x50, 0xF); + memcpy(buf + 0x90, hcd->regs + 0x90, 0x1F); +} +#else +#define debug_ehci_reg_dump (NULL) +#endif + +/** + * hsic pm device list for multiple modem support + */ +static LIST_HEAD(hsic_pm_dev_list); + +static void print_pm_dev_info(struct mdm_hsic_pm_data *pm_data) +{ + pr_info("pm device\n\tname = %s\n" + "\tudev = 0x%p\n" + "\tintf_cnt = %d\n" + "\tblock_request = %s\n", + pm_data->name, + pm_data->udev, + pm_data->intf_cnt, + pm_data->block_request ? "true" : "false"); +} + +static struct mdm_hsic_pm_data *get_pm_data_by_dev_name(const char *name) +{ + struct mdm_hsic_pm_data *pm_data; + + if (list_empty(&hsic_pm_dev_list)) { + pr_err("%s:there's no dev on pm dev list\n", __func__); + return NULL; + }; + + /* get device from list */ + list_for_each_entry(pm_data, &hsic_pm_dev_list, list) { + if (!strncmp(pm_data->name, name, strlen(name))) + return pm_data; + } + + return NULL; +} + +void notify_modem_fatal(void) +{ + struct mdm_hsic_pm_data *pm_data = + get_pm_data_by_dev_name("mdm_hsic_pm0"); + + pr_info("%s or shutdown\n", __func__); + + if (!pm_data || !pm_data->intf_cnt || !pm_data->udev) + return; + + pm_data->shutdown = true; + + /* crash from sleep, ehci is in waking up, so do not control ehci */ + if (!pm_data->block_request) { + struct device *dev, *hdev; + hdev = pm_data->udev->bus->root_hub->dev.parent; + dev = &pm_data->udev->dev; + + pm_runtime_get_noresume(dev); + pm_runtime_dont_use_autosuspend(dev); + wake_up_all(&dev->power.wait_queue); + pm_runtime_resume(dev); + pm_runtime_get_noresume(dev); + + blocking_notifier_call_chain(&mdm_reset_notifier_list, 0, 0); + } +} + +void request_autopm_lock(int status) +{ + struct mdm_hsic_pm_data *pm_data = + get_pm_data_by_dev_name("mdm_hsic_pm0"); + + if (!pm_data || !pm_data->udev) + return; + + pr_debug("%s: set runtime pm lock : %d\n", __func__, status); + + if (status) { + if (!atomic_read(&pm_data->pmlock_cnt)) { + atomic_inc(&pm_data->pmlock_cnt); + pr_info("get lock\n"); + pm_runtime_get(&pm_data->udev->dev); + pm_runtime_forbid(&pm_data->udev->dev); + } else + atomic_inc(&pm_data->pmlock_cnt); + } else { + if (!atomic_read(&pm_data->pmlock_cnt)) + pr_info("unbalanced release\n"); + else if (atomic_dec_and_test(&pm_data->pmlock_cnt)) { + pr_info("release lock\n"); + pm_runtime_allow(&pm_data->udev->dev); + pm_runtime_put(&pm_data->udev->dev); + } + } +} + +void request_active_lock_set(const char *name) +{ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + pr_info("%s\n", __func__); + if (pm_data) + wake_lock(&pm_data->l2_wake); +} + +void request_active_lock_release(const char *name) +{ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + pr_info("%s\n", __func__); + if (pm_data) + wake_unlock(&pm_data->l2_wake); +} + +void request_boot_lock_set(const char *name) +{ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + pr_info("%s\n", __func__); + if (pm_data) + wake_lock(&pm_data->boot_wake); +} + +void request_boot_lock_release(const char *name) +{ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + pr_info("%s\n", __func__); + if (pm_data) + wake_unlock(&pm_data->boot_wake); +} + +bool check_request_blocked(const char *name) +{ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + if (!pm_data) + return false; + + return pm_data->block_request; +} + +void set_host_stat(const char *name, enum pwr_stat status) +{ + /* find pm device from list by name */ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + + if (!pm_data) { + pr_err("%s:no pm device(%s) exist\n", __func__, name); + return; + } + + if (pm_data->gpio_host_ready) { + pr_info("dev rdy val = %d\n", + gpio_get_value(pm_data->gpio_device_ready)); + pr_info("%s:set host port power status to [%d]\n", + __func__, status); + + /*10ms delay location moved*/ + if(status == POWER_OFF) + mdelay(10); + + gpio_set_value(pm_data->gpio_host_ready, status); + } +} + +#define DEV_POWER_WAIT_SPIN 10 +#define DEV_POWER_WAIT_MS 10 +int wait_dev_pwr_stat(const char *name, enum pwr_stat status) +{ + int spin; + /* find pm device from list by name */ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + + if (!pm_data) { + pr_err("%s:no pm device(%s) exist\n", __func__, name); + return -ENODEV; + } + + pr_info("%s:[%s]...\n", __func__, status ? "PWR ON" : "PWR OFF"); + + if (pm_data->gpio_device_ready) { + for (spin = 0; spin < DEV_POWER_WAIT_SPIN ; spin++) { + if (gpio_get_value(pm_data->gpio_device_ready) == + status) + break; + else + mdelay(DEV_POWER_WAIT_MS); + } + } + + if (gpio_get_value(pm_data->gpio_device_ready) == status) + pr_info(" done\n"); + else + subsystem_restart(EXTERNAL_MODEM); + return 0; +} + +/** + * check suspended state for L3 drive + * if not, L3 blocked and stay at L2 / L0 state + */ +int check_udev_suspend_allowed(const char *name) +{ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + struct device *dev; + + if (!pm_data) { + pr_err("%s:no pm device(%s) exist\n", __func__, name); + return -ENODEV; + } + if (!pm_data->intf_cnt || !pm_data->udev) + return -ENODEV; + + dev = &pm_data->udev->dev; + + pr_info("%s:state_busy = %d, suspended = %d(rpmstat = %d:dpth:%d)," + " suspended_child = %d\n", __func__, pm_data->state_busy, + pm_runtime_suspended(dev), dev->power.runtime_status, + dev->power.disable_depth, pm_children_suspended(dev)); + + if (pm_data->state_busy) + return -EBUSY; + + return pm_runtime_suspended(dev) && pm_children_suspended(dev); +} + +int set_hsic_lpa_states(int states) +{ + /* if modem need to check survive, get status in variable */ + int val = 1; + + /* set state for LPA enter */ + if (val) { + switch (states) { + case STATE_HSIC_LPA_ENTER: + /* + * need get some delay for MDM9x15 suspend + * if L3 drive goes out to modem in suspending + * modem goes to unstable PM state. now 10 ms is enough + */ + /*10ms delay location moved*/ + //mdelay(10); + set_host_stat("mdm_hsic_pm0", POWER_OFF); + wait_dev_pwr_stat("mdm_hsic_pm0", POWER_OFF); + pr_info("set hsic lpa enter\n"); + break; + case STATE_HSIC_LPA_WAKE: + /* host control is done by ehci runtime resume code */ + #if 0 + set_host_stat("mdm_hsic_pm0", POWER_ON); + wait_dev_pwr_stat("mdm_hsic_pm0", POWER_ON); + #endif + lpa_handling = true; + pr_info("%s: set lpa handling to true\n", __func__); + request_active_lock_set("mdm_hsic_pm0"); + pr_info("set hsic lpa wake\n"); + break; + case STATE_HSIC_LPA_PHY_INIT: + pr_info("set hsic lpa phy init\n"); + break; + case STATE_HSIC_LPA_CHECK: + if (lpcharge) + return 0; + else + if (!get_pm_data_by_dev_name("mdm_hsic_pm0")) + return 1; + else + return 0; + default: + pr_info("unknown lpa state\n"); + break; + } + } + return 0; +} + +#define PM_START_DELAY_MS 3000 +int register_udev_to_pm_dev(const char *name, struct usb_device *udev) +{ + /* find pm device from list by name */ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + + if (!pm_data) { + pr_err("%s:no pm device(%s) exist for udev(0x%p)\n", + __func__, name, udev); + return -ENODEV; + } + + print_pm_dev_info(pm_data); + + if (!pm_data->intf_cnt) { + pr_info("%s: registering new udev(0x%p) to %s\n", __func__, + udev, pm_data->name); + pm_data->udev = udev; + atomic_set(&pm_data->pmlock_cnt, 0); + usb_disable_autosuspend(udev); + } else if (pm_data->udev && pm_data->udev != udev) { + pr_err("%s:udev mismatching: pm_data->udev(0x%p), udev(0x%p)\n", + __func__, pm_data->udev, udev); + return -EINVAL; + } + + pm_data->intf_cnt++; + pr_info("%s:udev(0x%p) successfully registerd to %s, intf count = %d\n", + __func__, udev, pm_data->name, pm_data->intf_cnt); + + queue_delayed_work(pm_data->wq, &pm_data->auto_rpm_start_work, + msecs_to_jiffies(PM_START_DELAY_MS)); + return 0; +} + +/* force fatal for debug when HSIC disconnect */ +extern void mdm_force_fatal(void); + +void unregister_udev_from_pm_dev(const char *name, struct usb_device *udev) +{ + /* find pm device from list by name */ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + struct device *hdev; + + pr_info("%s\n", __func__); + + if (!pm_data) { + pr_err("%s:no pm device(%s) exist for udev(0x%p)\n", + __func__, name, udev); + return; + } + + if (!pm_data->shutdown) { + hdev = udev->bus->root_hub->dev.parent; + pm_runtime_forbid(hdev); /*ehci*/ + debug_ehci_reg_dump(hdev); + } + + if (pm_data->udev && pm_data->udev != udev) { + pr_err("%s:udev mismatching: pm_data->udev(0x%p), udev(0x%p)\n", + __func__, pm_data->udev, udev); + return; + } + + pm_data->intf_cnt--; + pr_info("%s:udev(0x%p) unregistered from %s, intf count = %d\n", + __func__, udev, pm_data->name, pm_data->intf_cnt); + + if (!pm_data->intf_cnt) { + pr_info("%s: all intf device unregistered from %s\n", + __func__, pm_data->name); + pm_data->udev = NULL; + /* force fatal for debug when HSIC disconnect */ + if (!pm_data->shutdown) { + mdm_force_fatal(); + } + } +} + +static void mdm_hsic_rpm_check(struct work_struct *work) +{ + struct mdm_hsic_pm_data *pm_data = + container_of(work, struct mdm_hsic_pm_data, + request_resume_work.work); + struct device *dev; + + if (pm_data->shutdown) + return; + + pr_info("%s\n", __func__); + + if (!pm_data->udev) + return; + + if (lpa_handling) { + pr_info("ignore resume req, lpa handling\n"); + return; + } + + dev = &pm_data->udev->dev; + + if (pm_runtime_resume(dev) < 0) + queue_delayed_work(pm_data->wq, &pm_data->request_resume_work, + msecs_to_jiffies(20)); + + if (pm_runtime_suspended(dev)) + queue_delayed_work(pm_data->wq, &pm_data->request_resume_work, + msecs_to_jiffies(20)); +}; + +static void mdm_hsic_rpm_start(struct work_struct *work) +{ + struct mdm_hsic_pm_data *pm_data = + container_of(work, struct mdm_hsic_pm_data, + auto_rpm_start_work.work); + struct usb_device *udev = pm_data->udev; + struct device *dev, *pdev, *hdev; + + pr_info("%s\n", __func__); + + if (!pm_data->intf_cnt || !pm_data->udev) + return; + + dev = &pm_data->udev->dev; + pdev = dev->parent; + pm_runtime_set_autosuspend_delay(dev, 500); + hdev = udev->bus->root_hub->dev.parent; + pr_info("EHCI runtime %s, %s\n", dev_driver_string(hdev), + dev_name(hdev)); + + pm_runtime_allow(dev); + pm_runtime_allow(hdev);/*ehci*/ + + pm_data->shutdown = false; +} + +static void mdm_hsic_rpm_restart(struct work_struct *work) +{ + struct mdm_hsic_pm_data *pm_data = + container_of(work, struct mdm_hsic_pm_data, + auto_rpm_restart_work.work); + struct device *dev; + + pr_info("%s\n", __func__); + + if (!pm_data->intf_cnt || !pm_data->udev) + return; + + dev = &pm_data->udev->dev; + pm_runtime_set_autosuspend_delay(dev, 500); +} + +static void fast_dormancy_func(struct work_struct *work) +{ + struct mdm_hsic_pm_data *pm_data = + container_of(work, struct mdm_hsic_pm_data, + fast_dormancy_work.work); + pr_debug("%s\n", __func__); + + if (!pm_data || !pm_data->fd_wake_time) + return; + + wake_lock_timeout(&pm_data->fd_wake, pm_data->fd_wake_time); +}; + +void fast_dormancy_wakelock(const char *name) +{ + struct mdm_hsic_pm_data *pm_data = get_pm_data_by_dev_name(name); + + if (!pm_data || !pm_data->fd_wake_time) + return; + + queue_delayed_work(pm_data->wq, &pm_data->fast_dormancy_work, 0); +} + +static ssize_t show_waketime(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mdm_hsic_pm_data *pm_data = platform_get_drvdata(pdev); + char *p = buf; + unsigned int msec; + + if (!pm_data) + return 0; + + msec = jiffies_to_msecs(pm_data->fd_wake_time); + p += sprintf(p, "%u\n", msec); + + return p - buf; +} + +static ssize_t store_waketime(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mdm_hsic_pm_data *pm_data = platform_get_drvdata(pdev); + unsigned long msec; + int r; + + if (!pm_data) + return count; + + r = strict_strtoul(buf, 10, &msec); + if (r) + return count; + + pm_data->fd_wake_time = msecs_to_jiffies(msec); + + return count; +} +static DEVICE_ATTR(waketime, 0660, show_waketime, store_waketime); + +static ssize_t store_runtime(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mdm_hsic_pm_data *pm_data = platform_get_drvdata(pdev); + int value; + + if (sscanf(buf, "%d", &value) != 1) + return -EINVAL; + + if (!pm_data || !pm_data->intf_cnt || !pm_data->udev) + return -ENXIO; + + if (value == 1) { + pr_info("%s: request runtime resume\n", __func__); + if (pm_request_resume(&pm_data->udev->dev) < 0) + pr_err("%s: unable to add pm work for rpm\n", __func__); + } + + return count; +} +static DEVICE_ATTR(runtime, 0664, NULL, store_runtime); + +static struct attribute *mdm_hsic_attrs[] = { + &dev_attr_waketime.attr, + &dev_attr_runtime.attr, + NULL +}; + +static struct attribute_group mdm_hsic_attrgroup = { + .attrs = mdm_hsic_attrs, +}; + +static int mdm_reset_notify_main(struct notifier_block *this, + unsigned long event, void *ptr) { + pr_info("%s\n", __func__); + + return NOTIFY_DONE; +}; + +static struct notifier_block mdm_reset_main_block = { + .notifier_call = mdm_reset_notify_main, +}; + +static int mdm_hsic_pm_notify_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct mdm_hsic_pm_data *pm_data = + container_of(this, struct mdm_hsic_pm_data, pm_notifier); + + switch (event) { + case PM_SUSPEND_PREPARE: + /* to catch blocked resume req */ + pm_data->state_busy = false; + pm_data->block_request = true; + pr_info("%s: block request\n", __func__); + return NOTIFY_OK; + case PM_POST_SUSPEND: + pm_data->block_request = false; + pr_info("%s: unblock request\n", __func__); + + if (pm_data->shutdown) { + notify_modem_fatal(); + return NOTIFY_DONE; + } + /** + * cover L2 -> L3 broken and resume req blocked case : + * force resume request for the lost request + */ + /* pm_request_resume(&pm_data->udev->dev); */ + queue_delayed_work(pm_data->wq, &pm_data->request_resume_work, + msecs_to_jiffies(20)); + /*pm_runtime_set_autosuspend_delay(&pm_data->udev->dev, 200);*/ + queue_delayed_work(pm_data->wq, &pm_data->auto_rpm_restart_work, + msecs_to_jiffies(20)); + + request_active_lock_set(pm_data->name); + + return NOTIFY_OK; + } + return NOTIFY_DONE; +} + +#define HSIC_RESUME_TRIGGER_LEVEL 1 +static irqreturn_t mdm_hsic_irq_handler(int irq, void *data) +{ + int irq_level; + struct mdm_hsic_pm_data *pm_data = data; + + if (!pm_data || !pm_data->intf_cnt || !pm_data->udev) + return IRQ_HANDLED; + + if (pm_data->shutdown) + return IRQ_HANDLED; + + /** + * host wake up handler, takes both edge + * in rising, isr triggers L2 -> L0 resume + */ + + irq_level = gpio_get_value(pm_data->gpio_host_wake); + pr_info("%s: detect %s edge\n", __func__, + irq_level ? "Rising" : "Falling"); + + if (irq_level != HSIC_RESUME_TRIGGER_LEVEL) + return IRQ_HANDLED; + + if (pm_data->block_request) { + pr_info("%s: request blocked by kernel suspending\n", __func__); + pm_data->state_busy = true; + /* for blocked request, set wakelock to return at dpm suspend */ + wake_lock(&pm_data->l2_wake); + return IRQ_HANDLED; + } +#if 0 + if (pm_request_resume(&pm_data->udev->dev) < 0) + pr_err("%s: unable to add pm work for rpm\n", __func__); + /* check runtime pm runs in Active state, after 100ms */ + queue_delayed_work(pm_data->wq, &pm_data->request_resume_work, + msecs_to_jiffies(200)); +#else + queue_delayed_work(pm_data->wq, &pm_data->request_resume_work, 0); +#endif + return IRQ_HANDLED; +} + +static int mdm_hsic_pm_gpio_init(struct mdm_hsic_pm_data *pm_data, + struct platform_device *pdev) +{ + int ret; + struct resource *res; + + /* get gpio from platform data */ + + /* host ready gpio */ + res = platform_get_resource_byname(pdev, IORESOURCE_IO, + "AP2MDM_HSIC_ACTIVE"); + if (res) + pm_data->gpio_host_ready = res->start; + + if (pm_data->gpio_host_ready) { + ret = gpio_request(pm_data->gpio_host_ready, "host_rdy"); + if (ret < 0) + return ret; + gpio_direction_output(pm_data->gpio_host_ready, 1); + } else + return -ENXIO; + + /* device ready gpio */ + res = platform_get_resource_byname(pdev, IORESOURCE_IO, + "MDM2AP_DEVICE_PWR_ACTIVE"); + if (res) + pm_data->gpio_device_ready = res->start; + if (pm_data->gpio_device_ready) { + ret = gpio_request(pm_data->gpio_device_ready, "device_rdy"); + if (ret < 0) + return ret; + gpio_direction_input(pm_data->gpio_device_ready); + s3c_gpio_cfgpin(pm_data->gpio_device_ready, S3C_GPIO_INPUT); + } else + return -ENXIO; + + /* host wake gpio */ + res = platform_get_resource_byname(pdev, IORESOURCE_IO, + "MDM2AP_RESUME_REQ"); + if (res) + pm_data->gpio_host_wake = res->start; + if (pm_data->gpio_host_wake) { + ret = gpio_request(pm_data->gpio_host_wake, "host_wake"); + if (ret < 0) + return ret; + gpio_direction_input(pm_data->gpio_host_wake); + s3c_gpio_cfgpin(pm_data->gpio_host_wake, S3C_GPIO_SFN(0xF)); + } else + return -ENXIO; + + if (pm_data->gpio_host_wake) + pm_data->irq = gpio_to_irq(pm_data->gpio_host_wake); + + if (!pm_data->irq) { + pr_err("fail to get host wake irq\n"); + return -ENXIO; + } + + return 0; +} + +static void mdm_hsic_pm_gpio_free(struct mdm_hsic_pm_data *pm_data) +{ + if (pm_data->gpio_host_ready) + gpio_free(pm_data->gpio_host_ready); + + if (pm_data->gpio_device_ready) + gpio_free(pm_data->gpio_device_ready); + + if (pm_data->gpio_host_wake) + gpio_free(pm_data->gpio_host_wake); +} + +static int link_pm_netdev_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct mdm_hsic_pm_data *pm_data = + container_of(this, struct mdm_hsic_pm_data, netdev_notifier); + struct mdm_hsic_pm_platform_data *mdm_pdata = pm_data->mdm_pdata; + struct net_device *dev = ptr; + + if (!net_eq(dev_net(dev), &init_net)) + return NOTIFY_DONE; + + if (!strncmp(dev->name, "rndis", 5)) { + switch (event) { + case NETDEV_UP: + pr_info("%s: %s UP\n", __func__, dev->name); + if (mdm_pdata->freq_lock) + mdm_pdata->freq_lock(mdm_pdata->dev); + + break; + case NETDEV_DOWN: + pr_info("%s: %s DOWN\n", __func__, dev->name); + if (mdm_pdata->freq_unlock) + mdm_pdata->freq_unlock(mdm_pdata->dev); + break; + } + } + return NOTIFY_DONE; +} + +static int usb_composite_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct mdm_hsic_pm_data *pm_data = + container_of(this, struct mdm_hsic_pm_data, + usb_composite_notifier); + struct mdm_hsic_pm_platform_data *mdm_pdata = pm_data->mdm_pdata; + + switch (event) { + case 0: + if (mdm_pdata->freq_unlock) + mdm_pdata->freq_unlock(mdm_pdata->dev); + pr_info("%s: USB detached\n", __func__); + break; + case 1: + if (mdm_pdata->freq_lock) + mdm_pdata->freq_lock(mdm_pdata->dev); + pr_info("%s: USB attached\n", __func__); + break; + } + pr_info("%s: usb configuration: %s\n", __func__, (char *)ptr); + + return NOTIFY_DONE; +} + +static int mdm_hsic_pm_probe(struct platform_device *pdev) +{ + int ret; + struct mdm_hsic_pm_data *pm_data; + + pr_info("%s for %s\n", __func__, pdev->name); + + pm_data = kzalloc(sizeof(struct mdm_hsic_pm_data), GFP_KERNEL); + if (!pm_data) { + pr_err("%s: fail to alloc pm_data\n", __func__); + return -ENOMEM; + } + + /* initial value */ + memcpy(pm_data->name, pdev->name, strlen(pdev->name)); + + ret = mdm_hsic_pm_gpio_init(pm_data, pdev); + if (ret < 0) + goto err_gpio_init_fail; + + /* request irq for host wake interrupt */ + ret = request_irq(pm_data->irq, mdm_hsic_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | IRQF_DISABLED, + pm_data->name, (void *)pm_data); + if (ret < 0) { + pr_err("%s: fail to request irq(%d)\n", __func__, ret); + goto err_request_irq; + } + + ret = enable_irq_wake(pm_data->irq); + if (ret < 0) { + pr_err("%s: fail to set wake irq(%d)\n", __func__, ret); + goto err_set_wake_irq; + } + + pm_data->wq = create_singlethread_workqueue("hsicrpmd"); + if (!pm_data->wq) { + pr_err("%s: fail to create wq\n", __func__); + goto err_create_wq; + } + + if (sysfs_create_group(&pdev->dev.kobj, &mdm_hsic_attrgroup) < 0) { + pr_err("%s: fail to create sysfs\n", __func__); + goto err_create_sys_file; + } + + pm_data->mdm_pdata = + (struct mdm_hsic_pm_platform_data *)pdev->dev.platform_data; + INIT_DELAYED_WORK(&pm_data->auto_rpm_start_work, mdm_hsic_rpm_start); + INIT_DELAYED_WORK(&pm_data->auto_rpm_restart_work, + mdm_hsic_rpm_restart); + INIT_DELAYED_WORK(&pm_data->request_resume_work, mdm_hsic_rpm_check); + INIT_DELAYED_WORK(&pm_data->fast_dormancy_work, fast_dormancy_func); + /* register notifier call */ + pm_data->pm_notifier.notifier_call = mdm_hsic_pm_notify_event; + register_pm_notifier(&pm_data->pm_notifier); + blocking_notifier_chain_register(&mdm_reset_notifier_list, + &mdm_reset_main_block); + + pm_data->netdev_notifier.notifier_call = link_pm_netdev_event; + register_netdevice_notifier(&pm_data->netdev_notifier); + + pm_data->usb_composite_notifier.notifier_call = + usb_composite_notifier_event; + register_usb_composite_notifier(&pm_data->usb_composite_notifier); + + wake_lock_init(&pm_data->l2_wake, WAKE_LOCK_SUSPEND, pm_data->name); + wake_lock_init(&pm_data->boot_wake, WAKE_LOCK_SUSPEND, "mdm_boot"); + wake_lock_init(&pm_data->fd_wake, WAKE_LOCK_SUSPEND, "fast_dormancy"); + pm_data->fd_wake_time = DEFAULT_RAW_WAKE_TIME; + + print_pm_dev_info(pm_data); + list_add(&pm_data->list, &hsic_pm_dev_list); + platform_set_drvdata(pdev, pm_data); + pr_info("%s for %s has done\n", __func__, pdev->name); + + return 0; + +err_create_sys_file: + destroy_workqueue(pm_data->wq); +err_create_wq: + disable_irq_wake(pm_data->irq); +err_set_wake_irq: + free_irq(pm_data->irq, (void *)pm_data); +err_request_irq: +err_gpio_init_fail: + mdm_hsic_pm_gpio_free(pm_data); + kfree(pm_data); + return -ENXIO; +} + +static struct platform_driver mdm_pm_driver = { + .probe = mdm_hsic_pm_probe, + .driver = { + .name = "mdm_hsic_pm0", + .owner = THIS_MODULE, + }, +}; + +static int __init mdm_hsic_pm_init(void) +{ + /* in lpm mode, do not load modem driver */ + if (lpcharge) + return 0; + return platform_driver_register(&mdm_pm_driver); +} + +static void __exit mdm_hsic_pm_exit(void) +{ + platform_driver_unregister(&mdm_pm_driver); +} + +late_initcall(mdm_hsic_pm_init); diff --git a/arch/arm/mach-exynos/mdm_private.h b/arch/arm/mach-exynos/mdm_private.h index 206bd8b..6dbcfa4 100644 --- a/arch/arm/mach-exynos/mdm_private.h +++ b/arch/arm/mach-exynos/mdm_private.h @@ -17,6 +17,7 @@ struct mdm_modem_drv; struct mdm_ops { void (*power_on_mdm_cb)(struct mdm_modem_drv *mdm_drv); + void (*reset_mdm_cb)(struct mdm_modem_drv *mdm_drv); void (*normal_boot_done_cb)(struct mdm_modem_drv *mdm_drv); void (*power_down_mdm_cb)(struct mdm_modem_drv *mdm_drv); void (*debug_state_changed_cb)(int value); @@ -31,8 +32,12 @@ struct mdm_modem_drv { unsigned ap2mdm_status_gpio; unsigned mdm2ap_wakeup_gpio; unsigned ap2mdm_wakeup_gpio; - unsigned ap2mdm_pmic_reset_n_gpio; unsigned ap2mdm_kpdpwr_n_gpio; + unsigned ap2mdm_soft_reset_gpio; + unsigned ap2mdm_pmic_pwr_en_gpio; + unsigned mdm2ap_pblrdy; + + int proto_is_dload; int mdm_errfatal_irq; int mdm_status_irq; @@ -41,6 +46,7 @@ struct mdm_modem_drv { int mdm_ram_dump_status; enum charm_boot_type boot_type; int mdm_debug_on; + int mdm_unexpected_reset_occurred; struct mdm_ops *ops; struct mdm_platform_data *pdata; @@ -51,6 +57,13 @@ int mdm_common_create(struct platform_device *pdev, int mdm_common_modem_remove(struct platform_device *pdev); void mdm_common_modem_shutdown(struct platform_device *pdev); void mdm_common_set_debug_state(int value); +void mdm_peripheral_disconnect(struct mdm_modem_drv *mdm_drv); + +void notify_modem_fatal(void); +void request_autopm_lock(int status); +extern unsigned int lpcharge; +extern void ctrl_bridge_stop_all(void); +extern void rmnet_usb_ctrl_stop_all(void); #endif diff --git a/arch/arm/mach-exynos/midas-camera.c b/arch/arm/mach-exynos/midas-camera.c index d120808..636ba13 100644 --- a/arch/arm/mach-exynos/midas-camera.c +++ b/arch/arm/mach-exynos/midas-camera.c @@ -75,18 +75,38 @@ static int __init camera_class_init(void) subsys_initcall(camera_class_init); +#if defined(CONFIG_MACH_T0) +#ifdef CONFIG_TARGET_LOCALE_EUR +#ifdef CONFIG_MACH_T0_EUR_LTE +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x04 +#else /*T0_EUR_3G*/ +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x05 +#endif +#elif defined(CONFIG_TARGET_LOCALE_CHN) +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x05 +#else +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x04 +#endif +#elif defined(CONFIG_MACH_BAFFIN) +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x00 +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x00 +#else #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) -#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x06 +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x07 #define USE_8M_CAM_SENSOR_CORE_REVISION 0x09 #elif defined(CONFIG_MACH_C1_KOR_LGT) -#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x04 +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x05 #define USE_8M_CAM_SENSOR_CORE_REVISION 0x07 #elif defined(CONFIG_MACH_C1_USA_ATT) -#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x05 -#elif defined(CONFIG_MACH_C1VZW) -#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x0A +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x06 +#define USE_8M_CAM_SENSOR_CORE_REVISION 0x09 +#elif defined(CONFIG_MACH_REDWOOD) +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x04 +#define USE_8M_CAM_SENSOR_CORE_REVISION 0xFF #else -#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x08 +#define FRONT_CAM_MCLK_DEVIDED_REVISION 0x09 +#define USE_8M_CAM_SENSOR_CORE_REVISION 0xFF +#endif #endif #if defined(CONFIG_VIDEO_FIMC) @@ -323,7 +343,15 @@ static int s5k6a3_gpio_request(void) return ret; } - if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_SLP_T0_LTE) + ret = gpio_request(GPIO_VTCAM_MCLK, "GPM2"); + if (ret) { + printk(KERN_ERR "fail to request gpio(GPIO_VTCAM_MCLK)\n"); + return ret; + } +#else + if (system_rev < FRONT_CAM_MCLK_DEVIDED_REVISION) ret = gpio_request(GPIO_CAM_MCLK, "GPJ1"); else ret = gpio_request(GPIO_VTCAM_MCLK, "GPM2"); @@ -331,6 +359,7 @@ static int s5k6a3_gpio_request(void) printk(KERN_ERR "fail to request gpio(GPIO_VTCAM_MCLK)\n"); return ret; } +#endif ret = gpio_request(GPIO_CAM_VT_nRST, "GPM1"); if (ret) { @@ -357,7 +386,17 @@ static int s5k6a3_power_on(void) udelay(100); /* MCLK */ - if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) { +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) ||\ + defined(CONFIG_MACH_SLP_T0_LTE) + ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_NONE); +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_SLP_T0_LTE) + s5p_gpio_set_drvstr(GPIO_VTCAM_MCLK, S5P_GPIO_DRVSTR_LV1); +#else + s5p_gpio_set_drvstr(GPIO_VTCAM_MCLK, S5P_GPIO_DRVSTR_LV2); +#endif +#else + if (system_rev < FRONT_CAM_MCLK_DEVIDED_REVISION) { ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV2); @@ -366,6 +405,7 @@ static int s5k6a3_power_on(void) s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(GPIO_VTCAM_MCLK, S5P_GPIO_DRVSTR_LV2); } +#endif CAM_CHECK_ERR_RET(ret, "cfg mclk"); /* VT_RESET */ @@ -382,10 +422,16 @@ static int s5k6a3_power_on(void) gpio_free(GPIO_CAM_IO_EN); gpio_free(GPIO_CAM_VT_nRST); - if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) + +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_SLP_T0_LTE) + gpio_free(GPIO_VTCAM_MCLK); +#else + if (system_rev < FRONT_CAM_MCLK_DEVIDED_REVISION) gpio_free(GPIO_CAM_MCLK); else gpio_free(GPIO_VTCAM_MCLK); +#endif return ret; } @@ -419,7 +465,12 @@ static int s5k6a3_power_down(void) udelay(500); /* MCLK */ - if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) { +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_SLP_T0_LTE) + ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_DOWN); +#else + if (system_rev < FRONT_CAM_MCLK_DEVIDED_REVISION) { ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_INPUT); s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_DOWN); @@ -427,15 +478,21 @@ static int s5k6a3_power_down(void) ret = s3c_gpio_cfgpin(GPIO_VTCAM_MCLK, S3C_GPIO_INPUT); s3c_gpio_setpull(GPIO_VTCAM_MCLK, S3C_GPIO_PULL_DOWN); } +#endif CAM_CHECK_ERR(ret, "cfg mclk"); gpio_free(GPIO_CAM_IO_EN); gpio_free(GPIO_CAM_VT_nRST); - if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_SLP_T0_LTE) + gpio_free(GPIO_VTCAM_MCLK); +#else + if (system_rev < FRONT_CAM_MCLK_DEVIDED_REVISION) gpio_free(GPIO_CAM_MCLK); else gpio_free(GPIO_VTCAM_MCLK); +#endif return ret; } @@ -462,10 +519,12 @@ error_out: static const char *s5k6a3_get_clk_name(void) { -#ifdef CONFIG_MACH_P4NOTE +#if defined(CONFIG_MACH_P4NOTE) || \ + defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) \ + || defined(CONFIG_MACH_SLP_T0_LTE) return "sclk_cam1"; #else - if (system_rev <= FRONT_CAM_MCLK_DEVIDED_REVISION) + if (system_rev < FRONT_CAM_MCLK_DEVIDED_REVISION) return "sclk_cam0"; else return "sclk_cam1"; @@ -653,20 +712,28 @@ static int s5c73m3_gpio_request(void) printk(KERN_ERR "fail to request gpio(GPIO_CAM_IO_EN)\n"); return ret; } - +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_CAM_AF_EN, "GPM1"); +#else ret = gpio_request(GPIO_CAM_AF_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "faile to request gpio(GPIO_CAM_AF_EN)\n"); return ret; } +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM1"); +#else ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "fail to request gpio(GPIO_ISP_CORE_EN)\n"); return ret; } -#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_SLP_T0_LTE) || defined(CONFIG_MACH_BAFFIN) if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) { ret = gpio_request(GPIO_CAM_SENSOR_CORE_EN, "GPM0"); if (ret) { @@ -687,7 +754,8 @@ static void s5c73m3_gpio_free(void) gpio_free(GPIO_CAM_AF_EN); gpio_free(GPIO_ISP_CORE_EN); -#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_SLP_T0_LTE) || defined(CONFIG_MACH_BAFFIN) if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) gpio_free(GPIO_CAM_SENSOR_CORE_EN); #endif @@ -724,11 +792,14 @@ static int s5c73m3_power_on(void) CAM_CHECK_ERR_RET(ret, "output IO_EN"); /* CAM_SENSOR_CORE_1.2V */ -#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_SLP_T0_LTE) || defined(CONFIG_MACH_BAFFIN) + printk(KERN_DEBUG "system_rev : %d\n", system_rev); if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) { ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE_EN, 1); CAM_CHECK_ERR_RET(ret, "output CAM_SENSOR_CORE_EN"); - mdelay(5); + /* delay is needed : external LDO is slower than MCLK control*/ + udelay(200); } else { regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); if (IS_ERR(regulator)) @@ -754,7 +825,11 @@ static int s5c73m3_power_on(void) ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); CAM_CHECK_ERR_RET(ret, "cfg mclk"); s3c_gpio_setpull(GPIO_CAM_MCLK, S3C_GPIO_PULL_NONE); +#if defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_SLP_T0_LTE) + s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV2); +#else s5p_gpio_set_drvstr(GPIO_CAM_MCLK, S5P_GPIO_DRVSTR_LV3); +#endif /* CAM_AF_2.8V */ ret = gpio_direction_output(GPIO_CAM_AF_EN, 1); @@ -836,7 +911,8 @@ static int s5c73m3_power_down(void) CAM_CHECK_ERR(ret, "disable cam_isp_sensor_1.8v"); /* CAM_SENSOR_CORE_1.2V */ -#if defined(CONFIG_MACH_C1) && defined(CONFIG_TARGET_LOCALE_KOR) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_SLP_T0_LTE) || defined(CONFIG_MACH_BAFFIN) if (system_rev >= USE_8M_CAM_SENSOR_CORE_REVISION) { ret = gpio_direction_output(GPIO_CAM_SENSOR_CORE_EN, 0); CAM_CHECK_ERR_RET(ret, "output CAM_SENSOR_CORE_EN"); @@ -912,11 +988,6 @@ error_out: static int s5c73m3_get_i2c_busnum(void) { -#if 0 - if (system_rev == 0x03) /*M0, M1 REV00*/ - return 18; - else -#endif return 0; } @@ -1005,7 +1076,11 @@ static int m5mo_power_on(void) printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); return ret; } +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM1"); +#else ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); return ret; @@ -1143,7 +1218,11 @@ static int m5mo_power_down(void) printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); return ret; } +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM1"); +#else ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); return ret; @@ -1360,7 +1439,11 @@ static int m9mo_power_on(void) printk(KERN_DEBUG "%s: in\n", __func__); +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM1"); +#else ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n"); return ret; @@ -1385,16 +1468,6 @@ static int m9mo_power_on(void) regulator_put(regulator); CAM_CHECK_ERR_RET(ret, "enable cam_isp_1.2v"); - /* CAM_SENSOR_CORE_1.2V (CIS 1.2V) => LDO17*/ - regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); - if (IS_ERR(regulator)) { - CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v"); - return -ENODEV; - } - ret = regulator_enable(regulator); - regulator_put(regulator); - CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v"); - /* CAM_ISP_1.8V (ISP 1.8V) => LDO23*/ regulator = regulator_get(NULL, "cam_isp_1.8v"); if (IS_ERR(regulator)) { @@ -1423,6 +1496,16 @@ static int m9mo_power_on(void) regulator_put(regulator); CAM_CHECK_ERR_RET(ret, "enable cam_sensor_2.8v"); + /* CAM_SENSOR_CORE_1.2V (CIS 1.2V) => LDO17*/ + regulator = regulator_get(NULL, "cam_sensor_core_1.2v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err cam_sensor_core_1.2v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable cam_sensor_core_1.2v"); + /* MCLK */ ret = s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(2)); CAM_CHECK_ERR_RET(ret, "cfg mclk"); @@ -1459,7 +1542,11 @@ static int m9mo_power_down(void) return ret; } } +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM1"); +#else ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "faile to request gpio(GPIO_ISP_CORE_EN)\n"); return ret; @@ -1565,6 +1652,7 @@ static int m9mo_power_down(void) gpio_free(GPIO_MOT_EN); gpio_free(GPIO_SAMBAZ_RESET); } + gpio_free(GPIO_ISP_CORE_EN); gpio_free(GPIO_ISP_RESET); @@ -1577,6 +1665,57 @@ static int m9mo_flash_power(int enable) return 0; } +static int m9mo_af_led_power_on(void) +{ + struct regulator *regulator; + int ret = 0; + + /* AF_LED 3.3V => LDO24*/ + regulator = regulator_get(NULL, "led_3.3v"); + if (IS_ERR(regulator)) { + CAM_CHECK_ERR_RET(ret, "output Err led_3.3v"); + return -ENODEV; + } + ret = regulator_enable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR_RET(ret, "enable led_3.3v"); + + return ret; +} + +static int m9mo_af_led_power_down(void) +{ + struct regulator *regulator; + int ret = 0; + + /* AF_LED 3.3V => LDO24*/ + regulator = regulator_get(NULL, "led_3.3v"); + if (IS_ERR(regulator)) + return -ENODEV; + if (regulator_is_enabled(regulator)) + ret = regulator_force_disable(regulator); + regulator_put(regulator); + CAM_CHECK_ERR(ret, "disable led_3.3v"); + + return ret; +} + +static int m9mo_af_led_power(int enable) +{ + int ret = 0; + + printk(KERN_ERR "%s %s\n", __func__, enable ? "on" : "down"); + if (enable) { + ret = m9mo_af_led_power_on(); + if (unlikely(ret)) + goto error_out; + } else { + ret = m9mo_af_led_power_down(); + } +error_out: + return ret; +} + static int m9mo_power(int enable) { int ret = 0; @@ -1623,7 +1762,7 @@ static int m9mo_config_sambaz(int enable) } ret = gpio_direction_output(GPIO_MOT_EN, 1); CAM_CHECK_ERR(ret, "output reset"); - msleep(100); + msleep(2); } regulator = regulator_get(NULL, "mot_3.3v"); @@ -1632,7 +1771,7 @@ static int m9mo_config_sambaz(int enable) ret = regulator_enable(regulator); regulator_put(regulator); CAM_CHECK_ERR_RET(ret, "mot_3.3v"); - mdelay(100); + mdelay(2); regulator = regulator_get(NULL, "ois_1.5v"); if (IS_ERR(regulator)) @@ -1640,12 +1779,12 @@ static int m9mo_config_sambaz(int enable) ret = regulator_enable(regulator); regulator_put(regulator); CAM_CHECK_ERR_RET(ret, "ois_1.5v"); - mdelay(10); + mdelay(2); if (system_rev > 0) { ret = gpio_direction_output(GPIO_SAMBAZ_RESET, 1); CAM_CHECK_ERR(ret, "output reset"); - msleep(100); + msleep(2); gpio_free(GPIO_MOT_EN); gpio_free(GPIO_SAMBAZ_RESET); @@ -1684,6 +1823,7 @@ static struct m9mo_platform_data m9mo_plat = { .is_mipi = 1, .config_isp_irq = m9mo_config_isp_irq, .config_sambaz = m9mo_config_sambaz, + .af_led_power = m9mo_af_led_power, .irq = IRQ_EINT(2), }; @@ -1740,7 +1880,7 @@ static void isx012_flashtimer_handler(unsigned long data) int ret = -ENODEV; atomic_t *flash_status = (atomic_t *)data; - pr_info("********** flashtimer_handler **********\n"); + pr_info("********** flash_handler off **********\n"); ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 0); atomic_set(flash_status, ISX012_FLASH_OFF); @@ -1780,7 +1920,7 @@ static int isx012_flash_en(u32 mode, u32 onoff) ret = gpio_direction_output(GPIO_CAM_MOVIE_EN, 1); else { ret = gpio_direction_output(GPIO_CAM_FLASH_EN, 1); - flash_timer.expires = get_jiffies_64() + HZ / 2; + flash_timer.expires = get_jiffies_64() + HZ; add_timer(&flash_timer); } CAM_CHECK_ERR_GOTO(ret, out, @@ -2655,7 +2795,11 @@ static int sr200pc20m_power_on(void) printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); return ret; } +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM1"); +#else ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); return ret; @@ -2773,7 +2917,11 @@ static int sr200pc20m_power_off(void) printk(KERN_ERR "faile to request gpio(GPIO_CAM_VGA_nRST)\n"); return ret; } +#if defined(CONFIG_MACH_M3_JPN_DCM) + ret = gpio_request(GPIO_ISP_CORE_EN, "GPM1"); +#else ret = gpio_request(GPIO_ISP_CORE_EN, "GPM0"); +#endif if (ret) { printk(KERN_ERR "fail to request gpio(CAM_SENSOR_CORE)\n"); return ret; diff --git a/arch/arm/mach-exynos/midas-gpio.c b/arch/arm/mach-exynos/midas-gpio.c index ff7d99e..570b17b 100644 --- a/arch/arm/mach-exynos/midas-gpio.c +++ b/arch/arm/mach-exynos/midas-gpio.c @@ -38,8 +38,7 @@ static struct gpio_init_data midas_init_gpios[] = { S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */ {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M3) +#if defined(CONFIG_MACH_C1) {EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */ {EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -140,8 +139,6 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ defined(CONFIG_MACH_C1_KOR_LGT) {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, -#elif defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, #else {EXYNOS4_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, #endif @@ -181,8 +178,8 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0) /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, #else @@ -195,11 +192,7 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /*UART_SEL*/ {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPF2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -247,35 +240,23 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { #else {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#else {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPL0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#else {EXYNOS4_GPL1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#endif {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M3) +#if defined(CONFIG_MACH_C1) /* GLP2(4) CMC_CPU_RESET, hold high */ {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */ #else @@ -289,8 +270,7 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_M0) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) +#if defined(CONFIG_MACH_M0) /* GPX3(2) M0 CP_PMU_RESET, hold high */ {EXYNOS4_GPX3(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, #else @@ -319,33 +299,18 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPY3(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPY3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY3(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - /* GPY4(2) S2Plus PDA_ACTIVE, let cp know AP sleep status*/ - {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPY4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY4(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -443,11 +408,7 @@ static unsigned int exynos4212_sleep_gpio_table[][3] = { {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#endif {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -483,8 +444,7 @@ static unsigned int exynos4212_sleep_gpio_table[][3] = { {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) /* GPM3(3) M0, CP_RESET_REQ hold high */ {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_DOWN}, #else @@ -500,13 +460,8 @@ static unsigned int exynos4212_sleep_gpio_table[][3] = { {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */ {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */ {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBAS_EN */ - {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MICBIAS_EN */ -#else {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -662,7 +617,7 @@ static struct gpio_init_data m0_init_gpios[] = { S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) {EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */ {EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -756,7 +711,10 @@ static struct gpio_init_data m0_init_gpios[] = { {EXYNOS4212_GPM3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PMIC_DVS1 */ - +#if defined(CONFIG_MACH_M0_DUOSCTC) + {EXYNOS4212_GPM4(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV3}, /* MSENSE_RST_N */ +#endif {EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -788,12 +746,22 @@ static struct gpio_init_data m0_init_gpios[] = { {EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV3}, /* VTCAM_MCLK */ +#if !defined(CONFIG_MACH_M0_GRANDECTC) {EXYNOS4_GPK2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV4}, /* SD_CLK */ {EXYNOS4_GPK2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV4}, /* SD_CMD */ {EXYNOS4_GPK2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_nCD(NC) */ + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV4}, /* SD_nCD(NC) */ + {EXYNOS4_GPK2(3), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT0 */ + {EXYNOS4_GPK2(4), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT1 */ + {EXYNOS4_GPK2(5), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT2 */ + {EXYNOS4_GPK2(6), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* SD_DAT3 */ +#endif }; /* @@ -840,9 +808,6 @@ static unsigned int m0_sleep_gpio_table[][3] = { defined(CONFIG_MACH_C1_KOR_LGT) {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, -#elif defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPC0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, #else {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_IN(NC) */ {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_OUT(NC) */ @@ -879,7 +844,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) /* CMC221 Active States */ {EXYNOS4_GPF1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* NC */ #else @@ -889,7 +854,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ +#if defined(CONFIG_MACH_C1) || \ defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -903,11 +868,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPF2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */ {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */ @@ -967,7 +928,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) /* GLP2(4) CMC_CPU_RESET, hold high */ {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */ #else @@ -981,22 +942,18 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) {EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_CSN */ #else {EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPY0(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* VIA_DPRAM_CSN */ -#else {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif - {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_REN */ {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_WEN */ #else @@ -1004,13 +961,8 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_LBN */ - {EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_UBN */ -#else {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -1071,9 +1023,8 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) ||\ - defined(CONFIG_MACH_C1VZW) || defined(CONFIG_MACH_C1ATT) ||\ - defined(CONFIG_MACH_S2PLUS) || defined(CONFIG_MACH_SLP_PQ) +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_C1ATT) || defined(CONFIG_MACH_SLP_PQ) /* GPIO_PS_ALS_EN */ {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, #else @@ -1240,10 +1191,10 @@ static unsigned int m0_sleep_gpio_table_rev11[][3] = { {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ }; -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) /* * C1 GPIO Sleep Table - * Based on C1 Rev0.4(0x6) / C1VZW Rev0.3(0xB) + * Based on C1 Rev0.4(0x6) */ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -1259,13 +1210,8 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPA1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_TXD_1.8V */ - {EXYNOS4_GPA1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP_VIA_RXD_1.8V */ -#else {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#endif {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -1279,27 +1225,13 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_2.2V_EN */ {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(AP_CP_WAKEUP_1.8V) */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPC0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* EARMICBIAS_EN */ - {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* 2MIC_WAKE */ -#else {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_IN(NC) */ {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_OUT(NC) */ -#endif -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CP_RST_INDICATE_1.8V */ -#else {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* 2MIC_SDA_1.8V */ - {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* 2MIC_SCL_1.8V */ -#else {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -1321,11 +1253,7 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* OLED_ID */ -#else {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPF1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -1336,23 +1264,12 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CMC_INT */ -#else {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CP_INT */ -#endif {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPF2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_RST_1.8V */ - {EXYNOS4_GPF2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* 2MIC_RST */ - {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */ - {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */ -#else {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */ {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */ @@ -1395,11 +1312,7 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPL0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* USB_HUB_RST */ {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TOUCH_SCL */ {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TOUCH_SDA */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*FM_PW*/ -#else {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */ /* {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BT_EN */ @@ -1413,36 +1326,27 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_M0_GRANDECTC) {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* CMC221_CPU_RST */ {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_PMIC_PWRON */ +#else + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC221_CPU_RST */ + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_PMIC_PWRON */ +#endif {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_CSN */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPY0(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* VIA_DPRAM_CSN */ -#else {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_REN */ {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_WEN */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_LBN */ - {EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* DPRAM_UBN */ -#else {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPY1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*FM_BP*/ - {EXYNOS4_GPY1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*FM_RST*/ -#else {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -1487,11 +1391,7 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#else {EXYNOS4_GPZ(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AUTO_DFS */ -#endif {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -1505,11 +1405,7 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TOUCH_INT */ {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */ {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PS_ALS_EN */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* LTE_VIA_UART_SEL */ -#else {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CAM_SW_EN */ @@ -1523,22 +1419,12 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_BOOT_SEL_1.8V */ - {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_PMIC_ON */ -#else {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_PS_HOLD_OFF */ - {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIA_USB_OFF */ -#else {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ @@ -1560,13 +1446,8 @@ static unsigned int c1_sleep_gpio_table[][3] = { {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_SPI_CLK_REQ */ {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(ISP_RXD) */ -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},/*FM_SCL*/ - {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},/*FM_SDA*/ -#else {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */ {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */ {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_CLK_1.8V */ @@ -1626,19 +1507,6 @@ static unsigned int c1_sleep_gpio_table_rev05[][3] = { #endif }; -/* - * C1VZW Rev0.4(0xC) - */ -static unsigned int c1vzw_sleep_gpio_table_rev04[][3] = { -#if defined(CONFIG_MACH_C1VZW) - {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif -}; #endif struct m0_sleep_table { @@ -1670,7 +1538,7 @@ static struct m0_sleep_table m0_sleep_table[] = { GPIO_TABLE(m0_sleep_gpio_table_rev11), /* Rev1.1(0xC) */ }; -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) static struct m0_sleep_table c1_sleep_table[] = { GPIO_TABLE(c1_sleep_gpio_table), /* Rev0.0(0x0) */ GPIO_TABLE_NULL, @@ -1684,7 +1552,6 @@ static struct m0_sleep_table c1_sleep_table[] = { GPIO_TABLE_NULL, GPIO_TABLE_NULL, GPIO_TABLE_NULL, - GPIO_TABLE(c1vzw_sleep_gpio_table_rev04), /* C1VZW Rev0.4(0xC) */ }; #endif @@ -1725,19 +1592,19 @@ static unsigned int c1kor_sleep_gpio_table[][3] = { {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MOSI */ #if defined(CONFIG_MACH_C1_KOR_LGT) - {EXYNOS4_GPC0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */ + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */ #else {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_2.2V_EN */ #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) - {EXYNOS4_GPC0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */ + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */ {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #else {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_CP_WAKEUP_1.8V */ {EXYNOS4_GPC0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* EARMICBIAS_EN */ #endif - {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TDMB_INT */ + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_INT */ #if defined(CONFIG_MACH_C1_KOR_LGT) {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CP_RST_INDICATE_1.8V */ @@ -1774,7 +1641,7 @@ static unsigned int c1kor_sleep_gpio_table[][3] = { {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RESET */ {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SCL_1.8V */ {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SDA_1.8V */ - {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */ {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBIAS_EN */ {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MICBIAS_EN */ @@ -1850,8 +1717,13 @@ static unsigned int c1kor_sleep_gpio_table[][3] = { {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_nRST */ {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_EN */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_M0_GRANDECTC) {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* CMC221_CPU_RST */ {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CMC_PMIC_PWRON */ +#else + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC221_CPU_RST */ + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CMC_PMIC_PWRON */ +#endif {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NFC_EN */ {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NFC_FIRMWARE */ @@ -2141,19 +2013,18 @@ static struct c1kor_sleep_table c1kor_sleep_table[] = { #endif /* C1_KOR */ #endif /* CONFIG_MIDAS_COMMON */ -#if defined(CONFIG_MACH_S2PLUS) /* - * S2Plus GPIO Sleep Table + * M0CTC GPIO Sleep Table */ -static unsigned int s2plus_sleep_gpio_table[][3] = { +static unsigned int m0ctc_sleep_gpio_table[][3] = { {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, - {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -2162,23 +2033,27 @@ static unsigned int s2plus_sleep_gpio_table[][3] = { {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_MACH_M0_DUOSCTC) + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */ + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */ + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */ +#endif {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -2193,53 +2068,66 @@ static unsigned int s2plus_sleep_gpio_table[][3] = { {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ +#if defined(CONFIG_MACH_M0_DUOSCTC) + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MIC */ +#endif + {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ +#if defined(CONFIG_MACH_M0_DUOSCTC) + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PCM_SEL */ +#else + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SCL*/ + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /*L_I2C_SDA*/ + + {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK2_SEL*/ + {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK3_SEL*/ + {EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BUCK4_SEL*/ {EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */ - {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */ - {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */ - {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */ - {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */ - {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */ - {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */ + + {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CLK*/ + {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_CMD*/ + {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*eMMC_EN*/ + {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(0)*/ + {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(1)*/ + {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(2)*/ + {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(3)*/ + {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */ - {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */ - {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */ - {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */ + {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(4)*/ + {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(5)*/ + {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(6)*/ + {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*NAND_D(7)*/ + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -2253,190 +2141,198 @@ static unsigned int s2plus_sleep_gpio_table[][3] = { {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */ +/* {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +/* {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +/* {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, */ {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - - {EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY4(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - - {EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - - {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY6(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ /* Exynos4212 specific gpio */ - {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_MACH_M0_DUOSCTC) + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/* NC */ + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/* NC */ +#else + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/* NC */ + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/* NC */ +#endif + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*TCH_EN*/ + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE},/*TCH_SET*/ + {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */ - {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */ - /* GPM3(3) M0, CP_RESET_REQ hold high */ - {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_TXD */ - {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RXD */ + {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS1*/ + {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS2*/ + {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*PMIC_DVS3*/ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */ - {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */ - {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SCL*/ + {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN},/*VTC_SDA*/ + {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -}; /* S2Plus_sleep_gpio_table */ -#endif + {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +}; /* m0ctc_sleep_gpio_table */ +#if defined(CONFIG_MACH_M0_GRANDECTC) /* - * M0CTC GPIO Sleep Table + * M0 GRANDE GPIO Sleep Table */ -static unsigned int m0ctc_sleep_gpio_table[][3] = { +static unsigned int m0grandectc_sleep_gpio_table[][3] = { {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -2457,8 +2353,8 @@ static unsigned int m0ctc_sleep_gpio_table[][3] = { {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -2564,7 +2460,7 @@ static unsigned int m0ctc_sleep_gpio_table[][3] = { /* {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, */ {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, @@ -2730,7 +2626,8 @@ static unsigned int m0ctc_sleep_gpio_table[][3] = { {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -}; /* m0ctc_sleep_gpio_table */ +}; /* m0grandectc_sleep_gpio_table */ +#endif static void config_sleep_gpio_table(int array_size, unsigned int (*gpio_table)[3]) @@ -2759,7 +2656,7 @@ void m0_config_sleep_gpio_table(void) } } -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) void c1_config_sleep_gpio_table(void) { int i; @@ -2797,17 +2694,16 @@ void c1kor_config_sleep_gpio_table(void) void midas_config_sleep_gpio_table(void) { #ifdef CONFIG_MIDAS_COMMON -#if defined(CONFIG_MACH_S2PLUS) - config_sleep_gpio_table(ARRAY_SIZE(s2plus_sleep_gpio_table), - s2plus_sleep_gpio_table); -#elif defined(CONFIG_MACH_C1CTC) || defined(CONFIG_MACH_M0_CTC) || \ - defined(CONFIG_MACH_M0_GRANDECTC) +#if defined(CONFIG_MACH_M0_GRANDECTC) + config_sleep_gpio_table(ARRAY_SIZE(m0grandectc_sleep_gpio_table), + m0grandectc_sleep_gpio_table); +#elif defined(CONFIG_MACH_M0_CTC) config_sleep_gpio_table(ARRAY_SIZE(m0ctc_sleep_gpio_table), m0ctc_sleep_gpio_table); #elif defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ defined(CONFIG_MACH_C1_KOR_LGT) c1kor_config_sleep_gpio_table(); -#elif defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#elif defined(CONFIG_MACH_C1) c1_config_sleep_gpio_table(); #else m0_config_sleep_gpio_table(); diff --git a/arch/arm/mach-exynos/midas-lcd.c b/arch/arm/mach-exynos/midas-lcd.c index 68125e2..ad722a6 100644 --- a/arch/arm/mach-exynos/midas-lcd.c +++ b/arch/arm/mach-exynos/midas-lcd.c @@ -471,10 +471,13 @@ static struct s3cfb_lcd s6e8aa0 = { .width = 720, .p_width = 60, /* 59.76 mm */ #endif - .p_height = 106, /* 106.24 mm */ + .p_height = 106, .bpp = 24, .freq = 60, +#if defined(CONFIG_S6E8AA0_AMS480GYXX) + .freq_limit = 40, +#endif /* minumun value is 0 except for wr_act time. */ .cpu_timing = { @@ -506,14 +509,135 @@ static struct s3cfb_lcd s6e8aa0 = { }; #endif +#ifdef CONFIG_FB_S5P_EA8061 +/* for Geminus based on MIPI-DSI interface */ +static struct s3cfb_lcd ea8061 = { + .name = "ea8061", + .height = 1280, + .width = 720, + .p_width = 74, + .p_height = 131, + .bpp = 24, + .freq = 60, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + + .timing = { + .h_fp = 52, + .h_bp = 96, + .h_sw = 4, + .v_fp = 13, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + .cmd_allow_len = 11, /* v_fp=stable_vfp + cmd_allow_len */ + .stable_vfp = 2, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; +#endif + +#ifdef CONFIG_FB_S5P_S6EVR02 +/* for Geminus based on MIPI-DSI interface */ +static struct s3cfb_lcd s6evr02 = { + .name = "s6evr02", + .height = 1280, + .width = 720, + .p_width = 74, + .p_height = 131, + .bpp = 24, + .freq = 58, + .freq_limit = 41, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + + .timing = { + .h_fp = 70, + .h_bp = 40, + .h_sw = 3, + .v_fp = 13, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + .cmd_allow_len = 7, /* v_fp=stable_vfp + cmd_allow_len + mask_len*/ + .stable_vfp = 2, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; + +static struct s3cfb_lcd ea8061 = { + .name = "ea8061", + .height = 1280, + .width = 720, + .p_width = 64, + .p_height = 106, + .bpp = 24, + .freq = 60, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + + .timing = { + .h_fp = 52, + .h_bp = 96, + .h_sw = 4, + .v_fp = 13, + .v_fpe = 1, + .v_bp = 1, + .v_bpe = 1, + .v_sw = 2, + .cmd_allow_len = 7, /* v_fp=stable_vfp + cmd_allow_len + mask_len*/ + .stable_vfp = 2, + }, + + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; +#endif + #ifdef CONFIG_FB_S5P_S6E63M0 /* for Geminus based on MIPI-DSI interface */ static struct s3cfb_lcd s6e63m0 = { .name = "s6e63m0", .width = 480, .height = 800, - .p_width = 60, /* 59.76 mm */ - .p_height = 106, /* 106.24 mm */ + .p_width = 60, + .p_height = 106, .bpp = 24, .freq = 56, @@ -630,6 +754,44 @@ static struct s3cfb_lcd s6d6aa1 = { }; #endif +#ifdef CONFIG_FB_S5P_LMS501XX +/* for Geminus based on MIPI-DSI interface */ +static struct s3cfb_lcd lms501xx = { + .name = "lms501xx", + .width = 480, + .height = 800, + .p_width = 66, + .p_height = 110, + .bpp = 24, + .freq = 60, + + /* minumun value is 0 except for wr_act time. */ + .cpu_timing = { + .cs_setup = 0, + .wr_setup = 0, + .wr_act = 1, + .wr_hold = 0, + }, + .timing = { + .h_fp = 65, + .h_bp = 49, + .h_sw = 17, + .v_fp = 8, + .v_fpe = 1, + .v_bp = 12, + .v_bpe = 1, + .v_sw = 4, + .cmd_allow_len = 6, /* v_fp=stable_vfp + cmd_allow_len */ + .stable_vfp = 2, + }, + .polarity = { + .rise_vclk = 1, + .inv_hsync = 0, + .inv_vsync = 0, + .inv_vden = 0, + }, +}; +#endif static int reset_lcd(void) { int err; @@ -664,6 +826,65 @@ static void lcd_cfg_gpio(void) return; } +#if defined(CONFIG_FB_S5P_LMS501XX) +static int lcd_power_on(void *ld, int enable) +{ + struct regulator *regulator; + int err; + + printk(KERN_INFO "%s : enable=%d\n", __func__, enable); + + err = gpio_request(GPIO_LCD_BL_EN, "LCD_BL_EN"); + if (err) { + printk(KERN_ERR "failed to request GPF0[5] for " + "LCD_BL_EN control\n"); + return -EPERM; + } + err = gpio_request(GPIO_MLCD_RST, "MLCD_RST"); + if (err) { + printk(KERN_ERR "failed to request GPY4[5] for " + "MLCD_RST control\n"); + return -EPERM; + } + + err = gpio_request(GPIO_LCD_22V_EN_00, "LCD_EN"); + if (err) { + printk(KERN_ERR "failed to request GPM4[4] for " + "LCD_2.2V_EN control\n"); + return -EPERM; + } + + if (enable) { + gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_HIGH); + msleep(25); + regulator = regulator_get(NULL, "vlcd_3.3v"); + if (IS_ERR(regulator)) + goto out; + regulator_enable(regulator); + regulator_put(regulator); + gpio_set_value(GPIO_LCD_BL_EN, 1); + } else { + regulator = regulator_get(NULL, "vlcd_3.3v"); + if (IS_ERR(regulator)) + goto out; + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + regulator_put(regulator); + + gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_LOW); + gpio_set_value(GPIO_MLCD_RST, 0); + gpio_set_value(GPIO_LCD_BL_EN, 0); + } + +out: +/* Release GPIO */ + gpio_free(GPIO_MLCD_RST); + gpio_free(GPIO_LCD_22V_EN_00); + gpio_free(GPIO_LCD_BL_EN); +return 0; + +} +#else static int lcd_power_on(void *ld, int enable) { struct regulator *regulator; @@ -688,18 +909,52 @@ static int lcd_power_on(void *ld, int enable) if (enable) { gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_HIGH); +#if defined(CONFIG_MACH_T0) + regulator = regulator_get(NULL, "vcc_1.8v_lcd"); + if (IS_ERR(regulator)) + goto out; + regulator_enable(regulator); + regulator_put(regulator); +#endif + +#ifdef CONFIG_MACH_GC1 + regulator = regulator_get(NULL, "lcd_io_1.8v"); + if (IS_ERR(regulator)) + goto out; + regulator_enable(regulator); + regulator_put(regulator); +#else regulator = regulator_get(NULL, "vlcd_3.3v"); if (IS_ERR(regulator)) goto out; regulator_enable(regulator); regulator_put(regulator); +#endif } else { +#ifdef CONFIG_MACH_GC1 + regulator = regulator_get(NULL, "lcd_io_1.8v"); + if (IS_ERR(regulator)) + goto out; + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + regulator_put(regulator); +#else regulator = regulator_get(NULL, "vlcd_3.3v"); if (IS_ERR(regulator)) goto out; if (regulator_is_enabled(regulator)) regulator_force_disable(regulator); regulator_put(regulator); +#endif + +#if defined(CONFIG_MACH_T0) + regulator = regulator_get(NULL, "vcc_1.8v_lcd"); + if (IS_ERR(regulator)) + goto out; + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + regulator_put(regulator); +#endif gpio_set_value(GPIO_LCD_22V_EN_00, GPIO_LEVEL_LOW); gpio_set_value(GPIO_MLCD_RST, 0); } @@ -709,7 +964,9 @@ out: gpio_free(GPIO_MLCD_RST); gpio_free(GPIO_LCD_22V_EN_00); return 0; + } +#endif static void s5p_dsim_mipi_power_control(int enable) { @@ -781,10 +1038,26 @@ void __init mipi_fb_init(void) #if defined(CONFIG_FB_S5P_S6E8AA0) dsim_lcd_info->lcd_panel_info = (void *)&s6e8aa0; #endif + +#if defined(CONFIG_FB_S5P_EA8061) + dsim_lcd_info->lcd_panel_info = (void *)&ea8061; +#endif + +#if defined(CONFIG_FB_S5P_S6EVR02) + dsim_lcd_info->lcd_panel_info = (void *)&s6evr02; +#endif + #if defined(CONFIG_FB_S5P_S6D6AA1) dsim_lcd_info->lcd_panel_info = (void *)&s6d6aa1; #endif +#if defined(CONFIG_MACH_T0) && defined(CONFIG_FB_S5P_S6EVR02) && defined(GPIO_OLED_ID) + if (!gpio_get_value(GPIO_OLED_ID)) { /* for EA8061 DDI */ + dsim_lcd_info->lcd_panel_info = (void *)&ea8061; + fb_platform_data.lcd = (void *)&ea8061; + } +#endif + #ifdef CONFIG_FB_S5P_S6E63M0 dsim_lcd_info->lcd_panel_info = (void *)&s6e63m0; dsim_pd->dsim_info->e_no_data_lane = DSIM_DATA_LANE_2; @@ -792,6 +1065,13 @@ void __init mipi_fb_init(void) dsim_pd->dsim_info->p = 3; dsim_pd->dsim_info->m = 80; dsim_pd->dsim_info->s = 1; +#elif defined(CONFIG_FB_S5P_LMS501XX) + dsim_lcd_info->lcd_panel_info = (void *)&lms501xx; + dsim_pd->dsim_info->e_no_data_lane = DSIM_DATA_LANE_2; + /* 440Mbps */ + dsim_pd->dsim_info->p = 3; + dsim_pd->dsim_info->m = 110; + dsim_pd->dsim_info->s = 1; #else /* 500Mbps */ dsim_pd->dsim_info->p = 3; @@ -809,7 +1089,6 @@ void __init mipi_fb_init(void) /*s3cfb_set_platdata(&fb_platform_data);*/ } #endif -#endif struct s3c_platform_fb fb_platform_data __initdata = { .hw_ver = 0x70, @@ -839,7 +1118,17 @@ struct s3c_platform_fb fb_platform_data __initdata = { #if defined(CONFIG_FB_S5P_S6D6AA1) .lcd = &s6d6aa1 #endif +#if defined(CONFIG_FB_S5P_EA8061) + .lcd = &ea8061 +#endif +#if defined(CONFIG_FB_S5P_S6EVR02) + .lcd = &s6evr02 +#endif +#if defined(CONFIG_FB_S5P_LMS501XX) + .lcd = &lms501xx +#endif }; +#endif #ifdef CONFIG_FB_S5P_MDNIE static struct platform_mdnie_data mdnie_data = { diff --git a/arch/arm/mach-exynos/midas-leds.c b/arch/arm/mach-exynos/midas-leds.c index 2d6e1e2..88fb113 100644 --- a/arch/arm/mach-exynos/midas-leds.c +++ b/arch/arm/mach-exynos/midas-leds.c @@ -1,43 +1,121 @@ -#include <linux/platform_device.h> -#include <linux/gpio.h> +/* + * + * Copyright (C) 2011 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + #include <linux/i2c.h> -#include <linux/i2c-gpio.h> +#include <linux/slab.h> #include <linux/leds-lp5521.h> - -#include <plat/gpio-cfg.h> -#include <mach/regs-gpio.h> -#include <mach/gpio.h> #include "midas.h" -#ifdef CONFIG_LEDS_LP5521 static struct lp5521_led_config lp5521_led_config[] = { { - .name = "red", - .chan_nr = 0, - .led_current = 50, - .max_current = 130, - }, { - .name = "green", - .chan_nr = 1, - .led_current = 30, - .max_current = 130, - }, { - .name = "blue", - .chan_nr = 2, - .led_current = 30, - .max_current = 130, + .name = "led_r", + .chan_nr = 0, + .led_current = 20, + .max_current = 20, + }, + { + .name = "led_g", + .chan_nr = 1, + .led_current = 20, + .max_current = 20, + }, + { + .name = "led_b", + .chan_nr = 2, + .led_current = 20, + .max_current = 20, }, }; -#define LP5521_CONFIGS (LP5521_PWM_HF | LP5521_PWRSAVE_EN | \ -LP5521_CP_MODE_AUTO | LP5521_R_TO_BATT | \ -LP5521_CLK_INT) + +/* mode 1 (charging) : RGB(255,0,0) always on */ +static u8 mode_charging[] = { 0x40, 0xFF, }; + +/* mode 2 (charging error) : RGB(255,0,0) 500ms off, 500ms on */ +static u8 mode_charging_err[] = { + 0x40, 0x00, 0x60, 0x00, 0x40, 0xFF, + 0x60, 0x00, + }; + +/* mode 3 (missed noti) : RGB(0,0,255) 5000ms off, 500ms on */ +static u8 mode_missed_noti[] = { + 0x40, 0x00, 0x60, 0x00, 0xA4, 0xA1, + 0x40, 0xFF, 0x60, 0x00, + }; + +/* mode 4 (low batt) : RGB(255,0,0) 5000ms off, 500ms on */ +static u8 mode_low_batt[] = { + 0x40, 0x00, 0x60, 0x00, 0xA4, 0xA1, + 0x40, 0xFF, 0x60, 0x00, + }; + +/* mode 5 (full charged) : RGB(0,255,0) always on */ +static u8 mode_full_chg[] = { 0x40, 0xFF, }; + +/* mode 6 (power on) : RGB(0,0,0) -> RGB(0,140,255) + ramp up 672ms, wait 328ms, ramp down 672ms, wait 328ms */ +static u8 mode_poweron_green[] = { + 0x40, 0x00, 0x0A, 0x45, 0x0A, 0x45, + 0x40, 0x8C, 0x55, 0x00, 0x0A, 0xC5, + 0xE0, 0x08, 0x0A, 0xC5, 0x40, 0x00, + 0x55, 0x00, 0xE0, 0x08, + }; + +static u8 mode_poweron_blue[] = { + 0x40, 0x00, 0x05, 0x7E, 0x05, 0x7E, + 0x40, 0xFF, 0x55, 0x00, 0x05, 0xFE, + 0xE1, 0x00, 0x05, 0xFE, 0x40, 0x00, + 0x55, 0x00, 0xE1, 0x00, + }; + +static struct lp5521_led_pattern board_led_patterns[] = { + { + .r = mode_charging, + .size_r = ARRAY_SIZE(mode_charging), + }, + { + .r = mode_charging_err, + .size_r = ARRAY_SIZE(mode_charging_err), + }, + { + .b = mode_missed_noti, + .size_b = ARRAY_SIZE(mode_missed_noti), + }, + { + .r = mode_low_batt, + .size_r = ARRAY_SIZE(mode_low_batt), + }, + { + .g = mode_full_chg, + .size_g = ARRAY_SIZE(mode_full_chg), + }, + { + .g = mode_poweron_green, + .b = mode_poweron_blue, + .size_g = ARRAY_SIZE(mode_poweron_green), + .size_b = ARRAY_SIZE(mode_poweron_blue), + }, +}; + +#define LP5521_CONFIGS (LP5521_PWM_HF | LP5521_PWRSAVE_EN | \ + LP5521_CP_MODE_BYPASS | \ + LP5521_CLOCK_INT) static struct lp5521_platform_data lp5521_pdata = { .led_config = lp5521_led_config, .num_channels = ARRAY_SIZE(lp5521_led_config), .clock_mode = LP5521_CLOCK_INT, .update_config = LP5521_CONFIGS, + .patterns = board_led_patterns, + .num_patterns = ARRAY_SIZE(board_led_patterns), }; + static struct i2c_board_info i2c_devs21_emul[] __initdata = { { I2C_BOARD_INFO("lp5521", 0x32), @@ -47,8 +125,11 @@ static struct i2c_board_info i2c_devs21_emul[] __initdata = { int __init plat_leds_init(void) { - i2c_add_devices(21, i2c_devs21_emul, ARRAY_SIZE(i2c_devs21_emul)); + i2c_add_devices(21, i2c_devs21_emul, + ARRAY_SIZE(i2c_devs21_emul)); return 0; -}; +} + module_init(plat_leds_init); -#endif + + diff --git a/arch/arm/mach-exynos/midas-mhl.c b/arch/arm/mach-exynos/midas-mhl.c index 5a97b00..93f0bb2 100644 --- a/arch/arm/mach-exynos/midas-mhl.c +++ b/arch/arm/mach-exynos/midas-mhl.c @@ -9,7 +9,16 @@ #include <plat/gpio-cfg.h> #include <mach/regs-gpio.h> #include <mach/gpio.h> +#include <linux/mfd/max77693.h> +#include <linux/mfd/max77693-private.h> +#include <linux/power_supply.h> #include "midas.h" +#include <plat/udc-hs.h> + +/*Event of receiving*/ +#define PSY_BAT_NAME "battery" +/*Event of sending*/ +#define PSY_CHG_NAME "max77693-charger" #ifdef CONFIG_SAMSUNG_MHL static void sii9234_cfg_gpio(void) @@ -44,7 +53,8 @@ static void sii9234_cfg_gpio(void) gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); #if !defined(CONFIG_MACH_C1_KOR_LGT) && !defined(CONFIG_SAMSUNG_MHL_9290) -#if !defined(CONFIG_MACH_P4NOTE) +#if !defined(CONFIG_MACH_P4NOTE) && !defined(CONFIG_MACH_T0) && \ + !defined(CONFIG_MACH_M3) && !defined(CONFIG_MACH_SLP_T0_LTE) s3c_gpio_cfgpin(GPIO_MHL_SEL, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_MHL_SEL, S3C_GPIO_PULL_NONE); gpio_set_value(GPIO_MHL_SEL, GPIO_LEVEL_LOW); @@ -81,6 +91,82 @@ static void sii9234_power_onoff(bool on) } } +#ifdef __MHL_NEW_CBUS_MSC_CMD__ +#if defined(CONFIG_MFD_MAX77693) +static int sii9234_usb_op(bool on, int value) +{ + pr_info("func:%s bool on(%d) int value(%d)\n", __func__, on, value); + if (on) { + if (value == 1) + max77693_muic_usb_cb(USB_CABLE_ATTACHED); + else if (value == 2) + max77693_muic_usb_cb(USB_POWERED_HOST_ATTACHED); + else + return 0; + } else { + if (value == 1) + max77693_muic_usb_cb(USB_CABLE_DETACHED); + else if (value == 2) + max77693_muic_usb_cb(USB_POWERED_HOST_DETACHED); + else + return 0; + } + return 1; +} +#endif +static void sii9234_vbus_present(bool on, int value) +{ + struct power_supply *psy = power_supply_get_by_name(PSY_CHG_NAME); + union power_supply_propval power_value; + u8 intval; + pr_info("%s: on(%d), vbus type(%d)\n", __func__, on, value); + + if (!psy) { + pr_err("%s: fail to get %s psy\n", __func__, PSY_CHG_NAME); + return; + } + + power_value.intval = ((POWER_SUPPLY_TYPE_MISC << 4) | + (on << 2) | (value << 0)); + + pr_info("%s: value.intval(0x%x)\n", __func__, power_value.intval); + psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &power_value); + + return; +} +#endif + +#ifdef CONFIG_SAMSUNG_MHL_UNPOWERED +static int sii9234_get_vbus_status(void) +{ + struct power_supply *psy = power_supply_get_by_name(PSY_BAT_NAME); + union power_supply_propval value; + u8 intval; + + if (!psy) { + pr_err("%s: fail to get %s psy\n", __func__, PSY_BAT_NAME); + return -1; + } + + psy->get_property(psy, POWER_SUPPLY_PROP_ONLINE, &value); + pr_info("%s: value.intval(0x%x)\n", __func__, value.intval); + + return (int)value.intval; +} + +static void sii9234_otg_control(bool onoff) +{ + otg_control(onoff); + + gpio_request(GPIO_OTG_EN, "USB_OTG_EN"); + gpio_direction_output(GPIO_OTG_EN, onoff); + gpio_free(GPIO_OTG_EN); + + printk(KERN_INFO "[MHL] %s: onoff =%d\n", __func__, onoff); + + return; +} +#endif static void sii9234_reset(void) { printk(KERN_INFO "%s()\n", __func__); @@ -126,12 +212,11 @@ static struct sii9234_platform_data sii9234_pdata = { .hw_onoff = sii9234_power_onoff, .hw_reset = sii9234_reset, .enable_vbus = NULL, -#if defined(__MHL_NEW_CBUS_MSC_CMD__) - .vbus_present = NULL, -#else .vbus_present = NULL, +#ifdef CONFIG_SAMSUNG_MHL_UNPOWERED + .get_vbus_status = sii9234_get_vbus_status, + .sii9234_otg_control = sii9234_otg_control, #endif - #ifdef CONFIG_EXTCON .extcon_name = "max77693-muic", #endif @@ -171,7 +256,9 @@ static int __init midas_mhl_init(void) printk(KERN_ERR "[MHL] adding i2c fail - nodevice\n"); return -ENODEV; } -#if defined(CONFIG_MACH_S2PLUS) || defined(CONFIG_MACH_P4NOTE) +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) + sii9234_pdata.ddc_i2c_num = 6; +#elif defined(CONFIG_MACH_P4NOTE) || defined(CONFIG_MACH_T0) sii9234_pdata.ddc_i2c_num = 5; #else sii9234_pdata.ddc_i2c_num = (system_rev == 3 ? 16 : 5); diff --git a/arch/arm/mach-exynos/midas-nfc.c b/arch/arm/mach-exynos/midas-nfc.c index c9c05f5..4f3dc87 100644 --- a/arch/arm/mach-exynos/midas-nfc.c +++ b/arch/arm/mach-exynos/midas-nfc.c @@ -16,12 +16,22 @@ static unsigned int nfc_gpio_table[][4] = { static inline void nfc_setup_gpio(void) { + int err = 0; int array_size = ARRAY_SIZE(nfc_gpio_table); u32 i, gpio; for (i = 0; i < array_size; i++) { gpio = nfc_gpio_table[i][0]; - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(nfc_gpio_table[i][1])); - s3c_gpio_setpull(gpio, nfc_gpio_table[i][3]); + + err = s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(nfc_gpio_table[i][1])); + if (err < 0) + pr_err("%s, s3c_gpio_cfgpin gpio(%d) fail(err = %d)\n", + __func__, i, err); + + err = s3c_gpio_setpull(gpio, nfc_gpio_table[i][3]); + if (err < 0) + pr_err("%s, s3c_gpio_setpull gpio(%d) fail(err = %d)\n", + __func__, i, err); + if (nfc_gpio_table[i][2] != 2) gpio_set_value(gpio, nfc_gpio_table[i][2]); } @@ -53,12 +63,17 @@ int __init midas_nfc_init(int i2c_bus) static int __init midas_nfc_init(void) { int ret = 0; -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M3) || defined(CONFIG_MACH_M0_CTC) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_CTC) #define I2C_BUSNUM_PN65N (system_rev == 3 ? 0 : 5) -#elif defined(CONFIG_MACH_M0) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) +#elif defined(CONFIG_MACH_M3) +#define I2C_BUSNUM_PN65N 12 +#elif defined(CONFIG_MACH_M0) #define I2C_BUSNUM_PN65N (system_rev == 3 ? 12 : 5) +#elif defined(CONFIG_MACH_T0) +#define I2C_BUSNUM_PN65N (system_rev == 0 ? 5 : 12) +#elif defined(CONFIG_MACH_BAFFIN) +#define I2C_BUSNUM_PN65N 5 #else #define I2C_BUSNUM_PN65N 12 #endif diff --git a/arch/arm/mach-exynos/midas-power.c b/arch/arm/mach-exynos/midas-power.c index 78318f2..46a02b6 100644 --- a/arch/arm/mach-exynos/midas-power.c +++ b/arch/arm/mach-exynos/midas-power.c @@ -24,7 +24,9 @@ #include <plat/gpio-cfg.h> #include <mach/gpio-midas.h> #include <mach/irqs.h> - +#if defined(CONFIG_MACH_SLP_PQ) +#include <asm/mach-types.h> +#endif #include <linux/mfd/max8997.h> #include <linux/mfd/max77686.h> #include <linux/mfd/max77693.h> @@ -281,6 +283,9 @@ static struct regulator_consumer_supply ldo3_supply[] = { REGULATOR_SUPPLY("DBVDD1", NULL), REGULATOR_SUPPLY("DBVDD2", NULL), REGULATOR_SUPPLY("DBVDD3", NULL), +#ifdef CONFIG_MACH_REDWOOD + REGULATOR_SUPPLY("VDDI", "s6d6aa1"), +#endif }; #else static struct regulator_consumer_supply ldo3_supply[] = {}; @@ -317,7 +322,8 @@ static struct regulator_consumer_supply ldo12_supply[] = { }; #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ - defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_DUOSCTC) || defined(CONFIG_MACH_M0_GRANDECTC) static struct regulator_consumer_supply ldo13_supply[] = { REGULATOR_SUPPLY("vusbhub_osc_1.8v", NULL), }; @@ -347,9 +353,11 @@ static struct regulator_consumer_supply ldo23_supply[] = { REGULATOR_SUPPLY("touch", NULL), }; -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \ - defined(CONFIG_MACH_GC1) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) ||\ + defined(CONFIG_MACH_SLP_T0_LTE) static struct regulator_consumer_supply ldo24_supply[] = { REGULATOR_SUPPLY("touch_1.8v", NULL), }; @@ -363,6 +371,9 @@ static struct regulator_consumer_supply ldo24_supply[] = { static struct regulator_consumer_supply ldo25_supply[] = { REGULATOR_SUPPLY("vlcd_3.3v", NULL), REGULATOR_SUPPLY("VCI", "s6e8aa0"), +#if defined(CONFIG_MACH_SLP_T0_LTE) + REGULATOR_SUPPLY("VCI", "ea8061"), +#endif }; static struct regulator_consumer_supply ldo26_supply[] = { @@ -392,6 +403,7 @@ static struct regulator_consumer_supply max77686_buck9 = static struct regulator_consumer_supply max77686_enp32khz[] = { REGULATOR_SUPPLY("lpo_in", "bcm47511"), + REGULATOR_SUPPLY("lpo_in", "bcm4752"), REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"), }; @@ -429,7 +441,8 @@ REGULATOR_INIT(ldo11, "VABB1_1.95V", 1950000, 1950000, 1, REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1, REGULATOR_CHANGE_STATUS, 0); #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ - defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_DUOSCTC) || defined(CONFIG_MACH_M0_GRANDECTC) REGULATOR_INIT(ldo13, "VUSBHUB_OSC_1.8V", 1800000, 1800000, 0, REGULATOR_CHANGE_STATUS, 1); #endif @@ -445,9 +458,11 @@ REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0, REGULATOR_CHANGE_STATUS, 1); REGULATOR_INIT(ldo23, "TSP_AVDD_3.3V", 3300000, 3300000, 0, REGULATOR_CHANGE_STATUS, 1); -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \ - defined(CONFIG_MACH_GC1) +#if defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ + defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) ||\ + defined(CONFIG_MACH_SLP_T0_LTE) REGULATOR_INIT(ldo24, "VDD_1.8V_TSP", 1800000, 1800000, 0, REGULATOR_CHANGE_STATUS, 1); #else @@ -477,6 +492,25 @@ static struct regulator_init_data ldo24_pq11_init_data = { .num_consumer_supplies = 1, .consumer_supplies = ldo24_supply, }; + +static struct regulator_init_data ldo25_redwood_init_data = { + .constraints = { + .name = "LED_A_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .always_on = 0, + .boot_on = 0, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 0, + .disabled = 1, + } + }, + .num_consumer_supplies = 1, + .consumer_supplies = ldo25_supply, +}; + #endif static struct regulator_init_data max77686_buck1_data = { @@ -587,7 +621,8 @@ static struct max77686_regulator_data max77686_regulators[] = { {MAX77686_LDO11, &ldo11_init_data,}, {MAX77686_LDO12, &ldo12_init_data,}, #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ - defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_DUOSCTC) || defined(CONFIG_MACH_M0_GRANDECTC) {MAX77686_LDO13, &ldo13_init_data,}, #endif {MAX77686_LDO14, &ldo14_init_data,}, @@ -609,7 +644,8 @@ struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = { [MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY}, [MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY}, #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ - defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) + defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1) || \ + defined(CONFIG_MACH_M0_DUOSCTC) || defined(CONFIG_MACH_M0_GRANDECTC) [MAX77686_LDO13] = {MAX77686_LDO13, MAX77686_OPMODE_NORMAL}, #endif [MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY}, @@ -786,6 +822,25 @@ static int __init regulator_init_with_rev(void) } postcore_initcall(regulator_init_with_rev); + +static const char redwood_ldo25_name[] = "led_a_2.8v"; +static int __init regulator_init_with_redwood(void) +{ + /* SLP PQ redwood */ + if (__machine_arch_type == MACH_TYPE_REDWOOD) { + ldo25_supply[0].supply = redwood_ldo25_name; + + memcpy(&ldo25_init_data, &ldo25_redwood_init_data, + sizeof(struct regulator_init_data)); + } + + return 0; +} + +postcore_initcall(regulator_init_with_redwood); + + + #endif /* CONFIG_MACH_SLP_PQ */ #endif /* CONFIG_MFD_MAX77693 */ @@ -1112,13 +1167,8 @@ struct s5m_platform_data exynos4_s5m8767_info = { void midas_power_init(void) { -#ifdef CONFIG_MACH_S2PLUS - ldo8_init_data.constraints.always_on = 1; - ldo13_init_data.constraints.always_on = 1; -#else ldo8_init_data.constraints.always_on = 1; ldo10_init_data.constraints.always_on = 1; -#endif } /* End of S5M8767 */ diff --git a/arch/arm/mach-exynos/midas-sensor.c b/arch/arm/mach-exynos/midas-sensor.c index 6c8385c..5bdbee7 100644 --- a/arch/arm/mach-exynos/midas-sensor.c +++ b/arch/arm/mach-exynos/midas-sensor.c @@ -2,7 +2,12 @@ #include <linux/gpio.h> #include <linux/i2c.h> #include <linux/sensor/sensors_core.h> +#ifdef CONFIG_SENSORS_AK8975C #include <linux/sensor/ak8975.h> +#endif +#ifdef CONFIG_SENSORS_AK8963C +#include <linux/sensor/ak8963.h> +#endif #include <linux/sensor/k3dh.h> #include <linux/sensor/gp2a.h> #include <linux/sensor/lsm330dlc_accel.h> @@ -11,18 +16,49 @@ #include <linux/sensor/cm36651.h> #include <linux/sensor/cm3663.h> #include <linux/sensor/bh1721.h> - +#include <linux/delay.h> #include <plat/gpio-cfg.h> #include <mach/regs-gpio.h> #include <mach/gpio.h> #include "midas.h" -static int accel_get_position(void); +#ifdef CONFIG_SENSORS_SSP +#include <linux/ssp_platformdata.h> +#endif + + +#if defined(CONFIG_SENSORS_LSM330DLC) ||\ + defined(CONFIG_SENSORS_K3DH) +static int stm_get_position(void); static struct accel_platform_data accel_pdata = { - .accel_get_position = accel_get_position, + .accel_get_position = stm_get_position, .axis_adjust = true, }; +#endif + +#ifdef CONFIG_SENSORS_LSM330DLC +static struct gyro_platform_data gyro_pdata = { + .gyro_get_position = stm_get_position, + .axis_adjust = true, +}; +#endif + +#ifdef CONFIG_SENSORS_SSP +static int wakeup_mcu(void); +static int check_mcu_busy(void); +static int check_mcu_ready(void); +static int set_mcu_reset(int on); +static int check_ap_rev(void); + +static struct ssp_platform_data ssp_pdata = { + .wakeup_mcu = wakeup_mcu, + .check_mcu_busy = check_mcu_busy, + .check_mcu_ready = check_mcu_ready, + .set_mcu_reset = set_mcu_reset, + .check_ap_rev = check_ap_rev, +}; +#endif static struct i2c_board_info i2c_devs1[] __initdata = { #ifdef CONFIG_SENSORS_LSM330DLC @@ -32,25 +68,94 @@ static struct i2c_board_info i2c_devs1[] __initdata = { }, { I2C_BOARD_INFO("lsm330dlc_gyro", (0xD6 >> 1)), + .platform_data = &gyro_pdata, }, #elif defined(CONFIG_SENSORS_K3DH) { I2C_BOARD_INFO("k3dh", 0x19), .platform_data = &accel_pdata, }, +#elif defined(CONFIG_SENSORS_SSP) + { + I2C_BOARD_INFO("ssp", 0x18), + .platform_data = &ssp_pdata, + .irq = GPIO_MCU_AP_INT, + }, #endif }; -static int accel_get_position(void) +#ifdef CONFIG_SENSORS_SSP +static int initialize_ssp_gpio(void) { - int position = 0; + int err; -#if defined(CONFIG_MACH_C1VZW) /* C1_SPR */ - if (system_rev == 1) - position = 3; /* top/lower-left */ + err = gpio_request(GPIO_AP_MCU_INT, "AP_MCU_INT_PIN"); + if (err) + printk(KERN_ERR "failed to request AP_MCU_INT for SSP\n"); + + s3c_gpio_cfgpin(GPIO_AP_MCU_INT, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_AP_MCU_INT, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_AP_MCU_INT, 1); + + err = gpio_request(GPIO_MCU_AP_INT_2, "MCU_AP_INT_PIN2"); + if (err) + printk(KERN_ERR "failed to request AP_MCU_INT for SSP\n"); + s3c_gpio_cfgpin(GPIO_MCU_AP_INT_2, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_MCU_AP_INT_2, S3C_GPIO_PULL_NONE); + + err = gpio_request(GPIO_MCU_NRST, "AP_MCU_RESET"); + if (err) + printk(KERN_ERR "failed to request AP_MCU_RESET for SSP\n"); + s3c_gpio_cfgpin(GPIO_MCU_NRST, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_MCU_NRST, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_MCU_NRST, 1); + + return 0; +} + +static int wakeup_mcu(void) +{ + gpio_set_value(GPIO_AP_MCU_INT, 0); + udelay(1); + gpio_set_value(GPIO_AP_MCU_INT, 1); + + return 0; +} + +static int set_mcu_reset(int on) +{ + if (on == 0) + gpio_set_value(GPIO_MCU_NRST, 0); else - position = 2; /* top/lower-right */ -#elif defined(CONFIG_MACH_C1CTC) + gpio_set_value(GPIO_MCU_NRST, 1); + + return 0; +} + +static int check_mcu_busy(void) +{ + return gpio_get_value(GPIO_MCU_AP_INT); +} + +static int check_mcu_ready(void) +{ + return gpio_get_value(GPIO_MCU_AP_INT_2); +} + +static int check_ap_rev(void) +{ + return system_rev; +} + +#endif + +#if defined(CONFIG_SENSORS_LSM330DLC) || \ + defined(CONFIG_SENSORS_K3DH) +static int stm_get_position(void) +{ + int position = 0; + +#if defined(CONFIG_MACH_M3) /* C2_SPR, M3 */ position = 2; /* top/lower-right */ #elif defined(CONFIG_MACH_M0_CMCC) if (system_rev == 2) @@ -69,8 +174,6 @@ static int accel_get_position(void) position = 4; /* bottom/upper-left */ else position = 3; /* top/lower-left */ -#elif defined(CONFIG_MACH_S2PLUS) - position = 3; /* top/lower-left */ #elif defined(CONFIG_MACH_P4NOTE) position = 4; /* bottom/upper-left */ #elif defined(CONFIG_MACH_M0) @@ -88,14 +191,21 @@ static int accel_get_position(void) position = 3; /* top/lower-left */ else position = 2; /* top/lower-right */ +#elif defined(CONFIG_MACH_GC1) + if (system_rev >= 6) + position = 6; /* bottom/lower-right */ + else if (system_rev == 2 || system_rev == 3) + position = 1; /* top/upper-right */ + else + position = 0; /* top/upper-left */ +#elif defined(CONFIG_MACH_BAFFIN) + position = 6; /* bottom/lower-right */ #else /* Common */ position = 2; /* top/lower-right */ #endif return position; } -#if defined(CONFIG_SENSORS_LSM330DLC) || \ - defined(CONFIG_SENSORS_K3DH) static int accel_gpio_init(void) { int ret = gpio_request(GPIO_ACC_INT, "accelerometer_irq"); @@ -103,7 +213,7 @@ static int accel_gpio_init(void) pr_info("%s\n", __func__); if (ret) { - pr_err("%s, Failed to request gpio lsm330dlc_accel_irq(%d)\n", + pr_err("%s, Failed to request gpio accelerometer_irq(%d)\n", __func__, ret); return ret; } @@ -201,22 +311,22 @@ static int optical_gpio_init(void) /* Depends window, threshold is needed to be set */ static u8 cm36651_get_threshold(void) { - u8 threshold = 17; + u8 threshold = 15; /* Add model config and threshold here. */ -#if defined(CONFIG_MACH_M0) - if (system_rev >= 12) - threshold = 15; +#if defined(CONFIG_MACH_M0_DUOSCTC) + threshold = 13; +#elif defined(CONFIG_MACH_M0) + threshold = 15; #elif defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) ||\ defined(CONFIG_MACH_C1_KOR_LGT) if (system_rev >= 6) - threshold = 13; -#elif defined(CONFIG_MACH_C1VZW) - if (system_rev >= 11) - threshold = 13; + threshold = 15; +#elif defined(CONFIG_MACH_M3) + threshold = 14; #elif defined(CONFIG_MACH_C1) if (system_rev >= 7) - threshold = 13; + threshold = 15; #endif return threshold; @@ -255,22 +365,30 @@ static struct i2c_board_info i2c_devs9_emul[] __initdata = { { I2C_BOARD_INFO("gp2a", (0x72 >> 1)), }, -#elif defined(CONFIG_SENSORS_CM36651) +#endif +#if defined(CONFIG_SENSORS_CM36651) { I2C_BOARD_INFO("cm36651", (0x30 >> 1)), .platform_data = &cm36651_pdata, }, -#elif defined(CONFIG_SENSORS_CM3663) +#endif +#if defined(CONFIG_SENSORS_CM3663) { I2C_BOARD_INFO("cm3663", (0x20)), .irq = GPIO_PS_ALS_INT, .platform_data = &cm3663_pdata, }, -#elif defined(CONFIG_SENSORS_BH1721) +#endif +#if defined(CONFIG_SENSORS_BH1721) { I2C_BOARD_INFO("bh1721fvc", 0x23), }, #endif +#if defined(CONFIG_SENSORS_AL3201) + { + I2C_BOARD_INFO("AL3201", 0x1c), + }, +#endif }; #ifdef CONFIG_SENSORS_AK8975C @@ -305,6 +423,53 @@ static int ak8975c_gpio_init(void) } #endif +#ifdef CONFIG_SENSORS_AK8963C +static struct akm8963_platform_data akm8963_pdata = { + .gpio_data_ready_int = GPIO_MSENSOR_INT, + .layout = 1, + .outbit = 1, + .gpio_RST = GPIO_MSENSE_RST_N, +}; + +static struct i2c_board_info i2c_devs10_emul[] __initdata = { + { + I2C_BOARD_INFO("ak8963", 0x0C), + .platform_data = &akm8963_pdata, + }, +}; + +static int ak8963c_gpio_init(void) +{ + int ret; + + pr_info("%s\n", __func__); + + ret = gpio_request(GPIO_MSENSOR_INT, "gpio_akm_int"); + if (ret) { + pr_err("%s, Failed to request gpio akm_int.(%d)\n", + __func__, ret); + return ret; + } + s5p_register_gpio_interrupt(GPIO_MSENSOR_INT); + s3c_gpio_setpull(GPIO_MSENSOR_INT, S3C_GPIO_PULL_DOWN); + s3c_gpio_cfgpin(GPIO_MSENSOR_INT, S3C_GPIO_SFN(0xF)); + i2c_devs10_emul[0].irq = gpio_to_irq(GPIO_MSENSOR_INT); + + ret = gpio_request(GPIO_MSENSE_RST_N, "gpio_akm_rst"); + if (ret) { + pr_err("%s, Failed to request gpio akm_rst.(%d)\n", + __func__, ret); + return ret; + } + s3c_gpio_cfgpin(GPIO_MSENSE_RST_N, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_MSENSE_RST_N, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_MSENSE_RST_N, 1); + + return ret; +} +#endif + + #ifdef CONFIG_SENSORS_LPS331 static int lps331_gpio_init(void) { @@ -359,6 +524,8 @@ static int __init midas_sensor_init(void) pr_err("%s, accel_gpio_init fail(err=%d)\n", __func__, ret); return ret; } +#elif defined(CONFIG_SENSORS_SSP) + initialize_ssp_gpio(); #endif ret = i2c_add_devices(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); if (ret < 0) { @@ -379,7 +546,7 @@ static int __init midas_sensor_init(void) pr_err("%s, i2c9 adding i2c fail(err=%d)\n", __func__, ret); return ret; } -#elif defined(CONFIG_SENSORS_BH1721) +#elif defined(CONFIG_SENSORS_BH1721) || defined(CONFIG_SENSORS_AL3201) ret = i2c_add_devices(9, i2c_devs9_emul, ARRAY_SIZE(i2c_devs9_emul)); if (ret < 0) { pr_err("%s, i2c9 adding i2c fail(err=%d)\n", __func__, ret); @@ -409,12 +576,27 @@ static int __init midas_sensor_init(void) return ret; } #endif +#ifdef CONFIG_SENSORS_AK8963C + ret = ak8963c_gpio_init(); + if (ret < 0) { + pr_err("%s, ak8963c_gpio_init fail(err=%d)\n", + __func__, ret); + return ret; + } + ret = i2c_add_devices(10, i2c_devs10_emul, + ARRAY_SIZE(i2c_devs10_emul)); + if (ret < 0) { + pr_err("%s, i2c10 adding i2c fail(err=%d)\n", + __func__, ret); + return ret; + } +#endif /* Pressure Sensor */ #ifdef CONFIG_SENSORS_LPS331 ret = lps331_gpio_init(); if (ret < 0) { - pr_err("%s, ak8975c_gpio_init fail(err=%d)\n", __func__, ret); + pr_err("%s, lps331_gpio_init fail(err=%d)\n", __func__, ret); return ret; } ret = i2c_add_devices(11, i2c_devs11_emul, ARRAY_SIZE(i2c_devs11_emul)); diff --git a/arch/arm/mach-exynos/midas-sound.c b/arch/arm/mach-exynos/midas-sound.c index 80d2d45..28c7cbd 100644 --- a/arch/arm/mach-exynos/midas-sound.c +++ b/arch/arm/mach-exynos/midas-sound.c @@ -45,12 +45,29 @@ #include <linux/i2c/fm34_we395.h> #endif +#if defined(CONFIG_FM_SI4709_MODULE) || defined(CONFIG_FM_SI4705) || \ + defined(CONFIG_FM_SI4705_MODULE) +#include <linux/i2c/si47xx_common.h> +#endif + + #ifdef CONFIG_AUDIENCE_ES305 #include <linux/i2c/es305.h> #endif static bool midas_snd_mclk_enabled; +#if defined(CONFIG_FM_SI4705) +struct si47xx_info { +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M0_CTC) + int gpio_sw; +#endif + int gpio_int; + int gpio_rst; +} si47xx_data; + +#endif + #ifdef CONFIG_ARCH_EXYNOS5 #define I2C_NUM_2MIC 4 #define I2C_NUM_CODEC 7 @@ -184,10 +201,20 @@ static struct wm8994_drc_cfg drc_value[] = { .regs[0] = 0x008c, .regs[1] = 0x0253, .regs[2] = 0x0028, - .regs[3] = 0x028a, + .regs[3] = 0x028c, .regs[4] = 0x0000, }, #endif +#if defined(CONFIG_MACH_P4NOTE) +{ + .name = "cam rec DRC", + .regs[0] = 0x019B, + .regs[1] = 0x0844, + .regs[2] = 0x0408, + .regs[3] = 0x0108, + .regs[4] = 0x0120, + }, +#endif }; static struct wm8994_pdata wm1811_pdata = { @@ -222,7 +249,13 @@ static struct wm8994_pdata wm1811_pdata = { .jd_ext_cap = 1, /* Regulated mode at highest output voltage */ +#ifdef CONFIG_TARGET_LOCALE_KOR + .micbias = {0x22, 0x22}, +#elif defined(CONFIG_MACH_C1_USA_ATT) + .micbias = {0x2f, 0x29}, +#else .micbias = {0x2f, 0x27}, +#endif .micd_lvl_sel = 0xFF, @@ -231,14 +264,16 @@ static struct wm8994_pdata wm1811_pdata = { #ifdef CONFIG_TARGET_LOCALE_KOR .lineout2_diff = 0, #endif -#ifdef CONFIG_MACH_C1 +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_BAFFIN) .lineout1fb = 0, #else .lineout1fb = 1, #endif #if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1_KOR_SKT) || \ defined(CONFIG_MACH_C1_KOR_KT) || defined(CONFIG_MACH_C1_KOR_LGT) || \ - defined(CONFIG_MACH_P4NOTE) || defined(CONFIG_MACH_GC1) + defined(CONFIG_MACH_P4NOTE) || defined(CONFIG_MACH_GC1) || \ + defined(CONFIG_MACH_C1_USA_ATT) || defined(CONFIG_MACH_T0) || \ + defined(CONFIG_MACH_M3) || defined(CONFIG_MACH_BAFFIN) .lineout2fb = 0, #else .lineout2fb = 1, @@ -270,6 +305,7 @@ static struct fm34_platform_data fm34_we395_pdata_rev05 = { .set_mclk = midas_snd_set_mclk, }; #endif + static struct i2c_board_info i2c_2mic[] __initdata = { { I2C_BOARD_INFO("fm34_we395", (0xC0 >> 1)), /* 2MIC */ @@ -277,7 +313,7 @@ static struct i2c_board_info i2c_2mic[] __initdata = { }, }; -#if defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1_KOR_LGT) static struct i2c_gpio_platform_data gpio_i2c_fm34 = { .sda_pin = GPIO_FM34_SDA, .scl_pin = GPIO_FM34_SCL, @@ -291,6 +327,94 @@ struct platform_device s3c_device_fm34 = { #endif #endif +#if defined(CONFIG_FM_SI4709_MODULE) || defined(CONFIG_FM_SI4705) || \ + defined(CONFIG_FM_SI4705_MODULE) +static void fmradio_power(int on) +{ +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M0_CTC) + gpio_set_value(si47xx_data.gpio_sw, GPIO_LEVEL_HIGH); +#endif + if (on) { + gpio_request(GPIO_FM_INT, "GPC1"); + gpio_direction_output(GPIO_FM_INT, 1); + gpio_set_value(si47xx_data.gpio_rst, GPIO_LEVEL_LOW); + gpio_set_value(GPIO_FM_INT, GPIO_LEVEL_LOW); + usleep_range(5, 10); + gpio_set_value(si47xx_data.gpio_rst, GPIO_LEVEL_HIGH); + usleep_range(10, 15); + gpio_set_value(GPIO_FM_INT, GPIO_LEVEL_HIGH); + + s3c_gpio_cfgpin(GPIO_FM_INT, S3C_GPIO_SFN(0xF)); + gpio_free(GPIO_FM_INT); + } else { + gpio_set_value(si47xx_data.gpio_rst, GPIO_LEVEL_LOW); + } +} + +static struct si47xx_platform_data si47xx_pdata = { +#if defined(CONFIG_MACH_M0_CTC) + .rx_vol = {0x0, 0x15, 0x18, 0x1B, 0x1E, 0x21, 0x24, 0x27, + 0x2A, 0x2D, 0x30, 0x33, 0x36, 0x39, 0x3C, 0x3F}, +#else + .rx_vol = {0x0, 0x13, 0x16, 0x19, 0x1C, 0x1F, 0x22, 0x25, + 0x28, 0x2B, 0x2E, 0x31, 0x34, 0x37, 0x3A, 0x3D}, +#endif + .power = fmradio_power, +}; + +static struct i2c_gpio_platform_data gpio_i2c_data19 = { + .sda_pin = GPIO_FM_SDA, + .scl_pin = GPIO_FM_SCL, +}; + +struct platform_device s3c_device_i2c19 = { + .name = "i2c-gpio", + .id = 19, + .dev.platform_data = &gpio_i2c_data19, +}; + +/* I2C19 */ +static struct i2c_board_info i2c_devs19_emul[] __initdata = { +#if defined(CONFIG_FM_SI4705) || defined(CONFIG_FM_SI4705_MODULE) + { + I2C_BOARD_INFO("Si47xx", (0x22 >> 1)), + .platform_data = &si47xx_pdata, +#if defined(CONFIG_MACH_M0_DUOSCTC) + .irq = IRQ_EINT(4), +#else + .irq = IRQ_EINT(11), +#endif + }, +#endif +#ifdef CONFIG_FM_SI4709_MODULE + { + I2C_BOARD_INFO("Si4709", (0x20 >> 1)), + }, +#endif + +}; +#endif + +static void m0_gpio_init(void) +{ +#ifdef CONFIG_FM_SI4705 +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M0_CTC) + si47xx_data.gpio_sw = GPIO_FM_MIC_SW; +#endif + + si47xx_data.gpio_rst = GPIO_FM_RST; + s3c_gpio_setpull(GPIO_FM_INT, S3C_GPIO_PULL_UP); + + if (gpio_is_valid(si47xx_data.gpio_rst)) { + if (gpio_request(si47xx_data.gpio_rst, "GPC1")) + debug(KERN_ERR "Failed to request " + "FM_RST!\n\n"); + gpio_direction_output(si47xx_data.gpio_rst, GPIO_LEVEL_LOW); + } +#endif +} + + #ifdef CONFIG_AUDIENCE_ES305 static struct es305_platform_data es305_pdata = { .gpio_wakeup = GPIO_ES305_WAKEUP, @@ -307,17 +431,24 @@ static struct i2c_board_info i2c_2mic[] __initdata = { #endif static struct platform_device *midas_sound_devices[] __initdata = { -#if defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1_KOR_LGT) #ifdef CONFIG_FM34_WE395 &s3c_device_fm34, #endif #endif +#if defined(CONFIG_FM_SI4709_MODULE) || defined(CONFIG_FM_SI4705) || \ + defined(CONFIG_FM_SI4705_MODULE) + &s3c_device_i2c19, +#endif + }; void __init midas_sound_init(void) { printk(KERN_INFO "Sound: start %s\n", __func__); + m0_gpio_init(); + platform_add_devices(midas_sound_devices, ARRAY_SIZE(midas_sound_devices)); @@ -335,6 +466,11 @@ void __init midas_sound_init(void) i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811, ARRAY_SIZE(i2c_wm1811)); +#elif defined(CONFIG_MACH_GC1) + SET_PLATDATA_CODEC(NULL); + i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811, + ARRAY_SIZE(i2c_wm1811)); + #else if (system_rev != 3 && system_rev >= 0) { SET_PLATDATA_CODEC(NULL); @@ -362,4 +498,11 @@ void __init midas_sound_init(void) SET_PLATDATA_2MIC(NULL); i2c_register_board_info(I2C_NUM_2MIC, i2c_2mic, ARRAY_SIZE(i2c_2mic)); #endif +#if defined(CONFIG_FM_SI4709_MODULE) || defined(CONFIG_FM_SI4705) || \ + defined(CONFIG_FM_SI4705_MODULE) + i2c_register_board_info(19, i2c_devs19_emul, + ARRAY_SIZE(i2c_devs19_emul)); +#endif + } + diff --git a/arch/arm/mach-exynos/midas-thermistor.c b/arch/arm/mach-exynos/midas-thermistor.c index 999a56e..27c7e05 100644 --- a/arch/arm/mach-exynos/midas-thermistor.c +++ b/arch/arm/mach-exynos/midas-thermistor.c @@ -24,6 +24,11 @@ #include <mach/sec_thermistor.h> #endif +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) +extern int siopLevellimit; +#endif + #ifdef CONFIG_S3C_ADC #if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_P4NOTE) static struct adc_table_data ap_adc_temper_table_battery[] = { @@ -130,7 +135,6 @@ static struct adc_table_data ap_adc_temper_table_battery[] = { { 1856, -200 }, }; #elif defined(CONFIG_MACH_C1) -#if defined(CONFIG_TARGET_LOCALE_KOR) static struct adc_table_data ap_adc_temper_table_battery[] = { { 178, 800 }, { 186, 790 }, @@ -234,21 +238,390 @@ static struct adc_table_data ap_adc_temper_table_battery[] = { { 1805, -190 }, { 1824, -200 }, }; -#else +#elif defined(CONFIG_MACH_GC1)/*Sample # 3*/ static struct adc_table_data ap_adc_temper_table_battery[] = { - { 305, 650 }, - { 566, 430 }, - { 1494, 0 }, - { 1571, -50 }, + { 250, 700 }, + { 259, 690 }, + { 270, 680 }, + { 279, 670 }, + { 289, 660 }, + { 297, 650 }, + { 312, 640 }, + { 314, 630 }, + { 324, 620 }, + { 336, 610 }, + { 344, 600 }, + { 358, 590 }, + { 369, 580 }, + { 378, 570 }, + { 390, 560 }, + { 405, 550 }, + { 419, 540 }, + { 433, 530 }, + { 447, 520 }, + { 464, 510 }, + { 471, 500 }, + { 485, 490 }, + { 510, 480 }, + { 515, 470 }, + { 537, 460 }, + { 552, 450 }, + { 577, 440 }, + { 591, 430 }, + { 606, 420 }, + { 621, 410 }, + { 636, 400 }, + { 655, 390 }, + { 677, 380 }, + { 711, 370 }, + { 727, 360 }, + { 730, 350 }, + { 755, 340 }, + { 776, 330 }, + { 795, 320 }, + { 819, 310 }, + { 832, 300 }, + { 855, 290 }, + { 883, 280 }, + { 895, 270 }, + { 939, 260 }, + { 946, 250 }, + { 958, 240 }, + { 974, 230 }, + { 986, 220 }, + { 1023, 210 }, + { 1055, 200 }, + { 1065, 190 }, + { 1118, 180 }, + { 1147, 170 }, + { 1171, 160 }, + { 1190, 150 }, + { 1220, 140 }, + { 1224, 130 }, + { 1251, 120 }, + { 1271, 110 }, + { 1316, 100 }, + { 1325, 90 }, + { 1333, 80 }, + { 1365, 70 }, + { 1382, 60 }, + { 1404, 50 }, + { 1445, 40 }, + { 1461, 30 }, + { 1469, 20 }, + { 1492, 10 }, + { 1518, 0 }, + { 1552, -10 }, + { 1560, -20 }, + { 1588, -30 }, + { 1592, -40 }, + { 1613, -50 }, + { 1632, -60 }, + { 1647, -70 }, + { 1661, -80 }, + { 1685, -90 }, + { 1692, -100 }, }; -#endif -#elif defined(CONFIG_MACH_S2PLUS) +#elif defined(CONFIG_MACH_M3) static struct adc_table_data ap_adc_temper_table_battery[] = { - { 305, 650 }, - { 566, 430 }, - { 1494, 0 }, - { 1571, -50 }, + { 264, 700 }, + { 293, 670 }, + { 315, 650 }, + { 338, 630 }, + { 348, 620 }, + { 371, 600 }, + { 436, 550 }, + { 509, 500 }, + { 599, 450 }, + { 629, 430 }, + { 651, 420 }, + { 692, 400 }, + { 790, 350 }, + { 909, 300 }, + { 1027, 250 }, + { 1141, 200 }, + { 1246, 150 }, + { 1364, 100 }, + { 1460, 50 }, + { 1573, 0 }, + { 1614, -30 }, + { 1650, -50 }, + { 1735, -100 }, + { 1800, -150 }, + { 1857, -200 }, + { 1910, -250 }, + { 1970, -300 }, +}; +#elif defined(CONFIG_MACH_T0) +#if defined(CONFIG_TARGET_LOCALE_KOR) +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 200, 800 }, + { 207, 790 }, + { 214, 780 }, + { 221, 770 }, + { 228, 760 }, + { 235, 750 }, + { 248, 740 }, + { 260, 730 }, + { 273, 720 }, + { 286, 710 }, + { 299, 700 }, + { 310, 690 }, + { 321, 680 }, + { 332, 670 }, + { 345, 660 }, + { 355, 650 }, + { 370, 640 }, + { 381, 630 }, + { 393, 620 }, + { 406, 610 }, + { 423, 600 }, + { 435, 590 }, + { 448, 580 }, + { 460, 570 }, + { 473, 560 }, + { 485, 550 }, + { 498, 540 }, + { 511, 530 }, + { 524, 520 }, + { 537, 510 }, + { 550, 500 }, + { 566, 490 }, + { 582, 480 }, + { 598, 470 }, + { 614, 460 }, + { 630, 450 }, + { 649, 440 }, + { 668, 430 }, + { 687, 420 }, + { 706, 410 }, + { 725, 400 }, + { 744, 390 }, + { 763, 380 }, + { 782, 370 }, + { 801, 360 }, + { 820, 350 }, + { 841, 340 }, + { 862, 330 }, + { 883, 320 }, + { 904, 310 }, + { 925, 300 }, + { 946, 290 }, + { 967, 280 }, + { 988, 270 }, + { 1009, 260 }, + { 1030, 250 }, + { 1050, 240 }, + { 1070, 230 }, + { 1090, 220 }, + { 1110, 210 }, + { 1130, 200 }, + { 1154, 190 }, + { 1178, 180 }, + { 1202, 170 }, + { 1226, 160 }, + { 1250, 150 }, + { 1272, 140 }, + { 1294, 130 }, + { 1315, 120 }, + { 1337, 110 }, + { 1359, 100 }, + { 1381, 90 }, + { 1403, 80 }, + { 1424, 70 }, + { 1446, 60 }, + { 1468, 50 }, + { 1489, 40 }, + { 1510, 30 }, + { 1532, 20 }, + { 1553, 10 }, + { 1574, 0 }, + { 1591, -10 }, + { 1609, -20 }, + { 1626, -30 }, + { 1644, -40 }, + { 1661, -50 }, + { 1676, -60 }, + { 1691, -70 }, + { 1707, -80 }, + { 1722, -90 }, + { 1737, -100 }, + { 1749, -110 }, + { 1760, -120 }, + { 1772, -130 }, + { 1783, -140 }, + { 1795, -150 }, + { 1803, -160 }, + { 1811, -170 }, + { 1819, -180 }, + { 1827, -190 }, + { 1836, -200 }, +}; +#elif defined(CONFIG_MACH_T0_EUR_LTE) || defined(CONFIG_MACH_T0_USA_ATT) +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 332, 650 }, + { 389, 600 }, + { 460, 550 }, + { 530, 500 }, + { 617, 450 }, + { 735, 400 }, + { 803, 350 }, + { 913, 300 }, + { 992, 250 }, + { 1126, 200 }, + { 1265, 150 }, + { 1370, 100 }, + { 1475, 50 }, + { 1530, 0 }, + { 1635, -50 }, + { 1724, -100 }, + { 1803, -150 }, + { 1855, -200 }, +}; +#elif defined(CONFIG_MACH_T0_USA_VZW) || defined(CONFIG_MACH_T0_USA_SPR) || \ + defined(CONFIG_MACH_T0_USA_USCC) +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 193, 800 }, + { 222, 750 }, + { 272, 700 }, + { 320, 650 }, + { 379, 600 }, + { 439, 550 }, + { 519, 500 }, + { 555, 480 }, + { 605, 450 }, + { 698, 400 }, + { 802, 350 }, + { 906, 300 }, + { 1016, 250 }, + { 1127, 200 }, + { 1247, 150 }, + { 1360, 100 }, + { 1467, 50 }, + { 1567, 0 }, + { 1633, -50 }, + { 1725, -100 }, + { 1790, -150 }, + { 1839, -200 }, + { 1903, -250 }, +}; +#elif defined(CONFIG_MACH_BAFFIN) +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 178, 800 }, + { 186, 790 }, + { 193, 780 }, + { 198, 770 }, + { 204, 760 }, + { 210, 750 }, + { 220, 740 }, + { 226, 730 }, + { 232, 720 }, + { 247, 710 }, + { 254, 700 }, + { 261, 690 }, + { 270, 680 }, + { 278, 670 }, + { 285, 660 }, + { 292, 650 }, + { 304, 640 }, + { 319, 630 }, + { 325, 620 }, + { 331, 610 }, + { 343, 600 }, + { 354, 590 }, + { 373, 580 }, + { 387, 570 }, + { 392, 560 }, + { 408, 550 }, + { 422, 540 }, + { 433, 530 }, + { 452, 520 }, + { 466, 510 }, + { 479, 500 }, + { 497, 490 }, + { 510, 480 }, + { 529, 470 }, + { 545, 460 }, + { 562, 450 }, + { 578, 440 }, + { 594, 430 }, + { 620, 420 }, + { 632, 410 }, + { 651, 400 }, + { 663, 390 }, + { 681, 380 }, + { 705, 370 }, + { 727, 360 }, + { 736, 350 }, + { 778, 340 }, + { 793, 330 }, + { 820, 320 }, + { 834, 310 }, + { 859, 300 }, + { 872, 290 }, + { 891, 280 }, + { 914, 270 }, + { 939, 260 }, + { 951, 250 }, + { 967, 240 }, + { 999, 230 }, + { 1031, 220 }, + { 1049, 210 }, + { 1073, 200 }, + { 1097, 190 }, + { 1128, 180 }, + { 1140, 170 }, + { 1171, 160 }, + { 1188, 150 }, + { 1198, 140 }, + { 1223, 130 }, + { 1236, 120 }, + { 1274, 110 }, + { 1290, 100 }, + { 1312, 90 }, + { 1321, 80 }, + { 1353, 70 }, + { 1363, 60 }, + { 1404, 50 }, + { 1413, 40 }, + { 1444, 30 }, + { 1461, 20 }, + { 1470, 10 }, + { 1516, 0 }, + { 1522, -10 }, + { 1533, -20 }, + { 1540, -30 }, + { 1558, -40 }, + { 1581, -50 }, + { 1595, -60 }, + { 1607, -70 }, + { 1614, -80 }, + { 1627, -90 }, + { 1655, -100 }, + { 1664, -110 }, + { 1670, -120 }, + { 1676, -130 }, + { 1692, -140 }, + { 1713, -150 }, + { 1734, -160 }, + { 1746, -170 }, + { 1789, -180 }, + { 1805, -190 }, + { 1824, -200 }, +}; +#else /* T0 3G(default) */ +static struct adc_table_data ap_adc_temper_table_battery[] = { + { 358, 600 }, + { 500, 500 }, + { 698, 400 }, + { 898, 300 }, + { 1132, 200 }, + { 1363, 100 }, + { 1574, 0 }, + { 1732, -100 }, + { 1860, -200 }, }; +#endif #else /* sample */ static struct adc_table_data ap_adc_temper_table_battery[] = { { 305, 650 }, @@ -322,6 +695,39 @@ int convert_adc(int adc_data, int channel) #endif #ifdef CONFIG_SEC_THERMISTOR +#if defined(CONFIG_MACH_GC1) +static struct sec_therm_adc_table temper_table_ap[] = { + {241, 700}, + {260, 650}, + {301, 600}, + {351, 550}, + {367, 540}, + {383, 530}, + {399, 520}, + {415, 510}, + {431, 500}, + {442, 490}, + {454, 480}, + {465, 470}, + {477, 460}, + {488, 450}, + {508, 440}, + {528, 430}, + {548, 420}, + {568, 410}, + {587, 400}, + {604, 390}, + {622, 380}, + {639, 370}, + {657, 360}, + {674, 350}, + {696, 340}, + {718, 330}, + {740, 320}, + {762, 310}, + {784, 300}, +}; +#else static struct sec_therm_adc_table temper_table_ap[] = { {196, 700}, {211, 690}, @@ -347,8 +753,8 @@ static struct sec_therm_adc_table temper_table_ap[] = { {498, 500}, {509, 490}, {520, 480}, - {529, 460}, - {538, 470}, + {529, 470}, + {538, 460}, {547, 450}, {556, 440}, {564, 430}, @@ -366,6 +772,7 @@ static struct sec_therm_adc_table temper_table_ap[] = { {801, 310}, {822, 300}, }; +#endif /* when the next level is same as prev, returns -1 */ static int get_midas_siop_level(int temp) @@ -377,24 +784,24 @@ static int get_midas_siop_level(int temp) #if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ defined(CONFIG_MACH_C1_KOR_LGT) if (temp > prev_temp) { - if (temp >= 490) + if (temp >= 540) level = 4; - else if (temp >= 480) + else if (temp >= 530) level = 3; - else if (temp >= 450) + else if (temp >= 480) level = 2; - else if (temp >= 420) + else if (temp >= 440) level = 1; else level = 0; } else { - if (temp < 400) + if (temp < 410) level = 0; - else if (temp < 420) + else if (temp < 440) level = 1; - else if (temp < 450) - level = 2; else if (temp < 480) + level = 2; + else if (temp < 530) level = 3; else level = 4; @@ -402,6 +809,10 @@ static int get_midas_siop_level(int temp) if (level > prev_level) level = prev_level; } + + if (siopLevellimit != 0 && level > siopLevellimit) + level = siopLevellimit; + #elif defined(CONFIG_MACH_P4NOTE) if (temp > prev_temp) { if (temp >= 620) @@ -429,6 +840,60 @@ static int get_midas_siop_level(int temp) if (level > prev_level) level = prev_level; } +#elif defined(CONFIG_MACH_T0) + if (temp > prev_temp) { + if (temp >= 620) + level = 4; + else if (temp >= 610) + level = 3; + else if (temp >= 570) + level = 2; + else if (temp >= 540) + level = 1; + else + level = 0; + } else { + if (temp < 510) + level = 0; + else if (temp < 540) + level = 1; + else if (temp < 570) + level = 2; + else if (temp < 610) + level = 3; + else + level = 4; + + if (level > prev_level) + level = prev_level; + } +#elif defined(CONFIG_MACH_GC1) + if (temp > prev_temp) { + if (temp >= 590) + level = 4; + else if (temp >= 580) + level = 3; + else if (temp >= 550) + level = 2; + else if (temp >= 520) + level = 1; + else + level = 0; + } else { + if (temp < 480) + level = 0; + else if (temp < 520) + level = 1; + else if (temp < 550) + level = 2; + else if (temp < 580) + level = 3; + else + level = 4; + + if (level > prev_level) + level = prev_level; + } #else if (temp > prev_temp) { if (temp >= 540) diff --git a/arch/arm/mach-exynos/midas-tsp.c b/arch/arm/mach-exynos/midas-tsp.c index 75e54d0..cc374d8 100644 --- a/arch/arm/mach-exynos/midas-tsp.c +++ b/arch/arm/mach-exynos/midas-tsp.c @@ -17,6 +17,18 @@ #include <linux/i2c/mxt224_u1.h> #elif defined(CONFIG_TOUCHSCREEN_MELFAS_GC) #include <linux/platform_data/mms_ts_gc.h> +#elif defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E) +#include <linux/delay.h> +#include <linux/i2c/mxt540e.h> +#elif defined(CONFIG_TOUCHSCREEN_MELFAS_NOTE) +#include <linux/platform_data/mms152_ts.h> +#elif defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540S) +#include <linux/i2c/mxt540s.h> +#elif defined(CONFIG_TOUCHSCREEN_CYTTSP4) +#include <linux/platform_data/cypress_cyttsp4.h> +#include <linux/delay.h> +#include <linux/input.h> + #else #include <linux/platform_data/mms_ts.h> #endif @@ -62,6 +74,7 @@ static void mxt224_power_on(void) s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); mdelay(40); + printk(KERN_INFO "mxt224_power_on is finished\n"); } @@ -81,7 +94,6 @@ static void mxt224_power_off(void) regulator_disable(regulator); regulator_put(regulator); - printk(KERN_INFO "mxt224_power_off is finished\n"); } @@ -101,9 +113,9 @@ EXPORT_SYMBOL(mxt224_power_off); #define MXT224_ATCHCALTHR 30 static u8 t7_config[] = { GEN_POWERCONFIG_T7, - 48, /* IDLEACQINT */ - 255, /* ACTVACQINT */ - 25 /* ACTV2IDLETO: 25 * 200ms = 5s */ + 48, /* IDLEACQINT */ + 255, /* ACTVACQINT */ + 25 /* ACTV2IDLETO: 25 * 200ms = 5s */ }; static u8 t8_config[] = { GEN_ACQUISITIONCONFIG_T8, @@ -719,7 +731,12 @@ static struct melfas_tsi_platform_data mms_ts_pdata = { .gpio_sda = GPIO_TSP_SDA_18V, .power = melfas_power, .mux_fw_flash = melfas_mux_fw_flash, - .config_fw_version = "GC_Me_0000", + .tsp_vendor = "MELFAS", + .tsp_ic = "MMS144", + .tsp_tx = 26, /* TX_NUM (Reg Addr : 0xEF) */ + .tsp_rx = 14, /* RX_NUM (Reg Addr : 0xEE) */ +/* .fw_version = 0x02, */ + .config_fw_version = "GC100_Me_0829", .register_cb = melfas_register_callback, }; @@ -741,7 +758,7 @@ void __init midas_tsp_init(void) { int gpio; int ret; - pr_info("melfas-ts : GC TSP init() is called"); + pr_info("melfas-ts : GC TSP init() is called : [%d]", system_rev); /* TSP_INT: XEINT_4 */ gpio = GPIO_TSP_INT; @@ -759,9 +776,470 @@ void __init midas_tsp_init(void) i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); } -#else /* CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */ +#elif defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540E) +static struct charging_status_callbacks { + void (*tsp_set_charging_cable) (int type); +} charging_cbs; -/* MELFAS TSP */ +void tsp_register_callback(void *function) +{ + charging_cbs.tsp_set_charging_cable = function; +} + +void tsp_read_ta_status(void *ta_status) +{ + *(bool *) ta_status = is_cable_attached; +} + +void tsp_charger_infom(bool en) +{ + if (charging_cbs.tsp_set_charging_cable) + charging_cbs.tsp_set_charging_cable(en); +} + +void __init midas_tsp_set_lcdtype(int lcd_type) +{ +} + +static void mxt540e_power_on(void) +{ + struct regulator *regulator_avdd; + struct regulator *regulator_vdd; + + regulator_avdd = regulator_get(NULL, "touch"); + regulator_vdd = regulator_get(NULL, "touch_1.8v"); + + if (IS_ERR(regulator_avdd)) { + pr_err("[TSP] %s regulator_avdd error!", __func__); + return; + } + if (IS_ERR(regulator_vdd)) { + pr_err("[TSP] %s regulator_vdd error!", __func__); + return; + } + + s3c_gpio_cfgpin(GPIO_TSP_LDO_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_LDO_EN, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_TSP_LDO_EN, GPIO_LEVEL_HIGH); + + regulator_enable(regulator_vdd); + regulator_enable(regulator_avdd); + if (regulator_is_enabled(regulator_avdd) && + regulator_is_enabled(regulator_vdd)) { + pr_info("[TSP] %s", __func__); + } else { + pr_err("[TSP] %s fail", __func__); + } + regulator_put(regulator_vdd); + regulator_put(regulator_avdd); + + msleep(MXT540E_HW_RESET_TIME); + + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); +} + +static void mxt540e_power_off(void) +{ + struct regulator *regulator_avdd; + struct regulator *regulator_vdd; + + regulator_avdd = regulator_get(NULL, "touch"); + regulator_vdd = regulator_get(NULL, "touch_1.8v"); + + if (IS_ERR(regulator_avdd)) { + pr_err("[TSP] %s regulator_avdd error!", __func__); + return; + } + if (IS_ERR(regulator_vdd)) { + pr_err("[TSP] %s regulator_vdd error!", __func__); + return; + } + + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_TSP_LDO_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_LDO_EN, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_TSP_LDO_EN, GPIO_LEVEL_LOW); + + if (regulator_is_enabled(regulator_avdd)) + regulator_disable(regulator_avdd); + if (regulator_is_enabled(regulator_vdd)) + regulator_disable(regulator_vdd); + if (!regulator_is_enabled(regulator_avdd) && + !regulator_is_enabled(regulator_vdd)) { + pr_info("[TSP] %s", __func__); + } else { + pr_err("[TSP] %s fail", __func__); + } + regulator_put(regulator_vdd); + regulator_put(regulator_avdd); +} + +/* + Configuration for MXT540E +*/ +#define MXT540E_MAX_MT_FINGERS 10 +#define MXT540E_CHRGTIME_BATT 48 +#define MXT540E_CHRGTIME_CHRG 48 +#define MXT540E_THRESHOLD_BATT 50 +#define MXT540E_THRESHOLD_CHRG 40 +#define MXT540E_ACTVSYNCSPERX_BATT 34 +#define MXT540E_ACTVSYNCSPERX_CHRG 34 +#define MXT540E_CALCFG_BATT 98 +#define MXT540E_CALCFG_CHRG 114 +#define MXT540E_ATCHFRCCALTHR_WAKEUP 8 +#define MXT540E_ATCHFRCCALRATIO_WAKEUP 180 +#define MXT540E_ATCHFRCCALTHR_NORMAL 40 +#define MXT540E_ATCHFRCCALRATIO_NORMAL 55 + +static u8 t7_config_e[] = { GEN_POWERCONFIG_T7, + 48, 255, 50 +}; + +static u8 t8_config_e[] = { GEN_ACQUISITIONCONFIG_T8, + MXT540E_CHRGTIME_BATT, 0, 5, 1, 0, 0, 4, 20, + MXT540E_ATCHFRCCALTHR_WAKEUP, MXT540E_ATCHFRCCALRATIO_WAKEUP +}; + +static u8 t9_config_e[] = { TOUCH_MULTITOUCHSCREEN_T9, + 131, 0, 0, 16, 26, 0, 192, MXT540E_THRESHOLD_BATT, 2, 6, + 10, 10, 10, 80, MXT540E_MAX_MT_FINGERS, 20, 40, 20, 31, 3, + 255, 4, 3, 3, 2, 2, 136, 60, 136, 40, + 18, 15, 0, 0, 0 +}; + +static u8 t15_config_e[] = { TOUCH_KEYARRAY_T15, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t18_config_e[] = { SPT_COMCONFIG_T18, + 0, 0 +}; + +static u8 t19_config_e[] = { SPT_GPIOPWM_T19, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t24_config_e[] = { PROCI_ONETOUCHGESTUREPROCESSOR_T24, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t25_config_e[] = { SPT_SELFTEST_T25, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t27_config_e[] = { PROCI_TWOTOUCHGESTUREPROCESSOR_T27, + 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t40_config_e[] = { PROCI_GRIPSUPPRESSION_T40, + 0, 0, 0, 0, 0 +}; + +static u8 t42_config_e[] = { PROCI_TOUCHSUPPRESSION_T42, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t43_config_e[] = { SPT_DIGITIZER_T43, + 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t46_config_e[] = { SPT_CTECONFIG_T46, + 0, 0, 16, MXT540E_ACTVSYNCSPERX_BATT, 0, 0, 1, 0 +}; + +static u8 t47_config_e[] = { PROCI_STYLUS_T47, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t48_config_e[] = { PROCG_NOISESUPPRESSION_T48, + 3, 132, MXT540E_CALCFG_BATT, 0, 0, 0, 0, 0, 1, 2, + 0, 0, 0, 6, 6, 0, 0, 28, 4, 64, + 10, 0, 20, 6, 0, 30, 0, 0, 0, 0, + 0, 0, 0, 0, 192, MXT540E_THRESHOLD_BATT, 2, 10, 10, 47, + MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136, + 0, 18, 5, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0 +}; + +static u8 t48_config_chrg_e[] = { PROCG_NOISESUPPRESSION_T48, + 3, 132, MXT540E_CALCFG_CHRG, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 6, 6, 0, 0, 36, 4, 64, + 10, 0, 10, 6, 0, 20, 0, 0, 0, 0, + 0, 0, 0, 0, 112, MXT540E_THRESHOLD_CHRG, 2, 10, 5, 65, + MXT540E_MAX_MT_FINGERS, 5, 20, 253, 0, 7, 7, 160, 55, 136, + 0, 18, 10, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0 +}; + +static u8 t52_config_e[] = { TOUCH_PROXKEY_T52, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t55_config_e[] = {ADAPTIVE_T55, + 0, 0, 0, 0, 0, 0 +}; + +static u8 t57_config_e[] = {SPT_GENERICDATA_T57, + 243, 25, 1 +}; + +static u8 t61_config_e[] = {SPT_TIMER_T61, + 0, 0, 0, 0, 0 +}; + +static u8 end_config_e[] = { RESERVED_T255 }; + +static const u8 *mxt540e_config[] = { + t7_config_e, + t8_config_e, + t9_config_e, + t15_config_e, + t18_config_e, + t19_config_e, + t24_config_e, + t25_config_e, + t27_config_e, + t40_config_e, + t42_config_e, + t43_config_e, + t46_config_e, + t47_config_e, + t48_config_e, + t52_config_e, + t55_config_e, + t57_config_e, + t61_config_e, + end_config_e, +}; + +struct mxt540e_platform_data mxt540e_data = { + .max_finger_touches = MXT540E_MAX_MT_FINGERS, + .gpio_read_done = GPIO_TSP_INT, + .config_e = mxt540e_config, + .min_x = 0, + .max_x = 799, + .min_y = 0, + .max_y = 1279, + .min_z = 0, + .max_z = 255, + .min_w = 0, + .max_w = 30, + .chrgtime_batt = MXT540E_CHRGTIME_BATT, + .chrgtime_charging = MXT540E_CHRGTIME_CHRG, + .tchthr_batt = MXT540E_THRESHOLD_BATT, + .tchthr_charging = MXT540E_THRESHOLD_CHRG, + .actvsyncsperx_batt = MXT540E_ACTVSYNCSPERX_BATT, + .actvsyncsperx_charging = MXT540E_ACTVSYNCSPERX_CHRG, + .calcfg_batt_e = MXT540E_CALCFG_BATT, + .calcfg_charging_e = MXT540E_CALCFG_CHRG, + .atchfrccalthr_e = MXT540E_ATCHFRCCALTHR_NORMAL, + .atchfrccalratio_e = MXT540E_ATCHFRCCALRATIO_NORMAL, + .t48_config_batt_e = t48_config_e, + .t48_config_chrg_e = t48_config_chrg_e, + .power_on = mxt540e_power_on, + .power_off = mxt540e_power_off, + .power_on_with_oleddet = mxt540e_power_on, + .power_off_with_oleddet = mxt540e_power_off, + .register_cb = tsp_register_callback, + .read_ta_status = tsp_read_ta_status, +}; + +/* I2C3 */ +static struct i2c_board_info i2c_devs3[] __initdata = { + { + I2C_BOARD_INFO(MXT540E_DEV_NAME, 0x4c), + .platform_data = &mxt540e_data}, +}; + +void __init midas_tsp_init(void) +{ + int gpio; + int ret; + pr_info("[TSP] T0 TSP init() is called"); + + gpio = GPIO_TSP_LDO_EN; + gpio_request(gpio, "TSP_LDO_EN"); + gpio_direction_output(gpio, 0); + gpio_export(gpio, 0); + + /* TSP_INT: XEINT_4 */ + gpio = GPIO_TSP_INT; + ret = gpio_request(gpio, "TSP_INT"); + if (ret) + pr_err("[TSP] failed to request gpio(TSP_INT)"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + s5p_register_gpio_interrupt(gpio); + i2c_devs3[0].irq = gpio_to_irq(gpio); + + pr_info("[TSP] T0 %s touch : %d\n", __func__, i2c_devs3[0].irq); + + i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); +} + +#elif defined(CONFIG_TOUCHSCREEN_ATMEL_MXT540S) +#define MXT_FIRMWARE_540S "tsp_atmel/mXT540S.fw" + +struct mxt_callbacks *charger_callbacks; + +void tsp_charger_infom(bool en) +{ + if (charger_callbacks && charger_callbacks->inform_charger) + charger_callbacks->inform_charger(charger_callbacks, en); +} + +static void ts_register_callback(void *cb) +{ + charger_callbacks = cb; + pr_debug("[TSP] ts_register_callback\n"); +} + +int get_lcd_type; +void __init midas_tsp_set_lcdtype(int lcd_type) +{ + get_lcd_type = lcd_type; +} + +static int ts_power_on(void) +{ + struct regulator *regulator; + + /* enable I2C pullup */ + regulator = regulator_get(NULL, "touch_1.8v"); + if (IS_ERR(regulator)) { + printk(KERN_ERR "[TSP]ts_power_on : tsp_vdd regulator_get failed\n"); + return -EIO; + } + regulator_enable(regulator); + regulator_put(regulator); + + /* enable DVDD */ + s3c_gpio_cfgpin(GPIO_TSP_LDO_28V_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_LDO_28V_EN, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_TSP_LDO_28V_EN, GPIO_LEVEL_HIGH); + + /* enable AVDD */ + regulator = regulator_get(NULL, "touch"); + if (IS_ERR(regulator)) { + printk(KERN_ERR "[TSP]ts_power_on : tsp_avdd regulator_get failed\n"); + return -EIO; + } + regulator_enable(regulator); + regulator_put(regulator); + + /* touch interrupt pin */ + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + + printk(KERN_ERR "mxt_power_on is finished\n"); + + return 0; +} + +static int ts_power_off(void) +{ + struct regulator *regulator; + + /* disable AVDD */ + regulator = regulator_get(NULL, "touch"); + if (IS_ERR(regulator)) { + printk(KERN_ERR "[TSP]ts_power_off : tsp_avdd regulator_get failed\n"); + return -EIO; + } + + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + regulator_put(regulator); + + /* disable DVDD */ + s3c_gpio_cfgpin(GPIO_TSP_LDO_28V_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_LDO_28V_EN, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_TSP_LDO_28V_EN, GPIO_LEVEL_LOW); + + /* disable I2C pullup */ + regulator = regulator_get(NULL, "touch_1.8v"); + if (IS_ERR(regulator)) { + printk(KERN_ERR "[TSP]ts_power_off : tsp_vdd regulator_get failed\n"); + return -EIO; + } + + if (regulator_is_enabled(regulator)) + regulator_force_disable(regulator); + regulator_put(regulator); + + /* touch interrupt pin */ + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + + printk(KERN_ERR "mxt_power_off is finished\n"); + + return 0; +} + +static int ts_power_reset(void) +{ + return 0; +} + +static void ts_gpio_init(void) +{ + gpio_request(GPIO_TSP_LDO_28V_EN, "TSP_LDO_28V_EN"); + gpio_direction_output(GPIO_TSP_LDO_28V_EN, GPIO_LEVEL_LOW); + gpio_export(GPIO_TSP_LDO_28V_EN, 0); + + /* touch interrupt */ + gpio_request(GPIO_TSP_INT, "TSP_INT"); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + s5p_register_gpio_interrupt(GPIO_TSP_INT); +} + +static struct mxt_platform_data mxt_data = { + .max_finger_touches = 10, + .gpio_read_done = GPIO_TSP_INT, + .min_x = 0, + .max_x = 4095, + .min_y = 0, + .max_y = 4095, + .min_z = 0, + .max_z = 255, + .min_w = 0, + .max_w = 255, + .power_on = ts_power_on, + .power_off = ts_power_off, + .power_reset = ts_power_reset, + .boot_address = 0x24, + .firmware_name = MXT_FIRMWARE_540S, + .register_cb = ts_register_callback, +}; + +static struct i2c_board_info i2c_devs3[] __initdata = { + { + I2C_BOARD_INFO(MXT_DEV_NAME, 0x4a), + .platform_data = &mxt_data, + } +}; + +void __init midas_tsp_init(void) +{ + ts_gpio_init(); + + i2c_devs3[0].irq = gpio_to_irq(GPIO_TSP_INT); + + i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); + + printk(KERN_ERR "%s touch : %d\n", + __func__, i2c_devs3[0].irq); +} + +#elif defined(CONFIG_TOUCHSCREEN_MELFAS_NOTE) +/* MELFAS TSP(T0) */ static bool enabled; int TSP_VDD_18V(int on) { @@ -792,37 +1270,41 @@ int TSP_VDD_18V(int on) return 0; } -int melfas_power(int on) +int melfas_power(bool on) { - struct regulator *regulator; + struct regulator *regulator_vdd; + struct regulator *regulator_avdd; int ret; if (enabled == on) return 0; - regulator = regulator_get(NULL, "touch"); - if (IS_ERR(regulator)) - return PTR_ERR(regulator); + regulator_vdd = regulator_get(NULL, "touch_1.8v"); + if (IS_ERR(regulator_vdd)) + return PTR_ERR(regulator_vdd); + + regulator_avdd = regulator_get(NULL, "touch"); + if (IS_ERR(regulator_avdd)) + return PTR_ERR(regulator_avdd); printk(KERN_DEBUG "[TSP] %s %s\n", __func__, on ? "on" : "off"); if (on) { - /* Analog-Panel Power */ - regulator_enable(regulator); - /* IO Logit Power */ - TSP_VDD_18V(1); + regulator_enable(regulator_vdd); + regulator_enable(regulator_avdd); } else { /* * TODO: If there is a case the regulator must be disabled * (e,g firmware update?), consider regulator_force_disable. */ - if (regulator_is_enabled(regulator)) { - regulator_disable(regulator); - TSP_VDD_18V(0); - } + if (regulator_is_enabled(regulator_vdd)) + regulator_disable(regulator_vdd); + if (regulator_is_enabled(regulator_avdd)) + regulator_disable(regulator_avdd); } enabled = on; - regulator_put(regulator); + regulator_put(regulator_vdd); + regulator_put(regulator_avdd); return 0; } @@ -840,13 +1322,6 @@ int is_melfas_vdd_on(void) pr_err("could not get touch, rc = %d\n", ret); return ret; } -/* - ret = regulator_set_voltage(regulator, 3300000, 3300000); - if (ret) { - pr_err("%s: unable to set ldo17 voltage to 3.3V\n", - __func__); - return ret; - } */ } if (regulator_is_enabled(regulator)) @@ -961,10 +1436,7 @@ static void melfas_register_callback(void *cb) static struct melfas_tsi_platform_data mms_ts_pdata = { .max_x = 720, .max_y = 1280, -#if !defined(CONFIG_MACH_C1) && !defined(CONFIG_MACH_C1VZW) && \ - !defined(CONFIG_MACH_M0) && \ - !defined(CONFIG_MACH_M3) && \ - !defined(CONFIG_MACH_P4NOTE) +#if 0 .invert_x = 720, .invert_y = 1280, #else @@ -977,7 +1449,7 @@ static struct melfas_tsi_platform_data mms_ts_pdata = { .power = melfas_power, .mux_fw_flash = melfas_mux_fw_flash, .is_vdd_on = is_melfas_vdd_on, - .config_fw_version = "I9300_Me_0507", + .config_fw_version = "N7100_Me_0813", /* .set_touch_i2c = melfas_set_touch_i2c, */ /* .set_touch_i2c_to_gpio = melfas_set_touch_i2c_to_gpio, */ .lcd_type = melfas_get_lcdtype, @@ -1020,6 +1492,747 @@ void __init midas_tsp_init(void) i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); } + +#elif defined(CONFIG_TOUCHSCREEN_CYTTSP4) + +#define CY_I2C_NAME "cyttsp4-i2c" + +#define CY_USE_TMA400_SP2 +/* use the following define if the device is a TMA400 family part + */ +#define CY_USE_TMA400 +#define CY_USE_BUTTON_TEST_PANEL + +#ifdef CY_USE_TMA400 +#define CY_I2C_TCH_ADR 0x24 +#define CY_I2C_LDR_ADR 0x24 +#ifdef CY_USE_BUTTON_TEST_PANEL +#define CY_MAXX 480 +#define CY_MAXY 800 +#else +#define CY_MAXX 880 +#define CY_MAXY 1280 +#endif +#define CY_MINX 0 +#define CY_MINY 0 +#endif /* --CY_USE_TMA400 */ + +#define CY_ABS_MIN_X CY_MINX +#define CY_ABS_MIN_Y CY_MINY +#define CY_ABS_MIN_P 0 +#define CY_ABS_MIN_W 0 +#ifdef CY_USE_TMA400 +#define CY_ABS_MIN_T 0 +#endif /* --CY_USE_TMA400 */ + +#define CY_ABS_MAX_X CY_MAXX +#define CY_ABS_MAX_Y CY_MAXY +#define CY_ABS_MAX_P 255 +#define CY_ABS_MAX_W 255 +#ifdef CY_USE_TMA400 +#define CY_ABS_MAX_T 15 +#endif /* --CY_USE_TMA400 */ +#define CY_IGNORE_VALUE 0xFFFF + + + +#include "cyttsp4_params.h" + +static struct touch_settings cyttsp4_sett_param_regs = { + .data = (uint8_t *)&cyttsp4_param_regs[0], + .size = ARRAY_SIZE(cyttsp4_param_regs), + .tag = 0, +}; + +static struct touch_settings cyttsp4_sett_param_size = { + .data = (uint8_t *)&cyttsp4_param_size[0], + .size = ARRAY_SIZE(cyttsp4_param_size), + .tag = 0, +}; + + +/* Design Data Table */ +static u8 cyttsp4_ddata[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24 /* test padding + , 25, 26, 27, 28, 29, 30, 31 */ +}; + +static struct touch_settings cyttsp4_sett_ddata = { + .data = (uint8_t *)&cyttsp4_ddata[0], + .size = ARRAY_SIZE(cyttsp4_ddata), + .tag = 0, +}; + +/* Manufacturing Data Table */ +static u8 cyttsp4_mdata[] = { + 65, 64, /* test truncation */63, 62, 61, 60, 59, 58, 57, 56, 55, + 54, 53, 52, 51, 50, 49, 48, + 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, + 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, + 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 +}; + +static struct touch_settings cyttsp4_sett_mdata = { + .data = (uint8_t *)&cyttsp4_mdata[0], + .size = ARRAY_SIZE(cyttsp4_mdata), + .tag = 0, +}; + +/* Button to keycode conversion */ +static u16 cyttsp4_btn_keys[] = { + /* use this table to map buttons to keycodes (see input.h) */ + KEY_MENU, /* 139 */ + KEY_BACK, /* 158 */ +}; + +static struct touch_settings cyttsp4_sett_btn_keys = { + .data = (uint8_t *)&cyttsp4_btn_keys[0], + .size = ARRAY_SIZE(cyttsp4_btn_keys), + .tag = 0, +}; + +/* use this define to include auto boot image + */ +#define CY_USE_INCLUDE_FBL +#ifdef CY_USE_INCLUDE_FBL +#include "cyttsp4_img.h" +static struct touch_firmware cyttsp4_firmware = { + .img = cyttsp4_img, + .size = ARRAY_SIZE(cyttsp4_img), + .ver = cyttsp4_ver, + .vsize = ARRAY_SIZE(cyttsp4_ver), +}; +#else +static struct touch_firmware cyttsp4_firmware = { + .img = NULL, + .size = 0, + .ver = NULL, + .vsize = 0, +}; +#endif + +static const uint16_t cyttsp4_abs[] = { + ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0, + ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0, + ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0, +#ifdef CY_USE_TMA400 + CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0, +#endif /* --CY_USE_TMA400 */ +#ifndef CY_USE_TMA400 + ABS_MT_TOUCH_MAJOR, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0, +#endif /* --CY_USE_TMA400 */ + ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0, +#ifdef CY_USE_TMA400_SP2 +#ifdef CY_USE_TMA400 + ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0, + ABS_MT_TOUCH_MINOR, 0, 255, 0, 0, + ABS_MT_ORIENTATION, -128, 127, 0, 0, +#endif /* --CY_USE_TMA400 */ +#endif /* --CY_USE_TMA400_SP2 */ +}; + +struct touch_framework cyttsp4_framework = { + .abs = (uint16_t *)&cyttsp4_abs[0], + .size = ARRAY_SIZE(cyttsp4_abs), + .enable_vkeys = 0, +}; + +static bool enabled; +int TSP_VDD_18V(int on) +{ + struct regulator *regulator; + + if (enabled == on) + return 0; + + regulator = regulator_get(NULL, "touch_1.8v"); + if (IS_ERR(regulator)) + return PTR_ERR(regulator); + + if (on) { + regulator_enable(regulator); + /*printk(KERN_INFO "[TSP] melfas power on\n"); */ + } else { + /* + * TODO: If there is a case the regulator must be disabled + * (e,g firmware update?), consider regulator_force_disable. + */ + if (regulator_is_enabled(regulator)) + regulator_disable(regulator); + } + + enabled = on; + regulator_put(regulator); + + return 0; +} + +int melfas_power(int on) +{ + struct regulator *regulator_vdd; + struct regulator *regulator_avdd; + int ret; + if (enabled == on) + return 0; + + regulator_vdd = regulator_get(NULL, "touch_1.8v"); + if (IS_ERR(regulator_vdd)) + return PTR_ERR(regulator_vdd); + + regulator_avdd = regulator_get(NULL, "touch"); + if (IS_ERR(regulator_avdd)) + return PTR_ERR(regulator_avdd); + + printk(KERN_DEBUG "[TSP] %s %s\n", __func__, on ? "on" : "off"); + + if (on) { + regulator_enable(regulator_vdd); + regulator_enable(regulator_avdd); + } else { + /* + * TODO: If there is a case the regulator must be disabled + * (e,g firmware update?), consider regulator_force_disable. + */ + if (regulator_is_enabled(regulator_vdd)) + regulator_disable(regulator_vdd); + if (regulator_is_enabled(regulator_avdd)) + regulator_disable(regulator_avdd); + } + + enabled = on; + regulator_put(regulator_vdd); + regulator_put(regulator_avdd); + + return 0; +} + +int is_melfas_vdd_on(void) +{ + int ret; + /* 3.3V */ + static struct regulator *regulator; + + if (!regulator) { + regulator = regulator_get(NULL, "touch"); + if (IS_ERR(regulator)) { + ret = PTR_ERR(regulator); + pr_err("could not get touch, rc = %d\n", ret); + return ret; + } + } + + if (regulator_is_enabled(regulator)) + return 1; + else + return 0; +} + +int melfas_mux_fw_flash(bool to_gpios) +{ + pr_info("%s:to_gpios=%d\n", __func__, to_gpios); + + /* TOUCH_EN is always an output */ + if (to_gpios) { + if (gpio_request(GPIO_TSP_SCL_18V, "GPIO_TSP_SCL")) + pr_err("failed to request gpio(GPIO_TSP_SCL)\n"); + if (gpio_request(GPIO_TSP_SDA_18V, "GPIO_TSP_SDA")) + pr_err("failed to request gpio(GPIO_TSP_SDA)\n"); + + gpio_direction_output(GPIO_TSP_INT, 0); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + + gpio_direction_output(GPIO_TSP_SCL_18V, 0); + s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE); + + gpio_direction_output(GPIO_TSP_SDA_18V, 0); + s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE); + + } else { + gpio_direction_output(GPIO_TSP_INT, 1); + gpio_direction_input(GPIO_TSP_INT); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); + /*s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); */ + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + /*S3C_GPIO_PULL_UP */ + + gpio_direction_output(GPIO_TSP_SCL_18V, 1); + gpio_direction_input(GPIO_TSP_SCL_18V); + s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE); + + gpio_direction_output(GPIO_TSP_SDA_18V, 1); + gpio_direction_input(GPIO_TSP_SDA_18V); + s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE); + + gpio_free(GPIO_TSP_SCL_18V); + gpio_free(GPIO_TSP_SDA_18V); + } + return 0; +} + +void melfas_set_touch_i2c(void) +{ + s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP); + gpio_free(GPIO_TSP_SDA_18V); + gpio_free(GPIO_TSP_SCL_18V); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); + /* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */ + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); +} + +void melfas_set_touch_i2c_to_gpio(void) +{ + int ret; + s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP); + ret = gpio_request(GPIO_TSP_SDA_18V, "GPIO_TSP_SDA"); + if (ret) + pr_err("failed to request gpio(GPIO_TSP_SDA)\n"); + ret = gpio_request(GPIO_TSP_SCL_18V, "GPIO_TSP_SCL"); + if (ret) + pr_err("failed to request gpio(GPIO_TSP_SCL)\n"); + +} + +int get_lcd_type; +void __init midas_tsp_set_lcdtype(int lcd_type) +{ + get_lcd_type = lcd_type; +} + +int melfas_get_lcdtype(void) +{ + return get_lcd_type; +} +struct tsp_callbacks *charger_callbacks; +struct tsp_callbacks { + void (*inform_charger)(struct tsp_callbacks *, bool); +}; + +void tsp_charger_infom(bool en) +{ + if (charger_callbacks && charger_callbacks->inform_charger) + charger_callbacks->inform_charger(charger_callbacks, en); +} + +static void melfas_register_callback(void *cb) +{ + charger_callbacks = cb; + pr_debug("[TSP] melfas_register_callback\n"); +} + +int cyttsp4_hw_reset(void) +{ + struct regulator *regulator; + int ret = 0; + + regulator = regulator_get(NULL, "touch"); + + regulator_enable(regulator); + TSP_VDD_18V(1); + mdelay(20); + + if (regulator_is_enabled(regulator)) { + regulator_disable(regulator); + TSP_VDD_18V(0); + } + mdelay(40); + + regulator_enable(regulator); + TSP_VDD_18V(1); + mdelay(20); + + regulator_put(regulator); + + return ret; +} + +int cyttsp4_hw_power(int on) +{ + struct regulator *regulator_vdd; + struct regulator *regulator_avdd; + int ret; + + if (enabled == on) + return 0; + + regulator_vdd = regulator_get(NULL, "touch_1.8v"); + if (IS_ERR(regulator_vdd)) + return PTR_ERR(regulator_vdd); + + regulator_avdd = regulator_get(NULL, "touch"); + if (IS_ERR(regulator_avdd)) + return PTR_ERR(regulator_avdd); + + printk(KERN_DEBUG "[TSP] %s %s\n", __func__, on ? "on" : "off"); + + if (on) { + regulator_enable(regulator_vdd); + regulator_enable(regulator_avdd); + } else { + if (regulator_is_enabled(regulator_vdd)) + regulator_disable(regulator_vdd); + if (regulator_is_enabled(regulator_avdd)) + regulator_disable(regulator_avdd); + } + + enabled = on; + regulator_put(regulator_vdd); + regulator_put(regulator_avdd); + + return 0; +} + +#define CY_WAKE_DFLT 99 /* causes wake strobe on INT line + * in sample board configuration + * platform data->hw_recov() function + */ +int cyttsp4_hw_recov(int on) +{ + int retval = 0; + int gpio; + int ret; + + switch (on) { + case 0: + cyttsp4_hw_reset(); + retval = 0; + break; + case CY_WAKE_DFLT: + gpio = GPIO_TSP_INT; + ret = gpio_request(gpio, "TSP_INT"); + retval = gpio_direction_output(gpio, 0); + if (retval < 0) { + pr_err("%s: Fail switch IRQ pin to OUT r=%d\n", + __func__, retval); + } else { + udelay(2000); + retval = gpio_direction_input(gpio); + if (retval < 0) { + pr_err("%s: Fail switch IRQ pin to IN" + " r=%d\n", __func__, retval); + } + } + break; + default: + retval = -ENOSYS; + break; + } + + return retval; +} + +int cyttsp4_irq_stat(void) +{ + int irq_stat = 0; + int gpio; + int ret; + + gpio = GPIO_TSP_INT; + ret = gpio_request(gpio, "TSP_INT"); + irq_stat = gpio_get_value(gpio); + + return irq_stat; +} + +struct touch_platform_data cyttsp4_i2c_touch_platform_data = { + .sett = { + NULL, /* Reserved */ + NULL, /* Command Registers */ + NULL, /* Touch Report */ + NULL, /* Cypress Data Record */ + NULL, /* Test Record */ + NULL, /* Panel Configuration Record */ + &cyttsp4_sett_param_regs, /* &cyttsp4_sett_param_regs, */ + &cyttsp4_sett_param_size, /* &cyttsp4_sett_param_size, */ + NULL, /* Reserved */ + NULL, /* Reserved */ + NULL, /* Operational Configuration Record */ + NULL, /* &cyttsp4_sett_ddata, *//* Design Data Record */ + NULL, /* &cyttsp4_sett_mdata, *//* Manufacturing Data Record */ + NULL, /* Config and Test Registers */ + &cyttsp4_sett_btn_keys, /* button-to-keycode table */ + }, + .fw = &cyttsp4_firmware, + .frmwrk = &cyttsp4_framework, + .addr = {CY_I2C_TCH_ADR, CY_I2C_LDR_ADR}, + .flags = 0x00, + .hw_reset = cyttsp4_hw_reset, + .hw_power = cyttsp4_hw_power, + .hw_recov = cyttsp4_hw_recov, + .irq_stat = cyttsp4_irq_stat, +}; + +static struct i2c_board_info i2c_devs3[] = { + { + I2C_BOARD_INFO(CY_I2C_NAME, CY_I2C_TCH_ADR), + .platform_data = &cyttsp4_i2c_touch_platform_data + }, +}; + +void __init midas_tsp_set_platdata(struct touch_platform_data *pdata) +{ + if (!pdata) + pdata = &cyttsp4_i2c_touch_platform_data; + + i2c_devs3[0].platform_data = pdata; +} + +void __init midas_tsp_init(void) +{ + int gpio; + int ret; + printk(KERN_INFO "[TSP] midas_tsp_init() is called\n"); + + /* TSP_INT: XEINT_4 */ + gpio = GPIO_TSP_INT; + ret = gpio_request(gpio, "TSP_INT"); + if (ret) + pr_err("failed to request gpio(TSP_INT)\n"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + /* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */ + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + s5p_register_gpio_interrupt(gpio); + i2c_devs3[0].irq = gpio_to_irq(gpio); + + printk(KERN_INFO "%s touch : %d\n", __func__, i2c_devs3[0].irq); + + i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); +} + +#else /* CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */ + +/* MELFAS TSP */ +static bool enabled; +int TSP_VDD_18V(bool on) +{ + struct regulator *regulator; + + if (enabled == on) + return 0; + + regulator = regulator_get(NULL, "touch_1.8v"); + if (IS_ERR(regulator)) + return PTR_ERR(regulator); + + if (on) { + regulator_enable(regulator); + /*printk(KERN_INFO "[TSP] melfas power on\n"); */ + } else { + /* + * TODO: If there is a case the regulator must be disabled + * (e,g firmware update?), consider regulator_force_disable. + */ + if (regulator_is_enabled(regulator)) + regulator_disable(regulator); + } + + enabled = on; + regulator_put(regulator); + + return 0; +} + +int melfas_power(bool on) +{ + struct regulator *regulator; + int ret; + if (enabled == on) + return 0; + + regulator = regulator_get(NULL, "touch"); + if (IS_ERR(regulator)) + return PTR_ERR(regulator); + + printk(KERN_DEBUG "[TSP] %s %s\n", __func__, on ? "on" : "off"); + + if (on) { + /* Analog-Panel Power */ + regulator_enable(regulator); + /* IO Logit Power */ + TSP_VDD_18V(true); + } else { + /* + * TODO: If there is a case the regulator must be disabled + * (e,g firmware update?), consider regulator_force_disable. + */ + if (regulator_is_enabled(regulator)) { + regulator_disable(regulator); + TSP_VDD_18V(false); + } + } + + enabled = on; + regulator_put(regulator); + + return 0; +} + +int is_melfas_vdd_on(void) +{ + int ret; + /* 3.3V */ + static struct regulator *regulator; + + if (!regulator) { + regulator = regulator_get(NULL, "touch"); + if (IS_ERR(regulator)) { + ret = PTR_ERR(regulator); + pr_err("could not get touch, rc = %d\n", ret); + return ret; + } +/* + ret = regulator_set_voltage(regulator, 3300000, 3300000); + if (ret) { + pr_err("%s: unable to set ldo17 voltage to 3.3V\n", + __func__); + return ret; + } */ + } + + if (regulator_is_enabled(regulator)) + return 1; + else + return 0; +} + +int melfas_mux_fw_flash(bool to_gpios) +{ + pr_info("%s:to_gpios=%d\n", __func__, to_gpios); + + /* TOUCH_EN is always an output */ + if (to_gpios) { + if (gpio_request(GPIO_TSP_SCL_18V, "GPIO_TSP_SCL")) + pr_err("failed to request gpio(GPIO_TSP_SCL)\n"); + if (gpio_request(GPIO_TSP_SDA_18V, "GPIO_TSP_SDA")) + pr_err("failed to request gpio(GPIO_TSP_SDA)\n"); + + gpio_direction_output(GPIO_TSP_INT, 0); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + + gpio_direction_output(GPIO_TSP_SCL_18V, 0); + s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE); + + gpio_direction_output(GPIO_TSP_SDA_18V, 0); + s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE); + + } else { + gpio_direction_output(GPIO_TSP_INT, 1); + gpio_direction_input(GPIO_TSP_INT); + s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); + /*s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_INPUT); */ + s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); + /*S3C_GPIO_PULL_UP */ + + gpio_direction_output(GPIO_TSP_SCL_18V, 1); + gpio_direction_input(GPIO_TSP_SCL_18V); + s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE); + + gpio_direction_output(GPIO_TSP_SDA_18V, 1); + gpio_direction_input(GPIO_TSP_SDA_18V); + s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(3)); + s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE); + + gpio_free(GPIO_TSP_SCL_18V); + gpio_free(GPIO_TSP_SDA_18V); + } + return 0; +} + +int get_lcd_type; +void __init midas_tsp_set_lcdtype(int lcd_type) +{ + get_lcd_type = lcd_type; +} + +int melfas_get_lcdtype(void) +{ + return get_lcd_type; +} +struct tsp_callbacks *charger_callbacks; +struct tsp_callbacks { + void (*inform_charger)(struct tsp_callbacks *, bool); +}; + +void tsp_charger_infom(bool en) +{ + if (charger_callbacks && charger_callbacks->inform_charger) + charger_callbacks->inform_charger(charger_callbacks, en); +} + +static void melfas_register_callback(void *cb) +{ + charger_callbacks = cb; + pr_debug("[TSP] melfas_register_callback\n"); +} + +static struct melfas_tsi_platform_data mms_ts_pdata = { + .max_x = 720, + .max_y = 1280, + .invert_x = 0, + .invert_y = 0, + .gpio_int = GPIO_TSP_INT, + .gpio_scl = GPIO_TSP_SCL_18V, + .gpio_sda = GPIO_TSP_SDA_18V, + .power = melfas_power, + .mux_fw_flash = melfas_mux_fw_flash, + .is_vdd_on = is_melfas_vdd_on, + .config_fw_version = "I9300_Me_0507", + .lcd_type = melfas_get_lcdtype, + .register_cb = melfas_register_callback, +}; + +static struct i2c_board_info i2c_devs3[] = { + { + I2C_BOARD_INFO(MELFAS_TS_NAME, 0x48), + .platform_data = &mms_ts_pdata}, +}; + +void __init midas_tsp_set_platdata(struct melfas_tsi_platform_data *pdata) +{ + if (!pdata) + pdata = &mms_ts_pdata; + + i2c_devs3[0].platform_data = pdata; +} + +void __init midas_tsp_init(void) +{ + int gpio; + int ret; + printk(KERN_INFO "[TSP] midas_tsp_init() is called\n"); + + /* TSP_INT: XEINT_4 */ + gpio = GPIO_TSP_INT; + ret = gpio_request(gpio, "TSP_INT"); + if (ret) + pr_err("failed to request gpio(TSP_INT)\n"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + /* s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); */ + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + + s5p_register_gpio_interrupt(gpio); + i2c_devs3[0].irq = gpio_to_irq(gpio); + + printk(KERN_INFO "%s touch : %d\n", __func__, i2c_devs3[0].irq); + + i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); +} #endif /* CONFIG_TOUCHSCREEN_ATMEL_MXT224_U1 */ /* diff --git a/arch/arm/mach-exynos/naples-gpio.c b/arch/arm/mach-exynos/naples-gpio.c index 145197c..149a250 100644 --- a/arch/arm/mach-exynos/naples-gpio.c +++ b/arch/arm/mach-exynos/naples-gpio.c @@ -34,8 +34,7 @@ static struct gpio_init_data midas_init_gpios[] = { S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */ {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M3) || defined(CONFIG_MACH_C1CTC) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) {EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */ {EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -151,8 +150,8 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_M3) || \ +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) || \ + defined(CONFIG_MACH_M0) || \ defined(CONFIG_MACH_SLP_NAPLES) /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -210,35 +209,23 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#else {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPL0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#else {EXYNOS4_GPL1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#endif {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_M3) || defined(CONFIG_MACH_C1CTC) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) /* GLP2(4) CMC_CPU_RESET, hold high */ {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */ #else @@ -248,8 +235,7 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_NAPLES) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_NAPLES) /* GPX3(2) M0 CP_PMU_RESET, hold high */ {EXYNOS4_GPX3(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, #else @@ -278,33 +264,18 @@ static unsigned int exynos4_sleep_gpio_table_common[][3] = { {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPY3(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPY3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY3(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - /* GPY4(2) S2Plus PDA_ACTIVE, let cp know AP sleep status*/ - {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4_GPY4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY4(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#endif {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -402,11 +373,7 @@ static unsigned int exynos4212_sleep_gpio_table[][3] = { {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#endif {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -442,8 +409,7 @@ static unsigned int exynos4212_sleep_gpio_table[][3] = { {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) || \ - defined(CONFIG_MACH_JENGA) || defined(CONFIG_MACH_S2PLUS) || \ +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_PQ) defined(CONFIG_MACH_SLP_NAPLES) /* GPM3(3) M0, CP_RESET_REQ hold high */ {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_DOWN}, @@ -464,15 +430,8 @@ static unsigned int exynos4212_sleep_gpio_table[][3] = { {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */ {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_S2PLUS) - {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - /* MICBAS_EN */ - {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - /* SUB_MICBIAS_EN */ -#else {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -629,8 +588,7 @@ static struct gpio_init_data m0_init_gpios[] = { S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_C1CTC) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) {EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_SDA_1.8V */ {EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -777,7 +735,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) /* CMC221 Active States */ {EXYNOS4_GPF1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /* NC */ #else @@ -787,7 +745,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) || \ defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_SLP_NAPLES) /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -871,8 +829,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) || \ - defined(CONFIG_MACH_C1CTC) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) /* GLP2(4) CMC_CPU_RESET, hold high */ {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */ #else @@ -950,14 +907,7 @@ static unsigned int m0_sleep_gpio_table[][3] = { {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1) ||\ - defined(CONFIG_MACH_C1VZW) || defined(CONFIG_MACH_C1ATT) ||\ - defined(CONFIG_MACH_S2PLUS) - /* GPIO_PS_ALS_EN */ - {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#else {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ diff --git a/arch/arm/mach-exynos/naples-power.c b/arch/arm/mach-exynos/naples-power.c index caed0c4..e2b52cc 100644 --- a/arch/arm/mach-exynos/naples-power.c +++ b/arch/arm/mach-exynos/naples-power.c @@ -617,7 +617,7 @@ void midas_power_init(void) if (system_rev == 0 || system_rev == 3) #elif defined(CONFIG_MACH_C1) if (system_rev <= 1 || system_rev == 3) -#elif defined(CONFIG_MACH_C1VZW) +#elif defined(CONFIG_MACH_M3) if (system_rev == 0) #endif ldo8_init_data.constraints.always_on = 1; diff --git a/arch/arm/mach-exynos/p10-battery.c b/arch/arm/mach-exynos/p10-battery.c deleted file mode 100644 index e578b55..0000000 --- a/arch/arm/mach-exynos/p10-battery.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * Copyright (C) 2012 Samsung Electronics, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/i2c.h> -#include <linux/i2c-gpio.h> -#include <linux/gpio.h> - -#include <mach/gpio-p10.h> -#include <mach/regs-pmu.h> /* S5P_INFORMX */ - -#include <plat/gpio-cfg.h> - -#ifdef CONFIG_STMPE811_ADC -#include <linux/stmpe811-adc.h> -#endif - -#if defined(CONFIG_BATTERY_SAMSUNG_P1X) -#include <linux/battery/sec_battery.h> -#include <linux/battery/sec_fuelgauge.h> -#include <linux/battery/sec_charger.h> - -#define SEC_BATTERY_PMIC_NAME "" -#define SEC_FUELGAUGE_I2C_ID 9 -#define SEC_CHARGER_I2C_ID 10 - -static bool sec_bat_adc_none_init(struct platform_device *pdev) { return true; } -static bool sec_bat_adc_none_exit(void) { return true; } -static int sec_bat_adc_none_read(unsigned int channel) { return 0; } - -static bool sec_bat_adc_ap_init(struct platform_device *pdev) { return true; } -static bool sec_bat_adc_ap_exit(void) { return true; } -static int sec_bat_adc_ap_read(unsigned int channel) { return 0; } - -/* CHECK ME */ -#define SMTPE811_CHANNEL_ADC_CHECK_1 6 -#define SMTPE811_CHANNEL_VICHG 4 /* Not supported in P10 */ - -static bool sec_bat_adc_ic_init(struct platform_device *pdev) { return true; } -static bool sec_bat_adc_ic_exit(void) { return true; } -static int sec_bat_adc_ic_read(unsigned int channel) -{ - int data = 0; - int max_voltage = 3300; - - switch (channel) { - case SEC_BAT_ADC_CHANNEL_CABLE_CHECK: - data = stmpe811_get_adc_data(SMTPE811_CHANNEL_ADC_CHECK_1); - data = data * max_voltage / 4095; /* 4096 ? */ - break; - } - - return data; -} - -static bool sec_bat_gpio_init(void) -{ -#if defined(CONFIG_MACH_P10_LTE_00_BD) || defined(CONFIG_MACH_P10_WIFI_00_BD) - s3c_gpio_cfgpin(GPIO_TA_nCONNECTED, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_TA_nCONNECTED, S3C_GPIO_PULL_NONE); -#else - /* IRQ to detect cable insertion and removal */ - s3c_gpio_cfgpin(GPIO_TA_INT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_TA_INT, S3C_GPIO_PULL_NONE); -#endif - - return true; -} - -static bool sec_fg_gpio_init(void) -{ - /* IRQ to detect low battery from fuel gauge */ - s3c_gpio_cfgpin(GPIO_FUEL_ALERT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_FUEL_ALERT, S3C_GPIO_PULL_UP); - - return true; -} - -static bool sec_chg_gpio_init(void) -{ - s3c_gpio_cfgpin(GPIO_TA_EN, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TA_EN, S3C_GPIO_PULL_UP); -/* gpio_set_value(GPIO_TA_EN, 1); */ - - s3c_gpio_cfgpin(GPIO_TA_nCHG, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_TA_nCHG, S3C_GPIO_PULL_UP); - -#if defined(CONFIG_MACH_P10_LTE_00_BD) || defined(CONFIG_MACH_P10_WIFI_00_BD) - /* GPIO_CHG_INT not supported */ -#else - /* IRQ to detect charger status change */ - s3c_gpio_cfgpin(GPIO_CHG_INT, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_CHG_INT, S3C_GPIO_PULL_UP); -#endif - - return true; -} - -static bool sec_bat_is_lpm(void) -{ - u32 val = __raw_readl(S5P_INFORM2); - - pr_info("%s: LP charging: (INFORM2) 0x%x\n", __func__, val); - - if (val == 0x1) - return true; - - return false; -} - -static void sec_bat_initial_check(void) -{ - struct power_supply *psy = power_supply_get_by_name("battery"); - union power_supply_propval value; - int ret = 0; - - value.intval = gpio_get_value(GPIO_TA_nCONNECTED); - pr_debug("%s: %d\n", __func__, value.intval); - - ret = psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &value); - if (ret) { - pr_err("%s: fail to set power_suppy ONLINE property(%d)\n", - __func__, ret); - } -} - -static bool sec_bat_check_jig_status(void) -{ - /* TODO: */ - return false; -} - -static void sec_bat_switch_to_check(void) -{ - pr_debug("%s\n", __func__); - - s3c_gpio_cfgpin(GPIO_USB_SEL1, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_USB_SEL1, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_USB_SEL1, 0); - - mdelay(300); -} - -static void sec_bat_switch_to_normal(void) -{ - pr_debug("%s\n", __func__); - - s3c_gpio_cfgpin(GPIO_USB_SEL1, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_USB_SEL1, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_USB_SEL1, 1); -} - -static int current_cable_type = POWER_SUPPLY_TYPE_BATTERY; - -static int sec_bat_check_cable_callback(void) -{ - return current_cable_type; -} - -static bool sec_bat_check_cable_result_callback( - int cable_type) -{ - current_cable_type = cable_type; - - switch (cable_type) { - case POWER_SUPPLY_TYPE_USB: - pr_info("%s set vbus applied\n", - __func__); - break; - case POWER_SUPPLY_TYPE_BATTERY: - pr_info("%s set vbus cut\n", - __func__); - break; - case POWER_SUPPLY_TYPE_MAINS: - default: - pr_err("%s cable type (%d)\n", - __func__, cable_type); - return false; - } - - return true; -} - -/* callback for battery check - * return : bool - * true - battery detected, false battery NOT detected - */ -static bool sec_bat_check_callback(void) { return true; } -static bool sec_bat_check_result_callback(void) { return true; } - -/* callback for OVP/UVLO check - * return : int - * battery health - */ -static int sec_bat_ovp_uvlo_callback(void) -{ - int health; - health = POWER_SUPPLY_HEALTH_GOOD; - - return health; -} - -static bool sec_bat_ovp_uvlo_result_callback(int health) { return true; } - -/* - * val.intval : temperature - */ -static bool sec_bat_get_temperature_callback( - enum power_supply_property psp, - union power_supply_propval *val) { return true; } - -static bool sec_fg_fuelalert_process(bool is_fuel_alerted) { return true; } - -/* ADC region should be exclusive */ -static sec_bat_adc_region_t cable_adc_value_table[] = { - { 0, 500 }, /* POWER_SUPPLY_TYPE_BATTERY */ - { 0, 0 }, /* POWER_SUPPLY_TYPE_UPS */ - { 1000, 1500 }, /* POWER_SUPPLY_TYPE_MAINS */ - { 0, 0 }, /* POWER_SUPPLY_TYPE_USB */ - { 0, 0 }, /* POWER_SUPPLY_TYPE_OTG */ - { 0, 0 }, /* POWER_SUPPLY_TYPE_DOCK */ - { 0, 0 }, /* POWER_SUPPLY_TYPE_MISC */ -}; - -/* charging current (mA, 0 - NOT supported) */ -/* matching with power_supply_type in power_supply.h */ -static sec_charging_current_t charging_current_table[] = { - {0, 0, 0, 0}, /* POWER_SUPPLY_TYPE_BATTERY */ - {0, 0, 0, 0}, /* POWER_SUPPLY_TYPE_UPS */ - {2000, 2000, 256, 0}, /* POWER_SUPPLY_TYPE_MAINS */ - {500, 500, 256, 0}, /* POWER_SUPPLY_TYPE_USB */ - {500, 500, 256, 0}, /* POWER_SUPPLY_TYPE_USB_DCP */ - {500, 500, 256, 0}, /* POWER_SUPPLY_TYPE_USB_CDP */ - {500, 500, 256, 0}, /* POWER_SUPPLY_TYPE_USB_ACA */ - {0, 0, 0, 0}, /* POWER_SUPPLY_TYPE_OTG */ - {0, 0, 0, 0}, /* POWER_SUPPLY_TYPE_DOCK */ - {500, 500, 256, 0}, /* POWER_SUPPLY_TYPE_MISC */ - {0, 0, 0, 0}, /* POWER_SUPPLY_TYPE_WIRELESS */ -}; - -/* unit: seconds */ -static int polling_time_table[] = { - 10, /* BASIC */ - 30, /* CHARGING */ - 30, /* DISCHARGING */ - 30, /* NOT_CHARGING */ - 300, /* SLEEP */ -}; - -/* for MAX17050, MAX17047 */ -static struct battery_data_t p10_battery_data[] = { - /* SDI battery data */ - { - .Capacity = 0x2008, - .low_battery_comp_voltage = 3600, - .low_battery_table = { - /* range, slope, offset */ - {-5000, 0, 0}, /* dummy for top limit */ - {-1250, 0, 3320}, - {-750, 97, 3451}, - {-100, 96, 3461}, - {0, 0, 3456}, - }, - .temp_adjust_table = { - /* range, slope, offset */ - {47000, 122, 8950}, - {60000, 200, 51000}, - {100000, 0, 0}, /* dummy for top limit */ - }, - .type_str = "SDI", - } -}; - -static sec_battery_platform_data_t sec_battery_pdata = { - /* NO NEED TO BE CHANGED */ - .initial_check = sec_bat_initial_check, - .bat_gpio_init = sec_bat_gpio_init, - .fg_gpio_init = sec_fg_gpio_init, - .chg_gpio_init = sec_chg_gpio_init, - - .is_lpm = sec_bat_is_lpm, - .check_jig_status = sec_bat_check_jig_status, - .check_cable_callback = - sec_bat_check_cable_callback, - .cable_switch_check = sec_bat_switch_to_check, - .cable_switch_normal = sec_bat_switch_to_normal, - .check_cable_result_callback = - sec_bat_check_cable_result_callback, - .check_battery_callback = - sec_bat_check_callback, - .check_battery_result_callback = - sec_bat_check_result_callback, - .ovp_uvlo_callback = sec_bat_ovp_uvlo_callback, - .ovp_uvlo_result_callback = - sec_bat_ovp_uvlo_result_callback, - .fuelalert_process = sec_fg_fuelalert_process, - .get_temperature_callback = - sec_bat_get_temperature_callback, - - .adc_api[SEC_BATTERY_ADC_TYPE_NONE] = { - .init = sec_bat_adc_none_init, - .exit = sec_bat_adc_none_exit, - .read = sec_bat_adc_none_read - }, - .adc_api[SEC_BATTERY_ADC_TYPE_AP] = { - .init = sec_bat_adc_ap_init, - .exit = sec_bat_adc_ap_exit, - .read = sec_bat_adc_ap_read - }, - .adc_api[SEC_BATTERY_ADC_TYPE_IC] = { - .init = sec_bat_adc_ic_init, - .exit = sec_bat_adc_ic_exit, - .read = sec_bat_adc_ic_read - }, - .cable_adc_value = cable_adc_value_table, - .charging_current = charging_current_table, - .polling_time = polling_time_table, - /* NO NEED TO BE CHANGED */ - - .pmic_name = SEC_BATTERY_PMIC_NAME, - - .adc_check_count = 7, - .adc_type = { - SEC_BATTERY_ADC_TYPE_IC, /* CABLE_CHECK */ - SEC_BATTERY_ADC_TYPE_NONE, /* BAT_CHECK */ - SEC_BATTERY_ADC_TYPE_NONE, /* TEMP */ - SEC_BATTERY_ADC_TYPE_NONE, /* TEMP_AMB */ - SEC_BATTERY_ADC_TYPE_NONE, /* FULL_CHECK */ - }, - - /* Battery */ - .vendor = "SDI SDI", - .technology = POWER_SUPPLY_TECHNOLOGY_LION, - .battery_data = (void *)p10_battery_data, - .bat_gpio_ta_nconnected = GPIO_TA_nCONNECTED, - .bat_polarity_ta_nconnected = 1, /* active HIGH */ - .bat_irq = IRQ_EINT(0), /* GPIO_TA_INT */ - .bat_irq_attr = - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - .cable_check_type = - SEC_BATTERY_CABLE_CHECK_NOUSBCHARGE | - SEC_BATTERY_CABLE_CHECK_INT, - .cable_source_type = SEC_BATTERY_CABLE_SOURCE_ADC, - - .event_check = false, - .event_waiting_time = 60, - - /* Monitor setting */ - .polling_type = SEC_BATTERY_MONITOR_ALARM, - .monitor_initial_count = 3, - - /* Battery check */ - .battery_check_type = SEC_BATTERY_CHECK_NONE, - .check_count = 3, - - /* Battery check by ADC */ - .check_adc_max = 0, - .check_adc_min = 0, - - /* OVP/UVLO check */ - .ovp_uvlo_check_type = SEC_BATTERY_OVP_UVLO_CHGINT, - - /* Temperature check */ - .thermal_source = SEC_BATTERY_THERMAL_SOURCE_FG, - - .temp_check_type = SEC_BATTERY_TEMP_CHECK_TEMP, - .temp_check_count = 3, - .temp_high_threshold_event = 650, - .temp_high_recovery_event = 450, - .temp_low_threshold_event = 0, - .temp_low_recovery_event = -50, - .temp_high_threshold_normal = 470, - .temp_high_recovery_normal = 400, - .temp_low_threshold_normal = 0, - .temp_low_recovery_normal = -30, - .temp_high_threshold_lpm = 600, - .temp_high_recovery_lpm = 420, - .temp_low_threshold_lpm = 2, - .temp_low_recovery_lpm = -30, - - .full_check_type = SEC_BATTERY_FULLCHARGED_CHGGPIO, - .full_check_count = 3, - .full_check_adc_1st = 26500, /* CHECK ME */ - .full_check_adc_2nd = 25800, /* CHECK ME */ - .chg_gpio_full_check = GPIO_TA_nCHG, /* STAT of bq24191 */ - .chg_polarity_full_check = 1, - .full_condition_type = - SEC_BATTERY_FULL_CONDITION_SOC | - SEC_BATTERY_FULL_CONDITION_OCV, - .full_condition_soc = 99, - .full_condition_ocv = 4170, - - .recharge_condition_type = - SEC_BATTERY_RECHARGE_CONDITION_SOC | - SEC_BATTERY_RECHARGE_CONDITION_VCELL, - .recharge_condition_soc = 98, - .recharge_condition_avgvcell = 4150, - .recharge_condition_vcell = 4150, - - .charging_total_time = 6 * 60 * 60, - .recharging_total_time = 90 * 60, - .charging_reset_time = 10 * 60, - - /* Fuel Gauge */ - .fg_irq = IRQ_EINT(19), /* GPIO_FUEL_ALERT */ - .fg_irq_attr = IRQF_TRIGGER_LOW | IRQF_ONESHOT, - .fuel_alert_soc = 1, - .repeated_fuelalert = false, - .capacity_calculation_type = - SEC_FUELGAUGE_CAPACITY_TYPE_RAW, - /* SEC_FUELGAUGE_CAPACITY_TYPE_SCALE | */ - /* SEC_FUELGAUGE_CAPACITY_TYPE_ATOMIC, */ - .capacity_max = 1000, - .capacity_min = 0, - - /* Charger */ - .chg_gpio_en = GPIO_TA_EN, - .chg_polarity_en = 0, /* active LOW charge enable */ - .chg_gpio_status = GPIO_TA_nCHG, - .chg_polarity_status = 0, -#if defined(CONFIG_MACH_P10_LTE_00_BD) || defined(CONFIG_MACH_P10_WIFI_00_BD) - .chg_irq = 0, - .chg_irq_attr = 0, -#else - .chg_irq = IRQ_EINT(4), /* GPIO_CHG_INT */ - .chg_irq_attr = IRQF_TRIGGER_FALLING | IRQF_ONESHOT, -#endif - .chg_float_voltage = 4200, -}; - -static struct platform_device sec_device_battery = { - .name = "sec-battery", - .id = -1, - .dev.platform_data = &sec_battery_pdata, -}; - -static struct i2c_gpio_platform_data gpio_i2c_data_fuelgauge = { - .sda_pin = GPIO_FUEL_SDA_18V, - .scl_pin = GPIO_FUEL_SCL_18V, -}; - -struct platform_device sec_device_fuelgauge = { - .name = "i2c-gpio", - .id = SEC_FUELGAUGE_I2C_ID, - .dev.platform_data = &gpio_i2c_data_fuelgauge, -}; - -static struct i2c_board_info sec_brdinfo_fuelgauge[] __initdata = { - { - I2C_BOARD_INFO("sec-fuelgauge", - SEC_FUELGAUGE_I2C_SLAVEADDR), - .platform_data = &sec_battery_pdata, - }, -}; - -static struct i2c_gpio_platform_data gpio_i2c_data_charger = { - .sda_pin = GPIO_CHG_SDA_18V, - .scl_pin = GPIO_CHG_SCL_18V, -}; - -struct platform_device sec_device_charger = { - .name = "i2c-gpio", - .id = SEC_CHARGER_I2C_ID, - .dev.platform_data = &gpio_i2c_data_charger, -}; - -static struct i2c_board_info sec_brdinfo_charger[] __initdata = { - { - I2C_BOARD_INFO("sec-charger", - SEC_CHARGER_I2C_SLAVEADDR), - .platform_data = &sec_battery_pdata, - }, -}; - -static struct platform_device *sec_battery_devices[] __initdata = { - &sec_device_charger, - &sec_device_fuelgauge, - &sec_device_battery, -}; - -void __init p10_battery_init(void) -{ - platform_add_devices( - sec_battery_devices, - ARRAY_SIZE(sec_battery_devices)); - - i2c_register_board_info( - SEC_CHARGER_I2C_ID, - sec_brdinfo_charger, - ARRAY_SIZE(sec_brdinfo_charger)); - - i2c_register_board_info( - SEC_FUELGAUGE_I2C_ID, - sec_brdinfo_fuelgauge, - ARRAY_SIZE(sec_brdinfo_fuelgauge)); -} -#endif /* CONFIG_BATTERY_SAMSUNG_P1X */ diff --git a/arch/arm/mach-exynos/p10-gpio.c b/arch/arm/mach-exynos/p10-gpio.c deleted file mode 100644 index 3e6c9d3..0000000 --- a/arch/arm/mach-exynos/p10-gpio.c +++ /dev/null @@ -1,580 +0,0 @@ -/* - * linux/arch/arm/mach-exynos/p10-gpio.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS - GPIO setting in set board - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gpio.h> -#include <linux/serial_core.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/regs-serial.h> -#include <mach/gpio-midas.h> -#include <plat/cpu.h> -#include <mach/pmu.h> - -struct gpio_init_data { - uint num; - uint cfg; - uint val; - uint pud; - uint drv; -}; - -extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); -extern int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); - -/* this is sample code for p10 board */ -static struct gpio_init_data p10_init_gpios[] = { - - /* BT_UART_RXD */ - {EXYNOS5_GPA0(0), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP}, - /* BT_UART_TXD */ - {EXYNOS5_GPA0(1), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, - /* BT_UART_CTS */ - {EXYNOS5_GPA0(2), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, - /* BT_UART_RTS */ - {EXYNOS5_GPA0(3), S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, - - /* UART switch: configure as output */ - {EXYNOS5_GPE0(5), S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE}, - /* USB switch: configure as output */ - {EXYNOS5_GPH0(1), S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE}, - - {EXYNOS5_GPB2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */ - {EXYNOS5_GPB2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */ - - {EXYNOS5_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* DET_3.5 */ - {EXYNOS5_GPX0(2), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */ - - {EXYNOS5_GPX2(0), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */ - {EXYNOS5_GPX2(1), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */ - {EXYNOS5_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ADC_INT */ - {EXYNOS5_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKE */ -}; - -/* Initialize gpio set in p10 board */ -void p10_config_gpio_table(void) -{ - u32 i, gpio; - - printk(KERN_DEBUG "%s\n", __func__); - - for (i = 0; i < ARRAY_SIZE(p10_init_gpios); i++) { - gpio = p10_init_gpios[i].num; - s3c_gpio_cfgpin(gpio, p10_init_gpios[i].cfg); - s3c_gpio_setpull(gpio, p10_init_gpios[i].pud); - - if (p10_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) - gpio_set_value(gpio, p10_init_gpios[i].val); - - s5p_gpio_set_drvstr(gpio, p10_init_gpios[i].drv); - } -} - -/* this table only for p10 board */ -static unsigned int exynos5_sleep_gpio_table[][3] = { - {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_UP}, /* BT_UART_RXD */ - {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT1, - S3C_GPIO_PULL_NONE}, /* BT_UART_TXD */ - {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* BT_UART_CTS */ - {EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT1, - S3C_GPIO_PULL_NONE}, /* BT_UART_RTS */ - {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* GPS_UART_RXD */ - {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* GPS_UART_TXD */ - {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* GPS_UART_CTS */ - {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* GPS_UART_RTS */ - - {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* AP_RXD */ - {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* AP_TXD */ - {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* TSP_SDA_1.8V */ - {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* TSP_SCL_1.8V */ - {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* AP_FLM_RXD */ - {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* AP_FLM_TXD */ - - {EXYNOS5_GPA2(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* CHG_SDA_1.8V */ - {EXYNOS5_GPA2(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* CHG_SCL_1.8V */ - {EXYNOS5_GPA2(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* AP_PMIC_SDA */ - {EXYNOS5_GPA2(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* AP_PMIC_SCL */ - {EXYNOS5_GPA2(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* 5M_SPI_CLK */ - {EXYNOS5_GPA2(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* 5M_SPI_CS */ - {EXYNOS5_GPA2(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* 5M_SPI_DI */ - {EXYNOS5_GPA2(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* 5M_SPI_DO */ - - {EXYNOS5_GPB0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* AP_CP_INT */ - {EXYNOS5_GPB0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CMC221_CPU_RST */ - {EXYNOS5_GPB0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CMC_SPI_CLK_REQ */ - {EXYNOS5_GPB0(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPB0(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPB1(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* BARO_INT */ - {EXYNOS5_GPB1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPB1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPB1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPB1(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPB2(0), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* LCD_PWM_IN_1.8V */ - {EXYNOS5_GPB2(1), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* MOTOR_PWM */ - {EXYNOS5_GPB2(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* CODEC_SDA_1.8V */ - {EXYNOS5_GPB2(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* CODEC_SCL_1.8V */ - - {EXYNOS5_GPB3(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MHL_DSDA_1.8V */ - {EXYNOS5_GPB3(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MHL_DSCL_1.8V */ - {EXYNOS5_GPB3(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* GSENSE_SDA_1.8V */ - {EXYNOS5_GPB3(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* GSENSE_SCL_1.8V */ - - {EXYNOS5_GPC0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_CLK */ - {EXYNOS5_GPC0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_CMD */ - {EXYNOS5_GPC0(2), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* eMMC_EN */ - {EXYNOS5_GPC0(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(0) */ - {EXYNOS5_GPC0(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(1) */ - {EXYNOS5_GPC0(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(2) */ - {EXYNOS5_GPC0(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(3) */ - - {EXYNOS5_GPC1(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPC1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPC1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPC1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(4) */ - {EXYNOS5_GPC1(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(5) */ - {EXYNOS5_GPC1(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(6) */ - {EXYNOS5_GPC1(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NAND_D(7) */ - - {EXYNOS5_GPC2(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* T_FLASH_CLK */ - {EXYNOS5_GPC2(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* T_FLASH_CMD */ - {EXYNOS5_GPC2(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPC2(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(0) */ - {EXYNOS5_GPC2(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(1) */ - {EXYNOS5_GPC2(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(2) */ - {EXYNOS5_GPC2(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(3) */ - - {EXYNOS5_GPC3(0), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CLK */ - {EXYNOS5_GPC3(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CMD */ - {EXYNOS5_GPC3(2), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* OTG_EN */ - {EXYNOS5_GPC3(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(0) */ - {EXYNOS5_GPC3(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(1) */ - {EXYNOS5_GPC3(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(2) */ - {EXYNOS5_GPC3(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(3) */ - - {EXYNOS5_GPD0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* FUEL_SDA_1.8V */ - {EXYNOS5_GPD0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* FUEL_SCL_1.8V */ - {EXYNOS5_GPD0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* BSENSE_SDA_1.8V */ - {EXYNOS5_GPD0(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* BSENSE_SCL_1.8V */ - {EXYNOS5_GPD0(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MHL_SDA_1.8V */ - {EXYNOS5_GPD0(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MHL_SCL_1.8V */ - {EXYNOS5_GPD0(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* LCDP_SCL__1.8V */ - {EXYNOS5_GPD0(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* LCDP_SDA__1.8V */ - - {EXYNOS5_GPD1(0), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* HDMI_EN */ - {EXYNOS5_GPD1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPD1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MOTOR_SDA_1.8V */ - {EXYNOS5_GPD1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MOTOR_SCL_1.8V */ - {EXYNOS5_GPD1(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* LCD_ID */ - {EXYNOS5_GPD1(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CMC_PMIC_PWRON */ - {EXYNOS5_GPD1(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NFC_EN, NC */ - {EXYNOS5_GPD1(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NFC_FIRMWARE, NC */ - - {EXYNOS5_GPE0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CIS_nRST */ - {EXYNOS5_GPE0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* CHG_SDA_1.8V */ - {EXYNOS5_GPE0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* CHG_SCL_1.8V */ - {EXYNOS5_GPE0(3), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */ - {EXYNOS5_GPE0(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* ACCESSORY_CHECK */ - {EXYNOS5_GPE0(5), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* UART_SEL */ - {EXYNOS5_GPE0(6), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* GPS_nRST */ - {EXYNOS5_GPE0(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* ISP_TXD */ - - {EXYNOS5_GPE1(0), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* GPS_EN */ - {EXYNOS5_GPE1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* ISP_RXD */ - - {EXYNOS5_GPF0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* 5M_CAM_SDA_1.8V */ - {EXYNOS5_GPF0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* 5M_CAM_SCL_1.8V */ - {EXYNOS5_GPF0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* VT_CAM_SDA_1.8V */ - {EXYNOS5_GPF0(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* VT_CAM_SCL_1.8V */ - - {EXYNOS5_GPF1(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPF1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPF1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPF1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPG0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* ALS_SDA_1.8V */ - {EXYNOS5_GPG0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /*ALS_SCL_1.8V */ - {EXYNOS5_GPG0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* USB3.0_EN */ - {EXYNOS5_GPG0(3), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* FM34_PWDN */ - {EXYNOS5_GPG0(4), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* FM34_RESET */ - {EXYNOS5_GPG0(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* MHL_INT */ - {EXYNOS5_GPG0(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* MHL_RST */ - - {EXYNOS5_GPG1(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CAM_FLASH_EN */ - {EXYNOS5_GPG1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CAM_FLASH_SET */ - {EXYNOS5_GPG1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* TOUCH_CHG */ - {EXYNOS5_GPG1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* TOUCH_RESET */ - {EXYNOS5_GPG1(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* TA_nCHG */ - {EXYNOS5_GPG1(5), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* TA_EN */ - {EXYNOS5_GPG1(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CAM_VT_nRST */ - {EXYNOS5_GPG1(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPG2(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPG2(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* VTCAM_MCLK */ - - {EXYNOS5_GPH0(0), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* WLAN_EN */ - {EXYNOS5_GPH0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* USB_SEL1 */ - {EXYNOS5_GPH0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPH0(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CAM_MCLK */ - - {EXYNOS5_GPH1(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPH1(1), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */ - {EXYNOS5_GPH1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* LIGHT_nINT */ - {EXYNOS5_GPH1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* BT_WAKE */ - {EXYNOS5_GPH1(4), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* FM34_BYPASS */ - {EXYNOS5_GPH1(5), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* ACCESSORY_EN */ - {EXYNOS5_GPH1(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPH1(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* LCD_EN */ - - {EXYNOS5_GPV0(0), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */ - {EXYNOS5_GPV0(1), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */ - {EXYNOS5_GPV0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* 5M_CORE_EN */ - {EXYNOS5_GPV0(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* CAM_IO_EN */ - {EXYNOS5_GPV0(4), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */ - {EXYNOS5_GPV0(5), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */ - {EXYNOS5_GPV0(6), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */ - {EXYNOS5_GPV0(7), S3C_GPIO_SLP_OUT0, - S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */ - - {EXYNOS5_GPV1(0), S3C_GPIO_SLP_PREV, - S3C_GPIO_PULL_NONE}, /* WLAN_WAKE */ - {EXYNOS5_GPV1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* HW_REV3 */ - {EXYNOS5_GPV1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* HW_REV2 */ - {EXYNOS5_GPV1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* HW_REV1 */ - {EXYNOS5_GPV1(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* HW_REV0 */ - {EXYNOS5_GPV1(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV1(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV1(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPV2(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV2(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV2(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV2(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV2(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* HUM_SCL_1.8V */ - {EXYNOS5_GPV2(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* HUM_SDA_1.8V */ - {EXYNOS5_GPV2(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MSENSE_SCL_1.8V */ - {EXYNOS5_GPV2(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* MSENSE_SDA_1.8V */ - - {EXYNOS5_GPV3(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* ADC_SCL_1.8V */ - {EXYNOS5_GPV3(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_NONE}, /* ADC_SDA_1.8V */ - {EXYNOS5_GPV3(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV3(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV3(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV3(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV3(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPV3(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPY0(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_CSN */ - {EXYNOS5_GPY0(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY0(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY0(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY0(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_REN */ - {EXYNOS5_GPY0(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_WEN */ - - {EXYNOS5_GPY1(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY1(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY1(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY1(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPY2(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* TF_EN */ - {EXYNOS5_GPY2(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY2(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY2(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY2(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY2(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPY3(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(0) */ - {EXYNOS5_GPY3(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(1) */ - {EXYNOS5_GPY3(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(2) */ - {EXYNOS5_GPY3(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(3) */ - {EXYNOS5_GPY3(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(4) */ - {EXYNOS5_GPY3(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(5) */ - {EXYNOS5_GPY3(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(6) */ - {EXYNOS5_GPY3(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(7) */ - - {EXYNOS5_GPY4(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(8) */ - {EXYNOS5_GPY4(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(9) */ - {EXYNOS5_GPY4(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(10) */ - {EXYNOS5_GPY4(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(11) */ - {EXYNOS5_GPY4(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(12) */ - {EXYNOS5_GPY4(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_A(13) */ - {EXYNOS5_GPY4(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPY4(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS5_GPY5(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(0) */ - {EXYNOS5_GPY5(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(1) */ - {EXYNOS5_GPY5(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(2) */ - {EXYNOS5_GPY5(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(3) */ - {EXYNOS5_GPY5(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(4) */ - {EXYNOS5_GPY5(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(5) */ - {EXYNOS5_GPY5(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(6) */ - {EXYNOS5_GPY5(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(7) */ - - {EXYNOS5_GPY6(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(8) */ - {EXYNOS5_GPY6(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(9) */ - {EXYNOS5_GPY6(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(10) */ - {EXYNOS5_GPY6(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(11) */ - {EXYNOS5_GPY6(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(12) */ - {EXYNOS5_GPY6(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(13) */ - {EXYNOS5_GPY6(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(14) */ - {EXYNOS5_GPY6(7), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* DPRAM_D(15) */ - - {EXYNOS5_GPZ(0), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* MM_I2S_CLK */ - {EXYNOS5_GPZ(1), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPZ(2), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* MM_I2S_SYNC */ - {EXYNOS5_GPZ(3), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* MM_I2S_DI */ - {EXYNOS5_GPZ(4), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* MM_I2S_DO */ - {EXYNOS5_GPZ(5), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS5_GPZ(6), S3C_GPIO_SLP_INPUT, - S3C_GPIO_PULL_DOWN}, /* NC */ -}; - -static void config_sleep_gpio_table(int array_size, - unsigned int (*gpio_table)[3]) -{ - u32 i, gpio; - - for (i = 0; i < array_size; i++) { - gpio = gpio_table[i][0]; - s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); - s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); - } -} - -/* To save power consumption, gpio pin set before enterling sleep */ -void p10_config_sleep_gpio_table(void) -{ - config_sleep_gpio_table(ARRAY_SIZE(exynos5_sleep_gpio_table), - exynos5_sleep_gpio_table); -} diff --git a/arch/arm/mach-exynos/p10-input.c b/arch/arm/mach-exynos/p10-input.c deleted file mode 100644 index 0e781a2..0000000 --- a/arch/arm/mach-exynos/p10-input.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * arch/arm/mach-exynos/p4-input.c - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/i2c.h> -#include <linux/err.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/regulator/consumer.h> -#include <plat/gpio-cfg.h> -#include <plat/iic.h> - -#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S) -#include <linux/i2c/mxt1664s.h> -#endif - -#if defined(CONFIG_KEYBOARD_GPIO) -#include <mach/sec_debug.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#endif - -#define GPIO_TOUCH_EN EXYNOS5_GPD1(1) - -#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S) - -static int ts_power_on(void) -{ - struct regulator *regulator; - - /* touch reset pin */ - s3c_gpio_cfgpin(GPIO_TOUCH_RESET, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TOUCH_RESET, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TOUCH_RESET, 0); - - /* touch xvdd en pin */ - s3c_gpio_cfgpin(GPIO_TOUCH_EN, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TOUCH_EN, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TOUCH_EN, 0); - - regulator = regulator_get(NULL, "touch_vdd_1.8v"); - if (IS_ERR(regulator)) { - printk(KERN_ERR "[TSP]ts_power_on : regulator_get failed\n"); - return -EIO; - } - - regulator_enable(regulator); - regulator_put(regulator); - - regulator = regulator_get(NULL, "touch_avdd"); - if (IS_ERR(regulator)) { - printk(KERN_ERR "[TSP]ts_power_on : regulator_get failed\n"); - return -EIO; - } - regulator_enable(regulator); - regulator_put(regulator); - - /* enable touch xvdd */ - gpio_set_value(GPIO_TOUCH_EN, 1); - - /* reset ic */ - mdelay(1); - gpio_set_value(GPIO_TOUCH_RESET, 1); - - /* touch interrupt pin */ - /* s3c_gpio_cfgpin(GPIO_TOUCH_CHG, S3C_GPIO_INPUT); */ - - s3c_gpio_cfgpin(GPIO_TOUCH_CHG, S3C_GPIO_SFN(0xf)); - s3c_gpio_setpull(GPIO_TOUCH_CHG, S3C_GPIO_PULL_NONE); - - msleep(MXT_1664S_HW_RESET_TIME); - - printk(KERN_ERR "mxt_power_on is finished\n"); - - return 0; -} - -static int ts_power_off(void) -{ - struct regulator *regulator; - - regulator = regulator_get(NULL, "touch_avdd"); - if (IS_ERR(regulator)) { - printk(KERN_ERR "[TSP]ts_power_off : regulator_get failed\n"); - return -EIO; - } - - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - - regulator_put(regulator); - - /* CAUTION : EVT1 board has CHG_INT problem - * so it need a workaround code to ensure charging during sleep mode - */ - if (system_rev != 2) { - regulator = regulator_get(NULL, "touch_vdd_1.8v"); - if (IS_ERR(regulator)) { - printk(KERN_ERR "[TSP]ts_power_on : regulator_get failed\n"); - return -EIO; - } - - if (regulator_is_enabled(regulator)) - regulator_force_disable(regulator); - - regulator_put(regulator); - } - - /* touch interrupt pin */ - s3c_gpio_cfgpin(GPIO_TOUCH_CHG, S3C_GPIO_INPUT); - s3c_gpio_setpull(GPIO_TOUCH_CHG, S3C_GPIO_PULL_NONE); - - /* touch reset pin */ - s3c_gpio_cfgpin(GPIO_TOUCH_RESET, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TOUCH_RESET, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TOUCH_RESET, 0); - - /* touch xvdd en pin */ - s3c_gpio_cfgpin(GPIO_TOUCH_EN, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TOUCH_EN, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TOUCH_EN, 0); - - printk(KERN_ERR "mxt_power_off is finished\n"); - - return 0; -} - -/* - Configuration for MXT1664-S -*/ -#define MXT1664S_MAX_MT_FINGERS 10 -#define MXT1664S_BLEN_BATT 208 -#define MXT1664S_CHRGTIME_BATT 130 -#define MXT1664S_THRESHOLD_BATT 70 - -static u8 t7_config_s[] = { GEN_POWERCONFIG_T7, - 255, 255, 50, 3 -}; - -static u8 t8_config_s[] = { GEN_ACQUISITIONCONFIG_T8, - MXT1664S_CHRGTIME_BATT, 0, 10, 10, 0, 0, 20, 35, 0, 0 -}; - -static u8 t9_config_s[] = { TOUCH_MULTITOUCHSCREEN_T9, - 139, 0, 0, 32, 52, 0, MXT1664S_BLEN_BATT, MXT1664S_THRESHOLD_BATT, 2, 1, - 0, 5, 2, 0, MXT1664S_MAX_MT_FINGERS, 10, 20, 20, 63, 6, - 255, 9, 0, 0, 0, 0, 0, 0, 0, 0, - 15, 15, 42, 42, 0, 0 -}; - -static u8 t15_config_s[] = { TOUCH_KEYARRAY_T15, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0 -}; - -static u8 t18_config_s[] = { SPT_COMCONFIG_T18, - 0, 0 -}; - -static u8 t24_config_s[] = { - PROCI_ONETOUCHGESTUREPROCESSOR_T24, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t25_config_s[] = { - SPT_SELFTEST_T25, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 200 -}; - -static u8 t27_config_s[] = { - PROCI_TWOTOUCHGESTUREPROCESSOR_T27, - 0, 0, 0, 0, 0, 0, 0 -}; - -static u8 t40_config_s[] = { PROCI_GRIPSUPPRESSION_T40, - 0, 0, 0, 0, 0 -}; - -static u8 t42_config_s[] = { PROCI_TOUCHSUPPRESSION_T42, - 0, 60, 100, 60, 0, 20, 0, 0, 0, 0 -}; - -static u8 t43_config_s[] = { SPT_DIGITIZER_T43, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0 -}; - -static u8 t46_config_s[] = { SPT_CTECONFIG_T46, - 4, 0, 24, 24, 0, 0, 2, 0, 0, 0, - 0 -}; - -static u8 t47_config_s[] = { PROCI_STYLUS_T47, - 73, 20, 45, 4, 5, 30, 1, 120, 3, 32, - 0, 0, 15, 0, 32, 230, 0, 0, 0, 0 -}; - -static u8 t55_config_s[] = {ADAPTIVE_T55, - 0, 0, 0, 0, 0, 0 -}; - -static u8 t56_config_s[] = {PROCI_SHIELDLESS_T56, - 1, 0, 1, 24, 28, 28, 28, 28, 28, 28, - 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, - 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, - 28, 28, 28, 28, 28, 28, 2, 16, 0, 2, - 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, - 0 -}; - -static u8 t57_config_s[] = {PROCI_EXTRATOUCHSCREENDATA_T57, - 226, 25, 0 -}; - -static u8 t61_config_s[] = {SPT_TIMER_T61, - 0, 0, 0, 0, 0 -}; - -static u8 t62_config_s[] = {PROCG_NOISESUPPRESSION_T62, - 3, 0, 0, 23, 2, 0, 0, 0, 50, 0, - 0, 0, 0, 0, 5, 0, 10, 3, 5, 144, - 50, 20, 48, 20, 100, 16, 16, 4, 255, 0, - 0, 0, 0, 0, 176, 80, 2, 5, 1, 48, - 10, 20, 30, 0, 0, 0, 0, 0, 0, 0, - 0, 16, 10, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0 -}; -static u8 end_config_s[] = { RESERVED_T255 }; - -static const u8 *MXT1644S_config[] = { - t7_config_s, - t8_config_s, - t9_config_s, - t15_config_s, - t18_config_s, - t24_config_s, - t25_config_s, - t27_config_s, - t40_config_s, - t42_config_s, - t43_config_s, - t46_config_s, - t47_config_s, - t55_config_s, - t56_config_s, - t57_config_s, - t61_config_s, - t62_config_s, - end_config_s, -}; - -static struct mxt_platform_data mxt_data = { - .max_finger_touches = MXT1664S_MAX_MT_FINGERS, - .gpio_read_done = GPIO_TOUCH_CHG, - .min_x = 0, - .max_x = 2559, - .min_y = 0, - .max_y = 1599, - .min_z = 0, - .max_z = 255, - .min_w = 0, - .max_w = 255, - .config = MXT1644S_config, - .power_on = ts_power_on, - .power_off = ts_power_off, - .boot_address = 0x26, -}; -#endif - -static struct i2c_board_info i2c_devs3[] __initdata = { - { - I2C_BOARD_INFO(MXT_DEV_NAME, 0x4A), - .platform_data = &mxt_data, - } -}; - -void __init p10_tsp_init(void) -{ - int gpio; - - gpio = GPIO_TOUCH_CHG; - gpio_request(gpio, "TSP_INT"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_INPUT); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_register_gpio_interrupt(GPIO_TOUCH_CHG); - i2c_devs3[0].irq = gpio_to_irq(gpio); - - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, i2c_devs3, ARRAY_SIZE(i2c_devs3)); - - printk(KERN_ERR "%s touch : %d\n", __func__, i2c_devs3[0].irq); -} - -#if defined(CONFIG_KEYBOARD_GPIO) -#if defined(CONFIG_SEC_DEBUG) -#define GPIO_KEYS(_code, _gpio, _active_low, _iswake, _hook) \ - { \ - .code = _code, \ - .gpio = _gpio, \ - .active_low = _active_low, \ - .type = EV_KEY, \ - .wakeup = _iswake, \ - .debounce_interval = 10, \ - .isr_hook = _hook, \ - .value = 1 \ - } - -struct gpio_keys_button p10_buttons[] = { - GPIO_KEYS(KEY_VOLUMEUP, GPIO_VOL_UP, - 1, 0, sec_debug_check_crash_key), - GPIO_KEYS(KEY_VOLUMEDOWN, GPIO_VOL_DOWN, - 1, 0, sec_debug_check_crash_key), - GPIO_KEYS(KEY_POWER, GPIO_nPOWER, - 1, 1, sec_debug_check_crash_key), -}; -#endif - -struct gpio_keys_platform_data p10_gpiokeys_platform_data = { - p10_buttons, - ARRAY_SIZE(p10_buttons), -}; - -static struct platform_device p10_keypad = { - .name = "gpio-keys", - .dev = { - .platform_data = &p10_gpiokeys_platform_data, - }, -}; -#endif - -void __init p10_key_init(void) -{ -#if defined(CONFIG_KEYBOARD_GPIO) - platform_device_register(&p10_keypad); -#endif -} - diff --git a/arch/arm/mach-exynos/p10-mhl.c b/arch/arm/mach-exynos/p10-mhl.c deleted file mode 100644 index cb36311..0000000 --- a/arch/arm/mach-exynos/p10-mhl.c +++ /dev/null @@ -1,130 +0,0 @@ -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/i2c-gpio.h> -#include <linux/irq.h> -#include <linux/delay.h> -#include <linux/sii9234.h> - -#include <plat/gpio-cfg.h> -#include <mach/regs-gpio.h> -#include <mach/gpio.h> -#include "midas.h" - -#ifdef CONFIG_SAMSUNG_MHL -#define I2C_BUS_ID_MHL 15 -static void sii9234_cfg_gpio(void) -{ - printk(KERN_INFO "%s()\n", __func__); - - /* AP_MHL_SDA */ - s3c_gpio_cfgpin(GPIO_MHL_SDA_18V, S3C_GPIO_SFN(0x0)); - s3c_gpio_setpull(GPIO_MHL_SDA_18V, S3C_GPIO_PULL_NONE); - - /* AP_MHL_SCL */ - s3c_gpio_cfgpin(GPIO_MHL_SCL_18V, S3C_GPIO_SFN(0x1)); - s3c_gpio_setpull(GPIO_MHL_SCL_18V, S3C_GPIO_PULL_NONE); - - - gpio_request(GPIO_MHL_INT, "MHL_INT"); - s5p_register_gpio_interrupt(GPIO_MHL_INT); - s3c_gpio_setpull(GPIO_MHL_INT, S3C_GPIO_PULL_DOWN); - irq_set_irq_type(MHL_INT_IRQ, IRQ_TYPE_EDGE_RISING); - s3c_gpio_cfgpin(GPIO_MHL_INT, GPIO_MHL_INT_AF); - - s3c_gpio_cfgpin(GPIO_HDMI_EN, S3C_GPIO_OUTPUT); /* HDMI_EN */ - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW); - s3c_gpio_setpull(GPIO_HDMI_EN, S3C_GPIO_PULL_NONE); - - s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); -} - -static void sii9234_power_onoff(bool on) -{ - printk(KERN_INFO "%s(%d)\n", __func__, on); - - if (on) { - /* To avoid floating state of the HPD pin * - * in the absence of external pull-up */ - s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_HIGH); - - s3c_gpio_setpull(GPIO_MHL_SCL_18V, S3C_GPIO_PULL_DOWN); - s3c_gpio_setpull(GPIO_MHL_SCL_18V, S3C_GPIO_PULL_NONE); - - /* sii9234_unmaks_interrupt(); // - need to add */ - /* VCC_SUB_2.0V is always on */ - } else { - gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); - usleep_range(10000, 20000); - gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH); - - /* To avoid floating state of the HPD pin * - * in the absence of external pull-up */ - s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN); - gpio_set_value(GPIO_HDMI_EN, GPIO_LEVEL_LOW); - - gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); - } -} - -static void sii9234_reset(void) -{ - printk(KERN_INFO "%s()\n", __func__); - - s3c_gpio_cfgpin(GPIO_MHL_RST, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_MHL_RST, S3C_GPIO_PULL_NONE); - - - gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_LOW); - usleep_range(10000, 20000); - gpio_set_value(GPIO_MHL_RST, GPIO_LEVEL_HIGH); -} - - - -static struct sii9234_platform_data sii9234_pdata = { - .init = sii9234_cfg_gpio, - .mhl_sel = NULL, - .hw_onoff = sii9234_power_onoff, - .hw_reset = sii9234_reset, - .enable_vbus = NULL, - .vbus_present = NULL, -}; - -static struct i2c_board_info __initdata i2c_devs_sii9234[] = { - { - I2C_BOARD_INFO("sii9234_mhl_tx", 0x72>>1), - .platform_data = &sii9234_pdata, - }, - { - I2C_BOARD_INFO("sii9234_tpi", 0x7A>>1), - .platform_data = &sii9234_pdata, - }, - { - I2C_BOARD_INFO("sii9234_hdmi_rx", 0x92>>1), - .platform_data = &sii9234_pdata, - }, - { - I2C_BOARD_INFO("sii9234_cbus", 0xC8>>1), - .platform_data = &sii9234_pdata, - }, -}; - -static struct i2c_board_info i2c_dev_hdmi_ddc __initdata = { - I2C_BOARD_INFO("s5p_ddc", (0x74 >> 1)), -}; - -static int __init p10_mhl_init(void) -{ - i2c_add_devices(I2C_BUS_ID_MHL, i2c_devs_sii9234, - ARRAY_SIZE(i2c_devs_sii9234)); - - i2c_add_devices(sii9234_pdata.ddc_i2c_num, &i2c_dev_hdmi_ddc, 1); - - return 0; -} -module_init(p10_mhl_init); -#endif diff --git a/arch/arm/mach-exynos/p10-switch.c b/arch/arm/mach-exynos/p10-switch.c deleted file mode 100644 index 977b6e5..0000000 --- a/arch/arm/mach-exynos/p10-switch.c +++ /dev/null @@ -1,239 +0,0 @@ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/err.h> -#include <linux/semaphore.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio.h> -#include <mach/usb_switch.h> - -struct device *sec_switch_dev; - -enum usb_path_t current_path = USB_PATH_NONE; - -static struct semaphore usb_switch_sem; - -static bool usb_connected; - -static ssize_t show_usb_sel(struct device *dev, - struct device_attribute *attr, char *buf) -{ - const char *mode; - - if (current_path & USB_PATH_CP) { - /* CP */ - mode = "MODEM"; - } else { - /* AP */ - mode = "PDA"; - } - - pr_info("%s: %s\n", __func__, mode); - - return sprintf(buf, "%s\n", mode); -} - -static ssize_t store_usb_sel(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - pr_info("%s: %s\n", __func__, buf); - - if (!strncasecmp(buf, "PDA", 3)) { - usb_switch_lock(); - usb_switch_clr_path(USB_PATH_CP); - usb_switch_unlock(); - } else if (!strncasecmp(buf, "MODEM", 5)) { - usb_switch_lock(); - usb_switch_set_path(USB_PATH_CP); - usb_switch_unlock(); - } else { - pr_err("%s: wrong usb_sel value(%s)!!\n", __func__, buf); - return -EINVAL; - } - - return count; -} - -static ssize_t show_uart_sel(struct device *dev, - struct device_attribute *attr, char *buf) -{ - int val_sel; - const char *mode; - - val_sel = gpio_get_value(GPIO_UART_SEL); - - if (val_sel == 0) { - /* CP */ - mode = "CP"; - } else { - /* AP */ - mode = "AP"; - } - - pr_info("%s: %s\n", __func__, mode); - - return sprintf(buf, "%s\n", mode); -} - -static ssize_t store_uart_sel(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - int uart_sel = -1; - - pr_info("%s: %s\n", __func__, buf); - - if (!strncasecmp(buf, "AP", 2)) { - uart_sel = 1; - } else if (!strncasecmp(buf, "CP", 2)) { - uart_sel = 0; - } else { - pr_err("%s: wrong uart_sel value(%s)!!\n", __func__, buf); - return -EINVAL; - } - - /* 1 for AP, 0 for CP */ - gpio_set_value(GPIO_UART_SEL, uart_sel); - - return count; -} - -static ssize_t show_usb_state(struct device *dev, - struct device_attribute *attr, char *buf) -{ - const char *state; - - if (usb_connected) - state = "USB_STATE_CONFIGURED"; - else - state = "USB_STATE_NOTCONFIGURED"; - - pr_info("%s: %s\n", __func__, state); - - return sprintf(buf, "%s\n", state); -} - -static DEVICE_ATTR(usb_sel, 0664, show_usb_sel, store_usb_sel); -static DEVICE_ATTR(uart_sel, 0664, show_uart_sel, store_uart_sel); -static DEVICE_ATTR(usb_state, S_IRUGO, show_usb_state, NULL); - -static struct attribute *px_switch_attributes[] = { - &dev_attr_usb_sel.attr, - &dev_attr_uart_sel.attr, - &dev_attr_usb_state.attr, - NULL -}; - -static const struct attribute_group px_switch_group = { - .attrs = px_switch_attributes, -}; - -void set_usb_connection_state(bool connected) -{ - pr_info("%s: set %s\n", __func__, (connected ? "True" : "False")); - - if (usb_connected != connected) { - usb_connected = connected; - - pr_info("%s: send \"usb_state\" sysfs_notify\n", __func__); - sysfs_notify(&sec_switch_dev->kobj, NULL, "usb_state"); - } -} - -static void usb_apply_path(enum usb_path_t path) -{ - pr_info("%s: current gpio before changing : sel1:%d\n", - __func__, gpio_get_value(GPIO_USB_SEL1)); - pr_info("%s: target path %x\n", __func__, path); - - if (path & USB_PATH_ADCCHECK) { - gpio_set_value(GPIO_USB_SEL1, 0); - return; - } - - /* default : AP */ - gpio_set_value(GPIO_USB_SEL1, 1); - return; - -} - -/* - Typical usage of usb switch: - - usb_switch_lock(); (alternatively from hard/soft irq context) - ( or usb_switch_trylock() ) - ... - usb_switch_set_path(USB_PATH_ADCCHECK); - ... - usb_switch_set_path(USB_PATH_TA); - ... - usb_switch_unlock(); (this restores previous usb switch settings) -*/ -void usb_switch_set_path(enum usb_path_t path) -{ - pr_info("%s: %x current_path before changing\n", - __func__, current_path); - - current_path |= path; - usb_apply_path(current_path); -} - -void usb_switch_clr_path(enum usb_path_t path) -{ - pr_info("%s: %x current_path before changing\n", - __func__, current_path); - - current_path &= ~path; - usb_apply_path(current_path); -} - -int usb_switch_lock(void) -{ - return down_interruptible(&usb_switch_sem); -} - -int usb_switch_trylock(void) -{ - return down_trylock(&usb_switch_sem); -} - -void usb_switch_unlock(void) -{ - up(&usb_switch_sem); -} - -static int __init usb_switch_init(void) -{ - int ret; - - gpio_request(GPIO_USB_SEL1, "GPIO_USB_SEL1"); - gpio_request(GPIO_UART_SEL, "GPIO_UART_SEL"); - - gpio_export(GPIO_USB_SEL1, 1); - gpio_export(GPIO_UART_SEL, 1); - - BUG_ON(!sec_class); - sec_switch_dev = device_create(sec_class, NULL, 0, NULL, "switch"); - - BUG_ON(!sec_switch_dev); - gpio_export_link(sec_switch_dev, "GPIO_USB_SEL1", GPIO_USB_SEL1); - gpio_export_link(sec_switch_dev, "GPIO_UART_SEL", GPIO_UART_SEL); - - /*init_MUTEX(&usb_switch_sem);*/ - sema_init(&usb_switch_sem, 1); - - /* create sysfs group */ - ret = sysfs_create_group(&sec_switch_dev->kobj, &px_switch_group); - if (ret) { - pr_err("failed to create px switch attribute group\n"); - return ret; - } - - return 0; -} - -device_initcall(usb_switch_init); diff --git a/arch/arm/mach-exynos/p4-input.c b/arch/arm/mach-exynos/p4-input.c index 1420f41..e4d43c0 100644 --- a/arch/arm/mach-exynos/p4-input.c +++ b/arch/arm/mach-exynos/p4-input.c @@ -16,80 +16,6 @@ #include <plat/gpio-cfg.h> #include <plat/iic.h> -#if defined(CONFIG_RMI4_I2C) -#include <linux/rmi.h> -static int synaptics_tsp_pre_suspend(const void *pm_data) -{ - if (NULL == pm_data) - return -1; - printk(KERN_DEBUG "[TSP] %s\n", __func__); - - s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_SDA_18V, 0); - s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_SCL_18V, 0); - - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_INT, 0); - s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_RST, 0); - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_LDO_ON, 0); - - return 0; -} - -static int synaptics_tsp_post_resume(const void *pm_data) -{ - if (NULL == pm_data) - return -1; - printk(KERN_DEBUG "[TSP] %s\n", __func__); - - s3c_gpio_cfgpin(GPIO_TSP_SDA_18V, S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(GPIO_TSP_SDA_18V, S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(GPIO_TSP_SCL_18V, S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(GPIO_TSP_SCL_18V, S3C_GPIO_PULL_UP); - - s3c_gpio_cfgpin(GPIO_TSP_LDO_ON, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_LDO_ON, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_LDO_ON, 1); - s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_RST, 1); - s3c_gpio_setpull(GPIO_TSP_INT, S3C_GPIO_PULL_NONE); - s3c_gpio_cfgpin(GPIO_TSP_INT, S3C_GPIO_SFN(0xf)); - - return 0; -} - -static void synaptics_tsp_reset(void) -{ - printk(KERN_DEBUG "[TSP] %s\n", __func__); - s3c_gpio_cfgpin(GPIO_TSP_RST, S3C_GPIO_OUTPUT); - s3c_gpio_setpull(GPIO_TSP_RST, S3C_GPIO_PULL_NONE); - gpio_set_value(GPIO_TSP_RST, 0); - msleep(100); - gpio_set_value(GPIO_TSP_RST, 1); -} - -static struct rmi_device_platform_data synaptics_pdata = { - .driver_name = "rmi-generic", - .sensor_name = "s7301", - .attn_gpio = GPIO_TSP_INT, - .attn_polarity = RMI_ATTN_ACTIVE_LOW, - .axis_align = { }, - .pm_data = NULL, - .pre_suspend = synaptics_tsp_pre_suspend, - .post_resume = synaptics_tsp_post_resume, - .hw_reset = synaptics_tsp_reset, -}; -#endif /* CONFIG_RMI4_I2C */ - #if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301) #include <linux/synaptics_s7301.h> static bool have_tsp_ldo; @@ -171,29 +97,517 @@ static struct synaptics_platform_data synaptics_ts_pdata = { .hw_reset = synaptics_ts_reset, .register_cb = synaptics_ts_register_callback, }; -#endif /* CONFIG_TOUCHSCREEN_SYNAPTICS_S7301 */ -static struct i2c_board_info i2c_devs3[] __initdata = { +static struct i2c_board_info i2c_synaptics[] __initdata = { { -#if defined(CONFIG_RMI4_I2C) - I2C_BOARD_INFO(SYNAPTICS_RMI_NAME, - SYNAPTICS_RMI_ADDR), - .platform_data = &synaptics_pdata, -#endif /* CONFIG_RMI4_I2C */ -#if defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301) I2C_BOARD_INFO(SYNAPTICS_TS_NAME, SYNAPTICS_TS_ADDR), .platform_data = &synaptics_ts_pdata, + }, +}; #endif /* CONFIG_TOUCHSCREEN_SYNAPTICS_S7301 */ + +#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S) +#include <linux/i2c/mxt1664s.h> +static struct mxt_callbacks *mxt_callbacks; +static u32 hw_rev; + +/* Caution: Note10(p4note) has various H/W revision and each revision + * has different TSP tunning data. + * So If you add or change the tunning data, please refer the below + * simple description. + * + * H/W revision Project + * ~ 0.6 3G note10(N8010) final revision is 0.6 + * 0.7 ~ 0.8 Reserved + * 0.9 LTE model such as N8020 + */ + +static u8 inform_data_rev6[] = {0, + 7, 0, 48, 255, + 7, 1, 11, 255, + 47, 1, 35, 40, + 55, 0, 1, 0, + 55, 1, 25, 11, + 55, 2, 7, 3, + 56, 36, 0, 3, + 62, 1, 0, 1, + 62, 10, 5, 21, + 62, 12, 5, 21, + 62, 19, 130, 62, + 62, 20, 12, 20, +}; + +static u8 inform_data_rev5[] = {0, + 7, 0, 48, 255, + 7, 1, 11, 255, + 46, 2, 10, 24, + 46, 3, 16, 24, + 47, 1, 35, 40, + 56, 36, 0, 3, + 62, 1, 0, 1, + 62, 9, 16, 20, + 62, 11, 16, 20, + 62, 13, 16, 20, + 62, 13, 0, 21, + 62, 19, 128, 112, + 62, 20, 20, 30, +}; + +/* Added for the LTE model */ +static u8 inform_data_rev9[] = {0, + 7, 1, 11, 255, + 46, 3, 16, 24, + 47, 1, 35, 45, + 47, 9, 16, 24, + 55, 0, 1, 0, + 55, 1, 25, 11, + 55, 2, 7, 3, + 56, 3, 45, 40, + 56, 36, 0, 3, + 62, 3, 0, 23, + 62, 7, 90, 18, + 62, 8, 1, 8, + 62, 10, 0, 8, + 62, 12, 0, 8, + 62, 13, 1, 0, + 62, 19, 136, 100, + 62, 21, 35, 45, + 62, 25, 16, 24, + 62, 26, 16, 24, +}; + +static u8 inform_data[] = {0, + 7, 0, 48, 255, + 7, 1, 11, 255, + 8, 0, 160, 90, + 46, 3, 16, 24, + 47, 9, 16, 24, + 55, 1, 25, 11, + 55, 2, 7, 3, + 56, 36, 0, 3, + 62, 1, 0, 1, + 62, 8, 25, 40, + 62, 9, 15, 40, + 62, 10, 22, 35, + 62, 11, 15, 40, + 62, 12, 22, 35, + 62, 13, 15, 40, + 62, 19, 136, 80, + 62, 20, 15, 5, + 62, 21, 40, 45, + 62, 22, 24, 32, + 62, 25, 16, 24, + 62, 26, 16, 24, +}; + +void ts_charger_infom(bool en) +{ + if (mxt_callbacks && mxt_callbacks->inform_charger) + mxt_callbacks->inform_charger(mxt_callbacks, en); +} + +static u8 *ts_register_callback(struct mxt_callbacks *cb) +{ + mxt_callbacks = cb; + + inform_data[0] = sizeof(inform_data); + inform_data_rev5[0] = sizeof(inform_data_rev5); + inform_data_rev6[0] = sizeof(inform_data_rev6); + inform_data_rev9[0] = sizeof(inform_data_rev9); + + if (0x5 == hw_rev) + return inform_data_rev5; + else if (0x6 == hw_rev) + return inform_data_rev6; + else if (0x9 <= hw_rev) + return inform_data_rev9; + else + return inform_data; +} + +static int ts_power_on(void) +{ + int gpio = 0; + + gpio = GPIO_TSP_SDA_18V; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 1); + + gpio = GPIO_TSP_SCL_18V; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 1); + + gpio = GPIO_TSP_LDO_ON; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 1); + + gpio = GPIO_TSP_LDO_ON1; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 1); + + msleep(20); + + gpio = GPIO_TSP_LDO_ON2; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 1); + + msleep(20); + gpio = GPIO_TSP_RST; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 1); + + /* touch interrupt pin */ + gpio = GPIO_TSP_INT; + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + +#if 0 + msleep(MXT_1664S_HW_RESET_TIME); +#endif + + gpio = GPIO_TSP_SDA_18V; + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0x3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + + gpio = GPIO_TSP_SCL_18V; + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0x3)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); + + printk(KERN_ERR "mxt_power_on is finished\n"); + + return 0; +} + +static int ts_power_off(void) +{ + int gpio = 0; + + gpio = GPIO_TSP_SDA_18V; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 0); + + gpio = GPIO_TSP_SCL_18V; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 0); + + /* touch xvdd en pin */ + gpio = GPIO_TSP_LDO_ON2; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 0); + + gpio = GPIO_TSP_LDO_ON1; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 0); + + gpio = GPIO_TSP_LDO_ON; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 0); + + /* touch interrupt pin */ + gpio = GPIO_TSP_INT; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN); + + /* touch reset pin */ + gpio = GPIO_TSP_RST; + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + gpio_set_value(gpio, 0); + + printk(KERN_ERR "mxt_power_off is finished\n"); + + return 0; +} + +static int ts_power_reset(void) +{ + ts_power_off(); + msleep(100); + ts_power_on(); + msleep(300); + return 0; +} + +/* + Configuration for MXT1664-S +*/ +#define MXT1664S_CONFIG_DATE "N80XX_ATM_0703" +#define MXT1664S_MAX_MT_FINGERS 10 +#define MXT1664S_BLEN_BATT 112 +#define MXT1664S_CHRGTIME_BATT 180 +#define MXT1664S_THRESHOLD_BATT 65 +#define P4_NOTE_X_NUM 27 +#define P4_NOTE_Y_NUM 42 + +static u8 t7_config_s[] = { GEN_POWERCONFIG_T7, + 255, 255, 150, 3 +}; + +static u8 t8_config_s[] = { GEN_ACQUISITIONCONFIG_T8, + MXT1664S_CHRGTIME_BATT, 0, 5, 10, 0, 0, 255, 255, 0, 0 +}; + +static u8 t9_config_s[] = { TOUCH_MULTITOUCHSCREEN_T9, + 0x83, 0, 0, P4_NOTE_X_NUM, P4_NOTE_Y_NUM, + 0, MXT1664S_BLEN_BATT, MXT1664S_THRESHOLD_BATT, 1, 1, + 10, 15, 1, 65, MXT1664S_MAX_MT_FINGERS, 20, 30, 20, 255, 15, + 255, 15, 5, 246, 5, 5, 0, 0, 0, 0, + 32, 20, 51, 53, 0, 1 +}; + +static u8 t15_config_s[] = { TOUCH_KEYARRAY_T15, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 +}; + +static u8 t18_config_s[] = { SPT_COMCONFIG_T18, + 0, 0 +}; + +static u8 t24_config_s[] = { + PROCI_ONETOUCHGESTUREPROCESSOR_T24, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t25_config_s[] = { + SPT_SELFTEST_T25, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 200 +}; + +static u8 t27_config_s[] = { + PROCI_TWOTOUCHGESTUREPROCESSOR_T27, + 0, 0, 0, 0, 0, 0, 0 +}; + +static u8 t40_config_s[] = { PROCI_GRIPSUPPRESSION_T40, + 0x11, 3, 55, 0, 0 +}; + +static u8 t42_config_s[] = { PROCI_TOUCHSUPPRESSION_T42, + 0, 42, 50, 50, 127, 0, 0, 0, 5, 5 +}; + +static u8 t43_config_s[] = { SPT_DIGITIZER_T43, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 +}; + +static u8 t46_config_s[] = { SPT_CTECONFIG_T46, + 4, 0, 10, 16, 0, 0, 1, 0, 0, 0, + 15 +}; + +static u8 t47_config_s[] = { PROCI_STYLUS_T47, + 73, 40, 60, 15, 10, 40, 0, 120, 1, 16, + 0, 0, 15 +}; + +static u8 t55_config_s[] = {ADAPTIVE_T55, + 1, 25, 7, 10, 20, 1, 0 +}; + +static u8 t56_config_s[] = {PROCI_SHIELDLESS_T56, + 3, 0, 1, 55, 25, 25, 25, 25, 25, 25, + 24, 24, 24, 23, 23, 23, 22, 22, 22, 21, + 21, 20, 20, 20, 19, 19, 18, 18, 18, 17, + 17, 0, 0, 0, 0, 0, 0, 128, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 +}; + +static u8 t57_config_s[] = {PROCI_EXTRATOUCHSCREENDATA_T57, + 0xe3, 25, 0 +}; + +static u8 t61_config_s[] = {SPT_TIMER_T61, + 0, 0, 0, 0, 0 +}; + +static u8 t62_config_s[] = {PROCG_NOISESUPPRESSION_T62, + 3, 0, 0, 23, 10, 0, 0, 0, 25, 0, + 5, 0, 5, 0, 2, 0, 5, 5, 10, 130, + 12, 40, 32, 20, 63, 16, 16, 4, 100, 0, + 0, 0, 0, 0, 60, 40, 2, 15, 1, 66, + 10, 20, 30, 20, 15, 5, 5, 0, 0, 0, + 0, 60, 15, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0 +}; + +static u8 end_config_s[] = { RESERVED_T255 }; + +static const u8 *MXT1644S_config[] = { + t7_config_s, + t8_config_s, + t9_config_s, + t15_config_s, + t18_config_s, + t24_config_s, + t25_config_s, + t27_config_s, + t40_config_s, + t42_config_s, + t43_config_s, + t46_config_s, + t47_config_s, + t55_config_s, + t56_config_s, + t57_config_s, + t61_config_s, + t62_config_s, + end_config_s, +}; + +static struct mxt_platform_data mxt1664s_pdata = { + .max_finger_touches = MXT1664S_MAX_MT_FINGERS, + .gpio_read_done = GPIO_TSP_INT, + .min_x = 0, + .max_x = 4095, + .min_y = 0, + .max_y = 4095, + .min_z = 0, + .max_z = 255, + .min_w = 0, + .max_w = 255, + .config = MXT1644S_config, + .power_on = ts_power_on, + .power_off = ts_power_off, + .power_reset = ts_power_reset, + .boot_address = 0x26, + .register_cb = ts_register_callback, + .config_version = MXT1664S_CONFIG_DATE, +}; + +static struct i2c_board_info i2c_mxt1664s[] __initdata = { + { + I2C_BOARD_INFO(MXT_DEV_NAME, 0x4A), + .platform_data = &mxt1664s_pdata, }, }; +#endif + +static void switch_config(u32 rev) +{ + int i = 0; + + /* the number of the array should be added by 1 */ + if (0x5 == rev) { + t8_config_s[1] = 150; + + t9_config_s[9] = 1; + t9_config_s[11] = 0; + t9_config_s[12] = 5; + t9_config_s[16] = 10; + t9_config_s[17] = 20; + t9_config_s[32] = 15; + + t47_config_s[2] = 35; + t47_config_s[4] = 10; + t47_config_s[5] = 2; + t47_config_s[6] = 30; + t47_config_s[10] = 24; + + t55_config_s[1] = 0; + + for (i = 5; i < 32; i++) + t56_config_s[i] += 2; + + t62_config_s[9] = 20; + t62_config_s[10] = 16; + t62_config_s[11] = 0; + t62_config_s[12] = 16; + t62_config_s[13] = 0; + t62_config_s[14] = 16; + t62_config_s[20] = 128; + t62_config_s[21] = 20; + t62_config_s[22] = 10; + t62_config_s[23] = 40; + t62_config_s[24] = 10; + t62_config_s[25] = 64; + t62_config_s[26] = 24; + t62_config_s[27] = 24; + t62_config_s[35] = 64; + t62_config_s[36] = 45; + } else if (0x9 <= rev) { + u8 tmp = 0; + t7_config_s[1] = 48; + t7_config_s[2] = 11; + + t8_config_s[1] = 1; + + t9_config_s[8] = 55; + t9_config_s[27] = 64; + + t40_config_s[4] = 2; + t40_config_s[5] = 2; + + t46_config_s[11] = 11; + + t47_config_s[2] = 35; + + t56_config_s[4] = 45; + tmp = 22; + for (i = 5; i < 21; i++) { + if (1 == i % 4) + tmp--; + t56_config_s[i] = tmp; + } + + for (i = 21; i < 28; i++) + t56_config_s[i] = 17; + + for (i = 28; i < 31; i++) + t56_config_s[i] = 16; + + t56_config_s[39] = 1; + + t62_config_s[1] = 125; + t62_config_s[2] = 1; + t62_config_s[4] = 0; + t62_config_s[8] = 90; + t62_config_s[9] = 1; + t62_config_s[11] = 0; + t62_config_s[13] = 0; + t62_config_s[14] = 1; + t62_config_s[20] = 136; + t62_config_s[22] = 35; + t62_config_s[35] = 80; + t62_config_s[36] = 50; + t62_config_s[38] = 5; + t62_config_s[42] = 30; + t62_config_s[43] = 40; + t62_config_s[44] = 10; + t62_config_s[45] = 0; + t62_config_s[48] = 30; + t62_config_s[49] = 30; + t62_config_s[53] = 20; + } +} void __init p4_tsp_init(u32 system_rev) { - int gpio; + int gpio = 0, irq = 0; + hw_rev = system_rev; printk(KERN_DEBUG "[TSP] %s rev : %u\n", - __func__, system_rev); + __func__, hw_rev); + + printk(KERN_DEBUG "[TSP] TSP IC : %s\n", + (5 <= hw_rev) ? "Atmel" : "Synaptics"); gpio = GPIO_TSP_RST; gpio_request(gpio, "TSP_RST"); @@ -205,26 +619,45 @@ void __init p4_tsp_init(u32 system_rev) gpio_direction_output(gpio, 1); gpio_export(gpio, 0); + if (5 <= hw_rev) { + gpio = GPIO_TSP_LDO_ON1; + gpio_request(gpio, "TSP_LDO_ON1"); + gpio_direction_output(gpio, 1); + gpio_export(gpio, 0); + + gpio = GPIO_TSP_LDO_ON2; + gpio_request(gpio, "TSP_LDO_ON2"); + gpio_direction_output(gpio, 1); + gpio_export(gpio, 0); + + switch_config(hw_rev); + } else if (1 <= hw_rev) + have_tsp_ldo = true; + gpio = GPIO_TSP_INT; gpio_request(gpio, "TSP_INT"); - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); s5p_register_gpio_interrupt(gpio); - i2c_devs3[0].irq = gpio_to_irq(gpio); - if (1 <= system_rev) -#if defined(CONFIG_RMI4_I2C) - synaptics_pdata.pm_data = - (char *)synaptics_pdata.sensor_name; -#else - have_tsp_ldo = true; -#endif + irq = gpio_to_irq(gpio); #ifdef CONFIG_S3C_DEV_I2C3 s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, i2c_devs3, - ARRAY_SIZE(i2c_devs3)); + +#if defined(CONFIG_TOUCHSCREEN_ATMEL_MXT1664S) && \ + defined(CONFIG_TOUCHSCREEN_SYNAPTICS_S7301) + if (5 <= system_rev) { + i2c_mxt1664s[0].irq = irq; + i2c_register_board_info(3, i2c_mxt1664s, + ARRAY_SIZE(i2c_mxt1664s)); + } else { + i2c_synaptics[0].irq = irq; + i2c_register_board_info(3, i2c_synaptics, + ARRAY_SIZE(i2c_synaptics)); + } #endif +#endif /* CONFIG_S3C_DEV_I2C3 */ + } #if defined(CONFIG_EPEN_WACOM_G5SP) @@ -243,6 +676,12 @@ static struct wacom_g5_platform_data wacom_platform_data = { .y_invert = 0, .xy_switch = 0, .gpio_pendct = GPIO_PEN_PDCT_18V, +#ifdef WACOM_PEN_DETECT + .gpio_pen_insert = GPIO_S_PEN_IRQ, +#endif +#ifdef WACOM_HAVE_FWE_PIN + .gpio_fwe = GPIO_PEN_FWE0, +#endif .init_platform_hw = wacom_init_hw, .suspend_platform_hw = wacom_suspend_hw, .resume_platform_hw = wacom_resume_hw, @@ -274,7 +713,7 @@ static int wacom_init_hw(void) } s3c_gpio_cfgpin(GPIO_PEN_LDO_EN, S3C_GPIO_SFN(0x1)); s3c_gpio_setpull(GPIO_PEN_LDO_EN, S3C_GPIO_PULL_NONE); - gpio_direction_output(GPIO_PEN_LDO_EN, 1); + gpio_direction_output(GPIO_PEN_LDO_EN, 0); ret = gpio_request(GPIO_PEN_PDCT_18V, "PEN_PDCT"); if (ret) { @@ -293,6 +732,23 @@ static int wacom_init_hw(void) s3c_gpio_setpull(GPIO_PEN_IRQ_18V, S3C_GPIO_PULL_DOWN); s5p_register_gpio_interrupt(GPIO_PEN_IRQ_18V); i2c_devs6[0].irq = gpio_to_irq(GPIO_PEN_IRQ_18V); + +#ifdef WACOM_PEN_DETECT + s3c_gpio_cfgpin(GPIO_S_PEN_IRQ, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_S_PEN_IRQ, S3C_GPIO_PULL_UP); +#endif + +#ifdef WACOM_HAVE_FWE_PIN + ret = gpio_request(GPIO_PEN_FWE0, "GPIO_PEN_FWE0"); + if (ret) { + printk(KERN_ERR "[E-PEN] faile to request gpio(GPIO_PEN_FWE0)\n"); + return ret; + } + s3c_gpio_cfgpin(GPIO_PEN_FWE0, S3C_GPIO_SFN(0x1)); + s3c_gpio_setpull(GPIO_PEN_FWE0, S3C_GPIO_PULL_NONE); + gpio_direction_output(GPIO_PEN_FWE0, 0); +#endif + return 0; } diff --git a/arch/arm/mach-exynos/p4note-gpio.c b/arch/arm/mach-exynos/p4note-gpio.c index b28cc00..5596b7a 100644 --- a/arch/arm/mach-exynos/p4note-gpio.c +++ b/arch/arm/mach-exynos/p4note-gpio.c @@ -56,6 +56,13 @@ static struct gpio_init_data p4note_init_gpios[] = { {EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */ +#if defined(CONFIG_QC_MODEM) + {EXYNOS4_GPL2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* BUCK2_SEL */ + {EXYNOS4_GPL2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* BUCK3_SEL */ +#endif + {EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ADC_IC_INT */ {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -78,17 +85,23 @@ static struct gpio_init_data p4note_init_gpios[] = { S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TA_INT */ {EXYNOS4_GPX1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* OVP_FLAG */ -#if defined(CONFIG_SEC_MODEM) +#if defined(CONFIG_SEC_MODEM) || defined(CONFIG_QC_MODEM) {EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SIM_DETECT */ #endif +#if !defined(CONFIG_QC_MODEM) {EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif {EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */ +#if defined(CONFIG_QC_MODEM) + {EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif {EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */ {EXYNOS4_GPX2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -149,6 +162,10 @@ static struct gpio_init_data p4note_init_gpios[] = { S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* CAM_MCLK */ {EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* VTCAM_MCLK */ +#if defined(CONFIG_QC_MODEM) + {EXYNOS4212_GPM3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV1}, /* AP2MDM_PMIC_RESET_N */ +#endif }; /* @@ -159,10 +176,17 @@ static unsigned int p4note_sleep_gpio_table[][3] = { {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, +#if !defined(CONFIG_QC_MODEM) {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, +#else + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_PEN_FWE0 */ + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -192,17 +216,25 @@ static unsigned int p4note_sleep_gpio_table[][3] = { {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if !defined(CONFIG_QC_MODEM) {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_CLK(NC) */ - {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_EN */ {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_SYNC(NC) */ {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_IN(NC) */ {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* REC_PCM_OUT(NC) */ +#else + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WCN_PRIORITY */ + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_EN */ + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_HOST_READY */ + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*AP2MDM_ERR_FATAL*/ + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM_LTE_FRAME_SYNC */ +#endif #if defined(CONFIG_SEC_MODEM_M0_TD) {EXYNOS4_GPC1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, #else {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_PDCT */ #endif - {EXYNOS4_GPC1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* PEN_LDO_EN */ + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PEN_LDO_EN */ {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_IRQ_1.8V */ {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_SDA_1.8V */ @@ -286,6 +318,8 @@ static unsigned int p4note_sleep_gpio_table[][3] = { #if defined(CONFIG_SEC_MODEM) {EXYNOS4_GPL0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* ACTIVE_STATE_HSIC */ +#elif defined(CONFIG_QC_MODEM) + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM2AP_HSIC_READY */ #else {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif @@ -293,29 +327,37 @@ static unsigned int p4note_sleep_gpio_table[][3] = { {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PS_ALS_SDA_1.8V */ {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC(IRDA_CONTROL) */ {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */ -/* {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -/* {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, */ #if defined(CONFIG_SEC_MODEM) {EXYNOS4_GPL1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */ +#elif defined(CONFIG_QC_MODEM) + {EXYNOS4_GPL1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_STATUS */ #else {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif {EXYNOS4_GPL1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* 3M_nRST */ -/* {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, */ {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if !defined(CONFIG_QC_MODEM) {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */ + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */ +#endif {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_C1VZW) +#if defined(CONFIG_MACH_C1) || defined(CONFIG_MACH_M3) /* GLP2(4) CMC_CPU_RESET, hold high */ {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* NC */ #else {EXYNOS4_GPL2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* MOTOR_EN */ #endif +#if !defined(CONFIG_QC_MODEM) {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CP_ON(NC) */ +#else + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_PON_RESET_N */ +#endif {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* UART_SEL */ @@ -382,7 +424,11 @@ static unsigned int p4note_sleep_gpio_table[][3] = { {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ /* Exynos4212 specific gpio */ +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* UART_SEL2 */ +#else {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_PCLK */ +#endif {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_VSYNC */ {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_HSYNC */ {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_D */ @@ -422,17 +468,22 @@ static unsigned int p4note_sleep_gpio_table[][3] = { {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* SUSPEND_REQUEST_HSIC(NC) */ + /* SUSPEND_REQUEST_HSIC for 3G, AP2MDM_WAKEUP for LTE, NC */ + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */ {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */ {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */ #if defined(CONFIG_SEC_MODEM) {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* RESET_REQ_N */ + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_DOWN}, /* AP_DUMP_INT */ +#elif defined(CONFIG_QC_MODEM) + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP2MDM_SOFT_RESET */ + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_PMIC_RESET_N */ #else {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif - {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_DUMP_INT(NC) */ {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WLAN_EN */ {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CAM_MOVIE_EN */ {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* CAM_FLASH_EN */ @@ -512,6 +563,15 @@ static unsigned int p4note_sleep_gpio_table_rev09[][3] = { {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TSP_LDO_ON */ }; +/* + * P4NOTE Rev0.9 GPIO Sleep Table + */ +static unsigned int p4notelte_sleep_gpio_table_rev01[][3] = { +#if defined(CONFIG_QC_MODEM) + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* UART_SEL2 */ +#endif +}; + struct p4note_sleep_table { unsigned int (*ptr)[3]; int size; @@ -526,8 +586,18 @@ struct p4note_sleep_table { .size = 0} \ static struct p4note_sleep_table p4note_sleep_table[] = { - GPIO_TABLE(p4note_sleep_gpio_table), /* Rev0.8(0x0) */ - GPIO_TABLE(p4note_sleep_gpio_table_rev09), /* Rev0.9(0x1) */ + GPIO_TABLE(p4note_sleep_gpio_table), /* Rev0.8(0x0) */ + GPIO_TABLE(p4note_sleep_gpio_table_rev09), /* Rev0.9(0x1) */ + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE(p4notelte_sleep_gpio_table_rev01), /* lte Rev0.1(0xA) */ + GPIO_TABLE_NULL, }; #endif /* CONFIG_MIDAS_COMMON */ diff --git a/arch/arm/mach-exynos/p4note-jack.c b/arch/arm/mach-exynos/p4note-jack.c index 2a4d0df..7c85b27 100644 --- a/arch/arm/mach-exynos/p4note-jack.c +++ b/arch/arm/mach-exynos/p4note-jack.c @@ -24,6 +24,55 @@ static void sec_set_jack_micbias(bool on) gpio_set_value(GPIO_EAR_MIC_BIAS_EN, on); } +#ifdef CONFIG_TARGET_LOCALE_KOR +static struct sec_jack_zone sec_jack_zones[] = { + { + /* adc == 0, unstable zone, default to 3pole if it stays + * in this range for 300ms (15ms delays, 20 samples) + */ + .adc_high = 0, + .delay_ms = 10, + .check_count = 10, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 0 < adc <= 1200, unstable zone, default to 3pole if it stays + * in this range for 300ms (15ms delays, 20 samples) + */ + .adc_high = 1200, + .delay_ms = 10, + .check_count = 10, + .jack_type = SEC_HEADSET_3POLE, + }, + { + /* 1200 < adc <= 2600, unstable zone, default to 4pole if it + * stays in this range for 100ms (10ms delays, 80 samples) + */ + .adc_high = 2600, + .delay_ms = 10, + .check_count = 10, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* 2600 < adc <= 3800, 4 pole zone, default to 4pole if it + * stays in this range for 100ms (10ms delays, 10 samples) + */ + .adc_high = 3800, + .delay_ms = 10, + .check_count = 5, + .jack_type = SEC_HEADSET_4POLE, + }, + { + /* adc > 3800, unstable zone, default to 3pole if it stays + * in this range for two seconds (10ms delays, 200 samples) + */ + .adc_high = 0x7fffffff, + .delay_ms = 10, + .check_count = 200, + .jack_type = SEC_HEADSET_3POLE, + }, +}; +#else static struct sec_jack_zone sec_jack_zones[] = { { /* adc == 0, unstable zone, default to 3pole if it stays @@ -71,6 +120,7 @@ static struct sec_jack_zone sec_jack_zones[] = { .jack_type = SEC_HEADSET_3POLE, }, }; +#endif /* To support 3-buttons earjack */ static struct sec_jack_buttons_zone sec_jack_buttons_zones[] = { diff --git a/arch/arm/mach-exynos/p4note-power.c b/arch/arm/mach-exynos/p4note-power.c index 14769a6..5b78e79 100644 --- a/arch/arm/mach-exynos/p4note-power.c +++ b/arch/arm/mach-exynos/p4note-power.c @@ -299,7 +299,7 @@ static struct regulator_consumer_supply ldo8_supply[] = { }; static struct regulator_consumer_supply ldo9_supply[] = { - REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL), + REGULATOR_SUPPLY("vled_ic_1.9v", NULL), }; static struct regulator_consumer_supply ldo10_supply[] = { @@ -407,8 +407,13 @@ REGULATOR_INIT(ldo5, "VCC_1.8V_IO", 1800000, 1800000, 0, REGULATOR_CHANGE_STATUS, 1); REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1, REGULATOR_CHANGE_STATUS, 0); -REGULATOR_INIT(ldo9, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0, +#if defined(CONFIG_IR_REMOCON_MC96) +REGULATOR_INIT(ldo9, "VLED_IC_1.9V", 1950000, 1950000, 1, REGULATOR_CHANGE_STATUS, 1); +#else +REGULATOR_INIT(ldo9, "VLED_IC_1.9V", 1950000, 1950000, 0, + REGULATOR_CHANGE_STATUS, 1); +#endif REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1, REGULATOR_CHANGE_STATUS, 0); REGULATOR_INIT(ldo11, "VABB1_1.9V", 1950000, 1950000, 1, @@ -1099,13 +1104,8 @@ struct s5m_platform_data exynos4_s5m8767_info = { void midas_power_init(void) { -#ifdef CONFIG_MACH_S2PLUS - ldo8_init_data.constraints.always_on = 1; - ldo13_init_data.constraints.always_on = 1; -#else ldo8_init_data.constraints.always_on = 1; ldo10_init_data.constraints.always_on = 1; -#endif } /* End of S5M8767 */ diff --git a/arch/arm/mach-exynos/p8lte-gpio.c b/arch/arm/mach-exynos/p8lte-gpio.c new file mode 100644 index 0000000..ab4dbd4 --- /dev/null +++ b/arch/arm/mach-exynos/p8lte-gpio.c @@ -0,0 +1,465 @@ +#include <linux/gpio.h> +#include <linux/serial_core.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-serial.h> +#include <mach/gpio.h> +#include <mach/gpio-p8lte.h> + +#ifdef CONFIG_MACH_P8LTE +int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config); +int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config); +#endif + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +static struct gpio_init_data p8lte_init_gpios[] = { + { + .num = EXYNOS4_GPB(5), /* WLAN_nRST */ + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S5P_GPIO_DRVSTR_LV1, + }, { + .num = EXYNOS4_GPD0(2), /* MSENSOR_MHL_SDA_2.8V */ + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S5P_GPIO_DRVSTR_LV1, + }, { + .num = EXYNOS4_GPD0(3), /* MSENSOR_MHL_SCL_2.8V */ + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S5P_GPIO_DRVSTR_LV1, + }, { + .num = EXYNOS4_GPD1(2), /* SENSE_SDA_2.8V */ + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S5P_GPIO_DRVSTR_LV1, + }, { + .num = EXYNOS4_GPD1(3), /* SENSE_SCL_2.8V */ + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S5P_GPIO_DRVSTR_LV1, + }, { + .num = EXYNOS4_GPK2(2), /* PS_ALS_SDA_2.8V */ + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S5P_GPIO_DRVSTR_LV1, + }, { + .num = EXYNOS4_GPK3(2), /* PS_ALS_SCL_2.8V */ + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S5P_GPIO_DRVSTR_LV1, + }, { + /*.num = EXYNOS4_GPJ1(3),*/ /* GPIO_CAM_MCLK */ + /* GPIO_CAM_MCLK */ /*KAMALNATH - need to confirm*/ + .num = EXYNOS4210_GPJ1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S5P_GPIO_DRVSTR_LV4, + }, + /* BT UART */ + {GPIO_BT_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP}, + {GPIO_BT_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, + {GPIO_BT_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, + {GPIO_BT_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, + /* GPS UART */ + {GPIO_GPS_RXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_UP}, + {GPIO_GPS_TXD, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, + {GPIO_GPS_CTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, + {GPIO_GPS_RTS, S3C_GPIO_SFN(2), 2, S3C_GPIO_PULL_NONE}, + {GPIO_GPS_nRST, S3C_GPIO_OUTPUT, 1, S3C_GPIO_PULL_UP}, + {GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE}, + + /* UART switch: configure as output */ + {GPIO_UART_SEL1, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_UART_SEL2, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE}, + + /* USB switch: configure as output */ + {GPIO_USB_SEL1, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_USB_SEL2, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_USB_SEL3, S3C_GPIO_OUTPUT, 2, S3C_GPIO_PULL_NONE}, + + /* JIG On */ + {GPIO_IF_CON_SENSE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + + /* 30PIN CONNECTOR */ + {GPIO_DOCK_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + + /* MIC */ + {GPIO_EAR_MIC_BIAS_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE}, + + /* LTE PWR */ + {GPIO_220_PMIC_PWRON, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_DOWN}, + {GPIO_LTE_PS_HOLD_OFF, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_DOWN}, + {GPIO_CMC_RST, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_DOWN}, + + /*** GPX ***/ + {GPIO_GYRO_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_REMOTE_SENSE_IRQ, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_SIM_DETECT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_ACCESSORY_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_MSENSE_INT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_FUEL_ALERT, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_VIA_PS_HOLD_OFF, S3C_GPIO_OUTPUT, 1, S3C_GPIO_PULL_NONE}, + /* {GPIO_BT_HOST_WAKE, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, */ + {GPIO_DET_35, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_USB_OTG_EN, S3C_GPIO_OUTPUT, 0, S3C_GPIO_PULL_NONE}, + /* T_FLASH_DETECT */ + {EXYNOS4_GPX3(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + /* CP_AP_DPRAM_INT */ + {EXYNOS4_GPX3(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + {GPIO_HDMI_HPD, S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_NONE}, + + /* NC */ + {EXYNOS4_GPA1(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPA1(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPB(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + +/* {EXYNOS4_GPE0(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN},*/ + {EXYNOS4210_GPE0(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + + + {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY1(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY1(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY2(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(1), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(2), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(3), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(4), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY2(5), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY6(0), S3C_GPIO_INPUT, 2, S3C_GPIO_PULL_DOWN}, +}; + +void p8lte_config_gpio_table(void) +{ + u32 i, gpio; + + printk(KERN_DEBUG "%s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(p8lte_init_gpios); i++) { + gpio = p8lte_init_gpios[i].num; + if (gpio < EXYNOS4_GPIO_END) { + s3c_gpio_cfgpin(gpio, p8lte_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, p8lte_init_gpios[i].pud); + + if (p8lte_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, p8lte_init_gpios[i].val); + + s5p_gpio_set_drvstr(gpio, p8lte_init_gpios[i].drv); + } + } +} + +/* this table only for p8lte board */ +static unsigned int p8lte_sleep_gpio_table[][3] = { + { EXYNOS4_GPA0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA0(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPA1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPB(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + { EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPC1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /*{ EXYNOS4_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},*/ + { EXYNOS4210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { EXYNOS4210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + { EXYNOS4210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + + { EXYNOS4210_GPE2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + { EXYNOS4210_GPE2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NC */ + + { EXYNOS4210_GPE3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { EXYNOS4210_GPE4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPE4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + { EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + { EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + { EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { EXYNOS4210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + { EXYNOS4210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4210_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4210_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPK0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* WLAN_EN2 */ + { EXYNOS4_GPK1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { EXYNOS4_GPK2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + { EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + { EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + { EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + { EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, + + { EXYNOS4_GPL0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* ACCESSORY_EN */ + { EXYNOS4_GPL1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL1(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPL2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPL2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* UART_SEL1 */ + { EXYNOS4_GPY0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + { EXYNOS4_GPY2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + /* MHL_SDA_1.8V */ + { EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* V_ACCESSORY_5V CHECK */ + { EXYNOS4_GPY3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* MHL_SCL_1.8V */ + { EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* PDA_ACTIVE2 */ + { EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* PDA_ACTIVE */ + { EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* USB_SEL3 */ + { EXYNOS4_GPY4(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* USB_SEL2 */ + { EXYNOS4_GPY4(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* UART_SEL0 */ + { EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /* HW_REV0 */ + { EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* HW_REV1 */ + { EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* HW_REV2 */ + { EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* HW_REV3 */ + { EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* GPS_nRST */ + { EXYNOS4_GPY5(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* GPS_PWR_EN */ + { EXYNOS4_GPY5(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY5(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPY6(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY6(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY6(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + /* USB_SEL1 */ + { EXYNOS4_GPY6(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPY6(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TA_EN */ + { EXYNOS4_GPY6(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { EXYNOS4_GPZ(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPZ(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPZ(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPZ(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + { EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +}; + +static void config_sleep_gpio_table(int array_size, + unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +void p8lte_config_sleep_gpio_table(void) +{ + config_sleep_gpio_table(ARRAY_SIZE(p8lte_sleep_gpio_table), + p8lte_sleep_gpio_table); +} diff --git a/arch/arm/mach-exynos/pm-exynos4.c b/arch/arm/mach-exynos/pm-exynos4.c index e24e519..6a35e7a 100644 --- a/arch/arm/mach-exynos/pm-exynos4.c +++ b/arch/arm/mach-exynos/pm-exynos4.c @@ -334,8 +334,6 @@ void exynos4_cpu_suspend(void) outer_flush_all(); - /* Disable the full line of zero */ - disable_cache_foz(); #ifdef CONFIG_ARM_TRUSTZONE exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); #else @@ -378,12 +376,31 @@ static void exynos4_cpu_prepare(void) /* Before enter central sequence mode, clock src register have to set */ +#ifdef CONFIG_CACHE_L2X0 + /* Disable the full line of zero */ + disable_cache_foz(); +#endif + s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); if (soc_is_exynos4210()) s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc)); } +static unsigned int exynos4_pm_check_eint_pend(void) +{ + int i; + u32 wakeup_int_pend, pending_eint = 0; + + for (i = 0; i < 4; i++) { + wakeup_int_pend = + (__raw_readl(S5P_EINT_PEND(i)) & 0xff) << (i * 8); + pending_eint |= wakeup_int_pend & ~s3c_irqwake_eintmask; + } + + return pending_eint; +} + static int exynos4_pm_add(struct sys_device *sysdev) { pm_cpu_prep = exynos4_cpu_prepare; @@ -394,6 +411,9 @@ static int exynos4_pm_add(struct sys_device *sysdev) pm_finish = exynos4_pm_finish; #endif + if (soc_is_exynos4210()) + pm_check_eint_pend = exynos4_pm_check_eint_pend; + return 0; } @@ -540,10 +560,10 @@ static void exynos4_pm_resume(void) CHECK_POINT; if ((__raw_readl(S5P_WAKEUP_STAT) == 0) && soc_is_exynos4412()) { - __raw_writel(0, S5P_EINT_PEND(0)); - __raw_writel(0, S5P_EINT_PEND(1)); - __raw_writel(0, S5P_EINT_PEND(2)); - __raw_writel(0, S5P_EINT_PEND(3)); + __raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0)); + __raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1)); + __raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2)); + __raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3)); __raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2)); @@ -582,8 +602,6 @@ static void exynos4_pm_resume(void) /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif - /* Enable the full line of zero */ - enable_cache_foz(); #endif CHECK_POINT; @@ -592,6 +610,11 @@ early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); +#ifdef CONFIG_CACHE_L2X0 + /* Enable the full line of zero */ + enable_cache_foz(); +#endif + CHECK_POINT; /* Clear Check mode */ diff --git a/arch/arm/mach-exynos/pm-exynos5.c b/arch/arm/mach-exynos/pm-exynos5.c deleted file mode 100644 index 933ee08..0000000 --- a/arch/arm/mach-exynos/pm-exynos5.c +++ /dev/null @@ -1,466 +0,0 @@ -/* linux/arch/arm/mach-exynos/pm-exynos5.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS5 - Power Management support - * - * Based on arch/arm/mach-s3c2410/pm.c - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/init.h> -#include <linux/suspend.h> -#include <linux/syscore_ops.h> -#include <linux/io.h> -#include <linux/delay.h> - -#include <asm/cacheflush.h> - -#include <plat/cpu.h> -#include <plat/pm.h> -#include <plat/bts.h> - -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu5.h> -#include <mach/pm-core.h> -#include <mach/pmu.h> -#include <mach/smc.h> - -#include <mach/map-exynos5.h> - -void (*exynos5_sleep_gpio_table_set)(void); - -#ifdef CONFIG_ARM_TRUSTZONE -#define REG_INFORM0 (S5P_VA_SYSRAM_NS + 0x8) -#define REG_INFORM1 (S5P_VA_SYSRAM_NS + 0xC) -#else -#define REG_INFORM0 (EXYNOS5_INFORM0) -#define REG_INFORM1 (EXYNOS5_INFORM1) -#endif - -static struct sleep_save exynos5_set_clksrc[] = { - { .reg = EXYNOS5_CLKSRC_MASK_TOP , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_GSCL , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_DISP1_0 , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_MAUDIO , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_FSYS , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_PERIC0 , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_PERIC1 , .val = 0xffffffff, }, - { .reg = EXYNOS5_CLKSRC_MASK_ISP , .val = 0xffffffff, }, -}; - -static struct sleep_save exynos5_core_save[] = { - /* GIC side */ - SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x008), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x000), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x004), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x100), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x104), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x108), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x10C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x110), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x300), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x304), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x308), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x30C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x310), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x400), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x404), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x408), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x410), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x414), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x418), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x420), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x424), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x428), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x430), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x434), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x438), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x440), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x444), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x448), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x450), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x454), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x458), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x460), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x464), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x468), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x46C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x470), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x474), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x478), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x47C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x480), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x484), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x488), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x48C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x490), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x494), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x498), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x49C), - - SAVE_ITEM(S5P_VA_GIC_DIST + 0x800), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x804), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x808), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x810), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x814), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x818), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x820), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x824), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x828), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x830), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x834), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x838), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x840), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x844), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x848), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x850), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x854), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x858), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x860), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x864), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x868), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x86C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x870), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x874), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x878), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x87C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x880), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x884), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x888), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x88C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x890), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x894), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x898), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x89C), - - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC18), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC1C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24), - - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060), - SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070), - - SAVE_ITEM(S3C_VA_SYS + 0x234), -}; - -static struct sleep_save exynos5_regs_save[] = { - /* Common GPIO Part1 */ - SAVE_ITEM(S5P_VA_GPIO + 0x700), - SAVE_ITEM(S5P_VA_GPIO + 0x704), - SAVE_ITEM(S5P_VA_GPIO + 0x708), - SAVE_ITEM(S5P_VA_GPIO + 0x70C), - SAVE_ITEM(S5P_VA_GPIO + 0x710), - SAVE_ITEM(S5P_VA_GPIO + 0x714), - SAVE_ITEM(S5P_VA_GPIO + 0x718), - SAVE_ITEM(S5P_VA_GPIO + 0x71C), - SAVE_ITEM(S5P_VA_GPIO + 0x720), - SAVE_ITEM(S5P_VA_GPIO + 0x724), - SAVE_ITEM(S5P_VA_GPIO + 0x728), - SAVE_ITEM(S5P_VA_GPIO + 0x72C), - SAVE_ITEM(S5P_VA_GPIO + 0x730), - SAVE_ITEM(S5P_VA_GPIO + 0x900), - SAVE_ITEM(S5P_VA_GPIO + 0x904), - SAVE_ITEM(S5P_VA_GPIO + 0x908), - SAVE_ITEM(S5P_VA_GPIO + 0x90C), - SAVE_ITEM(S5P_VA_GPIO + 0x910), - SAVE_ITEM(S5P_VA_GPIO + 0x914), - SAVE_ITEM(S5P_VA_GPIO + 0x918), - SAVE_ITEM(S5P_VA_GPIO + 0x91C), - SAVE_ITEM(S5P_VA_GPIO + 0x920), - SAVE_ITEM(S5P_VA_GPIO + 0x924), - SAVE_ITEM(S5P_VA_GPIO + 0x928), - SAVE_ITEM(S5P_VA_GPIO + 0x92C), - SAVE_ITEM(S5P_VA_GPIO + 0x930), - /* Common GPIO Part2 */ - SAVE_ITEM(S5P_VA_GPIO2 + 0x700), - SAVE_ITEM(S5P_VA_GPIO2 + 0x704), - SAVE_ITEM(S5P_VA_GPIO2 + 0x708), - SAVE_ITEM(S5P_VA_GPIO2 + 0x70C), - SAVE_ITEM(S5P_VA_GPIO2 + 0x710), - SAVE_ITEM(S5P_VA_GPIO2 + 0x714), - SAVE_ITEM(S5P_VA_GPIO2 + 0x718), - SAVE_ITEM(S5P_VA_GPIO2 + 0x71C), - SAVE_ITEM(S5P_VA_GPIO2 + 0x720), - SAVE_ITEM(S5P_VA_GPIO2 + 0x900), - SAVE_ITEM(S5P_VA_GPIO2 + 0x904), - SAVE_ITEM(S5P_VA_GPIO2 + 0x908), - SAVE_ITEM(S5P_VA_GPIO2 + 0x90C), - SAVE_ITEM(S5P_VA_GPIO2 + 0x910), - SAVE_ITEM(S5P_VA_GPIO2 + 0x914), - SAVE_ITEM(S5P_VA_GPIO2 + 0x918), - SAVE_ITEM(S5P_VA_GPIO2 + 0x91C), - SAVE_ITEM(S5P_VA_GPIO2 + 0x920), -}; - -void exynos5_cpu_suspend(void) -{ - unsigned int tmp; - - /* Disable wakeup by EXT_GIC */ - tmp = __raw_readl(EXYNOS5_WAKEUP_MASK); - tmp |= EXYNOS5_DEFAULT_WAKEUP_MACK; - __raw_writel(tmp, EXYNOS5_WAKEUP_MASK); - - /* - * GPS LPI mask. - */ - if (samsung_rev() < EXYNOS5250_REV_1_0) - __raw_writel(0x10000, EXYNOS5_GPS_LPI); - - if (samsung_rev() >= EXYNOS5250_REV_1_0) - exynos4_reset_assert_ctrl(0); - -#ifdef CONFIG_ARM_TRUSTZONE - exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); -#else - /* issue the standby signal into the pm unit. */ - cpu_do_idle(); -#endif -} - -static void exynos5_pm_prepare(void) -{ - unsigned int tmp; - - if (exynos5_sleep_gpio_table_set) - exynos5_sleep_gpio_table_set(); - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - /* Disable USE_RETENTION of JPEG_MEM_OPTION */ - tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); - tmp &= ~EXYNOS5_OPTION_USE_RETENTION; - __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); - } - - if (samsung_rev() >= EXYNOS5250_REV_1_0) { - tmp = __raw_readl(EXYNOS5_ARM_L2_OPTION); - tmp &= ~(1 << 4); - __raw_writel(tmp, EXYNOS5_ARM_L2_OPTION); - } - - /* Set value of power down register for sleep mode */ - exynos5_sys_powerdown_conf(SYS_SLEEP); - __raw_writel(S5P_CHECK_SLEEP, REG_INFORM1); - - /* ensure at least INFORM0 has the resume address */ - __raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0); - - if (exynos4_is_c2c_use()) { - tmp = __raw_readl(EXYNOS5_INTRAM_MEM_OPTION); - tmp &= ~EXYNOS5_OPTION_USE_RETENTION; - __raw_writel(tmp, EXYNOS5_INTRAM_MEM_OPTION); - } - - s3c_pm_do_restore_core(exynos5_set_clksrc, ARRAY_SIZE(exynos5_set_clksrc)); -} - -static int exynos5_pm_add(struct sys_device *sysdev) -{ - pm_cpu_prep = exynos5_pm_prepare; - pm_cpu_sleep = exynos5_cpu_suspend; - - return 0; -} - -static struct sysdev_driver exynos5_pm_driver = { - .add = exynos5_pm_add, -}; - -static __init int exynos5_pm_drvinit(void) -{ - s3c_pm_init(); - - return sysdev_driver_register(&exynos5_sysclass, &exynos5_pm_driver); -} -arch_initcall(exynos5_pm_drvinit); - -bool isp_pwr_off; - -static int exynos5_pm_suspend(void) -{ - unsigned long tmp; - u32 timeout; - - s3c_pm_do_save(exynos5_core_save, ARRAY_SIZE(exynos5_core_save)); - - s3c_pm_do_save(exynos5_regs_save, ARRAY_SIZE(exynos5_regs_save)); - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - if (!(__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN)) { - isp_pwr_off = true; - /* - * Before enter suspend, ISP power domain should be on - */ - __raw_writel(S5P_INT_LOCAL_PWR_EN, - EXYNOS5_ISP_CONFIGURATION); - timeout = 1000; - - while (!(__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN)) { - if (timeout == 0) { - printk(KERN_ERR "ISP power domain can not on\n"); - } - timeout--; - udelay(1); - } - } - } - - tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - tmp &= ~(EXYNOS5_CENTRAL_LOWPWR_CFG); - __raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - - tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_OPTION); - - tmp = (EXYNOS5_USE_STANDBYWFI_ARM_CORE0 | - EXYNOS5_USE_STANDBYWFE_ARM_CORE0); - - __raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_OPTION); - - return 0; -} - -static void exynos5_pm_resume(void) -{ - unsigned long tmp, srctmp; - u32 timeout; - - if (samsung_rev() >= EXYNOS5250_REV_1_0) - exynos4_reset_assert_ctrl(1); - - /* If PMU failed while entering sleep mode, WFI will be - * ignored by PMU and then exiting cpu_do_idle(). - * EXYNOS5_CENTRAL_SEQ_CONFIGURATION bit will not be set - * automatically in this situation. - */ - tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - - if (!(tmp & EXYNOS5_CENTRAL_LOWPWR_CFG)) { - tmp |= EXYNOS5_CENTRAL_LOWPWR_CFG; - __raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION); - /* No need to perform below restore code */ - goto early_wakeup; - } - - if ((samsung_rev() < EXYNOS5250_REV_1_0) && isp_pwr_off) { - srctmp = __raw_readl(EXYNOS5_CLKSRC_TOP3); - /* - * To ISP power domain off, - * first, ISP_ARM power domain be off. - */ - if ((__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1)) { - /* Disable ISP_ARM */ - timeout = __raw_readl(EXYNOS5_ISP_ARM_OPTION); - timeout &= ~EXYNOS5_ISP_ARM_ENABLE; - __raw_writel(timeout, EXYNOS5_ISP_ARM_OPTION); - - /* ISP_ARM power off */ - __raw_writel(0x0, EXYNOS5_ISP_ARM_CONFIGURATION); - - timeout = 1000; - - while (__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1) { - if (timeout == 0) { - printk(KERN_ERR "ISP_ARM power domain can not off\n"); - return; - } - timeout--; - udelay(1); - } - /* CMU_RESET_ISP_ARM off */ - __raw_writel(0x0, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG); - } - - __raw_writel(0x0, EXYNOS5_ISP_CONFIGURATION); - - /* Wait max 1ms */ - timeout = 1000; - while (__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN) { - if (timeout == 0) { - printk(KERN_ERR "Power domain ISP disable failed.\n"); - return; - } - timeout--; - udelay(1); - } - - __raw_writel(srctmp, EXYNOS5_CLKSRC_TOP3); - - isp_pwr_off = false; - } - - /* For release retention */ - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MAU_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_UART_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCA_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCB_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIA_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIB_OPTION); - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_SPI_OPTION); - - /* For Retention release on GPV block */ - __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_OPTION); - - /* Disable CPU_nIRQ[0:1] */ - tmp = ((0x1 << 8) | (0x1 << 0)); - __raw_writel(tmp, S5P_VA_COMBINER_BASE + 0x54); - - bts_enable(PD_TOP); - - s3c_pm_do_restore(exynos5_regs_save, ARRAY_SIZE(exynos5_regs_save)); - - s3c_pm_do_restore_core(exynos5_core_save, ARRAY_SIZE(exynos5_core_save)); - -early_wakeup: - __raw_writel(0x0, REG_INFORM1); -} - -static struct syscore_ops exynos5_pm_syscore_ops = { - .suspend = exynos5_pm_suspend, - .resume = exynos5_pm_resume, -}; - -static __init int exynos5_pm_syscore_init(void) -{ - register_syscore_ops(&exynos5_pm_syscore_ops); - - return 0; -} -arch_initcall(exynos5_pm_syscore_init); diff --git a/arch/arm/mach-exynos/pmu-exynos5.c b/arch/arm/mach-exynos/pmu-exynos5.c deleted file mode 100644 index 27ff96c..0000000 --- a/arch/arm/mach-exynos/pmu-exynos5.c +++ /dev/null @@ -1,298 +0,0 @@ -/* linux/arch/arm/mach-exynos/pmu-exynos5.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS5 - CPU PMU(Power Management Unit) support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/io.h> -#include <linux/kernel.h> - -#include <mach/regs-clock.h> -#include <mach/regs-pmu5.h> -#include <mach/pmu.h> - -#include <plat/cpu.h> - -static struct exynos4_pmu_conf *exynos5_pmu_config; - -static unsigned int entry_cnt; - -static struct exynos4_pmu_conf exynos52xx_pmu_config[] = { - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ - { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} }, - { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, -}; - -static struct exynos4_pmu_conf exynos52xx_pmu_config_gps[] = { - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ - { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_GPS_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_GPS_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_GPS_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, -}; - -static struct exynos4_pmu_conf exynos52xx_pmu_c2c_config[] = { - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ - { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, -}; - -void __iomem *list_both_cnt_feed[] = { - EXYNOS5_ARM_CORE0_OPTION, - EXYNOS5_ARM_CORE1_OPTION, - EXYNOS5_ARM_COMMON_OPTION, - EXYNOS5_GSCL_OPTION, - EXYNOS5_ISP_OPTION, - EXYNOS5_MFC_OPTION, - EXYNOS5_G3D_OPTION, - EXYNOS5_DISP1_OPTION, - EXYNOS5_MAU_OPTION, - EXYNOS5_TOP_PWR_OPTION, - EXYNOS5_TOP_PWR_SYSMEM_OPTION, -}; - -void __iomem *list_diable_wfi_wfe[] = { - EXYNOS5_ARM_CORE1_OPTION, - EXYNOS5_FSYS_ARM_OPTION, - EXYNOS5_ISP_ARM_OPTION, -}; - -static void exynos5_init_pmu(void) -{ - unsigned int i; - unsigned int tmp; - - /* - * Enable both SC_FEEDBACK and SC_COUNTER - */ - for (i = 0 ; i < ARRAY_SIZE(list_both_cnt_feed) ; i++) { - tmp = __raw_readl(list_both_cnt_feed[i]); - tmp |= (EXYNOS5_USE_SC_FEEDBACK | - EXYNOS5_USE_SC_COUNTER); - __raw_writel(tmp, list_both_cnt_feed[i]); - } - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - tmp = __raw_readl(EXYNOS5_GPS_OPTION); - tmp |= (EXYNOS5_USE_SC_FEEDBACK | - EXYNOS5_USE_SC_COUNTER); - __raw_writel(tmp, EXYNOS5_GPS_OPTION); - } - - /* - * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable - * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable - */ - if (samsung_rev() < EXYNOS5250_REV_1_0) { - tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); - tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL | - EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN); - __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); - } else { - tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION); - tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; - __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); - } - - /* - * Disable WFI/WFE on XXX_OPTION - */ - for (i = 0 ; i < ARRAY_SIZE(list_diable_wfi_wfe) ; i++) { - tmp = __raw_readl(list_diable_wfi_wfe[i]); - tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | - EXYNOS5_OPTION_USE_STANDBYWFI); - __raw_writel(tmp, list_diable_wfi_wfe[i]); - } -} - -void exynos5_pmu_xclkout_set(unsigned int enable, enum xclkout_select source) -{ - unsigned int tmp; - - if (enable) { - tmp = __raw_readl(S5P_PMU_DEBUG); - /* CLKOUT enable */ - tmp &= ~ (0xF << S5P_PMU_CLKOUT_SEL_SHIFT | S5P_CLKOUT_DISABLE); - tmp |= (source << S5P_PMU_CLKOUT_SEL_SHIFT); - __raw_writel(tmp, S5P_PMU_DEBUG); - } else { - tmp = __raw_readl(S5P_PMU_DEBUG); - /* CLKOUT disable */ - tmp |= S5P_CLKOUT_DISABLE; - __raw_writel(tmp, S5P_PMU_DEBUG); - } - - printk(KERN_DEBUG "pmu_debug: 0x%08x\n", __raw_readl(S5P_PMU_DEBUG)); -} -EXPORT_SYMBOL_GPL(exynos5_pmu_xclkout_set); - -void exynos5_sys_powerdown_xxti_control(unsigned int enable) -{ - unsigned int count = entry_cnt; - - if (enable) - exynos5_pmu_config[count - 1].val[SYS_SLEEP] = 0x1; - else - exynos5_pmu_config[count - 1].val[SYS_SLEEP] = 0x0; - - printk(KERN_DEBUG "xxti_control: %ld\n", - exynos5_pmu_config[count - 1].val[SYS_SLEEP]); -} -EXPORT_SYMBOL_GPL(exynos5_sys_powerdown_xxti_control); - - -void exynos5_sys_powerdown_conf(enum sys_powerdown mode) -{ - unsigned int count = entry_cnt; - unsigned int i; - - exynos5_init_pmu(); - - for (; count > 0; count--) - __raw_writel(exynos5_pmu_config[count - 1].val[mode], - exynos5_pmu_config[count - 1].reg); - - if (samsung_rev() < EXYNOS5250_REV_1_0) { - for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_config_gps); i++) { - __raw_writel(exynos52xx_pmu_config_gps[i].val[mode], - exynos52xx_pmu_config_gps[i].reg); - } - - } - - if ((mode != SYS_AFTR) && (exynos4_is_c2c_use())) { - pr_info("%s power mode enter with C2C Enabling\n" - , (mode == SYS_LPA) ? "LPA" : "SLEEP"); - - for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_c2c_config); i++) { - __raw_writel(exynos52xx_pmu_c2c_config[i].val[mode], - exynos52xx_pmu_c2c_config[i].reg); - } - } -} - -static int __init exynos5_pmu_init(void) -{ - exynos5_pmu_config = exynos52xx_pmu_config; - entry_cnt = ARRAY_SIZE(exynos52xx_pmu_config); - printk(KERN_INFO "%s: PMU supports 52XX(%d)\n" - , __func__, entry_cnt); - - return 0; -} -arch_initcall(exynos5_pmu_init); diff --git a/arch/arm/mach-exynos/px-switch.c b/arch/arm/mach-exynos/px-switch.c index 90772ed..99f0e15 100644 --- a/arch/arm/mach-exynos/px-switch.c +++ b/arch/arm/mach-exynos/px-switch.c @@ -61,22 +61,45 @@ static ssize_t store_usb_sel(struct device *dev, static ssize_t show_uart_sel(struct device *dev, struct device_attribute *attr, char *buf) { +#ifdef CONFIG_MACH_P8LTE + /* 2 for LTE, 1 for AP, 0 for CP */ + int val_sel1, val_sel2; + val_sel1 = gpio_get_value(GPIO_UART_SEL1); + val_sel2 = gpio_get_value(GPIO_UART_SEL2); + return sprintf(buf, "%d", val_sel1 << (1 - val_sel2)); +#else int val_sel; +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + int val_sel2; +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ const char *mode; val_sel = gpio_get_value(GPIO_UART_SEL); +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + val_sel2 = gpio_get_value(GPIO_UART_SEL2); +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ if (val_sel == 0) { /* CP */ mode = "CP"; } else { - /* AP */ - mode = "AP"; +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + if (val_sel2 == 0) { +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ + /* AP */ + mode = "AP"; +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + } else { + /* Keyboard DOCK */ + mode = "DOCK"; + } +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ } pr_info("%s: %s\n", __func__, mode); return sprintf(buf, "%s\n", mode); +#endif /* CONFIG_MACH_P8LTE */ } static ssize_t store_uart_sel(struct device *dev, @@ -84,20 +107,63 @@ static ssize_t store_uart_sel(struct device *dev, const char *buf, size_t count) { int uart_sel = -1; +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + int uart_sel2 = -1; +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ + +#ifdef CONFIG_MACH_P8LTE + int set_val1, set_val2, ret = 0; +#endif /* CONFIG_MACH_P8LTE */ pr_info("%s: %s\n", __func__, buf); +#ifdef CONFIG_MACH_P8LTE + /* 2 for LTE, 1 for AP, 0 for CP */ + ret = sscanf(buf, "%d", &uart_sel); + + if (ret != 1) + return -EINVAL; + + set_val1 = (uart_sel > 0) ? 1 : 0; + set_val2 = uart_sel & 0x0001; + + gpio_set_value(GPIO_UART_SEL1, set_val1); + gpio_set_value(GPIO_UART_SEL2, set_val2); +#else + uart_sel = gpio_get_value(GPIO_UART_SEL); +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + uart_sel2 = gpio_get_value(GPIO_UART_SEL2); +#endif if (!strncasecmp(buf, "AP", 2)) { uart_sel = 1; +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + uart_sel2 = 0; +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ } else if (!strncasecmp(buf, "CP", 2)) { uart_sel = 0; } else { +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + if (!strncasecmp(buf, "DOCK", 4)) { + uart_sel = 1; + uart_sel2 = 1; + } else { +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ pr_err("%s: wrong uart_sel value(%s)!!\n", __func__, buf); return -EINVAL; +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + } +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ } /* 1 for AP, 0 for CP */ gpio_set_value(GPIO_UART_SEL, uart_sel); + pr_info("%s: uart_sel(%d)\n", __func__, uart_sel); +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + /* 1 for (AP)DOCK, 0 for (AP)FAC */ + gpio_set_value(GPIO_UART_SEL2, uart_sel2); + pr_info("%s: uart_sel2(%d)\n", __func__, uart_sel2); +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ +#endif /* CONFIG_MACH_P8LTE */ return count; } @@ -210,10 +276,22 @@ static void usb_apply_path(enum usb_path_t path) #else gpio_set_value(GPIO_USB_SEL1, 0); gpio_set_value(GPIO_USB_SEL2, 1); + /* don't care SEL3 */ +#if defined(CONFIG_MACH_P8LTE) gpio_set_value(GPIO_USB_SEL3, 1); -#endif +#endif /* CONFIG_MACH_P8LTE */ +#endif /* CONFIG_MACH_P4NOTE */ + goto out_nochange; + } + +#if defined(CONFIG_MACH_P4NOTE) + if (path & USB_PATH_TA) { + gpio_set_value(GPIO_USB_SEL0, 0); + gpio_set_value(GPIO_USB_SEL1, 0); goto out_nochange; } +#endif /* CONFIG_MACH_P4NOTE */ + if (path & USB_PATH_CP) { pr_info("DEBUG: set USB path to CP\n"); #if defined(CONFIG_MACH_P4NOTE) @@ -222,8 +300,11 @@ static void usb_apply_path(enum usb_path_t path) #else gpio_set_value(GPIO_USB_SEL1, 0); gpio_set_value(GPIO_USB_SEL2, 0); + /* don't care SEL3 */ +#if defined(CONFIG_MACH_P8LTE) gpio_set_value(GPIO_USB_SEL3, 1); -#endif +#endif /* CONFIG_MACH_P8LTE */ +#endif /* CONFIG_MACH_P4NOTE */ mdelay(3); goto out_cp; } @@ -241,14 +322,14 @@ static void usb_apply_path(enum usb_path_t path) goto out_ap; } if (path & USB_PATH_HOST) { -#ifndef CONFIG_MACH_P8LTE +#if !defined(CONFIG_MACH_P8LTE) gpio_set_value(GPIO_USB_SEL1, 1); -#endif +#endif /* !CONFIG_MACH_P8LTE */ /* don't care SEL2 */ gpio_set_value(GPIO_USB_SEL3, 0); goto out_ap; } -#endif +#endif /* CONFIG_MACH_P4NOTE */ /* default */ #if defined(CONFIG_MACH_P4NOTE) @@ -260,9 +341,9 @@ static void usb_apply_path(enum usb_path_t path) gpio_set_value(GPIO_USB_SEL2, 1); #else gpio_set_value(GPIO_USB_SEL2, 0); -#endif +#endif /* CONFIG_MACH_P8LTE */ gpio_set_value(GPIO_USB_SEL3, 1); -#endif +#endif /* CONFIG_MACH_P4NOTE */ out_ap: pr_info("%s: %x safeout2 off\n", __func__, path); @@ -296,6 +377,13 @@ sysfs_noti: ... usb_switch_unlock(); (this restores previous usb switch settings) */ +enum usb_path_t usb_switch_get_path(void) +{ + pr_info("%s: current path(%d)\n", __func__, current_path); + + return current_path; +} + void usb_switch_set_path(enum usb_path_t path) { pr_info("%s: %x current_path before changing\n", @@ -332,6 +420,11 @@ void usb_switch_unlock(void) #ifdef CONFIG_MACH_P4NOTE static void init_gpio(void) { + int uart_sel = -1; +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + int uart_sel2 = -1; +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ + s3c_gpio_cfgpin(GPIO_USB_SEL0, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_USB_SEL0, S3C_GPIO_PULL_NONE); @@ -343,66 +436,164 @@ static void init_gpio(void) s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + s3c_gpio_cfgpin(GPIO_UART_SEL2, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL2, S3C_GPIO_PULL_NONE); +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ + + uart_sel = gpio_get_value(GPIO_UART_SEL); + pr_info("%s: uart_sel(%d)\n", __func__, uart_sel); +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + uart_sel2 = gpio_get_value(GPIO_UART_SEL2); + pr_info("%s: uart_sel2(%d)\n", __func__, uart_sel2); +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ +} +#endif + +#ifdef CONFIG_TARGET_LOCALE_KOR +#include <plat/devs.h> +#include "../../../drivers/usb/gadget/s3c_udc.h" +/* usb access control for SEC DM */ +struct device *usb_lock; +static int is_usb_locked; + +int px_switch_get_usb_lock_state(void) +{ + return is_usb_locked; +} +EXPORT_SYMBOL(px_switch_get_usb_lock_state); + +static ssize_t px_switch_show_usb_lock(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (is_usb_locked) + return snprintf(buf, PAGE_SIZE, "USB_LOCK"); + else + return snprintf(buf, PAGE_SIZE, "USB_UNLOCK"); +} + +static ssize_t px_switch_store_usb_lock(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int lock; + struct s3c_udc *udc = platform_get_drvdata(&s3c_device_usbgadget); + + if (!strncmp(buf, "0", 1)) + lock = 0; + else if (!strncmp(buf, "1", 1)) + lock = 1; + else { + pr_warn("%s: Wrong command\n", __func__); + return count; + } + + if (IS_ERR_OR_NULL(udc)) + return count; + + pr_info("%s: lock=%d\n", __func__, lock); + + if (lock != is_usb_locked) { + is_usb_locked = lock; + + if (lock) { + if (udc->udc_enabled) + usb_gadget_vbus_disconnect(&udc->gadget); + } + } + + return count; } + +static DEVICE_ATTR(enable, 0664, + px_switch_show_usb_lock, px_switch_store_usb_lock); #endif static int __init usb_switch_init(void) { int ret; +/* USB_SEL gpio_request */ #if defined(CONFIG_MACH_P4NOTE) gpio_request(GPIO_USB_SEL0, "GPIO_USB_SEL0"); gpio_request(GPIO_USB_SEL1, "GPIO_USB_SEL1"); gpio_request(GPIO_USB_SEL_CP, "GPIO_USB_SEL_CP"); - gpio_request(GPIO_UART_SEL, "GPIO_UART_SEL"); #else gpio_request(GPIO_USB_SEL1, "GPIO_USB_SEL1"); gpio_request(GPIO_USB_SEL2, "GPIO_USB_SEL2"); gpio_request(GPIO_USB_SEL3, "GPIO_USB_SEL3"); +#endif /* CONFIG_MACH_P4NOTE */ + +/* UART_SEL gpio_request */ #ifdef CONFIG_MACH_P8LTE gpio_request(GPIO_UART_SEL1, "GPIO_UART_SEL1"); gpio_request(GPIO_UART_SEL2, "GPIO_UART_SEL2"); #else gpio_request(GPIO_UART_SEL, "GPIO_UART_SEL"); -#endif -#endif +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + gpio_request(GPIO_UART_SEL2, "GPIO_UART_SEL2"); +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ +#endif /* CONFIG_MACH_P8LTE */ +/* USB_SEL gpio_export */ #if defined(CONFIG_MACH_P4NOTE) gpio_export(GPIO_USB_SEL0, 1); gpio_export(GPIO_USB_SEL1, 1); gpio_export(GPIO_USB_SEL_CP, 1); - gpio_export(GPIO_UART_SEL, 1); #else gpio_export(GPIO_USB_SEL1, 1); gpio_export(GPIO_USB_SEL2, 1); gpio_export(GPIO_USB_SEL3, 1); +#endif /* CONFIG_MACH_P4NOTE */ + +/* UART_SEL gpio_export */ #ifdef CONFIG_MACH_P8LTE gpio_export(GPIO_UART_SEL1, 1); gpio_export(GPIO_UART_SEL2, 1); #else gpio_export(GPIO_UART_SEL, 1); -#endif -#endif +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + gpio_export(GPIO_UART_SEL2, 1); +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ +#endif /* CONFIG_MACH_P8LTE */ BUG_ON(!sec_class); sec_switch_dev = device_create(sec_class, NULL, 0, NULL, "switch"); BUG_ON(!sec_switch_dev); + +/* USB_SEL gpio_export_link */ #if defined(CONFIG_MACH_P4NOTE) gpio_export_link(sec_switch_dev, "GPIO_USB_SEL0", GPIO_USB_SEL0); gpio_export_link(sec_switch_dev, "GPIO_USB_SEL1", GPIO_USB_SEL1); gpio_export_link(sec_switch_dev, "GPIO_USB_SEL_CP", GPIO_USB_SEL_CP); - gpio_export_link(sec_switch_dev, "GPIO_UART_SEL", GPIO_UART_SEL); #else gpio_export_link(sec_switch_dev, "GPIO_USB_SEL1", GPIO_USB_SEL1); gpio_export_link(sec_switch_dev, "GPIO_USB_SEL2", GPIO_USB_SEL2); gpio_export_link(sec_switch_dev, "GPIO_USB_SEL3", GPIO_USB_SEL3); +#endif /* CONFIG_MACH_P4NOTE */ + +/* UART_SEL gpio_export_link */ #ifdef CONFIG_MACH_P8LTE gpio_export_link(sec_switch_dev, "GPIO_UART_SEL1", GPIO_UART_SEL1); gpio_export_link(sec_switch_dev, "GPIO_UART_SEL2", GPIO_UART_SEL2); #else gpio_export_link(sec_switch_dev, "GPIO_UART_SEL", GPIO_UART_SEL); -#endif +#if (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) + gpio_export_link(sec_switch_dev, "GPIO_UART_SEL2", GPIO_UART_SEL2); +#endif /* (CONFIG_SAMSUNG_ANALOG_UART_SWITCH == 2) */ +#endif /* CONFIG_MACH_P8LTE */ + +#ifdef CONFIG_TARGET_LOCALE_KOR + usb_lock = device_create(sec_class, sec_switch_dev, + MKDEV(0, 0), NULL, ".usb_lock"); + + if (IS_ERR(usb_lock)) + pr_err("Failed to create device (usb_lock)!\n"); + + if (device_create_file(usb_lock, &dev_attr_enable) < 0) + pr_err("Failed to create device file(.usblock/enable)!\n"); #endif /*init_MUTEX(&usb_switch_sem);*/ diff --git a/arch/arm/mach-exynos/px.h b/arch/arm/mach-exynos/px.h index 19cc144..09b54ae 100644 --- a/arch/arm/mach-exynos/px.h +++ b/arch/arm/mach-exynos/px.h @@ -13,6 +13,10 @@ extern void p2_config_sleep_gpio_table(void); #elif defined(CONFIG_MACH_P8) extern void p8_config_gpio_table(void); extern void p8_config_sleep_gpio_table(void); +#elif defined(CONFIG_MACH_P8LTE) +extern void modem_p8ltevzw_init(void); +extern void p8lte_config_gpio_table(void); +extern void p8lte_config_sleep_gpio_table(void); #else /* CONFIG_MACH_P4) */ extern void p4_config_gpio_table(void); extern void p4_config_sleep_gpio_table(void); diff --git a/arch/arm/mach-exynos/reserve_mem-exynos4.c b/arch/arm/mach-exynos/reserve_mem-exynos4.c index 23af3f7..c48c64f 100644 --- a/arch/arm/mach-exynos/reserve_mem-exynos4.c +++ b/arch/arm/mach-exynos/reserve_mem-exynos4.c @@ -49,7 +49,7 @@ struct s5p_media_device media_devs[] = { }, #endif -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) #ifdef CONFIG_ANDROID_PMEM_MEMSIZE_PMEM { .id = S5P_MDEV_PMEM, diff --git a/arch/arm/mach-exynos/s2plus-panel.h b/arch/arm/mach-exynos/s2plus-panel.h deleted file mode 100644 index 9640f8b..0000000 --- a/arch/arm/mach-exynos/s2plus-panel.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * arch/arm/mach-exynos/s2plus-panel.h - */ - -#ifndef __S2PLUS_PANEL_H__ -#define __S2PLUS_PANEL_H__ - -#define SLEEPMSEC 0x1000 -#define ENDDEF 0x2000 -#define DEFMASK 0xFF00 -#define COMMAND_ONLY 0xFE -#define DATA_ONLY 0xFF - - -static const unsigned short SEQ_USER_SETTING[] = { - 0xF0, 0x5A, - - DATA_ONLY, 0x5A, - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_DISPCTL[] = { - 0xF2, 0x02, - - DATA_ONLY, 0x06, - DATA_ONLY, 0x0A, - DATA_ONLY, 0x10, - DATA_ONLY, 0x10, - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_GTCON[] = { - 0xF7, 0x09, - - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_PANEL_CONDITION[] = { - 0xF8, 0x05, - DATA_ONLY, 0x5E, - DATA_ONLY, 0x96, - DATA_ONLY, 0x6B, - DATA_ONLY, 0x7D, - DATA_ONLY, 0x0D, - DATA_ONLY, 0x3F, - DATA_ONLY, 0x00, - DATA_ONLY, 0x00, - DATA_ONLY, 0x32, - DATA_ONLY, 0x00, - DATA_ONLY, 0x00, - DATA_ONLY, 0x00, - DATA_ONLY, 0x00, - DATA_ONLY, 0x00, - DATA_ONLY, 0x00, - DATA_ONLY, 0x07, - DATA_ONLY, 0x05, - DATA_ONLY, 0x1F, - DATA_ONLY, 0x1F, - DATA_ONLY, 0x1F, - DATA_ONLY, 0x00, - DATA_ONLY, 0x00, - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_SLPOUT[] = { - 0x11, COMMAND_ONLY, - SLEEPMSEC, 120, - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_SLPIN[] = { - 0x10, COMMAND_ONLY, - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_DISPON[] = { - 0x29, COMMAND_ONLY, - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_DISPOFF[] = { - 0x28, COMMAND_ONLY, - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_ELVSS_ON[] = { - 0xB1, 0x0F, - - DATA_ONLY, 0x00, - DATA_ONLY, 0x16, - ENDDEF, 0x00 -}; - - -static const unsigned short SEQ_ACL_ON[] = { - 0xC0, 0x01, - - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_ACL_OFF[] = { - 0xC0, 0x00, - - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_ACL_40P[] = { - 0xC1, 0x4D, - - DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, - DATA_ONLY, 0x06, DATA_ONLY, 0x11, DATA_ONLY, 0x1A, DATA_ONLY, 0x20, - DATA_ONLY, 0x25, DATA_ONLY, 0x29, DATA_ONLY, 0x2D, DATA_ONLY, 0x30, - DATA_ONLY, 0x33, DATA_ONLY, 0x35, - - 0xC0, 0x01, - - ENDDEF, 0x00 -}; - - -static const unsigned short SEQ_ACL_43P[] = { - 0xC1, 0x4D, - - DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, - DATA_ONLY, 0x07, DATA_ONLY, 0x12, DATA_ONLY, 0x1C, DATA_ONLY, 0x23, - DATA_ONLY, 0x29, DATA_ONLY, 0x2D, DATA_ONLY, 0x31, DATA_ONLY, 0x34, - DATA_ONLY, 0x37, DATA_ONLY, 0x3A, - - 0xC0, 0x01, - - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_ACL_45P[] = { - 0xC1, 0x4D, - - DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, - DATA_ONLY, 0x07, DATA_ONLY, 0x13, DATA_ONLY, 0x1E, DATA_ONLY, 0x25, - DATA_ONLY, 0x2B, DATA_ONLY, 0x30, DATA_ONLY, 0x34, DATA_ONLY, 0x37, - DATA_ONLY, 0x3A, DATA_ONLY, 0x3D, - - 0xC0, 0x01, - - ENDDEF, 0x00 -}; - - -static const unsigned short SEQ_ACL_47P[] = { - 0xC1, 0x4D, - - DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, - DATA_ONLY, 0x07, DATA_ONLY, 0x14, DATA_ONLY, 0x20, DATA_ONLY, 0x28, - DATA_ONLY, 0x2E, DATA_ONLY, 0x33, DATA_ONLY, 0x37, DATA_ONLY, 0x3B, - DATA_ONLY, 0x3E, DATA_ONLY, 0x41, - - 0xC0, 0x01, - - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_ACL_48P[] = { - 0xC1, 0x4D, - - DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, - DATA_ONLY, 0x08, DATA_ONLY, 0x15, DATA_ONLY, 0x20, DATA_ONLY, 0x29, - DATA_ONLY, 0x2F, DATA_ONLY, 0x34, DATA_ONLY, 0x39, DATA_ONLY, 0x3D, - DATA_ONLY, 0x40, DATA_ONLY, 0x43, - - 0xC0, 0x01, - - ENDDEF, 0x00 -}; - -static const unsigned short SEQ_ACL_50P[] = { - 0xC1, 0x4D, - - DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, - DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, - DATA_ONLY, 0x08, DATA_ONLY, 0x16, DATA_ONLY, 0x22, DATA_ONLY, 0x2B, - DATA_ONLY, 0x31, DATA_ONLY, 0x37, DATA_ONLY, 0x3B, DATA_ONLY, 0x3F, - DATA_ONLY, 0x43, DATA_ONLY, 0x46, - - 0xC0, 0x01, - - ENDDEF, 0x00 -}; - -static const unsigned short *ACL_cutoff_set[] = { - SEQ_ACL_OFF, - SEQ_ACL_40P, - SEQ_ACL_43P, - SEQ_ACL_45P, - SEQ_ACL_47P, - SEQ_ACL_48P, - SEQ_ACL_50P, -}; - -#endif diff --git a/arch/arm/mach-exynos/sec-common.c b/arch/arm/mach-exynos/sec-common.c index e099239..6fb5b458d 100644 --- a/arch/arm/mach-exynos/sec-common.c +++ b/arch/arm/mach-exynos/sec-common.c @@ -15,4 +15,8 @@ static int __init midas_class_create(void) return 0; } +#ifdef CONFIG_FAST_RESUME +beforeresume_initcall(midas_class_create); +#else subsys_initcall(midas_class_create); +#endif diff --git a/arch/arm/mach-exynos/sec-reboot.c b/arch/arm/mach-exynos/sec-reboot.c index fd70fc6..d847c6d 100644 --- a/arch/arm/mach-exynos/sec-reboot.c +++ b/arch/arm/mach-exynos/sec-reboot.c @@ -91,9 +91,6 @@ static void sec_reboot(char str, const char *cmd) else if (!strcmp(cmd, "recovery")) writel(REBOOT_MODE_PREFIX | REBOOT_MODE_RECOVERY, S5P_INFORM3); - else if (!strcmp(cmd, "bootloader")) - writel(REBOOT_MODE_PREFIX | REBOOT_MODE_DOWNLOAD, - S5P_INFORM3); else if (!strcmp(cmd, "download")) writel(REBOOT_MODE_PREFIX | REBOOT_MODE_DOWNLOAD, S5P_INFORM3); diff --git a/arch/arm/mach-exynos/sec-switch.c b/arch/arm/mach-exynos/sec-switch.c index 7b8726c..787a424 100644 --- a/arch/arm/mach-exynos/sec-switch.c +++ b/arch/arm/mach-exynos/sec-switch.c @@ -25,7 +25,9 @@ #include <linux/power_supply.h> #include <linux/battery/samsung_battery.h> +#ifdef CONFIG_SWITCH #include <linux/switch.h> +#endif #include <linux/sii9234.h> #ifdef CONFIG_USB_HOST_NOTIFY @@ -46,9 +48,11 @@ #include <linux/platform_data/mms_ts.h> #endif +#ifdef CONFIG_SWITCH static struct switch_dev switch_dock = { .name = "dock", }; +#endif extern struct class *sec_class; @@ -127,27 +131,98 @@ static ssize_t midas_switch_store_vbus(struct device *dev, DEVICE_ATTR(disable_vbus, 0664, midas_switch_show_vbus, midas_switch_store_vbus); +#ifdef CONFIG_TARGET_LOCALE_KOR +#include "../../../drivers/usb/gadget/s3c_udc.h" +/* usb access control for SEC DM */ +struct device *usb_lock; +static int is_usb_locked; + +static ssize_t midas_switch_show_usb_lock(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (is_usb_locked) + return snprintf(buf, PAGE_SIZE, "USB_LOCK"); + else + return snprintf(buf, PAGE_SIZE, "USB_UNLOCK"); +} + +static ssize_t midas_switch_store_usb_lock(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int lock; + struct s3c_udc *udc = platform_get_drvdata(&s3c_device_usbgadget); + + if (!strncmp(buf, "0", 1)) + lock = 0; + else if (!strncmp(buf, "1", 1)) + lock = 1; + else { + pr_warn("%s: Wrong command\n", __func__); + return count; + } + + if (IS_ERR_OR_NULL(udc)) + return count; + + pr_info("%s: lock=%d\n", __func__, lock); + + if (lock != is_usb_locked) { + is_usb_locked = lock; + + if (lock) { + if (udc->udc_enabled) + usb_gadget_vbus_disconnect(&udc->gadget); + } + } + + return count; +} + +static DEVICE_ATTR(enable, 0664, + midas_switch_show_usb_lock, midas_switch_store_usb_lock); +#endif + static int __init midas_sec_switch_init(void) { - int ret; + int ret = 0; switch_dev = device_create(sec_class, NULL, 0, NULL, "switch"); - if (IS_ERR(switch_dev)) - pr_err("Failed to create device(switch)!\n"); + if (IS_ERR(switch_dev)) { + pr_err("%s:%s= Failed to create device(switch)!\n", + __FILE__, __func__); + return -ENODEV; + } ret = device_create_file(switch_dev, &dev_attr_disable_vbus); - if (ret) - pr_err("Failed to create device file(disable_vbus)!\n"); + if (ret) { + pr_err("%s:%s= Failed to create device file(disable_vbus)!\n", + __FILE__, __func__); + return ret; + } - return 0; +#ifdef CONFIG_TARGET_LOCALE_KOR + usb_lock = device_create(sec_class, switch_dev, + MKDEV(0, 0), NULL, ".usb_lock"); + + if (IS_ERR(usb_lock)) + pr_err("Failed to create device (usb_lock)!\n"); + + if (device_create_file(usb_lock, &dev_attr_enable) < 0) + pr_err("Failed to create device file(.usblock/enable)!\n"); +#endif + + return ret; }; int max77693_muic_charger_cb(enum cable_type_muic cable_type) { +#if !defined(USE_CHGIN_INTR) #ifdef CONFIG_BATTERY_MAX77693_CHARGER struct power_supply *psy = power_supply_get_by_name("max77693-charger"); union power_supply_propval value; #endif +#endif pr_info("%s: %d\n", __func__, cable_type); switch (cable_type) { @@ -169,6 +244,7 @@ int max77693_muic_charger_cb(enum cable_type_muic cable_type) case CABLE_TYPE_CARDOCK_MUIC: case CABLE_TYPE_DESKDOCK_MUIC: case CABLE_TYPE_SMARTDOCK_MUIC: + case CABLE_TYPE_AUDIODOCK_MUIC: case CABLE_TYPE_JIG_UART_OFF_VB_MUIC: is_cable_attached = true; break; @@ -177,8 +253,9 @@ int max77693_muic_charger_cb(enum cable_type_muic cable_type) return -EINVAL; } +#if !defined(USE_CHGIN_INTR) #ifdef CONFIG_BATTERY_MAX77693_CHARGER - if (!psy) { + if (!psy || !psy->set_property) { pr_err("%s: fail to get max77693-charger psy\n", __func__); return 0; } @@ -186,12 +263,12 @@ int max77693_muic_charger_cb(enum cable_type_muic cable_type) value.intval = cable_type; psy->set_property(psy, POWER_SUPPLY_PROP_ONLINE, &value); #endif +#endif -#if defined(CONFIG_MACH_SLP_NAPLES) || defined(CONFIG_MACH_MIDAS) -#ifndef CONFIG_MACH_GC1 +#if defined(CONFIG_MACH_SLP_NAPLES) || defined(CONFIG_MACH_MIDAS) \ + || defined(CONFIG_MACH_GC1) || defined(CONFIG_MACH_T0) tsp_charger_infom(is_cable_attached); #endif -#endif #ifdef CONFIG_JACK_MON jack_event_handler("charger", is_cable_attached); #endif @@ -221,6 +298,13 @@ void max77693_muic_usb_cb(u8 usb_mode) host_notifier_device.dev.platform_data; #endif +#ifdef CONFIG_TARGET_LOCALE_KOR + if (is_usb_locked) { + pr_info("%s: usb locked by mdm\n", __func__); + return; + } +#endif + pr_info("MUIC usb_cb:%d\n", usb_mode); if (gadget) { switch (usb_mode) { @@ -288,7 +372,8 @@ void max77693_muic_usb_cb(u8 usb_mode) jack_event_handler("usb", usb_mode); #endif } - +EXPORT_SYMBOL(max77693_muic_usb_cb); +#if !defined(CONFIG_MUIC_MAX77693_SEPARATE_MHL_PORT) /*extern void MHL_On(bool on);*/ void max77693_muic_mhl_cb(int attached) { @@ -313,7 +398,9 @@ void max77693_muic_mhl_cb(int attached) #endif } } +#endif /* !CONFIG_MUIC_MAX77693_SEPARATE_MHL_PORT */ +#if !defined(CONFIG_MUIC_MAX77693_SEPARATE_MHL_PORT) bool max77693_muic_is_mhl_attached(void) { int val; @@ -336,42 +423,22 @@ bool max77693_muic_is_mhl_attached(void) return !!val; #endif } +#endif /* !CONFIG_MUIC_MAX77693_SEPARATE_MHL_PORT */ -void max77693_muic_deskdock_cb(bool attached) -{ - pr_info("MUIC deskdock attached=%d\n", attached); - if (attached) { -#ifdef CONFIG_JACK_MON - jack_event_handler("cradle", 1); -#endif - switch_set_state(&switch_dock, 1); - } else { -#ifdef CONFIG_JACK_MON - jack_event_handler("cradle", 0); -#endif - switch_set_state(&switch_dock, 0); - } -} - -void max77693_muic_cardock_cb(bool attached) +void max77693_muic_dock_cb(int type) { - pr_info("MUIC cardock attached=%d\n", attached); - pr_info("##MUIC [ %s ]- func : %s !!\n", __FILE__, __func__); - if (attached) { + pr_info("%s:%s= MUIC dock type=%d\n", "sec-switch.c", __func__, type); #ifdef CONFIG_JACK_MON - jack_event_handler("cradle", 2); + jack_event_handler("cradle", type); #endif - switch_set_state(&switch_dock, 2); - } else { -#ifdef CONFIG_JACK_MON - jack_event_handler("cradle", 0); +#ifdef CONFIG_SWITCH + switch_set_state(&switch_dock, type); #endif - switch_set_state(&switch_dock, 0); - } } void max77693_muic_init_cb(void) { +#ifdef CONFIG_SWITCH int ret; /* for CarDock, DeskDock */ @@ -381,8 +448,11 @@ void max77693_muic_init_cb(void) if (ret < 0) pr_err("Failed to register dock switch. %d\n", ret); +#endif } +#if !defined(CONFIG_MACH_GC1) && !defined(CONFIG_MACH_T0) && \ +!defined(CONFIG_MACH_M3) && !defined(CONFIG_MACH_SLP_T0_LTE) int max77693_muic_cfg_uart_gpio(void) { int uart_val, path; @@ -399,7 +469,10 @@ int max77693_muic_cfg_uart_gpio(void) path); return path; } +#endif +#if !defined(CONFIG_MACH_GC1) && !defined(CONFIG_MACH_T0) && \ +!defined(CONFIG_MACH_M3) && !defined(CONFIG_MACH_SLP_T0_LTE) void max77693_muic_jig_uart_cb(int path) { pr_info("func:%s : (path=%d\n", __func__, path); @@ -424,6 +497,21 @@ void max77693_muic_jig_uart_cb(int path) } } +#endif + +#if defined(CONFIG_MUIC_DET_JACK) +extern void jack_status_change(int attached); +extern void earkey_status_change(int pressed, int code); + +void max77693_muic_earjack_cb(int attached) +{ + jack_status_change(attached); +} +void max77693_muic_earjackkey_cb(int pressed, unsigned int code) +{ + earkey_status_change(pressed, code); +} +#endif #ifdef CONFIG_USB_HOST_NOTIFY int max77693_muic_host_notify_cb(int enable) @@ -487,22 +575,29 @@ int max77693_muic_set_safeout(int path) struct max77693_muic_data max77693_muic = { .usb_cb = max77693_muic_usb_cb, .charger_cb = max77693_muic_charger_cb, +#if !defined(CONFIG_MUIC_MAX77693_SEPARATE_MHL_PORT) .mhl_cb = max77693_muic_mhl_cb, .is_mhl_attached = max77693_muic_is_mhl_attached, +#endif .set_safeout = max77693_muic_set_safeout, .init_cb = max77693_muic_init_cb, - .deskdock_cb = max77693_muic_deskdock_cb, - .cardock_cb = max77693_muic_cardock_cb, -#if !defined(CONFIG_MACH_GC1) + .dock_cb = max77693_muic_dock_cb, +#if !defined(CONFIG_MACH_GC1) && !defined(CONFIG_MACH_T0) && \ +!defined(CONFIG_MACH_M3) && !defined(CONFIG_MACH_SLP_T0_LTE) .cfg_uart_gpio = max77693_muic_cfg_uart_gpio, .jig_uart_cb = max77693_muic_jig_uart_cb, #endif /* CONFIG_MACH_GC1 */ +#if defined(CONFIG_MUIC_DET_JACK) + .earjack_cb = max77693_muic_earjack_cb, + .earjackkey_cb = max77693_muic_earjackkey_cb, +#endif #ifdef CONFIG_USB_HOST_NOTIFY .host_notify_cb = max77693_muic_host_notify_cb, #else .host_notify_cb = NULL, #endif -#if !defined(CONFIG_MACH_GC1) +#if !defined(CONFIG_MACH_GC1) && !defined(CONFIG_MACH_T0) && \ +!defined(CONFIG_MACH_M3) && !defined(CONFIG_MACH_SLP_T0_LTE) .gpio_usb_sel = GPIO_USB_SEL, #else .gpio_usb_sel = -1, @@ -510,4 +605,31 @@ struct max77693_muic_data max77693_muic = { .jig_state = max77693_set_jig_state, }; +#if defined(CONFIG_MACH_SLP_PQ) || defined(CONFIG_MACH_REDWOOD) || \ +defined(CONFIG_MACH_SLP_T0_LTE) +static void otg_accessory_power(int enable) +{ + u8 on = (u8)!!enable; + + /* max77693 otg power control */ + otg_control(enable); + + gpio_request(GPIO_OTG_EN, "USB_OTG_EN"); + gpio_direction_output(GPIO_OTG_EN, on); + gpio_free(GPIO_OTG_EN); + pr_info("%s: otg accessory power = %d\n", __func__, on); +} + +static struct host_notifier_platform_data host_notifier_pdata = { + .ndev.name = "usb_otg", + .booster = otg_accessory_power, + .thread_enable = 0, +}; + +struct platform_device host_notifier_device = { + .name = "host_notifier", + .dev.platform_data = &host_notifier_pdata, +}; +#endif + device_initcall(midas_sec_switch_init); diff --git a/arch/arm/mach-exynos/sec-switch_max8997.c b/arch/arm/mach-exynos/sec-switch_max8997.c index 51f9c31..3d05864 100644 --- a/arch/arm/mach-exynos/sec-switch_max8997.c +++ b/arch/arm/mach-exynos/sec-switch_max8997.c @@ -209,11 +209,9 @@ static int __init u1_sec_switch_init(void) pr_err("Failed to create device file(.usblock/enable)!\n"); #endif -#if !defined(CONFIG_MACH_U1CAMERA_BD) ret = uart_switch_init(); if (ret) pr_err("Failed to create uart_switch\n"); -#endif /* CONFIG_MACH_U1CAMERA_BD */ return 0; }; diff --git a/arch/arm/mach-exynos/sec_debug.c b/arch/arm/mach-exynos/sec_debug.c index 2e19097..78e2b4a 100644 --- a/arch/arm/mach-exynos/sec_debug.c +++ b/arch/arm/mach-exynos/sec_debug.c @@ -32,6 +32,9 @@ #include <asm/mach/map.h> #include <plat/regs-watchdog.h> +#if defined(CONFIG_SEC_MODEM_P8LTE) +#include <linux/miscdevice.h> +#endif /* klaatu - schedule log */ #ifdef CONFIG_SEC_DEBUG_SCHED_LOG #define SCHED_LOG_MAX 2048 @@ -54,12 +57,17 @@ struct sched_log { struct work_struct *work; work_func_t f; } work[NR_CPUS][SCHED_LOG_MAX]; + struct hrtimer_log { + unsigned long long time; + struct hrtimer *timer; + enum hrtimer_restart (*fn)(struct hrtimer *); + int en; + } hrtimers[NR_CPUS][8]; }; #endif /* CONFIG_SEC_DEBUG_SCHED_LOG */ #ifdef CONFIG_SEC_DEBUG_AUXILIARY_LOG #define AUX_LOG_CPU_CLOCK_MAX 64 -#define AUX_LOG_LOGBUF_LOCK_MAX 64 #define AUX_LOG_LENGTH 128 struct auxiliary_info { @@ -71,7 +79,6 @@ struct auxiliary_info { /* This structure will be modified if some other items added for log */ struct auxiliary_log { struct auxiliary_info CpuClockLog[AUX_LOG_CPU_CLOCK_MAX]; - struct auxiliary_info LogBufLockLog[AUX_LOG_LOGBUF_LOCK_MAX]; }; #else @@ -229,6 +236,7 @@ static struct sched_log sec_debug_log[NR_CPUS][SCHED_LOG_MAX] static atomic_t task_log_idx[NR_CPUS] = { ATOMIC_INIT(-1), ATOMIC_INIT(-1) }; static atomic_t irq_log_idx[NR_CPUS] = { ATOMIC_INIT(-1), ATOMIC_INIT(-1) }; static atomic_t work_log_idx[NR_CPUS] = { ATOMIC_INIT(-1), ATOMIC_INIT(-1) }; +static atomic_t hrtimer_log_idx[NR_CPUS] = { ATOMIC_INIT(-1), ATOMIC_INIT(-1) }; static struct sched_log (*psec_debug_log) = (&sec_debug_log); /* static struct sched_log (*psec_debug_log)[NR_CPUS][SCHED_LOG_MAX] @@ -242,7 +250,6 @@ static unsigned long long gExcpIrqExitTime[NR_CPUS]; static struct auxiliary_log gExcpAuxLog __cacheline_aligned; static struct auxiliary_log *gExcpAuxLogPtr; static atomic_t gExcpAuxCpuClockLogIdx = ATOMIC_INIT(-1); -static atomic_t gExcpAuxLogBufLockLogIdx = ATOMIC_INIT(-1); #endif static int checksum_sched_log(void) @@ -548,6 +555,62 @@ static inline void sec_debug_disable_watchdog(void) } #endif +#if defined(CONFIG_SEC_MODEM_P8LTE) +static void __iomem *idpram_base; +void sec_set_cp_upload(void) +{ + unsigned int send_mail, wait_count; + volatile u16 *cp_dpram_mbx_BA;/*send mail box*/ + volatile u16 *cp_dpram_mbx_AB;/*receive mail box*/ + + cp_dpram_mbx_BA = (volatile u16 *)(idpram_base + 0x3FFC); + cp_dpram_mbx_AB = (volatile u16 *)(idpram_base + 0x3FFE); + + send_mail = 0xc9; /*KERNEL_SEC_DUMP_AP_DEAD_INDICATOR_DPRAM*/ + + *cp_dpram_mbx_BA = send_mail; + + pr_err("%s : set cp upload mode, MailboxBA 0x%x\n", + __func__, send_mail); + + wait_count = 0; + while (1) { + if (*cp_dpram_mbx_AB == 0xc6) { + pr_err("%s - Done.\n", __func__); + break; + } + mdelay(10); + if (++wait_count > 2500) { + pr_err("%s - Fail to set CP uploadmode.\n", __func__); + break; + } + } + pr_err("%s : modem_wait_count : %d\n", __func__, wait_count); +} + +static struct miscdevice sec_cp_upload_dev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "cp_upload", +}; +static __init int sec_cp_upload_init(void) +{ + /*DPRAM_START_ADDRESS_PHYS + DPRAM_SHARED_BANK_SIZE*/ + idpram_base = ioremap_nocache(0x13A00000, 0x4000); + + if (idpram_base == NULL) + printk(KERN_ERR "%s : failed ioremap\n", __func__); + + return misc_register(&sec_cp_upload_dev); +} + +static __exit void sec_cp_upload_exit(void) +{ + misc_deregister(&sec_cp_upload_dev); +} + +module_init(sec_cp_upload_init); +module_exit(sec_cp_upload_exit); +#endif static int sec_debug_panic_handler(struct notifier_block *nb, unsigned long l, void *buf) { @@ -577,21 +640,63 @@ static int sec_debug_panic_handler(struct notifier_block *nb, show_state(); sec_debug_dump_stack(); +#if defined(CONFIG_SEC_MODEM_P8LTE) + sec_set_cp_upload(); +#endif sec_debug_hw_reset(); return 0; } +#if defined(CONFIG_MACH_Q1_BD) +/* + * This function can be used while current pointer is invalid. + */ +int sec_debug_panic_handler_safe(void *buf) +{ + local_irq_disable(); + + sec_debug_set_upload_magic(0x66262564, buf); + + sec_debug_set_upload_cause(UPLOAD_CAUSE_KERNEL_PANIC); + + pr_err("(%s) checksum_sched_log: %x\n", __func__, checksum_sched_log()); + + sec_debug_dump_stack(); + sec_debug_hw_reset(); + + return 0; +} +#endif + #ifdef CONFIG_SEC_DEBUG_FUPLOAD_DUMP_MORE static void dump_state_and_upload(void); #endif +#if !defined(CONFIG_TARGET_LOCALE_NA) void sec_debug_check_crash_key(unsigned int code, int value) { static bool volup_p; static bool voldown_p; static int loopcount; + /* In Case of GC1, + * use Tele key as Volume up, + * use Wide key as volume down. + */ +#ifdef CONFIG_MACH_GC1 + static unsigned int VOLUME_UP = 0x221; + static unsigned int VOLUME_DOWN = 0x222; + + if (system_rev < 2) { + VOLUME_UP = KEY_CAMERA_ZOOMIN; + VOLUME_DOWN = KEY_CAMERA_ZOOMOUT; + } +#else + static const unsigned int VOLUME_UP = KEY_VOLUMEUP; + static const unsigned int VOLUME_DOWN = KEY_VOLUMEDOWN; +#endif + if (!sec_debug_level.en.kernel_fault) return; @@ -607,9 +712,9 @@ void sec_debug_check_crash_key(unsigned int code, int value) * and volume up key should not be pressed */ if (value) { - if (code == KEY_VOLUMEUP) + if (code == VOLUME_UP) volup_p = true; - if (code == KEY_VOLUMEDOWN) + if (code == VOLUME_DOWN) voldown_p = true; if (!volup_p && voldown_p) { if (code == KEY_POWER) { @@ -629,14 +734,73 @@ void sec_debug_check_crash_key(unsigned int code, int value) } } } else { - if (code == KEY_VOLUMEUP) + if (code == VOLUME_UP) volup_p = false; - if (code == KEY_VOLUMEDOWN) { + if (code == VOLUME_DOWN) { loopcount = 0; voldown_p = false; } } } +#else +static struct hrtimer upload_start_timer; + +static enum hrtimer_restart force_upload_timer_func(struct hrtimer *timer) +{ + panic("Crash Key"); + + return HRTIMER_NORESTART; +} + +/* Volume UP + Volume Down = Force Upload Mode + 1. check for VOL_UP and VOL_DOWN + 2. if both key pressed start a timer with timeout period 3s + 3. if any one of two keys is released before 3s disable timer. */ +void sec_debug_check_crash_key(unsigned int code, int value) +{ + static bool vol_up, vol_down, check; + + if (!sec_debug_level.en.kernel_fault) + return; + + if ((code == KEY_VOLUMEUP) || (code == KEY_VOLUMEDOWN)) { + if (value) { + if (code == KEY_VOLUMEUP) + vol_up = true; + + if (code == KEY_VOLUMEDOWN) + vol_down = true; + + if (vol_up == true && vol_down == true) { + hrtimer_start(&upload_start_timer, + ktime_set(3, 0), + HRTIMER_MODE_REL); + check = true; + } + } else { + if (vol_up == true) + vol_up = false; + if (vol_down == true) + vol_down = false; + if (check) { + hrtimer_cancel(&upload_start_timer); + check = 0; + } + } + } +} + +static int __init upload_timer_init(void) +{ + hrtimer_init(&upload_start_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + upload_start_timer.function = force_upload_timer_func; + return 0; +} + +/* this should be initialized prior to keypad driver */ +early_initcall(upload_timer_init); + +#endif static struct notifier_block nb_reboot_block = { .notifier_call = sec_debug_normal_reboot_handler @@ -719,7 +883,8 @@ void __sec_debug_task_log(int cpu, struct task_struct *task) { unsigned i; - i = atomic_inc_return(&task_log_idx[cpu]) & (SCHED_LOG_MAX - 1); + i = atomic_inc_return(&task_log_idx[cpu]) & + (ARRAY_SIZE(psec_debug_log->task[0]) - 1); psec_debug_log->task[cpu][i].time = cpu_clock(cpu); strcpy(psec_debug_log->task[cpu][i].comm, task->comm); psec_debug_log->task[cpu][i].pid = task->pid; @@ -730,7 +895,8 @@ void __sec_debug_irq_log(unsigned int irq, void *fn, int en) int cpu = raw_smp_processor_id(); unsigned i; - i = atomic_inc_return(&irq_log_idx[cpu]) & (SCHED_LOG_MAX - 1); + i = atomic_inc_return(&irq_log_idx[cpu]) & + (ARRAY_SIZE(psec_debug_log->irq[0]) - 1); psec_debug_log->irq[cpu][i].time = cpu_clock(cpu); psec_debug_log->irq[cpu][i].irq = irq; psec_debug_log->irq[cpu][i].fn = (void *)fn; @@ -743,13 +909,28 @@ void __sec_debug_work_log(struct worker *worker, int cpu = raw_smp_processor_id(); unsigned i; - i = atomic_inc_return(&work_log_idx[cpu]) & (SCHED_LOG_MAX - 1); + i = atomic_inc_return(&work_log_idx[cpu]) & + (ARRAY_SIZE(psec_debug_log->work[0]) - 1); psec_debug_log->work[cpu][i].time = cpu_clock(cpu); psec_debug_log->work[cpu][i].worker = worker; psec_debug_log->work[cpu][i].work = work; psec_debug_log->work[cpu][i].f = f; } +void __sec_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en) +{ + int cpu = raw_smp_processor_id(); + unsigned i; + + i = atomic_inc_return(&hrtimer_log_idx[cpu]) & + (ARRAY_SIZE(psec_debug_log->hrtimers[0]) - 1); + psec_debug_log->hrtimers[cpu][i].time = cpu_clock(cpu); + psec_debug_log->hrtimers[cpu][i].timer = timer; + psec_debug_log->hrtimers[cpu][i].fn = fn; + psec_debug_log->hrtimers[cpu][i].en = en; +} + #ifdef CONFIG_SEC_DEBUG_IRQ_EXIT_LOG void sec_debug_irq_last_exit_log(void) { @@ -783,14 +964,6 @@ void sec_debug_aux_log(int idx, char *fmt, ...) strncpy((*gExcpAuxLogPtr).CpuClockLog[i].log, buf, AUX_LOG_LENGTH); break; - case SEC_DEBUG_AUXLOG_LOGBUF_LOCK_CHANGE: - i = atomic_inc_return(&gExcpAuxLogBufLockLogIdx) - & (AUX_LOG_LOGBUF_LOCK_MAX - 1); - (*gExcpAuxLogPtr).LogBufLockLog[i].time = cpu_clock(cpu); - (*gExcpAuxLogPtr).LogBufLockLog[i].cpu = cpu; - strncpy((*gExcpAuxLogPtr).LogBufLockLog[i].log, - buf, AUX_LOG_LENGTH); - break; default: break; } @@ -981,7 +1154,7 @@ static int __init sec_debug_user_fault_init(void) { struct proc_dir_entry *entry; - entry = proc_create("user_fault", S_IWUGO, NULL, + entry = proc_create("user_fault", S_IWUSR | S_IWGRP, NULL, &sec_user_fault_proc_fops); if (!entry) return -ENOMEM; @@ -999,6 +1172,7 @@ int sec_debug_magic_init(void) } pr_info("%s: success reserving magic code area\n", __func__); + return 0; } diff --git a/arch/arm/mach-exynos/sec_log.c b/arch/arm/mach-exynos/sec_log.c index b55e7da..61e73af 100644 --- a/arch/arm/mach-exynos/sec_log.c +++ b/arch/arm/mach-exynos/sec_log.c @@ -105,6 +105,31 @@ out: __setup("sec_log=", sec_log_setup); +#ifdef CONFIG_CORESIGHT_ETM +static int __init sec_etb_setup(char *str) +{ + unsigned size = memparse(str, &str); + unsigned long base = 0; + + /* If we encounter any problem parsing str ... */ + if (!size || size != roundup_pow_of_two(size) || *str != '@' + || kstrtoul(str + 1, 0, &base)) + goto out; + + if (reserve_bootmem(base, size, BOOTMEM_EXCLUSIVE)) { + pr_err("%s: failed reserving size %d " + "at base 0x%lx\n", __func__, size, base); + goto out; + } + + return 1; +out: + return 0; +} + +__setup("sec_etb=", sec_etb_setup); +#endif + #ifdef CONFIG_SEC_LOG_LAST_KMSG static void __init sec_log_save_old(void) { diff --git a/arch/arm/mach-exynos/sec_thermistor.c b/arch/arm/mach-exynos/sec_thermistor.c index 2ae7ef3..a196abf 100644 --- a/arch/arm/mach-exynos/sec_thermistor.c +++ b/arch/arm/mach-exynos/sec_thermistor.c @@ -31,6 +31,13 @@ struct sec_therm_info { int curr_temp_adc; }; +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) +static void notify_change_of_temperature(struct sec_therm_info *info); +int siopLevellimit; +EXPORT_SYMBOL(siopLevellimit); +#endif + static ssize_t sec_therm_show_temperature(struct device *dev, struct device_attribute *attr, char *buf) @@ -49,12 +56,44 @@ static ssize_t sec_therm_show_temp_adc(struct device *dev, return sprintf(buf, "%d\n", info->curr_temp_adc); } +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) +static ssize_t sec_therm_show_sioplevel(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", siopLevellimit); +} + +static ssize_t sec_therm_store_sioplevel(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t n) +{ + unsigned int val; + struct sec_therm_info *info = dev_get_drvdata(dev); + + if (sscanf(buf, "%u", &val) == 1) + siopLevellimit = val; + + notify_change_of_temperature(info); + + return n; +} + +static DEVICE_ATTR(sioplevel, S_IWUSR | S_IRUGO, sec_therm_show_sioplevel, \ + sec_therm_store_sioplevel); +#endif + static DEVICE_ATTR(temperature, S_IRUGO, sec_therm_show_temperature, NULL); static DEVICE_ATTR(temp_adc, S_IRUGO, sec_therm_show_temp_adc, NULL); static struct attribute *sec_therm_attributes[] = { &dev_attr_temperature.attr, &dev_attr_temp_adc.attr, +#if defined(CONFIG_MACH_C1_KOR_SKT) || defined(CONFIG_MACH_C1_KOR_KT) || \ + defined(CONFIG_MACH_C1_KOR_LGT) + &dev_attr_sioplevel.attr, +#endif NULL }; @@ -141,6 +180,7 @@ static void notify_change_of_temperature(struct sec_therm_info *info) if (info->pdata->get_siop_level) siop_level = info->pdata->get_siop_level(info->curr_temperature); + if (siop_level >= 0) { snprintf(siop_buf, sizeof(siop_buf), "SIOP_LEVEL=%d", siop_level); diff --git a/arch/arm/mach-exynos/secmem-allocdev.c b/arch/arm/mach-exynos/secmem-allocdev.c index 1e68e9c..cab2bc5 100644 --- a/arch/arm/mach-exynos/secmem-allocdev.c +++ b/arch/arm/mach-exynos/secmem-allocdev.c @@ -223,14 +223,13 @@ static long secmem_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return -EFAULT; } - region.virt_addr = kmalloc(region.len, GFP_KERNEL | GFP_DMA); - if (!region.virt_addr) { - printk(KERN_ERR "%s: Get memory address failed. [size : %ld]\n", __func__, region.len); - return -EFAULT; - } - region.phys_addr = virt_to_phys(region.virt_addr); + pr_info("SECMEM_IOC_GET_ADDR: size:%lu\n", region.len); - dma_map_single(secmem.this_device, region.virt_addr, region.len, DMA_TO_DEVICE); + region.virt_addr = dma_alloc_coherent(NULL, region.len, + ®ion.phys_addr, GFP_KERNEL); + if (!region.virt_addr) + panic("SECMEM_IOC_GET_ADDR: dma_alloc_coherent failed! " + "size=%lu\n", region.len); if (copy_to_user((void __user *)arg, ®ion, sizeof(struct secmem_region))) @@ -245,12 +244,14 @@ static long secmem_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct secmem_region))) return -EFAULT; - if (!region.virt_addr) { - printk(KERN_ERR "Get secmem address error. [address : %x]\n", (uint32_t)region.virt_addr); - return -EFAULT; - } + if (!region.virt_addr) + panic("SECMEM_IOC_RELEASE_ADDR: Get secmem address error" + " [address : %x]\n", (uint32_t)region.virt_addr); + + pr_info("SECMEM_IOC_RELEASE_ADDR: size:%lu\n", region.len); - kfree(region.virt_addr); + dma_free_coherent(NULL, region.len, region.virt_addr, + region.phys_addr); break; } diff --git a/arch/arm/mach-exynos/setup-fb-s5p.c b/arch/arm/mach-exynos/setup-fb-s5p.c index 314e21a..6bb839f 100644 --- a/arch/arm/mach-exynos/setup-fb-s5p.c +++ b/arch/arm/mach-exynos/setup-fb-s5p.c @@ -31,7 +31,11 @@ #include <plat/gpio-cfg.h> #include <plat/cpu.h> #include <plat/clock-clksrc.h> +#if defined(CONFIG_S5P_DSIM_SWITCHABLE_DUAL_LCD) +#include <../../../drivers/video/samsung_duallcd/s3cfb.h> +#else #include <../../../drivers/video/samsung/s3cfb.h> /* should be fixed */ +#endif struct platform_device; /* don't need the contents */ @@ -668,9 +672,9 @@ int s3cfb_mdnie_pwm_clk_on(void) clk_set_rate(sclk, rate); printk(KERN_INFO "set mdnie_pwm sclk rate to %d\n", rate); clk_set_parent(sclk_pre, mout_mpll); - rate = clk_round_rate(sclk_pre, 24000000); + rate = clk_round_rate(sclk_pre, 22000000); if (!rate) - rate = 24000000; + rate = 22000000; clk_set_rate(sclk_pre, rate); #elif defined(CONFIG_FB_S5P_S6F1202A) if (soc_is_exynos4210()) @@ -745,24 +749,29 @@ unsigned int get_clk_rate(struct platform_device *pdev, struct clk *sclk) div = DIV_ROUND_CLOSEST(src_clk, vclk); - vclk_limit = (40 * - (timing->h_bp + timing->h_fp + timing->h_sw + lcd->width) * - (timing->v_bp + timing->v_fp + timing->v_sw + lcd->height)); + if (lcd->freq_limit) { + vclk_limit = (lcd->freq_limit * + (timing->h_bp + timing->h_fp + timing->h_sw + lcd->width) * + (timing->v_bp + timing->v_fp + timing->v_sw + lcd->height)); - div_limit = DIV_ROUND_CLOSEST(src_clk, vclk_limit); + div_limit = DIV_ROUND_CLOSEST(src_clk, vclk_limit); - fimd_div = gcd(div, div_limit); + fimd_div = gcd(div, div_limit); -#if defined(CONFIG_MACH_MIDAS) && defined(CONFIG_FB_S5P_S6E8AA0) && !defined(CONFIG_S6E8AA0_AMS529HA01) - div /= fimd_div; -#endif + div /= fimd_div; + } if (!div) { dev_err(&pdev->dev, "div(%d) should be non-zero\n", div); div = 1; } else if (div > 16) { dev_err(&pdev->dev, "div(%d) max should be 16\n", div); - div = 16; + for (fimd_div = 2; fimd_div < div; div++) { + if (div%fimd_div == 0) + break; + } + div /= fimd_div; + div = (div > 16) ? 16 : div; } rate = src_clk / div; diff --git a/arch/arm/mach-exynos/setup-fimc0.c b/arch/arm/mach-exynos/setup-fimc0.c index e95adcb..975412c 100644 --- a/arch/arm/mach-exynos/setup-fimc0.c +++ b/arch/arm/mach-exynos/setup-fimc0.c @@ -28,27 +28,41 @@ struct platform_device; /* don't need the contents */ void s3c_fimc0_cfg_gpio(struct platform_device *pdev) { -#if defined(CONFIG_MACH_SMDK4212) || defined(CONFIG_MACH_SMDK4210) +#if defined(CONFIG_MACH_SMDK4212) || defined(CONFIG_MACH_SMDK4210) \ + || defined(CONFIG_VIDEO_S5K5BBGX) if (soc_is_exynos4210()) { /* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */ - s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, S3C_GPIO_SFN(2)); - /* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */ - s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 5, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ0(0), 8, + S3C_GPIO_SFN(2)); + /* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), + * FIELD */ + s3c_gpio_cfgrange_nopull(EXYNOS4210_GPJ1(0), 5, + S3C_GPIO_SFN(2)); +#if !defined(CONFIG_MACH_P8LTE) || !defined(CONFIG_VIDEO_S5K5BBGX) /* CAM B port(b0011) : DATA[0-7] */ - s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, S3C_GPIO_SFN(3)); + s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, + S3C_GPIO_SFN(3)); /* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLKOUT */ - s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, S3C_GPIO_SFN(3)); + s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, + S3C_GPIO_SFN(3)); +#endif } else { /* CAM A port(b0010) : PCLK, VSYNC, HREF, DATA[0-4] */ - s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ0(0), 8, S3C_GPIO_SFN(2)); - /* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), FIELD */ - s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ1(0), 5, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ0(0), 8, + S3C_GPIO_SFN(2)); + /* CAM A port(b0010) : DATA[5-7], CLKOUT(MIPI CAM also), + * FIELD */ + s3c_gpio_cfgrange_nopull(EXYNOS4212_GPJ1(0), 5, + S3C_GPIO_SFN(2)); /* CAM B port(b0011) : PCLK, DATA[0-6] */ - s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM0(0), 8, S3C_GPIO_SFN(3)); + s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM0(0), 8, + S3C_GPIO_SFN(3)); /* CAM B port(b0011) : FIELD, DATA[7]*/ - s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM1(0), 2, S3C_GPIO_SFN(3)); + s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM1(0), 2, + S3C_GPIO_SFN(3)); /* CAM B port(b0011) : VSYNC, HREF, CLKOUT*/ - s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM2(0), 3, S3C_GPIO_SFN(3)); + s3c_gpio_cfgrange_nopull(EXYNOS4212_GPM2(0), 3, + S3C_GPIO_SFN(3)); } /* note : driver strength to max is unnecessary */ #elif defined(CONFIG_MACH_PX) @@ -60,11 +74,13 @@ void s3c_fimc0_cfg_gpio(struct platform_device *pdev) s3c_gpio_cfgpin(EXYNOS4210_GPJ1(3), S3C_GPIO_INPUT); s3c_gpio_setpull(EXYNOS4210_GPJ1(3), S3C_GPIO_PULL_DOWN); +#if !defined(CONFIG_MACH_P8LTE) /* CAM B port(b0011) : DATA[0-7] */ s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE1(0), 8, S3C_GPIO_SFN(3)); /* CAM B port(b0011) : PCLK, VSYNC, HREF, FIELD, CLKOUT */ s3c_gpio_cfgrange_nopull(EXYNOS4210_GPE0(0), 5, S3C_GPIO_SFN(3)); #endif +#endif } int s3c_fimc_clk_on(struct platform_device *pdev, struct clk **clk) diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c index 5e81e78..234f21f 100644 --- a/arch/arm/mach-exynos/setup-i2c4.c +++ b/arch/arm/mach-exynos/setup-i2c4.c @@ -19,6 +19,10 @@ struct platform_device; /* don't need the contents */ void s3c_i2c4_cfg_gpio(struct platform_device *dev) { +#if defined(CONFIG_MACH_U1_NA_USCC) +s3c_gpio_cfgall_range(EXYNOS4_GPB(0), 1, + S3C_GPIO_OUTPUT, S3C_GPIO_PULL_NONE); +#else if (soc_is_exynos4210()) s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2, S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); @@ -28,4 +32,5 @@ void s3c_i2c4_cfg_gpio(struct platform_device *dev) else s3c_gpio_cfgall_range(EXYNOS5_GPA2(0), 2, S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); +#endif } diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c index 2163904..b26235b 100644 --- a/arch/arm/mach-exynos/setup-keypad.c +++ b/arch/arm/mach-exynos/setup-keypad.c @@ -17,6 +17,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) { /* Keypads can be of various combinations, Just making sure */ +#if defined(CONFIG_MACH_M0_GRANDECTC) || defined(CONFIG_MACH_IRON) + s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(EXYNOS4_GPX2(4), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(EXYNOS4_GPX2(4), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(EXYNOS4_GPX3(0), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(EXYNOS4_GPX3(0), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(EXYNOS4_GPX3(3), 2, S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(EXYNOS4_GPL2(3), 5, S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE); +#else if (rows > 8) { /* Set all the necessary GPX2 pins: KP_ROW[0~7] */ s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, @@ -33,4 +43,5 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */ s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3)); +#endif } diff --git a/arch/arm/mach-exynos/setup-mshci-gpio.c b/arch/arm/mach-exynos/setup-mshci-gpio.c index db7d86a..7984a5d 100644 --- a/arch/arm/mach-exynos/setup-mshci-gpio.c +++ b/arch/arm/mach-exynos/setup-mshci-gpio.c @@ -87,10 +87,18 @@ void exynos4_setup_mshci_cfg_ddr(struct platform_device *dev, int ddr) #elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ) __raw_writel(0x01, DIV_FSYS3); #else +#ifdef CONFIG_EXYNOS4_MSHC_SUPPORT_PQPRIME_EPLL + if (soc_is_exynos4412() && + (samsung_rev() >= EXYNOS4412_REV_2_0)) + /* This is code for support PegasusQ Prime dynamically. + * PegasusQ Prime use EPLL rather than MPLL */ + __raw_writel(0x00, DIV_FSYS3); + else +#endif /* ifdef CONFIG_EXYNOS4_MSHC_SUPPORT_PQPRIME_EPLL */ if ((soc_is_exynos4412() || soc_is_exynos4212()) && - samsung_rev() >= EXYNOS4412_REV_1_0) { + samsung_rev() >= EXYNOS4412_REV_1_0) __raw_writel(0x1, DIV_FSYS3); - } else + else __raw_writel(0x05, DIV_FSYS3); #endif } else { @@ -99,8 +107,16 @@ void exynos4_setup_mshci_cfg_ddr(struct platform_device *dev, int ddr) #elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ) __raw_writel(0x03, DIV_FSYS3); #else +#ifdef CONFIG_EXYNOS4_MSHC_SUPPORT_PQPRIME_EPLL + if (soc_is_exynos4412() && + (samsung_rev() >= EXYNOS4412_REV_2_0)) + /* This is code for support PegasusQ Prime dynamically. + * PegasusQ Prime use EPLL rather than MPLL */ + __raw_writel(0x01, DIV_FSYS3); + else +#endif /* ifdef CONFIG_EXYNOS4_MSHC_SUPPORT_PQPRIME_EPLL */ if ((soc_is_exynos4412() || soc_is_exynos4212()) && - samsung_rev() >= EXYNOS4412_REV_1_0) + samsung_rev() >= EXYNOS4412_REV_1_0) __raw_writel(0x3, DIV_FSYS3); else __raw_writel(0xb, DIV_FSYS3); @@ -140,8 +156,10 @@ void exynos4_setup_mshci_set_power(struct platform_device *dev, int en) if (pdata->int_power_gpio) { if (en) { -#ifdef CONFIG_MACH_Q1_BD +#if defined(CONFIG_MACH_Q1_BD) mdelay(20); +#elif defined(CONFIG_MACH_PX) + mdelay(10); #endif /*CMD/CLK*/ for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c index 09b0818..05d8ed1 100644 --- a/arch/arm/mach-exynos/setup-sdhci-gpio.c +++ b/arch/arm/mach-exynos/setup-sdhci-gpio.c @@ -96,7 +96,7 @@ void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) /* Set all the necessary GPK2[0:1] pins to special-function 2 */ for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); #elif defined(CONFIG_MACH_MIDAS) @@ -113,7 +113,7 @@ void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { /* Data pin GPK3[3:6] to special-function 3 */ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); #elif defined(CONFIG_MACH_MIDAS) @@ -128,7 +128,7 @@ void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) { /* Data pin GPK2[3:6] to special-function 2 */ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); #elif defined(CONFIG_MACH_MIDAS) @@ -158,12 +158,16 @@ void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) /* Set all the necessary GPK3[0:1] pins to special-function 2 */ for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); -#elif defined(CONFIG_MACH_MIDAS) +#elif defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1_USA_ATT) || \ + defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); +#elif defined(CONFIG_MACH_MIDAS) + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); #elif defined(CONFIG_MACH_PX) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); @@ -180,12 +184,16 @@ void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { /* Data pin GPK3[3:6] to special-function 2 */ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); -#ifdef CONFIG_MACH_U1 +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_TRATS) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); -#elif defined(CONFIG_MACH_MIDAS) +#elif defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1_USA_ATT) || \ + defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV2); +#elif defined(CONFIG_MACH_MIDAS) + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); #elif defined(CONFIG_MACH_PX) s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c index 960028c..5b83023 100644 --- a/arch/arm/mach-exynos/setup-sdhci.c +++ b/arch/arm/mach-exynos/setup-sdhci.c @@ -56,8 +56,9 @@ void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, S3C_SDHCI_CTRL2_DFCNT_NONE | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); -#ifdef CONFIG_MACH_M0 - /* set 2ns delay for TX. This setting is just for wifi sdio i/f of +#if defined(CONFIG_MACH_M0) || defined(CONFIG_MACH_C1_USA_ATT) || \ + defined(CONFIG_MACH_T0) || defined(CONFIG_MACH_M3) + /* set 2ns delay for TX. This setting is just for wifi sdio i/f of M0 and his brother projects. */ if (pdata->pm_flags == S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME && (ios->clock >= 25 * 1000000)) { diff --git a/arch/arm/mach-exynos/setup-tvout.c b/arch/arm/mach-exynos/setup-tvout.c index 7e487f8..7948eb8 100644 --- a/arch/arm/mach-exynos/setup-tvout.c +++ b/arch/arm/mach-exynos/setup-tvout.c @@ -38,12 +38,21 @@ struct platform_device; /* don't need the contents */ void s5p_int_src_hdmi_hpd(struct platform_device *pdev) { printk(KERN_INFO "%s()\n", __func__); +#ifdef CONFIG_MACH_U1_NA_USCC + s3c_gpio_cfgpin(GPIO_HDMI_HPD , S3C_GPIO_INPUT); +#else s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0x3)); - s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE); +#endif + s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN); } void s5p_int_src_ext_hpd(struct platform_device *pdev) { +#ifdef CONFIG_MACH_U1_NA_USCC /* NC */ + printk(KERN_INFO "%s()\n", __func__); + s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN); +#else printk(KERN_INFO "%s()\n", __func__); s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0xf)); /* To avoid floating state of the HPD pin * @@ -53,6 +62,7 @@ void s5p_int_src_ext_hpd(struct platform_device *pdev) #else s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE); #endif +#endif } int s5p_hpd_read_gpio(struct platform_device *pdev) diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index bae906f..fd0b89e 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c @@ -347,16 +347,6 @@ static int exynos4_usb_phy1_resume(struct platform_device *pdev) u32 phypwr; int err; -#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) - /* HSIC LPA: reset-resume, let cp know pda active from LPA */ - /* slave wake at lpa wake ??? */ - /* 12.04.27 Move start of phy1_resume, If usb cable power on the - * host phy, EHCI resume miss the PDA_ACTVIE, then CP can't send Host - * wakeup Irq */ - if (!strcmp(pdev->name, "s5p-ehci")) - set_hsic_lpa_states(STATE_HSIC_LPA_WAKE); -#endif - if (exynos4_usb_host_phy_is_on()) { /* set to resume HSIC 0 and 1 and standard of PHY1 */ phypwr = readl(EXYNOS4_PHYPWR); @@ -372,10 +362,16 @@ static int exynos4_usb_phy1_resume(struct platform_device *pdev) } writel(phypwr, EXYNOS4_PHYPWR); if (usb_phy_control.lpa_entered) { +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \ + || defined(CONFIG_MDM_HSIC_PM) + if (!strcmp(pdev->name, "s5p-ehci")) + set_hsic_lpa_states(STATE_HSIC_LPA_WAKE); +#endif usb_phy_control.lpa_entered = 0; err = 1; - } else + } else { err = 0; + } } else { phypwr = readl(EXYNOS4_PHYPWR); /* set to normal HSIC 0 and 1 of PHY1 */ @@ -431,6 +427,11 @@ static int exynos4_usb_phy1_resume(struct platform_device *pdev) | EXYNOS4212_PHY1_SWRST_MASK); writel(rstcon, EXYNOS4_RSTCON); } +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \ + || defined(CONFIG_MDM_HSIC_PM) + if (!strcmp(pdev->name, "s5p-ehci")) + set_hsic_lpa_states(STATE_HSIC_LPA_WAKE); +#endif usb_phy_control.lpa_entered = 0; err = 1; } @@ -1008,6 +1009,11 @@ int exynos4_check_usb_op(void) unsigned long flags; int ret; +#if defined(CONFIG_MDM_HSIC_PM) + /* if it is normal boot, block lpa till modem boot */ + if (set_hsic_lpa_states(STATE_HSIC_LPA_CHECK)) + return 1; +#endif ret = clk_enable(phy_clk); if (ret) return 0; @@ -1045,7 +1051,8 @@ int exynos4_check_usb_op(void) if (phypwr & (PHY1_STD_FORCE_SUSPEND | EXYNOS4212_HSIC0_FORCE_SUSPEND | EXYNOS4212_HSIC1_FORCE_SUSPEND)) { -#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \ + || defined(CONFIG_MDM_HSIC_PM) /* HSIC LPA: LPA USB phy retention reume call the usb * reset resume, so we should let CP to HSIC L3 mode. */ set_hsic_lpa_states(STATE_HSIC_LPA_ENTER); @@ -1211,7 +1218,6 @@ int s5p_usb_phy_resume(struct platform_device *pdev, int type) if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412()) { - dev_info(&pdev->dev, "host_phy_resume\n"); #ifdef CONFIG_USB_OHCI_S5P phyclk = readl(EXYNOS4_PHYCLK); phyclk |= PHY1_COMMON_ON_N; @@ -1326,7 +1332,8 @@ int s5p_usb_phy_init(struct platform_device *pdev, int type) else if (!strcmp(pdev->name, "s5p-ohci")) set_bit(HOST_PHY_OHCI, &usb_phy_control.flags); -#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) +#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \ + || defined(CONFIG_MDM_HSIC_PM) /* HSIC LPA: Let CP know the slave wakeup from LPA wakeup */ if (!strcmp(pdev->name, "s5p-ehci")) set_hsic_lpa_states(STATE_HSIC_LPA_PHY_INIT); diff --git a/arch/arm/mach-exynos/sleep-exynos5.S b/arch/arm/mach-exynos/sleep-exynos5.S deleted file mode 100644 index 36b50c1..0000000 --- a/arch/arm/mach-exynos/sleep-exynos5.S +++ /dev/null @@ -1,137 +0,0 @@ -/* linux/arch/arm/mach-exynos/sleep-exynos5.S - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS5 power Manager (Suspend-To-RAM) support - * Based on S3C2410 sleep code by: - * Ben Dooks, (c) 2004 Simtec Electronics - * - * Based on PXA/SA1100 sleep code by: - * Nicolas Pitre, (c) 2002 Monta Vista Software Inc - * Cliff Brake, (c) 2001 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/memory.h> -#include <mach/smc.h> - - .text - - /* - * s3c_cpu_save - * - * entry: - * r1 = v:p offset - */ - -ENTRY(s3c_cpu_save) - - stmfd sp!, { r3 - r12, lr } - - adr r0, sleep_save_misc - -#ifdef CONFIG_ARM_TRUSTZONE - mrc p15, 0, r2, c1, c0, 1 @ read aux control register - str r2, [r0], #4 -#endif - mrc p15, 1, r2, c9, c0, 2 @ read l2 control register - str r2, [r0], #4 - mrc p15, 1, r2, c15, c0, 3 @ read l2 prefetch register - str r2, [r0], #4 - - ldr r3, =resume_with_mmu - bl cpu_suspend - - bl exynos5_cpu_suspend - - /* Restore original sp */ - mov r0, sp - add r0, r0, #4 - ldr sp, [r0] - - mov r0, #0 - b early_wakeup - -resume_with_mmu: - - adr r4, sleep_save_misc - -#ifdef CONFIG_ARM_TRUSTZONE - mov r3, #0 - - ldr r0, =SMC_CMD_REG - ldr r1, =SMC_REG_ID_CP15(1, 0, 0, 1) @ aux control register - ldr r2, [r4], #4 - smc 0 - ldr r0, =SMC_CMD_REG - ldr r1, =SMC_REG_ID_CP15(9, 1, 0, 2) @ L2 control register - ldr r2, [r4], #4 - smc 0 - ldr r0, =SMC_CMD_REG - ldr r1, =SMC_REG_ID_CP15(15, 1, 0, 3) @ L2 prefetch register - ldr r2, [r4], #4 - smc 0 -#else - ldr r2, [r4], #4 - mcr p15, 1, r2, c9, c0, 2 @ L2 control register - ldr r2, [r4], #4 - mcr p15, 1, r2, c15, c0, 3 @ L2 prefetch register -#endif - mov r0, #1 -early_wakeup: - - ldmfd sp!, { r3 - r12, pc } - - .ltorg - - /* - * sleep magic, to allow the bootloader to check for an valid - * image to resume to. Must be the first word before the - * s3c_cpu_resume entry. - */ - - .word 0x2bedf00d - -sleep_save_misc: - .long 0 - .long 0 - .long 0 - - /* - * s3c_cpu_resume - * - * resume code entry for bootloader to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) - */ - -ENTRY(s3c_cpu_resume) - /* - * Set for L2 Cache latency - */ - mcr p15, 1, r0, c9, c0, 2 - ldr r1, =0x3ff - bic r0, r0, r1 - ldr r1, =0x2a2 - orr r0, r0, r1 - mrc p15, 1, r0, c9, c0, 2 - - b cpu_resume diff --git a/arch/arm/mach-exynos/stand-hotplug.c b/arch/arm/mach-exynos/stand-hotplug.c index 2a83c72..1f3f59c 100644 --- a/arch/arm/mach-exynos/stand-hotplug.c +++ b/arch/arm/mach-exynos/stand-hotplug.c @@ -48,7 +48,8 @@ #endif -#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_PX) +#if defined(CONFIG_MACH_U1) || defined(CONFIG_MACH_PX) || \ + defined(CONFIG_MACH_TRATS) #define TRANS_LOAD_H0 30 #define TRANS_LOAD_L1 20 #define TRANS_LOAD_H1 100 @@ -58,24 +59,25 @@ #define CHECK_DELAY_OFF (.5*HZ) #endif -#if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_MACH_SMDK4X12) -#ifdef CONFIG_MACH_S2PLUS -#define TRANS_LOAD_H0 30 -#define TRANS_LOAD_L1 20 -#define TRANS_LOAD_H1 100 -#else +#if defined(CONFIG_MACH_MIDAS) || defined(CONFIG_MACH_SMDK4X12) \ + || defined(CONFIG_MACH_SLP_PQ) #define TRANS_LOAD_H0 20 #define TRANS_LOAD_L1 10 #define TRANS_LOAD_H1 35 -#endif #define TRANS_LOAD_L2 15 #define TRANS_LOAD_H2 45 #define TRANS_LOAD_L3 20 #define BOOT_DELAY 60 + +#if defined(CONFIG_MACH_SLP_PQ) +#define CHECK_DELAY_ON (.3*HZ * 4) +#define CHECK_DELAY_OFF (.3*HZ) +#else #define CHECK_DELAY_ON (.5*HZ * 4) #define CHECK_DELAY_OFF (.5*HZ) #endif +#endif #define TRANS_RQ 2 #define TRANS_LOAD_RQ 20 diff --git a/arch/arm/mach-exynos/subsystem_restart.c b/arch/arm/mach-exynos/subsystem_restart.c index 0a76ab3..a68804f 100644 --- a/arch/arm/mach-exynos/subsystem_restart.c +++ b/arch/arm/mach-exynos/subsystem_restart.c @@ -14,31 +14,16 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/uaccess.h> +#include <linux/slab.h> #include <linux/module.h> -#include <linux/fs.h> -#include <linux/proc_fs.h> #include <linux/delay.h> #include <linux/list.h> #include <linux/io.h> -#include <linux/kthread.h> #include <linux/time.h> #include <linux/wakelock.h> #include <linux/suspend.h> - -#include <asm/current.h> -#ifndef CONFIG_ARCH_EXYNOS -#include <mach/peripheral-loader.h> -#include <mach/scm.h> -#include <mach/socinfo.h> -#endif -#include <mach/subsystem_notif.h> #include <mach/subsystem_restart.h> -#ifndef CONFIG_ARCH_EXYNOS -#include "smd_private.h" -#endif - struct subsys_soc_restart_order { const char * const *subsystem_list; int count; @@ -63,7 +48,7 @@ struct restart_log { }; static int restart_level; -static int enable_ramdumps = 1; +static int mdm_dump = 1; struct workqueue_struct *ssr_wq; static LIST_HEAD(restart_log_list); @@ -72,130 +57,11 @@ static DEFINE_MUTEX(subsystem_list_lock); static DEFINE_MUTEX(soc_order_reg_lock); static DEFINE_MUTEX(restart_log_mutex); -/* SOC specific restart orders go here */ - -#define DEFINE_SINGLE_RESTART_ORDER(name, order) \ - static struct subsys_soc_restart_order __##name = { \ - .subsystem_list = order, \ - .count = ARRAY_SIZE(order), \ - .subsys_ptrs = {[ARRAY_SIZE(order)] = NULL} \ - }; \ - static struct subsys_soc_restart_order *name[] = { \ - &__##name, \ - } - -#ifndef CONFIG_ARCH_EXYNOS -/* MSM 8x60 restart ordering info */ -static const char * const _order_8x60_all[] = { - "external_modem", "modem", "lpass" -}; -DEFINE_SINGLE_RESTART_ORDER(orders_8x60_all, _order_8x60_all); - -static const char * const _order_8x60_modems[] = {"external_modem", "modem"}; -DEFINE_SINGLE_RESTART_ORDER(orders_8x60_modems, _order_8x60_modems); -#else /* CONFIG_ARCH_EXYNOS */ -/* MSM 8x60 restart ordering info */ -static const char * const _order_8x60_all[] = { - "external_modem", -}; -DEFINE_SINGLE_RESTART_ORDER(orders_8x60_all, _order_8x60_all); - -static const char * const _order_8x60_modems[] = {"external_modem"}; -DEFINE_SINGLE_RESTART_ORDER(orders_8x60_modems, _order_8x60_modems); -#endif - -/* MSM 8960 restart ordering info */ -static const char * const order_8960[] = {"modem", "lpass"}; - -static struct subsys_soc_restart_order restart_orders_8960_one = { - .subsystem_list = order_8960, - .count = ARRAY_SIZE(order_8960), - .subsys_ptrs = {[ARRAY_SIZE(order_8960)] = NULL} - }; - -static struct subsys_soc_restart_order *restart_orders_8960[] = { - &restart_orders_8960_one, -}; /* These will be assigned to one of the sets above after * runtime SoC identification. */ -static struct subsys_soc_restart_order **restart_orders; -static int n_restart_orders; - -module_param(enable_ramdumps, int, S_IRUGO | S_IWUSR); - -static struct subsys_soc_restart_order *_update_restart_order( - struct subsys_data *subsys); - -#ifndef CONFIG_ARCH_EXYNOS -int get_restart_level() -{ - return restart_level; -} -EXPORT_SYMBOL(get_restart_level); - -static void restart_level_changed(void) -{ - struct subsys_data *subsys; - - if (cpu_is_msm8x60() && restart_level == RESET_SUBSYS_COUPLED) { - restart_orders = orders_8x60_all; - n_restart_orders = ARRAY_SIZE(orders_8x60_all); - } - - if (cpu_is_msm8x60() && restart_level == RESET_SUBSYS_MIXED) { - restart_orders = orders_8x60_modems; - n_restart_orders = ARRAY_SIZE(orders_8x60_modems); - } - - mutex_lock(&subsystem_list_lock); - list_for_each_entry(subsys, &subsystem_list, list) - subsys->restart_order = _update_restart_order(subsys); - mutex_unlock(&subsystem_list_lock); -} - -static int restart_level_set(const char *val, struct kernel_param *kp) -{ - int ret; - int old_val = restart_level; - - if (cpu_is_msm9615()) { - pr_err("Only Phase 1 subsystem restart is supported\n"); - return -EINVAL; - } - - ret = param_set_int(val, kp); - if (ret) - return ret; - - switch (restart_level) { - - case RESET_SOC: - case RESET_SUBSYS_COUPLED: - case RESET_SUBSYS_INDEPENDENT: - pr_info("Phase %d behavior activated.\n", restart_level); - break; - - case RESET_SUBSYS_MIXED: - pr_info("Phase 2+ behavior activated.\n"); - break; - - default: - restart_level = old_val; - return -EINVAL; - break; +module_param(mdm_dump, int, S_IRUGO | S_IWUSR); - } - - if (restart_level != old_val) - restart_level_changed(); - - return 0; -} - -module_param_call(restart_level, restart_level_set, param_get_int, - &restart_level, 0644); -#endif static struct subsys_data *_find_subsystem(const char *subsys_name) { struct subsys_data *subsys; @@ -212,118 +78,18 @@ static struct subsys_data *_find_subsystem(const char *subsys_name) return NULL; } -static struct subsys_soc_restart_order *_update_restart_order( - struct subsys_data *subsys) -{ - int i, j; - - if (!subsys) - return NULL; - - if (!subsys->name) - return NULL; - - mutex_lock(&soc_order_reg_lock); - for (j = 0; j < n_restart_orders; j++) { - for (i = 0; i < restart_orders[j]->count; i++) - if (!strncmp(restart_orders[j]->subsystem_list[i], - subsys->name, SUBSYS_NAME_MAX_LENGTH)) { - - restart_orders[j]->subsys_ptrs[i] = - subsys; - mutex_unlock(&soc_order_reg_lock); - return restart_orders[j]; - } - } - - mutex_unlock(&soc_order_reg_lock); - - return NULL; -} - -static void _send_notification_to_order(struct subsys_data - **restart_list, int count, - enum subsys_notif_type notif_type) -{ - int i; - - for (i = 0; i < count; i++) - if (restart_list[i]) - subsys_notif_queue_notification( - restart_list[i]->notif_handle, notif_type); -} - static int max_restarts; module_param(max_restarts, int, 0644); static long max_history_time = 3600; module_param(max_history_time, long, 0644); -static void do_epoch_check(struct subsys_data *subsys) -{ - int n = 0; - struct timeval *time_first = NULL, *curr_time; - struct restart_log *r_log, *temp; - static int max_restarts_check; - static long max_history_time_check; - - mutex_lock(&restart_log_mutex); - - max_restarts_check = max_restarts; - max_history_time_check = max_history_time; - - /* Check if epoch checking is enabled */ - if (!max_restarts_check) - goto out; - - r_log = kmalloc(sizeof(struct restart_log), GFP_KERNEL); - if (!r_log) - goto out; - r_log->subsys = subsys; - do_gettimeofday(&r_log->time); - curr_time = &r_log->time; - INIT_LIST_HEAD(&r_log->list); - - list_add_tail(&r_log->list, &restart_log_list); - - list_for_each_entry_safe(r_log, temp, &restart_log_list, list) { - - if ((curr_time->tv_sec - r_log->time.tv_sec) > - max_history_time_check) { - - pr_debug("Deleted node with restart_time = %ld\n", - r_log->time.tv_sec); - list_del(&r_log->list); - kfree(r_log); - continue; - } - if (!n) { - time_first = &r_log->time; - pr_debug("Time_first: %ld\n", time_first->tv_sec); - } - n++; - pr_debug("Restart_time: %ld\n", r_log->time.tv_sec); - } - - if (time_first && n >= max_restarts_check) { - if ((curr_time->tv_sec - time_first->tv_sec) < - max_history_time_check) - panic("Subsystems have crashed %d times in less than " - "%ld seconds!", max_restarts_check, - max_history_time_check); - } - -out: - mutex_unlock(&restart_log_mutex); -} - static void subsystem_restart_wq_func(struct work_struct *work) { struct restart_wq_data *r_work = container_of(work, struct restart_wq_data, work); struct subsys_data **restart_list; struct subsys_data *subsys = r_work->subsys; - struct subsys_soc_restart_order *soc_restart_order = NULL; struct mutex *powerup_lock; struct mutex *shutdown_lock; @@ -331,26 +97,14 @@ static void subsystem_restart_wq_func(struct work_struct *work) int i; int restart_list_count = 0; - if (r_work->coupled) - soc_restart_order = subsys->restart_order; - /* It's OK to not take the registration lock at this point. * This is because the subsystem list inside the relevant * restart order is not being traversed. */ - if (!soc_restart_order) { - pr_info("i am here\n"); - restart_list = subsys->single_restart_list; - restart_list_count = 1; - powerup_lock = &subsys->powerup_lock; - shutdown_lock = &subsys->shutdown_lock; - } else { - pr_info("i am here, 2nd\n"); - restart_list = soc_restart_order->subsys_ptrs; - restart_list_count = soc_restart_order->count; - powerup_lock = &soc_restart_order->powerup_lock; - shutdown_lock = &soc_restart_order->shutdown_lock; - } + restart_list = subsys->single_restart_list; + restart_list_count = 1; + powerup_lock = &subsys->powerup_lock; + shutdown_lock = &subsys->shutdown_lock; pr_info("subsys[%p], powerup lock[%p], shutdown_lock[%p]\n", subsys, powerup_lock, shutdown_lock); @@ -373,8 +127,6 @@ static void subsystem_restart_wq_func(struct work_struct *work) panic("%s[%p]: Subsystem died during powerup!", __func__, current); - do_epoch_check(subsys); - /* Now it is necessary to take the registration lock. This is because * the subsystem list in the SoC restart order will be traversed * and it shouldn't be changed until _this_ restart sequence completes. @@ -384,10 +136,6 @@ static void subsystem_restart_wq_func(struct work_struct *work) pr_info("[%p]: Starting restart sequence for %s\n", current, r_work->subsys->name); - _send_notification_to_order(restart_list, - restart_list_count, - SUBSYS_BEFORE_SHUTDOWN); - for (i = 0; i < restart_list_count; i++) { if (!restart_list[i]) @@ -401,9 +149,6 @@ static void subsystem_restart_wq_func(struct work_struct *work) __func__, current, restart_list[i]->name); } - _send_notification_to_order(restart_list, restart_list_count, - SUBSYS_AFTER_SHUTDOWN); - /* Now that we've finished shutting down these subsystems, release the * shutdown lock. If a subsystem restart request comes in for a * subsystem in _this_ restart order after the unlock below, and @@ -417,16 +162,11 @@ static void subsystem_restart_wq_func(struct work_struct *work) continue; if (restart_list[i]->ramdump) - if (restart_list[i]->ramdump(enable_ramdumps, - subsys) < 0) + if (restart_list[i]->ramdump(mdm_dump, subsys) < 0) pr_warn("%s[%p]: Ramdump failed.\n", restart_list[i]->name, current); } - _send_notification_to_order(restart_list, - restart_list_count, - SUBSYS_BEFORE_POWERUP); - for (i = restart_list_count - 1; i >= 0; i--) { if (!restart_list[i]) @@ -440,10 +180,6 @@ static void subsystem_restart_wq_func(struct work_struct *work) current, restart_list[i]->name); } - _send_notification_to_order(restart_list, - restart_list_count, - SUBSYS_AFTER_POWERUP); - pr_info("[%p]: Restart sequence for %s completed.\n", current, r_work->subsys->name); @@ -457,6 +193,7 @@ out: wake_unlock(&r_work->ssr_wake_lock); wake_lock_destroy(&r_work->ssr_wake_lock); kfree(r_work); + subsys->ongoing = false; } int subsystem_restart(const char *subsys_name) @@ -483,59 +220,15 @@ int subsystem_restart(const char *subsys_name) return -EINVAL; } -#ifndef CONFIG_ARCH_EXYNOS - if (restart_level != RESET_SOC) { - data = kzalloc(sizeof(struct restart_wq_data), GFP_KERNEL); - if (!data) { - restart_level = RESET_SOC; - pr_warn("Failed to alloc restart data. Resetting.\n"); - } else { - if (restart_level == RESET_SUBSYS_COUPLED || - restart_level == RESET_SUBSYS_MIXED) - data->coupled = 1; - else - data->coupled = 0; - - data->subsys = subsys; - } + if (subsys->ongoing) { + pr_warn("subsys-restart: already requested, return busy\n"); + return -EBUSY; } - switch (restart_level) { - - case RESET_SUBSYS_COUPLED: - case RESET_SUBSYS_MIXED: - case RESET_SUBSYS_INDEPENDENT: - pr_debug("Restarting %s [level=%d]!\n", subsys_name, - restart_level); + subsys->ongoing = true; - snprintf(data->wakelockname, sizeof(data->wakelockname), - "ssr(%s)", subsys_name); - wake_lock_init(&data->ssr_wake_lock, WAKE_LOCK_SUSPEND, - data->wakelockname); - wake_lock(&data->ssr_wake_lock); - - INIT_WORK(&data->work, subsystem_restart_wq_func); - rc = schedule_work(&data->work); - - if (rc < 0) - panic("%s: Unable to schedule work to restart %s", - __func__, subsys->name); - break; - - case RESET_SOC: - panic("subsys-restart: Resetting the SoC - %s crashed.", - subsys->name); - break; - - default: - panic("subsys-restart: Unknown restart level!\n"); - break; - - } -#else /* CONFIG_ARCH_EXYNOS */ data = kzalloc(sizeof(struct restart_wq_data), GFP_KERNEL); if (!data) { - restart_level = RESET_SOC; pr_warn("Failed to alloc restart data. Resetting.\n"); panic("subsys-restart: Resetting the SoC - %s crashed.", subsys->name); @@ -553,11 +246,9 @@ int subsystem_restart(const char *subsys_name) INIT_WORK(&data->work, subsystem_restart_wq_func); rc = schedule_work(&data->work); - if (rc < 0) panic("%s: Unable to schedule work to restart %s", __func__, subsys->name); -#endif return 0; } EXPORT_SYMBOL(subsystem_restart); @@ -574,8 +265,6 @@ int ssr_register_subsystem(struct subsys_data *subsys) if (!subsys->powerup || !subsys->shutdown) goto err; - subsys->notif_handle = subsys_notif_add_subsys(subsys->name); - subsys->restart_order = _update_restart_order(subsys); subsys->single_restart_list[0] = subsys; mutex_init(&subsys->shutdown_lock); @@ -607,55 +296,6 @@ static struct notifier_block panic_nb = { .notifier_call = ssr_panic_handler, }; -static int __init ssr_init_soc_restart_orders(void) -{ - int i; - - atomic_notifier_chain_register(&panic_notifier_list, - &panic_nb); -#ifndef CONFIG_ARCH_EXYNOS - if (cpu_is_msm8x60()) { - for (i = 0; i < ARRAY_SIZE(orders_8x60_all); i++) { - mutex_init(&orders_8x60_all[i]->powerup_lock); - mutex_init(&orders_8x60_all[i]->shutdown_lock); - } - - for (i = 0; i < ARRAY_SIZE(orders_8x60_modems); i++) { - mutex_init(&orders_8x60_modems[i]->powerup_lock); - mutex_init(&orders_8x60_modems[i]->shutdown_lock); - } - - restart_orders = orders_8x60_all; - n_restart_orders = ARRAY_SIZE(orders_8x60_all); - } - - if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm9615() || - cpu_is_apq8064()) { - restart_orders = restart_orders_8960; - n_restart_orders = ARRAY_SIZE(restart_orders_8960); - } -#else - for (i = 0; i < ARRAY_SIZE(orders_8x60_all); i++) { - mutex_init(&orders_8x60_all[i]->powerup_lock); - mutex_init(&orders_8x60_all[i]->shutdown_lock); - } - - for (i = 0; i < ARRAY_SIZE(orders_8x60_modems); i++) { - mutex_init(&orders_8x60_modems[i]->powerup_lock); - mutex_init(&orders_8x60_modems[i]->shutdown_lock); - } - - restart_orders = orders_8x60_all; - n_restart_orders = ARRAY_SIZE(orders_8x60_all); -#endif - if (restart_orders == NULL || n_restart_orders < 1) { - WARN_ON(1); - return -EINVAL; - } - - return 0; -} - static int __init subsys_restart_init(void) { int ret = 0; @@ -669,7 +309,8 @@ static int __init subsys_restart_init(void) if (!ssr_wq) panic("Couldn't allocate workqueue for subsystem restart.\n"); - ret = ssr_init_soc_restart_orders(); + atomic_notifier_chain_register(&panic_notifier_list, + &panic_nb); return ret; } diff --git a/arch/arm/mach-exynos/t0-gpio.c b/arch/arm/mach-exynos/t0-gpio.c new file mode 100644 index 0000000..0712486 --- /dev/null +++ b/arch/arm/mach-exynos/t0-gpio.c @@ -0,0 +1,1160 @@ +/* + * linux/arch/arm/mach-exynos/midas-gpio.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - GPIO setting in set board + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/serial_core.h> +#include <plat/devs.h> +#include <plat/gpio-cfg.h> +#include <plat/regs-serial.h> +#include <mach/gpio-midas.h> +#include <plat/cpu.h> +#include <mach/pmu.h> + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +/* + * T0 GPIO Init Table + * Based on HW Rev0.4 + */ +static struct gpio_init_data t0_init_gpios[] = { +#if !defined(CONFIG_MACH_T0_EUR_OPEN) && !defined(CONFIG_TARGET_LOCALE_CHN) + {EXYNOS4_GPA0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#endif +#if !defined(CONFIG_MACH_T0_CHN_CMCC) + {EXYNOS4_GPA1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#endif +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC0(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_RST */ + {EXYNOS4_GPC0(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_EN */ +#endif +#if !defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + && !defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_SPI_CLK */ +#else + {EXYNOS4_GPC1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#endif +#endif + {EXYNOS4_GPC1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC1(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_SPI_DO */ +#endif + {EXYNOS4_GPD0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_SDA_1.8V */ + {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_SCL_1.8V */ + {EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SDA_1.8V */ + {EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GSENSE_SCL_1.8V */ + + {EXYNOS4_GPX0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MCU_AP_INT_1.8V */ + {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_INT */ + {EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + {EXYNOS4_GPX0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPX0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#endif + {EXYNOS4_GPX0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + + {EXYNOS4_GPX0(7), S3C_GPIO_SFN(0xF), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* AP_PMIC_IRQ */ + + {EXYNOS4_GPX1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* V_BUS_INT */ + {EXYNOS4_GPX1(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* NFC_IRQ */ + +#if !defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPX2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* G_DET_N */ +#endif + {EXYNOS4_GPX2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MCU_AP_INT_2_1.8V */ + {EXYNOS4_GPX2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WACOM_SENSE */ + {EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FUEL_ALERT */ + {EXYNOS4_GPX2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* WLAN_HOST_WAKEUP */ + {EXYNOS4_GPX2(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_HOST_WAKEUP */ + {EXYNOS4_GPX2(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* nPower */ + +#if !defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + && !defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPX3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WPC_INT */ +#endif + {EXYNOS4_GPX3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* BT_WAKE */ + {EXYNOS4_GPX3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CP_PMU_RST */ + {EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV1}, /* PEN_PDCT_1.8V */ + + {EXYNOS4212_GPJ0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, /* WLAN_EN */ + {EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */ + {EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */ + {EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */ + {EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */ + {EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */ + + {EXYNOS4212_GPM3(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PMIC_DVS1 */ + + {EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) + {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* FM_RST */ + {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FM_SCL_1.8V */ + {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* FM_SDA_1.8V */ +#else + {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#endif + {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ + {EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#else + /* GPIO_AP2MDM_PMIC_RESET_N */ + {EXYNOS4_GPY2(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV4}, +#endif + {EXYNOS4212_GPJ1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV2}, /* CAM_MCLK */ + {EXYNOS4212_GPM2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* VTCAM_MCLK */ +#if defined(CONFIG_MACH_T0_CHN_CMCC) + {EXYNOS4212_GPM0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* USBSW_EN */ +#endif + {EXYNOS4212_GPM4(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* SENSOR_CORE_EN */ +#if defined(CONFIG_MACH_T0_CHN_CTC) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPL0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SIM_SEL */ + +#endif +}; + +/* + * T0 GPIO Sleep Table + * Based on HW Rev0.4 + */ + +#if defined(CONFIG_MACH_T0_CHN_CTC) +static unsigned int t0_sleep_gpio_table[][3] = { + {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_RXD */ + {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* BT_UART_TXD */ + {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_CTS */ + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* BT_UART_RTS */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GPS_UART_RXD */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_TXD */ + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_CTS */ + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* GPS_UART_RTS */ +#else + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SDA_1.8V */ + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SCL_1.8V */ +#endif + + {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_RXD */ + {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_TXD */ + {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SDA_1.8V */ + {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SCL_1.8V */ + {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SDA_1.8V */ + {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SCL_1.8V */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SDA_1.8V */ + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SCL_1.8V */ +#else + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_SCLK */ + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* CAM_SPI_SSN */ + {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MISO */ + {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MOSI */ + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_RST */ +#else + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_1.8V_EN(NC) */ +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */ +#else + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PLD_SPI_CS1 */ +#endif +#if defined(CONFIG_MACH_T0) && defined(CONFIG_TARGET_LOCALE_KOR) + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VIB_ON */ +#else + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* APMDM_INT1 */ +#endif +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_INT */ +#else + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* APMDM_INT2 */ +#endif + +#ifdef CONFIG_JACK_FET + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* EAR_BIAS_DISCHARGE */ +#else + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* PLD_SPI_CLK */ + {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* PLD_SPI_CS */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSDA_1.8V */ + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSCL_1.8V */ +#else + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* PLD_SPI_MOSI */ +#endif + + {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VIBTONE_PWM */ + {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SDA_1.8V */ + {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SCL_1.8V */ + + {EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SDA_1.8V */ + {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SCL_1.8V */ + {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_MCU_SDA_1.8V */ + {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_MCU_SCL_1.8V */ + + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PLD2_CRESET */ + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PLD2_CDONE */ + {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PLD1_CRESET */ + {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PLD1_CDONE */ + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* ESC_OFF */ + {EXYNOS4_GPF0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM_OFF */ + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PLD1_RST */ + {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OTG_EN */ + + {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OLED_ID */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ACTIVE_STATE_HSIC */ +#else + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AUDIO_PCM_SEL */ +#endif + {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_ID */ + {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RESET */ + {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SCL_1.8V */ + {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SDA_1.8V */ + /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ +#if 1 /* defined(CONFIG_MACH_T0_EUR_OPEN) */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */ +#else + /* GPF1(6) T0 LTE prev level, if not mdm notice it as crash */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_STATUS */ +#endif + {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBIAS_EN */ + +#ifdef CONFIG_SND_USE_SUB_MIC + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MICBIAS_EN */ +#endif + {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MLCD_RST */ +#if 1 /* defined(CONFIG_MACH_T0_EUR_OPEN) */ + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CP_USB_EN */ + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PLD2_RST */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* BOOT_SW_SEL_CP2 */ +#else + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM2AP_HSIC_PWR_ACTIVE */ + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WCN_PRIORITY */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM_LTE_FRAME_SYNC */ +#endif + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */ + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */ + + {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* OLED_DET */ + {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */ + {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */ + {EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */ + {EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BOOT_SW_SEL_CP1 */ + {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */ + {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */ + {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */ + {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */ + {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */ + {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */ + {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */ + + {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */ + {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */ + {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */ + {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */ + + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CLK */ + {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CMD */ + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(0) */ + {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(1) */ + {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(2) */ + {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(3) */ + + {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CLK */ + {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CMD */ + {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(0) */ + {EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(1) */ + {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(2) */ + {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(3) */ + + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* USB_HUB_RST */ + {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2TOUCH_SCL */ + {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2TOUCH_SDA */ + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VPS_SOUND_EN */ + {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*SIM_SEL*/ + {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BT_EN */ + + {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* USB_HUB_SCL */ + {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* USB_HUB_SDA */ + + {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_RST */ + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_EN(NC) */ + {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if 1 /* defined(CONFIG_MACH_T0_EUR_OPEN) */ + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_ON */ +#else + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_PON_RESET_N */ +#endif + {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NFC_EN */ + {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NFC_FIRMWARE */ + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* PLD_CS0 */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */ +#else + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* PLD_CS1 */ +#endif + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* AP_OE */ + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* AP_WE */ + + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_SLP_1.8V */ + + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ + {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_RESET_N_1.8V */ + {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MCU_NRST_1.8V */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, + S3C_GPIO_PULL_DOWN}, /* NC */ +#else + /* AP2MDM_PMIC_RESET_N */ + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_PREV, + S3C_GPIO_PULL_UP}, +#endif + {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NFC_SDA_1.8V */ + {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NFC_SCL_1.8V */ + + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY4(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {EXYNOS4_GPY5(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY5(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPY6(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPY6(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_CLK */ + {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_SYNC */ + {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DI */ + {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DO */ + {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + /* Exynos4212 specific gpio */ + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WLAN_EN */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*AP_DUMP_INT*/ +#else + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* UART_SEL */ + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2_TOUCH_INT */ + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */ + {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ERR_FG */ + + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CAM_SW_EN */ + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_EN */ + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_SET */ + {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_MCLK */ + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* USB_SEL */ + + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP2_RST */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP2_ON */ + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2TOUCH_EN */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_STANDBY */ + {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_IO_EN */ + + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_ISP_CORE_EN */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_AF_EN */ + {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_VT_nRST */ + + {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SDA_1.8V */ + {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SCL_1.8V */ + {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VTCAM_MCLK */ + {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_nINT */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* SUSPEND_REQUEST_HSIC */ +#else + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + + {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */ + {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */ + {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + /* GPM3(3) M0, CP_RESET_REQ hold high */ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* RESET_REQ_N */ +#else + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SENSOR_CORE_EN */ +#endif + {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */ + {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */ + {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +}; /* t0_sleep_gpio_table */ + +#else + +static unsigned int t0_sleep_gpio_table[][3] = { + {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_RXD */ + {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* BT_UART_TXD */ + {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BT_UART_CTS */ + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* BT_UART_RTS */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_TARGET_LOCALE_CHN) + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* GPS_UART_RXD */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_TXD */ + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_UART_CTS */ + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* GPS_UART_RTS */ +#else + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SDA_1.8V */ + {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SCL_1.8V */ +#endif + + {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_RXD */ + {EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP_TXD */ + {EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SDA_1.8V */ + {EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_SCL_1.8V */ + {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SDA_1.8V */ + {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CODEC_SCL_1.8V */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_TARGET_LOCALE_CHN) + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SDA_1.8V */ + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* PEN_SCL_1.8V */ +#else + {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSDA_1.8V */ + {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSCL_1.8V */ +#endif + {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_SCLK */ + {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* CAM_SPI_SSN */ + {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MISO */ + {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SPI_MOSI */ + +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_RST */ +#else + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* LCD_1.8V_EN(NC) */ +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_PWR_EN */ +#else + {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDMB_INT */ +#else + {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + +#ifdef CONFIG_JACK_FET + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* EAR_BIAS_DISCHARGE */ +#else + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TDMB_SPI_CLK */ +#else + {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSDA_1.8V */ + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_DSCL_1.8V */ +#else + {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* TDMB_SPI_DO */ +#else + {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif +#endif + + {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VIBTONE_PWM */ + {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SDA_1.8V */ + {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_PMIC_SCL_1.8V */ + + {EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SDA_1.8V */ + {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 8M_CAM_SCL_1.8V */ + {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_MCU_SDA_1.8V */ + {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_MCU_SCL_1.8V */ + + {EXYNOS4_GPF0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BARCODE_SDA_1.8V */ + {EXYNOS4_GPF0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* BARCODE_SCL_1.8V */ +#if !defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + && !defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPF0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CRESET_B */ + {EXYNOS4_GPF0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CDONE */ +#endif + +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* ESC_OFF */ +#else + {EXYNOS4_GPF0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_SDA_1.8V */ +#endif + {EXYNOS4_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* FPGA_RST_N */ +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PLD_RESET_N */ +#else + {EXYNOS4_GPF0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MHL_SCL_1.8V */ +#endif + {EXYNOS4_GPF0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OTG_EN */ + + {EXYNOS4_GPF1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* OLED_ID */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ACTIVE_STATE_HSIC */ +#else + {EXYNOS4_GPF1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM2AP_HSIC_READY */ +#endif + {EXYNOS4_GPF1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_ID */ + {EXYNOS4_GPF1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_RESET */ + {EXYNOS4_GPF1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SCL_1.8V */ + {EXYNOS4_GPF1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FUEL_SDA_1.8V */ + /* GPF1(6) M0, C1 PDA_ACTIVE, let cp know AP sleep status*/ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* PDA_ACTIVE */ +#else + /* GPF1(6) T0 LTE prev level, if not mdm notice it as crash */ + {EXYNOS4_GPF1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_STATUS */ +#endif + {EXYNOS4_GPF1(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MICBIAS_EN */ + +#ifdef CONFIG_SND_USE_SUB_MIC + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SUB_MICBIAS_EN */ +#else + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPF2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MLCD_RST */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else + {EXYNOS4_GPF2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM2AP_HSIC_PWR_ACTIVE */ + {EXYNOS4_GPF2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WCN_PRIORITY */ + {EXYNOS4_GPF2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* MDM_LTE_FRAME_SYNC */ +#endif +#if defined(CONFIG_MACH_T0_EUR_OPEN) + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* WACOM_LDO_EN */ +#else + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPF2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SCL */ + {EXYNOS4_GPF2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* S_LED_I2C_SDA */ + + {EXYNOS4_GPF3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* OLED_DET */ + {EXYNOS4_GPF3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK2_SEL */ + {EXYNOS4_GPF3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK3_SEL */ + {EXYNOS4_GPF3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* BUCK4_SEL */ +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CDONE */ + {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* CRESET_B */ +#else + {EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* MHL_RST */ + {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_INT */ +#endif + + {EXYNOS4_GPK0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CLK */ + {EXYNOS4_GPK0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_CMD */ + {EXYNOS4_GPK0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* eMMC_EN */ + {EXYNOS4_GPK0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(0) */ + {EXYNOS4_GPK0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(1) */ + {EXYNOS4_GPK0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(2) */ + {EXYNOS4_GPK0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(3) */ + + {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(4) */ + {EXYNOS4_GPK1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(5) */ + {EXYNOS4_GPK1(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(6) */ + {EXYNOS4_GPK1(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NAND_D(7) */ + + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CLK */ + {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_CMD */ + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(0) */ + {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(1) */ + {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(2) */ + {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* T_FLASH_D(3) */ + + {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CLK */ + {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_CMD */ + {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(0) */ + {EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(1) */ + {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(2) */ + {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* WLAN_SDIO_D(3) */ + + {EXYNOS4_GPL0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2TOUCH_SCL */ + {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2TOUCH_SDA */ + {EXYNOS4_GPL0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* VPS_SOUND_EN */ + {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* HDMI_EN */ + {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*BT_EN */ + + {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_T0_CHN_CMCC) && defined(CONFIG_SEC_DUAL_MODEM_MODE) + {EXYNOS4_GPL2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* SIM_IO_SEL */ +#else + {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* GPS_EN(NC) */ +#if defined(CONFIG_MACH_T0_CHN_CMCC) && defined(CONFIG_SEC_DUAL_MODEM_MODE) + {EXYNOS4_GPL2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_CTRL1 */ + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_CTRL2 */ +#else + {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPL2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CP_ON */ +#else + {EXYNOS4_GPL2(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_PON_RESET_N */ +#endif + {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* NFC_EN */ + {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NFC_FIRMWARE */ + {EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_OPEN) + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* FM_RST */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FM_SCL_1.8V */ + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* FM_SDA_1.8V */ +#else + {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_SLP_1.8V */ + + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TF_EN */ + {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, /* PEN_RESET_N_1.8V */ + {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* MCU_NRST_1.8V */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else + {EXYNOS4_GPY2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* AP2MDM_PMIC_RESET_N */ +#endif + {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NFC_SDA_1.8V */ + {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* NFC_SCL_1.8V */ + + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4_GPZ(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_CLK */ + {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_SYNC */ + {EXYNOS4_GPZ(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DI */ + {EXYNOS4_GPZ(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MM_I2S_DO */ + {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + /* Exynos4212 specific gpio */ + {EXYNOS4212_GPJ0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* WLAN_EN */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*AP_DUMP_INT*/ +#else + {EXYNOS4212_GPJ0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /*AP2MDM_ERR_FATAL*/ +#endif +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* UART_SEL */ +#else + {EXYNOS4212_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2_TOUCH_INT */ + {EXYNOS4212_GPJ0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CODEC_LDO_EN */ + {EXYNOS4212_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ERR_FG */ + + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CAM_SW_EN */ + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_EN */ + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TORCH_SET */ + {EXYNOS4212_GPJ1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_MCLK */ +#if defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* USB_SEL */ +#else + {EXYNOS4212_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* MHL_WAKE_UP */ +#endif + + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_T0_CHN_CMCC) + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* TDCP_ON */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* CP_USB_ON */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PCM_SEL */ + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* USBSW_EN */ +#elif defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4212_GPM0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /*CP2_RST */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_DOWN}, /*CP2_ON */ +#else + {EXYNOS4212_GPM0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPM0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* 2TOUCH_EN */ + {EXYNOS4212_GPM0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* ISP_STANDBY */ + {EXYNOS4212_GPM0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_IO_EN */ + + {EXYNOS4212_GPM1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_ISP_CORE_EN */ + {EXYNOS4212_GPM1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_AF_EN */ + {EXYNOS4212_GPM1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* AP_HW_REV0 */ + {EXYNOS4212_GPM1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_VT_nRST */ + + {EXYNOS4212_GPM2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SDA_1.8V */ + {EXYNOS4212_GPM2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, /* IF_PMIC_SCL_1.8V */ + {EXYNOS4212_GPM2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VTCAM_MCLK */ + {EXYNOS4212_GPM2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TSP_nINT */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* SUSPEND_REQUEST_HSIC */ +#else + {EXYNOS4212_GPM2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP2MDM_WAKEUP */ +#endif + + {EXYNOS4212_GPM3(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS1 */ + {EXYNOS4212_GPM3(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS2 */ + {EXYNOS4212_GPM3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* PMIC_DVS3 */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + /* GPM3(3) M0, CP_RESET_REQ hold high */ + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, /* RESET_REQ_N */ +#else + {EXYNOS4212_GPM3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* AP2MDM_SOFT_RESET */ +#endif + {EXYNOS4212_GPM3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPM3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if defined(CONFIG_MACH_T0_CHN_CMCC) + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* UART_SEL */ +#else + {EXYNOS4212_GPM3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4212_GPM3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + +#if defined(CONFIG_MACH_T0_CHN_CMCC) + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, /* USB_SEL */ +#else + {EXYNOS4212_GPM4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif +#if defined(CONFIG_MACH_T0_EUR_OPEN) || defined(CONFIG_MACH_T0_CHN_CMCC) \ + || defined(CONFIG_MACH_T0_CHN_OPEN) || defined(CONFIG_MACH_T0_CHN_CU_DUOS) \ + || defined(CONFIG_MACH_T0_CHN_OPEN_DUOS) + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else + {EXYNOS4212_GPM4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* CAM_SENSOR_CORE_EN */ +#endif + {EXYNOS4212_GPM4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SCL */ + {EXYNOS4212_GPM4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* VT_CAM_SDA */ + {EXYNOS4212_GPM4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* FPGA_SPI_CLK */ + {EXYNOS4212_GPM4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* FPGA_SPI_EN */ + {EXYNOS4212_GPM4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* FPGA_SPI_SI */ + {EXYNOS4212_GPM4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + {EXYNOS4212_GPV4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPV4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +}; /* t0_sleep_gpio_table */ + +#endif + +/* + * T0 Rev0.5 GPIO Sleep Table + */ +static unsigned int t0_sleep_gpio_table_rev05[][3] = { +#if defined(CONFIG_TARGET_LOCALE_KOR) + {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif + {EXYNOS4_GPF2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + {EXYNOS4212_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +}; + +/* + * T0 Rev1.1 GPIO Sleep Table + */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) +static unsigned int t0_sleep_gpio_table_rev11[][3] = { + {EXYNOS4_GPF2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* WACOM_LDO_EN */ +}; +#endif + +struct t0_sleep_table { + unsigned int (*ptr)[3]; + int size; +}; + +#define GPIO_TABLE(_ptr) \ + {.ptr = _ptr, \ + .size = ARRAY_SIZE(_ptr)} \ + +#define GPIO_TABLE_NULL \ + {.ptr = NULL, \ + .size = 0} \ + +static struct t0_sleep_table t0_sleep_table[] = { + GPIO_TABLE(t0_sleep_gpio_table), /* Rev0.4 - Universal */ + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE(t0_sleep_gpio_table_rev05), /* Rev0.5 */ +#if defined(CONFIG_MACH_T0_EUR_OPEN) + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE_NULL, + GPIO_TABLE(t0_sleep_gpio_table_rev11), /* Rev1.1 */ +#endif +}; + +static void config_sleep_gpio_table(int array_size, + unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +static void t0_config_sleep_gpio_table(void) +{ + int i; + int index = min(ARRAY_SIZE(t0_sleep_table), system_rev + 1); + + for (i = 0; i < index; i++) { + if (t0_sleep_table[i].ptr == NULL) + continue; + + config_sleep_gpio_table(t0_sleep_table[i].size, + t0_sleep_table[i].ptr); + } +} + +/* To save power consumption, gpio pin set before enterling sleep */ +void midas_config_sleep_gpio_table(void) +{ + t0_config_sleep_gpio_table(); +} + +/* Intialize gpio set in midas board */ +void midas_config_gpio_table(void) +{ + u32 i, gpio; + + printk(KERN_DEBUG "%s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(t0_init_gpios); i++) { + gpio = t0_init_gpios[i].num; + if (gpio <= EXYNOS4212_GPV4(1)) { + s3c_gpio_cfgpin(gpio, t0_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, t0_init_gpios[i].pud); + + if (t0_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, t0_init_gpios[i].val); + + s5p_gpio_set_drvstr(gpio, t0_init_gpios[i].drv); + } + } +} diff --git a/arch/arm/mach-exynos/t0-power.c b/arch/arm/mach-exynos/t0-power.c new file mode 100644 index 0000000..c092bc0 --- /dev/null +++ b/arch/arm/mach-exynos/t0-power.c @@ -0,0 +1,824 @@ +/* + * t0-power.c - Power Management of T0 Project + * + * Copyright (C) 2011 Samsung Electrnoics + * Chiwoong Byun <woong.byun@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/i2c.h> +#include <linux/regulator/machine.h> +#include <plat/gpio-cfg.h> +#include <mach/gpio-midas.h> +#include <mach/irqs.h> + +#include <linux/mfd/max8997.h> +#include <linux/mfd/max77686.h> +#include <linux/mfd/max77693.h> + +#if defined(CONFIG_REGULATOR_S5M8767) +#include <linux/mfd/s5m87xx/s5m-pmic.h> +#include <linux/mfd/s5m87xx/s5m-core.h> +#endif + + +#ifdef CONFIG_REGULATOR_MAX77686 +/* max77686 */ + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo3_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +}; +#else +static struct regulator_consumer_supply ldo3_supply[] = {}; +#endif + +static struct regulator_consumer_supply ldo5_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v", NULL), + REGULATOR_SUPPLY("touchkey", NULL), +}; + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), + REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), +}; + +static struct regulator_consumer_supply ldo9_supply[] = { + REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo10_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), +}; + +static struct regulator_consumer_supply ldo11_supply[] = { + REGULATOR_SUPPLY("vabb1_1.95v", NULL), +}; + +static struct regulator_consumer_supply ldo12_supply[] = { + REGULATOR_SUPPLY("votg_3.0v", NULL), +}; + +static struct regulator_consumer_supply ldo13_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v_lcd", NULL), +}; + +static struct regulator_consumer_supply ldo14_supply[] = { + REGULATOR_SUPPLY("vabb2_1.95v", NULL), +}; + +#if defined(CONFIG_MACH_T0_CHN_CTC) +static struct regulator_consumer_supply ldo17_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v_usb", NULL), +}; +#else +static struct regulator_consumer_supply ldo17_supply[] = { +#if defined(CONFIG_TARGET_LOCALE_USA) + REGULATOR_SUPPLY("vcc_adc_1.8v", NULL), +#else + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +#endif +}; +#endif + +static struct regulator_consumer_supply ldo18_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo19_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo21_supply[] = { + REGULATOR_SUPPLY("vtf_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo23_supply[] = { + REGULATOR_SUPPLY("touch", NULL), +}; + +static struct regulator_consumer_supply ldo24_supply[] = { + REGULATOR_SUPPLY("touch_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo25_supply[] = { + REGULATOR_SUPPLY("vlcd_3.3v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +}; + +static struct regulator_consumer_supply ldo26_supply[] = { + REGULATOR_SUPPLY("vmotor", NULL), +}; + +static struct regulator_consumer_supply max77686_buck1[] = { + REGULATOR_SUPPLY("vdd_mif", NULL), + REGULATOR_SUPPLY("vdd_mif", "exynos4412-busfreq"), +}; + +static struct regulator_consumer_supply max77686_buck2 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply max77686_buck3[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"), +}; + +static struct regulator_consumer_supply max77686_buck4[] = { + REGULATOR_SUPPLY("vdd_g3d", NULL), + REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"), +}; + +static struct regulator_consumer_supply max77686_buck9 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); + +static struct regulator_consumer_supply max77686_enp32khz[] = { + REGULATOR_SUPPLY("lpo_in", "bcm47511"), + REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"), +}; + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo5, "VCC_1.8V_IO", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo9, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo11, "VABB1_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo13, "VCC_1.8V_LCD", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo14, "VABB2_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +#if defined(CONFIG_MACH_T0_CHN_CTC) +REGULATOR_INIT(ldo17, "VCC_1.8V_USB", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +#else +#if defined(CONFIG_TARGET_LOCALE_USA) +REGULATOR_INIT(ldo17, "VCC_ADC_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +#else +REGULATOR_INIT(ldo17, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +#endif +#endif +REGULATOR_INIT(ldo18, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo19, "VT_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo21, "VTF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo23, "TSP_AVDD_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo24, "VDD_1.8V_TSP", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo25, "VCC_3.0V_LCD", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo26, "VCC_MOTOR_3.0V", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data max77686_buck1_data = { + .constraints = { + .name = "vdd_mif range", + .min_uV = 850000, + .max_uV = 1200000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck1), + .consumer_supplies = max77686_buck1, +}; + +static struct regulator_init_data max77686_buck2_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 850000, + .max_uV = 1500000, + .apply_uV = 1, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max77686_buck2, +}; + +static struct regulator_init_data max77686_buck3_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 825000, + .max_uV = 1300000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck3), + .consumer_supplies = max77686_buck3, +}; + +static struct regulator_init_data max77686_buck4_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 850000, + .max_uV = 1200000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_buck4), + .consumer_supplies = max77686_buck4, +}; + +static struct regulator_init_data max77686_buck9_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1000000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &max77686_buck9, +}; + +static struct regulator_init_data max77686_enp32khz_data = { + .constraints = { + .name = "32KHZ_PMIC", + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(max77686_enp32khz), + .consumer_supplies = max77686_enp32khz, +}; + +static struct max77686_regulator_data max77686_regulators[] = { + {MAX77686_BUCK1, &max77686_buck1_data,}, + {MAX77686_BUCK2, &max77686_buck2_data,}, + {MAX77686_BUCK3, &max77686_buck3_data,}, + {MAX77686_BUCK4, &max77686_buck4_data,}, + {MAX77686_BUCK9, &max77686_buck9_data,}, + {MAX77686_LDO3, &ldo3_init_data,}, + {MAX77686_LDO5, &ldo5_init_data,}, + {MAX77686_LDO8, &ldo8_init_data,}, + {MAX77686_LDO9, &ldo9_init_data,}, + {MAX77686_LDO10, &ldo10_init_data,}, + {MAX77686_LDO11, &ldo11_init_data,}, + {MAX77686_LDO12, &ldo12_init_data,}, + {MAX77686_LDO13, &ldo13_init_data,}, + {MAX77686_LDO14, &ldo14_init_data,}, + {MAX77686_LDO17, &ldo17_init_data,}, + {MAX77686_LDO18, &ldo18_init_data,}, + {MAX77686_LDO19, &ldo19_init_data,}, + {MAX77686_LDO21, &ldo21_init_data,}, + {MAX77686_LDO23, &ldo23_init_data,}, + {MAX77686_LDO24, &ldo24_init_data,}, + {MAX77686_LDO25, &ldo25_init_data,}, + {MAX77686_LDO26, &ldo26_init_data,}, + {MAX77686_P32KH, &max77686_enp32khz_data,}, +}; + +struct max77686_opmode_data max77686_opmode_data[MAX77686_REG_MAX] = { + [MAX77686_LDO3] = {MAX77686_LDO3, MAX77686_OPMODE_NORMAL}, + [MAX77686_LDO8] = {MAX77686_LDO8, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO10] = {MAX77686_LDO10, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO11] = {MAX77686_LDO11, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO12] = {MAX77686_LDO12, MAX77686_OPMODE_STANDBY}, + [MAX77686_LDO13] = {MAX77686_LDO13, MAX77686_OPMODE_NORMAL}, + [MAX77686_LDO14] = {MAX77686_LDO14, MAX77686_OPMODE_STANDBY}, +#if defined(CONFIG_MACH_T0_CHN_CTC) + [MAX77686_LDO17] = {MAX77686_LDO17, MAX77686_OPMODE_NORMAL}, +#endif + [MAX77686_BUCK1] = {MAX77686_BUCK1, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK2] = {MAX77686_BUCK2, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK3] = {MAX77686_BUCK3, MAX77686_OPMODE_STANDBY}, + [MAX77686_BUCK4] = {MAX77686_BUCK4, MAX77686_OPMODE_STANDBY}, +}; + +struct max77686_platform_data exynos4_max77686_info = { + .num_regulators = ARRAY_SIZE(max77686_regulators), + .regulators = max77686_regulators, + .irq_gpio = GPIO_PMIC_IRQ, + .irq_base = IRQ_BOARD_PMIC_START, + .wakeup = 1, + + .opmode_data = max77686_opmode_data, + .ramp_rate = MAX77686_RAMP_RATE_27MV, + .wtsr_smpl = MAX77686_WTSR_ENABLE | MAX77686_SMPL_ENABLE, + + .buck234_gpio_dvs = { + /* Use DVS2 register of each bucks to supply stable power + * after sudden reset */ + {GPIO_PMIC_DVS1, 1}, + {GPIO_PMIC_DVS2, 0}, + {GPIO_PMIC_DVS3, 0}, + }, + .buck234_gpio_selb = { + GPIO_BUCK2_SEL, + GPIO_BUCK3_SEL, + GPIO_BUCK4_SEL, + }, + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1100000, /* 1.1V */ + .buck2_voltage[2] = 1100000, /* 1.1V */ + .buck2_voltage[3] = 1100000, /* 1.1V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1100000, /* 1.1V */ + .buck2_voltage[6] = 1100000, /* 1.1V */ + .buck2_voltage[7] = 1100000, /* 1.1V */ + + .buck3_voltage[0] = 1100000, /* 1.1V */ + .buck3_voltage[1] = 1000000, /* 1.0V */ + .buck3_voltage[2] = 1100000, /* 1.1V */ + .buck3_voltage[3] = 1100000, /* 1.1V */ + .buck3_voltage[4] = 1100000, /* 1.1V */ + .buck3_voltage[5] = 1100000, /* 1.1V */ + .buck3_voltage[6] = 1100000, /* 1.1V */ + .buck3_voltage[7] = 1100000, /* 1.1V */ + + .buck4_voltage[0] = 1100000, /* 1.1V */ + .buck4_voltage[1] = 1000000, /* 1.0V */ + .buck4_voltage[2] = 1100000, /* 1.1V */ + .buck4_voltage[3] = 1100000, /* 1.1V */ + .buck4_voltage[4] = 1100000, /* 1.1V */ + .buck4_voltage[5] = 1100000, /* 1.1V */ + .buck4_voltage[6] = 1100000, /* 1.1V */ + .buck4_voltage[7] = 1100000, /* 1.1V */ +}; + +#endif /* CONFIG_REGULATOR_MAX77686 */ + +void midas_power_set_muic_pdata(void *pdata, int gpio) +{ + gpio_request(gpio, "AP_PMIC_IRQ"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); +} + +void midas_power_gpio_init(void) +{ +} + +#ifdef CONFIG_MFD_MAX77693 +static struct regulator_consumer_supply safeout1_supply[] = { + REGULATOR_SUPPLY("safeout1", NULL), +}; + +static struct regulator_consumer_supply safeout2_supply[] = { + REGULATOR_SUPPLY("safeout2", NULL), +}; + +static struct regulator_consumer_supply charger_supply[] = { + REGULATOR_SUPPLY("vinchg1", "charger-manager.0"), + REGULATOR_SUPPLY("vinchg1", NULL), +}; + +static struct regulator_init_data safeout1_init_data = { + .constraints = { + .name = "safeout1 range", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 1, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout1_supply), + .consumer_supplies = safeout1_supply, +}; + +static struct regulator_init_data safeout2_init_data = { + .constraints = { + .name = "safeout2 range", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 0, + .boot_on = 0, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout2_supply), + .consumer_supplies = safeout2_supply, +}; + +static struct regulator_init_data charger_init_data = { + .constraints = { + .name = "CHARGER", + .valid_ops_mask = REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_CURRENT, + .boot_on = 1, + .min_uA = 60000, + .max_uA = 2580000, + }, + .num_consumer_supplies = ARRAY_SIZE(charger_supply), + .consumer_supplies = charger_supply, +}; + +struct max77693_regulator_data max77693_regulators[] = { + {MAX77693_ESAFEOUT1, &safeout1_init_data,}, + {MAX77693_ESAFEOUT2, &safeout2_init_data,}, + {MAX77693_CHARGER, &charger_init_data,}, +}; +#endif /* CONFIG_MFD_MAX77693 */ + +#if defined(CONFIG_REGULATOR_S5M8767) +/* S5M8767 Regulator */ + +#ifdef CONFIG_SND_SOC_WM8994 +static struct regulator_consumer_supply ldo3_supply[] = { + REGULATOR_SUPPLY("AVDD2", NULL), + REGULATOR_SUPPLY("CPVDD", NULL), + REGULATOR_SUPPLY("DBVDD1", NULL), + REGULATOR_SUPPLY("DBVDD2", NULL), + REGULATOR_SUPPLY("DBVDD3", NULL), +}; +#else +static struct regulator_consumer_supply ldo3_supply[] = {}; +#endif + +static struct regulator_consumer_supply ldo8_supply[] = { + REGULATOR_SUPPLY("vmipi_1.0v", NULL), + REGULATOR_SUPPLY("VDD10", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), + REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), +}; + +static struct regulator_consumer_supply ldo9_supply[] = { + REGULATOR_SUPPLY("cam_isp_mipi_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo10_supply[] = { + REGULATOR_SUPPLY("vmipi_1.8v", NULL), + REGULATOR_SUPPLY("VDD18", "s5p-mipi-dsim.0"), + REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), +}; + +static struct regulator_consumer_supply ldo11_supply[] = { + REGULATOR_SUPPLY("vabb1_1.95v", NULL), +}; + +static struct regulator_consumer_supply ldo12_supply[] = { + REGULATOR_SUPPLY("votg_3.0v", NULL), +}; + +static struct regulator_consumer_supply ldo14_supply[] = { + REGULATOR_SUPPLY("vabb2_1.95v", NULL), +}; + +static struct regulator_consumer_supply ldo19_supply[] = { + REGULATOR_SUPPLY("touch_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo20_supply[] = { + REGULATOR_SUPPLY("vlcd_3.3v", NULL), + REGULATOR_SUPPLY("VCI", "s6e8aa0"), +}; +static struct regulator_consumer_supply ldo21_supply[] = { + REGULATOR_SUPPLY("vmotor", NULL), +}; + +static struct regulator_consumer_supply ldo22_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v", NULL), + REGULATOR_SUPPLY("touchkey", NULL), +}; + +static struct regulator_consumer_supply ldo23_supply[] = { + REGULATOR_SUPPLY("vtf_2.8v", NULL), +}; + +static struct regulator_consumer_supply ldo24_supply[] = { + REGULATOR_SUPPLY("touch", NULL), +}; + +static struct regulator_consumer_supply ldo25_supply[] = { + REGULATOR_SUPPLY("cam_sensor_core_1.2v", NULL), +}; + +static struct regulator_consumer_supply ldo26_supply[] = { + REGULATOR_SUPPLY("cam_isp_sensor_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo27_supply[] = { + REGULATOR_SUPPLY("vt_cam_1.8v", NULL), +}; + +static struct regulator_consumer_supply ldo28_supply[] = { + REGULATOR_SUPPLY("vcc_1.8v_lcd", NULL), +}; + +static struct regulator_consumer_supply s5m8767_buck1[] = { + REGULATOR_SUPPLY("vdd_mif", NULL), + REGULATOR_SUPPLY("vdd_mif", "exynos4212-busfreq"), +}; + +static struct regulator_consumer_supply s5m8767_buck2 = + REGULATOR_SUPPLY("vdd_arm", NULL); + +static struct regulator_consumer_supply s5m8767_buck3[] = { + REGULATOR_SUPPLY("vdd_int", NULL), + REGULATOR_SUPPLY("vdd_int", "exynoss4412-busfreq"), +}; + +static struct regulator_consumer_supply s5m8767_buck4[] = { + REGULATOR_SUPPLY("vdd_g3d", NULL), + REGULATOR_SUPPLY("vdd_g3d", "mali_dev.0"), +}; + +static struct regulator_consumer_supply s5m8767_buck6 = + REGULATOR_SUPPLY("cam_isp_core_1.2v", NULL); + +static struct regulator_consumer_supply s5m8767_enp32khz[] = { + REGULATOR_SUPPLY("lpo_in", "bcm47511"), + REGULATOR_SUPPLY("lpo", "bcm4334_bluetooth"), +}; + +#define REGULATOR_INIT(_ldo, _name, _min_uV, _max_uV, _always_on, _ops_mask, \ + _disabled) \ + static struct regulator_init_data _ldo##_init_data = { \ + .constraints = { \ + .name = _name, \ + .min_uV = _min_uV, \ + .max_uV = _max_uV, \ + .always_on = _always_on, \ + .boot_on = _always_on, \ + .apply_uV = 1, \ + .valid_ops_mask = _ops_mask, \ + .state_mem = { \ + .disabled = _disabled, \ + .enabled = !(_disabled), \ + } \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(_ldo##_supply), \ + .consumer_supplies = &_ldo##_supply[0], \ + }; + +REGULATOR_INIT(ldo3, "VCC_1.8V_AP", 1800000, 1800000, 1, 0, 0); +REGULATOR_INIT(ldo8, "VMIPI_1.0V", 1000000, 1000000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo9, "CAM_ISP_MIPI_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo10, "VMIPI_1.8V", 1800000, 1800000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo11, "VABB1_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo12, "VUOTG_3.0V", 3000000, 3000000, 1, + REGULATOR_CHANGE_STATUS, 0); +REGULATOR_INIT(ldo14, "VABB2_1.95V", 1950000, 1950000, 1, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo19, "VDD_1.8V_TSP", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo20, "VCC_3.0V_LCD", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo21, "VCC_MOTOR_3.0V", 3000000, 3000000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo22, "VTOUCH_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo23, "VTF_2.8V", 2800000, 2800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo24, "TSP_AVDD_3.3V", 3300000, 3300000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo25, "CAM_SENSOR_CORE_1.2V", 1200000, 1200000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo26, "CAM_ISP_SENSOR_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo27, "VT_CAM_1.8V", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); +REGULATOR_INIT(ldo28, "VCC_1.8V_LCD", 1800000, 1800000, 0, + REGULATOR_CHANGE_STATUS, 1); + +static struct regulator_init_data s5m8767_buck1_data = { + .constraints = { + .name = "vdd_mif range", + .min_uV = 850000, + .max_uV = 1100000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck1), + .consumer_supplies = s5m8767_buck1, +}; + +static struct regulator_init_data s5m8767_buck2_data = { + .constraints = { + .name = "vdd_arm range", + .min_uV = 850000, + .max_uV = 1500000, + .always_on = 1, + .apply_uV = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck2, +}; + +static struct regulator_init_data s5m8767_buck3_data = { + .constraints = { + .name = "vdd_int range", + .min_uV = 850000, + .max_uV = 1100000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck3), + .consumer_supplies = s5m8767_buck3, +}; + +static struct regulator_init_data s5m8767_buck4_data = { + .constraints = { + .name = "vdd_g3d range", + .min_uV = 850000, + .max_uV = 1075000, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_buck4), + .consumer_supplies = s5m8767_buck4, +}; + +static struct regulator_init_data s5m8767_buck6_data = { + .constraints = { + .name = "CAM_ISP_CORE_1.2V", + .min_uV = 1000000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &s5m8767_buck6, +}; + +static struct regulator_init_data s5m8767_enp32khz_data = { + .constraints = { + .name = "32KHZ_PMIC", + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + .disabled = 0, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(s5m8767_enp32khz), + .consumer_supplies = s5m8767_enp32khz, +}; + +static struct s5m_regulator_data s5m8767_regulators[] = { + {S5M8767_BUCK1, &s5m8767_buck1_data,}, + {S5M8767_BUCK2, &s5m8767_buck2_data,}, + {S5M8767_BUCK3, &s5m8767_buck3_data,}, + {S5M8767_BUCK4, &s5m8767_buck4_data,}, + {S5M8767_BUCK6, &s5m8767_buck6_data,}, + {S5M8767_LDO3, &ldo3_init_data,}, + {S5M8767_LDO8, &ldo8_init_data,}, + {S5M8767_LDO9, &ldo9_init_data,}, + {S5M8767_LDO10, &ldo10_init_data,}, + {S5M8767_LDO11, &ldo11_init_data,}, + {S5M8767_LDO12, &ldo12_init_data,}, + {S5M8767_LDO14, &ldo14_init_data,}, + {S5M8767_LDO19, &ldo19_init_data,}, + {S5M8767_LDO20, &ldo20_init_data,}, + {S5M8767_LDO21, &ldo21_init_data,}, + {S5M8767_LDO22, &ldo22_init_data,}, + {S5M8767_LDO23, &ldo23_init_data,}, + {S5M8767_LDO24, &ldo24_init_data,}, + {S5M8767_LDO25, &ldo25_init_data,}, + {S5M8767_LDO26, &ldo26_init_data,}, + {S5M8767_LDO27, &ldo27_init_data,}, + {S5M8767_LDO28, &ldo28_init_data,}, +}; + +struct s5m_opmode_data s5m8767_opmode_data[S5M8767_REG_MAX] = { + [S5M8767_BUCK1] = {S5M8767_BUCK1, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK2] = {S5M8767_BUCK2, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK3] = {S5M8767_BUCK3, S5M_OPMODE_STANDBY}, + [S5M8767_BUCK4] = {S5M8767_BUCK4, S5M_OPMODE_STANDBY}, + [S5M8767_LDO3] = {S5M8767_LDO3, S5M_OPMODE_NORMAL}, + [S5M8767_LDO8] = {S5M8767_LDO8, S5M_OPMODE_STANDBY}, + [S5M8767_LDO10] = {S5M8767_LDO10, S5M_OPMODE_STANDBY}, + [S5M8767_LDO11] = {S5M8767_LDO11, S5M_OPMODE_STANDBY}, + [S5M8767_LDO12] = {S5M8767_LDO12, S5M_OPMODE_STANDBY}, + [S5M8767_LDO14] = {S5M8767_LDO14, S5M_OPMODE_STANDBY}, +}; + +struct s5m_platform_data exynos4_s5m8767_info = { + .device_type = S5M8767X, + .num_regulators = ARRAY_SIZE(s5m8767_regulators), + .regulators = s5m8767_regulators, + .buck2_ramp_enable = true, + .buck3_ramp_enable = true, + .buck4_ramp_enable = true, + .irq_gpio = GPIO_PMIC_IRQ, + .irq_base = IRQ_BOARD_PMIC_START, + .wakeup = 1, + + .opmode_data = s5m8767_opmode_data, + .wtsr_smpl = 1, + + .buck2_voltage[0] = 1100000, /* 1.1V */ + .buck2_voltage[1] = 1100000, /* 1.1V */ + .buck2_voltage[2] = 1100000, /* 1.1V */ + .buck2_voltage[3] = 1100000, /* 1.1V */ + .buck2_voltage[4] = 1100000, /* 1.1V */ + .buck2_voltage[5] = 1100000, /* 1.1V */ + .buck2_voltage[6] = 1100000, /* 1.1V */ + .buck2_voltage[7] = 1100000, /* 1.1V */ + + .buck3_voltage[0] = 1100000, /* 1.1V */ + .buck3_voltage[1] = 1100000, /* 1.1V */ + .buck3_voltage[2] = 1100000, /* 1.1V */ + .buck3_voltage[3] = 1100000, /* 1.1V */ + .buck3_voltage[4] = 1100000, /* 1.1V */ + .buck3_voltage[5] = 1100000, /* 1.1V */ + .buck3_voltage[6] = 1100000, /* 1.1V */ + .buck3_voltage[7] = 1100000, /* 1.1V */ + + .buck4_voltage[0] = 1100000, /* 1.1V */ + .buck4_voltage[1] = 1100000, /* 1.1V */ + .buck4_voltage[2] = 1100000, /* 1.1V */ + .buck4_voltage[3] = 1100000, /* 1.1V */ + .buck4_voltage[4] = 1100000, /* 1.1V */ + .buck4_voltage[5] = 1100000, /* 1.1V */ + .buck4_voltage[6] = 1100000, /* 1.1V */ + .buck4_voltage[7] = 1100000, /* 1.1V */ + + .buck_ramp_delay = 25, + .buck_default_idx = 1, + + .buck_gpios[0] = EXYNOS4212_GPM3(0), + .buck_gpios[1] = EXYNOS4212_GPM3(1), + .buck_gpios[2] = EXYNOS4212_GPM3(2), + + .buck_ds[0] = EXYNOS4_GPF3(1), + .buck_ds[1] = EXYNOS4_GPF3(2), + .buck_ds[2] = EXYNOS4_GPF3(3), + + .buck1_init = 1000000, + .buck2_init = 1100000, + .buck3_init = 1000000, + .buck4_init = 1000000, +}; + +/* End of S5M8767 */ +#endif + +void midas_power_init(void) +{ + printk(KERN_INFO "%s\n", __func__); +} diff --git a/arch/arm/mach-exynos/t0-sound.c b/arch/arm/mach-exynos/t0-sound.c new file mode 100644 index 0000000..6f931a6 --- /dev/null +++ b/arch/arm/mach-exynos/t0-sound.c @@ -0,0 +1,481 @@ +/* + * t0-sound.c - Sound Management of T0 Project + * + * Copyright (C) 2012 Samsung Electrnoics + * Uk Kim <w0806.kim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/i2c.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/i2c-gpio.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <mach/irqs.h> +#include <mach/pmu.h> +#include <plat/iic.h> + +#include <plat/gpio-cfg.h> +#include <mach/gpio-midas.h> + +#ifdef CONFIG_SND_SOC_WM8994 +#include <linux/mfd/wm8994/pdata.h> +#include <linux/mfd/wm8994/gpio.h> +#endif + +#if defined(CONFIG_FM_SI4705) +#include <linux/i2c/si47xx_common.h> +#endif + +#include <linux/exynos_audio.h> + +static bool midas_snd_mclk_enabled; + +#if defined(CONFIG_FM_SI4705) +struct si47xx_info { + int gpio_int; + int gpio_rst; +} si47xx_data; + +#endif + +#define I2C_NUM_CODEC 4 +#define SET_PLATDATA_CODEC(i2c_pd) s3c_i2c4_set_platdata(i2c_pd) + +static DEFINE_SPINLOCK(midas_snd_spinlock); + +void midas_snd_set_mclk(bool on, bool forced) +{ + static int use_cnt; + + spin_lock(&midas_snd_spinlock); + + midas_snd_mclk_enabled = on; + + if (midas_snd_mclk_enabled) { + if (use_cnt++ == 0 || forced) { + pr_info("Sound: enabled mclk\n"); + exynos4_pmu_xclkout_set(midas_snd_mclk_enabled, + XCLKOUT_XUSBXTI); + mdelay(10); + } + } else { + if ((--use_cnt <= 0) || forced) { + pr_info("Sound: disabled mclk\n"); +#ifdef CONFIG_ARCH_EXYNOS5 + exynos5_pmu_xclkout_set(midas_snd_mclk_enabled, + XCLKOUT_XXTI); +#else /* for CONFIG_ARCH_EXYNOS4 */ + exynos4_pmu_xclkout_set(midas_snd_mclk_enabled, + XCLKOUT_XUSBXTI); +#endif + use_cnt = 0; + } + } + + spin_unlock(&midas_snd_spinlock); + + pr_info("Sound: state: %d, use_cnt: %d\n", + midas_snd_mclk_enabled, use_cnt); +} + +bool midas_snd_get_mclk(void) +{ + return midas_snd_mclk_enabled; +} + +#ifdef CONFIG_SND_SOC_WM8994 +/* vbatt_devices */ +static struct regulator_consumer_supply vbatt_supplies[] = { + REGULATOR_SUPPLY("LDO1VDD", NULL), + REGULATOR_SUPPLY("SPKVDD1", NULL), + REGULATOR_SUPPLY("SPKVDD2", NULL), +}; + +static struct regulator_init_data vbatt_initdata = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vbatt_supplies), + .consumer_supplies = vbatt_supplies, +}; + +static struct fixed_voltage_config vbatt_config = { + .init_data = &vbatt_initdata, + .microvolts = 5000000, + .supply_name = "VBATT", + .gpio = -EINVAL, +}; + +struct platform_device vbatt_device = { + .name = "reg-fixed-voltage", + .id = -1, + .dev = { + .platform_data = &vbatt_config, + }, +}; + +/* wm1811 ldo1 */ +static struct regulator_consumer_supply wm1811_ldo1_supplies[] = { + REGULATOR_SUPPLY("AVDD1", NULL), +}; + +static struct regulator_init_data wm1811_ldo1_initdata = { + .constraints = { + .name = "WM1811 LDO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(wm1811_ldo1_supplies), + .consumer_supplies = wm1811_ldo1_supplies, +}; + +/* wm1811 ldo2 */ +static struct regulator_consumer_supply wm1811_ldo2_supplies[] = { + REGULATOR_SUPPLY("DCVDD", NULL), +}; + +static struct regulator_init_data wm1811_ldo2_initdata = { + .constraints = { + .name = "WM1811 LDO2", + .always_on = true, /* Actually status changed by LDO1 */ + }, + .num_consumer_supplies = ARRAY_SIZE(wm1811_ldo2_supplies), + .consumer_supplies = wm1811_ldo2_supplies, +}; + +static struct wm8994_drc_cfg drc_value[] = { + { + .name = "voice call DRC", + .regs[0] = 0x009B, + .regs[1] = 0x0844, + .regs[2] = 0x00E8, + .regs[3] = 0x0210, + .regs[4] = 0x0000, + }, +}; + +static struct wm8994_pdata wm1811_pdata = { + .gpio_defaults = { + [0] = WM8994_GP_FN_IRQ, /* GPIO1 IRQ output, CMOS mode */ + [7] = WM8994_GPN_DIR | WM8994_GP_FN_PIN_SPECIFIC, /* DACDAT3 */ + [8] = WM8994_CONFIGURE_GPIO | + WM8994_GP_FN_PIN_SPECIFIC, /* ADCDAT3 */ + [9] = WM8994_CONFIGURE_GPIO |\ + WM8994_GP_FN_PIN_SPECIFIC, /* LRCLK3 */ + [10] = WM8994_CONFIGURE_GPIO |\ + WM8994_GP_FN_PIN_SPECIFIC, /* BCLK3 */ + }, + + .irq_base = IRQ_BOARD_CODEC_START, + + /* The enable is shared but assign it to LDO1 for software */ + .ldo = { + { + .enable = GPIO_WM8994_LDO, + .init_data = &wm1811_ldo1_initdata, + }, + { + .init_data = &wm1811_ldo2_initdata, + }, + }, + /* Apply DRC Value */ + .drc_cfgs = drc_value, + .num_drc_cfgs = ARRAY_SIZE(drc_value), + + /* Support external capacitors*/ + .jd_ext_cap = 1, + + /* Regulated mode at highest output voltage */ + .micbias = {0x2f, 0x27}, + + .micd_lvl_sel = 0xFF, + + .ldo_ena_always_driven = true, + .ldo_ena_delay = 30000, + + .lineout1fb = 1, + + .lineout2fb = 0, +}; + +static struct i2c_board_info i2c_wm1811[] __initdata = { + { + I2C_BOARD_INFO("wm1811", (0x34 >> 1)), /* Audio CODEC */ + .platform_data = &wm1811_pdata, + .irq = IRQ_EINT(30), + }, +}; + +#endif + +#if defined(CONFIG_FM_SI4705) +static void fmradio_power(int on) +{ + if (on) { + gpio_request(GPIO_FM_INT, "FMRAIDO INT"); + gpio_direction_output(GPIO_FM_INT, 1); + gpio_set_value(si47xx_data.gpio_rst, GPIO_LEVEL_LOW); + gpio_set_value(GPIO_FM_INT, GPIO_LEVEL_LOW); + usleep_range(5, 10); + gpio_set_value(si47xx_data.gpio_rst, GPIO_LEVEL_HIGH); + usleep_range(10, 15); + gpio_set_value(GPIO_FM_INT, GPIO_LEVEL_HIGH); + + s3c_gpio_cfgpin(GPIO_FM_INT, S3C_GPIO_SFN(0xF)); + gpio_free(GPIO_FM_INT); + } else { + gpio_set_value(si47xx_data.gpio_rst, GPIO_LEVEL_LOW); + } +} + +static struct si47xx_platform_data si47xx_pdata = { + .rx_vol = {0x0, 0x13, 0x16, 0x19, 0x1C, 0x1F, 0x22, 0x25, + 0x28, 0x2B, 0x2E, 0x31, 0x34, 0x37, 0x3A, 0x3D}, + .power = fmradio_power, + +}; + +static struct i2c_gpio_platform_data gpio_i2c_data19 = { + .sda_pin = GPIO_FM_SDA, + .scl_pin = GPIO_FM_SCL, +}; + +struct platform_device s3c_device_i2c19 = { + .name = "i2c-gpio", + .id = 19, + .dev.platform_data = &gpio_i2c_data19, +}; + +static struct i2c_board_info i2c_devs19_emul[] __initdata = { + { + I2C_BOARD_INFO("Si47xx", (0x22 >> 1)), + .platform_data = &si47xx_pdata, + .irq = IRQ_EINT(11), + }, +}; +#endif + +static void t0_gpio_init(void) +{ + int err; + unsigned int gpio; + +#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS + /* Main Microphone BIAS */ + err = gpio_request(GPIO_MIC_BIAS_EN, "MAIN MIC"); + if (err) { + pr_err(KERN_ERR "MIC_BIAS_EN GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_MIC_BIAS_EN, 0); + gpio_free(GPIO_MIC_BIAS_EN); +#endif + +#ifdef CONFIG_SND_USE_SUB_MIC + /* Sub Microphone BIAS */ + err = gpio_request(GPIO_SUB_MIC_BIAS_EN, "SUB MIC"); + if (err) { + pr_err(KERN_ERR "SUB_MIC_BIAS_EN GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_SUB_MIC_BIAS_EN, 0); + gpio_free(GPIO_SUB_MIC_BIAS_EN); +#endif + +#ifdef CONFIG_SND_USE_LINEOUT_SWITCH + err = gpio_request(GPIO_VPS_SOUND_EN, "LINEOUT_EN"); + if (err) { + pr_err(KERN_ERR "LINEOUT_EN GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_VPS_SOUND_EN, 0); + gpio_free(GPIO_VPS_SOUND_EN); +#endif + +#if defined(CONFIG_SND_DUOS_MODEM_SWITCH) + /* Modem selection for DUOS model */ + err = gpio_request(GPIO_AUDIO_PCM_SEL, "PCM_SEL"); + if (err) { + pr_err(KERN_ERR "PCM switch GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_AUDIO_PCM_SEL, 0); + gpio_free(GPIO_AUDIO_PCM_SEL); +#endif + +#ifdef CONFIG_JACK_GROUND_DET + if (system_rev >= 3) + gpio = GPIO_G_DET_N_REV03; + else + gpio = GPIO_G_DET_N; + + err = gpio_request(gpio, "GROUND DET"); + if (err) { + pr_err(KERN_ERR "G_DET_N GPIO set error!\n"); + return; + } + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + s5p_register_gpio_interrupt(gpio); + irq_set_irq_type(gpio_to_irq(gpio), IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING | IRQF_ONESHOT); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); +#endif + +#ifdef CONFIG_JACK_FET + if (system_rev >= 4) { + err = gpio_request(GPIO_EAR_BIAS_DISCHARGE, "EAR DISCHARGE"); + if (err) { + pr_err("EAR_BIAS_DISCHARGE GPIO set error!\n"); + return; + } + gpio_direction_output(GPIO_EAR_BIAS_DISCHARGE, 0); + gpio_free(GPIO_EAR_BIAS_DISCHARGE); + } + +#endif + +#ifdef CONFIG_FM_SI4705 + if (system_rev >= 3) + si47xx_data.gpio_rst = GPIO_FM_RST_REV03; + + if (gpio_is_valid(si47xx_data.gpio_rst)) { + if (gpio_request(si47xx_data.gpio_rst, "FM_RST")) + debug(KERN_ERR "Failed to request " + "FM_RST!\n\n"); + gpio_direction_output(si47xx_data.gpio_rst, GPIO_LEVEL_LOW); + } +#endif +} + +static void t0_set_lineout_switch(int on) +{ +#ifdef CONFIG_SND_USE_LINEOUT_SWITCH + gpio_set_value(GPIO_VPS_SOUND_EN, on); + pr_info("%s: lineout switch on = %d\n", __func__, on); +#endif +} + +static void t0_set_ext_main_mic(int on) +{ +#ifdef CONFIG_SND_SOC_USE_EXTERNAL_MIC_BIAS + /* Main Microphone BIAS */ + gpio_set_value(GPIO_MIC_BIAS_EN, on); + + if (on) + msleep(100); + + pr_info("%s: main_mic bias on = %d\n", __func__, on); +#endif +} + +static void t0_set_ext_sub_mic(int on) +{ +#ifdef CONFIG_SND_USE_SUB_MIC + /* Sub Microphone BIAS */ + gpio_set_value(GPIO_SUB_MIC_BIAS_EN, on); + + if (on) + msleep(100); + + pr_info("%s: sub_mic bias on = %d\n", __func__, on); +#endif +} + +#ifdef CONFIG_JACK_GROUND_DET +static int t0_get_ground_det_value(void) +{ + unsigned int g_det_gpio; + + if (system_rev >= 3) + g_det_gpio = GPIO_G_DET_N_REV03; + else + g_det_gpio = GPIO_G_DET_N; + return gpio_get_value(g_det_gpio); +} + +static int t0_get_ground_det_irq_num(void) +{ + unsigned int g_det_gpio; + + if (system_rev >= 3) + g_det_gpio = GPIO_G_DET_N_REV03; + else + g_det_gpio = GPIO_G_DET_N; + return gpio_to_irq(g_det_gpio); +} +#endif + +#if defined(CONFIG_SND_DUOS_MODEM_SWITCH) +static void t0_set_modem_switch(int on) +{ + /* Modem selection for DUOS model */ + gpio_set_value(GPIO_AUDIO_PCM_SEL, on); + pr_info("%s: t0_set_modem_switch = %d\n", __func__, on); +} +#endif + +struct exynos_sound_platform_data t0_sound_pdata __initdata = { + .set_lineout_switch = t0_set_lineout_switch, + .set_ext_main_mic = t0_set_ext_main_mic, + .set_ext_sub_mic = t0_set_ext_sub_mic, +#ifdef CONFIG_JACK_GROUND_DET + .get_ground_det_value = t0_get_ground_det_value, + .get_ground_det_irq_num = t0_get_ground_det_irq_num, +#endif +#if defined(CONFIG_SND_DUOS_MODEM_SWITCH) + .set_modem_switch = t0_set_modem_switch, +#endif + .dcs_offset_l = -9, + .dcs_offset_r = -7, +}; + +static struct platform_device *t0_sound_devices[] __initdata = { +#if defined(CONFIG_FM_SI4705) + &s3c_device_i2c19, +#endif +}; + +void __init midas_sound_init(void) +{ + pr_info("Sound: start %s\n", __func__); + +#if defined(CONFIG_MACH_T0_EUR_LTE) + t0_sound_pdata.dcs_offset_l = -11; + t0_sound_pdata.dcs_offset_r = -8; +#endif + + t0_gpio_init(); + + platform_add_devices(t0_sound_devices, + ARRAY_SIZE(t0_sound_devices)); + + pr_info("%s: set sound platform data for T0 device\n", __func__); + if (exynos_sound_set_platform_data(&t0_sound_pdata)) + pr_err("%s: failed to register sound pdata\n", __func__); + + SET_PLATDATA_CODEC(NULL); + i2c_register_board_info(I2C_NUM_CODEC, i2c_wm1811, + ARRAY_SIZE(i2c_wm1811)); + +#if defined(CONFIG_FM_SI4705) + i2c_register_board_info(19, i2c_devs19_emul, + ARRAY_SIZE(i2c_devs19_emul)); +#endif + +} diff --git a/arch/arm/mach-exynos/tmu.c b/arch/arm/mach-exynos/tmu.c index cdfd916..d602835 100644 --- a/arch/arm/mach-exynos/tmu.c +++ b/arch/arm/mach-exynos/tmu.c @@ -67,11 +67,12 @@ static struct workqueue_struct *tmu_monitor_wq; static DEFINE_MUTEX(tmu_lock); -#if (defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)) \ - && defined(CONFIG_VIDEO_MALI400MP) +#if (defined(CONFIG_CPU_EXYNOS4212) || defined(CONFIG_CPU_EXYNOS4412)) +#if defined(CONFIG_VIDEO_MALI400MP) extern int mali_voltage_lock_init(void); extern int mali_voltage_lock_push(int lock_vol); extern int mali_voltage_lock_pop(void); +#endif #define CONFIG_TC_VOLTAGE /* Temperature compensated voltage */ #endif @@ -468,6 +469,7 @@ static void exynos_interrupt_enable(struct s5p_tmu_info *info, int enable) __raw_writel(0x0, info->tmu_base + EXYNOS4_TMU_INTEN); } +#if defined(CONFIG_TC_VOLTAGE) /** * exynos_tc_volt - locks or frees vdd_arm, vdd_mif/int and vdd_g3d for * temperature compensation. @@ -481,7 +483,7 @@ static int exynos_tc_volt(struct s5p_tmu_info *info, int enable) static int usage; int ret = 0; - if (!info) + if (!info || !(info->dev)) return -EPERM; data = info->dev->platform_data; @@ -501,12 +503,14 @@ static int exynos_tc_volt(struct s5p_tmu_info *info, int enable) if (ret) goto err_lock; #endif +#if defined(CONFIG_VIDEO_MALI400MP) ret = mali_voltage_lock_push(data->temp_compensate.g3d_volt); if (ret < 0) { pr_err("TMU: g3d_push error: %u uV\n", data->temp_compensate.g3d_volt); goto err_lock; } +#endif } else { exynos_cpufreq_lock_free(DVFS_LOCK_ID_TMU); #ifdef CONFIG_BUSFREQ_OPP @@ -514,11 +518,13 @@ static int exynos_tc_volt(struct s5p_tmu_info *info, int enable) if (ret) goto err_unlock; #endif +#if defined(CONFIG_VIDEO_MALI400MP) ret = mali_voltage_lock_pop(); if (ret < 0) { pr_err("TMU: g3d_pop error\n"); goto err_unlock; } +#endif } usage = enable; pr_info("TMU: %s is ok!\n", enable ? "lock" : "unlock"); @@ -529,6 +535,7 @@ err_unlock: pr_err("TMU: %s is fail.\n", enable ? "lock" : "unlock"); return ret; } +#endif static void exynos4_handler_tmu_state(struct work_struct *work) { @@ -1104,7 +1111,7 @@ static int __devinit s5p_tmu_probe(struct platform_device *pdev) &info->cpulevel_tc) < 0) { dev_err(&pdev->dev, "cpufreq_get_level error\n"); ret = -EINVAL; - goto err_nomem; + goto err_nores; } #ifdef CONFIG_BUSFREQ_OPP /* To lock bus frequency in OPP mode */ @@ -1112,13 +1119,13 @@ static int __devinit s5p_tmu_probe(struct platform_device *pdev) if (info->bus_dev < 0) { dev_err(&pdev->dev, "Failed to get_dev\n"); ret = -EINVAL; - goto err_nomem; + goto err_nores; } if (exynos4x12_find_busfreq_by_volt(pdata->temp_compensate.bus_volt, &info->busfreq_tc)) { dev_err(&pdev->dev, "get_busfreq_value error\n"); ret = -EINVAL; - goto err_nomem; + goto err_nores; } #endif pr_info("%s: cpufreq_level[%u], busfreq_value[%u]\n", @@ -1243,9 +1250,11 @@ static int __devinit s5p_tmu_probe(struct platform_device *pdev) if (exynos_tc_volt(info, 1) < 0) pr_err("TMU: lock error!\n"); } +#if defined(CONFIG_VIDEO_MALI400MP) if (mali_voltage_lock_init()) pr_err("Failed to initialize mail voltage lock.\n"); #endif +#endif /* initialize tmu_state */ queue_delayed_work_on(0, tmu_monitor_wq, &info->polling, @@ -1355,7 +1364,7 @@ static int s5p_tmu_resume(struct platform_device *pdev) struct s5p_tmu_info *info = platform_get_drvdata(pdev); struct s5p_platform_tmu *data; - if (!info) + if (!info || !(info->dev)) return -EAGAIN; data = info->dev->platform_data; diff --git a/arch/arm/mach-exynos/u1-gpio.c b/arch/arm/mach-exynos/u1-gpio.c index 434ccd2..dd1385d 100644 --- a/arch/arm/mach-exynos/u1-gpio.c +++ b/arch/arm/mach-exynos/u1-gpio.c @@ -31,6 +31,10 @@ static struct gpio_init_data u1_init_gpios[] = { {EXYNOS4_GPC0(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* TDMB_EN */ #endif +#if defined(CONFIG_LEDS_GPIO) + {EXYNOS4_GPB(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, +#endif #if defined(CONFIG_ISDBT_FC8100) {EXYNOS4210_GPE1(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* ISDBT_RST_N */ @@ -130,6 +134,38 @@ static struct gpio_init_data u1_init_gpios[] = { S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPK2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* PS_ALS_SDA_2.8V */ +#if defined(CONFIG_TARGET_LOCALE_NA) + /* GPIO_BT_EN */ + {EXYNOS4_GPL0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* GPIO_BT_nRST */ + {EXYNOS4_GPL1(0), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ + +#if defined(CONFIG_TARGET_LOCALE_NA) + /* PS_ALS_SCL_2.8V */ + {EXYNOS4_GPK3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + /* NC */ + /*BUCK2_EN for PMIC 8997*/ + {EXYNOS4_GPL0(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /*WLAN_EN*/ + {EXYNOS4_GPL1(2), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /*CHG_ING_N*/ + {EXYNOS4_GPL2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + /*TA_nCONNECTED*/ + {EXYNOS4_GPL2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + /* FUEL_ALERT */ + {EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ + +#if !defined(CONFIG_TARGET_LOCALE_NA) {EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */ {EXYNOS4_GPK3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -142,14 +178,18 @@ static struct gpio_init_data u1_init_gpios[] = { S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */ {EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */ + {EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */ +#endif /*CONFIG_TARGET_LOCALE_NA*/ + + #if defined(CONFIG_MACH_U1_KOR_LGT) {EXYNOS4_GPL0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ {EXYNOS4_GPL1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, /* NC */ #endif - {EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */ + {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */ {EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -157,33 +197,81 @@ static struct gpio_init_data u1_init_gpios[] = { {EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_FUEL_ALERT */ {EXYNOS4_GPX3(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_BT_WAKE */ {EXYNOS4_GPX3(2), S3C_GPIO_SFN(GPIO_DET_35_AF), S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_DET_35 */ {EXYNOS4_GPX3(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, +#if defined(CONFIG_TARGET_LOCALE_NA) + /* NC */ + {EXYNOS4_GPX3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#else {EXYNOS4_GPX3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ + +#if defined(CONFIG_TARGET_LOCALE_NA) + /* NC*/ + {EXYNOS4_GPX3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif /* CONFIG_TARGET_LOCALE_NA */ + #if defined(CONFIG_TARGET_LOCALE_NTT) {EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, #endif +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) + /* SIDE_CS */ + {EXYNOS4_GPY0(2), S3C_GPIO_SFN(3), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, +#else {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif /*CONFIG_MACH_U1_NA_SPR*/ + +#if defined(CONFIG_TARGET_LOCALE_NA) + /*USBHUB_I2C_SCL*/ + {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + /*USBHUB_I2C_SDA*/ + {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, +#else {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif /* CONFIG_TARGET_LOCALE_NA */ + {EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) + /* westbridge changes */ + /* SIDE_RST */ + {EXYNOS4_GPY1(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + /* SIDE_CLE */ + {EXYNOS4_GPY2(0), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, + /* SIDE_ALE */ + {EXYNOS4_GPY2(1), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1,}, + /* SIDE_RB */ + {EXYNOS4_GPY2(2), S3C_GPIO_SFN(2), S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, +#else {EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -192,6 +280,7 @@ static struct gpio_init_data u1_init_gpios[] = { S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1,}, {EXYNOS4_GPY2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif /* CONFIG_MACH_U1_NA_SPR */ {EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -200,6 +289,8 @@ static struct gpio_init_data u1_init_gpios[] = { S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + +#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) {EXYNOS4_GPY5(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY5(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -216,6 +307,7 @@ static struct gpio_init_data u1_init_gpios[] = { S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY5(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#endif {EXYNOS4_GPY6(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY6(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, @@ -232,16 +324,100 @@ static struct gpio_init_data u1_init_gpios[] = { S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, {EXYNOS4_GPY6(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, +#ifdef CONFIG_WIMAX_CMC + /*WIMAX_EEP_SEL*/ + {EXYNOS4210_GPE1(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ONE, + S3C_GPIO_PULL_UP, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_EN */ + {EXYNOS4210_GPE1(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WLAN_WAKE */ + {EXYNOS4_GPD0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_SDIO_CLK */ + {EXYNOS4_GPK3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_SDIO_CMD */ + {EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_SDIO_D(0) */ + {EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_SDIO_D(1) */ + {EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_SDIO_D(2) */ + {EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_SDIO_D(3) */ + {EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_EEP_SCL_1.8V */ + { EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_EEP_SDA_1.8V */ + {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, + /* WIMAX_MODE1 */ + {EXYNOS4_GPY3(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_MODE0 */ + { EXYNOS4_GPY3(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_CON1 */ + {EXYNOS4_GPL2(7), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_CON0 */ + {EXYNOS4_GPL2(6), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_WAKEUP */ + {EXYNOS4_GPX1(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_CON2 */ + { EXYNOS4210_GPE2(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_INT */ + {EXYNOS4_GPX1(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_NONE, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /* WIMAX_RESET_N */ + {EXYNOS4_GPA0(5), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, + /*WIMAX_DBGEN_2.8V */ + {EXYNOS4_GPA0(4), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, + S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV4}, +#endif }; /* this table only for u1 board */ static unsigned int u1_sleep_gpio_table[][3] = { + {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_TARGET_LOCALE_NA) + /* BT_UART_RXD */ + {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* BT_UART_TXD */ + {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#else /* CONFIG_TARGET_LOCALE_NA */ {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_UP}, {EXYNOS4_GPA0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + +#if defined(CONFIG_WIMAX_CMC) && defined(CONFIG_TARGET_LOCALE_NA) + /* WIMAX_DBGEN_2.8V */ + {EXYNOS4_GPA0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* WIMAX_RESET_N */ + {EXYNOS4_GPA0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#else /* WIMAX_CMC & CONFIG_TARGET_LOCALE_NA */ {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + +#if defined(CONFIG_TARGET_LOCALE_NA) + /* BT_RTS */ + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#else + {EXYNOS4_GPA0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ + #if defined(CONFIG_MACH_U1_KOR_LGT) {EXYNOS4_GPA0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, #elif defined(CONFIG_TARGET_LOCALE_NTT) @@ -254,6 +430,21 @@ static unsigned int u1_sleep_gpio_table[][3] = { #else {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif + +#if defined(CONFIG_TARGET_LOCALE_NA) + /* AP_RXD */ + { EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* AP_TXD */ + { EXYNOS4_GPA1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* TSP_SDA_2.8V */ + { EXYNOS4_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* TSP_SCL_2.8v */ + { EXYNOS4_GPA1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* USBHUB_TCXO_EN */ + { EXYNOS4_GPA1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* SVC_LED_B */ + { EXYNOS4_GPA1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#else #if defined(CONFIG_MACH_U1_KOR_LGT) {EXYNOS4_GPA1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, #else @@ -268,6 +459,7 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, #endif {EXYNOS4_GPA1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) {EXYNOS4_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -285,24 +477,38 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, #else {EXYNOS4_GPB(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_LEDS_GPIO) + {EXYNOS4_GPB(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#else /*CONFIG_LEDS_GPIO*/ + /* SVC_LED_R */ {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif /*CONFIG_LEDS_GPIO*/ +#if defined(CONFIG_MACH_U1_NA_USCC) + { EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #endif {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE},/* NC */ #if defined(CONFIG_TDMB) || defined(CONFIG_TDMB_MODULE) {EXYNOS4_GPC0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, #elif defined(CONFIG_ISDBT_FC8100) {EXYNOS4_GPC0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, #else {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif +#endif /*CONFIG_ISDBT_FC8100 CONFIG_TDMB CONFIG_TDMB_MODULE */ + +#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) + /* NC */ {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif /*CONFIG_MACH_U1_NA_SPR*/ {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -330,6 +536,17 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_TARGET_LOCALE_NA) + /* EBI2_WE_N */ + { EXYNOS4210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* CP_DPRAM_CS_N */ + { EXYNOS4210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* EBI2_OE_N */ + { EXYNOS4210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { EXYNOS4210_GPE0(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + /* NAND_ADV_N */ + { EXYNOS4210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#else #if !defined(CONFIG_VIDEO_TSI) {EXYNOS4210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ #if defined(CONFIG_MACH_U1_KOR_LGT) @@ -355,6 +572,8 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4210_GPE1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4210_GPE1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#endif /* CONFIG_TARGET_LOCALE_NA */ + #if !defined(CONFIG_VIDEO_TSI) #if defined(CONFIG_MACH_U1_KOR_LGT) {EXYNOS4210_GPE1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -382,6 +601,25 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4210_GPE2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4210_GPE2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) + {EXYNOS4210_GPE3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {EXYNOS4210_GPE4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE4(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {EXYNOS4210_GPE4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#else /*MACH_U1_NA_SPR changes*/ {EXYNOS4210_GPE3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4210_GPE3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4210_GPE3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -399,7 +637,70 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4210_GPE4(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4210_GPE4(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4210_GPE4(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif +#if defined(CONFIG_TARGET_LOCALE_NA) + /* LCD_HSYNC */ + { EXYNOS4_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_VSYNC */ + { EXYNOS4_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_DE */ + { EXYNOS4_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_PCLK */ + { EXYNOS4_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(0) */ + { EXYNOS4_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(1) */ + { EXYNOS4_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(2) */ + { EXYNOS4_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(3) */ + { EXYNOS4_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(4) */ + { EXYNOS4_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(5) */ + { EXYNOS4_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(6) */ + { EXYNOS4_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(7) */ + { EXYNOS4_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(8) */ + { EXYNOS4_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(9) */ + { EXYNOS4_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(10) */ + { EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(11) */ + { EXYNOS4_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(12) */ + { EXYNOS4_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(13) */ + { EXYNOS4_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(14) */ + { EXYNOS4_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(15) */ + { EXYNOS4_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(16) */ + { EXYNOS4_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(17) */ + { EXYNOS4_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(18) */ + { EXYNOS4_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(19) */ + { EXYNOS4_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(20) */ + { EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(21) */ + { EXYNOS4_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(22) */ + { EXYNOS4_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* LCD_D(23) */ + { EXYNOS4_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* MHL_RST */ + { EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* MHL_INT */ + { EXYNOS4_GPF3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#else /*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -434,6 +735,8 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPF3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {EXYNOS4210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -447,8 +750,11 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4210_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_MACH_U1_NA_USCC) + {EXYNOS4210_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4210_GPJ1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - +#endif/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4_GPK0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -465,6 +771,22 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPK1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) + /*WIFI_CLK*/ + {EXYNOS4_GPK2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /*WIFI_CMD*/ + {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /*PS_ALS_SDA_2.8V*/ + {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /*WIFI_D0*/ + {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /*WIFI_D1*/ + {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /*WIFI_D2*/ + {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /*WIFI_D3*/ + {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#else {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -472,8 +794,14 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif +#if defined(CONFIG_TARGET_LOCALE_NA) + /* WIMAX_SDIO_CLK */ + { EXYNOS4_GPK3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#else/*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif /* CONFIG_TARGET_LOCALE_NA */ {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -486,10 +814,14 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_TARGET_LOCALE_NA) + /* 3_TOUCH_INT */ + { EXYNOS4_GPL0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else /*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPL0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL1(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, @@ -500,11 +832,12 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#if !defined(CONFIG_TARGET_LOCALE_NA) #if defined(CONFIG_PN544) && (defined(CONFIG_TARGET_LOCALE_KOR) \ || defined(CONFIG_TARGET_LOCALE_EUR_U1_NFC)) {EXYNOS4_GPL2(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, -#elif defined(CONFIG_TARGET_LOCALE_NTT) +#elif defined(CONFIG_TARGET_LOCALE_NTT) || defined(CONFIG_MACH_U1_NA_USCC) {EXYNOS4_GPL2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, #else @@ -515,7 +848,9 @@ static unsigned int u1_sleep_gpio_table[][3] = { #endif {EXYNOS4_GPL2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, #endif +#endif/*CONFIG_TARGET_LOCALE_NA*/ +#if !defined(CONFIG_TARGET_LOCALE_NA) #if defined(CONFIG_PN544) && defined(CONFIG_TARGET_LOCALE_KOR) {EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, @@ -527,6 +862,7 @@ static unsigned int u1_sleep_gpio_table[][3] = { #endif {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, #endif +#endif #if defined(CONFIG_MACH_U1_KOR_LGT) {EXYNOS4_GPY0(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -537,20 +873,41 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPY1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, -#else - {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#else/*CONFIG_MACH_U1_KOR_LGT*/ +#if !defined(CONFIG_TARGET_LOCALE_NA) + /* NC */ + {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if !defined(CONFIG_TARGET_LOCALE_NA) + /* NC */ + {EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* NC */ + {EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif /* CONFIG_TARGET_LOCALE_NA */ +#if defined(CONFIG_TARGET_LOCALE_NA) + /*USBHUB_I2C_SCL*/ + { EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /*USBHUB_I2C_SDA*/ + { EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#else /* CONFIG_TARGET_LOCALE_NA */ {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif /*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -#endif - - {EXYNOS4_GPY2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +/*!CONFIG_MACH_U1_NA_SPR*/ +#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) + /* NC */ + {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif /*CONFIG_MACH_U1_NA_SPR*/ +#endif/*CONFIG_MACH_U1_KOR_LGT*/ +#if !defined(CONFIG_TARGET_LOCALE_NA) + /* NC */ + {EXYNOS4_GPY2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* NC */ + {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ #if defined(CONFIG_MACH_U1_KOR_LGT) {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, #else @@ -558,7 +915,11 @@ static unsigned int u1_sleep_gpio_table[][3] = { #endif {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +/*CONFIG_MACH_U1_NA_SPR*/ +#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) + /*SIDE_CLK_EN*/ {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#endif /*CONFIG_MACH_U1_NA_SPR*/ #if defined(CONFIG_MACH_U1_KOR_LGT) {EXYNOS4_GPY3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, @@ -597,24 +958,41 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPY6(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */ {EXYNOS4_GPY6(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, /* NC */ #else +#if defined(CONFIG_MACH_U1_NA_USCC) + {EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined(CONFIG_MACH_U1_NA_USCC) + {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#else/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif/*CONFIG_MACH_U1_NA_USCC*/ {EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +/*CONFIG_TARGET_LOCALE_NA*/ +#if !defined(CONFIG_TARGET_LOCALE_NA) + /*WIMAX_IF_MODE0*/ {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /*WIMAX_IF_MODE1*/ {EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ +#if !defined(CONFIG_TARGET_LOCALE_NA) + /*NC*/ + {EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif /*CONFIG_TARGET_LOCALE_NA*/ {EXYNOS4_GPY4(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPY4(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - +#if !defined(CONFIG_MACH_U1_NA_SPR) && !defined(CONFIG_MACH_U1_NA_USCC) + /*SIDE_D(0)*/ {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, @@ -622,7 +1000,9 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, {EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /*SIDE_D(7)*/ {EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif /*CONFIG_MACH_U1_NA_SPR*/ {EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ @@ -641,6 +1021,64 @@ static unsigned int u1_sleep_gpio_table[][3] = { {EXYNOS4_GPZ(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ + + +#ifdef CONFIG_TARGET_LOCALE_NA + /*Wimax sleep gpio config start*/ + /* WIMAX_USB_EN */ +#ifdef CONFIG_WIMAX_CMC + { EXYNOS4_GPB(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_DBGEN_28V, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_I2C_CON, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_INT, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_WAKEUP, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_IF_MODE1, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_IF_MODE0, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_CON0, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_CON1, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_CON2, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_EN , S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_WIMAX_RESET_N, S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { GPIO_CMC_SCL_18V, S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { GPIO_CMC_SDA_18V, S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif/*Wimax sleep gpio config end*/ +#endif /* CONFIG_TARGET_LOCALE_NA */ + +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) + /* SIDE_CLK_EN */ + { EXYNOS4_GPY2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + /* SIDE_INT */ + { EXYNOS4_GPC0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_RST */ + { EXYNOS4_GPY1(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_WAKEUP */ + { EXYNOS4_GPY4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_CS */ + { EXYNOS4_GPY0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_CLE */ + { EXYNOS4_GPY2(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_ALE */ + { EXYNOS4_GPY2(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_WE */ + { EXYNOS4_GPY0(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_RE */ + { EXYNOS4_GPY0(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_RB */ + { EXYNOS4_GPY2(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_D0 */ + { EXYNOS4_GPY5(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_D1 */ + { EXYNOS4_GPY5(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY5(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY5(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY5(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY5(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { EXYNOS4_GPY5(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* SIDE_D7 */ + { EXYNOS4_GPY5(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + /* AP_T_FLASH_DETECT */ + { EXYNOS4_GPC0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +#endif }; void u1_config_gpio_table(void) diff --git a/arch/arm/mach-exynos/s2plus-panel.c b/arch/arm/mach-exynos/u1-na-spr-panel.c index 58dd374..fb11951 100644 --- a/arch/arm/mach-exynos/s2plus-panel.c +++ b/arch/arm/mach-exynos/u1-na-spr-panel.c @@ -16,49 +16,64 @@ #include <linux/kernel.h> #include <linux/types.h> #include <linux/ld9040.h> -#include "s2plus-panel.h" +#define SLEEPMSEC 0x1000 +#define ENDDEF 0x2000 +#define DEFMASK 0xFF00 +#define COMMAND_ONLY 0xFE +#define DATA_ONLY 0xFF -static const unsigned short SEQ_SM2_ELVSS_44[] = { - 0xB2, 0x15, - DATA_ONLY, 0x15, - DATA_ONLY, 0x15, - DATA_ONLY, 0x15, - ENDDEF, 0x00 -}; -static const unsigned short SEQ_SM2_ELVSS_37[] = { - 0xB2, 0x1C, - DATA_ONLY, 0x1C, - DATA_ONLY, 0x1C, - DATA_ONLY, 0x1C, +static const unsigned short SEQ_USER_SETTING[] = { + 0xF0, 0x5A, + + DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short SEQ_SM2_ELVSS_34[] = { - 0xB2, 0x1F, - DATA_ONLY, 0x1F, - DATA_ONLY, 0x1F, - DATA_ONLY, 0x1F, +static const unsigned short SEQ_DISPCTL[] = { + 0xF2, 0x02, + + DATA_ONLY, 0x06, + DATA_ONLY, 0x0A, + DATA_ONLY, 0x10, + DATA_ONLY, 0x10, ENDDEF, 0x00 }; -static const unsigned short SEQ_SM2_ELVSS_30[] = { - 0xB2, 0x23, - DATA_ONLY, 0x23, - DATA_ONLY, 0x23, - DATA_ONLY, 0x23, +static const unsigned short SEQ_GTCON[] = { + 0xF7, 0x09, + ENDDEF, 0x00 }; -static const unsigned short *SEQ_SM2_ELVSS_set[] = { - SEQ_SM2_ELVSS_30, - SEQ_SM2_ELVSS_34, - SEQ_SM2_ELVSS_37, - SEQ_SM2_ELVSS_44, +static const unsigned short SEQ_PANEL_CONDITION[] = { + 0xF8, 0x05, + DATA_ONLY, 0x5E, + DATA_ONLY, 0x96, + DATA_ONLY, 0x6B, + DATA_ONLY, 0x7D, + DATA_ONLY, 0x0D, + DATA_ONLY, 0x3F, + DATA_ONLY, 0x00, + DATA_ONLY, 0x00, + DATA_ONLY, 0x32, + DATA_ONLY, 0x00, + DATA_ONLY, 0x00, + DATA_ONLY, 0x00, + DATA_ONLY, 0x00, + DATA_ONLY, 0x00, + DATA_ONLY, 0x00, + DATA_ONLY, 0x07, + DATA_ONLY, 0x05, + DATA_ONLY, 0x1F, + DATA_ONLY, 0x1F, + DATA_ONLY, 0x1F, + DATA_ONLY, 0x00, + DATA_ONLY, 0x00, + ENDDEF, 0x00 }; - static const unsigned short SEQ_PWR_CTRL[] = { 0xF4, 0x0A, @@ -70,109 +85,181 @@ static const unsigned short SEQ_PWR_CTRL[] = { ENDDEF, 0x00 }; +static const unsigned short SEQ_SLPOUT[] = { + 0x11, COMMAND_ONLY, + SLEEPMSEC, 120, + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_SLPIN[] = { + 0x10, COMMAND_ONLY, + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_DISPON[] = { + 0x29, COMMAND_ONLY, + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_DISPOFF[] = { + 0x28, COMMAND_ONLY, + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_ACL_ON[] = { + 0xC0, 0x01, + + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_ACL_OFF[] = { + 0xC0, 0x00, + + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_ACL_40P[] = { + 0xC1, 0x4D, + + DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, + DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, + DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, + DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, + DATA_ONLY, 0x06, DATA_ONLY, 0x11, DATA_ONLY, 0x1A, DATA_ONLY, 0x20, + DATA_ONLY, 0x25, DATA_ONLY, 0x29, DATA_ONLY, 0x2D, DATA_ONLY, 0x30, + DATA_ONLY, 0x33, DATA_ONLY, 0x35, + + 0xC0, 0x01, + + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_ACL_50P[] = { + 0xC1, 0x4D, + + DATA_ONLY, 0x96, DATA_ONLY, 0x1D, DATA_ONLY, 0x00, DATA_ONLY, 0x00, + DATA_ONLY, 0x01, DATA_ONLY, 0xDF, DATA_ONLY, 0x00, DATA_ONLY, 0x00, + DATA_ONLY, 0x03, DATA_ONLY, 0x1F, DATA_ONLY, 0x00, DATA_ONLY, 0x00, + DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x00, DATA_ONLY, 0x01, + DATA_ONLY, 0x08, DATA_ONLY, 0x16, DATA_ONLY, 0x22, DATA_ONLY, 0x2B, + DATA_ONLY, 0x31, DATA_ONLY, 0x37, DATA_ONLY, 0x3B, DATA_ONLY, 0x3F, + DATA_ONLY, 0x43, DATA_ONLY, 0x46, + + 0xC0, 0x01, + + ENDDEF, 0x00 +}; + +static const unsigned short *ACL_cutoff_set[] = { + SEQ_ACL_OFF, + SEQ_ACL_40P, + SEQ_ACL_50P, +}; + + +static const unsigned short SEQ_ELVSS_ON[] = { + 0xB1, 0x0F, -/* LD9040, 4.27", SM2 A1 Panel Gamma Data */ -static const unsigned short ld9040_sm2_a1_22_300[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xB9, - DATA_ONLY, 0x00, - DATA_ONLY, 0xA3, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xA6, - DATA_ONLY, 0x9F, - DATA_ONLY, 0xB8, - DATA_ONLY, 0x00, - DATA_ONLY, 0xBB, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xA8, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xA3, - DATA_ONLY, 0xB9, DATA_ONLY, 0x00, - DATA_ONLY, 0xCE, - 0xFB, 0x02, - DATA_ONLY, 0x5A, + DATA_ONLY, 0x16, + ENDDEF, 0x00 +}; + +/* ELVSS set for SM2 4.52" LCD */ +static const unsigned short SEQ_SM2_ELVSS_45[] = { + 0xB2, 0x14, + DATA_ONLY, 0x14, + DATA_ONLY, 0x14, + DATA_ONLY, 0x14, + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_SM2_ELVSS_38[] = { + 0xB2, 0x1B, + DATA_ONLY, 0x1B, + DATA_ONLY, 0x1B, + DATA_ONLY, 0x1B, + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_SM2_ELVSS_35[] = { + 0xB2, 0x1E, + DATA_ONLY, 0x1E, + DATA_ONLY, 0x1E, + DATA_ONLY, 0x1E, + ENDDEF, 0x00 +}; + +static const unsigned short SEQ_SM2_ELVSS_31[] = { + 0xB2, 0x22, + DATA_ONLY, 0x22, + DATA_ONLY, 0x22, + DATA_ONLY, 0x22, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_290[] = { - 0xF9, 0x2E, +static const unsigned short *SEQ_SM2_ELVSS_set[] = { + SEQ_SM2_ELVSS_31, + SEQ_SM2_ELVSS_35, + SEQ_SM2_ELVSS_38, + SEQ_SM2_ELVSS_45, +}; + +/* 160cd for SM2 4.52" LCD : default */ +static const unsigned short SEQ_SM2_GAMMA_SET1[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xBA, DATA_ONLY, 0xB1, + DATA_ONLY, 0xC5, + DATA_ONLY, 0x00, + DATA_ONLY, 0x75, + DATA_ONLY, 0x1C, DATA_ONLY, 0xB0, - DATA_ONLY, 0xA8, - DATA_ONLY, 0xBA, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xC2, DATA_ONLY, 0x00, - DATA_ONLY, 0xA1, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xA7, - DATA_ONLY, 0xA0, + DATA_ONLY, 0x8C, + DATA_ONLY, 0x1E, DATA_ONLY, 0xB7, + DATA_ONLY, 0xB4, + DATA_ONLY, 0xAD, + DATA_ONLY, 0xC1, DATA_ONLY, 0x00, - DATA_ONLY, 0xB9, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xA2, - DATA_ONLY, 0xB8, - DATA_ONLY, 0x00, - DATA_ONLY, 0xCC, + DATA_ONLY, 0x98, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_280[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xBB, - DATA_ONLY, 0x00, - DATA_ONLY, 0xA0, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xA8, - DATA_ONLY, 0xA2, - DATA_ONLY, 0xB7, - DATA_ONLY, 0x00, - DATA_ONLY, 0xB8, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xA4, - DATA_ONLY, 0xB9, - DATA_ONLY, 0x00, - DATA_ONLY, 0xCA, +static const unsigned short SEQ_GAMMA_CTRL[] = { 0xFB, 0x02, + DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_270[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xBD, +static const unsigned short ld9040_sm2_22_300[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xAB, + DATA_ONLY, 0xBC, DATA_ONLY, 0x00, - DATA_ONLY, 0x9E, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA6, + DATA_ONLY, 0x9D, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB5, DATA_ONLY, 0xA8, - DATA_ONLY, 0xA3, - DATA_ONLY, 0xB8, + DATA_ONLY, 0xBA, DATA_ONLY, 0x00, - DATA_ONLY, 0xB5, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xA4, - DATA_ONLY, 0xB4, + DATA_ONLY, 0xBA, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xA6, + DATA_ONLY, 0xB9, DATA_ONLY, 0x00, DATA_ONLY, 0xC8, 0xFB, 0x02, @@ -180,26 +267,26 @@ static const unsigned short ld9040_sm2_a1_22_270[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_260[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB1, +static const unsigned short ld9040_sm2_22_290[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xAB, + DATA_ONLY, 0xBC, + DATA_ONLY, 0x00, + DATA_ONLY, 0x9A, + DATA_ONLY, 0x1C, DATA_ONLY, 0xB3, + DATA_ONLY, 0xB5, DATA_ONLY, 0xA8, - DATA_ONLY, 0xBD, - DATA_ONLY, 0x00, - DATA_ONLY, 0x9C, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA5, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xA2, - DATA_ONLY, 0xB9, + DATA_ONLY, 0xBA, DATA_ONLY, 0x00, - DATA_ONLY, 0xB2, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xA4, + DATA_ONLY, 0xB7, + DATA_ONLY, 0x1E, DATA_ONLY, 0xB4, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xA6, + DATA_ONLY, 0xB9, DATA_ONLY, 0x00, DATA_ONLY, 0xC5, 0xFB, 0x02, @@ -207,52 +294,52 @@ static const unsigned short ld9040_sm2_a1_22_260[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_250[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xBC, +static const unsigned short ld9040_sm2_22_280[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xAC, + DATA_ONLY, 0xBD, DATA_ONLY, 0x00, - DATA_ONLY, 0x9A, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA5, + DATA_ONLY, 0x97, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xB6, DATA_ONLY, 0xA9, - DATA_ONLY, 0xA4, - DATA_ONLY, 0xB9, + DATA_ONLY, 0xBB, DATA_ONLY, 0x00, - DATA_ONLY, 0xAF, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xB9, + DATA_ONLY, 0xB3, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xA7, + DATA_ONLY, 0xBA, DATA_ONLY, 0x00, - DATA_ONLY, 0xC2, + DATA_ONLY, 0xC1, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_240[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAA, +static const unsigned short ld9040_sm2_22_270[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xAC, DATA_ONLY, 0xBE, DATA_ONLY, 0x00, - DATA_ONLY, 0x96, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA4, + DATA_ONLY, 0x94, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xB6, DATA_ONLY, 0xA9, - DATA_ONLY, 0xA4, - DATA_ONLY, 0xBA, + DATA_ONLY, 0xBC, DATA_ONLY, 0x00, - DATA_ONLY, 0xAC, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xA6, + DATA_ONLY, 0xB0, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB4, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xA7, DATA_ONLY, 0xBB, DATA_ONLY, 0x00, DATA_ONLY, 0xBE, @@ -261,24 +348,24 @@ static const unsigned short ld9040_sm2_a1_22_240[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_230[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAA, +static const unsigned short ld9040_sm2_22_260[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xAB, DATA_ONLY, 0xBE, DATA_ONLY, 0x00, - DATA_ONLY, 0x94, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA4, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xA3, - DATA_ONLY, 0xBB, - DATA_ONLY, 0x00, + DATA_ONLY, 0x92, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xB8, DATA_ONLY, 0xA9, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xAC, + DATA_ONLY, 0xBC, + DATA_ONLY, 0x00, + DATA_ONLY, 0xAD, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB4, + DATA_ONLY, 0xB3, DATA_ONLY, 0xA6, DATA_ONLY, 0xBB, DATA_ONLY, 0x00, @@ -288,25 +375,25 @@ static const unsigned short ld9040_sm2_a1_22_230[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_220[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xB4, +static const unsigned short ld9040_sm2_22_250[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB8, DATA_ONLY, 0xAC, - DATA_ONLY, 0xBE, + DATA_ONLY, 0xBF, DATA_ONLY, 0x00, - DATA_ONLY, 0x91, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA3, + DATA_ONLY, 0x8F, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xB8, DATA_ONLY, 0xAA, - DATA_ONLY, 0xA4, - DATA_ONLY, 0xBB, + DATA_ONLY, 0xBD, DATA_ONLY, 0x00, - DATA_ONLY, 0xA6, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xA7, + DATA_ONLY, 0xAA, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB4, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xA8, DATA_ONLY, 0xBC, DATA_ONLY, 0x00, DATA_ONLY, 0xB7, @@ -315,24 +402,24 @@ static const unsigned short ld9040_sm2_a1_22_220[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_210[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB3, +static const unsigned short ld9040_sm2_22_240[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB9, DATA_ONLY, 0xAD, DATA_ONLY, 0xBF, DATA_ONLY, 0x00, - DATA_ONLY, 0x8E, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA3, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xBB, + DATA_ONLY, 0x8C, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xAA, + DATA_ONLY, 0xBD, DATA_ONLY, 0x00, - DATA_ONLY, 0xA3, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xAD, + DATA_ONLY, 0xA7, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xB4, DATA_ONLY, 0xA8, DATA_ONLY, 0xBC, DATA_ONLY, 0x00, @@ -342,26 +429,25 @@ static const unsigned short ld9040_sm2_a1_22_210[] = { ENDDEF, 0x00 }; - -static const unsigned short ld9040_sm2_a1_22_200[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xC0, - DATA_ONLY, 0x00, - DATA_ONLY, 0x8B, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA2, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xA5, - DATA_ONLY, 0xBC, +static const unsigned short ld9040_sm2_22_230[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xAD, + DATA_ONLY, 0xBF, DATA_ONLY, 0x00, - DATA_ONLY, 0xA0, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x8A, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB8, DATA_ONLY, 0xAC, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA7, + DATA_ONLY, 0xBD, + DATA_ONLY, 0x00, + DATA_ONLY, 0xA4, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xA9, DATA_ONLY, 0xBC, DATA_ONLY, 0x00, DATA_ONLY, 0xB1, @@ -370,628 +456,620 @@ static const unsigned short ld9040_sm2_a1_22_200[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_190[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xC1, +static const unsigned short ld9040_sm2_22_220[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xAF, + DATA_ONLY, 0xC0, + DATA_ONLY, 0x00, + DATA_ONLY, 0x87, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xAD, + DATA_ONLY, 0xBE, DATA_ONLY, 0x00, - DATA_ONLY, 0x88, - DATA_ONLY, 0x36, DATA_ONLY, 0xA1, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xA6, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xAA, DATA_ONLY, 0xBD, DATA_ONLY, 0x00, - DATA_ONLY, 0x9C, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAB, DATA_ONLY, 0xAE, - DATA_ONLY, 0xA8, - DATA_ONLY, 0xBD, - DATA_ONLY, 0x00, - DATA_ONLY, 0xAD, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_180[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAF, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xC1, +static const unsigned short ld9040_sm2_22_210[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xC0, DATA_ONLY, 0x00, - DATA_ONLY, 0x85, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA0, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xBD, + DATA_ONLY, 0x84, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xAD, + DATA_ONLY, 0xBE, DATA_ONLY, 0x00, - DATA_ONLY, 0x99, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x9E, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xB3, DATA_ONLY, 0xAB, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xBE, + DATA_ONLY, 0xBD, DATA_ONLY, 0x00, - DATA_ONLY, 0xA9, + DATA_ONLY, 0xAA, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; - -static const unsigned short ld9040_sm2_a1_22_170[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xC1, +static const unsigned short ld9040_sm2_22_200[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xC2, DATA_ONLY, 0x00, - DATA_ONLY, 0x82, - DATA_ONLY, 0x36, - DATA_ONLY, 0x9F, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xBE, + DATA_ONLY, 0x81, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xAD, + DATA_ONLY, 0xC0, DATA_ONLY, 0x00, - DATA_ONLY, 0x95, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x9A, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB2, DATA_ONLY, 0xAB, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA9, DATA_ONLY, 0xBF, DATA_ONLY, 0x00, - DATA_ONLY, 0xA5, + DATA_ONLY, 0xA6, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_160[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xAD, +static const unsigned short ld9040_sm2_22_190[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB0, DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0x7F, - DATA_ONLY, 0x36, - DATA_ONLY, 0x9D, + DATA_ONLY, 0x7E, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB2, + DATA_ONLY, 0xB9, DATA_ONLY, 0xAD, - DATA_ONLY, 0xA7, - DATA_ONLY, 0xBF, - DATA_ONLY, 0x00, - DATA_ONLY, 0x91, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA9, DATA_ONLY, 0xC0, DATA_ONLY, 0x00, - DATA_ONLY, 0xA1, + DATA_ONLY, 0x97, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xAB, + DATA_ONLY, 0xBF, + DATA_ONLY, 0x00, + DATA_ONLY, 0xA3, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_150[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xAF, +static const unsigned short ld9040_sm2_22_180[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB0, DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0x7C, - DATA_ONLY, 0x36, - DATA_ONLY, 0x9B, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA8, - DATA_ONLY, 0xBF, + DATA_ONLY, 0x7B, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xAF, + DATA_ONLY, 0xC0, DATA_ONLY, 0x00, - DATA_ONLY, 0x8E, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x93, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xB5, DATA_ONLY, 0xAC, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xC1, + DATA_ONLY, 0xBF, DATA_ONLY, 0x00, - DATA_ONLY, 0x9D, + DATA_ONLY, 0x9F, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_140[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAF, - DATA_ONLY, 0xC5, +static const unsigned short ld9040_sm2_22_170[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC4, DATA_ONLY, 0x00, DATA_ONLY, 0x78, - DATA_ONLY, 0x36, - DATA_ONLY, 0x9B, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xC1, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xC2, DATA_ONLY, 0x00, - DATA_ONLY, 0x89, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x8F, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xB3, DATA_ONLY, 0xAD, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xC2, + DATA_ONLY, 0xC1, DATA_ONLY, 0x00, - DATA_ONLY, 0x99, + DATA_ONLY, 0x9B, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_130[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xAF, - DATA_ONLY, 0xC4, +static const unsigned short ld9040_sm2_22_160[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC5, DATA_ONLY, 0x00, DATA_ONLY, 0x75, - DATA_ONLY, 0x36, - DATA_ONLY, 0x9A, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xC1, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xC2, DATA_ONLY, 0x00, - DATA_ONLY, 0x86, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x8C, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB4, DATA_ONLY, 0xAD, - DATA_ONLY, 0xAF, - DATA_ONLY, 0xAB, DATA_ONLY, 0xC1, DATA_ONLY, 0x00, - DATA_ONLY, 0x95, + DATA_ONLY, 0x98, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_120[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAC, +static const unsigned short ld9040_sm2_22_150[] = { + 0xF9, 0x1D, DATA_ONLY, 0xB7, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xC4, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x71, - DATA_ONLY, 0x36, - DATA_ONLY, 0x97, - DATA_ONLY, 0xAF, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xC2, + DATA_ONLY, 0x72, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xAE, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0x82, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xAC, + DATA_ONLY, 0x88, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xAD, DATA_ONLY, 0xC2, DATA_ONLY, 0x00, - DATA_ONLY, 0x90, + DATA_ONLY, 0x94, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_110[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAB, +static const unsigned short ld9040_sm2_22_140[] = { + 0xF9, 0x1D, DATA_ONLY, 0xB7, - DATA_ONLY, 0xB1, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB3, DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x6D, - DATA_ONLY, 0x36, - DATA_ONLY, 0x96, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xC3, + DATA_ONLY, 0x6E, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xAE, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC4, DATA_ONLY, 0x00, - DATA_ONLY, 0x7D, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xAC, + DATA_ONLY, 0x84, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xAE, DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0x8C, + DATA_ONLY, 0x8F, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; - -static const unsigned short ld9040_sm2_a1_22_100[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xA8, +static const unsigned short ld9040_sm2_22_130[] = { + 0xF9, 0x1D, DATA_ONLY, 0xB8, + DATA_ONLY, 0xBD, DATA_ONLY, 0xB2, - DATA_ONLY, 0xC6, - DATA_ONLY, 0x00, - DATA_ONLY, 0x69, - DATA_ONLY, 0x36, - DATA_ONLY, 0x93, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xC3, + DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x79, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAC, + DATA_ONLY, 0x6B, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xAE, + DATA_ONLY, 0xBE, DATA_ONLY, 0xB1, - DATA_ONLY, 0xAC, + DATA_ONLY, 0xC5, + DATA_ONLY, 0x00, + DATA_ONLY, 0x80, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xAD, DATA_ONLY, 0xC4, DATA_ONLY, 0x00, - DATA_ONLY, 0x87, + DATA_ONLY, 0x8B, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; - -static const unsigned short ld9040_sm2_a1_22_90[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xA7, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xC8, - DATA_ONLY, 0x00, - DATA_ONLY, 0x65, - DATA_ONLY, 0x36, - DATA_ONLY, 0x92, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xC4, +static const unsigned short ld9040_sm2_22_120[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB4, + DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x74, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x68, + DATA_ONLY, 0x1C, DATA_ONLY, 0xAC, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xAD, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB3, DATA_ONLY, 0xC5, DATA_ONLY, 0x00, - DATA_ONLY, 0x82, + DATA_ONLY, 0x7C, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB0, + DATA_ONLY, 0xC3, + DATA_ONLY, 0x00, + DATA_ONLY, 0x87, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; - - -static const unsigned short ld9040_sm2_a1_22_80[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xA6, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xC9, +static const unsigned short ld9040_sm2_22_110[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xC8, DATA_ONLY, 0x00, - DATA_ONLY, 0x60, - DATA_ONLY, 0x36, - DATA_ONLY, 0x8E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xC6, + DATA_ONLY, 0x64, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xAC, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB4, + DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x6F, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xC6, + DATA_ONLY, 0x77, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC5, DATA_ONLY, 0x00, - DATA_ONLY, 0x7C, + DATA_ONLY, 0x82, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; - -static const unsigned short ld9040_sm2_a1_22_70[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xA4, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xC9, +static const unsigned short ld9040_sm2_22_100[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xC8, DATA_ONLY, 0x00, - DATA_ONLY, 0x5B, - DATA_ONLY, 0x36, - DATA_ONLY, 0x8C, - DATA_ONLY, 0xB2, + DATA_ONLY, 0x60, + DATA_ONLY, 0x1C, DATA_ONLY, 0xAC, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB5, DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x69, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xAF, + DATA_ONLY, 0x73, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB2, DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x76, + DATA_ONLY, 0x7D, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; - -static const unsigned short ld9040_sm2_a1_22_60[] = { - 0xF9, 0x2E, - DATA_ONLY, 0x9F, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB4, +static const unsigned short ld9040_sm2_22_90[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB7, DATA_ONLY, 0xC9, DATA_ONLY, 0x00, - DATA_ONLY, 0x56, - DATA_ONLY, 0x36, - DATA_ONLY, 0x89, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xAD, + DATA_ONLY, 0x5C, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xAC, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB6, DATA_ONLY, 0xC8, DATA_ONLY, 0x00, - DATA_ONLY, 0x63, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAC, + DATA_ONLY, 0x6E, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xB7, DATA_ONLY, 0xB2, - DATA_ONLY, 0xB0, DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x6F, + DATA_ONLY, 0x78, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_50[] = { - 0xF9, 0x2E, - DATA_ONLY, 0x9E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xC9, - DATA_ONLY, 0x00, - DATA_ONLY, 0x50, - DATA_ONLY, 0x36, - DATA_ONLY, 0x88, - DATA_ONLY, 0xAF, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xC8, +static const unsigned short ld9040_sm2_22_80[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xCA, DATA_ONLY, 0x00, - DATA_ONLY, 0x5D, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x57, + DATA_ONLY, 0x1C, DATA_ONLY, 0xAC, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xC8, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xCA, DATA_ONLY, 0x00, DATA_ONLY, 0x68, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xB3, + DATA_ONLY, 0xC8, + DATA_ONLY, 0x00, + DATA_ONLY, 0x72, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_40[] = { - 0xF9, 0x2E, - DATA_ONLY, 0x96, +static const unsigned short ld9040_sm2_22_70[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xBC, DATA_ONLY, 0xB9, + DATA_ONLY, 0xCC, + DATA_ONLY, 0x00, + DATA_ONLY, 0x52, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xAC, + DATA_ONLY, 0xBD, DATA_ONLY, 0xB8, DATA_ONLY, 0xCB, DATA_ONLY, 0x00, - DATA_ONLY, 0x49, - DATA_ONLY, 0x36, - DATA_ONLY, 0x85, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xAF, - DATA_ONLY, 0xC9, - DATA_ONLY, 0x00, - DATA_ONLY, 0x55, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB3, + DATA_ONLY, 0x63, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xB4, DATA_ONLY, 0xCA, DATA_ONLY, 0x00, - DATA_ONLY, 0x60, + DATA_ONLY, 0x6C, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_22_30_dimming[] = { - 0xF9, 0x2E, - DATA_ONLY, 0x81, - DATA_ONLY, 0xB7, +static const unsigned short ld9040_sm2_22_60[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xAA, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xCD, + DATA_ONLY, 0x00, + DATA_ONLY, 0x4C, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xA2, + DATA_ONLY, 0xBD, DATA_ONLY, 0xBA, DATA_ONLY, 0xCD, DATA_ONLY, 0x00, - DATA_ONLY, 0x41, - DATA_ONLY, 0x36, - DATA_ONLY, 0x80, - DATA_ONLY, 0xA7, - DATA_ONLY, 0xB1, + DATA_ONLY, 0x5C, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB6, DATA_ONLY, 0xCB, DATA_ONLY, 0x00, - DATA_ONLY, 0x4C, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xCC, - DATA_ONLY, 0x00, - DATA_ONLY, 0x56, + DATA_ONLY, 0x65, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; - -static const unsigned short ld9040_sm2_a1_19_300[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xBF, - DATA_ONLY, 0x00, - DATA_ONLY, 0xA4, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xAE, +static const unsigned short ld9040_sm2_22_50[] = { + 0xF9, 0x1D, DATA_ONLY, 0xA9, - DATA_ONLY, 0xBE, - DATA_ONLY, 0x00, + DATA_ONLY, 0xC1, DATA_ONLY, 0xBB, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xAB, - DATA_ONLY, 0xBE, + DATA_ONLY, 0xCD, DATA_ONLY, 0x00, - DATA_ONLY, 0xCF, + DATA_ONLY, 0x47, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xA2, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xCD, + DATA_ONLY, 0x00, + DATA_ONLY, 0x56, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xCB, + DATA_ONLY, 0x00, + DATA_ONLY, 0x5F, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_290[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xC1, +static const unsigned short ld9040_sm2_22_40[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xA6, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xD0, DATA_ONLY, 0x00, + DATA_ONLY, 0x3F, + DATA_ONLY, 0x1C, DATA_ONLY, 0xA2, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xA9, - DATA_ONLY, 0xBF, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xCF, DATA_ONLY, 0x00, - DATA_ONLY, 0xBA, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAA, + DATA_ONLY, 0x4E, + DATA_ONLY, 0x1E, DATA_ONLY, 0xC0, - DATA_ONLY, 0x00, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xB8, DATA_ONLY, 0xCD, + DATA_ONLY, 0x00, + DATA_ONLY, 0x56, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_280[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xC2, - DATA_ONLY, 0x00, - DATA_ONLY, 0xA0, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xAA, +static const unsigned short ld9040_sm2_22_30_dimming[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xA3, DATA_ONLY, 0xBF, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xCF, DATA_ONLY, 0x00, - DATA_ONLY, 0xB8, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAB, + DATA_ONLY, 0x38, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xA2, + DATA_ONLY, 0xB9, DATA_ONLY, 0xC1, + DATA_ONLY, 0xD0, DATA_ONLY, 0x00, - DATA_ONLY, 0xCA, + DATA_ONLY, 0x45, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xCD, + DATA_ONLY, 0x00, + DATA_ONLY, 0x4D, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_270[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xB8, +static const unsigned short ld9040_sm2_19_300[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC0, + DATA_ONLY, 0xBB, DATA_ONLY, 0xB1, DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0x9E, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xC0, - DATA_ONLY, 0x00, - DATA_ONLY, 0xB5, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAC, + DATA_ONLY, 0x9D, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xAF, DATA_ONLY, 0xC1, DATA_ONLY, 0x00, + DATA_ONLY, 0xBA, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xAE, + DATA_ONLY, 0xC0, + DATA_ONLY, 0x00, DATA_ONLY, 0xC8, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_260[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xC4, - DATA_ONLY, 0x00, - DATA_ONLY, 0x9C, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xAB, +static const unsigned short ld9040_sm2_19_290[] = { + 0xF9, 0x1D, DATA_ONLY, 0xC0, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0xB2, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAC, + DATA_ONLY, 0x9A, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xAF, DATA_ONLY, 0xC1, DATA_ONLY, 0x00, + DATA_ONLY, 0xB7, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xAD, + DATA_ONLY, 0xC0, + DATA_ONLY, 0x00, DATA_ONLY, 0xC5, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_250[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB1, +static const unsigned short ld9040_sm2_19_280[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB2, DATA_ONLY, 0xC4, DATA_ONLY, 0x00, - DATA_ONLY, 0x99, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x97, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBB, DATA_ONLY, 0xB0, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xC1, + DATA_ONLY, 0xC2, DATA_ONLY, 0x00, - DATA_ONLY, 0xAF, - DATA_ONLY, 0x2E, DATA_ONLY, 0xB3, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xC2, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xAE, + DATA_ONLY, 0xC1, DATA_ONLY, 0x00, DATA_ONLY, 0xC1, 0xFB, 0x02, @@ -999,24 +1077,24 @@ static const unsigned short ld9040_sm2_a1_19_250[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_240[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB1, +static const unsigned short ld9040_sm2_19_270[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB3, DATA_ONLY, 0xC5, DATA_ONLY, 0x00, - DATA_ONLY, 0x96, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x94, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBB, DATA_ONLY, 0xB0, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xC2, + DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0xAC, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB4, + DATA_ONLY, 0xB0, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB8, DATA_ONLY, 0xAE, DATA_ONLY, 0xC2, DATA_ONLY, 0x00, @@ -1026,26 +1104,26 @@ static const unsigned short ld9040_sm2_a1_19_240[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_230[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xBA, +static const unsigned short ld9040_sm2_19_260[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC0, + DATA_ONLY, 0xBD, DATA_ONLY, 0xB2, + DATA_ONLY, 0xC6, + DATA_ONLY, 0x00, + DATA_ONLY, 0x92, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB0, DATA_ONLY, 0xC4, DATA_ONLY, 0x00, - DATA_ONLY, 0x94, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xB1, DATA_ONLY, 0xAD, - DATA_ONLY, 0xC2, - DATA_ONLY, 0x00, - DATA_ONLY, 0xA9, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB9, DATA_ONLY, 0xAE, - DATA_ONLY, 0xC2, + DATA_ONLY, 0xC3, DATA_ONLY, 0x00, DATA_ONLY, 0xBB, 0xFB, 0x02, @@ -1053,24 +1131,24 @@ static const unsigned short ld9040_sm2_a1_19_230[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_220[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xBA, +static const unsigned short ld9040_sm2_19_250[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBD, DATA_ONLY, 0xB3, - DATA_ONLY, 0xC5, + DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x91, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xC2, + DATA_ONLY, 0x8F, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC4, DATA_ONLY, 0x00, - DATA_ONLY, 0xA6, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB4, + DATA_ONLY, 0xAA, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB9, DATA_ONLY, 0xAF, DATA_ONLY, 0xC3, DATA_ONLY, 0x00, @@ -1080,322 +1158,349 @@ static const unsigned short ld9040_sm2_a1_19_220[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_210[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xB9, +static const unsigned short ld9040_sm2_19_240[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBD, DATA_ONLY, 0xB4, - DATA_ONLY, 0xC5, + DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x8F, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB3, + DATA_ONLY, 0x8C, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBC, DATA_ONLY, 0xB2, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xC3, + DATA_ONLY, 0xC4, DATA_ONLY, 0x00, - DATA_ONLY, 0xA3, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xAF, + DATA_ONLY, 0xA7, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB0, DATA_ONLY, 0xC3, DATA_ONLY, 0x00, - DATA_ONLY, 0xB5, + DATA_ONLY, 0xB4, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_200[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBC, - DATA_ONLY, 0xB9, +static const unsigned short ld9040_sm2_19_230[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBE, DATA_ONLY, 0xB5, - DATA_ONLY, 0xC5, + DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x8C, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB3, + DATA_ONLY, 0x8A, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBD, DATA_ONLY, 0xB3, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xC3, - DATA_ONLY, 0x00, - DATA_ONLY, 0xA0, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xAF, DATA_ONLY, 0xC4, DATA_ONLY, 0x00, + DATA_ONLY, 0xA4, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xB1, + DATA_ONLY, 0xC3, + DATA_ONLY, 0x00, DATA_ONLY, 0xB1, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_190[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBC, - DATA_ONLY, 0xB9, +static const unsigned short ld9040_sm2_19_220[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBE, DATA_ONLY, 0xB5, - DATA_ONLY, 0xC6, + DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x89, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB3, + DATA_ONLY, 0x87, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBD, DATA_ONLY, 0xB3, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xC4, + DATA_ONLY, 0xC5, DATA_ONLY, 0x00, - DATA_ONLY, 0x9C, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xB0, + DATA_ONLY, 0xA1, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB1, DATA_ONLY, 0xC4, DATA_ONLY, 0x00, - DATA_ONLY, 0xAD, + DATA_ONLY, 0xAE, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_180[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBD, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xC7, +static const unsigned short ld9040_sm2_19_210[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xC8, DATA_ONLY, 0x00, - DATA_ONLY, 0x85, - DATA_ONLY, 0x36, + DATA_ONLY, 0x84, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBE, DATA_ONLY, 0xB3, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xC4, + DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x99, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xB6, + DATA_ONLY, 0x9E, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xBB, DATA_ONLY, 0xB1, DATA_ONLY, 0xC5, DATA_ONLY, 0x00, - DATA_ONLY, 0xA9, + DATA_ONLY, 0xAA, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_170[] = { - 0xF9, 0x2E, +static const unsigned short ld9040_sm2_19_200[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB6, + DATA_ONLY, 0xC9, + DATA_ONLY, 0x00, + DATA_ONLY, 0x81, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, DATA_ONLY, 0xBE, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xB5, + DATA_ONLY, 0xB4, DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x82, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB2, + DATA_ONLY, 0x9A, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xBB, DATA_ONLY, 0xB2, - DATA_ONLY, 0xAF, DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0x95, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xC5, - DATA_ONLY, 0x00, - DATA_ONLY, 0xA5, + DATA_ONLY, 0xA6, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_160[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xBB, +static const unsigned short ld9040_sm2_19_190[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xBE, DATA_ONLY, 0xB7, - DATA_ONLY, 0xC8, + DATA_ONLY, 0xCA, DATA_ONLY, 0x00, - DATA_ONLY, 0x7F, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xC6, + DATA_ONLY, 0x7E, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x91, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB7, + DATA_ONLY, 0x97, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xBA, DATA_ONLY, 0xB3, DATA_ONLY, 0xC6, DATA_ONLY, 0x00, - DATA_ONLY, 0xA1, + DATA_ONLY, 0xA3, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_150[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xBC, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xC9, - DATA_ONLY, 0x00, - DATA_ONLY, 0x7C, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xC8, +static const unsigned short ld9040_sm2_19_180[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xCA, DATA_ONLY, 0x00, - DATA_ONLY, 0x8D, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB2, + DATA_ONLY, 0x7B, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB6, DATA_ONLY, 0xC7, DATA_ONLY, 0x00, - DATA_ONLY, 0x9D, + DATA_ONLY, 0x93, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xB4, + DATA_ONLY, 0xC6, + DATA_ONLY, 0x00, + DATA_ONLY, 0x9F, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_140[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xBC, +static const unsigned short ld9040_sm2_19_170[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB8, + DATA_ONLY, 0xCB, + DATA_ONLY, 0x00, + DATA_ONLY, 0x78, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBF, DATA_ONLY, 0xB6, DATA_ONLY, 0xC9, DATA_ONLY, 0x00, - DATA_ONLY, 0x79, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB0, + DATA_ONLY, 0x8F, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xBA, DATA_ONLY, 0xB4, - DATA_ONLY, 0xB1, - DATA_ONLY, 0xC8, - DATA_ONLY, 0x00, - DATA_ONLY, 0x89, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB2, DATA_ONLY, 0xC8, DATA_ONLY, 0x00, - DATA_ONLY, 0x99, + DATA_ONLY, 0x9B, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_130[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBC, +static const unsigned short ld9040_sm2_19_160[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC3, DATA_ONLY, 0xBD, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xCA, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xCC, DATA_ONLY, 0x00, DATA_ONLY, 0x75, - DATA_ONLY, 0x36, - DATA_ONLY, 0xB0, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xB2, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xC9, + DATA_ONLY, 0x00, + DATA_ONLY, 0x8C, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xB5, DATA_ONLY, 0xC8, DATA_ONLY, 0x00, - DATA_ONLY, 0x86, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x98, + 0xFB, 0x02, + DATA_ONLY, 0x5A, + ENDDEF, 0x00 +}; + +static const unsigned short ld9040_sm2_19_150[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC3, + DATA_ONLY, 0xC0, DATA_ONLY, 0xB8, - DATA_ONLY, 0xB3, + DATA_ONLY, 0xCC, + DATA_ONLY, 0x00, + DATA_ONLY, 0x72, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xB7, + DATA_ONLY, 0xC9, + DATA_ONLY, 0x00, + DATA_ONLY, 0x88, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB4, DATA_ONLY, 0xC8, DATA_ONLY, 0x00, - DATA_ONLY, 0x95, + DATA_ONLY, 0x94, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_120[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xBE, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xCB, +static const unsigned short ld9040_sm2_19_140[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xCC, DATA_ONLY, 0x00, - DATA_ONLY, 0x71, - DATA_ONLY, 0x36, - DATA_ONLY, 0xAE, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xB2, + DATA_ONLY, 0x6E, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xB9, DATA_ONLY, 0xCA, DATA_ONLY, 0x00, - DATA_ONLY, 0x81, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x84, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xB7, DATA_ONLY, 0xC9, DATA_ONLY, 0x00, - DATA_ONLY, 0x90, + DATA_ONLY, 0x8F, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_110[] = { - 0xF9, 0x2E, +static const unsigned short ld9040_sm2_19_130[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xCD, + DATA_ONLY, 0x00, + DATA_ONLY, 0x6B, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xC3, DATA_ONLY, 0xB9, - DATA_ONLY, 0xBE, - DATA_ONLY, 0xB8, DATA_ONLY, 0xCB, DATA_ONLY, 0x00, - DATA_ONLY, 0x6E, - DATA_ONLY, 0x36, - DATA_ONLY, 0xAC, + DATA_ONLY, 0x80, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xBE, DATA_ONLY, 0xB6, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xCA, - DATA_ONLY, 0x00, - DATA_ONLY, 0x7D, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xB4, DATA_ONLY, 0xCA, DATA_ONLY, 0x00, - DATA_ONLY, 0x8C, + DATA_ONLY, 0x8B, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_100[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xBE, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xCC, +static const unsigned short ld9040_sm2_19_120[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xCD, DATA_ONLY, 0x00, - DATA_ONLY, 0x6A, - DATA_ONLY, 0x36, - DATA_ONLY, 0xAC, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xB3, + DATA_ONLY, 0x68, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xBA, DATA_ONLY, 0xCC, DATA_ONLY, 0x00, - DATA_ONLY, 0x78, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x7C, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xB7, DATA_ONLY, 0xCB, DATA_ONLY, 0x00, DATA_ONLY, 0x87, @@ -1404,25 +1509,25 @@ static const unsigned short ld9040_sm2_a1_19_100[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_90[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xC0, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xCB, +static const unsigned short ld9040_sm2_19_110[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC3, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xBB, + DATA_ONLY, 0xCE, DATA_ONLY, 0x00, - DATA_ONLY, 0x66, - DATA_ONLY, 0x36, - DATA_ONLY, 0xAA, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xCB, + DATA_ONLY, 0x64, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xBA, + DATA_ONLY, 0xCD, DATA_ONLY, 0x00, - DATA_ONLY, 0x74, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB2, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xB6, + DATA_ONLY, 0x77, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB7, DATA_ONLY, 0xCB, DATA_ONLY, 0x00, DATA_ONLY, 0x82, @@ -1431,134 +1536,161 @@ static const unsigned short ld9040_sm2_a1_19_90[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_80[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB8, +static const unsigned short ld9040_sm2_19_100[] = { + 0xF9, 0x1D, DATA_ONLY, 0xC2, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xCD, + DATA_ONLY, 0x00, + DATA_ONLY, 0x60, + DATA_ONLY, 0x1C, DATA_ONLY, 0xBA, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xBC, DATA_ONLY, 0xCD, DATA_ONLY, 0x00, - DATA_ONLY, 0x61, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA7, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x73, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB9, + DATA_ONLY, 0xCC, + DATA_ONLY, 0x00, + DATA_ONLY, 0x7D, + 0xFB, 0x02, + DATA_ONLY, 0x5A, + ENDDEF, 0x00 +}; + +static const unsigned short ld9040_sm2_19_90[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xBD, DATA_ONLY, 0xCE, DATA_ONLY, 0x00, - DATA_ONLY, 0x6E, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, + DATA_ONLY, 0x5C, + DATA_ONLY, 0x1C, DATA_ONLY, 0xBA, - DATA_ONLY, 0xB5, + DATA_ONLY, 0xC6, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xCE, + DATA_ONLY, 0x00, + DATA_ONLY, 0x6E, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xB9, DATA_ONLY, 0xCD, DATA_ONLY, 0x00, - DATA_ONLY, 0x7C, + DATA_ONLY, 0x78, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_70[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xC3, - DATA_ONLY, 0xBB, - DATA_ONLY, 0xCC, +static const unsigned short ld9040_sm2_19_80[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xD0, DATA_ONLY, 0x00, - DATA_ONLY, 0x5C, - DATA_ONLY, 0x36, - DATA_ONLY, 0xA4, + DATA_ONLY, 0x57, + DATA_ONLY, 0x1C, DATA_ONLY, 0xB8, - DATA_ONLY, 0xB5, - DATA_ONLY, 0xCE, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xD0, DATA_ONLY, 0x00, - DATA_ONLY, 0x69, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB4, + DATA_ONLY, 0x68, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xC0, DATA_ONLY, 0xBA, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xCD, + DATA_ONLY, 0xCF, DATA_ONLY, 0x00, - DATA_ONLY, 0x75, + DATA_ONLY, 0x72, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_60[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB6, +static const unsigned short ld9040_sm2_19_70[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC0, DATA_ONLY, 0xC4, - DATA_ONLY, 0xBC, - DATA_ONLY, 0xCF, + DATA_ONLY, 0xC0, + DATA_ONLY, 0xD1, DATA_ONLY, 0x00, - DATA_ONLY, 0x55, - DATA_ONLY, 0x36, - DATA_ONLY, 0x9F, - DATA_ONLY, 0xB9, + DATA_ONLY, 0x52, + DATA_ONLY, 0x1C, DATA_ONLY, 0xB5, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xC0, DATA_ONLY, 0xD0, DATA_ONLY, 0x00, DATA_ONLY, 0x63, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xD0, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xCF, DATA_ONLY, 0x00, - DATA_ONLY, 0x6E, + DATA_ONLY, 0x6C, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_50[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xB3, +static const unsigned short ld9040_sm2_19_60[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC0, DATA_ONLY, 0xC5, - DATA_ONLY, 0xBE, - DATA_ONLY, 0xCF, + DATA_ONLY, 0xC0, + DATA_ONLY, 0xD4, DATA_ONLY, 0x00, - DATA_ONLY, 0x4F, - DATA_ONLY, 0x36, - DATA_ONLY, 0x9B, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB6, - DATA_ONLY, 0xCF, + DATA_ONLY, 0x4C, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xC0, + DATA_ONLY, 0xD3, DATA_ONLY, 0x00, - DATA_ONLY, 0x5D, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB3, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xD0, + DATA_ONLY, 0x5C, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xC0, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBC, + DATA_ONLY, 0xD2, DATA_ONLY, 0x00, - DATA_ONLY, 0x67, + DATA_ONLY, 0x65, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_40[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xAD, - DATA_ONLY, 0xC7, - DATA_ONLY, 0xBF, +static const unsigned short ld9040_sm2_19_50[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xC0, + DATA_ONLY, 0xC6, + DATA_ONLY, 0xC2, DATA_ONLY, 0xD2, DATA_ONLY, 0x00, - DATA_ONLY, 0x48, - DATA_ONLY, 0x36, - DATA_ONLY, 0x97, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xD1, + DATA_ONLY, 0x47, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xC6, + DATA_ONLY, 0xC3, + DATA_ONLY, 0xD3, DATA_ONLY, 0x00, - DATA_ONLY, 0x55, - DATA_ONLY, 0x2E, - DATA_ONLY, 0xB4, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xD2, + DATA_ONLY, 0x56, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xD1, DATA_ONLY, 0x00, DATA_ONLY, 0x5F, 0xFB, 0x02, @@ -1566,93 +1698,122 @@ static const unsigned short ld9040_sm2_a1_19_40[] = { ENDDEF, 0x00 }; -static const unsigned short ld9040_sm2_a1_19_30_dimming[] = { - 0xF9, 0x2E, - DATA_ONLY, 0xA7, - DATA_ONLY, 0xC5, - DATA_ONLY, 0xC0, +static const unsigned short ld9040_sm2_19_40[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xBD, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xC3, + DATA_ONLY, 0xD6, + DATA_ONLY, 0x00, + DATA_ONLY, 0x3F, + DATA_ONLY, 0x1C, + DATA_ONLY, 0xB5, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xC4, DATA_ONLY, 0xD5, DATA_ONLY, 0x00, - DATA_ONLY, 0x40, - DATA_ONLY, 0x36, - DATA_ONLY, 0x93, - DATA_ONLY, 0xB7, - DATA_ONLY, 0xB8, - DATA_ONLY, 0xD2, + DATA_ONLY, 0x4E, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xC3, + DATA_ONLY, 0xC2, + DATA_ONLY, 0xBF, + DATA_ONLY, 0xD4, DATA_ONLY, 0x00, - DATA_ONLY, 0x4C, - DATA_ONLY, 0x2E, + DATA_ONLY, 0x56, + 0xFB, 0x02, + DATA_ONLY, 0x5A, + ENDDEF, 0x00 +}; + +static const unsigned short ld9040_sm2_19_30_dimming[] = { + 0xF9, 0x1D, + DATA_ONLY, 0xBE, + DATA_ONLY, 0xC8, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xD6, + DATA_ONLY, 0x00, + DATA_ONLY, 0x38, + DATA_ONLY, 0x1C, DATA_ONLY, 0xB5, - DATA_ONLY, 0xB9, - DATA_ONLY, 0xBA, - DATA_ONLY, 0xD2, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xD6, DATA_ONLY, 0x00, - DATA_ONLY, 0x56, + DATA_ONLY, 0x45, + DATA_ONLY, 0x1E, + DATA_ONLY, 0xC7, + DATA_ONLY, 0xC4, + DATA_ONLY, 0xC1, + DATA_ONLY, 0xD4, + DATA_ONLY, 0x00, + DATA_ONLY, 0x4D, 0xFB, 0x02, DATA_ONLY, 0x5A, ENDDEF, 0x00 }; -/* LD9040, 4.27", SM2 A1 Panel Gamma Table */ -static const unsigned short *psm2_a1_22Gamma_set[] = { - ld9040_sm2_a1_22_30_dimming, - ld9040_sm2_a1_22_40, - ld9040_sm2_a1_22_70, - ld9040_sm2_a1_22_90, - ld9040_sm2_a1_22_100, - ld9040_sm2_a1_22_110, - ld9040_sm2_a1_22_120, - ld9040_sm2_a1_22_130, - ld9040_sm2_a1_22_140, - ld9040_sm2_a1_22_150, - ld9040_sm2_a1_22_160, - ld9040_sm2_a1_22_170, - ld9040_sm2_a1_22_180, - ld9040_sm2_a1_22_190, - ld9040_sm2_a1_22_200, - ld9040_sm2_a1_22_210, - ld9040_sm2_a1_22_220, - ld9040_sm2_a1_22_230, - ld9040_sm2_a1_22_240, - ld9040_sm2_a1_22_250, - ld9040_sm2_a1_22_260, - ld9040_sm2_a1_22_270, - ld9040_sm2_a1_22_280, - ld9040_sm2_a1_22_290, - ld9040_sm2_a1_22_300, -}; - -static const unsigned short *psm2_a1_19Gamma_set[] = { - ld9040_sm2_a1_19_30_dimming, - ld9040_sm2_a1_19_40, - ld9040_sm2_a1_19_70, - ld9040_sm2_a1_19_90, - ld9040_sm2_a1_19_100, - ld9040_sm2_a1_19_110, - ld9040_sm2_a1_19_120, - ld9040_sm2_a1_19_130, - ld9040_sm2_a1_19_140, - ld9040_sm2_a1_19_150, - ld9040_sm2_a1_19_160, - ld9040_sm2_a1_19_170, - ld9040_sm2_a1_19_180, - ld9040_sm2_a1_19_190, - ld9040_sm2_a1_19_200, - ld9040_sm2_a1_19_210, - ld9040_sm2_a1_19_220, - ld9040_sm2_a1_19_230, - ld9040_sm2_a1_19_240, - ld9040_sm2_a1_19_250, - ld9040_sm2_a1_19_260, - ld9040_sm2_a1_19_270, - ld9040_sm2_a1_19_280, - ld9040_sm2_a1_19_290, - ld9040_sm2_a1_19_300, -}; - - -struct ld9040_panel_data s2plus_panel_data = { +/* SM2 4.52" GAMMA 2.2 Table */ +static const unsigned short *psm2_22Gamma_set[] = { + ld9040_sm2_22_30_dimming, + ld9040_sm2_22_40, + ld9040_sm2_22_70, + ld9040_sm2_22_90, + ld9040_sm2_22_100, + ld9040_sm2_22_110, + ld9040_sm2_22_120, + ld9040_sm2_22_130, + ld9040_sm2_22_140, + ld9040_sm2_22_150, + ld9040_sm2_22_160, + ld9040_sm2_22_170, + ld9040_sm2_22_180, + ld9040_sm2_22_190, + ld9040_sm2_22_200, + ld9040_sm2_22_210, + ld9040_sm2_22_220, + ld9040_sm2_22_230, + ld9040_sm2_22_240, + ld9040_sm2_22_250, + ld9040_sm2_22_260, + ld9040_sm2_22_270, + ld9040_sm2_22_280, + ld9040_sm2_22_290, + ld9040_sm2_22_300, +}; + + +/* SM2 4.52" GAMMA 1.9 Table */ +static const unsigned short *psm2_19Gamma_set[] = { + ld9040_sm2_19_30_dimming, + ld9040_sm2_19_40, + ld9040_sm2_19_70, + ld9040_sm2_19_90, + ld9040_sm2_19_100, + ld9040_sm2_19_110, + ld9040_sm2_19_120, + ld9040_sm2_19_130, + ld9040_sm2_19_140, + ld9040_sm2_19_150, + ld9040_sm2_19_160, + ld9040_sm2_19_170, + ld9040_sm2_19_180, + ld9040_sm2_19_190, + ld9040_sm2_19_200, + ld9040_sm2_19_210, + ld9040_sm2_19_220, + ld9040_sm2_19_230, + ld9040_sm2_19_240, + ld9040_sm2_19_250, + ld9040_sm2_19_260, + ld9040_sm2_19_270, + ld9040_sm2_19_280, + ld9040_sm2_19_290, + ld9040_sm2_19_300, +}; + + +struct ld9040_panel_data u1_panel_data = { .seq_user_set = SEQ_USER_SETTING, .seq_displayctl_set = SEQ_DISPCTL, .seq_gtcon_set = SEQ_GTCON, @@ -1662,11 +1823,11 @@ struct ld9040_panel_data s2plus_panel_data = { .display_off = SEQ_DISPOFF, .sleep_in = SEQ_SLPIN, .sleep_out = SEQ_SLPOUT, - .acl_on = SEQ_ACL_ON, + .gamma19_table = psm2_19Gamma_set, + .gamma22_table = psm2_22Gamma_set, .acl_table = ACL_cutoff_set, - .elvss_on = SEQ_ELVSS_ON, .elvss_table = SEQ_SM2_ELVSS_set, - .gamma19_table = psm2_a1_19Gamma_set, - .gamma22_table = psm2_a1_22Gamma_set, + .acl_on = SEQ_ACL_ON, + .elvss_on = SEQ_ELVSS_ON, .lcdtype = LCDTYPE_SM2_A1, }; diff --git a/arch/arm/mach-exynos/u1-wimax.c b/arch/arm/mach-exynos/u1-wimax.c new file mode 100644 index 0000000..9743a6e --- /dev/null +++ b/arch/arm/mach-exynos/u1-wimax.c @@ -0,0 +1,327 @@ +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/skbuff.h> +#include <linux/wimax/samsung/wimax732.h> + +#include <plat/devs.h> +#include <plat/sdhci.h> +#include <plat/gpio-cfg.h> +#include <mach/regs-gpio.h> +#include <mach/gpio.h> +#include <mach/gpio-u1.h> +#include <linux/wimax/samsung/max8893.h> + +#if defined(CONFIG_WIMAX_CMC) /* && defined(CONFIG_TARGET_LOCALE_NA)*/ + +void wimax_on_pin_conf(int onoff) +{ + int gpio; + if (onoff) { + + for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + } else { + for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN); + } + for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + } + +} + +static void wimax_deinit_gpios(void); +static void wimax_wakeup_assert(int enable) +{ + gpio_set_value(GPIO_WIMAX_WAKEUP, !enable); +} + +static int get_wimax_sleep_mode(void) +{ + return gpio_get_value(GPIO_WIMAX_IF_MODE1); +} + +static int is_wimax_active(void) +{ + return gpio_get_value(GPIO_WIMAX_CON0); +} + +static void signal_ap_active(int enable) +{ + gpio_set_value(GPIO_WIMAX_CON1, enable); +} + +static void switch_eeprom_wimax(void) +{ + gpio_set_value(GPIO_WIMAX_I2C_CON, GPIO_LEVEL_LOW); + usleep_range(10000, 10000); +} + +static void switch_usb_ap(void) +{ + gpio_set_value(GPIO_WIMAX_USB_EN, GPIO_LEVEL_LOW); +#if defined(CONFIG_MACH_C1_REV02) + gpio_set_value(USB_SEL, GPIO_LEVEL_LOW); +#endif /* CONFIG_MACH_C1_REV02 */ + usleep_range(10000, 10000); +} + +static void switch_usb_wimax(void) +{ + gpio_set_value(GPIO_WIMAX_USB_EN, GPIO_LEVEL_HIGH); +#if defined(CONFIG_MACH_C1_REV02) + gpio_set_value(USB_SEL, GPIO_LEVEL_HIGH); +#endif /* CONFIG_MACH_C1_REV02 */ + usleep_range(10000, 10000); +} + +#if defined(CONFIG_UART_SWITCH_AND_GPIO_DUMP_FOR_WIMAX) +static void switch_uart_ap(void) +{ + gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_HIGH); +} +#endif + +#if 1 +static void switch_uart_wimax(void) +{ + gpio_set_value(GPIO_UART_SEL, GPIO_LEVEL_LOW); + gpio_set_value(GPIO_UART_SEL1, GPIO_LEVEL_HIGH); +} +#endif + +static void wimax_init_gpios(void) +{ + s3c_gpio_cfgpin(GPIO_WIMAX_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_INT, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_WIMAX_CON0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON0, S3C_GPIO_PULL_UP); + /* default idle */ + gpio_set_value(GPIO_WIMAX_IF_MODE1, GPIO_LEVEL_HIGH); + /* active low interrupt */ + gpio_set_value(GPIO_WIMAX_CON2, GPIO_LEVEL_HIGH); + gpio_set_value(GPIO_WIMAX_CON1, GPIO_LEVEL_HIGH); +} + +static void wimax_hsmmc_presence_check(int card_present) +{ + mmc_force_presence_change(&s3c_device_hsmmc3); +} + +#if defined(CONFIG_UART_SWITCH_AND_GPIO_DUMP_FOR_WIMAX) +static void display_gpios(void) +{ + int val = 0; + val = gpio_get_value(GPIO_WIMAX_EN); + dump_debug("WIMAX_EN: %d", val); + val = gpio_get_value(GPIO_WIMAX_RESET_N); + dump_debug("WIMAX_RESET: %d", val); + val = gpio_get_value(GPIO_WIMAX_CON0); + dump_debug("WIMAX_CON0: %d", val); + val = gpio_get_value(GPIO_WIMAX_CON1); + dump_debug("WIMAX_CON1: %d", val); + val = gpio_get_value(GPIO_WIMAX_CON2); + dump_debug("WIMAX_CON2: %d", val); + val = gpio_get_value(GPIO_WIMAX_WAKEUP); + dump_debug("WIMAX_WAKEUP: %d", val); + val = gpio_get_value(GPIO_WIMAX_INT); + dump_debug("WIMAX_INT: %d", val); + val = gpio_get_value(GPIO_WIMAX_IF_MODE0); + dump_debug("WIMAX_IF_MODE0: %d", val); + val = gpio_get_value(GPIO_WIMAX_IF_MODE1); + dump_debug("WIMAX_IF_MODE1: %d", val); + val = gpio_get_value(GPIO_WIMAX_USB_EN); + dump_debug("WIMAX_USB_EN: %d", val); + val = gpio_get_value(GPIO_WIMAX_I2C_CON); + dump_debug("I2C_SEL: %d", val); +#if defined(CONFIG_MACH_C1_REV02) + val = gpio_get_value(USB_SEL); + dump_debug("WIMAX_USB_SEL: %d", val); +#endif /* CONFIG_MACH_C1_REV02 */ + val = gpio_get_value(GPIO_UART_SEL); + dump_debug("UART_SEL1: %d", val); +} +#endif + +static void hw_set_wimax_mode(void); +static void restore_uart_path(void); +static void store_uart_path(void); +static int gpio_wimax_power(int); + +static struct wimax732_platform_data wimax732_pdata = { + .power = gpio_wimax_power, + .detect = wimax_hsmmc_presence_check, + .set_mode = hw_set_wimax_mode, + .signal_ap_active = signal_ap_active, + .get_sleep_mode = get_wimax_sleep_mode, + .is_modem_awake = is_wimax_active, + .wakeup_assert = wimax_wakeup_assert, +#if defined(CONFIG_UART_SWITCH_AND_GPIO_DUMP_FOR_WIMAX) + .uart_wimax = switch_uart_wimax, + .uart_ap = switch_uart_ap, + .gpio_display = display_gpios, +#endif + .g_cfg = NULL, + .wimax_int = GPIO_WIMAX_INT, + .restore_uart_path = restore_uart_path, +}; + +static int gpio_wimax_power(int enable) +{ + if (!enable) + goto wimax_power_off; + pr_err("Wimax power ON"); + if (wimax732_pdata.g_cfg->wimax_mode != SDIO_MODE) { + switch_usb_wimax(); + s3c_bat_use_wimax(1); + } + if (wimax732_pdata.g_cfg->wimax_mode == WTM_MODE) { + store_uart_path(); + switch_uart_wimax(); + } + switch_eeprom_wimax(); + wimax_on_pin_conf(1); + /*s3c_gpio_setpull(GPIO_WIMAX_EN, S3C_GPIO_PULL_UP);*/ + gpio_set_value(GPIO_WIMAX_EN, GPIO_LEVEL_HIGH); + + wimax_init_gpios(); + + s3c_gpio_cfgpin(EXYNOS4_GPB(2), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(EXYNOS4_GPB(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(EXYNOS4_GPB(3), S3C_GPIO_SFN(3)); + s3c_gpio_setpull(EXYNOS4_GPB(3), S3C_GPIO_PULL_UP); + + wimax_pmic_set_voltage(); + pr_err("RESET"); + gpio_set_value(GPIO_WIMAX_RESET_N, GPIO_LEVEL_LOW); + mdelay(3); + gpio_set_value(GPIO_WIMAX_RESET_N, GPIO_LEVEL_HIGH); + return WIMAX_POWER_SUCCESS; + wimax_power_off: + wimax_deinit_gpios(); + pr_err("Wimax power OFF"); + + if (wimax732_pdata.g_cfg->wimax_mode != SDIO_MODE) + s3c_bat_use_wimax(0); + + wimax_on_pin_conf(0); + + return WIMAX_POWER_SUCCESS; +} + +static void wimax_deinit_gpios(void) +{ + s3c_gpio_cfgpin(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_DBGEN_28V, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_DBGEN_28V, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_I2C_CON, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_I2C_CON, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_I2C_CON, GPIO_LEVEL_HIGH); + + s3c_gpio_cfgpin(GPIO_WIMAX_WAKEUP, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_WAKEUP, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_WAKEUP, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE0, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_IF_MODE0, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_IF_MODE0, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_CON0, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON0, S3C_GPIO_PULL_DOWN); + s3c_gpio_cfgpin(GPIO_WIMAX_IF_MODE1, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_IF_MODE1, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_IF_MODE1, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_CON2, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON2, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_CON2, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_CON1, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_CON1, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_CON1, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_RESET_N, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_RESET_N, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_RESET_N, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_EN, GPIO_LEVEL_LOW); + s3c_gpio_cfgpin(GPIO_WIMAX_USB_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_USB_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_USB_EN, GPIO_LEVEL_LOW); +#if defined(CONFIG_MACH_C1_REV02) + s3c_gpio_cfgpin(USB_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(USB_SEL, S3C_GPIO_PULL_NONE); +#endif /* CONFIG_MACH_C1_REV02 */ + s3c_gpio_cfgpin(GPIO_UART_SEL1, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL1, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_CMC_SCL_18V, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CMC_SCL_18V, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_CMC_SDA_18V, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_CMC_SDA_18V, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_WIMAX_INT, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WIMAX_INT, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WIMAX_INT, GPIO_LEVEL_LOW); + + switch_usb_ap(); +} + +static void store_uart_path(void) +{ + wimax732_pdata.uart_sel = gpio_get_value(GPIO_UART_SEL); + wimax732_pdata.uart_sel1 = gpio_get_value(GPIO_UART_SEL1); +} + +static void restore_uart_path(void) +{ + gpio_set_value(GPIO_UART_SEL, wimax732_pdata.uart_sel); + gpio_set_value(GPIO_UART_SEL1, wimax732_pdata.uart_sel1); +} + +static void hw_set_wimax_mode(void) +{ + switch (wimax732_pdata.g_cfg->wimax_mode) { + case SDIO_MODE: + pr_err("SDIO MODE"); + gpio_set_value(GPIO_WIMAX_WAKEUP, GPIO_LEVEL_HIGH); + gpio_set_value(GPIO_WIMAX_IF_MODE0, GPIO_LEVEL_HIGH); + break; + case WTM_MODE: + case AUTH_MODE: + pr_err("WTM_MODE || AUTH_MODE"); + gpio_set_value(GPIO_WIMAX_WAKEUP, GPIO_LEVEL_LOW); + gpio_set_value(GPIO_WIMAX_IF_MODE0, GPIO_LEVEL_LOW); + break; + case DM_MODE: + pr_err("DM MODE"); + gpio_set_value(GPIO_WIMAX_WAKEUP, GPIO_LEVEL_HIGH); + gpio_set_value(GPIO_WIMAX_IF_MODE0, GPIO_LEVEL_LOW); + break; + case USB_MODE: + case USIM_RELAY_MODE: + pr_err("USB MODE"); + gpio_set_value(GPIO_WIMAX_WAKEUP, GPIO_LEVEL_LOW); + gpio_set_value(GPIO_WIMAX_IF_MODE0, GPIO_LEVEL_HIGH); + break; + } +} + +struct platform_device s3c_device_cmc732 = { + .name = "wimax732_driver", + .id = 1, + .dev.platform_data = &wimax732_pdata, +}; + +#endif diff --git a/arch/arm/mach-exynos/u1-wlan.c b/arch/arm/mach-exynos/u1-wlan.c index c570fc8..c88b909 100644 --- a/arch/arm/mach-exynos/u1-wlan.c +++ b/arch/arm/mach-exynos/u1-wlan.c @@ -208,8 +208,11 @@ ARRAY_SIZE(wlan_sdio_on_table), wlan_sdio_on_table); ARRAY_SIZE(wlan_sdio_off_table), wlan_sdio_off_table); } udelay(200); - +#if defined(CONFIG_MACH_U1_NA_SPR) || defined(CONFIG_MACH_U1_NA_USCC) + mmc_force_presence_change(&s3c_device_hsmmc2); +#else mmc_force_presence_change(&s3c_device_hsmmc3); +#endif msleep(500); /* wait for carddetect */ return 0; } @@ -290,9 +293,10 @@ static struct resource brcm_wlan_resources[] = { .start = IRQ_EINT(21), .end = IRQ_EINT(21), #ifdef CONFIG_MACH_Q1_BD - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL + |IORESOURCE_IRQ_SHAREABLE, #else - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, #endif }, }; diff --git a/arch/arm/mach-exynos/u1.h b/arch/arm/mach-exynos/u1.h index d77e440..355bae1 100644 --- a/arch/arm/mach-exynos/u1.h +++ b/arch/arm/mach-exynos/u1.h @@ -22,4 +22,8 @@ extern void set_gps_uart_op(int onoff); extern int u1_switch_get_usb_lock_state(void); #endif +#ifdef CONFIG_WIMAX_CMC +extern struct platform_device s3c_device_cmc732; +#endif + #endif diff --git a/arch/arm/mach-exynos/u1camera-gpio.c b/arch/arm/mach-exynos/u1camera-gpio.c deleted file mode 100644 index b00b6c5..0000000 --- a/arch/arm/mach-exynos/u1camera-gpio.c +++ /dev/null @@ -1,439 +0,0 @@ -#include <linux/gpio.h> -#include <linux/serial_core.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/regs-serial.h> -#include <mach/gpio.h> -#include "u1.h" - -struct gpio_init_data { - uint num; - uint cfg; - uint val; - uint pud; - uint drv; -}; - -static struct gpio_init_data u1_init_gpios[] = { - {EXYNOS4_GPC1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SDA_1.8V */ - {EXYNOS4_GPC1(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* CODEC_SCL_1.8V */ - - {EXYNOS4_GPD0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SDA_2.8V */ - {EXYNOS4_GPD0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* MHL_SCL_2.8V */ - - {EXYNOS4_GPD1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SDA_2.8V */ - {EXYNOS4_GPD1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* 8M_CAM_SCL_2.8V */ - {EXYNOS4_GPD1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SDA_2.8V */ - {EXYNOS4_GPD1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* SENSE_SCL_2.8V */ - - {EXYNOS4_GPK3(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_CMD */ - {EXYNOS4_GPK3(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(0) */ - {EXYNOS4_GPK3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(1) */ - {EXYNOS4_GPK3(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(2) */ - {EXYNOS4_GPK3(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* WLAN_SDIO_D(3) */ - - {EXYNOS4_GPX0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_UP */ - {EXYNOS4_GPX0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* VOL_DOWN */ - {EXYNOS4_GPX0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_BOOT_MODE */ - - {EXYNOS4_GPX2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_FUEL_ALERT */ - - {EXYNOS4_GPX3(1), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPX3(2), S3C_GPIO_SFN(GPIO_DET_35_AF), S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, /* GPIO_DET_35 */ - {EXYNOS4_GPX3(3), S3C_GPIO_OUTPUT, S3C_GPIO_SETPIN_ZERO, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPX3(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_NONE, S5P_GPIO_DRVSTR_LV1}, - - {EXYNOS4_GPY0(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY0(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY0(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY0(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY0(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY0(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - - {EXYNOS4_GPY1(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY1(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY1(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY1(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - - {EXYNOS4_GPY2(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY2(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1,}, - {EXYNOS4_GPY2(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY2(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY2(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY2(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - - {EXYNOS4_GPY3(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY3(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - - {EXYNOS4_GPY4(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY4(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY4(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY4(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - - {EXYNOS4_GPY5(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY5(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY5(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY5(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY5(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY5(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY5(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY5(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - - {EXYNOS4_GPY6(0), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY6(1), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY6(2), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY6(3), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY6(4), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY6(5), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY6(6), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, - {EXYNOS4_GPY6(7), S3C_GPIO_INPUT, S3C_GPIO_SETPIN_NONE, - S3C_GPIO_PULL_DOWN, S5P_GPIO_DRVSTR_LV1}, -}; - -/* this table only for GC1 board */ -static unsigned int u1_sleep_gpio_table[][3] = { - {EXYNOS4_GPA0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPA0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPA0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPA0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPA0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPA0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - - {EXYNOS4_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPA1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPA1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPA1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPA1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPB(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPB(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPB(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPD0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - - {EXYNOS4210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE0(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, - - {EXYNOS4210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE1(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4210_GPE2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPE2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4210_GPE3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE3(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4210_GPE4(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE4(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE4(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE4(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE4(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE4(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPE4(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPF3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4210_GPJ1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4210_GPJ1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPK0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPK0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - - {EXYNOS4_GPK1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPK1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPK1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPK1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - - {EXYNOS4_GPK2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPK2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPK2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - - {EXYNOS4_GPK3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPK3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPK3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPK3(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPK3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPK3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPK3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPL0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL0(6), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPL1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL1(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPL2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPL2(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPL2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPL2(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPY0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPY1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPY2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPY3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, - {EXYNOS4_GPY3(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY3(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - - {EXYNOS4_GPY4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY4(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY4(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPY4(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY4(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPY5(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* TP */ - {EXYNOS4_GPY5(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY5(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY5(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY5(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY5(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY5(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY5(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPY6(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY6(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY6(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY6(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY6(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY6(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY6(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPY6(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - - {EXYNOS4_GPZ(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPZ(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPZ(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPZ(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPZ(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, - {EXYNOS4_GPZ(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ - {EXYNOS4_GPZ(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, /* NC */ -}; - -void u1_config_gpio_table(void) -{ - u32 i, gpio; - - for (i = 0; i < ARRAY_SIZE(u1_init_gpios); i++) { - gpio = u1_init_gpios[i].num; - s3c_gpio_cfgpin(gpio, u1_init_gpios[i].cfg); - s3c_gpio_setpull(gpio, u1_init_gpios[i].pud); - - if (u1_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) - gpio_set_value(gpio, u1_init_gpios[i].val); - - s5p_gpio_set_drvstr(gpio, u1_init_gpios[i].drv); - } -} - -static void config_sleep_gpio_table(int array_size, - unsigned int (*gpio_table)[3]) -{ - u32 i, gpio; - - for (i = 0; i < array_size; i++) { - gpio = gpio_table[i][0]; - s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); - s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); - } -} - -void u1_config_sleep_gpio_table(void) -{ - config_sleep_gpio_table(ARRAY_SIZE(u1_sleep_gpio_table), - u1_sleep_gpio_table); -} |